2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
48 #include "mlx5_core.h"
50 #define MLX5E_MAX_NUM_TC 8
52 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
53 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
54 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
56 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
57 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
58 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
60 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
61 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
62 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
63 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
64 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
65 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
67 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
68 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
69 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
70 #define MLX5E_TX_CQ_POLL_BUDGET 128
71 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
72 #define MLX5E_SQ_BF_BUDGET 16
74 #define MLX5E_NUM_MAIN_GROUPS 9
76 #ifdef CONFIG_MLX5_CORE_EN_DCB
77 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
78 #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
81 static const char vport_strings
[][ETH_GSTRING_LEN
] = {
82 /* vport statistics */
95 "rx_multicast_packets",
97 "tx_multicast_packets",
99 "rx_broadcast_packets",
100 "rx_broadcast_bytes",
101 "tx_broadcast_packets",
102 "tx_broadcast_bytes",
122 struct mlx5e_vport_stats
{
128 u64 rx_error_packets
;
130 u64 tx_error_packets
;
132 u64 rx_unicast_packets
;
133 u64 rx_unicast_bytes
;
134 u64 tx_unicast_packets
;
135 u64 tx_unicast_bytes
;
136 u64 rx_multicast_packets
;
137 u64 rx_multicast_bytes
;
138 u64 tx_multicast_packets
;
139 u64 tx_multicast_bytes
;
140 u64 rx_broadcast_packets
;
141 u64 rx_broadcast_bytes
;
142 u64 tx_broadcast_packets
;
143 u64 tx_broadcast_bytes
;
148 u64 tso_inner_packets
;
157 u64 tx_queue_stopped
;
159 u64 tx_queue_dropped
;
162 #define NUM_VPORT_COUNTERS 35
165 static const char pport_strings
[][ETH_GSTRING_LEN
] = {
166 /* IEEE802.3 counters */
177 "in_range_len_errors",
187 /* RFC2863 counters */
199 "out_multicast_pkts",
200 "out_broadcast_pkts",
202 /* RFC2819 counters */
223 "p8192to10239octets",
226 #define NUM_IEEE_802_3_COUNTERS 19
227 #define NUM_RFC_2863_COUNTERS 13
228 #define NUM_RFC_2819_COUNTERS 21
229 #define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \
230 NUM_RFC_2863_COUNTERS + \
231 NUM_RFC_2819_COUNTERS)
233 struct mlx5e_pport_stats
{
234 __be64 IEEE_802_3_counters
[NUM_IEEE_802_3_COUNTERS
];
235 __be64 RFC_2863_counters
[NUM_RFC_2863_COUNTERS
];
236 __be64 RFC_2819_counters
[NUM_RFC_2819_COUNTERS
];
239 static const char rq_stats_strings
[][ETH_GSTRING_LEN
] = {
249 struct mlx5e_rq_stats
{
257 #define NUM_RQ_STATS 7
260 static const char sq_stats_strings
[][ETH_GSTRING_LEN
] = {
267 "csum_offload_inner",
275 struct mlx5e_sq_stats
{
276 /* commonly accessed in data path */
281 u64 tso_inner_packets
;
283 u64 csum_offload_inner
;
285 /* less likely accessed in data path */
286 u64 csum_offload_none
;
290 #define NUM_SQ_STATS 12
294 struct mlx5e_vport_stats vport
;
295 struct mlx5e_pport_stats pport
;
298 struct mlx5e_params
{
303 u16 rx_cq_moderation_usec
;
304 u16 rx_cq_moderation_pkts
;
305 u16 tx_cq_moderation_usec
;
306 u16 tx_cq_moderation_pkts
;
312 u8 toeplitz_hash_key
[40];
313 u32 indirection_rqt
[MLX5E_INDIR_RQT_SIZE
];
314 #ifdef CONFIG_MLX5_CORE_EN_DCB
319 struct mlx5e_tstamp
{
321 struct cyclecounter cycles
;
322 struct timecounter clock
;
323 struct hwtstamp_config hwtstamp_config
;
325 unsigned long overflow_period
;
326 struct delayed_work overflow_work
;
327 struct mlx5_core_dev
*mdev
;
328 struct ptp_clock
*ptp
;
329 struct ptp_clock_info ptp_info
;
333 MLX5E_RQ_STATE_POST_WQES_ENABLE
,
337 /* data path - accessed per cqe */
340 /* data path - accessed per napi poll */
341 struct napi_struct
*napi
;
342 struct mlx5_core_cq mcq
;
343 struct mlx5e_channel
*channel
;
344 struct mlx5e_priv
*priv
;
347 struct mlx5_wq_ctrl wq_ctrl
;
348 } ____cacheline_aligned_in_smp
;
352 struct mlx5_wq_ll wq
;
354 struct sk_buff
**skb
;
357 struct net_device
*netdev
;
358 struct mlx5e_tstamp
*tstamp
;
359 struct mlx5e_rq_stats stats
;
366 struct mlx5_wq_ctrl wq_ctrl
;
368 struct mlx5e_channel
*channel
;
369 struct mlx5e_priv
*priv
;
370 } ____cacheline_aligned_in_smp
;
372 struct mlx5e_tx_wqe_info
{
378 enum mlx5e_dma_map_type
{
379 MLX5E_DMA_MAP_SINGLE
,
383 struct mlx5e_sq_dma
{
386 enum mlx5e_dma_map_type type
;
390 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE
,
391 MLX5E_SQ_STATE_BF_ENABLE
,
397 /* dirtied @completion */
402 u16 pc ____cacheline_aligned_in_smp
;
407 struct mlx5e_sq_stats stats
;
411 /* pointers to per packet info: write@xmit, read@completion */
412 struct sk_buff
**skb
;
413 struct mlx5e_sq_dma
*dma_fifo
;
414 struct mlx5e_tx_wqe_info
*wqe_info
;
417 struct mlx5_wq_cyc wq
;
419 void __iomem
*uar_map
;
420 struct netdev_queue
*txq
;
426 struct mlx5e_tstamp
*tstamp
;
431 struct mlx5_wq_ctrl wq_ctrl
;
433 struct mlx5e_channel
*channel
;
435 } ____cacheline_aligned_in_smp
;
437 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq
*sq
, u16 n
)
439 return (((sq
->wq
.sz_m1
& (sq
->cc
- sq
->pc
)) >= n
) ||
444 MLX5E_CHANNEL_NAPI_SCHED
= 1,
447 struct mlx5e_channel
{
450 struct mlx5e_sq sq
[MLX5E_MAX_NUM_TC
];
451 struct napi_struct napi
;
453 struct net_device
*netdev
;
459 struct mlx5e_priv
*priv
;
464 enum mlx5e_traffic_types
{
469 MLX5E_TT_IPV4_IPSEC_AH
,
470 MLX5E_TT_IPV6_IPSEC_AH
,
471 MLX5E_TT_IPV4_IPSEC_ESP
,
472 MLX5E_TT_IPV6_IPSEC_ESP
,
479 #define IS_HASHING_TT(tt) (tt != MLX5E_TT_ANY)
482 MLX5E_INDIRECTION_RQT
,
487 struct mlx5e_eth_addr_info
{
488 u8 addr
[ETH_ALEN
+ 2];
490 struct mlx5_flow_rule
*ft_rule
[MLX5E_NUM_TT
];
493 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
495 struct mlx5e_eth_addr_db
{
496 struct hlist_head netdev_uc
[MLX5E_ETH_ADDR_HASH_SIZE
];
497 struct hlist_head netdev_mc
[MLX5E_ETH_ADDR_HASH_SIZE
];
498 struct mlx5e_eth_addr_info broadcast
;
499 struct mlx5e_eth_addr_info allmulti
;
500 struct mlx5e_eth_addr_info promisc
;
501 bool broadcast_enabled
;
502 bool allmulti_enabled
;
503 bool promisc_enabled
;
507 MLX5E_STATE_ASYNC_EVENTS_ENABLE
,
509 MLX5E_STATE_DESTROYING
,
512 struct mlx5e_vlan_db
{
513 unsigned long active_vlans
[BITS_TO_LONGS(VLAN_N_VID
)];
514 struct mlx5_flow_rule
*active_vlans_rule
[VLAN_N_VID
];
515 struct mlx5_flow_rule
*untagged_rule
;
516 struct mlx5_flow_rule
*any_vlan_rule
;
517 bool filter_disabled
;
520 struct mlx5e_vxlan_db
{
521 spinlock_t lock
; /* protect vxlan table */
522 struct radix_tree_root tree
;
525 struct mlx5e_flow_table
{
527 struct mlx5_flow_table
*t
;
528 struct mlx5_flow_group
**g
;
531 struct mlx5e_tc_flow_table
{
532 struct mlx5_flow_table
*t
;
534 struct rhashtable_params ht_params
;
535 struct rhashtable ht
;
538 struct mlx5e_flow_tables
{
539 struct mlx5_flow_namespace
*ns
;
540 struct mlx5e_tc_flow_table tc
;
541 struct mlx5e_flow_table vlan
;
542 struct mlx5e_flow_table main
;
546 /* priv data path fields - start */
547 struct mlx5e_sq
**txq_to_sq_map
;
548 int channeltc_to_txq_map
[MLX5E_MAX_NUM_CHANNELS
][MLX5E_MAX_NUM_TC
];
549 /* priv data path fields - end */
552 struct mutex state_lock
; /* Protects Interface state */
553 struct mlx5_uar cq_uar
;
556 struct mlx5_core_mkey mkey
;
557 struct mlx5e_rq drop_rq
;
559 struct mlx5e_channel
**channel
;
560 u32 tisn
[MLX5E_MAX_NUM_TC
];
561 u32 rqtn
[MLX5E_NUM_RQT
];
562 u32 tirn
[MLX5E_NUM_TT
];
564 struct mlx5e_flow_tables fts
;
565 struct mlx5e_eth_addr_db eth_addr
;
566 struct mlx5e_vlan_db vlan
;
567 struct mlx5e_vxlan_db vxlan
;
569 struct mlx5e_params params
;
570 struct workqueue_struct
*wq
;
571 struct work_struct update_carrier_work
;
572 struct work_struct set_rx_mode_work
;
573 struct delayed_work update_stats_work
;
575 struct mlx5_core_dev
*mdev
;
576 struct net_device
*netdev
;
577 struct mlx5e_stats stats
;
578 struct mlx5e_tstamp tstamp
;
581 #define MLX5E_NET_IP_ALIGN 2
583 struct mlx5e_tx_wqe
{
584 struct mlx5_wqe_ctrl_seg ctrl
;
585 struct mlx5_wqe_eth_seg eth
;
588 struct mlx5e_rx_wqe
{
589 struct mlx5_wqe_srq_next_seg next
;
590 struct mlx5_wqe_data_seg data
;
593 enum mlx5e_link_mode
{
594 MLX5E_1000BASE_CX_SGMII
= 0,
595 MLX5E_1000BASE_KX
= 1,
596 MLX5E_10GBASE_CX4
= 2,
597 MLX5E_10GBASE_KX4
= 3,
598 MLX5E_10GBASE_KR
= 4,
599 MLX5E_20GBASE_KR2
= 5,
600 MLX5E_40GBASE_CR4
= 6,
601 MLX5E_40GBASE_KR4
= 7,
602 MLX5E_56GBASE_R4
= 8,
603 MLX5E_10GBASE_CR
= 12,
604 MLX5E_10GBASE_SR
= 13,
605 MLX5E_10GBASE_ER
= 14,
606 MLX5E_40GBASE_SR4
= 15,
607 MLX5E_40GBASE_LR4
= 16,
608 MLX5E_100GBASE_CR4
= 20,
609 MLX5E_100GBASE_SR4
= 21,
610 MLX5E_100GBASE_KR4
= 22,
611 MLX5E_100GBASE_LR4
= 23,
612 MLX5E_100BASE_TX
= 24,
613 MLX5E_1000BASE_T
= 25,
614 MLX5E_10GBASE_T
= 26,
615 MLX5E_25GBASE_CR
= 27,
616 MLX5E_25GBASE_KR
= 28,
617 MLX5E_25GBASE_SR
= 29,
618 MLX5E_50GBASE_CR2
= 30,
619 MLX5E_50GBASE_KR2
= 31,
620 MLX5E_LINK_MODES_NUMBER
,
623 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
625 void mlx5e_send_nop(struct mlx5e_sq
*sq
, bool notify_hw
);
626 u16
mlx5e_select_queue(struct net_device
*dev
, struct sk_buff
*skb
,
627 void *accel_priv
, select_queue_fallback_t fallback
);
628 netdev_tx_t
mlx5e_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
630 void mlx5e_completion_event(struct mlx5_core_cq
*mcq
);
631 void mlx5e_cq_error_event(struct mlx5_core_cq
*mcq
, enum mlx5_event event
);
632 int mlx5e_napi_poll(struct napi_struct
*napi
, int budget
);
633 bool mlx5e_poll_tx_cq(struct mlx5e_cq
*cq
, int napi_budget
);
634 int mlx5e_poll_rx_cq(struct mlx5e_cq
*cq
, int budget
);
635 bool mlx5e_post_rx_wqes(struct mlx5e_rq
*rq
);
636 struct mlx5_cqe64
*mlx5e_get_cqe(struct mlx5e_cq
*cq
);
638 void mlx5e_update_stats(struct mlx5e_priv
*priv
);
640 int mlx5e_create_flow_tables(struct mlx5e_priv
*priv
);
641 void mlx5e_destroy_flow_tables(struct mlx5e_priv
*priv
);
642 void mlx5e_init_eth_addr(struct mlx5e_priv
*priv
);
643 void mlx5e_set_rx_mode_work(struct work_struct
*work
);
645 void mlx5e_fill_hwstamp(struct mlx5e_tstamp
*clock
, u64 timestamp
,
646 struct skb_shared_hwtstamps
*hwts
);
647 void mlx5e_timestamp_init(struct mlx5e_priv
*priv
);
648 void mlx5e_timestamp_cleanup(struct mlx5e_priv
*priv
);
649 int mlx5e_hwstamp_set(struct net_device
*dev
, struct ifreq
*ifr
);
650 int mlx5e_hwstamp_get(struct net_device
*dev
, struct ifreq
*ifr
);
652 int mlx5e_vlan_rx_add_vid(struct net_device
*dev
, __always_unused __be16 proto
,
654 int mlx5e_vlan_rx_kill_vid(struct net_device
*dev
, __always_unused __be16 proto
,
656 void mlx5e_enable_vlan_filter(struct mlx5e_priv
*priv
);
657 void mlx5e_disable_vlan_filter(struct mlx5e_priv
*priv
);
659 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, enum mlx5e_rqt_ix rqt_ix
);
660 void mlx5e_build_tir_ctx_hash(void *tirc
, struct mlx5e_priv
*priv
);
662 int mlx5e_open_locked(struct net_device
*netdev
);
663 int mlx5e_close_locked(struct net_device
*netdev
);
664 void mlx5e_build_default_indir_rqt(u32
*indirection_rqt
, int len
,
667 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq
*sq
,
668 struct mlx5e_tx_wqe
*wqe
, int bf_sz
)
670 u16 ofst
= MLX5_BF_OFFSET
+ sq
->bf_offset
;
672 /* ensure wqe is visible to device before updating doorbell record */
675 *sq
->wq
.db
= cpu_to_be32(sq
->pc
);
677 /* ensure doorbell record is visible to device before ringing the
682 __iowrite64_copy(sq
->uar_map
+ ofst
, &wqe
->ctrl
, bf_sz
);
684 mlx5_write64((__be32
*)&wqe
->ctrl
, sq
->uar_map
+ ofst
, NULL
);
685 /* flush the write-combining mapped buffer */
688 sq
->bf_offset
^= sq
->bf_buf_size
;
691 static inline void mlx5e_cq_arm(struct mlx5e_cq
*cq
)
693 struct mlx5_core_cq
*mcq
;
696 mlx5_cq_arm(mcq
, MLX5_CQ_DB_REQ_NOT
, mcq
->uar
->map
, NULL
, cq
->wq
.cc
);
699 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev
*mdev
)
701 return min_t(int, mdev
->priv
.eq_table
.num_comp_vectors
,
702 MLX5E_MAX_NUM_CHANNELS
);
705 extern const struct ethtool_ops mlx5e_ethtool_ops
;
706 #ifdef CONFIG_MLX5_CORE_EN_DCB
707 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops
;
708 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv
*priv
, struct ieee_ets
*ets
);
711 u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev
*mdev
);
713 #endif /* __MLX5_EN_H__ */