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net/mlx5e: Add TXQ set max rate support
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en.h
1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
47 #include "wq.h"
48 #include "mlx5_core.h"
49 #include "en_stats.h"
50
51 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
52
53 #define MLX5E_MAX_NUM_TC 8
54
55 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
56 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
57 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
58
59 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
60 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
61 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
62
63 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
64 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4
65 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
66
67 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
68 #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */
69 #define MLX5_MPWRQ_LOG_WQE_SZ 17
70 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
71 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
72 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
73 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
74 MLX5_MPWRQ_WQE_PAGE_ORDER)
75 #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \
76 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW))
77 #define MLX5_UMR_ALIGN (2048)
78 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
79
80 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
81 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
82 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
83 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
84 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
85 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
86 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
87
88 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
89 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
90 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
91 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
92 #define MLX5E_TX_CQ_POLL_BUDGET 128
93 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
94 #define MLX5E_SQ_BF_BUDGET 16
95
96 #define MLX5E_NUM_MAIN_GROUPS 9
97
98 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
99 {
100 switch (wq_type) {
101 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
102 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
103 wq_size / 2);
104 default:
105 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
106 wq_size / 2);
107 }
108 }
109
110 static inline int mlx5_min_log_rq_size(int wq_type)
111 {
112 switch (wq_type) {
113 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
114 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
115 default:
116 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
117 }
118 }
119
120 static inline int mlx5_max_log_rq_size(int wq_type)
121 {
122 switch (wq_type) {
123 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
124 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
125 default:
126 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
127 }
128 }
129
130 struct mlx5e_tx_wqe {
131 struct mlx5_wqe_ctrl_seg ctrl;
132 struct mlx5_wqe_eth_seg eth;
133 };
134
135 struct mlx5e_rx_wqe {
136 struct mlx5_wqe_srq_next_seg next;
137 struct mlx5_wqe_data_seg data;
138 };
139
140 struct mlx5e_umr_wqe {
141 struct mlx5_wqe_ctrl_seg ctrl;
142 struct mlx5_wqe_umr_ctrl_seg uctrl;
143 struct mlx5_mkey_seg mkc;
144 struct mlx5_wqe_data_seg data;
145 };
146
147 #ifdef CONFIG_MLX5_CORE_EN_DCB
148 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
149 #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
150 #endif
151
152 struct mlx5e_params {
153 u8 log_sq_size;
154 u8 rq_wq_type;
155 u8 mpwqe_log_stride_sz;
156 u8 mpwqe_log_num_strides;
157 u8 log_rq_size;
158 u16 num_channels;
159 u8 num_tc;
160 bool rx_cqe_compress_admin;
161 bool rx_cqe_compress;
162 u16 rx_cq_moderation_usec;
163 u16 rx_cq_moderation_pkts;
164 u16 tx_cq_moderation_usec;
165 u16 tx_cq_moderation_pkts;
166 u16 min_rx_wqes;
167 bool lro_en;
168 u32 lro_wqe_sz;
169 u16 tx_max_inline;
170 u8 rss_hfunc;
171 u8 toeplitz_hash_key[40];
172 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
173 bool vlan_strip_disable;
174 #ifdef CONFIG_MLX5_CORE_EN_DCB
175 struct ieee_ets ets;
176 #endif
177 };
178
179 struct mlx5e_tstamp {
180 rwlock_t lock;
181 struct cyclecounter cycles;
182 struct timecounter clock;
183 struct hwtstamp_config hwtstamp_config;
184 u32 nominal_c_mult;
185 unsigned long overflow_period;
186 struct delayed_work overflow_work;
187 struct mlx5_core_dev *mdev;
188 struct ptp_clock *ptp;
189 struct ptp_clock_info ptp_info;
190 };
191
192 enum {
193 MLX5E_RQ_STATE_POST_WQES_ENABLE,
194 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
195 };
196
197 struct mlx5e_cq {
198 /* data path - accessed per cqe */
199 struct mlx5_cqwq wq;
200
201 /* data path - accessed per napi poll */
202 struct napi_struct *napi;
203 struct mlx5_core_cq mcq;
204 struct mlx5e_channel *channel;
205 struct mlx5e_priv *priv;
206
207 /* cqe decompression */
208 struct mlx5_cqe64 title;
209 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
210 u8 mini_arr_idx;
211 u16 decmprs_left;
212 u16 decmprs_wqe_counter;
213
214 /* control */
215 struct mlx5_wq_ctrl wq_ctrl;
216 } ____cacheline_aligned_in_smp;
217
218 struct mlx5e_rq;
219 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
220 struct mlx5_cqe64 *cqe);
221 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
222 u16 ix);
223
224 struct mlx5e_dma_info {
225 struct page *page;
226 dma_addr_t addr;
227 };
228
229 struct mlx5e_rq {
230 /* data path */
231 struct mlx5_wq_ll wq;
232 u32 wqe_sz;
233 struct sk_buff **skb;
234 struct mlx5e_mpw_info *wqe_info;
235 __be32 mkey_be;
236 __be32 umr_mkey_be;
237
238 struct device *pdev;
239 struct net_device *netdev;
240 struct mlx5e_tstamp *tstamp;
241 struct mlx5e_rq_stats stats;
242 struct mlx5e_cq cq;
243 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
244 mlx5e_fp_alloc_wqe alloc_wqe;
245
246 unsigned long state;
247 int ix;
248
249 /* control */
250 struct mlx5_wq_ctrl wq_ctrl;
251 u8 wq_type;
252 u32 mpwqe_stride_sz;
253 u32 mpwqe_num_strides;
254 u32 rqn;
255 struct mlx5e_channel *channel;
256 struct mlx5e_priv *priv;
257 } ____cacheline_aligned_in_smp;
258
259 struct mlx5e_umr_dma_info {
260 __be64 *mtt;
261 __be64 *mtt_no_align;
262 dma_addr_t mtt_addr;
263 struct mlx5e_dma_info *dma_info;
264 };
265
266 struct mlx5e_mpw_info {
267 union {
268 struct mlx5e_dma_info dma_info;
269 struct mlx5e_umr_dma_info umr;
270 };
271 u16 consumed_strides;
272 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
273
274 void (*dma_pre_sync)(struct device *pdev,
275 struct mlx5e_mpw_info *wi,
276 u32 wqe_offset, u32 len);
277 void (*add_skb_frag)(struct mlx5e_rq *rq,
278 struct sk_buff *skb,
279 struct mlx5e_mpw_info *wi,
280 u32 page_idx, u32 frag_offset, u32 len);
281 void (*copy_skb_header)(struct device *pdev,
282 struct sk_buff *skb,
283 struct mlx5e_mpw_info *wi,
284 u32 page_idx, u32 offset,
285 u32 headlen);
286 void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
287 };
288
289 struct mlx5e_tx_wqe_info {
290 u32 num_bytes;
291 u8 num_wqebbs;
292 u8 num_dma;
293 };
294
295 enum mlx5e_dma_map_type {
296 MLX5E_DMA_MAP_SINGLE,
297 MLX5E_DMA_MAP_PAGE
298 };
299
300 struct mlx5e_sq_dma {
301 dma_addr_t addr;
302 u32 size;
303 enum mlx5e_dma_map_type type;
304 };
305
306 enum {
307 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
308 MLX5E_SQ_STATE_BF_ENABLE,
309 };
310
311 struct mlx5e_ico_wqe_info {
312 u8 opcode;
313 u8 num_wqebbs;
314 };
315
316 struct mlx5e_sq {
317 /* data path */
318
319 /* dirtied @completion */
320 u16 cc;
321 u32 dma_fifo_cc;
322
323 /* dirtied @xmit */
324 u16 pc ____cacheline_aligned_in_smp;
325 u32 dma_fifo_pc;
326 u16 bf_offset;
327 u16 prev_cc;
328 u8 bf_budget;
329 struct mlx5e_sq_stats stats;
330
331 struct mlx5e_cq cq;
332
333 /* pointers to per packet info: write@xmit, read@completion */
334 struct sk_buff **skb;
335 struct mlx5e_sq_dma *dma_fifo;
336 struct mlx5e_tx_wqe_info *wqe_info;
337
338 /* read only */
339 struct mlx5_wq_cyc wq;
340 u32 dma_fifo_mask;
341 void __iomem *uar_map;
342 struct netdev_queue *txq;
343 u32 sqn;
344 u16 bf_buf_size;
345 u16 max_inline;
346 u16 edge;
347 struct device *pdev;
348 struct mlx5e_tstamp *tstamp;
349 __be32 mkey_be;
350 unsigned long state;
351
352 /* control path */
353 struct mlx5_wq_ctrl wq_ctrl;
354 struct mlx5_uar uar;
355 struct mlx5e_channel *channel;
356 int tc;
357 struct mlx5e_ico_wqe_info *ico_wqe_info;
358 u32 rate_limit;
359 } ____cacheline_aligned_in_smp;
360
361 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
362 {
363 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
364 (sq->cc == sq->pc));
365 }
366
367 enum channel_flags {
368 MLX5E_CHANNEL_NAPI_SCHED = 1,
369 };
370
371 struct mlx5e_channel {
372 /* data path */
373 struct mlx5e_rq rq;
374 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
375 struct mlx5e_sq icosq; /* internal control operations */
376 struct napi_struct napi;
377 struct device *pdev;
378 struct net_device *netdev;
379 __be32 mkey_be;
380 u8 num_tc;
381 unsigned long flags;
382
383 /* control */
384 struct mlx5e_priv *priv;
385 int ix;
386 int cpu;
387 };
388
389 enum mlx5e_traffic_types {
390 MLX5E_TT_IPV4_TCP,
391 MLX5E_TT_IPV6_TCP,
392 MLX5E_TT_IPV4_UDP,
393 MLX5E_TT_IPV6_UDP,
394 MLX5E_TT_IPV4_IPSEC_AH,
395 MLX5E_TT_IPV6_IPSEC_AH,
396 MLX5E_TT_IPV4_IPSEC_ESP,
397 MLX5E_TT_IPV6_IPSEC_ESP,
398 MLX5E_TT_IPV4,
399 MLX5E_TT_IPV6,
400 MLX5E_TT_ANY,
401 MLX5E_NUM_TT,
402 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
403 };
404
405 enum {
406 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
407 MLX5E_STATE_OPENED,
408 MLX5E_STATE_DESTROYING,
409 };
410
411 struct mlx5e_vxlan_db {
412 spinlock_t lock; /* protect vxlan table */
413 struct radix_tree_root tree;
414 };
415
416 struct mlx5e_l2_rule {
417 u8 addr[ETH_ALEN + 2];
418 struct mlx5_flow_rule *rule;
419 };
420
421 struct mlx5e_flow_table {
422 int num_groups;
423 struct mlx5_flow_table *t;
424 struct mlx5_flow_group **g;
425 };
426
427 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
428
429 struct mlx5e_tc_table {
430 struct mlx5_flow_table *t;
431
432 struct rhashtable_params ht_params;
433 struct rhashtable ht;
434 };
435
436 struct mlx5e_vlan_table {
437 struct mlx5e_flow_table ft;
438 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
439 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
440 struct mlx5_flow_rule *untagged_rule;
441 struct mlx5_flow_rule *any_vlan_rule;
442 bool filter_disabled;
443 };
444
445 struct mlx5e_l2_table {
446 struct mlx5e_flow_table ft;
447 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
448 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
449 struct mlx5e_l2_rule broadcast;
450 struct mlx5e_l2_rule allmulti;
451 struct mlx5e_l2_rule promisc;
452 bool broadcast_enabled;
453 bool allmulti_enabled;
454 bool promisc_enabled;
455 };
456
457 /* L3/L4 traffic type classifier */
458 struct mlx5e_ttc_table {
459 struct mlx5e_flow_table ft;
460 struct mlx5_flow_rule *rules[MLX5E_NUM_TT];
461 };
462
463 #define ARFS_HASH_SHIFT BITS_PER_BYTE
464 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
465 struct arfs_table {
466 struct mlx5e_flow_table ft;
467 struct mlx5_flow_rule *default_rule;
468 struct hlist_head rules_hash[ARFS_HASH_SIZE];
469 };
470
471 enum arfs_type {
472 ARFS_IPV4_TCP,
473 ARFS_IPV6_TCP,
474 ARFS_IPV4_UDP,
475 ARFS_IPV6_UDP,
476 ARFS_NUM_TYPES,
477 };
478
479 struct mlx5e_arfs_tables {
480 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
481 /* Protect aRFS rules list */
482 spinlock_t arfs_lock;
483 struct list_head rules;
484 int last_filter_id;
485 struct workqueue_struct *wq;
486 };
487
488 /* NIC prio FTS */
489 enum {
490 MLX5E_VLAN_FT_LEVEL = 0,
491 MLX5E_L2_FT_LEVEL,
492 MLX5E_TTC_FT_LEVEL,
493 MLX5E_ARFS_FT_LEVEL
494 };
495
496 struct mlx5e_flow_steering {
497 struct mlx5_flow_namespace *ns;
498 struct mlx5e_tc_table tc;
499 struct mlx5e_vlan_table vlan;
500 struct mlx5e_l2_table l2;
501 struct mlx5e_ttc_table ttc;
502 struct mlx5e_arfs_tables arfs;
503 };
504
505 struct mlx5e_direct_tir {
506 u32 tirn;
507 u32 rqtn;
508 };
509
510 enum {
511 MLX5E_TC_PRIO = 0,
512 MLX5E_NIC_PRIO
513 };
514
515 struct mlx5e_priv {
516 /* priv data path fields - start */
517 struct mlx5e_sq **txq_to_sq_map;
518 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
519 /* priv data path fields - end */
520
521 unsigned long state;
522 struct mutex state_lock; /* Protects Interface state */
523 struct mlx5_uar cq_uar;
524 u32 pdn;
525 u32 tdn;
526 struct mlx5_core_mkey mkey;
527 struct mlx5_core_mkey umr_mkey;
528 struct mlx5e_rq drop_rq;
529
530 struct mlx5e_channel **channel;
531 u32 tisn[MLX5E_MAX_NUM_TC];
532 u32 indir_rqtn;
533 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
534 struct mlx5e_direct_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
535 u32 tx_rates[MLX5E_MAX_NUM_SQS];
536
537 struct mlx5e_flow_steering fs;
538 struct mlx5e_vxlan_db vxlan;
539
540 struct mlx5e_params params;
541 struct workqueue_struct *wq;
542 struct work_struct update_carrier_work;
543 struct work_struct set_rx_mode_work;
544 struct delayed_work update_stats_work;
545
546 struct mlx5_core_dev *mdev;
547 struct net_device *netdev;
548 struct mlx5e_stats stats;
549 struct mlx5e_tstamp tstamp;
550 u16 q_counter;
551 };
552
553 enum mlx5e_link_mode {
554 MLX5E_1000BASE_CX_SGMII = 0,
555 MLX5E_1000BASE_KX = 1,
556 MLX5E_10GBASE_CX4 = 2,
557 MLX5E_10GBASE_KX4 = 3,
558 MLX5E_10GBASE_KR = 4,
559 MLX5E_20GBASE_KR2 = 5,
560 MLX5E_40GBASE_CR4 = 6,
561 MLX5E_40GBASE_KR4 = 7,
562 MLX5E_56GBASE_R4 = 8,
563 MLX5E_10GBASE_CR = 12,
564 MLX5E_10GBASE_SR = 13,
565 MLX5E_10GBASE_ER = 14,
566 MLX5E_40GBASE_SR4 = 15,
567 MLX5E_40GBASE_LR4 = 16,
568 MLX5E_100GBASE_CR4 = 20,
569 MLX5E_100GBASE_SR4 = 21,
570 MLX5E_100GBASE_KR4 = 22,
571 MLX5E_100GBASE_LR4 = 23,
572 MLX5E_100BASE_TX = 24,
573 MLX5E_1000BASE_T = 25,
574 MLX5E_10GBASE_T = 26,
575 MLX5E_25GBASE_CR = 27,
576 MLX5E_25GBASE_KR = 28,
577 MLX5E_25GBASE_SR = 29,
578 MLX5E_50GBASE_CR2 = 30,
579 MLX5E_50GBASE_KR2 = 31,
580 MLX5E_LINK_MODES_NUMBER,
581 };
582
583 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
584
585 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
586 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
587 void *accel_priv, select_queue_fallback_t fallback);
588 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
589
590 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
591 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
592 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
593 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
594 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
595
596 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
597 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
598 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
599 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
600 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
601 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq);
602 void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq,
603 struct mlx5_cqe64 *cqe,
604 u16 byte_cnt,
605 struct mlx5e_mpw_info *wi,
606 struct sk_buff *skb);
607 void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
608 struct mlx5_cqe64 *cqe,
609 u16 byte_cnt,
610 struct mlx5e_mpw_info *wi,
611 struct sk_buff *skb);
612 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
613 struct mlx5e_mpw_info *wi);
614 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
615 struct mlx5e_mpw_info *wi);
616 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
617
618 void mlx5e_update_stats(struct mlx5e_priv *priv);
619
620 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
621 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
622 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
623 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
624 void mlx5e_set_rx_mode_work(struct work_struct *work);
625
626 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
627 struct skb_shared_hwtstamps *hwts);
628 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
629 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
630 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
631 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
632 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val);
633
634 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
635 u16 vid);
636 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
637 u16 vid);
638 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
639 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
640
641 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
642
643 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
644 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
645
646 int mlx5e_open_locked(struct net_device *netdev);
647 int mlx5e_close_locked(struct net_device *netdev);
648 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
649 u32 *indirection_rqt, int len,
650 int num_channels);
651 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
652
653 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
654 struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
655 {
656 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
657
658 /* ensure wqe is visible to device before updating doorbell record */
659 dma_wmb();
660
661 *sq->wq.db = cpu_to_be32(sq->pc);
662
663 /* ensure doorbell record is visible to device before ringing the
664 * doorbell
665 */
666 wmb();
667 if (bf_sz)
668 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
669 else
670 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
671 /* flush the write-combining mapped buffer */
672 wmb();
673
674 sq->bf_offset ^= sq->bf_buf_size;
675 }
676
677 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
678 {
679 struct mlx5_core_cq *mcq;
680
681 mcq = &cq->mcq;
682 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
683 }
684
685 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
686 {
687 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
688 MLX5E_MAX_NUM_CHANNELS);
689 }
690
691 static inline int mlx5e_get_mtt_octw(int npages)
692 {
693 return ALIGN(npages, 8) / 2;
694 }
695
696 extern const struct ethtool_ops mlx5e_ethtool_ops;
697 #ifdef CONFIG_MLX5_CORE_EN_DCB
698 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
699 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
700 #endif
701
702 #ifndef CONFIG_RFS_ACCEL
703 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
704 {
705 return 0;
706 }
707
708 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
709
710 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
711 {
712 return -ENOTSUPP;
713 }
714
715 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
716 {
717 return -ENOTSUPP;
718 }
719 #else
720 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
721 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
722 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
723 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
724 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
725 u16 rxq_index, u32 flow_id);
726 #endif
727
728 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
729
730 #endif /* __MLX5_EN_H__ */
Linux kernel - Deliverables
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