2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
48 #include "mlx5_core.h"
51 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
53 #define MLX5E_MAX_NUM_TC 8
55 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
56 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
57 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
59 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
60 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
61 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
63 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
64 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4
65 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
67 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
68 #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */
69 #define MLX5_MPWRQ_LOG_WQE_SZ 17
70 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
71 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
72 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
73 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
74 MLX5_MPWRQ_WQE_PAGE_ORDER)
75 #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \
76 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW))
77 #define MLX5_UMR_ALIGN (2048)
78 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
80 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
81 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
82 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
83 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
84 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
85 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
86 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
88 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
89 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
90 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
91 #define MLX5E_TX_CQ_POLL_BUDGET 128
92 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
93 #define MLX5E_SQ_BF_BUDGET 16
95 #define MLX5E_NUM_MAIN_GROUPS 9
97 static inline u16
mlx5_min_rx_wqes(int wq_type
, u32 wq_size
)
100 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
101 return min_t(u16
, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW
,
104 return min_t(u16
, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES
,
109 static inline int mlx5_min_log_rq_size(int wq_type
)
112 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
113 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW
;
115 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE
;
119 static inline int mlx5_max_log_rq_size(int wq_type
)
122 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
123 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW
;
125 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE
;
129 struct mlx5e_tx_wqe
{
130 struct mlx5_wqe_ctrl_seg ctrl
;
131 struct mlx5_wqe_eth_seg eth
;
134 struct mlx5e_rx_wqe
{
135 struct mlx5_wqe_srq_next_seg next
;
136 struct mlx5_wqe_data_seg data
;
139 struct mlx5e_umr_wqe
{
140 struct mlx5_wqe_ctrl_seg ctrl
;
141 struct mlx5_wqe_umr_ctrl_seg uctrl
;
142 struct mlx5_mkey_seg mkc
;
143 struct mlx5_wqe_data_seg data
;
146 #ifdef CONFIG_MLX5_CORE_EN_DCB
147 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
148 #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
151 struct mlx5e_params
{
154 u8 mpwqe_log_stride_sz
;
155 u8 mpwqe_log_num_strides
;
159 bool rx_cqe_compress_admin
;
160 bool rx_cqe_compress
;
161 u16 rx_cq_moderation_usec
;
162 u16 rx_cq_moderation_pkts
;
163 u16 tx_cq_moderation_usec
;
164 u16 tx_cq_moderation_pkts
;
170 u8 toeplitz_hash_key
[40];
171 u32 indirection_rqt
[MLX5E_INDIR_RQT_SIZE
];
172 bool vlan_strip_disable
;
173 #ifdef CONFIG_MLX5_CORE_EN_DCB
178 struct mlx5e_tstamp
{
180 struct cyclecounter cycles
;
181 struct timecounter clock
;
182 struct hwtstamp_config hwtstamp_config
;
184 unsigned long overflow_period
;
185 struct delayed_work overflow_work
;
186 struct mlx5_core_dev
*mdev
;
187 struct ptp_clock
*ptp
;
188 struct ptp_clock_info ptp_info
;
192 MLX5E_RQ_STATE_POST_WQES_ENABLE
,
193 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS
,
197 /* data path - accessed per cqe */
200 /* data path - accessed per napi poll */
201 struct napi_struct
*napi
;
202 struct mlx5_core_cq mcq
;
203 struct mlx5e_channel
*channel
;
204 struct mlx5e_priv
*priv
;
206 /* cqe decompression */
207 struct mlx5_cqe64 title
;
208 struct mlx5_mini_cqe8 mini_arr
[MLX5_MINI_CQE_ARRAY_SIZE
];
211 u16 decmprs_wqe_counter
;
214 struct mlx5_wq_ctrl wq_ctrl
;
215 } ____cacheline_aligned_in_smp
;
218 typedef void (*mlx5e_fp_handle_rx_cqe
)(struct mlx5e_rq
*rq
,
219 struct mlx5_cqe64
*cqe
);
220 typedef int (*mlx5e_fp_alloc_wqe
)(struct mlx5e_rq
*rq
, struct mlx5e_rx_wqe
*wqe
,
223 struct mlx5e_dma_info
{
230 struct mlx5_wq_ll wq
;
232 struct sk_buff
**skb
;
233 struct mlx5e_mpw_info
*wqe_info
;
238 struct net_device
*netdev
;
239 struct mlx5e_tstamp
*tstamp
;
240 struct mlx5e_rq_stats stats
;
242 mlx5e_fp_handle_rx_cqe handle_rx_cqe
;
243 mlx5e_fp_alloc_wqe alloc_wqe
;
249 struct mlx5_wq_ctrl wq_ctrl
;
252 u32 mpwqe_num_strides
;
254 struct mlx5e_channel
*channel
;
255 struct mlx5e_priv
*priv
;
256 } ____cacheline_aligned_in_smp
;
258 struct mlx5e_umr_dma_info
{
260 __be64
*mtt_no_align
;
262 struct mlx5e_dma_info
*dma_info
;
265 struct mlx5e_mpw_info
{
267 struct mlx5e_dma_info dma_info
;
268 struct mlx5e_umr_dma_info umr
;
270 u16 consumed_strides
;
271 u16 skbs_frags
[MLX5_MPWRQ_PAGES_PER_WQE
];
273 void (*dma_pre_sync
)(struct device
*pdev
,
274 struct mlx5e_mpw_info
*wi
,
275 u32 wqe_offset
, u32 len
);
276 void (*add_skb_frag
)(struct mlx5e_rq
*rq
,
278 struct mlx5e_mpw_info
*wi
,
279 u32 page_idx
, u32 frag_offset
, u32 len
);
280 void (*copy_skb_header
)(struct device
*pdev
,
282 struct mlx5e_mpw_info
*wi
,
283 u32 page_idx
, u32 offset
,
285 void (*free_wqe
)(struct mlx5e_rq
*rq
, struct mlx5e_mpw_info
*wi
);
288 struct mlx5e_tx_wqe_info
{
294 enum mlx5e_dma_map_type
{
295 MLX5E_DMA_MAP_SINGLE
,
299 struct mlx5e_sq_dma
{
302 enum mlx5e_dma_map_type type
;
306 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE
,
307 MLX5E_SQ_STATE_BF_ENABLE
,
310 struct mlx5e_ico_wqe_info
{
318 /* dirtied @completion */
323 u16 pc ____cacheline_aligned_in_smp
;
328 struct mlx5e_sq_stats stats
;
332 /* pointers to per packet info: write@xmit, read@completion */
333 struct sk_buff
**skb
;
334 struct mlx5e_sq_dma
*dma_fifo
;
335 struct mlx5e_tx_wqe_info
*wqe_info
;
338 struct mlx5_wq_cyc wq
;
340 void __iomem
*uar_map
;
341 struct netdev_queue
*txq
;
347 struct mlx5e_tstamp
*tstamp
;
352 struct mlx5_wq_ctrl wq_ctrl
;
354 struct mlx5e_channel
*channel
;
356 struct mlx5e_ico_wqe_info
*ico_wqe_info
;
357 } ____cacheline_aligned_in_smp
;
359 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq
*sq
, u16 n
)
361 return (((sq
->wq
.sz_m1
& (sq
->cc
- sq
->pc
)) >= n
) ||
366 MLX5E_CHANNEL_NAPI_SCHED
= 1,
369 struct mlx5e_channel
{
372 struct mlx5e_sq sq
[MLX5E_MAX_NUM_TC
];
373 struct mlx5e_sq icosq
; /* internal control operations */
374 struct napi_struct napi
;
376 struct net_device
*netdev
;
382 struct mlx5e_priv
*priv
;
387 enum mlx5e_traffic_types
{
392 MLX5E_TT_IPV4_IPSEC_AH
,
393 MLX5E_TT_IPV6_IPSEC_AH
,
394 MLX5E_TT_IPV4_IPSEC_ESP
,
395 MLX5E_TT_IPV6_IPSEC_ESP
,
400 MLX5E_NUM_INDIR_TIRS
= MLX5E_TT_ANY
,
404 MLX5E_STATE_ASYNC_EVENTS_ENABLE
,
406 MLX5E_STATE_DESTROYING
,
409 struct mlx5e_vxlan_db
{
410 spinlock_t lock
; /* protect vxlan table */
411 struct radix_tree_root tree
;
414 struct mlx5e_l2_rule
{
415 u8 addr
[ETH_ALEN
+ 2];
416 struct mlx5_flow_rule
*rule
;
419 struct mlx5e_flow_table
{
421 struct mlx5_flow_table
*t
;
422 struct mlx5_flow_group
**g
;
425 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
427 struct mlx5e_tc_table
{
428 struct mlx5_flow_table
*t
;
430 struct rhashtable_params ht_params
;
431 struct rhashtable ht
;
434 struct mlx5e_vlan_table
{
435 struct mlx5e_flow_table ft
;
436 unsigned long active_vlans
[BITS_TO_LONGS(VLAN_N_VID
)];
437 struct mlx5_flow_rule
*active_vlans_rule
[VLAN_N_VID
];
438 struct mlx5_flow_rule
*untagged_rule
;
439 struct mlx5_flow_rule
*any_vlan_rule
;
440 bool filter_disabled
;
443 struct mlx5e_l2_table
{
444 struct mlx5e_flow_table ft
;
445 struct hlist_head netdev_uc
[MLX5E_L2_ADDR_HASH_SIZE
];
446 struct hlist_head netdev_mc
[MLX5E_L2_ADDR_HASH_SIZE
];
447 struct mlx5e_l2_rule broadcast
;
448 struct mlx5e_l2_rule allmulti
;
449 struct mlx5e_l2_rule promisc
;
450 bool broadcast_enabled
;
451 bool allmulti_enabled
;
452 bool promisc_enabled
;
455 /* L3/L4 traffic type classifier */
456 struct mlx5e_ttc_table
{
457 struct mlx5e_flow_table ft
;
458 struct mlx5_flow_rule
*rules
[MLX5E_NUM_TT
];
461 #define ARFS_HASH_SHIFT BITS_PER_BYTE
462 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
464 struct mlx5e_flow_table ft
;
465 struct mlx5_flow_rule
*default_rule
;
466 struct hlist_head rules_hash
[ARFS_HASH_SIZE
];
477 struct mlx5e_arfs_tables
{
478 struct arfs_table arfs_tables
[ARFS_NUM_TYPES
];
479 /* Protect aRFS rules list */
480 spinlock_t arfs_lock
;
481 struct list_head rules
;
483 struct workqueue_struct
*wq
;
488 MLX5E_VLAN_FT_LEVEL
= 0,
494 struct mlx5e_flow_steering
{
495 struct mlx5_flow_namespace
*ns
;
496 struct mlx5e_tc_table tc
;
497 struct mlx5e_vlan_table vlan
;
498 struct mlx5e_l2_table l2
;
499 struct mlx5e_ttc_table ttc
;
500 struct mlx5e_arfs_tables arfs
;
503 struct mlx5e_direct_tir
{
514 /* priv data path fields - start */
515 struct mlx5e_sq
**txq_to_sq_map
;
516 int channeltc_to_txq_map
[MLX5E_MAX_NUM_CHANNELS
][MLX5E_MAX_NUM_TC
];
517 /* priv data path fields - end */
520 struct mutex state_lock
; /* Protects Interface state */
521 struct mlx5_uar cq_uar
;
524 struct mlx5_core_mkey mkey
;
525 struct mlx5_core_mkey umr_mkey
;
526 struct mlx5e_rq drop_rq
;
528 struct mlx5e_channel
**channel
;
529 u32 tisn
[MLX5E_MAX_NUM_TC
];
531 u32 indir_tirn
[MLX5E_NUM_INDIR_TIRS
];
532 struct mlx5e_direct_tir direct_tir
[MLX5E_MAX_NUM_CHANNELS
];
534 struct mlx5e_flow_steering fs
;
535 struct mlx5e_vxlan_db vxlan
;
537 struct mlx5e_params params
;
538 struct workqueue_struct
*wq
;
539 struct work_struct update_carrier_work
;
540 struct work_struct set_rx_mode_work
;
541 struct delayed_work update_stats_work
;
543 struct mlx5_core_dev
*mdev
;
544 struct net_device
*netdev
;
545 struct mlx5e_stats stats
;
546 struct mlx5e_tstamp tstamp
;
550 enum mlx5e_link_mode
{
551 MLX5E_1000BASE_CX_SGMII
= 0,
552 MLX5E_1000BASE_KX
= 1,
553 MLX5E_10GBASE_CX4
= 2,
554 MLX5E_10GBASE_KX4
= 3,
555 MLX5E_10GBASE_KR
= 4,
556 MLX5E_20GBASE_KR2
= 5,
557 MLX5E_40GBASE_CR4
= 6,
558 MLX5E_40GBASE_KR4
= 7,
559 MLX5E_56GBASE_R4
= 8,
560 MLX5E_10GBASE_CR
= 12,
561 MLX5E_10GBASE_SR
= 13,
562 MLX5E_10GBASE_ER
= 14,
563 MLX5E_40GBASE_SR4
= 15,
564 MLX5E_40GBASE_LR4
= 16,
565 MLX5E_100GBASE_CR4
= 20,
566 MLX5E_100GBASE_SR4
= 21,
567 MLX5E_100GBASE_KR4
= 22,
568 MLX5E_100GBASE_LR4
= 23,
569 MLX5E_100BASE_TX
= 24,
570 MLX5E_1000BASE_T
= 25,
571 MLX5E_10GBASE_T
= 26,
572 MLX5E_25GBASE_CR
= 27,
573 MLX5E_25GBASE_KR
= 28,
574 MLX5E_25GBASE_SR
= 29,
575 MLX5E_50GBASE_CR2
= 30,
576 MLX5E_50GBASE_KR2
= 31,
577 MLX5E_LINK_MODES_NUMBER
,
580 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
582 void mlx5e_send_nop(struct mlx5e_sq
*sq
, bool notify_hw
);
583 u16
mlx5e_select_queue(struct net_device
*dev
, struct sk_buff
*skb
,
584 void *accel_priv
, select_queue_fallback_t fallback
);
585 netdev_tx_t
mlx5e_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
587 void mlx5e_completion_event(struct mlx5_core_cq
*mcq
);
588 void mlx5e_cq_error_event(struct mlx5_core_cq
*mcq
, enum mlx5_event event
);
589 int mlx5e_napi_poll(struct napi_struct
*napi
, int budget
);
590 bool mlx5e_poll_tx_cq(struct mlx5e_cq
*cq
, int napi_budget
);
591 int mlx5e_poll_rx_cq(struct mlx5e_cq
*cq
, int budget
);
593 void mlx5e_handle_rx_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
);
594 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
);
595 bool mlx5e_post_rx_wqes(struct mlx5e_rq
*rq
);
596 int mlx5e_alloc_rx_wqe(struct mlx5e_rq
*rq
, struct mlx5e_rx_wqe
*wqe
, u16 ix
);
597 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq
*rq
, struct mlx5e_rx_wqe
*wqe
, u16 ix
);
598 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq
*rq
);
599 void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq
*rq
,
600 struct mlx5_cqe64
*cqe
,
602 struct mlx5e_mpw_info
*wi
,
603 struct sk_buff
*skb
);
604 void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq
*rq
,
605 struct mlx5_cqe64
*cqe
,
607 struct mlx5e_mpw_info
*wi
,
608 struct sk_buff
*skb
);
609 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq
*rq
,
610 struct mlx5e_mpw_info
*wi
);
611 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq
*rq
,
612 struct mlx5e_mpw_info
*wi
);
613 struct mlx5_cqe64
*mlx5e_get_cqe(struct mlx5e_cq
*cq
);
615 void mlx5e_update_stats(struct mlx5e_priv
*priv
);
617 int mlx5e_create_flow_steering(struct mlx5e_priv
*priv
);
618 void mlx5e_destroy_flow_steering(struct mlx5e_priv
*priv
);
619 void mlx5e_init_l2_addr(struct mlx5e_priv
*priv
);
620 void mlx5e_destroy_flow_table(struct mlx5e_flow_table
*ft
);
621 void mlx5e_set_rx_mode_work(struct work_struct
*work
);
623 void mlx5e_fill_hwstamp(struct mlx5e_tstamp
*clock
, u64 timestamp
,
624 struct skb_shared_hwtstamps
*hwts
);
625 void mlx5e_timestamp_init(struct mlx5e_priv
*priv
);
626 void mlx5e_timestamp_cleanup(struct mlx5e_priv
*priv
);
627 int mlx5e_hwstamp_set(struct net_device
*dev
, struct ifreq
*ifr
);
628 int mlx5e_hwstamp_get(struct net_device
*dev
, struct ifreq
*ifr
);
629 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv
*priv
, bool val
);
631 int mlx5e_vlan_rx_add_vid(struct net_device
*dev
, __always_unused __be16 proto
,
633 int mlx5e_vlan_rx_kill_vid(struct net_device
*dev
, __always_unused __be16 proto
,
635 void mlx5e_enable_vlan_filter(struct mlx5e_priv
*priv
);
636 void mlx5e_disable_vlan_filter(struct mlx5e_priv
*priv
);
638 int mlx5e_modify_rqs_vsd(struct mlx5e_priv
*priv
, bool vsd
);
640 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, u32 rqtn
, int sz
, int ix
);
641 void mlx5e_build_tir_ctx_hash(void *tirc
, struct mlx5e_priv
*priv
);
643 int mlx5e_open_locked(struct net_device
*netdev
);
644 int mlx5e_close_locked(struct net_device
*netdev
);
645 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev
*mdev
,
646 u32
*indirection_rqt
, int len
,
648 int mlx5e_get_max_linkspeed(struct mlx5_core_dev
*mdev
, u32
*speed
);
650 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq
*sq
,
651 struct mlx5_wqe_ctrl_seg
*ctrl
, int bf_sz
)
653 u16 ofst
= MLX5_BF_OFFSET
+ sq
->bf_offset
;
655 /* ensure wqe is visible to device before updating doorbell record */
658 *sq
->wq
.db
= cpu_to_be32(sq
->pc
);
660 /* ensure doorbell record is visible to device before ringing the
665 __iowrite64_copy(sq
->uar_map
+ ofst
, ctrl
, bf_sz
);
667 mlx5_write64((__be32
*)ctrl
, sq
->uar_map
+ ofst
, NULL
);
668 /* flush the write-combining mapped buffer */
671 sq
->bf_offset
^= sq
->bf_buf_size
;
674 static inline void mlx5e_cq_arm(struct mlx5e_cq
*cq
)
676 struct mlx5_core_cq
*mcq
;
679 mlx5_cq_arm(mcq
, MLX5_CQ_DB_REQ_NOT
, mcq
->uar
->map
, NULL
, cq
->wq
.cc
);
682 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev
*mdev
)
684 return min_t(int, mdev
->priv
.eq_table
.num_comp_vectors
,
685 MLX5E_MAX_NUM_CHANNELS
);
688 static inline int mlx5e_get_mtt_octw(int npages
)
690 return ALIGN(npages
, 8) / 2;
693 extern const struct ethtool_ops mlx5e_ethtool_ops
;
694 #ifdef CONFIG_MLX5_CORE_EN_DCB
695 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops
;
696 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv
*priv
, struct ieee_ets
*ets
);
699 #ifndef CONFIG_RFS_ACCEL
700 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv
*priv
)
705 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv
*priv
) {}
707 static inline int mlx5e_arfs_enable(struct mlx5e_priv
*priv
)
712 static inline int mlx5e_arfs_disable(struct mlx5e_priv
*priv
)
717 int mlx5e_arfs_create_tables(struct mlx5e_priv
*priv
);
718 void mlx5e_arfs_destroy_tables(struct mlx5e_priv
*priv
);
719 int mlx5e_arfs_enable(struct mlx5e_priv
*priv
);
720 int mlx5e_arfs_disable(struct mlx5e_priv
*priv
);
721 int mlx5e_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
722 u16 rxq_index
, u32 flow_id
);
725 u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev
*mdev
);
727 #endif /* __MLX5_EN_H__ */