drivers/net/ethernet/mellanox/mlx5/core/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <asm-generic/kmap_types.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #include <linux/io-mapping.h>
  41 #include <linux/mlx5/driver.h>
  42 #include <linux/mlx5/cq.h>
  43 #include <linux/mlx5/qp.h>
  44 #include <linux/mlx5/srq.h>
  45 #include <linux/debugfs.h>
  46 #include <linux/kmod.h>
  47 #include <linux/mlx5/mlx5_ifc.h>
  48 #include "mlx5_core.h"
  49
  50 #define DRIVER_NAME "mlx5_core"
  51 #define DRIVER_VERSION "3.0"
  52 #define DRIVER_RELDATE  "January 2015"
  53
  54 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  55 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
  56 MODULE_LICENSE("Dual BSD/GPL");
  57 MODULE_VERSION(DRIVER_VERSION);
  58
  59 int mlx5_core_debug_mask;
  60 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
  61 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
  62
  63 #define MLX5_DEFAULT_PROF       2
  64 static int prof_sel = MLX5_DEFAULT_PROF;
  65 module_param_named(prof_sel, prof_sel, int, 0444);
  66 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
  67
  68 struct workqueue_struct *mlx5_core_wq;
  69 static LIST_HEAD(intf_list);
  70 static LIST_HEAD(dev_list);
  71 static DEFINE_MUTEX(intf_mutex);
  72
  73 struct mlx5_device_context {
  74         struct list_head        list;
  75         struct mlx5_interface  *intf;
  76         void                   *context;
  77 };
  78
  79 static struct mlx5_profile profile[] = {
  80         [0] = {
  81                 .mask           = 0,
  82         },
  83         [1] = {
  84                 .mask           = MLX5_PROF_MASK_QP_SIZE,
  85                 .log_max_qp     = 12,
  86         },
  87         [2] = {
  88                 .mask           = MLX5_PROF_MASK_QP_SIZE |
  89                                   MLX5_PROF_MASK_MR_CACHE,
  90                 .log_max_qp     = 17,
  91                 .mr_cache[0]    = {
  92                         .size   = 500,
  93                         .limit  = 250
  94                 },
  95                 .mr_cache[1]    = {
  96                         .size   = 500,
  97                         .limit  = 250
  98                 },
  99                 .mr_cache[2]    = {
 100                         .size   = 500,
 101                         .limit  = 250
 102                 },
 103                 .mr_cache[3]    = {
 104                         .size   = 500,
 105                         .limit  = 250
 106                 },
 107                 .mr_cache[4]    = {
 108                         .size   = 500,
 109                         .limit  = 250
 110                 },
 111                 .mr_cache[5]    = {
 112                         .size   = 500,
 113                         .limit  = 250
 114                 },
 115                 .mr_cache[6]    = {
 116                         .size   = 500,
 117                         .limit  = 250
 118                 },
 119                 .mr_cache[7]    = {
 120                         .size   = 500,
 121                         .limit  = 250
 122                 },
 123                 .mr_cache[8]    = {
 124                         .size   = 500,
 125                         .limit  = 250
 126                 },
 127                 .mr_cache[9]    = {
 128                         .size   = 500,
 129                         .limit  = 250
 130                 },
 131                 .mr_cache[10]   = {
 132                         .size   = 500,
 133                         .limit  = 250
 134                 },
 135                 .mr_cache[11]   = {
 136                         .size   = 500,
 137                         .limit  = 250
 138                 },
 139                 .mr_cache[12]   = {
 140                         .size   = 64,
 141                         .limit  = 32
 142                 },
 143                 .mr_cache[13]   = {
 144                         .size   = 32,
 145                         .limit  = 16
 146                 },
 147                 .mr_cache[14]   = {
 148                         .size   = 16,
 149                         .limit  = 8
 150                 },
 151                 .mr_cache[15]   = {
 152                         .size   = 8,
 153                         .limit  = 4
 154                 },
 155         },
 156 };
 157
 158 static int set_dma_caps(struct pci_dev *pdev)
 159 {
 160         int err;
 161
 162         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
 163         if (err) {
 164                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
 165                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 166                 if (err) {
 167                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
 168                         return err;
 169                 }
 170         }
 171
 172         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 173         if (err) {
 174                 dev_warn(&pdev->dev,
 175                          "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
 176                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 177                 if (err) {
 178                         dev_err(&pdev->dev,
 179                                 "Can't set consistent PCI DMA mask, aborting\n");
 180                         return err;
 181                 }
 182         }
 183
 184         dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
 185         return err;
 186 }
 187
 188 static int request_bar(struct pci_dev *pdev)
 189 {
 190         int err = 0;
 191
 192         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
 193                 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
 194                 return -ENODEV;
 195         }
 196
 197         err = pci_request_regions(pdev, DRIVER_NAME);
 198         if (err)
 199                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
 200
 201         return err;
 202 }
 203
 204 static void release_bar(struct pci_dev *pdev)
 205 {
 206         pci_release_regions(pdev);
 207 }
 208
 209 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
 210 {
 211         struct mlx5_eq_table *table = &dev->priv.eq_table;
 212         int num_eqs = 1 << dev->caps.gen.log_max_eq;
 213         int nvec;
 214         int i;
 215
 216         nvec = dev->caps.gen.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
 217         nvec = min_t(int, nvec, num_eqs);
 218         if (nvec <= MLX5_EQ_VEC_COMP_BASE)
 219                 return -ENOMEM;
 220
 221         table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL);
 222         if (!table->msix_arr)
 223                 return -ENOMEM;
 224
 225         for (i = 0; i < nvec; i++)
 226                 table->msix_arr[i].entry = i;
 227
 228         nvec = pci_enable_msix_range(dev->pdev, table->msix_arr,
 229                                      MLX5_EQ_VEC_COMP_BASE + 1, nvec);
 230         if (nvec < 0)
 231                 return nvec;
 232
 233         table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
 234
 235         return 0;
 236 }
 237
 238 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
 239 {
 240         struct mlx5_eq_table *table = &dev->priv.eq_table;
 241
 242         pci_disable_msix(dev->pdev);
 243         kfree(table->msix_arr);
 244 }
 245
 246 struct mlx5_reg_host_endianess {
 247         u8      he;
 248         u8      rsvd[15];
 249 };
 250
 251
 252 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
 253
 254 enum {
 255         MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
 256                                 MLX5_DEV_CAP_FLAG_DCT,
 257 };
 258
 259 static u16 to_fw_pkey_sz(u32 size)
 260 {
 261         switch (size) {
 262         case 128:
 263                 return 0;
 264         case 256:
 265                 return 1;
 266         case 512:
 267                 return 2;
 268         case 1024:
 269                 return 3;
 270         case 2048:
 271                 return 4;
 272         case 4096:
 273                 return 5;
 274         default:
 275                 pr_warn("invalid pkey table size %d\n", size);
 276                 return 0;
 277         }
 278 }
 279
 280 /* selectively copy writable fields clearing any reserved area
 281  */
 282 static void copy_rw_fields(void *to, struct mlx5_caps *from)
 283 {
 284         __be64 *flags_off = (__be64 *)MLX5_ADDR_OF(cmd_hca_cap, to, reserved_22);
 285         u64 v64;
 286
 287         MLX5_SET(cmd_hca_cap, to, log_max_qp, from->gen.log_max_qp);
 288         MLX5_SET(cmd_hca_cap, to, log_max_ra_req_qp, from->gen.log_max_ra_req_qp);
 289         MLX5_SET(cmd_hca_cap, to, log_max_ra_res_qp, from->gen.log_max_ra_res_qp);
 290         MLX5_SET(cmd_hca_cap, to, pkey_table_size, from->gen.pkey_table_size);
 291         MLX5_SET(cmd_hca_cap, to, pkey_table_size, to_fw_pkey_sz(from->gen.pkey_table_size));
 292         MLX5_SET(cmd_hca_cap, to, log_uar_page_sz, PAGE_SHIFT - 12);
 293         v64 = from->gen.flags & MLX5_CAP_BITS_RW_MASK;
 294         *flags_off = cpu_to_be64(v64);
 295 }
 296
 297 static u16 get_pkey_table_size(int pkey)
 298 {
 299         if (pkey > MLX5_MAX_LOG_PKEY_TABLE)
 300                 return 0;
 301
 302         return MLX5_MIN_PKEY_TABLE_SIZE << pkey;
 303 }
 304
 305 static void fw2drv_caps(struct mlx5_caps *caps, void *out)
 306 {
 307         struct mlx5_general_caps *gen = &caps->gen;
 308
 309         gen->max_srq_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_srq_sz);
 310         gen->max_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_qp_sz);
 311         gen->log_max_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_qp);
 312         gen->log_max_strq = MLX5_GET_PR(cmd_hca_cap, out, log_max_strq_sz);
 313         gen->log_max_srq = MLX5_GET_PR(cmd_hca_cap, out, log_max_srqs);
 314         gen->max_cqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_cq_sz);
 315         gen->log_max_cq = MLX5_GET_PR(cmd_hca_cap, out, log_max_cq);
 316         gen->max_eqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_eq_sz);
 317         gen->log_max_mkey = MLX5_GET_PR(cmd_hca_cap, out, log_max_mkey);
 318         gen->log_max_eq = MLX5_GET_PR(cmd_hca_cap, out, log_max_eq);
 319         gen->max_indirection = MLX5_GET_PR(cmd_hca_cap, out, max_indirection);
 320         gen->log_max_mrw_sz = MLX5_GET_PR(cmd_hca_cap, out, log_max_mrw_sz);
 321         gen->log_max_bsf_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_bsf_list_size);
 322         gen->log_max_klm_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_klm_list_size);
 323         gen->log_max_ra_req_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_dc);
 324         gen->log_max_ra_res_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_dc);
 325         gen->log_max_ra_req_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_qp);
 326         gen->log_max_ra_res_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_qp);
 327         gen->max_qp_counters = MLX5_GET_PR(cmd_hca_cap, out, max_qp_cnt);
 328         gen->pkey_table_size = get_pkey_table_size(MLX5_GET_PR(cmd_hca_cap, out, pkey_table_size));
 329         gen->local_ca_ack_delay = MLX5_GET_PR(cmd_hca_cap, out, local_ca_ack_delay);
 330         gen->num_ports = MLX5_GET_PR(cmd_hca_cap, out, num_ports);
 331         gen->log_max_msg = MLX5_GET_PR(cmd_hca_cap, out, log_max_msg);
 332         gen->stat_rate_support = MLX5_GET_PR(cmd_hca_cap, out, stat_rate_support);
 333         gen->flags = be64_to_cpu(*(__be64 *)MLX5_ADDR_OF(cmd_hca_cap, out, reserved_22));
 334         pr_debug("flags = 0x%llx\n", gen->flags);
 335         gen->uar_sz = MLX5_GET_PR(cmd_hca_cap, out, uar_sz);
 336         gen->min_log_pg_sz = MLX5_GET_PR(cmd_hca_cap, out, log_pg_sz);
 337         gen->bf_reg_size = MLX5_GET_PR(cmd_hca_cap, out, bf);
 338         gen->bf_reg_size = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_bf_reg_size);
 339         gen->max_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq);
 340         gen->max_rq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_rq);
 341         gen->max_dc_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq_dc);
 342         gen->max_qp_mcg = MLX5_GET_PR(cmd_hca_cap, out, max_qp_mcg);
 343         gen->log_max_pd = MLX5_GET_PR(cmd_hca_cap, out, log_max_pd);
 344         gen->log_max_xrcd = MLX5_GET_PR(cmd_hca_cap, out, log_max_xrcd);
 345         gen->log_uar_page_sz = MLX5_GET_PR(cmd_hca_cap, out, log_uar_page_sz);
 346 }
 347
 348 static const char *caps_opmod_str(u16 opmod)
 349 {
 350         switch (opmod) {
 351         case HCA_CAP_OPMOD_GET_MAX:
 352                 return "GET_MAX";
 353         case HCA_CAP_OPMOD_GET_CUR:
 354                 return "GET_CUR";
 355         default:
 356                 return "Invalid";
 357         }
 358 }
 359
 360 int mlx5_core_get_caps(struct mlx5_core_dev *dev, struct mlx5_caps *caps,
 361                        u16 opmod)
 362 {
 363         u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
 364         int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
 365         void *out;
 366         int err;
 367
 368         memset(in, 0, sizeof(in));
 369         out = kzalloc(out_sz, GFP_KERNEL);
 370         if (!out)
 371                 return -ENOMEM;
 372         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 373         MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
 374         err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
 375         if (err)
 376                 goto query_ex;
 377
 378         err = mlx5_cmd_status_to_err_v2(out);
 379         if (err) {
 380                 mlx5_core_warn(dev, "query max hca cap failed, %d\n", err);
 381                 goto query_ex;
 382         }
 383         mlx5_core_dbg(dev, "%s\n", caps_opmod_str(opmod));
 384         fw2drv_caps(caps, MLX5_ADDR_OF(query_hca_cap_out, out, capability_struct));
 385
 386 query_ex:
 387         kfree(out);
 388         return err;
 389 }
 390
 391 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
 392 {
 393         u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
 394         int err;
 395
 396         memset(out, 0, sizeof(out));
 397
 398         MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
 399         err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
 400         if (err)
 401                 return err;
 402
 403         err = mlx5_cmd_status_to_err_v2(out);
 404
 405         return err;
 406 }
 407
 408 static int handle_hca_cap(struct mlx5_core_dev *dev)
 409 {
 410         void *set_ctx = NULL;
 411         struct mlx5_profile *prof = dev->profile;
 412         struct mlx5_caps *cur_caps = NULL;
 413         struct mlx5_caps *max_caps = NULL;
 414         int err = -ENOMEM;
 415         int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
 416
 417         set_ctx = kzalloc(set_sz, GFP_KERNEL);
 418         if (!set_ctx)
 419                 goto query_ex;
 420
 421         max_caps = kzalloc(sizeof(*max_caps), GFP_KERNEL);
 422         if (!max_caps)
 423                 goto query_ex;
 424
 425         cur_caps = kzalloc(sizeof(*cur_caps), GFP_KERNEL);
 426         if (!cur_caps)
 427                 goto query_ex;
 428
 429         err = mlx5_core_get_caps(dev, max_caps, HCA_CAP_OPMOD_GET_MAX);
 430         if (err)
 431                 goto query_ex;
 432
 433         err = mlx5_core_get_caps(dev, cur_caps, HCA_CAP_OPMOD_GET_CUR);
 434         if (err)
 435                 goto query_ex;
 436
 437         /* we limit the size of the pkey table to 128 entries for now */
 438         cur_caps->gen.pkey_table_size = 128;
 439
 440         if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
 441                 cur_caps->gen.log_max_qp = prof->log_max_qp;
 442
 443         /* disable checksum */
 444         cur_caps->gen.flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
 445
 446         copy_rw_fields(MLX5_ADDR_OF(set_hca_cap_in, set_ctx, hca_capability_struct),
 447                        cur_caps);
 448         err = set_caps(dev, set_ctx, set_sz);
 449
 450 query_ex:
 451         kfree(cur_caps);
 452         kfree(max_caps);
 453         kfree(set_ctx);
 454
 455         return err;
 456 }
 457
 458 static int set_hca_ctrl(struct mlx5_core_dev *dev)
 459 {
 460         struct mlx5_reg_host_endianess he_in;
 461         struct mlx5_reg_host_endianess he_out;
 462         int err;
 463
 464         memset(&he_in, 0, sizeof(he_in));
 465         he_in.he = MLX5_SET_HOST_ENDIANNESS;
 466         err = mlx5_core_access_reg(dev, &he_in,  sizeof(he_in),
 467                                         &he_out, sizeof(he_out),
 468                                         MLX5_REG_HOST_ENDIANNESS, 0, 1);
 469         return err;
 470 }
 471
 472 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
 473 {
 474         int err;
 475         struct mlx5_enable_hca_mbox_in in;
 476         struct mlx5_enable_hca_mbox_out out;
 477
 478         memset(&in, 0, sizeof(in));
 479         memset(&out, 0, sizeof(out));
 480         in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
 481         err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
 482         if (err)
 483                 return err;
 484
 485         if (out.hdr.status)
 486                 return mlx5_cmd_status_to_err(&out.hdr);
 487
 488         return 0;
 489 }
 490
 491 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
 492 {
 493         int err;
 494         struct mlx5_disable_hca_mbox_in in;
 495         struct mlx5_disable_hca_mbox_out out;
 496
 497         memset(&in, 0, sizeof(in));
 498         memset(&out, 0, sizeof(out));
 499         in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
 500         err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
 501         if (err)
 502                 return err;
 503
 504         if (out.hdr.status)
 505                 return mlx5_cmd_status_to_err(&out.hdr);
 506
 507         return 0;
 508 }
 509
 510 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
 511 {
 512         struct mlx5_eq_table *table = &dev->priv.eq_table;
 513         struct mlx5_eq *eq, *n;
 514         int err = -ENOENT;
 515
 516         spin_lock(&table->lock);
 517         list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
 518                 if (eq->index == vector) {
 519                         *eqn = eq->eqn;
 520                         *irqn = eq->irqn;
 521                         err = 0;
 522                         break;
 523                 }
 524         }
 525         spin_unlock(&table->lock);
 526
 527         return err;
 528 }
 529 EXPORT_SYMBOL(mlx5_vector2eqn);
 530
 531 static void free_comp_eqs(struct mlx5_core_dev *dev)
 532 {
 533         struct mlx5_eq_table *table = &dev->priv.eq_table;
 534         struct mlx5_eq *eq, *n;
 535
 536         spin_lock(&table->lock);
 537         list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
 538                 list_del(&eq->list);
 539                 spin_unlock(&table->lock);
 540                 if (mlx5_destroy_unmap_eq(dev, eq))
 541                         mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
 542                                        eq->eqn);
 543                 kfree(eq);
 544                 spin_lock(&table->lock);
 545         }
 546         spin_unlock(&table->lock);
 547 }
 548
 549 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
 550 {
 551         struct mlx5_eq_table *table = &dev->priv.eq_table;
 552         char name[MLX5_MAX_EQ_NAME];
 553         struct mlx5_eq *eq;
 554         int ncomp_vec;
 555         int nent;
 556         int err;
 557         int i;
 558
 559         INIT_LIST_HEAD(&table->comp_eqs_list);
 560         ncomp_vec = table->num_comp_vectors;
 561         nent = MLX5_COMP_EQ_SIZE;
 562         for (i = 0; i < ncomp_vec; i++) {
 563                 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
 564                 if (!eq) {
 565                         err = -ENOMEM;
 566                         goto clean;
 567                 }
 568
 569                 snprintf(name, MLX5_MAX_EQ_NAME, "mlx5_comp%d", i);
 570                 err = mlx5_create_map_eq(dev, eq,
 571                                          i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
 572                                          name, &dev->priv.uuari.uars[0]);
 573                 if (err) {
 574                         kfree(eq);
 575                         goto clean;
 576                 }
 577                 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
 578                 eq->index = i;
 579                 spin_lock(&table->lock);
 580                 list_add_tail(&eq->list, &table->comp_eqs_list);
 581                 spin_unlock(&table->lock);
 582         }
 583
 584         return 0;
 585
 586 clean:
 587         free_comp_eqs(dev);
 588         return err;
 589 }
 590
 591 static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
 592 {
 593         struct mlx5_priv *priv = &dev->priv;
 594         int err;
 595
 596         dev->pdev = pdev;
 597         pci_set_drvdata(dev->pdev, dev);
 598         strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
 599         priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
 600
 601         mutex_init(&priv->pgdir_mutex);
 602         INIT_LIST_HEAD(&priv->pgdir_list);
 603         spin_lock_init(&priv->mkey_lock);
 604
 605         priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
 606         if (!priv->dbg_root)
 607                 return -ENOMEM;
 608
 609         err = pci_enable_device(pdev);
 610         if (err) {
 611                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
 612                 goto err_dbg;
 613         }
 614
 615         err = request_bar(pdev);
 616         if (err) {
 617                 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
 618                 goto err_disable;
 619         }
 620
 621         pci_set_master(pdev);
 622
 623         err = set_dma_caps(pdev);
 624         if (err) {
 625                 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
 626                 goto err_clr_master;
 627         }
 628
 629         dev->iseg_base = pci_resource_start(dev->pdev, 0);
 630         dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
 631         if (!dev->iseg) {
 632                 err = -ENOMEM;
 633                 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
 634                 goto err_clr_master;
 635         }
 636         dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
 637                  fw_rev_min(dev), fw_rev_sub(dev));
 638
 639         err = mlx5_cmd_init(dev);
 640         if (err) {
 641                 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
 642                 goto err_unmap;
 643         }
 644
 645         mlx5_pagealloc_init(dev);
 646
 647         err = mlx5_core_enable_hca(dev);
 648         if (err) {
 649                 dev_err(&pdev->dev, "enable hca failed\n");
 650                 goto err_pagealloc_cleanup;
 651         }
 652
 653         err = mlx5_satisfy_startup_pages(dev, 1);
 654         if (err) {
 655                 dev_err(&pdev->dev, "failed to allocate boot pages\n");
 656                 goto err_disable_hca;
 657         }
 658
 659         err = set_hca_ctrl(dev);
 660         if (err) {
 661                 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
 662                 goto reclaim_boot_pages;
 663         }
 664
 665         err = handle_hca_cap(dev);
 666         if (err) {
 667                 dev_err(&pdev->dev, "handle_hca_cap failed\n");
 668                 goto reclaim_boot_pages;
 669         }
 670
 671         err = mlx5_satisfy_startup_pages(dev, 0);
 672         if (err) {
 673                 dev_err(&pdev->dev, "failed to allocate init pages\n");
 674                 goto reclaim_boot_pages;
 675         }
 676
 677         err = mlx5_pagealloc_start(dev);
 678         if (err) {
 679                 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
 680                 goto reclaim_boot_pages;
 681         }
 682
 683         err = mlx5_cmd_init_hca(dev);
 684         if (err) {
 685                 dev_err(&pdev->dev, "init hca failed\n");
 686                 goto err_pagealloc_stop;
 687         }
 688
 689         mlx5_start_health_poll(dev);
 690
 691         err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
 692         if (err) {
 693                 dev_err(&pdev->dev, "query hca failed\n");
 694                 goto err_stop_poll;
 695         }
 696
 697         err = mlx5_cmd_query_adapter(dev);
 698         if (err) {
 699                 dev_err(&pdev->dev, "query adapter failed\n");
 700                 goto err_stop_poll;
 701         }
 702
 703         err = mlx5_enable_msix(dev);
 704         if (err) {
 705                 dev_err(&pdev->dev, "enable msix failed\n");
 706                 goto err_stop_poll;
 707         }
 708
 709         err = mlx5_eq_init(dev);
 710         if (err) {
 711                 dev_err(&pdev->dev, "failed to initialize eq\n");
 712                 goto disable_msix;
 713         }
 714
 715         err = mlx5_alloc_uuars(dev, &priv->uuari);
 716         if (err) {
 717                 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
 718                 goto err_eq_cleanup;
 719         }
 720
 721         err = mlx5_start_eqs(dev);
 722         if (err) {
 723                 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
 724                 goto err_free_uar;
 725         }
 726
 727         err = alloc_comp_eqs(dev);
 728         if (err) {
 729                 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
 730                 goto err_stop_eqs;
 731         }
 732
 733         MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
 734
 735         mlx5_init_cq_table(dev);
 736         mlx5_init_qp_table(dev);
 737         mlx5_init_srq_table(dev);
 738         mlx5_init_mr_table(dev);
 739
 740         return 0;
 741
 742 err_stop_eqs:
 743         mlx5_stop_eqs(dev);
 744
 745 err_free_uar:
 746         mlx5_free_uuars(dev, &priv->uuari);
 747
 748 err_eq_cleanup:
 749         mlx5_eq_cleanup(dev);
 750
 751 disable_msix:
 752         mlx5_disable_msix(dev);
 753
 754 err_stop_poll:
 755         mlx5_stop_health_poll(dev);
 756         if (mlx5_cmd_teardown_hca(dev)) {
 757                 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
 758                 return err;
 759         }
 760
 761 err_pagealloc_stop:
 762         mlx5_pagealloc_stop(dev);
 763
 764 reclaim_boot_pages:
 765         mlx5_reclaim_startup_pages(dev);
 766
 767 err_disable_hca:
 768         mlx5_core_disable_hca(dev);
 769
 770 err_pagealloc_cleanup:
 771         mlx5_pagealloc_cleanup(dev);
 772         mlx5_cmd_cleanup(dev);
 773
 774 err_unmap:
 775         iounmap(dev->iseg);
 776
 777 err_clr_master:
 778         pci_clear_master(dev->pdev);
 779         release_bar(dev->pdev);
 780
 781 err_disable:
 782         pci_disable_device(dev->pdev);
 783
 784 err_dbg:
 785         debugfs_remove(priv->dbg_root);
 786         return err;
 787 }
 788
 789 static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
 790 {
 791         struct mlx5_priv *priv = &dev->priv;
 792
 793         mlx5_cleanup_srq_table(dev);
 794         mlx5_cleanup_qp_table(dev);
 795         mlx5_cleanup_cq_table(dev);
 796         free_comp_eqs(dev);
 797         mlx5_stop_eqs(dev);
 798         mlx5_free_uuars(dev, &priv->uuari);
 799         mlx5_eq_cleanup(dev);
 800         mlx5_disable_msix(dev);
 801         mlx5_stop_health_poll(dev);
 802         if (mlx5_cmd_teardown_hca(dev)) {
 803                 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
 804                 return;
 805         }
 806         mlx5_pagealloc_stop(dev);
 807         mlx5_reclaim_startup_pages(dev);
 808         mlx5_core_disable_hca(dev);
 809         mlx5_pagealloc_cleanup(dev);
 810         mlx5_cmd_cleanup(dev);
 811         iounmap(dev->iseg);
 812         pci_clear_master(dev->pdev);
 813         release_bar(dev->pdev);
 814         pci_disable_device(dev->pdev);
 815         debugfs_remove(priv->dbg_root);
 816 }
 817
 818 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
 819 {
 820         struct mlx5_device_context *dev_ctx;
 821         struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
 822
 823         dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
 824         if (!dev_ctx) {
 825                 pr_warn("mlx5_add_device: alloc context failed\n");
 826                 return;
 827         }
 828
 829         dev_ctx->intf    = intf;
 830         dev_ctx->context = intf->add(dev);
 831
 832         if (dev_ctx->context) {
 833                 spin_lock_irq(&priv->ctx_lock);
 834                 list_add_tail(&dev_ctx->list, &priv->ctx_list);
 835                 spin_unlock_irq(&priv->ctx_lock);
 836         } else {
 837                 kfree(dev_ctx);
 838         }
 839 }
 840
 841 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
 842 {
 843         struct mlx5_device_context *dev_ctx;
 844         struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
 845
 846         list_for_each_entry(dev_ctx, &priv->ctx_list, list)
 847                 if (dev_ctx->intf == intf) {
 848                         spin_lock_irq(&priv->ctx_lock);
 849                         list_del(&dev_ctx->list);
 850                         spin_unlock_irq(&priv->ctx_lock);
 851
 852                         intf->remove(dev, dev_ctx->context);
 853                         kfree(dev_ctx);
 854                         return;
 855                 }
 856 }
 857 static int mlx5_register_device(struct mlx5_core_dev *dev)
 858 {
 859         struct mlx5_priv *priv = &dev->priv;
 860         struct mlx5_interface *intf;
 861
 862         mutex_lock(&intf_mutex);
 863         list_add_tail(&priv->dev_list, &dev_list);
 864         list_for_each_entry(intf, &intf_list, list)
 865                 mlx5_add_device(intf, priv);
 866         mutex_unlock(&intf_mutex);
 867
 868         return 0;
 869 }
 870 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
 871 {
 872         struct mlx5_priv *priv = &dev->priv;
 873         struct mlx5_interface *intf;
 874
 875         mutex_lock(&intf_mutex);
 876         list_for_each_entry(intf, &intf_list, list)
 877                 mlx5_remove_device(intf, priv);
 878         list_del(&priv->dev_list);
 879         mutex_unlock(&intf_mutex);
 880 }
 881
 882 int mlx5_register_interface(struct mlx5_interface *intf)
 883 {
 884         struct mlx5_priv *priv;
 885
 886         if (!intf->add || !intf->remove)
 887                 return -EINVAL;
 888
 889         mutex_lock(&intf_mutex);
 890         list_add_tail(&intf->list, &intf_list);
 891         list_for_each_entry(priv, &dev_list, dev_list)
 892                 mlx5_add_device(intf, priv);
 893         mutex_unlock(&intf_mutex);
 894
 895         return 0;
 896 }
 897 EXPORT_SYMBOL(mlx5_register_interface);
 898
 899 void mlx5_unregister_interface(struct mlx5_interface *intf)
 900 {
 901         struct mlx5_priv *priv;
 902
 903         mutex_lock(&intf_mutex);
 904         list_for_each_entry(priv, &dev_list, dev_list)
 905                mlx5_remove_device(intf, priv);
 906         list_del(&intf->list);
 907         mutex_unlock(&intf_mutex);
 908 }
 909 EXPORT_SYMBOL(mlx5_unregister_interface);
 910
 911 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
 912 {
 913         struct mlx5_priv *priv = &mdev->priv;
 914         struct mlx5_device_context *dev_ctx;
 915         unsigned long flags;
 916         void *result = NULL;
 917
 918         spin_lock_irqsave(&priv->ctx_lock, flags);
 919
 920         list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
 921                 if ((dev_ctx->intf->protocol == protocol) &&
 922                     dev_ctx->intf->get_dev) {
 923                         result = dev_ctx->intf->get_dev(dev_ctx->context);
 924                         break;
 925                 }
 926
 927         spin_unlock_irqrestore(&priv->ctx_lock, flags);
 928
 929         return result;
 930 }
 931 EXPORT_SYMBOL(mlx5_get_protocol_dev);
 932
 933 static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
 934                             unsigned long param)
 935 {
 936         struct mlx5_priv *priv = &dev->priv;
 937         struct mlx5_device_context *dev_ctx;
 938         unsigned long flags;
 939
 940         spin_lock_irqsave(&priv->ctx_lock, flags);
 941
 942         list_for_each_entry(dev_ctx, &priv->ctx_list, list)
 943                 if (dev_ctx->intf->event)
 944                         dev_ctx->intf->event(dev, dev_ctx->context, event, param);
 945
 946         spin_unlock_irqrestore(&priv->ctx_lock, flags);
 947 }
 948
 949 struct mlx5_core_event_handler {
 950         void (*event)(struct mlx5_core_dev *dev,
 951                       enum mlx5_dev_event event,
 952                       void *data);
 953 };
 954
 955 #define MLX5_IB_MOD "mlx5_ib"
 956
 957 static int init_one(struct pci_dev *pdev,
 958                     const struct pci_device_id *id)
 959 {
 960         struct mlx5_core_dev *dev;
 961         struct mlx5_priv *priv;
 962         int err;
 963
 964         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
 965         if (!dev) {
 966                 dev_err(&pdev->dev, "kzalloc failed\n");
 967                 return -ENOMEM;
 968         }
 969         priv = &dev->priv;
 970
 971         pci_set_drvdata(pdev, dev);
 972
 973         if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
 974                 pr_warn("selected profile out of range, selecting default (%d)\n",
 975                         MLX5_DEFAULT_PROF);
 976                 prof_sel = MLX5_DEFAULT_PROF;
 977         }
 978         dev->profile = &profile[prof_sel];
 979         dev->event = mlx5_core_event;
 980
 981         INIT_LIST_HEAD(&priv->ctx_list);
 982         spin_lock_init(&priv->ctx_lock);
 983         err = mlx5_dev_init(dev, pdev);
 984         if (err) {
 985                 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
 986                 goto out;
 987         }
 988
 989         err = mlx5_register_device(dev);
 990         if (err) {
 991                 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
 992                 goto out_init;
 993         }
 994
 995         err = request_module_nowait(MLX5_IB_MOD);
 996         if (err)
 997                 pr_info("failed request module on %s\n", MLX5_IB_MOD);
 998
 999         return 0;
1000
1001 out_init:
1002         mlx5_dev_cleanup(dev);
1003 out:
1004         kfree(dev);
1005         return err;
1006 }
1007 static void remove_one(struct pci_dev *pdev)
1008 {
1009         struct mlx5_core_dev *dev  = pci_get_drvdata(pdev);
1010
1011         mlx5_unregister_device(dev);
1012         mlx5_dev_cleanup(dev);
1013         kfree(dev);
1014 }
1015
1016 static const struct pci_device_id mlx5_core_pci_table[] = {
1017         { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1018         { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1019         { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1020         { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1021         { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1022         { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
1023         { 0, }
1024 };
1025
1026 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1027
1028 static struct pci_driver mlx5_core_driver = {
1029         .name           = DRIVER_NAME,
1030         .id_table       = mlx5_core_pci_table,
1031         .probe          = init_one,
1032         .remove         = remove_one
1033 };
1034
1035 static int __init init(void)
1036 {
1037         int err;
1038
1039         mlx5_register_debugfs();
1040         mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1041         if (!mlx5_core_wq) {
1042                 err = -ENOMEM;
1043                 goto err_debug;
1044         }
1045         mlx5_health_init();
1046
1047         err = pci_register_driver(&mlx5_core_driver);
1048         if (err)
1049                 goto err_health;
1050
1051         return 0;
1052
1053 err_health:
1054         mlx5_health_cleanup();
1055         destroy_workqueue(mlx5_core_wq);
1056 err_debug:
1057         mlx5_unregister_debugfs();
1058         return err;
1059 }
1060
1061 static void __exit cleanup(void)
1062 {
1063         pci_unregister_driver(&mlx5_core_driver);
1064         mlx5_health_cleanup();
1065         destroy_workqueue(mlx5_core_wq);
1066         mlx5_unregister_debugfs();
1067 }
1068
1069 module_init(init);
1070 module_exit(cleanup);