2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/delay.h>
50 #include <linux/mlx5/mlx5_ifc.h>
51 #ifdef CONFIG_RFS_ACCEL
52 #include <linux/cpu_rmap.h>
54 #include <net/devlink.h>
55 #include "mlx5_core.h"
57 #ifdef CONFIG_MLX5_CORE_EN
61 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
62 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
63 MODULE_LICENSE("Dual BSD/GPL");
64 MODULE_VERSION(DRIVER_VERSION
);
66 int mlx5_core_debug_mask
;
67 module_param_named(debug_mask
, mlx5_core_debug_mask
, int, 0644);
68 MODULE_PARM_DESC(debug_mask
, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
70 #define MLX5_DEFAULT_PROF 2
71 static int prof_sel
= MLX5_DEFAULT_PROF
;
72 module_param_named(prof_sel
, prof_sel
, int, 0444);
73 MODULE_PARM_DESC(prof_sel
, "profile selector. Valid range 0 - 2");
75 static LIST_HEAD(intf_list
);
76 static LIST_HEAD(dev_list
);
77 static DEFINE_MUTEX(intf_mutex
);
79 struct mlx5_device_context
{
80 struct list_head list
;
81 struct mlx5_interface
*intf
;
86 MLX5_ATOMIC_REQ_MODE_BE
= 0x0,
87 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
= 0x1,
90 static struct mlx5_profile profile
[] = {
95 .mask
= MLX5_PROF_MASK_QP_SIZE
,
99 .mask
= MLX5_PROF_MASK_QP_SIZE
|
100 MLX5_PROF_MASK_MR_CACHE
,
169 #define FW_INIT_TIMEOUT_MILI 2000
170 #define FW_INIT_WAIT_MS 2
172 static int wait_fw_init(struct mlx5_core_dev
*dev
, u32 max_wait_mili
)
174 unsigned long end
= jiffies
+ msecs_to_jiffies(max_wait_mili
);
177 while (fw_initializing(dev
)) {
178 if (time_after(jiffies
, end
)) {
182 msleep(FW_INIT_WAIT_MS
);
188 static int set_dma_caps(struct pci_dev
*pdev
)
192 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
194 dev_warn(&pdev
->dev
, "Warning: couldn't set 64-bit PCI DMA mask\n");
195 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
197 dev_err(&pdev
->dev
, "Can't set PCI DMA mask, aborting\n");
202 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
205 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
206 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
209 "Can't set consistent PCI DMA mask, aborting\n");
214 dma_set_max_seg_size(&pdev
->dev
, 2u * 1024 * 1024 * 1024);
218 static int mlx5_pci_enable_device(struct mlx5_core_dev
*dev
)
220 struct pci_dev
*pdev
= dev
->pdev
;
223 mutex_lock(&dev
->pci_status_mutex
);
224 if (dev
->pci_status
== MLX5_PCI_STATUS_DISABLED
) {
225 err
= pci_enable_device(pdev
);
227 dev
->pci_status
= MLX5_PCI_STATUS_ENABLED
;
229 mutex_unlock(&dev
->pci_status_mutex
);
234 static void mlx5_pci_disable_device(struct mlx5_core_dev
*dev
)
236 struct pci_dev
*pdev
= dev
->pdev
;
238 mutex_lock(&dev
->pci_status_mutex
);
239 if (dev
->pci_status
== MLX5_PCI_STATUS_ENABLED
) {
240 pci_disable_device(pdev
);
241 dev
->pci_status
= MLX5_PCI_STATUS_DISABLED
;
243 mutex_unlock(&dev
->pci_status_mutex
);
246 static int request_bar(struct pci_dev
*pdev
)
250 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
251 dev_err(&pdev
->dev
, "Missing registers BAR, aborting\n");
255 err
= pci_request_regions(pdev
, DRIVER_NAME
);
257 dev_err(&pdev
->dev
, "Couldn't get PCI resources, aborting\n");
262 static void release_bar(struct pci_dev
*pdev
)
264 pci_release_regions(pdev
);
267 static int mlx5_enable_msix(struct mlx5_core_dev
*dev
)
269 struct mlx5_priv
*priv
= &dev
->priv
;
270 struct mlx5_eq_table
*table
= &priv
->eq_table
;
271 int num_eqs
= 1 << MLX5_CAP_GEN(dev
, log_max_eq
);
275 nvec
= MLX5_CAP_GEN(dev
, num_ports
) * num_online_cpus() +
276 MLX5_EQ_VEC_COMP_BASE
;
277 nvec
= min_t(int, nvec
, num_eqs
);
278 if (nvec
<= MLX5_EQ_VEC_COMP_BASE
)
281 priv
->msix_arr
= kcalloc(nvec
, sizeof(*priv
->msix_arr
), GFP_KERNEL
);
283 priv
->irq_info
= kcalloc(nvec
, sizeof(*priv
->irq_info
), GFP_KERNEL
);
284 if (!priv
->msix_arr
|| !priv
->irq_info
)
287 for (i
= 0; i
< nvec
; i
++)
288 priv
->msix_arr
[i
].entry
= i
;
290 nvec
= pci_enable_msix_range(dev
->pdev
, priv
->msix_arr
,
291 MLX5_EQ_VEC_COMP_BASE
+ 1, nvec
);
295 table
->num_comp_vectors
= nvec
- MLX5_EQ_VEC_COMP_BASE
;
300 kfree(priv
->irq_info
);
301 kfree(priv
->msix_arr
);
305 static void mlx5_disable_msix(struct mlx5_core_dev
*dev
)
307 struct mlx5_priv
*priv
= &dev
->priv
;
309 pci_disable_msix(dev
->pdev
);
310 kfree(priv
->irq_info
);
311 kfree(priv
->msix_arr
);
314 struct mlx5_reg_host_endianess
{
320 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
323 MLX5_CAP_BITS_RW_MASK
= CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM
, 2) |
324 MLX5_DEV_CAP_FLAG_DCT
,
327 static u16
to_fw_pkey_sz(u32 size
)
343 pr_warn("invalid pkey table size %d\n", size
);
348 static int mlx5_core_get_caps_mode(struct mlx5_core_dev
*dev
,
349 enum mlx5_cap_type cap_type
,
350 enum mlx5_cap_mode cap_mode
)
352 u8 in
[MLX5_ST_SZ_BYTES(query_hca_cap_in
)];
353 int out_sz
= MLX5_ST_SZ_BYTES(query_hca_cap_out
);
354 void *out
, *hca_caps
;
355 u16 opmod
= (cap_type
<< 1) | (cap_mode
& 0x01);
358 memset(in
, 0, sizeof(in
));
359 out
= kzalloc(out_sz
, GFP_KERNEL
);
363 MLX5_SET(query_hca_cap_in
, in
, opcode
, MLX5_CMD_OP_QUERY_HCA_CAP
);
364 MLX5_SET(query_hca_cap_in
, in
, op_mod
, opmod
);
365 err
= mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, out_sz
);
369 err
= mlx5_cmd_status_to_err_v2(out
);
372 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
373 cap_type
, cap_mode
, err
);
377 hca_caps
= MLX5_ADDR_OF(query_hca_cap_out
, out
, capability
);
380 case HCA_CAP_OPMOD_GET_MAX
:
381 memcpy(dev
->hca_caps_max
[cap_type
], hca_caps
,
382 MLX5_UN_SZ_BYTES(hca_cap_union
));
384 case HCA_CAP_OPMOD_GET_CUR
:
385 memcpy(dev
->hca_caps_cur
[cap_type
], hca_caps
,
386 MLX5_UN_SZ_BYTES(hca_cap_union
));
390 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
400 int mlx5_core_get_caps(struct mlx5_core_dev
*dev
, enum mlx5_cap_type cap_type
)
404 ret
= mlx5_core_get_caps_mode(dev
, cap_type
, HCA_CAP_OPMOD_GET_CUR
);
407 return mlx5_core_get_caps_mode(dev
, cap_type
, HCA_CAP_OPMOD_GET_MAX
);
410 static int set_caps(struct mlx5_core_dev
*dev
, void *in
, int in_sz
, int opmod
)
412 u32 out
[MLX5_ST_SZ_DW(set_hca_cap_out
)];
415 memset(out
, 0, sizeof(out
));
417 MLX5_SET(set_hca_cap_in
, in
, opcode
, MLX5_CMD_OP_SET_HCA_CAP
);
418 MLX5_SET(set_hca_cap_in
, in
, op_mod
, opmod
<< 1);
419 err
= mlx5_cmd_exec(dev
, in
, in_sz
, out
, sizeof(out
));
423 err
= mlx5_cmd_status_to_err_v2(out
);
428 static int handle_hca_cap_atomic(struct mlx5_core_dev
*dev
)
432 int set_sz
= MLX5_ST_SZ_BYTES(set_hca_cap_in
);
436 if (MLX5_CAP_GEN(dev
, atomic
)) {
437 err
= mlx5_core_get_caps(dev
, MLX5_CAP_ATOMIC
);
446 supported_atomic_req_8B_endianess_mode_1
);
448 if (req_endianness
!= MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
)
451 set_ctx
= kzalloc(set_sz
, GFP_KERNEL
);
455 set_hca_cap
= MLX5_ADDR_OF(set_hca_cap_in
, set_ctx
, capability
);
457 /* Set requestor to host endianness */
458 MLX5_SET(atomic_caps
, set_hca_cap
, atomic_req_8B_endianess_mode
,
459 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS
);
461 err
= set_caps(dev
, set_ctx
, set_sz
, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC
);
467 static int handle_hca_cap(struct mlx5_core_dev
*dev
)
469 void *set_ctx
= NULL
;
470 struct mlx5_profile
*prof
= dev
->profile
;
472 int set_sz
= MLX5_ST_SZ_BYTES(set_hca_cap_in
);
475 set_ctx
= kzalloc(set_sz
, GFP_KERNEL
);
479 err
= mlx5_core_get_caps(dev
, MLX5_CAP_GENERAL
);
483 set_hca_cap
= MLX5_ADDR_OF(set_hca_cap_in
, set_ctx
,
485 memcpy(set_hca_cap
, dev
->hca_caps_cur
[MLX5_CAP_GENERAL
],
486 MLX5_ST_SZ_BYTES(cmd_hca_cap
));
488 mlx5_core_dbg(dev
, "Current Pkey table size %d Setting new size %d\n",
489 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev
, pkey_table_size
)),
491 /* we limit the size of the pkey table to 128 entries for now */
492 MLX5_SET(cmd_hca_cap
, set_hca_cap
, pkey_table_size
,
495 if (prof
->mask
& MLX5_PROF_MASK_QP_SIZE
)
496 MLX5_SET(cmd_hca_cap
, set_hca_cap
, log_max_qp
,
499 /* disable cmdif checksum */
500 MLX5_SET(cmd_hca_cap
, set_hca_cap
, cmdif_checksum
, 0);
502 MLX5_SET(cmd_hca_cap
, set_hca_cap
, log_uar_page_sz
, PAGE_SHIFT
- 12);
504 err
= set_caps(dev
, set_ctx
, set_sz
,
505 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE
);
512 static int set_hca_ctrl(struct mlx5_core_dev
*dev
)
514 struct mlx5_reg_host_endianess he_in
;
515 struct mlx5_reg_host_endianess he_out
;
518 if (!mlx5_core_is_pf(dev
))
521 memset(&he_in
, 0, sizeof(he_in
));
522 he_in
.he
= MLX5_SET_HOST_ENDIANNESS
;
523 err
= mlx5_core_access_reg(dev
, &he_in
, sizeof(he_in
),
524 &he_out
, sizeof(he_out
),
525 MLX5_REG_HOST_ENDIANNESS
, 0, 1);
529 int mlx5_core_enable_hca(struct mlx5_core_dev
*dev
, u16 func_id
)
531 u32 out
[MLX5_ST_SZ_DW(enable_hca_out
)];
532 u32 in
[MLX5_ST_SZ_DW(enable_hca_in
)];
535 memset(in
, 0, sizeof(in
));
536 MLX5_SET(enable_hca_in
, in
, opcode
, MLX5_CMD_OP_ENABLE_HCA
);
537 MLX5_SET(enable_hca_in
, in
, function_id
, func_id
);
538 memset(out
, 0, sizeof(out
));
540 err
= mlx5_cmd_exec(dev
, &in
, sizeof(in
), &out
, sizeof(out
));
544 return mlx5_cmd_status_to_err_v2(out
);
547 int mlx5_core_disable_hca(struct mlx5_core_dev
*dev
, u16 func_id
)
549 u32 out
[MLX5_ST_SZ_DW(disable_hca_out
)];
550 u32 in
[MLX5_ST_SZ_DW(disable_hca_in
)];
553 memset(in
, 0, sizeof(in
));
554 MLX5_SET(disable_hca_in
, in
, opcode
, MLX5_CMD_OP_DISABLE_HCA
);
555 MLX5_SET(disable_hca_in
, in
, function_id
, func_id
);
556 memset(out
, 0, sizeof(out
));
557 err
= mlx5_cmd_exec(dev
, in
, sizeof(in
), out
, sizeof(out
));
561 return mlx5_cmd_status_to_err_v2(out
);
564 cycle_t
mlx5_read_internal_timer(struct mlx5_core_dev
*dev
)
566 u32 timer_h
, timer_h1
, timer_l
;
568 timer_h
= ioread32be(&dev
->iseg
->internal_timer_h
);
569 timer_l
= ioread32be(&dev
->iseg
->internal_timer_l
);
570 timer_h1
= ioread32be(&dev
->iseg
->internal_timer_h
);
571 if (timer_h
!= timer_h1
) /* wrap around */
572 timer_l
= ioread32be(&dev
->iseg
->internal_timer_l
);
574 return (cycle_t
)timer_l
| (cycle_t
)timer_h1
<< 32;
577 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev
*mdev
, int i
)
579 struct mlx5_priv
*priv
= &mdev
->priv
;
580 struct msix_entry
*msix
= priv
->msix_arr
;
581 int irq
= msix
[i
+ MLX5_EQ_VEC_COMP_BASE
].vector
;
582 int numa_node
= priv
->numa_node
;
585 if (!zalloc_cpumask_var(&priv
->irq_info
[i
].mask
, GFP_KERNEL
)) {
586 mlx5_core_warn(mdev
, "zalloc_cpumask_var failed");
590 cpumask_set_cpu(cpumask_local_spread(i
, numa_node
),
591 priv
->irq_info
[i
].mask
);
593 err
= irq_set_affinity_hint(irq
, priv
->irq_info
[i
].mask
);
595 mlx5_core_warn(mdev
, "irq_set_affinity_hint failed,irq 0x%.4x",
603 free_cpumask_var(priv
->irq_info
[i
].mask
);
607 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev
*mdev
, int i
)
609 struct mlx5_priv
*priv
= &mdev
->priv
;
610 struct msix_entry
*msix
= priv
->msix_arr
;
611 int irq
= msix
[i
+ MLX5_EQ_VEC_COMP_BASE
].vector
;
613 irq_set_affinity_hint(irq
, NULL
);
614 free_cpumask_var(priv
->irq_info
[i
].mask
);
617 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev
*mdev
)
622 for (i
= 0; i
< mdev
->priv
.eq_table
.num_comp_vectors
; i
++) {
623 err
= mlx5_irq_set_affinity_hint(mdev
, i
);
631 for (i
--; i
>= 0; i
--)
632 mlx5_irq_clear_affinity_hint(mdev
, i
);
637 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev
*mdev
)
641 for (i
= 0; i
< mdev
->priv
.eq_table
.num_comp_vectors
; i
++)
642 mlx5_irq_clear_affinity_hint(mdev
, i
);
645 int mlx5_vector2eqn(struct mlx5_core_dev
*dev
, int vector
, int *eqn
,
648 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
649 struct mlx5_eq
*eq
, *n
;
652 spin_lock(&table
->lock
);
653 list_for_each_entry_safe(eq
, n
, &table
->comp_eqs_list
, list
) {
654 if (eq
->index
== vector
) {
661 spin_unlock(&table
->lock
);
665 EXPORT_SYMBOL(mlx5_vector2eqn
);
667 struct mlx5_eq
*mlx5_eqn2eq(struct mlx5_core_dev
*dev
, int eqn
)
669 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
672 spin_lock(&table
->lock
);
673 list_for_each_entry(eq
, &table
->comp_eqs_list
, list
)
674 if (eq
->eqn
== eqn
) {
675 spin_unlock(&table
->lock
);
679 spin_unlock(&table
->lock
);
681 return ERR_PTR(-ENOENT
);
684 static void free_comp_eqs(struct mlx5_core_dev
*dev
)
686 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
687 struct mlx5_eq
*eq
, *n
;
689 #ifdef CONFIG_RFS_ACCEL
691 free_irq_cpu_rmap(dev
->rmap
);
695 spin_lock(&table
->lock
);
696 list_for_each_entry_safe(eq
, n
, &table
->comp_eqs_list
, list
) {
698 spin_unlock(&table
->lock
);
699 if (mlx5_destroy_unmap_eq(dev
, eq
))
700 mlx5_core_warn(dev
, "failed to destroy EQ 0x%x\n",
703 spin_lock(&table
->lock
);
705 spin_unlock(&table
->lock
);
708 static int alloc_comp_eqs(struct mlx5_core_dev
*dev
)
710 struct mlx5_eq_table
*table
= &dev
->priv
.eq_table
;
711 char name
[MLX5_MAX_IRQ_NAME
];
718 INIT_LIST_HEAD(&table
->comp_eqs_list
);
719 ncomp_vec
= table
->num_comp_vectors
;
720 nent
= MLX5_COMP_EQ_SIZE
;
721 #ifdef CONFIG_RFS_ACCEL
722 dev
->rmap
= alloc_irq_cpu_rmap(ncomp_vec
);
726 for (i
= 0; i
< ncomp_vec
; i
++) {
727 eq
= kzalloc(sizeof(*eq
), GFP_KERNEL
);
733 #ifdef CONFIG_RFS_ACCEL
734 irq_cpu_rmap_add(dev
->rmap
,
735 dev
->priv
.msix_arr
[i
+ MLX5_EQ_VEC_COMP_BASE
].vector
);
737 snprintf(name
, MLX5_MAX_IRQ_NAME
, "mlx5_comp%d", i
);
738 err
= mlx5_create_map_eq(dev
, eq
,
739 i
+ MLX5_EQ_VEC_COMP_BASE
, nent
, 0,
740 name
, &dev
->priv
.uuari
.uars
[0]);
745 mlx5_core_dbg(dev
, "allocated completion EQN %d\n", eq
->eqn
);
747 spin_lock(&table
->lock
);
748 list_add_tail(&eq
->list
, &table
->comp_eqs_list
);
749 spin_unlock(&table
->lock
);
759 static int mlx5_core_set_issi(struct mlx5_core_dev
*dev
)
761 u32 query_in
[MLX5_ST_SZ_DW(query_issi_in
)];
762 u32 query_out
[MLX5_ST_SZ_DW(query_issi_out
)];
763 u32 set_in
[MLX5_ST_SZ_DW(set_issi_in
)];
764 u32 set_out
[MLX5_ST_SZ_DW(set_issi_out
)];
768 memset(query_in
, 0, sizeof(query_in
));
769 memset(query_out
, 0, sizeof(query_out
));
771 MLX5_SET(query_issi_in
, query_in
, opcode
, MLX5_CMD_OP_QUERY_ISSI
);
773 err
= mlx5_cmd_exec_check_status(dev
, query_in
, sizeof(query_in
),
774 query_out
, sizeof(query_out
));
776 if (((struct mlx5_outbox_hdr
*)query_out
)->status
==
777 MLX5_CMD_STAT_BAD_OP_ERR
) {
778 pr_debug("Only ISSI 0 is supported\n");
782 pr_err("failed to query ISSI\n");
786 sup_issi
= MLX5_GET(query_issi_out
, query_out
, supported_issi_dw0
);
788 if (sup_issi
& (1 << 1)) {
789 memset(set_in
, 0, sizeof(set_in
));
790 memset(set_out
, 0, sizeof(set_out
));
792 MLX5_SET(set_issi_in
, set_in
, opcode
, MLX5_CMD_OP_SET_ISSI
);
793 MLX5_SET(set_issi_in
, set_in
, current_issi
, 1);
795 err
= mlx5_cmd_exec_check_status(dev
, set_in
, sizeof(set_in
),
796 set_out
, sizeof(set_out
));
798 pr_err("failed to set ISSI=1\n");
805 } else if (sup_issi
& (1 << 0) || !sup_issi
) {
812 static void mlx5_add_device(struct mlx5_interface
*intf
, struct mlx5_priv
*priv
)
814 struct mlx5_device_context
*dev_ctx
;
815 struct mlx5_core_dev
*dev
= container_of(priv
, struct mlx5_core_dev
, priv
);
817 dev_ctx
= kmalloc(sizeof(*dev_ctx
), GFP_KERNEL
);
821 dev_ctx
->intf
= intf
;
822 dev_ctx
->context
= intf
->add(dev
);
824 if (dev_ctx
->context
) {
825 spin_lock_irq(&priv
->ctx_lock
);
826 list_add_tail(&dev_ctx
->list
, &priv
->ctx_list
);
827 spin_unlock_irq(&priv
->ctx_lock
);
833 static void mlx5_remove_device(struct mlx5_interface
*intf
, struct mlx5_priv
*priv
)
835 struct mlx5_device_context
*dev_ctx
;
836 struct mlx5_core_dev
*dev
= container_of(priv
, struct mlx5_core_dev
, priv
);
838 list_for_each_entry(dev_ctx
, &priv
->ctx_list
, list
)
839 if (dev_ctx
->intf
== intf
) {
840 spin_lock_irq(&priv
->ctx_lock
);
841 list_del(&dev_ctx
->list
);
842 spin_unlock_irq(&priv
->ctx_lock
);
844 intf
->remove(dev
, dev_ctx
->context
);
850 static int mlx5_register_device(struct mlx5_core_dev
*dev
)
852 struct mlx5_priv
*priv
= &dev
->priv
;
853 struct mlx5_interface
*intf
;
855 mutex_lock(&intf_mutex
);
856 list_add_tail(&priv
->dev_list
, &dev_list
);
857 list_for_each_entry(intf
, &intf_list
, list
)
858 mlx5_add_device(intf
, priv
);
859 mutex_unlock(&intf_mutex
);
864 static void mlx5_unregister_device(struct mlx5_core_dev
*dev
)
866 struct mlx5_priv
*priv
= &dev
->priv
;
867 struct mlx5_interface
*intf
;
869 mutex_lock(&intf_mutex
);
870 list_for_each_entry(intf
, &intf_list
, list
)
871 mlx5_remove_device(intf
, priv
);
872 list_del(&priv
->dev_list
);
873 mutex_unlock(&intf_mutex
);
876 int mlx5_register_interface(struct mlx5_interface
*intf
)
878 struct mlx5_priv
*priv
;
880 if (!intf
->add
|| !intf
->remove
)
883 mutex_lock(&intf_mutex
);
884 list_add_tail(&intf
->list
, &intf_list
);
885 list_for_each_entry(priv
, &dev_list
, dev_list
)
886 mlx5_add_device(intf
, priv
);
887 mutex_unlock(&intf_mutex
);
891 EXPORT_SYMBOL(mlx5_register_interface
);
893 void mlx5_unregister_interface(struct mlx5_interface
*intf
)
895 struct mlx5_priv
*priv
;
897 mutex_lock(&intf_mutex
);
898 list_for_each_entry(priv
, &dev_list
, dev_list
)
899 mlx5_remove_device(intf
, priv
);
900 list_del(&intf
->list
);
901 mutex_unlock(&intf_mutex
);
903 EXPORT_SYMBOL(mlx5_unregister_interface
);
905 void *mlx5_get_protocol_dev(struct mlx5_core_dev
*mdev
, int protocol
)
907 struct mlx5_priv
*priv
= &mdev
->priv
;
908 struct mlx5_device_context
*dev_ctx
;
912 spin_lock_irqsave(&priv
->ctx_lock
, flags
);
914 list_for_each_entry(dev_ctx
, &mdev
->priv
.ctx_list
, list
)
915 if ((dev_ctx
->intf
->protocol
== protocol
) &&
916 dev_ctx
->intf
->get_dev
) {
917 result
= dev_ctx
->intf
->get_dev(dev_ctx
->context
);
921 spin_unlock_irqrestore(&priv
->ctx_lock
, flags
);
925 EXPORT_SYMBOL(mlx5_get_protocol_dev
);
927 static int mlx5_pci_init(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
)
929 struct pci_dev
*pdev
= dev
->pdev
;
932 pci_set_drvdata(dev
->pdev
, dev
);
933 strncpy(priv
->name
, dev_name(&pdev
->dev
), MLX5_MAX_NAME_LEN
);
934 priv
->name
[MLX5_MAX_NAME_LEN
- 1] = 0;
936 mutex_init(&priv
->pgdir_mutex
);
937 INIT_LIST_HEAD(&priv
->pgdir_list
);
938 spin_lock_init(&priv
->mkey_lock
);
940 mutex_init(&priv
->alloc_mutex
);
942 priv
->numa_node
= dev_to_node(&dev
->pdev
->dev
);
944 priv
->dbg_root
= debugfs_create_dir(dev_name(&pdev
->dev
), mlx5_debugfs_root
);
948 err
= mlx5_pci_enable_device(dev
);
950 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
954 err
= request_bar(pdev
);
956 dev_err(&pdev
->dev
, "error requesting BARs, aborting\n");
960 pci_set_master(pdev
);
962 err
= set_dma_caps(pdev
);
964 dev_err(&pdev
->dev
, "Failed setting DMA capabilities mask, aborting\n");
968 dev
->iseg_base
= pci_resource_start(dev
->pdev
, 0);
969 dev
->iseg
= ioremap(dev
->iseg_base
, sizeof(*dev
->iseg
));
972 dev_err(&pdev
->dev
, "Failed mapping initialization segment, aborting\n");
979 pci_clear_master(dev
->pdev
);
980 release_bar(dev
->pdev
);
982 mlx5_pci_disable_device(dev
);
985 debugfs_remove(priv
->dbg_root
);
989 static void mlx5_pci_close(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
)
992 pci_clear_master(dev
->pdev
);
993 release_bar(dev
->pdev
);
994 mlx5_pci_disable_device(dev
);
995 debugfs_remove(priv
->dbg_root
);
998 #define MLX5_IB_MOD "mlx5_ib"
999 static int mlx5_load_one(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
)
1001 struct pci_dev
*pdev
= dev
->pdev
;
1004 mutex_lock(&dev
->intf_state_mutex
);
1005 if (test_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
)) {
1006 dev_warn(&dev
->pdev
->dev
, "%s: interface is up, NOP\n",
1011 dev_info(&pdev
->dev
, "firmware version: %d.%d.%d\n", fw_rev_maj(dev
),
1012 fw_rev_min(dev
), fw_rev_sub(dev
));
1014 /* on load removing any previous indication of internal error, device is
1017 dev
->state
= MLX5_DEVICE_STATE_UP
;
1019 err
= mlx5_cmd_init(dev
);
1021 dev_err(&pdev
->dev
, "Failed initializing command interface, aborting\n");
1025 err
= wait_fw_init(dev
, FW_INIT_TIMEOUT_MILI
);
1027 dev_err(&dev
->pdev
->dev
, "Firmware over %d MS in initializing state, aborting\n",
1028 FW_INIT_TIMEOUT_MILI
);
1032 mlx5_pagealloc_init(dev
);
1034 err
= mlx5_core_enable_hca(dev
, 0);
1036 dev_err(&pdev
->dev
, "enable hca failed\n");
1037 goto err_pagealloc_cleanup
;
1040 err
= mlx5_core_set_issi(dev
);
1042 dev_err(&pdev
->dev
, "failed to set issi\n");
1043 goto err_disable_hca
;
1046 err
= mlx5_satisfy_startup_pages(dev
, 1);
1048 dev_err(&pdev
->dev
, "failed to allocate boot pages\n");
1049 goto err_disable_hca
;
1052 err
= set_hca_ctrl(dev
);
1054 dev_err(&pdev
->dev
, "set_hca_ctrl failed\n");
1055 goto reclaim_boot_pages
;
1058 err
= handle_hca_cap(dev
);
1060 dev_err(&pdev
->dev
, "handle_hca_cap failed\n");
1061 goto reclaim_boot_pages
;
1064 err
= handle_hca_cap_atomic(dev
);
1066 dev_err(&pdev
->dev
, "handle_hca_cap_atomic failed\n");
1067 goto reclaim_boot_pages
;
1070 err
= mlx5_satisfy_startup_pages(dev
, 0);
1072 dev_err(&pdev
->dev
, "failed to allocate init pages\n");
1073 goto reclaim_boot_pages
;
1076 err
= mlx5_pagealloc_start(dev
);
1078 dev_err(&pdev
->dev
, "mlx5_pagealloc_start failed\n");
1079 goto reclaim_boot_pages
;
1082 err
= mlx5_cmd_init_hca(dev
);
1084 dev_err(&pdev
->dev
, "init hca failed\n");
1085 goto err_pagealloc_stop
;
1088 mlx5_start_health_poll(dev
);
1090 err
= mlx5_query_hca_caps(dev
);
1092 dev_err(&pdev
->dev
, "query hca failed\n");
1096 err
= mlx5_query_board_id(dev
);
1098 dev_err(&pdev
->dev
, "query board id failed\n");
1102 err
= mlx5_enable_msix(dev
);
1104 dev_err(&pdev
->dev
, "enable msix failed\n");
1108 err
= mlx5_eq_init(dev
);
1110 dev_err(&pdev
->dev
, "failed to initialize eq\n");
1114 err
= mlx5_alloc_uuars(dev
, &priv
->uuari
);
1116 dev_err(&pdev
->dev
, "Failed allocating uar, aborting\n");
1117 goto err_eq_cleanup
;
1120 err
= mlx5_start_eqs(dev
);
1122 dev_err(&pdev
->dev
, "Failed to start pages and async EQs\n");
1126 err
= alloc_comp_eqs(dev
);
1128 dev_err(&pdev
->dev
, "Failed to alloc completion EQs\n");
1132 err
= mlx5_irq_set_affinity_hints(dev
);
1134 dev_err(&pdev
->dev
, "Failed to alloc affinity hint cpumask\n");
1136 MLX5_INIT_DOORBELL_LOCK(&priv
->cq_uar_lock
);
1138 mlx5_init_cq_table(dev
);
1139 mlx5_init_qp_table(dev
);
1140 mlx5_init_srq_table(dev
);
1141 mlx5_init_mkey_table(dev
);
1143 err
= mlx5_init_fs(dev
);
1145 dev_err(&pdev
->dev
, "Failed to init flow steering\n");
1149 err
= mlx5_init_rl_table(dev
);
1151 dev_err(&pdev
->dev
, "Failed to init rate limiting\n");
1155 #ifdef CONFIG_MLX5_CORE_EN
1156 err
= mlx5_eswitch_init(dev
);
1158 dev_err(&pdev
->dev
, "eswitch init failed %d\n", err
);
1163 err
= mlx5_sriov_init(dev
);
1165 dev_err(&pdev
->dev
, "sriov init failed %d\n", err
);
1169 err
= mlx5_register_device(dev
);
1171 dev_err(&pdev
->dev
, "mlx5_register_device failed %d\n", err
);
1175 err
= request_module_nowait(MLX5_IB_MOD
);
1177 pr_info("failed request module on %s\n", MLX5_IB_MOD
);
1179 clear_bit(MLX5_INTERFACE_STATE_DOWN
, &dev
->intf_state
);
1180 set_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
);
1182 mutex_unlock(&dev
->intf_state_mutex
);
1187 if (mlx5_sriov_cleanup(dev
))
1188 dev_err(&dev
->pdev
->dev
, "sriov cleanup failed\n");
1190 #ifdef CONFIG_MLX5_CORE_EN
1191 mlx5_eswitch_cleanup(dev
->priv
.eswitch
);
1194 mlx5_cleanup_rl_table(dev
);
1196 mlx5_cleanup_fs(dev
);
1198 mlx5_cleanup_mkey_table(dev
);
1199 mlx5_cleanup_srq_table(dev
);
1200 mlx5_cleanup_qp_table(dev
);
1201 mlx5_cleanup_cq_table(dev
);
1202 mlx5_irq_clear_affinity_hints(dev
);
1209 mlx5_free_uuars(dev
, &priv
->uuari
);
1212 mlx5_eq_cleanup(dev
);
1215 mlx5_disable_msix(dev
);
1218 mlx5_stop_health_poll(dev
);
1219 if (mlx5_cmd_teardown_hca(dev
)) {
1220 dev_err(&dev
->pdev
->dev
, "tear_down_hca failed, skip cleanup\n");
1225 mlx5_pagealloc_stop(dev
);
1228 mlx5_reclaim_startup_pages(dev
);
1231 mlx5_core_disable_hca(dev
, 0);
1233 err_pagealloc_cleanup
:
1234 mlx5_pagealloc_cleanup(dev
);
1235 mlx5_cmd_cleanup(dev
);
1238 dev
->state
= MLX5_DEVICE_STATE_INTERNAL_ERROR
;
1239 mutex_unlock(&dev
->intf_state_mutex
);
1244 static int mlx5_unload_one(struct mlx5_core_dev
*dev
, struct mlx5_priv
*priv
)
1248 err
= mlx5_sriov_cleanup(dev
);
1250 dev_warn(&dev
->pdev
->dev
, "%s: sriov cleanup failed - abort\n",
1255 mutex_lock(&dev
->intf_state_mutex
);
1256 if (test_bit(MLX5_INTERFACE_STATE_DOWN
, &dev
->intf_state
)) {
1257 dev_warn(&dev
->pdev
->dev
, "%s: interface is down, NOP\n",
1261 mlx5_unregister_device(dev
);
1262 #ifdef CONFIG_MLX5_CORE_EN
1263 mlx5_eswitch_cleanup(dev
->priv
.eswitch
);
1266 mlx5_cleanup_rl_table(dev
);
1267 mlx5_cleanup_fs(dev
);
1268 mlx5_cleanup_mkey_table(dev
);
1269 mlx5_cleanup_srq_table(dev
);
1270 mlx5_cleanup_qp_table(dev
);
1271 mlx5_cleanup_cq_table(dev
);
1272 mlx5_irq_clear_affinity_hints(dev
);
1275 mlx5_free_uuars(dev
, &priv
->uuari
);
1276 mlx5_eq_cleanup(dev
);
1277 mlx5_disable_msix(dev
);
1278 mlx5_stop_health_poll(dev
);
1279 err
= mlx5_cmd_teardown_hca(dev
);
1281 dev_err(&dev
->pdev
->dev
, "tear_down_hca failed, skip cleanup\n");
1284 mlx5_pagealloc_stop(dev
);
1285 mlx5_reclaim_startup_pages(dev
);
1286 mlx5_core_disable_hca(dev
, 0);
1287 mlx5_pagealloc_cleanup(dev
);
1288 mlx5_cmd_cleanup(dev
);
1291 clear_bit(MLX5_INTERFACE_STATE_UP
, &dev
->intf_state
);
1292 set_bit(MLX5_INTERFACE_STATE_DOWN
, &dev
->intf_state
);
1293 mutex_unlock(&dev
->intf_state_mutex
);
1297 void mlx5_core_event(struct mlx5_core_dev
*dev
, enum mlx5_dev_event event
,
1298 unsigned long param
)
1300 struct mlx5_priv
*priv
= &dev
->priv
;
1301 struct mlx5_device_context
*dev_ctx
;
1302 unsigned long flags
;
1304 spin_lock_irqsave(&priv
->ctx_lock
, flags
);
1306 list_for_each_entry(dev_ctx
, &priv
->ctx_list
, list
)
1307 if (dev_ctx
->intf
->event
)
1308 dev_ctx
->intf
->event(dev
, dev_ctx
->context
, event
, param
);
1310 spin_unlock_irqrestore(&priv
->ctx_lock
, flags
);
1313 struct mlx5_core_event_handler
{
1314 void (*event
)(struct mlx5_core_dev
*dev
,
1315 enum mlx5_dev_event event
,
1319 static const struct devlink_ops mlx5_devlink_ops
= {
1320 #ifdef CONFIG_MLX5_CORE_EN
1321 .eswitch_mode_set
= mlx5_devlink_eswitch_mode_set
,
1322 .eswitch_mode_get
= mlx5_devlink_eswitch_mode_get
,
1326 static int init_one(struct pci_dev
*pdev
,
1327 const struct pci_device_id
*id
)
1329 struct mlx5_core_dev
*dev
;
1330 struct devlink
*devlink
;
1331 struct mlx5_priv
*priv
;
1334 devlink
= devlink_alloc(&mlx5_devlink_ops
, sizeof(*dev
));
1336 dev_err(&pdev
->dev
, "kzalloc failed\n");
1340 dev
= devlink_priv(devlink
);
1342 priv
->pci_dev_data
= id
->driver_data
;
1344 pci_set_drvdata(pdev
, dev
);
1346 if (prof_sel
< 0 || prof_sel
>= ARRAY_SIZE(profile
)) {
1347 pr_warn("selected profile out of range, selecting default (%d)\n",
1349 prof_sel
= MLX5_DEFAULT_PROF
;
1351 dev
->profile
= &profile
[prof_sel
];
1353 dev
->event
= mlx5_core_event
;
1355 INIT_LIST_HEAD(&priv
->ctx_list
);
1356 spin_lock_init(&priv
->ctx_lock
);
1357 mutex_init(&dev
->pci_status_mutex
);
1358 mutex_init(&dev
->intf_state_mutex
);
1359 err
= mlx5_pci_init(dev
, priv
);
1361 dev_err(&pdev
->dev
, "mlx5_pci_init failed with error code %d\n", err
);
1365 err
= mlx5_health_init(dev
);
1367 dev_err(&pdev
->dev
, "mlx5_health_init failed with error code %d\n", err
);
1371 err
= mlx5_load_one(dev
, priv
);
1373 dev_err(&pdev
->dev
, "mlx5_load_one failed with error code %d\n", err
);
1377 err
= devlink_register(devlink
, &pdev
->dev
);
1384 mlx5_unload_one(dev
, priv
);
1386 mlx5_health_cleanup(dev
);
1388 mlx5_pci_close(dev
, priv
);
1390 pci_set_drvdata(pdev
, NULL
);
1391 devlink_free(devlink
);
1396 static void remove_one(struct pci_dev
*pdev
)
1398 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1399 struct devlink
*devlink
= priv_to_devlink(dev
);
1400 struct mlx5_priv
*priv
= &dev
->priv
;
1402 devlink_unregister(devlink
);
1403 if (mlx5_unload_one(dev
, priv
)) {
1404 dev_err(&dev
->pdev
->dev
, "mlx5_unload_one failed\n");
1405 mlx5_health_cleanup(dev
);
1408 mlx5_health_cleanup(dev
);
1409 mlx5_pci_close(dev
, priv
);
1410 pci_set_drvdata(pdev
, NULL
);
1411 devlink_free(devlink
);
1414 static pci_ers_result_t
mlx5_pci_err_detected(struct pci_dev
*pdev
,
1415 pci_channel_state_t state
)
1417 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1418 struct mlx5_priv
*priv
= &dev
->priv
;
1420 dev_info(&pdev
->dev
, "%s was called\n", __func__
);
1421 mlx5_enter_error_state(dev
);
1422 mlx5_unload_one(dev
, priv
);
1423 pci_save_state(pdev
);
1424 mlx5_pci_disable_device(dev
);
1425 return state
== pci_channel_io_perm_failure
?
1426 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
1429 /* wait for the device to show vital signs by waiting
1430 * for the health counter to start counting.
1432 static int wait_vital(struct pci_dev
*pdev
)
1434 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1435 struct mlx5_core_health
*health
= &dev
->priv
.health
;
1436 const int niter
= 100;
1441 for (i
= 0; i
< niter
; i
++) {
1442 count
= ioread32be(health
->health_counter
);
1443 if (count
&& count
!= 0xffffffff) {
1444 if (last_count
&& last_count
!= count
) {
1445 dev_info(&pdev
->dev
, "Counter value 0x%x after %d iterations\n", count
, i
);
1456 static pci_ers_result_t
mlx5_pci_slot_reset(struct pci_dev
*pdev
)
1458 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1461 dev_info(&pdev
->dev
, "%s was called\n", __func__
);
1463 err
= mlx5_pci_enable_device(dev
);
1465 dev_err(&pdev
->dev
, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1467 return PCI_ERS_RESULT_DISCONNECT
;
1470 pci_set_master(pdev
);
1471 pci_restore_state(pdev
);
1473 if (wait_vital(pdev
)) {
1474 dev_err(&pdev
->dev
, "%s: wait_vital timed out\n", __func__
);
1475 return PCI_ERS_RESULT_DISCONNECT
;
1478 return PCI_ERS_RESULT_RECOVERED
;
1481 void mlx5_disable_device(struct mlx5_core_dev
*dev
)
1483 mlx5_pci_err_detected(dev
->pdev
, 0);
1486 static void mlx5_pci_resume(struct pci_dev
*pdev
)
1488 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1489 struct mlx5_priv
*priv
= &dev
->priv
;
1492 dev_info(&pdev
->dev
, "%s was called\n", __func__
);
1494 err
= mlx5_load_one(dev
, priv
);
1496 dev_err(&pdev
->dev
, "%s: mlx5_load_one failed with error code: %d\n"
1499 dev_info(&pdev
->dev
, "%s: device recovered\n", __func__
);
1502 static const struct pci_error_handlers mlx5_err_handler
= {
1503 .error_detected
= mlx5_pci_err_detected
,
1504 .slot_reset
= mlx5_pci_slot_reset
,
1505 .resume
= mlx5_pci_resume
1508 static void shutdown(struct pci_dev
*pdev
)
1510 struct mlx5_core_dev
*dev
= pci_get_drvdata(pdev
);
1511 struct mlx5_priv
*priv
= &dev
->priv
;
1513 dev_info(&pdev
->dev
, "Shutdown was called\n");
1514 /* Notify mlx5 clients that the kernel is being shut down */
1515 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN
, &dev
->intf_state
);
1516 mlx5_unload_one(dev
, priv
);
1517 mlx5_pci_disable_device(dev
);
1520 static const struct pci_device_id mlx5_core_pci_table
[] = {
1521 { PCI_VDEVICE(MELLANOX
, 0x1011) }, /* Connect-IB */
1522 { PCI_VDEVICE(MELLANOX
, 0x1012), MLX5_PCI_DEV_IS_VF
}, /* Connect-IB VF */
1523 { PCI_VDEVICE(MELLANOX
, 0x1013) }, /* ConnectX-4 */
1524 { PCI_VDEVICE(MELLANOX
, 0x1014), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-4 VF */
1525 { PCI_VDEVICE(MELLANOX
, 0x1015) }, /* ConnectX-4LX */
1526 { PCI_VDEVICE(MELLANOX
, 0x1016), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-4LX VF */
1527 { PCI_VDEVICE(MELLANOX
, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
1528 { PCI_VDEVICE(MELLANOX
, 0x1018), MLX5_PCI_DEV_IS_VF
}, /* ConnectX-5 VF */
1529 { PCI_VDEVICE(MELLANOX
, 0x1019) }, /* ConnectX-5, PCIe 4.0 */
1533 MODULE_DEVICE_TABLE(pci
, mlx5_core_pci_table
);
1535 static struct pci_driver mlx5_core_driver
= {
1536 .name
= DRIVER_NAME
,
1537 .id_table
= mlx5_core_pci_table
,
1539 .remove
= remove_one
,
1540 .shutdown
= shutdown
,
1541 .err_handler
= &mlx5_err_handler
,
1542 .sriov_configure
= mlx5_core_sriov_configure
,
1545 static int __init
init(void)
1549 mlx5_register_debugfs();
1551 err
= pci_register_driver(&mlx5_core_driver
);
1555 #ifdef CONFIG_MLX5_CORE_EN
1562 mlx5_unregister_debugfs();
1566 static void __exit
cleanup(void)
1568 #ifdef CONFIG_MLX5_CORE_EN
1571 pci_unregister_driver(&mlx5_core_driver
);
1572 mlx5_unregister_debugfs();
1576 module_exit(cleanup
);