drivers/net/ethernet/mellanox/mlx5/core/main.c

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <asm-generic/kmap_types.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #include <linux/io-mapping.h>
  41 #include <linux/mlx5/driver.h>
  42 #include <linux/mlx5/cq.h>
  43 #include <linux/mlx5/qp.h>
  44 #include <linux/mlx5/srq.h>
  45 #include <linux/debugfs.h>
  46 #include <linux/kmod.h>
  47 #include <linux/mlx5/mlx5_ifc.h>
  48 #include "mlx5_core.h"
  49
  50 #define DRIVER_NAME "mlx5_core"
  51 #define DRIVER_VERSION "2.2-1"
  52 #define DRIVER_RELDATE  "Feb 2014"
  53
  54 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  55 MODULE_DESCRIPTION("Mellanox ConnectX-IB HCA core library");
  56 MODULE_LICENSE("Dual BSD/GPL");
  57 MODULE_VERSION(DRIVER_VERSION);
  58
  59 int mlx5_core_debug_mask;
  60 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
  61 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
  62
  63 #define MLX5_DEFAULT_PROF       2
  64 static int prof_sel = MLX5_DEFAULT_PROF;
  65 module_param_named(prof_sel, prof_sel, int, 0444);
  66 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
  67
  68 struct workqueue_struct *mlx5_core_wq;
  69 static LIST_HEAD(intf_list);
  70 static LIST_HEAD(dev_list);
  71 static DEFINE_MUTEX(intf_mutex);
  72
  73 struct mlx5_device_context {
  74         struct list_head        list;
  75         struct mlx5_interface  *intf;
  76         void                   *context;
  77 };
  78
  79 static struct mlx5_profile profile[] = {
  80         [0] = {
  81                 .mask           = 0,
  82         },
  83         [1] = {
  84                 .mask           = MLX5_PROF_MASK_QP_SIZE,
  85                 .log_max_qp     = 12,
  86         },
  87         [2] = {
  88                 .mask           = MLX5_PROF_MASK_QP_SIZE |
  89                                   MLX5_PROF_MASK_MR_CACHE,
  90                 .log_max_qp     = 17,
  91                 .mr_cache[0]    = {
  92                         .size   = 500,
  93                         .limit  = 250
  94                 },
  95                 .mr_cache[1]    = {
  96                         .size   = 500,
  97                         .limit  = 250
  98                 },
  99                 .mr_cache[2]    = {
 100                         .size   = 500,
 101                         .limit  = 250
 102                 },
 103                 .mr_cache[3]    = {
 104                         .size   = 500,
 105                         .limit  = 250
 106                 },
 107                 .mr_cache[4]    = {
 108                         .size   = 500,
 109                         .limit  = 250
 110                 },
 111                 .mr_cache[5]    = {
 112                         .size   = 500,
 113                         .limit  = 250
 114                 },
 115                 .mr_cache[6]    = {
 116                         .size   = 500,
 117                         .limit  = 250
 118                 },
 119                 .mr_cache[7]    = {
 120                         .size   = 500,
 121                         .limit  = 250
 122                 },
 123                 .mr_cache[8]    = {
 124                         .size   = 500,
 125                         .limit  = 250
 126                 },
 127                 .mr_cache[9]    = {
 128                         .size   = 500,
 129                         .limit  = 250
 130                 },
 131                 .mr_cache[10]   = {
 132                         .size   = 500,
 133                         .limit  = 250
 134                 },
 135                 .mr_cache[11]   = {
 136                         .size   = 500,
 137                         .limit  = 250
 138                 },
 139                 .mr_cache[12]   = {
 140                         .size   = 64,
 141                         .limit  = 32
 142                 },
 143                 .mr_cache[13]   = {
 144                         .size   = 32,
 145                         .limit  = 16
 146                 },
 147                 .mr_cache[14]   = {
 148                         .size   = 16,
 149                         .limit  = 8
 150                 },
 151                 .mr_cache[15]   = {
 152                         .size   = 8,
 153                         .limit  = 4
 154                 },
 155         },
 156 };
 157
 158 static int set_dma_caps(struct pci_dev *pdev)
 159 {
 160         int err;
 161
 162         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
 163         if (err) {
 164                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
 165                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 166                 if (err) {
 167                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
 168                         return err;
 169                 }
 170         }
 171
 172         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 173         if (err) {
 174                 dev_warn(&pdev->dev,
 175                          "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
 176                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 177                 if (err) {
 178                         dev_err(&pdev->dev,
 179                                 "Can't set consistent PCI DMA mask, aborting\n");
 180                         return err;
 181                 }
 182         }
 183
 184         dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
 185         return err;
 186 }
 187
 188 static int request_bar(struct pci_dev *pdev)
 189 {
 190         int err = 0;
 191
 192         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
 193                 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
 194                 return -ENODEV;
 195         }
 196
 197         err = pci_request_regions(pdev, DRIVER_NAME);
 198         if (err)
 199                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
 200
 201         return err;
 202 }
 203
 204 static void release_bar(struct pci_dev *pdev)
 205 {
 206         pci_release_regions(pdev);
 207 }
 208
 209 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
 210 {
 211         struct mlx5_eq_table *table = &dev->priv.eq_table;
 212         int num_eqs = 1 << dev->caps.gen.log_max_eq;
 213         int nvec;
 214         int i;
 215
 216         nvec = dev->caps.gen.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
 217         nvec = min_t(int, nvec, num_eqs);
 218         if (nvec <= MLX5_EQ_VEC_COMP_BASE)
 219                 return -ENOMEM;
 220
 221         table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL);
 222         if (!table->msix_arr)
 223                 return -ENOMEM;
 224
 225         for (i = 0; i < nvec; i++)
 226                 table->msix_arr[i].entry = i;
 227
 228         nvec = pci_enable_msix_range(dev->pdev, table->msix_arr,
 229                                      MLX5_EQ_VEC_COMP_BASE + 1, nvec);
 230         if (nvec < 0)
 231                 return nvec;
 232
 233         table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
 234
 235         return 0;
 236 }
 237
 238 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
 239 {
 240         struct mlx5_eq_table *table = &dev->priv.eq_table;
 241
 242         pci_disable_msix(dev->pdev);
 243         kfree(table->msix_arr);
 244 }
 245
 246 struct mlx5_reg_host_endianess {
 247         u8      he;
 248         u8      rsvd[15];
 249 };
 250
 251
 252 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
 253
 254 enum {
 255         MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
 256                                 MLX5_DEV_CAP_FLAG_DCT,
 257 };
 258
 259 static u16 to_fw_pkey_sz(u32 size)
 260 {
 261         switch (size) {
 262         case 128:
 263                 return 0;
 264         case 256:
 265                 return 1;
 266         case 512:
 267                 return 2;
 268         case 1024:
 269                 return 3;
 270         case 2048:
 271                 return 4;
 272         case 4096:
 273                 return 5;
 274         default:
 275                 pr_warn("invalid pkey table size %d\n", size);
 276                 return 0;
 277         }
 278 }
 279
 280 /* selectively copy writable fields clearing any reserved area
 281  */
 282 static void copy_rw_fields(void *to, struct mlx5_caps *from)
 283 {
 284         __be64 *flags_off = (__be64 *)MLX5_ADDR_OF(cmd_hca_cap, to, reserved_22);
 285         u64 v64;
 286
 287         MLX5_SET(cmd_hca_cap, to, log_max_qp, from->gen.log_max_qp);
 288         MLX5_SET(cmd_hca_cap, to, log_max_ra_req_qp, from->gen.log_max_ra_req_qp);
 289         MLX5_SET(cmd_hca_cap, to, log_max_ra_res_qp, from->gen.log_max_ra_res_qp);
 290         MLX5_SET(cmd_hca_cap, to, pkey_table_size, from->gen.pkey_table_size);
 291         MLX5_SET(cmd_hca_cap, to, log_max_ra_req_dc, from->gen.log_max_ra_req_dc);
 292         MLX5_SET(cmd_hca_cap, to, log_max_ra_res_dc, from->gen.log_max_ra_res_dc);
 293         MLX5_SET(cmd_hca_cap, to, pkey_table_size, to_fw_pkey_sz(from->gen.pkey_table_size));
 294         MLX5_SET(cmd_hca_cap, to, log_uar_page_sz, PAGE_SHIFT - 12);
 295         v64 = from->gen.flags & MLX5_CAP_BITS_RW_MASK;
 296         *flags_off = cpu_to_be64(v64);
 297 }
 298
 299 static u16 get_pkey_table_size(int pkey)
 300 {
 301         if (pkey > MLX5_MAX_LOG_PKEY_TABLE)
 302                 return 0;
 303
 304         return MLX5_MIN_PKEY_TABLE_SIZE << pkey;
 305 }
 306
 307 static void fw2drv_caps(struct mlx5_caps *caps, void *out)
 308 {
 309         struct mlx5_general_caps *gen = &caps->gen;
 310
 311         gen->max_srq_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_srq_sz);
 312         gen->max_wqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_qp_sz);
 313         gen->log_max_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_qp);
 314         gen->log_max_strq = MLX5_GET_PR(cmd_hca_cap, out, log_max_strq_sz);
 315         gen->log_max_srq = MLX5_GET_PR(cmd_hca_cap, out, log_max_srqs);
 316         gen->max_cqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_cq_sz);
 317         gen->log_max_cq = MLX5_GET_PR(cmd_hca_cap, out, log_max_cq);
 318         gen->max_eqes = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_max_eq_sz);
 319         gen->log_max_mkey = MLX5_GET_PR(cmd_hca_cap, out, log_max_mkey);
 320         gen->log_max_eq = MLX5_GET_PR(cmd_hca_cap, out, log_max_eq);
 321         gen->max_indirection = MLX5_GET_PR(cmd_hca_cap, out, max_indirection);
 322         gen->log_max_mrw_sz = MLX5_GET_PR(cmd_hca_cap, out, log_max_mrw_sz);
 323         gen->log_max_bsf_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_bsf_list_size);
 324         gen->log_max_klm_list_size = MLX5_GET_PR(cmd_hca_cap, out, log_max_klm_list_size);
 325         gen->log_max_ra_req_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_dc);
 326         gen->log_max_ra_res_dc = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_dc);
 327         gen->log_max_ra_req_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_req_qp);
 328         gen->log_max_ra_res_qp = MLX5_GET_PR(cmd_hca_cap, out, log_max_ra_res_qp);
 329         gen->max_qp_counters = MLX5_GET_PR(cmd_hca_cap, out, max_qp_cnt);
 330         gen->pkey_table_size = get_pkey_table_size(MLX5_GET_PR(cmd_hca_cap, out, pkey_table_size));
 331         gen->local_ca_ack_delay = MLX5_GET_PR(cmd_hca_cap, out, local_ca_ack_delay);
 332         gen->num_ports = MLX5_GET_PR(cmd_hca_cap, out, num_ports);
 333         gen->log_max_msg = MLX5_GET_PR(cmd_hca_cap, out, log_max_msg);
 334         gen->stat_rate_support = MLX5_GET_PR(cmd_hca_cap, out, stat_rate_support);
 335         gen->flags = be64_to_cpu(*(__be64 *)MLX5_ADDR_OF(cmd_hca_cap, out, reserved_22));
 336         pr_debug("flags = 0x%llx\n", gen->flags);
 337         gen->uar_sz = MLX5_GET_PR(cmd_hca_cap, out, uar_sz);
 338         gen->min_log_pg_sz = MLX5_GET_PR(cmd_hca_cap, out, log_pg_sz);
 339         gen->bf_reg_size = MLX5_GET_PR(cmd_hca_cap, out, bf);
 340         gen->bf_reg_size = 1 << MLX5_GET_PR(cmd_hca_cap, out, log_bf_reg_size);
 341         gen->max_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq);
 342         gen->max_rq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_rq);
 343         gen->max_dc_sq_desc_sz = MLX5_GET_PR(cmd_hca_cap, out, max_wqe_sz_sq_dc);
 344         gen->max_qp_mcg = MLX5_GET_PR(cmd_hca_cap, out, max_qp_mcg);
 345         gen->log_max_pd = MLX5_GET_PR(cmd_hca_cap, out, log_max_pd);
 346         gen->log_max_xrcd = MLX5_GET_PR(cmd_hca_cap, out, log_max_xrcd);
 347         gen->log_uar_page_sz = MLX5_GET_PR(cmd_hca_cap, out, log_uar_page_sz);
 348 }
 349
 350 static const char *caps_opmod_str(u16 opmod)
 351 {
 352         switch (opmod) {
 353         case HCA_CAP_OPMOD_GET_MAX:
 354                 return "GET_MAX";
 355         case HCA_CAP_OPMOD_GET_CUR:
 356                 return "GET_CUR";
 357         default:
 358                 return "Invalid";
 359         }
 360 }
 361
 362 int mlx5_core_get_caps(struct mlx5_core_dev *dev, struct mlx5_caps *caps,
 363                        u16 opmod)
 364 {
 365         u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
 366         int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
 367         void *out;
 368         int err;
 369
 370         memset(in, 0, sizeof(in));
 371         out = kzalloc(out_sz, GFP_KERNEL);
 372         if (!out)
 373                 return -ENOMEM;
 374         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 375         MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
 376         err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
 377         if (err)
 378                 goto query_ex;
 379
 380         err = mlx5_cmd_status_to_err_v2(out);
 381         if (err) {
 382                 mlx5_core_warn(dev, "query max hca cap failed, %d\n", err);
 383                 goto query_ex;
 384         }
 385         mlx5_core_dbg(dev, "%s\n", caps_opmod_str(opmod));
 386         fw2drv_caps(caps, MLX5_ADDR_OF(query_hca_cap_out, out, capability_struct));
 387
 388 query_ex:
 389         kfree(out);
 390         return err;
 391 }
 392
 393 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
 394 {
 395         u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
 396         int err;
 397
 398         memset(out, 0, sizeof(out));
 399
 400         MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
 401         err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
 402         if (err)
 403                 return err;
 404
 405         err = mlx5_cmd_status_to_err_v2(out);
 406
 407         return err;
 408 }
 409
 410 static int handle_hca_cap(struct mlx5_core_dev *dev)
 411 {
 412         void *set_ctx = NULL;
 413         struct mlx5_profile *prof = dev->profile;
 414         struct mlx5_caps *cur_caps = NULL;
 415         struct mlx5_caps *max_caps = NULL;
 416         int err = -ENOMEM;
 417         int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
 418
 419         set_ctx = kzalloc(set_sz, GFP_KERNEL);
 420         if (!set_ctx)
 421                 goto query_ex;
 422
 423         max_caps = kzalloc(sizeof(*max_caps), GFP_KERNEL);
 424         if (!max_caps)
 425                 goto query_ex;
 426
 427         cur_caps = kzalloc(sizeof(*cur_caps), GFP_KERNEL);
 428         if (!cur_caps)
 429                 goto query_ex;
 430
 431         err = mlx5_core_get_caps(dev, max_caps, HCA_CAP_OPMOD_GET_MAX);
 432         if (err)
 433                 goto query_ex;
 434
 435         err = mlx5_core_get_caps(dev, cur_caps, HCA_CAP_OPMOD_GET_CUR);
 436         if (err)
 437                 goto query_ex;
 438
 439         /* we limit the size of the pkey table to 128 entries for now */
 440         cur_caps->gen.pkey_table_size = 128;
 441
 442         if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
 443                 cur_caps->gen.log_max_qp = prof->log_max_qp;
 444
 445         /* disable checksum */
 446         cur_caps->gen.flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
 447
 448         copy_rw_fields(MLX5_ADDR_OF(set_hca_cap_in, set_ctx, hca_capability_struct),
 449                        cur_caps);
 450         err = set_caps(dev, set_ctx, set_sz);
 451
 452 query_ex:
 453         kfree(cur_caps);
 454         kfree(max_caps);
 455         kfree(set_ctx);
 456
 457         return err;
 458 }
 459
 460 static int set_hca_ctrl(struct mlx5_core_dev *dev)
 461 {
 462         struct mlx5_reg_host_endianess he_in;
 463         struct mlx5_reg_host_endianess he_out;
 464         int err;
 465
 466         memset(&he_in, 0, sizeof(he_in));
 467         he_in.he = MLX5_SET_HOST_ENDIANNESS;
 468         err = mlx5_core_access_reg(dev, &he_in,  sizeof(he_in),
 469                                         &he_out, sizeof(he_out),
 470                                         MLX5_REG_HOST_ENDIANNESS, 0, 1);
 471         return err;
 472 }
 473
 474 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
 475 {
 476         int err;
 477         struct mlx5_enable_hca_mbox_in in;
 478         struct mlx5_enable_hca_mbox_out out;
 479
 480         memset(&in, 0, sizeof(in));
 481         memset(&out, 0, sizeof(out));
 482         in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
 483         err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
 484         if (err)
 485                 return err;
 486
 487         if (out.hdr.status)
 488                 return mlx5_cmd_status_to_err(&out.hdr);
 489
 490         return 0;
 491 }
 492
 493 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
 494 {
 495         int err;
 496         struct mlx5_disable_hca_mbox_in in;
 497         struct mlx5_disable_hca_mbox_out out;
 498
 499         memset(&in, 0, sizeof(in));
 500         memset(&out, 0, sizeof(out));
 501         in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
 502         err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
 503         if (err)
 504                 return err;
 505
 506         if (out.hdr.status)
 507                 return mlx5_cmd_status_to_err(&out.hdr);
 508
 509         return 0;
 510 }
 511
 512 static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
 513 {
 514         struct mlx5_priv *priv = &dev->priv;
 515         int err;
 516
 517         dev->pdev = pdev;
 518         pci_set_drvdata(dev->pdev, dev);
 519         strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
 520         priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
 521
 522         mutex_init(&priv->pgdir_mutex);
 523         INIT_LIST_HEAD(&priv->pgdir_list);
 524         spin_lock_init(&priv->mkey_lock);
 525
 526         priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
 527         if (!priv->dbg_root)
 528                 return -ENOMEM;
 529
 530         err = pci_enable_device(pdev);
 531         if (err) {
 532                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
 533                 goto err_dbg;
 534         }
 535
 536         err = request_bar(pdev);
 537         if (err) {
 538                 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
 539                 goto err_disable;
 540         }
 541
 542         pci_set_master(pdev);
 543
 544         err = set_dma_caps(pdev);
 545         if (err) {
 546                 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
 547                 goto err_clr_master;
 548         }
 549
 550         dev->iseg_base = pci_resource_start(dev->pdev, 0);
 551         dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
 552         if (!dev->iseg) {
 553                 err = -ENOMEM;
 554                 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
 555                 goto err_clr_master;
 556         }
 557         dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
 558                  fw_rev_min(dev), fw_rev_sub(dev));
 559
 560         err = mlx5_cmd_init(dev);
 561         if (err) {
 562                 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
 563                 goto err_unmap;
 564         }
 565
 566         mlx5_pagealloc_init(dev);
 567
 568         err = mlx5_core_enable_hca(dev);
 569         if (err) {
 570                 dev_err(&pdev->dev, "enable hca failed\n");
 571                 goto err_pagealloc_cleanup;
 572         }
 573
 574         err = mlx5_satisfy_startup_pages(dev, 1);
 575         if (err) {
 576                 dev_err(&pdev->dev, "failed to allocate boot pages\n");
 577                 goto err_disable_hca;
 578         }
 579
 580         err = set_hca_ctrl(dev);
 581         if (err) {
 582                 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
 583                 goto reclaim_boot_pages;
 584         }
 585
 586         err = handle_hca_cap(dev);
 587         if (err) {
 588                 dev_err(&pdev->dev, "handle_hca_cap failed\n");
 589                 goto reclaim_boot_pages;
 590         }
 591
 592         err = mlx5_satisfy_startup_pages(dev, 0);
 593         if (err) {
 594                 dev_err(&pdev->dev, "failed to allocate init pages\n");
 595                 goto reclaim_boot_pages;
 596         }
 597
 598         err = mlx5_pagealloc_start(dev);
 599         if (err) {
 600                 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
 601                 goto reclaim_boot_pages;
 602         }
 603
 604         err = mlx5_cmd_init_hca(dev);
 605         if (err) {
 606                 dev_err(&pdev->dev, "init hca failed\n");
 607                 goto err_pagealloc_stop;
 608         }
 609
 610         mlx5_start_health_poll(dev);
 611
 612         err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
 613         if (err) {
 614                 dev_err(&pdev->dev, "query hca failed\n");
 615                 goto err_stop_poll;
 616         }
 617
 618         err = mlx5_cmd_query_adapter(dev);
 619         if (err) {
 620                 dev_err(&pdev->dev, "query adapter failed\n");
 621                 goto err_stop_poll;
 622         }
 623
 624         err = mlx5_enable_msix(dev);
 625         if (err) {
 626                 dev_err(&pdev->dev, "enable msix failed\n");
 627                 goto err_stop_poll;
 628         }
 629
 630         err = mlx5_eq_init(dev);
 631         if (err) {
 632                 dev_err(&pdev->dev, "failed to initialize eq\n");
 633                 goto disable_msix;
 634         }
 635
 636         err = mlx5_alloc_uuars(dev, &priv->uuari);
 637         if (err) {
 638                 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
 639                 goto err_eq_cleanup;
 640         }
 641
 642         err = mlx5_start_eqs(dev);
 643         if (err) {
 644                 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
 645                 goto err_free_uar;
 646         }
 647
 648         MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
 649
 650         mlx5_init_cq_table(dev);
 651         mlx5_init_qp_table(dev);
 652         mlx5_init_srq_table(dev);
 653         mlx5_init_mr_table(dev);
 654
 655         return 0;
 656
 657 err_free_uar:
 658         mlx5_free_uuars(dev, &priv->uuari);
 659
 660 err_eq_cleanup:
 661         mlx5_eq_cleanup(dev);
 662
 663 disable_msix:
 664         mlx5_disable_msix(dev);
 665
 666 err_stop_poll:
 667         mlx5_stop_health_poll(dev);
 668         if (mlx5_cmd_teardown_hca(dev)) {
 669                 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
 670                 return err;
 671         }
 672
 673 err_pagealloc_stop:
 674         mlx5_pagealloc_stop(dev);
 675
 676 reclaim_boot_pages:
 677         mlx5_reclaim_startup_pages(dev);
 678
 679 err_disable_hca:
 680         mlx5_core_disable_hca(dev);
 681
 682 err_pagealloc_cleanup:
 683         mlx5_pagealloc_cleanup(dev);
 684         mlx5_cmd_cleanup(dev);
 685
 686 err_unmap:
 687         iounmap(dev->iseg);
 688
 689 err_clr_master:
 690         pci_clear_master(dev->pdev);
 691         release_bar(dev->pdev);
 692
 693 err_disable:
 694         pci_disable_device(dev->pdev);
 695
 696 err_dbg:
 697         debugfs_remove(priv->dbg_root);
 698         return err;
 699 }
 700 EXPORT_SYMBOL(mlx5_dev_init);
 701
 702 static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
 703 {
 704         struct mlx5_priv *priv = &dev->priv;
 705
 706         mlx5_cleanup_srq_table(dev);
 707         mlx5_cleanup_qp_table(dev);
 708         mlx5_cleanup_cq_table(dev);
 709         mlx5_stop_eqs(dev);
 710         mlx5_free_uuars(dev, &priv->uuari);
 711         mlx5_eq_cleanup(dev);
 712         mlx5_disable_msix(dev);
 713         mlx5_stop_health_poll(dev);
 714         if (mlx5_cmd_teardown_hca(dev)) {
 715                 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
 716                 return;
 717         }
 718         mlx5_pagealloc_stop(dev);
 719         mlx5_reclaim_startup_pages(dev);
 720         mlx5_core_disable_hca(dev);
 721         mlx5_pagealloc_cleanup(dev);
 722         mlx5_cmd_cleanup(dev);
 723         iounmap(dev->iseg);
 724         pci_clear_master(dev->pdev);
 725         release_bar(dev->pdev);
 726         pci_disable_device(dev->pdev);
 727         debugfs_remove(priv->dbg_root);
 728 }
 729
 730 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
 731 {
 732         struct mlx5_device_context *dev_ctx;
 733         struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
 734
 735         dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
 736         if (!dev_ctx) {
 737                 pr_warn("mlx5_add_device: alloc context failed\n");
 738                 return;
 739         }
 740
 741         dev_ctx->intf    = intf;
 742         dev_ctx->context = intf->add(dev);
 743
 744         if (dev_ctx->context) {
 745                 spin_lock_irq(&priv->ctx_lock);
 746                 list_add_tail(&dev_ctx->list, &priv->ctx_list);
 747                 spin_unlock_irq(&priv->ctx_lock);
 748         } else {
 749                 kfree(dev_ctx);
 750         }
 751 }
 752
 753 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
 754 {
 755         struct mlx5_device_context *dev_ctx;
 756         struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
 757
 758         list_for_each_entry(dev_ctx, &priv->ctx_list, list)
 759                 if (dev_ctx->intf == intf) {
 760                         spin_lock_irq(&priv->ctx_lock);
 761                         list_del(&dev_ctx->list);
 762                         spin_unlock_irq(&priv->ctx_lock);
 763
 764                         intf->remove(dev, dev_ctx->context);
 765                         kfree(dev_ctx);
 766                         return;
 767                 }
 768 }
 769 static int mlx5_register_device(struct mlx5_core_dev *dev)
 770 {
 771         struct mlx5_priv *priv = &dev->priv;
 772         struct mlx5_interface *intf;
 773
 774         mutex_lock(&intf_mutex);
 775         list_add_tail(&priv->dev_list, &dev_list);
 776         list_for_each_entry(intf, &intf_list, list)
 777                 mlx5_add_device(intf, priv);
 778         mutex_unlock(&intf_mutex);
 779
 780         return 0;
 781 }
 782 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
 783 {
 784         struct mlx5_priv *priv = &dev->priv;
 785         struct mlx5_interface *intf;
 786
 787         mutex_lock(&intf_mutex);
 788         list_for_each_entry(intf, &intf_list, list)
 789                 mlx5_remove_device(intf, priv);
 790         list_del(&priv->dev_list);
 791         mutex_unlock(&intf_mutex);
 792 }
 793
 794 int mlx5_register_interface(struct mlx5_interface *intf)
 795 {
 796         struct mlx5_priv *priv;
 797
 798         if (!intf->add || !intf->remove)
 799                 return -EINVAL;
 800
 801         mutex_lock(&intf_mutex);
 802         list_add_tail(&intf->list, &intf_list);
 803         list_for_each_entry(priv, &dev_list, dev_list)
 804                 mlx5_add_device(intf, priv);
 805         mutex_unlock(&intf_mutex);
 806
 807         return 0;
 808 }
 809 EXPORT_SYMBOL(mlx5_register_interface);
 810
 811 void mlx5_unregister_interface(struct mlx5_interface *intf)
 812 {
 813         struct mlx5_priv *priv;
 814
 815         mutex_lock(&intf_mutex);
 816         list_for_each_entry(priv, &dev_list, dev_list)
 817                mlx5_remove_device(intf, priv);
 818         list_del(&intf->list);
 819         mutex_unlock(&intf_mutex);
 820 }
 821 EXPORT_SYMBOL(mlx5_unregister_interface);
 822
 823 static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
 824                             unsigned long param)
 825 {
 826         struct mlx5_priv *priv = &dev->priv;
 827         struct mlx5_device_context *dev_ctx;
 828         unsigned long flags;
 829
 830         spin_lock_irqsave(&priv->ctx_lock, flags);
 831
 832         list_for_each_entry(dev_ctx, &priv->ctx_list, list)
 833                 if (dev_ctx->intf->event)
 834                         dev_ctx->intf->event(dev, dev_ctx->context, event, param);
 835
 836         spin_unlock_irqrestore(&priv->ctx_lock, flags);
 837 }
 838
 839 struct mlx5_core_event_handler {
 840         void (*event)(struct mlx5_core_dev *dev,
 841                       enum mlx5_dev_event event,
 842                       void *data);
 843 };
 844
 845 #define MLX5_IB_MOD "mlx5_ib"
 846
 847 static int init_one(struct pci_dev *pdev,
 848                     const struct pci_device_id *id)
 849 {
 850         struct mlx5_core_dev *dev;
 851         struct mlx5_priv *priv;
 852         int err;
 853
 854         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
 855         if (!dev) {
 856                 dev_err(&pdev->dev, "kzalloc failed\n");
 857                 return -ENOMEM;
 858         }
 859         priv = &dev->priv;
 860
 861         pci_set_drvdata(pdev, dev);
 862
 863         if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
 864                 pr_warn("selected profile out of range, selecting default (%d)\n",
 865                         MLX5_DEFAULT_PROF);
 866                 prof_sel = MLX5_DEFAULT_PROF;
 867         }
 868         dev->profile = &profile[prof_sel];
 869         dev->event = mlx5_core_event;
 870
 871         INIT_LIST_HEAD(&priv->ctx_list);
 872         spin_lock_init(&priv->ctx_lock);
 873         err = mlx5_dev_init(dev, pdev);
 874         if (err) {
 875                 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
 876                 goto out;
 877         }
 878
 879         err = mlx5_register_device(dev);
 880         if (err) {
 881                 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
 882                 goto out_init;
 883         }
 884
 885         err = request_module_nowait(MLX5_IB_MOD);
 886         if (err)
 887                 pr_info("failed request module on %s\n", MLX5_IB_MOD);
 888
 889         return 0;
 890
 891 out_init:
 892         mlx5_dev_cleanup(dev);
 893 out:
 894         kfree(dev);
 895         return err;
 896 }
 897 static void remove_one(struct pci_dev *pdev)
 898 {
 899         struct mlx5_core_dev *dev  = pci_get_drvdata(pdev);
 900
 901         mlx5_unregister_device(dev);
 902         mlx5_dev_cleanup(dev);
 903         kfree(dev);
 904 }
 905
 906 static const struct pci_device_id mlx5_core_pci_table[] = {
 907         { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
 908         { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
 909         { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
 910         { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
 911         { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
 912         { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
 913         { 0, }
 914 };
 915
 916 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
 917
 918 static struct pci_driver mlx5_core_driver = {
 919         .name           = DRIVER_NAME,
 920         .id_table       = mlx5_core_pci_table,
 921         .probe          = init_one,
 922         .remove         = remove_one
 923 };
 924
 925 static int __init init(void)
 926 {
 927         int err;
 928
 929         mlx5_register_debugfs();
 930         mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
 931         if (!mlx5_core_wq) {
 932                 err = -ENOMEM;
 933                 goto err_debug;
 934         }
 935         mlx5_health_init();
 936
 937         err = pci_register_driver(&mlx5_core_driver);
 938         if (err)
 939                 goto err_health;
 940
 941         return 0;
 942
 943 err_health:
 944         mlx5_health_cleanup();
 945         destroy_workqueue(mlx5_core_wq);
 946 err_debug:
 947         mlx5_unregister_debugfs();
 948         return err;
 949 }
 950
 951 static void __exit cleanup(void)
 952 {
 953         pci_unregister_driver(&mlx5_core_driver);
 954         mlx5_health_cleanup();
 955         destroy_workqueue(mlx5_core_wq);
 956         mlx5_unregister_debugfs();
 957 }
 958
 959 module_init(init);
 960 module_exit(cleanup);