2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 #ifndef _MLXSW_SPECTRUM_H
38 #define _MLXSW_SPECTRUM_H
40 #include <linux/types.h>
41 #include <linux/netdevice.h>
42 #include <linux/rhashtable.h>
43 #include <linux/bitops.h>
44 #include <linux/if_vlan.h>
45 #include <linux/list.h>
46 #include <linux/dcbnl.h>
47 #include <linux/in6.h>
48 #include <net/switchdev.h>
53 #define MLXSW_SP_VFID_BASE VLAN_N_VID
54 #define MLXSW_SP_VFID_MAX 6656 /* Bridged VLAN interfaces */
56 #define MLXSW_SP_RFID_BASE 15360
57 #define MLXSW_SP_RIF_MAX 800
59 #define MLXSW_SP_LAG_MAX 64
60 #define MLXSW_SP_PORT_PER_LAG_MAX 16
62 #define MLXSW_SP_MID_MAX 7000
64 #define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
66 #define MLXSW_SP_LPM_TREE_MIN 2 /* trees 0 and 1 are reserved */
67 #define MLXSW_SP_LPM_TREE_MAX 22
68 #define MLXSW_SP_LPM_TREE_COUNT (MLXSW_SP_LPM_TREE_MAX - MLXSW_SP_LPM_TREE_MIN)
70 #define MLXSW_SP_VIRTUAL_ROUTER_MAX 256
72 #define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
74 #define MLXSW_SP_BYTES_PER_CELL 96
76 #define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
77 #define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL)
79 #define MLXSW_SP_KVD_LINEAR_SIZE 65536 /* entries */
80 #define MLXSW_SP_KVD_HASH_SINGLE_SIZE 163840 /* entries */
81 #define MLXSW_SP_KVD_HASH_DOUBLE_SIZE 32768 /* entries */
83 /* Maximum delay buffer needed in case of PAUSE frames, in cells.
84 * Assumes 100m cable and maximum MTU.
86 #define MLXSW_SP_PAUSE_DELAY 612
88 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
90 static inline u16
mlxsw_sp_pfc_delay_get(int mtu
, u16 delay
)
92 delay
= MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay
, BITS_PER_BYTE
));
93 return MLXSW_SP_CELL_FACTOR
* delay
+ MLXSW_SP_BYTES_TO_CELLS(mtu
);
98 struct mlxsw_sp_upper
{
99 struct net_device
*dev
;
100 unsigned int ref_count
;
103 struct mlxsw_sp_fid
{
104 void (*leave
)(struct mlxsw_sp_port
*mlxsw_sp_vport
);
105 struct list_head list
;
106 unsigned int ref_count
;
107 struct net_device
*dev
;
108 struct mlxsw_sp_rif
*r
;
112 struct mlxsw_sp_rif
{
113 struct net_device
*dev
;
114 unsigned int ref_count
;
115 struct mlxsw_sp_fid
*f
;
116 unsigned char addr
[ETH_ALEN
];
121 struct mlxsw_sp_mid
{
122 struct list_head list
;
123 unsigned char addr
[ETH_ALEN
];
126 unsigned int ref_count
;
129 static inline u16
mlxsw_sp_vfid_to_fid(u16 vfid
)
131 return MLXSW_SP_VFID_BASE
+ vfid
;
134 static inline u16
mlxsw_sp_fid_to_vfid(u16 fid
)
136 return fid
- MLXSW_SP_VFID_BASE
;
139 static inline bool mlxsw_sp_fid_is_vfid(u16 fid
)
141 return fid
>= MLXSW_SP_VFID_BASE
&& fid
< MLXSW_SP_RFID_BASE
;
144 static inline bool mlxsw_sp_fid_is_rfid(u16 fid
)
146 return fid
>= MLXSW_SP_RFID_BASE
;
149 static inline u16
mlxsw_sp_rif_sp_to_fid(u16 rif
)
151 return MLXSW_SP_RFID_BASE
+ rif
;
154 struct mlxsw_sp_sb_pr
{
155 enum mlxsw_reg_sbpr_mode mode
;
159 struct mlxsw_cp_sb_occ
{
164 struct mlxsw_sp_sb_cm
{
168 struct mlxsw_cp_sb_occ occ
;
171 struct mlxsw_sp_sb_pm
{
174 struct mlxsw_cp_sb_occ occ
;
177 #define MLXSW_SP_SB_POOL_COUNT 4
178 #define MLXSW_SP_SB_TC_COUNT 8
181 struct mlxsw_sp_sb_pr prs
[2][MLXSW_SP_SB_POOL_COUNT
];
183 struct mlxsw_sp_sb_cm cms
[2][MLXSW_SP_SB_TC_COUNT
];
184 struct mlxsw_sp_sb_pm pms
[2][MLXSW_SP_SB_POOL_COUNT
];
185 } ports
[MLXSW_PORT_MAX_PORTS
];
188 #define MLXSW_SP_PREFIX_COUNT (sizeof(struct in6_addr) * BITS_PER_BYTE)
190 struct mlxsw_sp_prefix_usage
{
191 DECLARE_BITMAP(b
, MLXSW_SP_PREFIX_COUNT
);
194 enum mlxsw_sp_l3proto
{
195 MLXSW_SP_L3_PROTO_IPV4
,
196 MLXSW_SP_L3_PROTO_IPV6
,
199 struct mlxsw_sp_lpm_tree
{
201 unsigned int ref_count
;
202 enum mlxsw_sp_l3proto proto
;
203 struct mlxsw_sp_prefix_usage prefix_usage
;
209 u16 id
; /* virtual router ID */
211 enum mlxsw_sp_l3proto proto
;
212 u32 tb_id
; /* kernel fib table id */
213 struct mlxsw_sp_lpm_tree
*lpm_tree
;
214 struct mlxsw_sp_fib
*fib
;
217 enum mlxsw_sp_span_type
{
218 MLXSW_SP_SPAN_EGRESS
,
219 MLXSW_SP_SPAN_INGRESS
222 struct mlxsw_sp_span_inspected_port
{
223 struct list_head list
;
224 enum mlxsw_sp_span_type type
;
228 struct mlxsw_sp_span_entry
{
231 struct list_head bound_ports_list
;
236 enum mlxsw_sp_port_mall_action_type
{
237 MLXSW_SP_PORT_MALL_MIRROR
,
240 struct mlxsw_sp_port_mall_mirror_tc_entry
{
245 struct mlxsw_sp_port_mall_tc_entry
{
246 struct list_head list
;
247 unsigned long cookie
;
248 enum mlxsw_sp_port_mall_action_type type
;
250 struct mlxsw_sp_port_mall_mirror_tc_entry mirror
;
254 struct mlxsw_sp_router
{
255 struct mlxsw_sp_lpm_tree lpm_trees
[MLXSW_SP_LPM_TREE_COUNT
];
256 struct mlxsw_sp_vr vrs
[MLXSW_SP_VIRTUAL_ROUTER_MAX
];
257 struct rhashtable neigh_ht
;
259 struct delayed_work dw
;
260 unsigned long interval
; /* ms */
262 struct delayed_work nexthop_probe_dw
;
263 #define MLXSW_SP_UNRESOLVED_NH_PROBE_INTERVAL 5000 /* ms */
264 struct list_head nexthop_group_list
;
265 struct list_head nexthop_neighs_list
;
270 struct list_head list
;
271 DECLARE_BITMAP(mapped
, MLXSW_SP_VFID_MAX
);
274 struct list_head list
;
275 DECLARE_BITMAP(mapped
, MLXSW_SP_MID_MAX
);
277 struct list_head fids
; /* VLAN-aware bridge FIDs */
278 struct mlxsw_sp_rif
*rifs
[MLXSW_SP_RIF_MAX
];
279 struct mlxsw_sp_port
**ports
;
280 struct mlxsw_core
*core
;
281 const struct mlxsw_bus_info
*bus_info
;
282 unsigned char base_mac
[ETH_ALEN
];
284 struct delayed_work dw
;
285 #define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
286 unsigned int interval
; /* ms */
288 #define MLXSW_SP_MIN_AGEING_TIME 10
289 #define MLXSW_SP_MAX_AGEING_TIME 1000000
290 #define MLXSW_SP_DEFAULT_AGEING_TIME 300
292 struct mlxsw_sp_upper master_bridge
;
293 struct mlxsw_sp_upper lags
[MLXSW_SP_LAG_MAX
];
294 u8 port_to_module
[MLXSW_PORT_MAX_PORTS
];
295 struct mlxsw_sp_sb sb
;
296 struct mlxsw_sp_router router
;
298 DECLARE_BITMAP(usage
, MLXSW_SP_KVD_LINEAR_SIZE
);
302 struct mlxsw_sp_span_entry
*entries
;
307 static inline struct mlxsw_sp_upper
*
308 mlxsw_sp_lag_get(struct mlxsw_sp
*mlxsw_sp
, u16 lag_id
)
310 return &mlxsw_sp
->lags
[lag_id
];
313 struct mlxsw_sp_port_pcpu_stats
{
318 struct u64_stats_sync syncp
;
322 struct mlxsw_sp_port
{
323 struct mlxsw_core_port core_port
; /* must be first */
324 struct net_device
*dev
;
325 struct mlxsw_sp_port_pcpu_stats __percpu
*pcpu_stats
;
326 struct mlxsw_sp
*mlxsw_sp
;
338 struct list_head list
;
339 struct mlxsw_sp_fid
*f
;
347 struct ieee_ets
*ets
;
348 struct ieee_maxrate
*maxrate
;
349 struct ieee_pfc
*pfc
;
356 /* 802.1Q bridge VLANs */
357 unsigned long *active_vlans
;
358 unsigned long *untagged_vlans
;
359 /* VLAN interfaces */
360 struct list_head vports_list
;
362 struct list_head mall_tc_list
;
365 struct mlxsw_sp_port
*mlxsw_sp_port_lower_dev_hold(struct net_device
*dev
);
366 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port
*mlxsw_sp_port
);
369 mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port
*mlxsw_sp_port
)
371 return mlxsw_sp_port
->link
.tx_pause
|| mlxsw_sp_port
->link
.rx_pause
;
374 static inline struct mlxsw_sp_port
*
375 mlxsw_sp_port_lagged_get(struct mlxsw_sp
*mlxsw_sp
, u16 lag_id
, u8 port_index
)
377 struct mlxsw_sp_port
*mlxsw_sp_port
;
380 local_port
= mlxsw_core_lag_mapping_get(mlxsw_sp
->core
,
382 mlxsw_sp_port
= mlxsw_sp
->ports
[local_port
];
383 return mlxsw_sp_port
&& mlxsw_sp_port
->lagged
? mlxsw_sp_port
: NULL
;
387 mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port
*mlxsw_sp_vport
)
389 return mlxsw_sp_vport
->vport
.vid
;
393 mlxsw_sp_port_is_vport(const struct mlxsw_sp_port
*mlxsw_sp_port
)
395 u16 vid
= mlxsw_sp_vport_vid_get(mlxsw_sp_port
);
400 static inline void mlxsw_sp_vport_fid_set(struct mlxsw_sp_port
*mlxsw_sp_vport
,
401 struct mlxsw_sp_fid
*f
)
403 mlxsw_sp_vport
->vport
.f
= f
;
406 static inline struct mlxsw_sp_fid
*
407 mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port
*mlxsw_sp_vport
)
409 return mlxsw_sp_vport
->vport
.f
;
412 static inline struct net_device
*
413 mlxsw_sp_vport_dev_get(const struct mlxsw_sp_port
*mlxsw_sp_vport
)
415 struct mlxsw_sp_fid
*f
= mlxsw_sp_vport_fid_get(mlxsw_sp_vport
);
417 return f
? f
->dev
: NULL
;
420 static inline struct mlxsw_sp_port
*
421 mlxsw_sp_port_vport_find(const struct mlxsw_sp_port
*mlxsw_sp_port
, u16 vid
)
423 struct mlxsw_sp_port
*mlxsw_sp_vport
;
425 list_for_each_entry(mlxsw_sp_vport
, &mlxsw_sp_port
->vports_list
,
427 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport
) == vid
)
428 return mlxsw_sp_vport
;
434 static inline struct mlxsw_sp_port
*
435 mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port
*mlxsw_sp_port
,
438 struct mlxsw_sp_port
*mlxsw_sp_vport
;
440 list_for_each_entry(mlxsw_sp_vport
, &mlxsw_sp_port
->vports_list
,
442 struct mlxsw_sp_fid
*f
= mlxsw_sp_vport_fid_get(mlxsw_sp_vport
);
444 if (f
&& f
->fid
== fid
)
445 return mlxsw_sp_vport
;
451 static inline struct mlxsw_sp_fid
*mlxsw_sp_fid_find(struct mlxsw_sp
*mlxsw_sp
,
454 struct mlxsw_sp_fid
*f
;
456 list_for_each_entry(f
, &mlxsw_sp
->fids
, list
)
463 static inline struct mlxsw_sp_fid
*
464 mlxsw_sp_vfid_find(const struct mlxsw_sp
*mlxsw_sp
,
465 const struct net_device
*br_dev
)
467 struct mlxsw_sp_fid
*f
;
469 list_for_each_entry(f
, &mlxsw_sp
->vfids
.list
, list
)
470 if (f
->dev
== br_dev
)
476 static inline struct mlxsw_sp_rif
*
477 mlxsw_sp_rif_find_by_dev(const struct mlxsw_sp
*mlxsw_sp
,
478 const struct net_device
*dev
)
482 for (i
= 0; i
< MLXSW_SP_RIF_MAX
; i
++)
483 if (mlxsw_sp
->rifs
[i
] && mlxsw_sp
->rifs
[i
]->dev
== dev
)
484 return mlxsw_sp
->rifs
[i
];
489 enum mlxsw_sp_flood_table
{
490 MLXSW_SP_FLOOD_TABLE_UC
,
491 MLXSW_SP_FLOOD_TABLE_BM
,
494 int mlxsw_sp_buffers_init(struct mlxsw_sp
*mlxsw_sp
);
495 void mlxsw_sp_buffers_fini(struct mlxsw_sp
*mlxsw_sp
);
496 int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port
*mlxsw_sp_port
);
497 int mlxsw_sp_sb_pool_get(struct mlxsw_core
*mlxsw_core
,
498 unsigned int sb_index
, u16 pool_index
,
499 struct devlink_sb_pool_info
*pool_info
);
500 int mlxsw_sp_sb_pool_set(struct mlxsw_core
*mlxsw_core
,
501 unsigned int sb_index
, u16 pool_index
, u32 size
,
502 enum devlink_sb_threshold_type threshold_type
);
503 int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port
*mlxsw_core_port
,
504 unsigned int sb_index
, u16 pool_index
,
506 int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port
*mlxsw_core_port
,
507 unsigned int sb_index
, u16 pool_index
,
509 int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port
*mlxsw_core_port
,
510 unsigned int sb_index
, u16 tc_index
,
511 enum devlink_sb_pool_type pool_type
,
512 u16
*p_pool_index
, u32
*p_threshold
);
513 int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port
*mlxsw_core_port
,
514 unsigned int sb_index
, u16 tc_index
,
515 enum devlink_sb_pool_type pool_type
,
516 u16 pool_index
, u32 threshold
);
517 int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core
*mlxsw_core
,
518 unsigned int sb_index
);
519 int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core
*mlxsw_core
,
520 unsigned int sb_index
);
521 int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port
*mlxsw_core_port
,
522 unsigned int sb_index
, u16 pool_index
,
523 u32
*p_cur
, u32
*p_max
);
524 int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port
*mlxsw_core_port
,
525 unsigned int sb_index
, u16 tc_index
,
526 enum devlink_sb_pool_type pool_type
,
527 u32
*p_cur
, u32
*p_max
);
529 int mlxsw_sp_switchdev_init(struct mlxsw_sp
*mlxsw_sp
);
530 void mlxsw_sp_switchdev_fini(struct mlxsw_sp
*mlxsw_sp
);
531 int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port
*mlxsw_sp_port
);
532 void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port
*mlxsw_sp_port
);
533 void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port
*mlxsw_sp_port
);
534 int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port
*mlxsw_sp_port
,
535 enum mlxsw_reg_svfa_mt mt
, bool valid
, u16 fid
,
537 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port
*mlxsw_sp_port
, u16 vid_begin
,
538 u16 vid_end
, bool is_member
, bool untagged
);
539 int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port
*mlxsw_sp_vport
, u16 fid
,
541 void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port
*mlxsw_sp_port
);
542 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port
*mlxsw_sp_port
, u16 vid
);
543 int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port
*mlxsw_sp_port
, u16 fid
);
544 int mlxsw_sp_rif_fdb_op(struct mlxsw_sp
*mlxsw_sp
, const char *mac
, u16 fid
,
546 struct mlxsw_sp_fid
*mlxsw_sp_fid_create(struct mlxsw_sp
*mlxsw_sp
, u16 fid
);
547 void mlxsw_sp_fid_destroy(struct mlxsw_sp
*mlxsw_sp
, struct mlxsw_sp_fid
*f
);
548 void mlxsw_sp_rif_bridge_destroy(struct mlxsw_sp
*mlxsw_sp
,
549 struct mlxsw_sp_rif
*r
);
550 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port
*mlxsw_sp_port
,
551 enum mlxsw_reg_qeec_hr hr
, u8 index
, u8 next_index
,
552 bool dwrr
, u8 dwrr_weight
);
553 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port
*mlxsw_sp_port
,
554 u8 switch_prio
, u8 tclass
);
555 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port
*mlxsw_sp_port
, int mtu
,
556 u8
*prio_tc
, bool pause_en
,
557 struct ieee_pfc
*my_pfc
);
558 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port
*mlxsw_sp_port
,
559 enum mlxsw_reg_qeec_hr hr
, u8 index
,
560 u8 next_index
, u32 maxrate
);
561 int __mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port
*mlxsw_sp_port
,
562 u16 vid_begin
, u16 vid_end
,
565 #ifdef CONFIG_MLXSW_SPECTRUM_DCB
567 int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port
*mlxsw_sp_port
);
568 void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port
*mlxsw_sp_port
);
572 static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port
*mlxsw_sp_port
)
577 static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port
*mlxsw_sp_port
)
582 int mlxsw_sp_router_init(struct mlxsw_sp
*mlxsw_sp
);
583 void mlxsw_sp_router_fini(struct mlxsw_sp
*mlxsw_sp
);
584 int mlxsw_sp_router_fib4_add(struct mlxsw_sp_port
*mlxsw_sp_port
,
585 const struct switchdev_obj_ipv4_fib
*fib4
,
586 struct switchdev_trans
*trans
);
587 int mlxsw_sp_router_fib4_del(struct mlxsw_sp_port
*mlxsw_sp_port
,
588 const struct switchdev_obj_ipv4_fib
*fib4
);
589 int mlxsw_sp_router_neigh_construct(struct net_device
*dev
,
590 struct neighbour
*n
);
591 void mlxsw_sp_router_neigh_destroy(struct net_device
*dev
,
592 struct neighbour
*n
);
594 int mlxsw_sp_kvdl_alloc(struct mlxsw_sp
*mlxsw_sp
, unsigned int entry_count
);
595 void mlxsw_sp_kvdl_free(struct mlxsw_sp
*mlxsw_sp
, int entry_index
);