2 * drivers/net/ks8851_mll.c
3 * Copyright (c) 2009 Micrel Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 * KS8851 16bit MLL chip from Micrel Inc.
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/cache.h>
33 #include <linux/crc32.h>
34 #include <linux/mii.h>
35 #include <linux/platform_device.h>
36 #include <linux/delay.h>
37 #include <linux/slab.h>
40 #define DRV_NAME "ks8851_mll"
42 static u8 KS_DEFAULT_MAC_ADDRESS
[] = { 0x00, 0x10, 0xA1, 0x86, 0x95, 0x11 };
43 #define MAX_RECV_FRAMES 32
44 #define MAX_BUF_SIZE 2048
45 #define TX_BUF_SIZE 2000
46 #define RX_BUF_SIZE 2000
49 #define CCR_EEPROM (1 << 9)
50 #define CCR_SPI (1 << 8)
51 #define CCR_8BIT (1 << 7)
52 #define CCR_16BIT (1 << 6)
53 #define CCR_32BIT (1 << 5)
54 #define CCR_SHARED (1 << 4)
55 #define CCR_32PIN (1 << 0)
57 /* MAC address registers */
63 #define OBCR_ODS_16MA (1 << 6)
66 #define EEPCR_EESA (1 << 4)
67 #define EEPCR_EESB (1 << 3)
68 #define EEPCR_EEDO (1 << 2)
69 #define EEPCR_EESCK (1 << 1)
70 #define EEPCR_EECS (1 << 0)
73 #define MBIR_TXMBF (1 << 12)
74 #define MBIR_TXMBFA (1 << 11)
75 #define MBIR_RXMBF (1 << 4)
76 #define MBIR_RXMBFA (1 << 3)
79 #define GRR_QMU (1 << 1)
80 #define GRR_GSR (1 << 0)
83 #define WFCR_MPRXE (1 << 7)
84 #define WFCR_WF3E (1 << 3)
85 #define WFCR_WF2E (1 << 2)
86 #define WFCR_WF1E (1 << 1)
87 #define WFCR_WF0E (1 << 0)
89 #define KS_WF0CRC0 0x30
90 #define KS_WF0CRC1 0x32
91 #define KS_WF0BM0 0x34
92 #define KS_WF0BM1 0x36
93 #define KS_WF0BM2 0x38
94 #define KS_WF0BM3 0x3A
96 #define KS_WF1CRC0 0x40
97 #define KS_WF1CRC1 0x42
98 #define KS_WF1BM0 0x44
99 #define KS_WF1BM1 0x46
100 #define KS_WF1BM2 0x48
101 #define KS_WF1BM3 0x4A
103 #define KS_WF2CRC0 0x50
104 #define KS_WF2CRC1 0x52
105 #define KS_WF2BM0 0x54
106 #define KS_WF2BM1 0x56
107 #define KS_WF2BM2 0x58
108 #define KS_WF2BM3 0x5A
110 #define KS_WF3CRC0 0x60
111 #define KS_WF3CRC1 0x62
112 #define KS_WF3BM0 0x64
113 #define KS_WF3BM1 0x66
114 #define KS_WF3BM2 0x68
115 #define KS_WF3BM3 0x6A
118 #define TXCR_TCGICMP (1 << 8)
119 #define TXCR_TCGUDP (1 << 7)
120 #define TXCR_TCGTCP (1 << 6)
121 #define TXCR_TCGIP (1 << 5)
122 #define TXCR_FTXQ (1 << 4)
123 #define TXCR_TXFCE (1 << 3)
124 #define TXCR_TXPE (1 << 2)
125 #define TXCR_TXCRC (1 << 1)
126 #define TXCR_TXE (1 << 0)
129 #define TXSR_TXLC (1 << 13)
130 #define TXSR_TXMC (1 << 12)
131 #define TXSR_TXFID_MASK (0x3f << 0)
132 #define TXSR_TXFID_SHIFT (0)
133 #define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
136 #define KS_RXCR1 0x74
137 #define RXCR1_FRXQ (1 << 15)
138 #define RXCR1_RXUDPFCC (1 << 14)
139 #define RXCR1_RXTCPFCC (1 << 13)
140 #define RXCR1_RXIPFCC (1 << 12)
141 #define RXCR1_RXPAFMA (1 << 11)
142 #define RXCR1_RXFCE (1 << 10)
143 #define RXCR1_RXEFE (1 << 9)
144 #define RXCR1_RXMAFMA (1 << 8)
145 #define RXCR1_RXBE (1 << 7)
146 #define RXCR1_RXME (1 << 6)
147 #define RXCR1_RXUE (1 << 5)
148 #define RXCR1_RXAE (1 << 4)
149 #define RXCR1_RXINVF (1 << 1)
150 #define RXCR1_RXE (1 << 0)
151 #define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \
152 RXCR1_RXMAFMA | RXCR1_RXPAFMA)
154 #define KS_RXCR2 0x76
155 #define RXCR2_SRDBL_MASK (0x7 << 5)
156 #define RXCR2_SRDBL_SHIFT (5)
157 #define RXCR2_SRDBL_4B (0x0 << 5)
158 #define RXCR2_SRDBL_8B (0x1 << 5)
159 #define RXCR2_SRDBL_16B (0x2 << 5)
160 #define RXCR2_SRDBL_32B (0x3 << 5)
161 /* #define RXCR2_SRDBL_FRAME (0x4 << 5) */
162 #define RXCR2_IUFFP (1 << 4)
163 #define RXCR2_RXIUFCEZ (1 << 3)
164 #define RXCR2_UDPLFE (1 << 2)
165 #define RXCR2_RXICMPFCC (1 << 1)
166 #define RXCR2_RXSAF (1 << 0)
168 #define KS_TXMIR 0x78
170 #define KS_RXFHSR 0x7C
171 #define RXFSHR_RXFV (1 << 15)
172 #define RXFSHR_RXICMPFCS (1 << 13)
173 #define RXFSHR_RXIPFCS (1 << 12)
174 #define RXFSHR_RXTCPFCS (1 << 11)
175 #define RXFSHR_RXUDPFCS (1 << 10)
176 #define RXFSHR_RXBF (1 << 7)
177 #define RXFSHR_RXMF (1 << 6)
178 #define RXFSHR_RXUF (1 << 5)
179 #define RXFSHR_RXMR (1 << 4)
180 #define RXFSHR_RXFT (1 << 3)
181 #define RXFSHR_RXFTL (1 << 2)
182 #define RXFSHR_RXRF (1 << 1)
183 #define RXFSHR_RXCE (1 << 0)
184 #define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\
185 RXFSHR_RXFTL | RXFSHR_RXMR |\
186 RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\
188 #define KS_RXFHBCR 0x7E
189 #define RXFHBCR_CNT_MASK 0x0FFF
191 #define KS_TXQCR 0x80
192 #define TXQCR_AETFE (1 << 2)
193 #define TXQCR_TXQMAM (1 << 1)
194 #define TXQCR_METFE (1 << 0)
196 #define KS_RXQCR 0x82
197 #define RXQCR_RXDTTS (1 << 12)
198 #define RXQCR_RXDBCTS (1 << 11)
199 #define RXQCR_RXFCTS (1 << 10)
200 #define RXQCR_RXIPHTOE (1 << 9)
201 #define RXQCR_RXDTTE (1 << 7)
202 #define RXQCR_RXDBCTE (1 << 6)
203 #define RXQCR_RXFCTE (1 << 5)
204 #define RXQCR_ADRFE (1 << 4)
205 #define RXQCR_SDA (1 << 3)
206 #define RXQCR_RRXEF (1 << 0)
207 #define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE)
209 #define KS_TXFDPR 0x84
210 #define TXFDPR_TXFPAI (1 << 14)
211 #define TXFDPR_TXFP_MASK (0x7ff << 0)
212 #define TXFDPR_TXFP_SHIFT (0)
214 #define KS_RXFDPR 0x86
215 #define RXFDPR_RXFPAI (1 << 14)
217 #define KS_RXDTTR 0x8C
218 #define KS_RXDBCTR 0x8E
222 #define IRQ_LCI (1 << 15)
223 #define IRQ_TXI (1 << 14)
224 #define IRQ_RXI (1 << 13)
225 #define IRQ_RXOI (1 << 11)
226 #define IRQ_TXPSI (1 << 9)
227 #define IRQ_RXPSI (1 << 8)
228 #define IRQ_TXSAI (1 << 6)
229 #define IRQ_RXWFDI (1 << 5)
230 #define IRQ_RXMPDI (1 << 4)
231 #define IRQ_LDI (1 << 3)
232 #define IRQ_EDI (1 << 2)
233 #define IRQ_SPIBEI (1 << 1)
234 #define IRQ_DEDI (1 << 0)
236 #define KS_RXFCTR 0x9C
237 #define RXFCTR_THRESHOLD_MASK 0x00FF
240 #define RXFCTR_RXFC_MASK (0xff << 8)
241 #define RXFCTR_RXFC_SHIFT (8)
242 #define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
243 #define RXFCTR_RXFCT_MASK (0xff << 0)
244 #define RXFCTR_RXFCT_SHIFT (0)
246 #define KS_TXNTFSR 0x9E
248 #define KS_MAHTR0 0xA0
249 #define KS_MAHTR1 0xA2
250 #define KS_MAHTR2 0xA4
251 #define KS_MAHTR3 0xA6
253 #define KS_FCLWR 0xB0
254 #define KS_FCHWR 0xB2
255 #define KS_FCOWR 0xB4
257 #define KS_CIDER 0xC0
258 #define CIDER_ID 0x8870
259 #define CIDER_REV_MASK (0x7 << 1)
260 #define CIDER_REV_SHIFT (1)
261 #define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
265 #define IACR_RDEN (1 << 12)
266 #define IACR_TSEL_MASK (0x3 << 10)
267 #define IACR_TSEL_SHIFT (10)
268 #define IACR_TSEL_MIB (0x3 << 10)
269 #define IACR_ADDR_MASK (0x1f << 0)
270 #define IACR_ADDR_SHIFT (0)
272 #define KS_IADLR 0xD0
273 #define KS_IAHDR 0xD2
275 #define KS_PMECR 0xD4
276 #define PMECR_PME_DELAY (1 << 14)
277 #define PMECR_PME_POL (1 << 12)
278 #define PMECR_WOL_WAKEUP (1 << 11)
279 #define PMECR_WOL_MAGICPKT (1 << 10)
280 #define PMECR_WOL_LINKUP (1 << 9)
281 #define PMECR_WOL_ENERGY (1 << 8)
282 #define PMECR_AUTO_WAKE_EN (1 << 7)
283 #define PMECR_WAKEUP_NORMAL (1 << 6)
284 #define PMECR_WKEVT_MASK (0xf << 2)
285 #define PMECR_WKEVT_SHIFT (2)
286 #define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
287 #define PMECR_WKEVT_ENERGY (0x1 << 2)
288 #define PMECR_WKEVT_LINK (0x2 << 2)
289 #define PMECR_WKEVT_MAGICPKT (0x4 << 2)
290 #define PMECR_WKEVT_FRAME (0x8 << 2)
291 #define PMECR_PM_MASK (0x3 << 0)
292 #define PMECR_PM_SHIFT (0)
293 #define PMECR_PM_NORMAL (0x0 << 0)
294 #define PMECR_PM_ENERGY (0x1 << 0)
295 #define PMECR_PM_SOFTDOWN (0x2 << 0)
296 #define PMECR_PM_POWERSAVE (0x3 << 0)
298 /* Standard MII PHY data */
299 #define KS_P1MBCR 0xE4
300 #define P1MBCR_FORCE_FDX (1 << 8)
302 #define KS_P1MBSR 0xE6
303 #define P1MBSR_AN_COMPLETE (1 << 5)
304 #define P1MBSR_AN_CAPABLE (1 << 3)
305 #define P1MBSR_LINK_UP (1 << 2)
307 #define KS_PHY1ILR 0xE8
308 #define KS_PHY1IHR 0xEA
309 #define KS_P1ANAR 0xEC
310 #define KS_P1ANLPR 0xEE
312 #define KS_P1SCLMD 0xF4
313 #define P1SCLMD_LEDOFF (1 << 15)
314 #define P1SCLMD_TXIDS (1 << 14)
315 #define P1SCLMD_RESTARTAN (1 << 13)
316 #define P1SCLMD_DISAUTOMDIX (1 << 10)
317 #define P1SCLMD_FORCEMDIX (1 << 9)
318 #define P1SCLMD_AUTONEGEN (1 << 7)
319 #define P1SCLMD_FORCE100 (1 << 6)
320 #define P1SCLMD_FORCEFDX (1 << 5)
321 #define P1SCLMD_ADV_FLOW (1 << 4)
322 #define P1SCLMD_ADV_100BT_FDX (1 << 3)
323 #define P1SCLMD_ADV_100BT_HDX (1 << 2)
324 #define P1SCLMD_ADV_10BT_FDX (1 << 1)
325 #define P1SCLMD_ADV_10BT_HDX (1 << 0)
328 #define P1CR_HP_MDIX (1 << 15)
329 #define P1CR_REV_POL (1 << 13)
330 #define P1CR_OP_100M (1 << 10)
331 #define P1CR_OP_FDX (1 << 9)
332 #define P1CR_OP_MDI (1 << 7)
333 #define P1CR_AN_DONE (1 << 6)
334 #define P1CR_LINK_GOOD (1 << 5)
335 #define P1CR_PNTR_FLOW (1 << 4)
336 #define P1CR_PNTR_100BT_FDX (1 << 3)
337 #define P1CR_PNTR_100BT_HDX (1 << 2)
338 #define P1CR_PNTR_10BT_FDX (1 << 1)
339 #define P1CR_PNTR_10BT_HDX (1 << 0)
341 /* TX Frame control */
343 #define TXFR_TXIC (1 << 15)
344 #define TXFR_TXFID_MASK (0x3f << 0)
345 #define TXFR_TXFID_SHIFT (0)
348 #define P1SR_HP_MDIX (1 << 15)
349 #define P1SR_REV_POL (1 << 13)
350 #define P1SR_OP_100M (1 << 10)
351 #define P1SR_OP_FDX (1 << 9)
352 #define P1SR_OP_MDI (1 << 7)
353 #define P1SR_AN_DONE (1 << 6)
354 #define P1SR_LINK_GOOD (1 << 5)
355 #define P1SR_PNTR_FLOW (1 << 4)
356 #define P1SR_PNTR_100BT_FDX (1 << 3)
357 #define P1SR_PNTR_100BT_HDX (1 << 2)
358 #define P1SR_PNTR_10BT_FDX (1 << 1)
359 #define P1SR_PNTR_10BT_HDX (1 << 0)
361 #define ENUM_BUS_NONE 0
362 #define ENUM_BUS_8BIT 1
363 #define ENUM_BUS_16BIT 2
364 #define ENUM_BUS_32BIT 3
366 #define MAX_MCAST_LST 32
367 #define HW_MCAST_SIZE 8
370 * union ks_tx_hdr - tx header data
371 * @txb: The header as bytes
372 * @txw: The header as 16bit, little-endian words
374 * A dual representation of the tx header data to allow
375 * access to individual bytes, and to allow 16bit accesses
376 * with 16bit alignment.
384 * struct ks_net - KS8851 driver private data
385 * @net_device : The network device we're bound to
386 * @hw_addr : start address of data register.
387 * @hw_addr_cmd : start address of command register.
388 * @txh : temporaly buffer to save status/length.
389 * @lock : Lock to ensure that the device is not accessed when busy.
390 * @pdev : Pointer to platform device.
391 * @mii : The MII state information for the mii calls.
392 * @frame_head_info : frame header information for multi-pkt rx.
393 * @statelock : Lock on this structure for tx list.
394 * @msg_enable : The message flags controlling driver output (see ethtool).
395 * @frame_cnt : number of frames received.
396 * @bus_width : i/o bus width.
397 * @rc_rxqcr : Cached copy of KS_RXQCR.
398 * @rc_txcr : Cached copy of KS_TXCR.
399 * @rc_ier : Cached copy of KS_IER.
400 * @sharedbus : Multipex(addr and data bus) mode indicator.
401 * @cmd_reg_cache : command register cached.
402 * @cmd_reg_cache_int : command register cached. Used in the irq handler.
403 * @promiscuous : promiscuous mode indicator.
404 * @all_mcast : mutlicast indicator.
405 * @mcast_lst_size : size of multicast list.
406 * @mcast_lst : multicast list.
407 * @mcast_bits : multicast enabed.
408 * @mac_addr : MAC address assigned to this device.
410 * @extra_byte : number of extra byte prepended rx pkt.
411 * @enabled : indicator this device works.
413 * The @lock ensures that the chip is protected when certain operations are
414 * in progress. When the read or write packet transfer is in progress, most
415 * of the chip registers are not accessible until the transfer is finished and
416 * the DMA has been de-asserted.
418 * The @statelock is used to protect information in the structure which may
419 * need to be accessed via several sources, such as the network driver layer
420 * or one of the work queues.
424 /* Receive multiplex framer header info */
425 struct type_frame_head
{
426 u16 sts
; /* Frame status */
427 u16 len
; /* Byte count */
431 struct net_device
*netdev
;
432 void __iomem
*hw_addr
;
433 void __iomem
*hw_addr_cmd
;
434 union ks_tx_hdr txh ____cacheline_aligned
;
435 struct mutex lock
; /* spinlock to be interrupt safe */
436 struct platform_device
*pdev
;
437 struct mii_if_info mii
;
438 struct type_frame_head
*frame_head_info
;
439 spinlock_t statelock
;
449 u16 cmd_reg_cache_int
;
453 u8 mcast_lst
[MAX_MCAST_LST
][ETH_ALEN
];
454 u8 mcast_bits
[HW_MCAST_SIZE
];
461 static int msg_enable
;
463 #define BE3 0x8000 /* Byte Enable 3 */
464 #define BE2 0x4000 /* Byte Enable 2 */
465 #define BE1 0x2000 /* Byte Enable 1 */
466 #define BE0 0x1000 /* Byte Enable 0 */
469 * register read/write calls.
471 * All these calls issue transactions to access the chip's registers. They
472 * all require that the necessary lock is held to prevent accesses when the
473 * chip is busy transferring packet data (RX/TX FIFO accesses).
477 * ks_rdreg8 - read 8 bit register from device
478 * @ks : The chip information
479 * @offset: The register address
481 * Read a 8bit register from the chip, returning the result
483 static u8
ks_rdreg8(struct ks_net
*ks
, int offset
)
486 u8 shift_bit
= offset
& 0x03;
487 u8 shift_data
= (offset
& 1) << 3;
488 ks
->cmd_reg_cache
= (u16
) offset
| (u16
)(BE0
<< shift_bit
);
489 iowrite16(ks
->cmd_reg_cache
, ks
->hw_addr_cmd
);
490 data
= ioread16(ks
->hw_addr
);
491 return (u8
)(data
>> shift_data
);
495 * ks_rdreg16 - read 16 bit register from device
496 * @ks : The chip information
497 * @offset: The register address
499 * Read a 16bit register from the chip, returning the result
502 static u16
ks_rdreg16(struct ks_net
*ks
, int offset
)
504 ks
->cmd_reg_cache
= (u16
)offset
| ((BE1
| BE0
) << (offset
& 0x02));
505 iowrite16(ks
->cmd_reg_cache
, ks
->hw_addr_cmd
);
506 return ioread16(ks
->hw_addr
);
510 * ks_wrreg8 - write 8bit register value to chip
511 * @ks: The chip information
512 * @offset: The register address
513 * @value: The value to write
516 static void ks_wrreg8(struct ks_net
*ks
, int offset
, u8 value
)
518 u8 shift_bit
= (offset
& 0x03);
519 u16 value_write
= (u16
)(value
<< ((offset
& 1) << 3));
520 ks
->cmd_reg_cache
= (u16
)offset
| (BE0
<< shift_bit
);
521 iowrite16(ks
->cmd_reg_cache
, ks
->hw_addr_cmd
);
522 iowrite16(value_write
, ks
->hw_addr
);
526 * ks_wrreg16 - write 16bit register value to chip
527 * @ks: The chip information
528 * @offset: The register address
529 * @value: The value to write
533 static void ks_wrreg16(struct ks_net
*ks
, int offset
, u16 value
)
535 ks
->cmd_reg_cache
= (u16
)offset
| ((BE1
| BE0
) << (offset
& 0x02));
536 iowrite16(ks
->cmd_reg_cache
, ks
->hw_addr_cmd
);
537 iowrite16(value
, ks
->hw_addr
);
541 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode enabled.
542 * @ks: The chip state
543 * @wptr: buffer address to save data
544 * @len: length in byte to read
547 static inline void ks_inblk(struct ks_net
*ks
, u16
*wptr
, u32 len
)
551 *wptr
++ = (u16
)ioread16(ks
->hw_addr
);
555 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
556 * @ks: The chip information
557 * @wptr: buffer address
558 * @len: length in byte to write
561 static inline void ks_outblk(struct ks_net
*ks
, u16
*wptr
, u32 len
)
565 iowrite16(*wptr
++, ks
->hw_addr
);
568 static void ks_disable_int(struct ks_net
*ks
)
570 ks_wrreg16(ks
, KS_IER
, 0x0000);
571 } /* ks_disable_int */
573 static void ks_enable_int(struct ks_net
*ks
)
575 ks_wrreg16(ks
, KS_IER
, ks
->rc_ier
);
576 } /* ks_enable_int */
579 * ks_tx_fifo_space - return the available hardware buffer size.
580 * @ks: The chip information
583 static inline u16
ks_tx_fifo_space(struct ks_net
*ks
)
585 return ks_rdreg16(ks
, KS_TXMIR
) & 0x1fff;
589 * ks_save_cmd_reg - save the command register from the cache.
590 * @ks: The chip information
593 static inline void ks_save_cmd_reg(struct ks_net
*ks
)
595 /*ks8851 MLL has a bug to read back the command register.
596 * So rely on software to save the content of command register.
598 ks
->cmd_reg_cache_int
= ks
->cmd_reg_cache
;
602 * ks_restore_cmd_reg - restore the command register from the cache and
603 * write to hardware register.
604 * @ks: The chip information
607 static inline void ks_restore_cmd_reg(struct ks_net
*ks
)
609 ks
->cmd_reg_cache
= ks
->cmd_reg_cache_int
;
610 iowrite16(ks
->cmd_reg_cache
, ks
->hw_addr_cmd
);
614 * ks_set_powermode - set power mode of the device
615 * @ks: The chip information
616 * @pwrmode: The power mode value to write to KS_PMECR.
618 * Change the power mode of the chip.
620 static void ks_set_powermode(struct ks_net
*ks
, unsigned pwrmode
)
624 netif_dbg(ks
, hw
, ks
->netdev
, "setting power mode %d\n", pwrmode
);
626 ks_rdreg16(ks
, KS_GRR
);
627 pmecr
= ks_rdreg16(ks
, KS_PMECR
);
628 pmecr
&= ~PMECR_PM_MASK
;
631 ks_wrreg16(ks
, KS_PMECR
, pmecr
);
635 * ks_read_config - read chip configuration of bus width.
636 * @ks: The chip information
639 static void ks_read_config(struct ks_net
*ks
)
643 /* Regardless of bus width, 8 bit read should always work.*/
644 reg_data
= ks_rdreg8(ks
, KS_CCR
) & 0x00FF;
645 reg_data
|= ks_rdreg8(ks
, KS_CCR
+1) << 8;
647 /* addr/data bus are multiplexed */
648 ks
->sharedbus
= (reg_data
& CCR_SHARED
) == CCR_SHARED
;
650 /* There are garbage data when reading data from QMU,
651 depending on bus-width.
654 if (reg_data
& CCR_8BIT
) {
655 ks
->bus_width
= ENUM_BUS_8BIT
;
657 } else if (reg_data
& CCR_16BIT
) {
658 ks
->bus_width
= ENUM_BUS_16BIT
;
661 ks
->bus_width
= ENUM_BUS_32BIT
;
667 * ks_soft_reset - issue one of the soft reset to the device
668 * @ks: The device state.
669 * @op: The bit(s) to set in the GRR
671 * Issue the relevant soft-reset command to the device's GRR register
674 * Note, the delays are in there as a caution to ensure that the reset
675 * has time to take effect and then complete. Since the datasheet does
676 * not currently specify the exact sequence, we have chosen something
677 * that seems to work with our device.
679 static void ks_soft_reset(struct ks_net
*ks
, unsigned op
)
681 /* Disable interrupt first */
682 ks_wrreg16(ks
, KS_IER
, 0x0000);
683 ks_wrreg16(ks
, KS_GRR
, op
);
684 mdelay(10); /* wait a short time to effect reset */
685 ks_wrreg16(ks
, KS_GRR
, 0);
686 mdelay(1); /* wait for condition to clear */
690 void ks_enable_qmu(struct ks_net
*ks
)
694 w
= ks_rdreg16(ks
, KS_TXCR
);
695 /* Enables QMU Transmit (TXCR). */
696 ks_wrreg16(ks
, KS_TXCR
, w
| TXCR_TXE
);
699 * RX Frame Count Threshold Enable and Auto-Dequeue RXQ Frame
703 w
= ks_rdreg16(ks
, KS_RXQCR
);
704 ks_wrreg16(ks
, KS_RXQCR
, w
| RXQCR_RXFCTE
);
706 /* Enables QMU Receive (RXCR1). */
707 w
= ks_rdreg16(ks
, KS_RXCR1
);
708 ks_wrreg16(ks
, KS_RXCR1
, w
| RXCR1_RXE
);
710 } /* ks_enable_qmu */
712 static void ks_disable_qmu(struct ks_net
*ks
)
716 w
= ks_rdreg16(ks
, KS_TXCR
);
718 /* Disables QMU Transmit (TXCR). */
720 ks_wrreg16(ks
, KS_TXCR
, w
);
722 /* Disables QMU Receive (RXCR1). */
723 w
= ks_rdreg16(ks
, KS_RXCR1
);
725 ks_wrreg16(ks
, KS_RXCR1
, w
);
729 } /* ks_disable_qmu */
732 * ks_read_qmu - read 1 pkt data from the QMU.
733 * @ks: The chip information
734 * @buf: buffer address to save 1 pkt
736 * Here is the sequence to read 1 pkt:
737 * 1. set sudo DMA mode
738 * 2. read prepend data
740 * 4. reset sudo DMA Mode
742 static inline void ks_read_qmu(struct ks_net
*ks
, u16
*buf
, u32 len
)
744 u32 r
= ks
->extra_byte
& 0x1 ;
745 u32 w
= ks
->extra_byte
- r
;
747 /* 1. set sudo DMA mode */
748 ks_wrreg16(ks
, KS_RXFDPR
, RXFDPR_RXFPAI
);
749 ks_wrreg8(ks
, KS_RXQCR
, (ks
->rc_rxqcr
| RXQCR_SDA
) & 0xff);
751 /* 2. read prepend data */
753 * read 4 + extra bytes and discard them.
754 * extra bytes for dummy, 2 for status, 2 for len
757 /* use likely(r) for 8 bit access for performance */
759 ioread8(ks
->hw_addr
);
760 ks_inblk(ks
, buf
, w
+ 2 + 2);
762 /* 3. read pkt data */
763 ks_inblk(ks
, buf
, ALIGN(len
, 4));
765 /* 4. reset sudo DMA Mode */
766 ks_wrreg8(ks
, KS_RXQCR
, ks
->rc_rxqcr
);
770 * ks_rcv - read multiple pkts data from the QMU.
771 * @ks: The chip information
772 * @netdev: The network device being opened.
774 * Read all of header information before reading pkt content.
775 * It is not allowed only port of pkts in QMU after issuing
778 static void ks_rcv(struct ks_net
*ks
, struct net_device
*netdev
)
781 struct type_frame_head
*frame_hdr
= ks
->frame_head_info
;
784 ks
->frame_cnt
= ks_rdreg16(ks
, KS_RXFCTR
) >> 8;
786 /* read all header information */
787 for (i
= 0; i
< ks
->frame_cnt
; i
++) {
788 /* Checking Received packet status */
789 frame_hdr
->sts
= ks_rdreg16(ks
, KS_RXFHSR
);
790 /* Get packet len from hardware */
791 frame_hdr
->len
= ks_rdreg16(ks
, KS_RXFHBCR
);
795 frame_hdr
= ks
->frame_head_info
;
796 while (ks
->frame_cnt
--) {
797 skb
= dev_alloc_skb(frame_hdr
->len
+ 16);
798 if (likely(skb
&& (frame_hdr
->sts
& RXFSHR_RXFV
) &&
799 (frame_hdr
->len
< RX_BUF_SIZE
) && frame_hdr
->len
)) {
801 /* read data block including CRC 4 bytes */
802 ks_read_qmu(ks
, (u16
*)skb
->data
, frame_hdr
->len
);
803 skb_put(skb
, frame_hdr
->len
);
804 skb
->protocol
= eth_type_trans(skb
, netdev
);
807 pr_err("%s: err:skb alloc\n", __func__
);
808 ks_wrreg16(ks
, KS_RXQCR
, (ks
->rc_rxqcr
| RXQCR_RRXEF
));
810 dev_kfree_skb_irq(skb
);
817 * ks_update_link_status - link status update.
818 * @netdev: The network device being opened.
819 * @ks: The chip information
823 static void ks_update_link_status(struct net_device
*netdev
, struct ks_net
*ks
)
825 /* check the status of the link */
827 if (ks_rdreg16(ks
, KS_P1SR
) & P1SR_LINK_GOOD
) {
828 netif_carrier_on(netdev
);
829 link_up_status
= true;
831 netif_carrier_off(netdev
);
832 link_up_status
= false;
834 netif_dbg(ks
, link
, ks
->netdev
,
835 "%s: %s\n", __func__
, link_up_status
? "UP" : "DOWN");
839 * ks_irq - device interrupt handler
840 * @irq: Interrupt number passed from the IRQ hnalder.
841 * @pw: The private word passed to register_irq(), our struct ks_net.
843 * This is the handler invoked to find out what happened
845 * Read the interrupt status, work out what needs to be done and then clear
846 * any of the interrupts that are not needed.
849 static irqreturn_t
ks_irq(int irq
, void *pw
)
851 struct net_device
*netdev
= pw
;
852 struct ks_net
*ks
= netdev_priv(netdev
);
855 /*this should be the first in IRQ handler */
858 status
= ks_rdreg16(ks
, KS_ISR
);
859 if (unlikely(!status
)) {
860 ks_restore_cmd_reg(ks
);
864 ks_wrreg16(ks
, KS_ISR
, status
);
866 if (likely(status
& IRQ_RXI
))
869 if (unlikely(status
& IRQ_LCI
))
870 ks_update_link_status(netdev
, ks
);
872 if (unlikely(status
& IRQ_TXI
))
873 netif_wake_queue(netdev
);
875 if (unlikely(status
& IRQ_LDI
)) {
877 u16 pmecr
= ks_rdreg16(ks
, KS_PMECR
);
878 pmecr
&= ~PMECR_WKEVT_MASK
;
879 ks_wrreg16(ks
, KS_PMECR
, pmecr
| PMECR_WKEVT_LINK
);
882 /* this should be the last in IRQ handler*/
883 ks_restore_cmd_reg(ks
);
889 * ks_net_open - open network device
890 * @netdev: The network device being opened.
892 * Called when the network device is marked active, such as a user executing
893 * 'ifconfig up' on the device.
895 static int ks_net_open(struct net_device
*netdev
)
897 struct ks_net
*ks
= netdev_priv(netdev
);
900 #define KS_INT_FLAGS (IRQF_DISABLED|IRQF_TRIGGER_LOW)
901 /* lock the card, even if we may not actually do anything
902 * else at the moment.
905 netif_dbg(ks
, ifup
, ks
->netdev
, "%s - entry\n", __func__
);
908 err
= request_irq(netdev
->irq
, ks_irq
, KS_INT_FLAGS
, DRV_NAME
, netdev
);
911 pr_err("Failed to request IRQ: %d: %d\n", netdev
->irq
, err
);
915 /* wake up powermode to normal mode */
916 ks_set_powermode(ks
, PMECR_PM_NORMAL
);
917 mdelay(1); /* wait for normal mode to take effect */
919 ks_wrreg16(ks
, KS_ISR
, 0xffff);
922 netif_start_queue(ks
->netdev
);
924 netif_dbg(ks
, ifup
, ks
->netdev
, "network device up\n");
930 * ks_net_stop - close network device
931 * @netdev: The device being closed.
933 * Called to close down a network device which has been active. Cancell any
934 * work, shutdown the RX and TX process and then place the chip into a low
935 * power state whilst it is not being used.
937 static int ks_net_stop(struct net_device
*netdev
)
939 struct ks_net
*ks
= netdev_priv(netdev
);
941 netif_info(ks
, ifdown
, netdev
, "shutting down\n");
943 netif_stop_queue(netdev
);
945 mutex_lock(&ks
->lock
);
947 /* turn off the IRQs and ack any outstanding */
948 ks_wrreg16(ks
, KS_IER
, 0x0000);
949 ks_wrreg16(ks
, KS_ISR
, 0xffff);
951 /* shutdown RX/TX QMU */
954 /* set powermode to soft power down to save power */
955 ks_set_powermode(ks
, PMECR_PM_SOFTDOWN
);
956 free_irq(netdev
->irq
, netdev
);
957 mutex_unlock(&ks
->lock
);
963 * ks_write_qmu - write 1 pkt data to the QMU.
964 * @ks: The chip information
965 * @pdata: buffer address to save 1 pkt
966 * @len: Pkt length in byte
967 * Here is the sequence to write 1 pkt:
968 * 1. set sudo DMA mode
969 * 2. write status/length
971 * 4. reset sudo DMA Mode
972 * 5. reset sudo DMA mode
973 * 6. Wait until pkt is out
975 static void ks_write_qmu(struct ks_net
*ks
, u8
*pdata
, u16 len
)
977 /* start header at txb[0] to align txw entries */
979 ks
->txh
.txw
[1] = cpu_to_le16(len
);
981 /* 1. set sudo-DMA mode */
982 ks_wrreg8(ks
, KS_RXQCR
, (ks
->rc_rxqcr
| RXQCR_SDA
) & 0xff);
983 /* 2. write status/lenth info */
984 ks_outblk(ks
, ks
->txh
.txw
, 4);
985 /* 3. write pkt data */
986 ks_outblk(ks
, (u16
*)pdata
, ALIGN(len
, 4));
987 /* 4. reset sudo-DMA mode */
988 ks_wrreg8(ks
, KS_RXQCR
, ks
->rc_rxqcr
);
989 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
990 ks_wrreg16(ks
, KS_TXQCR
, TXQCR_METFE
);
991 /* 6. wait until TXQCR_METFE is auto-cleared */
992 while (ks_rdreg16(ks
, KS_TXQCR
) & TXQCR_METFE
)
997 * ks_start_xmit - transmit packet
998 * @skb : The buffer to transmit
999 * @netdev : The device used to transmit the packet.
1001 * Called by the network layer to transmit the @skb.
1002 * spin_lock_irqsave is required because tx and rx should be mutual exclusive.
1003 * So while tx is in-progress, prevent IRQ interrupt from happenning.
1005 static int ks_start_xmit(struct sk_buff
*skb
, struct net_device
*netdev
)
1007 int retv
= NETDEV_TX_OK
;
1008 struct ks_net
*ks
= netdev_priv(netdev
);
1010 disable_irq(netdev
->irq
);
1012 spin_lock(&ks
->statelock
);
1014 /* Extra space are required:
1015 * 4 byte for alignment, 4 for status/length, 4 for CRC
1018 if (likely(ks_tx_fifo_space(ks
) >= skb
->len
+ 12)) {
1019 ks_write_qmu(ks
, skb
->data
, skb
->len
);
1022 retv
= NETDEV_TX_BUSY
;
1023 spin_unlock(&ks
->statelock
);
1025 enable_irq(netdev
->irq
);
1030 * ks_start_rx - ready to serve pkts
1031 * @ks : The chip information
1034 static void ks_start_rx(struct ks_net
*ks
)
1038 /* Enables QMU Receive (RXCR1). */
1039 cntl
= ks_rdreg16(ks
, KS_RXCR1
);
1041 ks_wrreg16(ks
, KS_RXCR1
, cntl
);
1045 * ks_stop_rx - stop to serve pkts
1046 * @ks : The chip information
1049 static void ks_stop_rx(struct ks_net
*ks
)
1053 /* Disables QMU Receive (RXCR1). */
1054 cntl
= ks_rdreg16(ks
, KS_RXCR1
);
1055 cntl
&= ~RXCR1_RXE
;
1056 ks_wrreg16(ks
, KS_RXCR1
, cntl
);
1060 static unsigned long const ethernet_polynomial
= 0x04c11db7U
;
1062 static unsigned long ether_gen_crc(int length
, u8
*data
)
1065 while (--length
>= 0) {
1066 u8 current_octet
= *data
++;
1069 for (bit
= 0; bit
< 8; bit
++, current_octet
>>= 1) {
1071 ((crc
< 0) ^ (current_octet
& 1) ?
1072 ethernet_polynomial
: 0);
1075 return (unsigned long)crc
;
1076 } /* ether_gen_crc */
1079 * ks_set_grpaddr - set multicast information
1080 * @ks : The chip information
1083 static void ks_set_grpaddr(struct ks_net
*ks
)
1086 u32 index
, position
, value
;
1088 memset(ks
->mcast_bits
, 0, sizeof(u8
) * HW_MCAST_SIZE
);
1090 for (i
= 0; i
< ks
->mcast_lst_size
; i
++) {
1091 position
= (ether_gen_crc(6, ks
->mcast_lst
[i
]) >> 26) & 0x3f;
1092 index
= position
>> 3;
1093 value
= 1 << (position
& 7);
1094 ks
->mcast_bits
[index
] |= (u8
)value
;
1097 for (i
= 0; i
< HW_MCAST_SIZE
; i
++) {
1099 ks_wrreg16(ks
, (u16
)((KS_MAHTR0
+ i
) & ~1),
1100 (ks
->mcast_bits
[i
] << 8) |
1101 ks
->mcast_bits
[i
- 1]);
1104 } /* ks_set_grpaddr */
1107 * ks_clear_mcast - clear multicast information
1109 * @ks : The chip information
1110 * This routine removes all mcast addresses set in the hardware.
1113 static void ks_clear_mcast(struct ks_net
*ks
)
1116 for (i
= 0; i
< HW_MCAST_SIZE
; i
++)
1117 ks
->mcast_bits
[i
] = 0;
1119 mcast_size
= HW_MCAST_SIZE
>> 2;
1120 for (i
= 0; i
< mcast_size
; i
++)
1121 ks_wrreg16(ks
, KS_MAHTR0
+ (2*i
), 0);
1124 static void ks_set_promis(struct ks_net
*ks
, u16 promiscuous_mode
)
1127 ks
->promiscuous
= promiscuous_mode
;
1128 ks_stop_rx(ks
); /* Stop receiving for reconfiguration */
1129 cntl
= ks_rdreg16(ks
, KS_RXCR1
);
1131 cntl
&= ~RXCR1_FILTER_MASK
;
1132 if (promiscuous_mode
)
1133 /* Enable Promiscuous mode */
1134 cntl
|= RXCR1_RXAE
| RXCR1_RXINVF
;
1136 /* Disable Promiscuous mode (default normal mode) */
1137 cntl
|= RXCR1_RXPAFMA
;
1139 ks_wrreg16(ks
, KS_RXCR1
, cntl
);
1144 } /* ks_set_promis */
1146 static void ks_set_mcast(struct ks_net
*ks
, u16 mcast
)
1150 ks
->all_mcast
= mcast
;
1151 ks_stop_rx(ks
); /* Stop receiving for reconfiguration */
1152 cntl
= ks_rdreg16(ks
, KS_RXCR1
);
1153 cntl
&= ~RXCR1_FILTER_MASK
;
1155 /* Enable "Perfect with Multicast address passed mode" */
1156 cntl
|= (RXCR1_RXAE
| RXCR1_RXMAFMA
| RXCR1_RXPAFMA
);
1159 * Disable "Perfect with Multicast address passed
1160 * mode" (normal mode).
1162 cntl
|= RXCR1_RXPAFMA
;
1164 ks_wrreg16(ks
, KS_RXCR1
, cntl
);
1168 } /* ks_set_mcast */
1170 static void ks_set_rx_mode(struct net_device
*netdev
)
1172 struct ks_net
*ks
= netdev_priv(netdev
);
1173 struct netdev_hw_addr
*ha
;
1175 /* Turn on/off promiscuous mode. */
1176 if ((netdev
->flags
& IFF_PROMISC
) == IFF_PROMISC
)
1178 (u16
)((netdev
->flags
& IFF_PROMISC
) == IFF_PROMISC
));
1179 /* Turn on/off all mcast mode. */
1180 else if ((netdev
->flags
& IFF_ALLMULTI
) == IFF_ALLMULTI
)
1182 (u16
)((netdev
->flags
& IFF_ALLMULTI
) == IFF_ALLMULTI
));
1184 ks_set_promis(ks
, false);
1186 if ((netdev
->flags
& IFF_MULTICAST
) && netdev_mc_count(netdev
)) {
1187 if (netdev_mc_count(netdev
) <= MAX_MCAST_LST
) {
1190 netdev_for_each_mc_addr(ha
, netdev
) {
1191 if (i
>= MAX_MCAST_LST
)
1193 memcpy(ks
->mcast_lst
[i
++], ha
->addr
, ETH_ALEN
);
1195 ks
->mcast_lst_size
= (u8
)i
;
1199 * List too big to support so
1200 * turn on all mcast mode.
1202 ks
->mcast_lst_size
= MAX_MCAST_LST
;
1203 ks_set_mcast(ks
, true);
1206 ks
->mcast_lst_size
= 0;
1209 } /* ks_set_rx_mode */
1211 static void ks_set_mac(struct ks_net
*ks
, u8
*data
)
1213 u16
*pw
= (u16
*)data
;
1216 ks_stop_rx(ks
); /* Stop receiving for reconfiguration */
1219 w
= ((u
& 0xFF) << 8) | ((u
>> 8) & 0xFF);
1220 ks_wrreg16(ks
, KS_MARH
, w
);
1223 w
= ((u
& 0xFF) << 8) | ((u
>> 8) & 0xFF);
1224 ks_wrreg16(ks
, KS_MARM
, w
);
1227 w
= ((u
& 0xFF) << 8) | ((u
>> 8) & 0xFF);
1228 ks_wrreg16(ks
, KS_MARL
, w
);
1230 memcpy(ks
->mac_addr
, data
, 6);
1236 static int ks_set_mac_address(struct net_device
*netdev
, void *paddr
)
1238 struct ks_net
*ks
= netdev_priv(netdev
);
1239 struct sockaddr
*addr
= paddr
;
1242 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
1244 da
= (u8
*)netdev
->dev_addr
;
1250 static int ks_net_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
1252 struct ks_net
*ks
= netdev_priv(netdev
);
1254 if (!netif_running(netdev
))
1257 return generic_mii_ioctl(&ks
->mii
, if_mii(req
), cmd
, NULL
);
1260 static const struct net_device_ops ks_netdev_ops
= {
1261 .ndo_open
= ks_net_open
,
1262 .ndo_stop
= ks_net_stop
,
1263 .ndo_do_ioctl
= ks_net_ioctl
,
1264 .ndo_start_xmit
= ks_start_xmit
,
1265 .ndo_set_mac_address
= ks_set_mac_address
,
1266 .ndo_set_rx_mode
= ks_set_rx_mode
,
1267 .ndo_change_mtu
= eth_change_mtu
,
1268 .ndo_validate_addr
= eth_validate_addr
,
1271 /* ethtool support */
1273 static void ks_get_drvinfo(struct net_device
*netdev
,
1274 struct ethtool_drvinfo
*di
)
1276 strlcpy(di
->driver
, DRV_NAME
, sizeof(di
->driver
));
1277 strlcpy(di
->version
, "1.00", sizeof(di
->version
));
1278 strlcpy(di
->bus_info
, dev_name(netdev
->dev
.parent
),
1279 sizeof(di
->bus_info
));
1282 static u32
ks_get_msglevel(struct net_device
*netdev
)
1284 struct ks_net
*ks
= netdev_priv(netdev
);
1285 return ks
->msg_enable
;
1288 static void ks_set_msglevel(struct net_device
*netdev
, u32 to
)
1290 struct ks_net
*ks
= netdev_priv(netdev
);
1291 ks
->msg_enable
= to
;
1294 static int ks_get_settings(struct net_device
*netdev
, struct ethtool_cmd
*cmd
)
1296 struct ks_net
*ks
= netdev_priv(netdev
);
1297 return mii_ethtool_gset(&ks
->mii
, cmd
);
1300 static int ks_set_settings(struct net_device
*netdev
, struct ethtool_cmd
*cmd
)
1302 struct ks_net
*ks
= netdev_priv(netdev
);
1303 return mii_ethtool_sset(&ks
->mii
, cmd
);
1306 static u32
ks_get_link(struct net_device
*netdev
)
1308 struct ks_net
*ks
= netdev_priv(netdev
);
1309 return mii_link_ok(&ks
->mii
);
1312 static int ks_nway_reset(struct net_device
*netdev
)
1314 struct ks_net
*ks
= netdev_priv(netdev
);
1315 return mii_nway_restart(&ks
->mii
);
1318 static const struct ethtool_ops ks_ethtool_ops
= {
1319 .get_drvinfo
= ks_get_drvinfo
,
1320 .get_msglevel
= ks_get_msglevel
,
1321 .set_msglevel
= ks_set_msglevel
,
1322 .get_settings
= ks_get_settings
,
1323 .set_settings
= ks_set_settings
,
1324 .get_link
= ks_get_link
,
1325 .nway_reset
= ks_nway_reset
,
1328 /* MII interface controls */
1331 * ks_phy_reg - convert MII register into a KS8851 register
1332 * @reg: MII register number.
1334 * Return the KS8851 register number for the corresponding MII PHY register
1335 * if possible. Return zero if the MII register has no direct mapping to the
1336 * KS8851 register set.
1338 static int ks_phy_reg(int reg
)
1359 * ks_phy_read - MII interface PHY register read.
1360 * @netdev: The network device the PHY is on.
1361 * @phy_addr: Address of PHY (ignored as we only have one)
1362 * @reg: The register to read.
1364 * This call reads data from the PHY register specified in @reg. Since the
1365 * device does not support all the MII registers, the non-existent values
1366 * are always returned as zero.
1368 * We return zero for unsupported registers as the MII code does not check
1369 * the value returned for any error status, and simply returns it to the
1370 * caller. The mii-tool that the driver was tested with takes any -ve error
1371 * as real PHY capabilities, thus displaying incorrect data to the user.
1373 static int ks_phy_read(struct net_device
*netdev
, int phy_addr
, int reg
)
1375 struct ks_net
*ks
= netdev_priv(netdev
);
1379 ksreg
= ks_phy_reg(reg
);
1381 return 0x0; /* no error return allowed, so use zero */
1383 mutex_lock(&ks
->lock
);
1384 result
= ks_rdreg16(ks
, ksreg
);
1385 mutex_unlock(&ks
->lock
);
1390 static void ks_phy_write(struct net_device
*netdev
,
1391 int phy
, int reg
, int value
)
1393 struct ks_net
*ks
= netdev_priv(netdev
);
1396 ksreg
= ks_phy_reg(reg
);
1398 mutex_lock(&ks
->lock
);
1399 ks_wrreg16(ks
, ksreg
, value
);
1400 mutex_unlock(&ks
->lock
);
1405 * ks_read_selftest - read the selftest memory info.
1406 * @ks: The device state
1408 * Read and check the TX/RX memory selftest information.
1410 static int ks_read_selftest(struct ks_net
*ks
)
1412 unsigned both_done
= MBIR_TXMBF
| MBIR_RXMBF
;
1416 rd
= ks_rdreg16(ks
, KS_MBIR
);
1418 if ((rd
& both_done
) != both_done
) {
1419 netdev_warn(ks
->netdev
, "Memory selftest not finished\n");
1423 if (rd
& MBIR_TXMBFA
) {
1424 netdev_err(ks
->netdev
, "TX memory selftest fails\n");
1428 if (rd
& MBIR_RXMBFA
) {
1429 netdev_err(ks
->netdev
, "RX memory selftest fails\n");
1433 netdev_info(ks
->netdev
, "the selftest passes\n");
1437 static void ks_setup(struct ks_net
*ks
)
1442 * Configure QMU Transmit
1445 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
1446 ks_wrreg16(ks
, KS_TXFDPR
, TXFDPR_TXFPAI
);
1448 /* Setup Receive Frame Data Pointer Auto-Increment */
1449 ks_wrreg16(ks
, KS_RXFDPR
, RXFDPR_RXFPAI
);
1451 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
1452 ks_wrreg16(ks
, KS_RXFCTR
, 1 & RXFCTR_THRESHOLD_MASK
);
1454 /* Setup RxQ Command Control (RXQCR) */
1455 ks
->rc_rxqcr
= RXQCR_CMD_CNTL
;
1456 ks_wrreg16(ks
, KS_RXQCR
, ks
->rc_rxqcr
);
1459 * set the force mode to half duplex, default is full duplex
1460 * because if the auto-negotiation fails, most switch uses
1464 w
= ks_rdreg16(ks
, KS_P1MBCR
);
1465 w
&= ~P1MBCR_FORCE_FDX
;
1466 ks_wrreg16(ks
, KS_P1MBCR
, w
);
1468 w
= TXCR_TXFCE
| TXCR_TXPE
| TXCR_TXCRC
| TXCR_TCGIP
;
1469 ks_wrreg16(ks
, KS_TXCR
, w
);
1471 w
= RXCR1_RXFCE
| RXCR1_RXBE
| RXCR1_RXUE
| RXCR1_RXME
| RXCR1_RXIPFCC
;
1473 if (ks
->promiscuous
) /* bPromiscuous */
1474 w
|= (RXCR1_RXAE
| RXCR1_RXINVF
);
1475 else if (ks
->all_mcast
) /* Multicast address passed mode */
1476 w
|= (RXCR1_RXAE
| RXCR1_RXMAFMA
| RXCR1_RXPAFMA
);
1477 else /* Normal mode */
1480 ks_wrreg16(ks
, KS_RXCR1
, w
);
1484 static void ks_setup_int(struct ks_net
*ks
)
1487 /* Clear the interrupts status of the hardware. */
1488 ks_wrreg16(ks
, KS_ISR
, 0xffff);
1490 /* Enables the interrupts of the hardware. */
1491 ks
->rc_ier
= (IRQ_LCI
| IRQ_TXI
| IRQ_RXI
);
1492 } /* ks_setup_int */
1494 static int ks_hw_init(struct ks_net
*ks
)
1496 #define MHEADER_SIZE (sizeof(struct type_frame_head) * MAX_RECV_FRAMES)
1497 ks
->promiscuous
= 0;
1499 ks
->mcast_lst_size
= 0;
1501 ks
->frame_head_info
= kmalloc(MHEADER_SIZE
, GFP_KERNEL
);
1502 if (!ks
->frame_head_info
) {
1503 pr_err("Error: Fail to allocate frame memory\n");
1507 ks_set_mac(ks
, KS_DEFAULT_MAC_ADDRESS
);
1512 static int __devinit
ks8851_probe(struct platform_device
*pdev
)
1515 struct resource
*io_d
, *io_c
;
1516 struct net_device
*netdev
;
1520 io_d
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1521 io_c
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1523 if (!request_mem_region(io_d
->start
, resource_size(io_d
), DRV_NAME
))
1524 goto err_mem_region
;
1526 if (!request_mem_region(io_c
->start
, resource_size(io_c
), DRV_NAME
))
1527 goto err_mem_region1
;
1529 netdev
= alloc_etherdev(sizeof(struct ks_net
));
1531 goto err_alloc_etherdev
;
1533 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
1535 ks
= netdev_priv(netdev
);
1536 ks
->netdev
= netdev
;
1537 ks
->hw_addr
= ioremap(io_d
->start
, resource_size(io_d
));
1542 ks
->hw_addr_cmd
= ioremap(io_c
->start
, resource_size(io_c
));
1543 if (!ks
->hw_addr_cmd
)
1546 netdev
->irq
= platform_get_irq(pdev
, 0);
1548 if ((int)netdev
->irq
< 0) {
1555 mutex_init(&ks
->lock
);
1556 spin_lock_init(&ks
->statelock
);
1558 netdev
->netdev_ops
= &ks_netdev_ops
;
1559 netdev
->ethtool_ops
= &ks_ethtool_ops
;
1561 /* setup mii state */
1562 ks
->mii
.dev
= netdev
;
1564 ks
->mii
.phy_id_mask
= 1;
1565 ks
->mii
.reg_num_mask
= 0xf;
1566 ks
->mii
.mdio_read
= ks_phy_read
;
1567 ks
->mii
.mdio_write
= ks_phy_write
;
1569 netdev_info(netdev
, "message enable is %d\n", msg_enable
);
1570 /* set the default message enable */
1571 ks
->msg_enable
= netif_msg_init(msg_enable
, (NETIF_MSG_DRV
|
1576 /* simple check for a valid chip being connected to the bus */
1577 if ((ks_rdreg16(ks
, KS_CIDER
) & ~CIDER_REV_MASK
) != CIDER_ID
) {
1578 netdev_err(netdev
, "failed to read device ID\n");
1583 if (ks_read_selftest(ks
)) {
1584 netdev_err(netdev
, "failed to read device ID\n");
1589 err
= register_netdev(netdev
);
1593 platform_set_drvdata(pdev
, netdev
);
1595 ks_soft_reset(ks
, GRR_GSR
);
1600 memcpy(netdev
->dev_addr
, ks
->mac_addr
, 6);
1602 data
= ks_rdreg16(ks
, KS_OBCR
);
1603 ks_wrreg16(ks
, KS_OBCR
, data
| OBCR_ODS_16MA
);
1606 * If you want to use the default MAC addr,
1607 * comment out the 2 functions below.
1610 random_ether_addr(netdev
->dev_addr
);
1611 ks_set_mac(ks
, netdev
->dev_addr
);
1613 id
= ks_rdreg16(ks
, KS_CIDER
);
1615 netdev_info(netdev
, "Found chip, family: 0x%x, id: 0x%x, rev: 0x%x\n",
1616 (id
>> 8) & 0xff, (id
>> 4) & 0xf, (id
>> 1) & 0x7);
1621 iounmap(ks
->hw_addr_cmd
);
1623 iounmap(ks
->hw_addr
);
1625 free_netdev(netdev
);
1627 release_mem_region(io_c
->start
, resource_size(io_c
));
1629 release_mem_region(io_d
->start
, resource_size(io_d
));
1634 static int __devexit
ks8851_remove(struct platform_device
*pdev
)
1636 struct net_device
*netdev
= platform_get_drvdata(pdev
);
1637 struct ks_net
*ks
= netdev_priv(netdev
);
1638 struct resource
*iomem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1640 kfree(ks
->frame_head_info
);
1641 unregister_netdev(netdev
);
1642 iounmap(ks
->hw_addr
);
1643 free_netdev(netdev
);
1644 release_mem_region(iomem
->start
, resource_size(iomem
));
1645 platform_set_drvdata(pdev
, NULL
);
1650 static struct platform_driver ks8851_platform_driver
= {
1653 .owner
= THIS_MODULE
,
1655 .probe
= ks8851_probe
,
1656 .remove
= __devexit_p(ks8851_remove
),
1659 module_platform_driver(ks8851_platform_driver
);
1661 MODULE_DESCRIPTION("KS8851 MLL Network driver");
1662 MODULE_AUTHOR("David Choi <david.choi@micrel.com>");
1663 MODULE_LICENSE("GPL");
1664 module_param_named(message
, msg_enable
, int, 0);
1665 MODULE_PARM_DESC(message
, "Message verbosity level (0=none, 31=all)");