2 * drivers/net/ethernet/micrel/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver
4 * Copyright (c) 2009-2010 Micrel, Inc.
5 * Tristram Ha <Tristram.Ha@micrel.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/ioport.h>
24 #include <linux/pci.h>
25 #include <linux/proc_fs.h>
26 #include <linux/mii.h>
27 #include <linux/platform_device.h>
28 #include <linux/ethtool.h>
29 #include <linux/etherdevice.h>
32 #include <linux/if_vlan.h>
33 #include <linux/crc32.h>
34 #include <linux/sched.h>
35 #include <linux/slab.h>
40 #define KS_DMA_TX_CTRL 0x0000
41 #define DMA_TX_ENABLE 0x00000001
42 #define DMA_TX_CRC_ENABLE 0x00000002
43 #define DMA_TX_PAD_ENABLE 0x00000004
44 #define DMA_TX_LOOPBACK 0x00000100
45 #define DMA_TX_FLOW_ENABLE 0x00000200
46 #define DMA_TX_CSUM_IP 0x00010000
47 #define DMA_TX_CSUM_TCP 0x00020000
48 #define DMA_TX_CSUM_UDP 0x00040000
49 #define DMA_TX_BURST_SIZE 0x3F000000
51 #define KS_DMA_RX_CTRL 0x0004
52 #define DMA_RX_ENABLE 0x00000001
53 #define KS884X_DMA_RX_MULTICAST 0x00000002
54 #define DMA_RX_PROMISCUOUS 0x00000004
55 #define DMA_RX_ERROR 0x00000008
56 #define DMA_RX_UNICAST 0x00000010
57 #define DMA_RX_ALL_MULTICAST 0x00000020
58 #define DMA_RX_BROADCAST 0x00000040
59 #define DMA_RX_FLOW_ENABLE 0x00000200
60 #define DMA_RX_CSUM_IP 0x00010000
61 #define DMA_RX_CSUM_TCP 0x00020000
62 #define DMA_RX_CSUM_UDP 0x00040000
63 #define DMA_RX_BURST_SIZE 0x3F000000
65 #define DMA_BURST_SHIFT 24
66 #define DMA_BURST_DEFAULT 8
68 #define KS_DMA_TX_START 0x0008
69 #define KS_DMA_RX_START 0x000C
70 #define DMA_START 0x00000001
72 #define KS_DMA_TX_ADDR 0x0010
73 #define KS_DMA_RX_ADDR 0x0014
75 #define DMA_ADDR_LIST_MASK 0xFFFFFFFC
76 #define DMA_ADDR_LIST_SHIFT 2
79 #define KS884X_MULTICAST_0_OFFSET 0x0020
80 #define KS884X_MULTICAST_1_OFFSET 0x0021
81 #define KS884X_MULTICAST_2_OFFSET 0x0022
82 #define KS884x_MULTICAST_3_OFFSET 0x0023
84 #define KS884X_MULTICAST_4_OFFSET 0x0024
85 #define KS884X_MULTICAST_5_OFFSET 0x0025
86 #define KS884X_MULTICAST_6_OFFSET 0x0026
87 #define KS884X_MULTICAST_7_OFFSET 0x0027
89 /* Interrupt Registers */
92 #define KS884X_INTERRUPTS_ENABLE 0x0028
94 #define KS884X_INTERRUPTS_STATUS 0x002C
96 #define KS884X_INT_RX_STOPPED 0x02000000
97 #define KS884X_INT_TX_STOPPED 0x04000000
98 #define KS884X_INT_RX_OVERRUN 0x08000000
99 #define KS884X_INT_TX_EMPTY 0x10000000
100 #define KS884X_INT_RX 0x20000000
101 #define KS884X_INT_TX 0x40000000
102 #define KS884X_INT_PHY 0x80000000
104 #define KS884X_INT_RX_MASK \
105 (KS884X_INT_RX | KS884X_INT_RX_OVERRUN)
106 #define KS884X_INT_TX_MASK \
107 (KS884X_INT_TX | KS884X_INT_TX_EMPTY)
108 #define KS884X_INT_MASK (KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY)
110 /* MAC Additional Station Address */
113 #define KS_ADD_ADDR_0_LO 0x0080
115 #define KS_ADD_ADDR_0_HI 0x0084
117 #define KS_ADD_ADDR_1_LO 0x0088
119 #define KS_ADD_ADDR_1_HI 0x008C
121 #define KS_ADD_ADDR_2_LO 0x0090
123 #define KS_ADD_ADDR_2_HI 0x0094
125 #define KS_ADD_ADDR_3_LO 0x0098
127 #define KS_ADD_ADDR_3_HI 0x009C
129 #define KS_ADD_ADDR_4_LO 0x00A0
131 #define KS_ADD_ADDR_4_HI 0x00A4
133 #define KS_ADD_ADDR_5_LO 0x00A8
135 #define KS_ADD_ADDR_5_HI 0x00AC
137 #define KS_ADD_ADDR_6_LO 0x00B0
139 #define KS_ADD_ADDR_6_HI 0x00B4
141 #define KS_ADD_ADDR_7_LO 0x00B8
143 #define KS_ADD_ADDR_7_HI 0x00BC
145 #define KS_ADD_ADDR_8_LO 0x00C0
147 #define KS_ADD_ADDR_8_HI 0x00C4
149 #define KS_ADD_ADDR_9_LO 0x00C8
151 #define KS_ADD_ADDR_9_HI 0x00CC
153 #define KS_ADD_ADDR_A_LO 0x00D0
155 #define KS_ADD_ADDR_A_HI 0x00D4
157 #define KS_ADD_ADDR_B_LO 0x00D8
159 #define KS_ADD_ADDR_B_HI 0x00DC
161 #define KS_ADD_ADDR_C_LO 0x00E0
163 #define KS_ADD_ADDR_C_HI 0x00E4
165 #define KS_ADD_ADDR_D_LO 0x00E8
167 #define KS_ADD_ADDR_D_HI 0x00EC
169 #define KS_ADD_ADDR_E_LO 0x00F0
171 #define KS_ADD_ADDR_E_HI 0x00F4
173 #define KS_ADD_ADDR_F_LO 0x00F8
175 #define KS_ADD_ADDR_F_HI 0x00FC
177 #define ADD_ADDR_HI_MASK 0x0000FFFF
178 #define ADD_ADDR_ENABLE 0x80000000
179 #define ADD_ADDR_INCR 8
181 /* Miscellaneous Registers */
184 #define KS884X_ADDR_0_OFFSET 0x0200
185 #define KS884X_ADDR_1_OFFSET 0x0201
187 #define KS884X_ADDR_2_OFFSET 0x0202
188 #define KS884X_ADDR_3_OFFSET 0x0203
190 #define KS884X_ADDR_4_OFFSET 0x0204
191 #define KS884X_ADDR_5_OFFSET 0x0205
194 #define KS884X_BUS_CTRL_OFFSET 0x0210
196 #define BUS_SPEED_125_MHZ 0x0000
197 #define BUS_SPEED_62_5_MHZ 0x0001
198 #define BUS_SPEED_41_66_MHZ 0x0002
199 #define BUS_SPEED_25_MHZ 0x0003
202 #define KS884X_EEPROM_CTRL_OFFSET 0x0212
204 #define EEPROM_CHIP_SELECT 0x0001
205 #define EEPROM_SERIAL_CLOCK 0x0002
206 #define EEPROM_DATA_OUT 0x0004
207 #define EEPROM_DATA_IN 0x0008
208 #define EEPROM_ACCESS_ENABLE 0x0010
211 #define KS884X_MEM_INFO_OFFSET 0x0214
213 #define RX_MEM_TEST_FAILED 0x0008
214 #define RX_MEM_TEST_FINISHED 0x0010
215 #define TX_MEM_TEST_FAILED 0x0800
216 #define TX_MEM_TEST_FINISHED 0x1000
219 #define KS884X_GLOBAL_CTRL_OFFSET 0x0216
220 #define GLOBAL_SOFTWARE_RESET 0x0001
222 #define KS8841_POWER_MANAGE_OFFSET 0x0218
225 #define KS8841_WOL_CTRL_OFFSET 0x021A
226 #define KS8841_WOL_MAGIC_ENABLE 0x0080
227 #define KS8841_WOL_FRAME3_ENABLE 0x0008
228 #define KS8841_WOL_FRAME2_ENABLE 0x0004
229 #define KS8841_WOL_FRAME1_ENABLE 0x0002
230 #define KS8841_WOL_FRAME0_ENABLE 0x0001
233 #define KS8841_WOL_FRAME_CRC_OFFSET 0x0220
234 #define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224
235 #define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228
238 #define KS884X_IACR_P 0x04A0
239 #define KS884X_IACR_OFFSET KS884X_IACR_P
242 #define KS884X_IADR1_P 0x04A2
243 #define KS884X_IADR2_P 0x04A4
244 #define KS884X_IADR3_P 0x04A6
245 #define KS884X_IADR4_P 0x04A8
246 #define KS884X_IADR5_P 0x04AA
248 #define KS884X_ACC_CTRL_SEL_OFFSET KS884X_IACR_P
249 #define KS884X_ACC_CTRL_INDEX_OFFSET (KS884X_ACC_CTRL_SEL_OFFSET + 1)
251 #define KS884X_ACC_DATA_0_OFFSET KS884X_IADR4_P
252 #define KS884X_ACC_DATA_1_OFFSET (KS884X_ACC_DATA_0_OFFSET + 1)
253 #define KS884X_ACC_DATA_2_OFFSET KS884X_IADR5_P
254 #define KS884X_ACC_DATA_3_OFFSET (KS884X_ACC_DATA_2_OFFSET + 1)
255 #define KS884X_ACC_DATA_4_OFFSET KS884X_IADR2_P
256 #define KS884X_ACC_DATA_5_OFFSET (KS884X_ACC_DATA_4_OFFSET + 1)
257 #define KS884X_ACC_DATA_6_OFFSET KS884X_IADR3_P
258 #define KS884X_ACC_DATA_7_OFFSET (KS884X_ACC_DATA_6_OFFSET + 1)
259 #define KS884X_ACC_DATA_8_OFFSET KS884X_IADR1_P
262 #define KS884X_P1MBCR_P 0x04D0
263 #define KS884X_P1MBSR_P 0x04D2
264 #define KS884X_PHY1ILR_P 0x04D4
265 #define KS884X_PHY1IHR_P 0x04D6
266 #define KS884X_P1ANAR_P 0x04D8
267 #define KS884X_P1ANLPR_P 0x04DA
270 #define KS884X_P2MBCR_P 0x04E0
271 #define KS884X_P2MBSR_P 0x04E2
272 #define KS884X_PHY2ILR_P 0x04E4
273 #define KS884X_PHY2IHR_P 0x04E6
274 #define KS884X_P2ANAR_P 0x04E8
275 #define KS884X_P2ANLPR_P 0x04EA
277 #define KS884X_PHY_1_CTRL_OFFSET KS884X_P1MBCR_P
278 #define PHY_CTRL_INTERVAL (KS884X_P2MBCR_P - KS884X_P1MBCR_P)
280 #define KS884X_PHY_CTRL_OFFSET 0x00
282 /* Mode Control Register */
283 #define PHY_REG_CTRL 0
285 #define PHY_RESET 0x8000
286 #define PHY_LOOPBACK 0x4000
287 #define PHY_SPEED_100MBIT 0x2000
288 #define PHY_AUTO_NEG_ENABLE 0x1000
289 #define PHY_POWER_DOWN 0x0800
290 #define PHY_MII_DISABLE 0x0400
291 #define PHY_AUTO_NEG_RESTART 0x0200
292 #define PHY_FULL_DUPLEX 0x0100
293 #define PHY_COLLISION_TEST 0x0080
294 #define PHY_HP_MDIX 0x0020
295 #define PHY_FORCE_MDIX 0x0010
296 #define PHY_AUTO_MDIX_DISABLE 0x0008
297 #define PHY_REMOTE_FAULT_DISABLE 0x0004
298 #define PHY_TRANSMIT_DISABLE 0x0002
299 #define PHY_LED_DISABLE 0x0001
301 #define KS884X_PHY_STATUS_OFFSET 0x02
303 /* Mode Status Register */
304 #define PHY_REG_STATUS 1
306 #define PHY_100BT4_CAPABLE 0x8000
307 #define PHY_100BTX_FD_CAPABLE 0x4000
308 #define PHY_100BTX_CAPABLE 0x2000
309 #define PHY_10BT_FD_CAPABLE 0x1000
310 #define PHY_10BT_CAPABLE 0x0800
311 #define PHY_MII_SUPPRESS_CAPABLE 0x0040
312 #define PHY_AUTO_NEG_ACKNOWLEDGE 0x0020
313 #define PHY_REMOTE_FAULT 0x0010
314 #define PHY_AUTO_NEG_CAPABLE 0x0008
315 #define PHY_LINK_STATUS 0x0004
316 #define PHY_JABBER_DETECT 0x0002
317 #define PHY_EXTENDED_CAPABILITY 0x0001
319 #define KS884X_PHY_ID_1_OFFSET 0x04
320 #define KS884X_PHY_ID_2_OFFSET 0x06
322 /* PHY Identifier Registers */
323 #define PHY_REG_ID_1 2
324 #define PHY_REG_ID_2 3
326 #define KS884X_PHY_AUTO_NEG_OFFSET 0x08
328 /* Auto-Negotiation Advertisement Register */
329 #define PHY_REG_AUTO_NEGOTIATION 4
331 #define PHY_AUTO_NEG_NEXT_PAGE 0x8000
332 #define PHY_AUTO_NEG_REMOTE_FAULT 0x2000
334 #define PHY_AUTO_NEG_ASYM_PAUSE 0x0800
335 #define PHY_AUTO_NEG_SYM_PAUSE 0x0400
336 #define PHY_AUTO_NEG_100BT4 0x0200
337 #define PHY_AUTO_NEG_100BTX_FD 0x0100
338 #define PHY_AUTO_NEG_100BTX 0x0080
339 #define PHY_AUTO_NEG_10BT_FD 0x0040
340 #define PHY_AUTO_NEG_10BT 0x0020
341 #define PHY_AUTO_NEG_SELECTOR 0x001F
342 #define PHY_AUTO_NEG_802_3 0x0001
344 #define PHY_AUTO_NEG_PAUSE (PHY_AUTO_NEG_SYM_PAUSE | PHY_AUTO_NEG_ASYM_PAUSE)
346 #define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A
348 /* Auto-Negotiation Link Partner Ability Register */
349 #define PHY_REG_REMOTE_CAPABILITY 5
351 #define PHY_REMOTE_NEXT_PAGE 0x8000
352 #define PHY_REMOTE_ACKNOWLEDGE 0x4000
353 #define PHY_REMOTE_REMOTE_FAULT 0x2000
354 #define PHY_REMOTE_SYM_PAUSE 0x0400
355 #define PHY_REMOTE_100BTX_FD 0x0100
356 #define PHY_REMOTE_100BTX 0x0080
357 #define PHY_REMOTE_10BT_FD 0x0040
358 #define PHY_REMOTE_10BT 0x0020
361 #define KS884X_P1VCT_P 0x04F0
362 #define KS884X_P1PHYCTRL_P 0x04F2
365 #define KS884X_P2VCT_P 0x04F4
366 #define KS884X_P2PHYCTRL_P 0x04F6
368 #define KS884X_PHY_SPECIAL_OFFSET KS884X_P1VCT_P
369 #define PHY_SPECIAL_INTERVAL (KS884X_P2VCT_P - KS884X_P1VCT_P)
371 #define KS884X_PHY_LINK_MD_OFFSET 0x00
373 #define PHY_START_CABLE_DIAG 0x8000
374 #define PHY_CABLE_DIAG_RESULT 0x6000
375 #define PHY_CABLE_STAT_NORMAL 0x0000
376 #define PHY_CABLE_STAT_OPEN 0x2000
377 #define PHY_CABLE_STAT_SHORT 0x4000
378 #define PHY_CABLE_STAT_FAILED 0x6000
379 #define PHY_CABLE_10M_SHORT 0x1000
380 #define PHY_CABLE_FAULT_COUNTER 0x01FF
382 #define KS884X_PHY_PHY_CTRL_OFFSET 0x02
384 #define PHY_STAT_REVERSED_POLARITY 0x0020
385 #define PHY_STAT_MDIX 0x0010
386 #define PHY_FORCE_LINK 0x0008
387 #define PHY_POWER_SAVING_DISABLE 0x0004
388 #define PHY_REMOTE_LOOPBACK 0x0002
391 #define KS884X_SIDER_P 0x0400
392 #define KS884X_CHIP_ID_OFFSET KS884X_SIDER_P
393 #define KS884X_FAMILY_ID_OFFSET (KS884X_CHIP_ID_OFFSET + 1)
395 #define REG_FAMILY_ID 0x88
397 #define REG_CHIP_ID_41 0x8810
398 #define REG_CHIP_ID_42 0x8800
400 #define KS884X_CHIP_ID_MASK_41 0xFF10
401 #define KS884X_CHIP_ID_MASK 0xFFF0
402 #define KS884X_CHIP_ID_SHIFT 4
403 #define KS884X_REVISION_MASK 0x000E
404 #define KS884X_REVISION_SHIFT 1
405 #define KS8842_START 0x0001
407 #define CHIP_IP_41_M 0x8810
408 #define CHIP_IP_42_M 0x8800
409 #define CHIP_IP_61_M 0x8890
410 #define CHIP_IP_62_M 0x8880
412 #define CHIP_IP_41_P 0x8850
413 #define CHIP_IP_42_P 0x8840
414 #define CHIP_IP_61_P 0x88D0
415 #define CHIP_IP_62_P 0x88C0
418 #define KS8842_SGCR1_P 0x0402
419 #define KS8842_SWITCH_CTRL_1_OFFSET KS8842_SGCR1_P
421 #define SWITCH_PASS_ALL 0x8000
422 #define SWITCH_TX_FLOW_CTRL 0x2000
423 #define SWITCH_RX_FLOW_CTRL 0x1000
424 #define SWITCH_CHECK_LENGTH 0x0800
425 #define SWITCH_AGING_ENABLE 0x0400
426 #define SWITCH_FAST_AGING 0x0200
427 #define SWITCH_AGGR_BACKOFF 0x0100
428 #define SWITCH_PASS_PAUSE 0x0008
429 #define SWITCH_LINK_AUTO_AGING 0x0001
432 #define KS8842_SGCR2_P 0x0404
433 #define KS8842_SWITCH_CTRL_2_OFFSET KS8842_SGCR2_P
435 #define SWITCH_VLAN_ENABLE 0x8000
436 #define SWITCH_IGMP_SNOOP 0x4000
437 #define IPV6_MLD_SNOOP_ENABLE 0x2000
438 #define IPV6_MLD_SNOOP_OPTION 0x1000
439 #define PRIORITY_SCHEME_SELECT 0x0800
440 #define SWITCH_MIRROR_RX_TX 0x0100
441 #define UNICAST_VLAN_BOUNDARY 0x0080
442 #define MULTICAST_STORM_DISABLE 0x0040
443 #define SWITCH_BACK_PRESSURE 0x0020
444 #define FAIR_FLOW_CTRL 0x0010
445 #define NO_EXC_COLLISION_DROP 0x0008
446 #define SWITCH_HUGE_PACKET 0x0004
447 #define SWITCH_LEGAL_PACKET 0x0002
448 #define SWITCH_BUF_RESERVE 0x0001
451 #define KS8842_SGCR3_P 0x0406
452 #define KS8842_SWITCH_CTRL_3_OFFSET KS8842_SGCR3_P
454 #define BROADCAST_STORM_RATE_LO 0xFF00
455 #define SWITCH_REPEATER 0x0080
456 #define SWITCH_HALF_DUPLEX 0x0040
457 #define SWITCH_FLOW_CTRL 0x0020
458 #define SWITCH_10_MBIT 0x0010
459 #define SWITCH_REPLACE_NULL_VID 0x0008
460 #define BROADCAST_STORM_RATE_HI 0x0007
462 #define BROADCAST_STORM_RATE 0x07FF
465 #define KS8842_SGCR4_P 0x0408
468 #define KS8842_SGCR5_P 0x040A
469 #define KS8842_SWITCH_CTRL_5_OFFSET KS8842_SGCR5_P
471 #define LED_MODE 0x8200
472 #define LED_SPEED_DUPLEX_ACT 0x0000
473 #define LED_SPEED_DUPLEX_LINK_ACT 0x8000
474 #define LED_DUPLEX_10_100 0x0200
477 #define KS8842_SGCR6_P 0x0410
478 #define KS8842_SWITCH_CTRL_6_OFFSET KS8842_SGCR6_P
480 #define KS8842_PRIORITY_MASK 3
481 #define KS8842_PRIORITY_SHIFT 2
484 #define KS8842_SGCR7_P 0x0412
485 #define KS8842_SWITCH_CTRL_7_OFFSET KS8842_SGCR7_P
487 #define SWITCH_UNK_DEF_PORT_ENABLE 0x0008
488 #define SWITCH_UNK_DEF_PORT_3 0x0004
489 #define SWITCH_UNK_DEF_PORT_2 0x0002
490 #define SWITCH_UNK_DEF_PORT_1 0x0001
493 #define KS8842_MACAR1_P 0x0470
494 #define KS8842_MACAR2_P 0x0472
495 #define KS8842_MACAR3_P 0x0474
496 #define KS8842_MAC_ADDR_1_OFFSET KS8842_MACAR1_P
497 #define KS8842_MAC_ADDR_0_OFFSET (KS8842_MAC_ADDR_1_OFFSET + 1)
498 #define KS8842_MAC_ADDR_3_OFFSET KS8842_MACAR2_P
499 #define KS8842_MAC_ADDR_2_OFFSET (KS8842_MAC_ADDR_3_OFFSET + 1)
500 #define KS8842_MAC_ADDR_5_OFFSET KS8842_MACAR3_P
501 #define KS8842_MAC_ADDR_4_OFFSET (KS8842_MAC_ADDR_5_OFFSET + 1)
504 #define KS8842_TOSR1_P 0x0480
505 #define KS8842_TOSR2_P 0x0482
506 #define KS8842_TOSR3_P 0x0484
507 #define KS8842_TOSR4_P 0x0486
508 #define KS8842_TOSR5_P 0x0488
509 #define KS8842_TOSR6_P 0x048A
510 #define KS8842_TOSR7_P 0x0490
511 #define KS8842_TOSR8_P 0x0492
512 #define KS8842_TOS_1_OFFSET KS8842_TOSR1_P
513 #define KS8842_TOS_2_OFFSET KS8842_TOSR2_P
514 #define KS8842_TOS_3_OFFSET KS8842_TOSR3_P
515 #define KS8842_TOS_4_OFFSET KS8842_TOSR4_P
516 #define KS8842_TOS_5_OFFSET KS8842_TOSR5_P
517 #define KS8842_TOS_6_OFFSET KS8842_TOSR6_P
519 #define KS8842_TOS_7_OFFSET KS8842_TOSR7_P
520 #define KS8842_TOS_8_OFFSET KS8842_TOSR8_P
523 #define KS8842_P1CR1_P 0x0500
524 #define KS8842_P1CR2_P 0x0502
525 #define KS8842_P1VIDR_P 0x0504
526 #define KS8842_P1CR3_P 0x0506
527 #define KS8842_P1IRCR_P 0x0508
528 #define KS8842_P1ERCR_P 0x050A
529 #define KS884X_P1SCSLMD_P 0x0510
530 #define KS884X_P1CR4_P 0x0512
531 #define KS884X_P1SR_P 0x0514
534 #define KS8842_P2CR1_P 0x0520
535 #define KS8842_P2CR2_P 0x0522
536 #define KS8842_P2VIDR_P 0x0524
537 #define KS8842_P2CR3_P 0x0526
538 #define KS8842_P2IRCR_P 0x0528
539 #define KS8842_P2ERCR_P 0x052A
540 #define KS884X_P2SCSLMD_P 0x0530
541 #define KS884X_P2CR4_P 0x0532
542 #define KS884X_P2SR_P 0x0534
545 #define KS8842_P3CR1_P 0x0540
546 #define KS8842_P3CR2_P 0x0542
547 #define KS8842_P3VIDR_P 0x0544
548 #define KS8842_P3CR3_P 0x0546
549 #define KS8842_P3IRCR_P 0x0548
550 #define KS8842_P3ERCR_P 0x054A
552 #define KS8842_PORT_1_CTRL_1 KS8842_P1CR1_P
553 #define KS8842_PORT_2_CTRL_1 KS8842_P2CR1_P
554 #define KS8842_PORT_3_CTRL_1 KS8842_P3CR1_P
556 #define PORT_CTRL_ADDR(port, addr) \
557 (addr = KS8842_PORT_1_CTRL_1 + (port) * \
558 (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1))
560 #define KS8842_PORT_CTRL_1_OFFSET 0x00
562 #define PORT_BROADCAST_STORM 0x0080
563 #define PORT_DIFFSERV_ENABLE 0x0040
564 #define PORT_802_1P_ENABLE 0x0020
565 #define PORT_BASED_PRIORITY_MASK 0x0018
566 #define PORT_BASED_PRIORITY_BASE 0x0003
567 #define PORT_BASED_PRIORITY_SHIFT 3
568 #define PORT_BASED_PRIORITY_0 0x0000
569 #define PORT_BASED_PRIORITY_1 0x0008
570 #define PORT_BASED_PRIORITY_2 0x0010
571 #define PORT_BASED_PRIORITY_3 0x0018
572 #define PORT_INSERT_TAG 0x0004
573 #define PORT_REMOVE_TAG 0x0002
574 #define PORT_PRIO_QUEUE_ENABLE 0x0001
576 #define KS8842_PORT_CTRL_2_OFFSET 0x02
578 #define PORT_INGRESS_VLAN_FILTER 0x4000
579 #define PORT_DISCARD_NON_VID 0x2000
580 #define PORT_FORCE_FLOW_CTRL 0x1000
581 #define PORT_BACK_PRESSURE 0x0800
582 #define PORT_TX_ENABLE 0x0400
583 #define PORT_RX_ENABLE 0x0200
584 #define PORT_LEARN_DISABLE 0x0100
585 #define PORT_MIRROR_SNIFFER 0x0080
586 #define PORT_MIRROR_RX 0x0040
587 #define PORT_MIRROR_TX 0x0020
588 #define PORT_USER_PRIORITY_CEILING 0x0008
589 #define PORT_VLAN_MEMBERSHIP 0x0007
591 #define KS8842_PORT_CTRL_VID_OFFSET 0x04
593 #define PORT_DEFAULT_VID 0x0001
595 #define KS8842_PORT_CTRL_3_OFFSET 0x06
597 #define PORT_INGRESS_LIMIT_MODE 0x000C
598 #define PORT_INGRESS_ALL 0x0000
599 #define PORT_INGRESS_UNICAST 0x0004
600 #define PORT_INGRESS_MULTICAST 0x0008
601 #define PORT_INGRESS_BROADCAST 0x000C
602 #define PORT_COUNT_IFG 0x0002
603 #define PORT_COUNT_PREAMBLE 0x0001
605 #define KS8842_PORT_IN_RATE_OFFSET 0x08
606 #define KS8842_PORT_OUT_RATE_OFFSET 0x0A
608 #define PORT_PRIORITY_RATE 0x0F
609 #define PORT_PRIORITY_RATE_SHIFT 4
611 #define KS884X_PORT_LINK_MD 0x10
613 #define PORT_CABLE_10M_SHORT 0x8000
614 #define PORT_CABLE_DIAG_RESULT 0x6000
615 #define PORT_CABLE_STAT_NORMAL 0x0000
616 #define PORT_CABLE_STAT_OPEN 0x2000
617 #define PORT_CABLE_STAT_SHORT 0x4000
618 #define PORT_CABLE_STAT_FAILED 0x6000
619 #define PORT_START_CABLE_DIAG 0x1000
620 #define PORT_FORCE_LINK 0x0800
621 #define PORT_POWER_SAVING_DISABLE 0x0400
622 #define PORT_PHY_REMOTE_LOOPBACK 0x0200
623 #define PORT_CABLE_FAULT_COUNTER 0x01FF
625 #define KS884X_PORT_CTRL_4_OFFSET 0x12
627 #define PORT_LED_OFF 0x8000
628 #define PORT_TX_DISABLE 0x4000
629 #define PORT_AUTO_NEG_RESTART 0x2000
630 #define PORT_REMOTE_FAULT_DISABLE 0x1000
631 #define PORT_POWER_DOWN 0x0800
632 #define PORT_AUTO_MDIX_DISABLE 0x0400
633 #define PORT_FORCE_MDIX 0x0200
634 #define PORT_LOOPBACK 0x0100
635 #define PORT_AUTO_NEG_ENABLE 0x0080
636 #define PORT_FORCE_100_MBIT 0x0040
637 #define PORT_FORCE_FULL_DUPLEX 0x0020
638 #define PORT_AUTO_NEG_SYM_PAUSE 0x0010
639 #define PORT_AUTO_NEG_100BTX_FD 0x0008
640 #define PORT_AUTO_NEG_100BTX 0x0004
641 #define PORT_AUTO_NEG_10BT_FD 0x0002
642 #define PORT_AUTO_NEG_10BT 0x0001
644 #define KS884X_PORT_STATUS_OFFSET 0x14
646 #define PORT_HP_MDIX 0x8000
647 #define PORT_REVERSED_POLARITY 0x2000
648 #define PORT_RX_FLOW_CTRL 0x0800
649 #define PORT_TX_FLOW_CTRL 0x1000
650 #define PORT_STATUS_SPEED_100MBIT 0x0400
651 #define PORT_STATUS_FULL_DUPLEX 0x0200
652 #define PORT_REMOTE_FAULT 0x0100
653 #define PORT_MDIX_STATUS 0x0080
654 #define PORT_AUTO_NEG_COMPLETE 0x0040
655 #define PORT_STATUS_LINK_GOOD 0x0020
656 #define PORT_REMOTE_SYM_PAUSE 0x0010
657 #define PORT_REMOTE_100BTX_FD 0x0008
658 #define PORT_REMOTE_100BTX 0x0004
659 #define PORT_REMOTE_10BT_FD 0x0002
660 #define PORT_REMOTE_10BT 0x0001
663 #define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
664 #define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000
665 #define STATIC_MAC_TABLE_VALID 00-00080000-00000000
666 #define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000
667 #define STATIC_MAC_TABLE_USE_FID 00-00200000-00000000
668 #define STATIC_MAC_TABLE_FID 00-03C00000-00000000
671 #define STATIC_MAC_TABLE_ADDR 0x0000FFFF
672 #define STATIC_MAC_TABLE_FWD_PORTS 0x00070000
673 #define STATIC_MAC_TABLE_VALID 0x00080000
674 #define STATIC_MAC_TABLE_OVERRIDE 0x00100000
675 #define STATIC_MAC_TABLE_USE_FID 0x00200000
676 #define STATIC_MAC_TABLE_FID 0x03C00000
678 #define STATIC_MAC_FWD_PORTS_SHIFT 16
679 #define STATIC_MAC_FID_SHIFT 22
682 #define VLAN_TABLE_VID 00-00000000-00000FFF
683 #define VLAN_TABLE_FID 00-00000000-0000F000
684 #define VLAN_TABLE_MEMBERSHIP 00-00000000-00070000
685 #define VLAN_TABLE_VALID 00-00000000-00080000
688 #define VLAN_TABLE_VID 0x00000FFF
689 #define VLAN_TABLE_FID 0x0000F000
690 #define VLAN_TABLE_MEMBERSHIP 0x00070000
691 #define VLAN_TABLE_VALID 0x00080000
693 #define VLAN_TABLE_FID_SHIFT 12
694 #define VLAN_TABLE_MEMBERSHIP_SHIFT 16
697 #define DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
698 #define DYNAMIC_MAC_TABLE_FID 00-000F0000-00000000
699 #define DYNAMIC_MAC_TABLE_SRC_PORT 00-00300000-00000000
700 #define DYNAMIC_MAC_TABLE_TIMESTAMP 00-00C00000-00000000
701 #define DYNAMIC_MAC_TABLE_ENTRIES 03-FF000000-00000000
702 #define DYNAMIC_MAC_TABLE_MAC_EMPTY 04-00000000-00000000
703 #define DYNAMIC_MAC_TABLE_RESERVED 78-00000000-00000000
704 #define DYNAMIC_MAC_TABLE_NOT_READY 80-00000000-00000000
707 #define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
708 #define DYNAMIC_MAC_TABLE_FID 0x000F0000
709 #define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000
710 #define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000
711 #define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000
713 #define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03
714 #define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04
715 #define DYNAMIC_MAC_TABLE_RESERVED 0x78
716 #define DYNAMIC_MAC_TABLE_NOT_READY 0x80
718 #define DYNAMIC_MAC_FID_SHIFT 16
719 #define DYNAMIC_MAC_SRC_PORT_SHIFT 20
720 #define DYNAMIC_MAC_TIMESTAMP_SHIFT 22
721 #define DYNAMIC_MAC_ENTRIES_SHIFT 24
722 #define DYNAMIC_MAC_ENTRIES_H_SHIFT 8
725 #define MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
726 #define MIB_COUNTER_VALID 00-00000000-40000000
727 #define MIB_COUNTER_OVERFLOW 00-00000000-80000000
730 #define MIB_COUNTER_VALUE 0x3FFFFFFF
731 #define MIB_COUNTER_VALID 0x40000000
732 #define MIB_COUNTER_OVERFLOW 0x80000000
734 #define MIB_PACKET_DROPPED 0x0000FFFF
736 #define KS_MIB_PACKET_DROPPED_TX_0 0x100
737 #define KS_MIB_PACKET_DROPPED_TX_1 0x101
738 #define KS_MIB_PACKET_DROPPED_TX 0x102
739 #define KS_MIB_PACKET_DROPPED_RX_0 0x103
740 #define KS_MIB_PACKET_DROPPED_RX_1 0x104
741 #define KS_MIB_PACKET_DROPPED_RX 0x105
743 /* Change default LED mode. */
744 #define SET_DEFAULT_LED LED_SPEED_DUPLEX_ACT
746 #define MAC_ADDR_ORDER(i) (ETH_ALEN - 1 - (i))
748 #define MAX_ETHERNET_BODY_SIZE 1500
749 #define ETHERNET_HEADER_SIZE (14 + VLAN_HLEN)
751 #define MAX_ETHERNET_PACKET_SIZE \
752 (MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE)
754 #define REGULAR_RX_BUF_SIZE (MAX_ETHERNET_PACKET_SIZE + 4)
755 #define MAX_RX_BUF_SIZE (1912 + 4)
757 #define ADDITIONAL_ENTRIES 16
758 #define MAX_MULTICAST_LIST 32
760 #define HW_MULTICAST_SIZE 8
762 #define HW_TO_DEV_PORT(port) (port - 1)
774 /* total transmit errors */
775 OID_COUNTER_XMIT_ERROR
,
777 /* total receive errors */
778 OID_COUNTER_RCV_ERROR
,
784 * Hardware descriptor definitions
787 #define DESC_ALIGNMENT 16
788 #define BUFFER_ALIGNMENT 8
790 #define NUM_OF_RX_DESC 64
791 #define NUM_OF_TX_DESC 64
793 #define KS_DESC_RX_FRAME_LEN 0x000007FF
794 #define KS_DESC_RX_FRAME_TYPE 0x00008000
795 #define KS_DESC_RX_ERROR_CRC 0x00010000
796 #define KS_DESC_RX_ERROR_RUNT 0x00020000
797 #define KS_DESC_RX_ERROR_TOO_LONG 0x00040000
798 #define KS_DESC_RX_ERROR_PHY 0x00080000
799 #define KS884X_DESC_RX_PORT_MASK 0x00300000
800 #define KS_DESC_RX_MULTICAST 0x01000000
801 #define KS_DESC_RX_ERROR 0x02000000
802 #define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000
803 #define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000
804 #define KS_DESC_RX_ERROR_CSUM_IP 0x10000000
805 #define KS_DESC_RX_LAST 0x20000000
806 #define KS_DESC_RX_FIRST 0x40000000
807 #define KS_DESC_RX_ERROR_COND \
808 (KS_DESC_RX_ERROR_CRC | \
809 KS_DESC_RX_ERROR_RUNT | \
810 KS_DESC_RX_ERROR_PHY | \
811 KS_DESC_RX_ERROR_TOO_LONG)
813 #define KS_DESC_HW_OWNED 0x80000000
815 #define KS_DESC_BUF_SIZE 0x000007FF
816 #define KS884X_DESC_TX_PORT_MASK 0x00300000
817 #define KS_DESC_END_OF_RING 0x02000000
818 #define KS_DESC_TX_CSUM_GEN_UDP 0x04000000
819 #define KS_DESC_TX_CSUM_GEN_TCP 0x08000000
820 #define KS_DESC_TX_CSUM_GEN_IP 0x10000000
821 #define KS_DESC_TX_LAST 0x20000000
822 #define KS_DESC_TX_FIRST 0x40000000
823 #define KS_DESC_TX_INTERRUPT 0x80000000
825 #define KS_DESC_PORT_SHIFT 20
827 #define KS_DESC_RX_MASK (KS_DESC_BUF_SIZE)
829 #define KS_DESC_TX_MASK \
830 (KS_DESC_TX_INTERRUPT | \
833 KS_DESC_TX_CSUM_GEN_IP | \
834 KS_DESC_TX_CSUM_GEN_TCP | \
835 KS_DESC_TX_CSUM_GEN_UDP | \
838 struct ksz_desc_rx_stat
{
839 #ifdef __BIG_ENDIAN_BITFIELD
876 struct ksz_desc_tx_stat
{
877 #ifdef __BIG_ENDIAN_BITFIELD
886 struct ksz_desc_rx_buf
{
887 #ifdef __BIG_ENDIAN_BITFIELD
900 struct ksz_desc_tx_buf
{
901 #ifdef __BIG_ENDIAN_BITFIELD
929 struct ksz_desc_rx_stat rx
;
930 struct ksz_desc_tx_stat tx
;
935 struct ksz_desc_rx_buf rx
;
936 struct ksz_desc_tx_buf tx
;
941 * struct ksz_hw_desc - Hardware descriptor data structure
942 * @ctrl: Descriptor control value.
943 * @buf: Descriptor buffer value.
944 * @addr: Physical address of memory buffer.
945 * @next: Pointer to next hardware descriptor.
948 union desc_stat ctrl
;
955 * struct ksz_sw_desc - Software descriptor data structure
956 * @ctrl: Descriptor control value.
957 * @buf: Descriptor buffer value.
958 * @buf_size: Current buffers size value in hardware descriptor.
961 union desc_stat ctrl
;
967 * struct ksz_dma_buf - OS dependent DMA buffer data structure
968 * @skb: Associated socket buffer.
969 * @dma: Associated physical DMA address.
970 * len: Actual len used.
979 * struct ksz_desc - Descriptor structure
980 * @phw: Hardware descriptor pointer to uncached physical memory.
981 * @sw: Cached memory to hold hardware descriptor values for
983 * @dma_buf: Operating system dependent data structure to hold physical
984 * memory buffer allocation information.
987 struct ksz_hw_desc
*phw
;
988 struct ksz_sw_desc sw
;
989 struct ksz_dma_buf dma_buf
;
992 #define DMA_BUFFER(desc) ((struct ksz_dma_buf *)(&(desc)->dma_buf))
995 * struct ksz_desc_info - Descriptor information data structure
996 * @ring: First descriptor in the ring.
997 * @cur: Current descriptor being manipulated.
998 * @ring_virt: First hardware descriptor in the ring.
999 * @ring_phys: The physical address of the first descriptor of the ring.
1000 * @size: Size of hardware descriptor.
1001 * @alloc: Number of descriptors allocated.
1002 * @avail: Number of descriptors available for use.
1003 * @last: Index for last descriptor released to hardware.
1004 * @next: Index for next descriptor available for use.
1005 * @mask: Mask for index wrapping.
1007 struct ksz_desc_info
{
1008 struct ksz_desc
*ring
;
1009 struct ksz_desc
*cur
;
1010 struct ksz_hw_desc
*ring_virt
;
1021 * KSZ8842 switch definitions
1025 TABLE_STATIC_MAC
= 0,
1031 #define LEARNED_MAC_TABLE_ENTRIES 1024
1032 #define STATIC_MAC_TABLE_ENTRIES 8
1035 * struct ksz_mac_table - Static MAC table data structure
1036 * @mac_addr: MAC address to filter.
1039 * @ports: Port membership.
1040 * @override: Override setting.
1041 * @use_fid: FID use setting.
1042 * @valid: Valid setting indicating the entry is being used.
1044 struct ksz_mac_table
{
1045 u8 mac_addr
[ETH_ALEN
];
1054 #define VLAN_TABLE_ENTRIES 16
1057 * struct ksz_vlan_table - VLAN table data structure
1060 * @member: Port membership.
1062 struct ksz_vlan_table
{
1068 #define DIFFSERV_ENTRIES 64
1069 #define PRIO_802_1P_ENTRIES 8
1070 #define PRIO_QUEUES 4
1072 #define SWITCH_PORT_NUM 2
1073 #define TOTAL_PORT_NUM (SWITCH_PORT_NUM + 1)
1074 #define HOST_MASK (1 << SWITCH_PORT_NUM)
1078 #define OTHER_PORT 1
1079 #define HOST_PORT SWITCH_PORT_NUM
1081 #define PORT_COUNTER_NUM 0x20
1082 #define TOTAL_PORT_COUNTER_NUM (PORT_COUNTER_NUM + 2)
1084 #define MIB_COUNTER_RX_LO_PRIORITY 0x00
1085 #define MIB_COUNTER_RX_HI_PRIORITY 0x01
1086 #define MIB_COUNTER_RX_UNDERSIZE 0x02
1087 #define MIB_COUNTER_RX_FRAGMENT 0x03
1088 #define MIB_COUNTER_RX_OVERSIZE 0x04
1089 #define MIB_COUNTER_RX_JABBER 0x05
1090 #define MIB_COUNTER_RX_SYMBOL_ERR 0x06
1091 #define MIB_COUNTER_RX_CRC_ERR 0x07
1092 #define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08
1093 #define MIB_COUNTER_RX_CTRL_8808 0x09
1094 #define MIB_COUNTER_RX_PAUSE 0x0A
1095 #define MIB_COUNTER_RX_BROADCAST 0x0B
1096 #define MIB_COUNTER_RX_MULTICAST 0x0C
1097 #define MIB_COUNTER_RX_UNICAST 0x0D
1098 #define MIB_COUNTER_RX_OCTET_64 0x0E
1099 #define MIB_COUNTER_RX_OCTET_65_127 0x0F
1100 #define MIB_COUNTER_RX_OCTET_128_255 0x10
1101 #define MIB_COUNTER_RX_OCTET_256_511 0x11
1102 #define MIB_COUNTER_RX_OCTET_512_1023 0x12
1103 #define MIB_COUNTER_RX_OCTET_1024_1522 0x13
1104 #define MIB_COUNTER_TX_LO_PRIORITY 0x14
1105 #define MIB_COUNTER_TX_HI_PRIORITY 0x15
1106 #define MIB_COUNTER_TX_LATE_COLLISION 0x16
1107 #define MIB_COUNTER_TX_PAUSE 0x17
1108 #define MIB_COUNTER_TX_BROADCAST 0x18
1109 #define MIB_COUNTER_TX_MULTICAST 0x19
1110 #define MIB_COUNTER_TX_UNICAST 0x1A
1111 #define MIB_COUNTER_TX_DEFERRED 0x1B
1112 #define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C
1113 #define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D
1114 #define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E
1115 #define MIB_COUNTER_TX_MULTI_COLLISION 0x1F
1117 #define MIB_COUNTER_RX_DROPPED_PACKET 0x20
1118 #define MIB_COUNTER_TX_DROPPED_PACKET 0x21
1121 * struct ksz_port_mib - Port MIB data structure
1122 * @cnt_ptr: Current pointer to MIB counter index.
1123 * @link_down: Indication the link has just gone down.
1124 * @state: Connection status of the port.
1125 * @mib_start: The starting counter index. Some ports do not start at 0.
1126 * @counter: 64-bit MIB counter value.
1127 * @dropped: Temporary buffer to remember last read packet dropped values.
1129 * MIB counters needs to be read periodically so that counters do not get
1130 * overflowed and give incorrect values. A right balance is needed to
1131 * satisfy this condition and not waste too much CPU time.
1133 * It is pointless to read MIB counters when the port is disconnected. The
1134 * @state provides the connection status so that MIB counters are read only
1135 * when the port is connected. The @link_down indicates the port is just
1136 * disconnected so that all MIB counters are read one last time to update the
1139 struct ksz_port_mib
{
1145 u64 counter
[TOTAL_PORT_COUNTER_NUM
];
1150 * struct ksz_port_cfg - Port configuration data structure
1152 * @member: Port membership.
1153 * @port_prio: Port priority.
1154 * @rx_rate: Receive priority rate.
1155 * @tx_rate: Transmit priority rate.
1156 * @stp_state: Current Spanning Tree Protocol state.
1158 struct ksz_port_cfg
{
1162 u32 rx_rate
[PRIO_QUEUES
];
1163 u32 tx_rate
[PRIO_QUEUES
];
1168 * struct ksz_switch - KSZ8842 switch data structure
1169 * @mac_table: MAC table entries information.
1170 * @vlan_table: VLAN table entries information.
1171 * @port_cfg: Port configuration information.
1172 * @diffserv: DiffServ priority settings. Possible values from 6-bit of ToS
1173 * (bit7 ~ bit2) field.
1174 * @p_802_1p: 802.1P priority settings. Possible values from 3-bit of 802.1p
1175 * Tag priority field.
1176 * @br_addr: Bridge address. Used for STP.
1177 * @other_addr: Other MAC address. Used for multiple network device mode.
1178 * @broad_per: Broadcast storm percentage.
1179 * @member: Current port membership. Used for STP.
1182 struct ksz_mac_table mac_table
[STATIC_MAC_TABLE_ENTRIES
];
1183 struct ksz_vlan_table vlan_table
[VLAN_TABLE_ENTRIES
];
1184 struct ksz_port_cfg port_cfg
[TOTAL_PORT_NUM
];
1186 u8 diffserv
[DIFFSERV_ENTRIES
];
1187 u8 p_802_1p
[PRIO_802_1P_ENTRIES
];
1189 u8 br_addr
[ETH_ALEN
];
1190 u8 other_addr
[ETH_ALEN
];
1196 #define TX_RATE_UNIT 10000
1199 * struct ksz_port_info - Port information data structure
1200 * @state: Connection status of the port.
1201 * @tx_rate: Transmit rate divided by 10000 to get Mbit.
1202 * @duplex: Duplex mode.
1203 * @advertised: Advertised auto-negotiation setting. Used to determine link.
1204 * @partner: Auto-negotiation partner setting. Used to determine link.
1205 * @port_id: Port index to access actual hardware register.
1206 * @pdev: Pointer to OS dependent network device.
1208 struct ksz_port_info
{
1218 #define MAX_TX_HELD_SIZE 52000
1220 /* Hardware features and bug fixes. */
1221 #define LINK_INT_WORKING (1 << 0)
1222 #define SMALL_PACKET_TX_BUG (1 << 1)
1223 #define HALF_DUPLEX_SIGNAL_BUG (1 << 2)
1224 #define RX_HUGE_FRAME (1 << 4)
1225 #define STP_SUPPORT (1 << 8)
1227 /* Software overrides. */
1228 #define PAUSE_FLOW_CTRL (1 << 0)
1229 #define FAST_AGING (1 << 1)
1232 * struct ksz_hw - KSZ884X hardware data structure
1233 * @io: Virtual address assigned.
1234 * @ksz_switch: Pointer to KSZ8842 switch.
1235 * @port_info: Port information.
1236 * @port_mib: Port MIB information.
1237 * @dev_count: Number of network devices this hardware supports.
1238 * @dst_ports: Destination ports in switch for transmission.
1239 * @id: Hardware ID. Used for display only.
1240 * @mib_cnt: Number of MIB counters this hardware has.
1241 * @mib_port_cnt: Number of ports with MIB counters.
1242 * @tx_cfg: Cached transmit control settings.
1243 * @rx_cfg: Cached receive control settings.
1244 * @intr_mask: Current interrupt mask.
1245 * @intr_set: Current interrup set.
1246 * @intr_blocked: Interrupt blocked.
1247 * @rx_desc_info: Receive descriptor information.
1248 * @tx_desc_info: Transmit descriptor information.
1249 * @tx_int_cnt: Transmit interrupt count. Used for TX optimization.
1250 * @tx_int_mask: Transmit interrupt mask. Used for TX optimization.
1251 * @tx_size: Transmit data size. Used for TX optimization.
1252 * The maximum is defined by MAX_TX_HELD_SIZE.
1253 * @perm_addr: Permanent MAC address.
1254 * @override_addr: Overrided MAC address.
1255 * @address: Additional MAC address entries.
1256 * @addr_list_size: Additional MAC address list size.
1257 * @mac_override: Indication of MAC address overrided.
1258 * @promiscuous: Counter to keep track of promiscuous mode set.
1259 * @all_multi: Counter to keep track of all multicast mode set.
1260 * @multi_list: Multicast address entries.
1261 * @multi_bits: Cached multicast hash table settings.
1262 * @multi_list_size: Multicast address list size.
1263 * @enabled: Indication of hardware enabled.
1264 * @rx_stop: Indication of receive process stop.
1265 * @features: Hardware features to enable.
1266 * @overrides: Hardware features to override.
1267 * @parent: Pointer to parent, network device private structure.
1272 struct ksz_switch
*ksz_switch
;
1273 struct ksz_port_info port_info
[SWITCH_PORT_NUM
];
1274 struct ksz_port_mib port_mib
[TOTAL_PORT_NUM
];
1287 struct ksz_desc_info rx_desc_info
;
1288 struct ksz_desc_info tx_desc_info
;
1294 u8 perm_addr
[ETH_ALEN
];
1295 u8 override_addr
[ETH_ALEN
];
1296 u8 address
[ADDITIONAL_ENTRIES
][ETH_ALEN
];
1301 u8 multi_list
[MAX_MULTICAST_LIST
][ETH_ALEN
];
1302 u8 multi_bits
[HW_MULTICAST_SIZE
];
1323 * struct ksz_port - Virtual port data structure
1324 * @duplex: Duplex mode setting. 1 for half duplex, 2 for full
1325 * duplex, and 0 for auto, which normally results in full
1327 * @speed: Speed setting. 10 for 10 Mbit, 100 for 100 Mbit, and
1328 * 0 for auto, which normally results in 100 Mbit.
1329 * @force_link: Force link setting. 0 for auto-negotiation, and 1 for
1331 * @flow_ctrl: Flow control setting. PHY_NO_FLOW_CTRL for no flow
1332 * control, and PHY_FLOW_CTRL for flow control.
1333 * PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100
1335 * @first_port: Index of first port this port supports.
1336 * @mib_port_cnt: Number of ports with MIB counters.
1337 * @port_cnt: Number of ports this port supports.
1338 * @counter: Port statistics counter.
1339 * @hw: Pointer to hardware structure.
1340 * @linked: Pointer to port information linked to this port.
1351 u64 counter
[OID_COUNTER_LAST
];
1354 struct ksz_port_info
*linked
;
1358 * struct ksz_timer_info - Timer information data structure
1359 * @timer: Kernel timer.
1360 * @cnt: Running timer counter.
1361 * @max: Number of times to run timer; -1 for infinity.
1362 * @period: Timer period in jiffies.
1364 struct ksz_timer_info
{
1365 struct timer_list timer
;
1372 * struct ksz_shared_mem - OS dependent shared memory data structure
1373 * @dma_addr: Physical DMA address allocated.
1374 * @alloc_size: Allocation size.
1375 * @phys: Actual physical address used.
1376 * @alloc_virt: Virtual address allocated.
1377 * @virt: Actual virtual address used.
1379 struct ksz_shared_mem
{
1380 dma_addr_t dma_addr
;
1388 * struct ksz_counter_info - OS dependent counter information data structure
1389 * @counter: Wait queue to wakeup after counters are read.
1390 * @time: Next time in jiffies to read counter.
1391 * @read: Indication of counters read in full or not.
1393 struct ksz_counter_info
{
1394 wait_queue_head_t counter
;
1400 * struct dev_info - Network device information data structure
1401 * @dev: Pointer to network device.
1402 * @pdev: Pointer to PCI device.
1403 * @hw: Hardware structure.
1404 * @desc_pool: Physical memory used for descriptor pool.
1405 * @hwlock: Spinlock to prevent hardware from accessing.
1406 * @lock: Mutex lock to prevent device from accessing.
1407 * @dev_rcv: Receive process function used.
1408 * @last_skb: Socket buffer allocated for descriptor rx fragments.
1409 * @skb_index: Buffer index for receiving fragments.
1410 * @skb_len: Buffer length for receiving fragments.
1411 * @mib_read: Workqueue to read MIB counters.
1412 * @mib_timer_info: Timer to read MIB counters.
1413 * @counter: Used for MIB reading.
1414 * @mtu: Current MTU used. The default is REGULAR_RX_BUF_SIZE;
1415 * the maximum is MAX_RX_BUF_SIZE.
1416 * @opened: Counter to keep track of device open.
1417 * @rx_tasklet: Receive processing tasklet.
1418 * @tx_tasklet: Transmit processing tasklet.
1419 * @wol_enable: Wake-on-LAN enable set by ethtool.
1420 * @wol_support: Wake-on-LAN support used by ethtool.
1421 * @pme_wait: Used for KSZ8841 power management.
1424 struct net_device
*dev
;
1425 struct pci_dev
*pdev
;
1428 struct ksz_shared_mem desc_pool
;
1433 int (*dev_rcv
)(struct dev_info
*);
1435 struct sk_buff
*last_skb
;
1439 struct work_struct mib_read
;
1440 struct ksz_timer_info mib_timer_info
;
1441 struct ksz_counter_info counter
[TOTAL_PORT_NUM
];
1446 struct tasklet_struct rx_tasklet
;
1447 struct tasklet_struct tx_tasklet
;
1451 unsigned long pme_wait
;
1455 * struct dev_priv - Network device private data structure
1456 * @adapter: Adapter device information.
1457 * @port: Port information.
1458 * @monitor_time_info: Timer to monitor ports.
1459 * @proc_sem: Semaphore for proc accessing.
1461 * @mii_if: MII interface information.
1462 * @advertising: Temporary variable to store advertised settings.
1463 * @msg_enable: The message flags controlling driver output.
1464 * @media_state: The connection status of the device.
1465 * @multicast: The all multicast state of the device.
1466 * @promiscuous: The promiscuous state of the device.
1469 struct dev_info
*adapter
;
1470 struct ksz_port port
;
1471 struct ksz_timer_info monitor_timer_info
;
1473 struct semaphore proc_sem
;
1476 struct mii_if_info mii_if
;
1485 #define DRV_NAME "KSZ884X PCI"
1486 #define DEVICE_NAME "KSZ884x PCI"
1487 #define DRV_VERSION "1.0.0"
1488 #define DRV_RELDATE "Feb 8, 2010"
1490 static char version
[] =
1491 "Micrel " DEVICE_NAME
" " DRV_VERSION
" (" DRV_RELDATE
")";
1493 static u8 DEFAULT_MAC_ADDRESS
[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 };
1496 * Interrupt processing primary routines
1499 static inline void hw_ack_intr(struct ksz_hw
*hw
, uint interrupt
)
1501 writel(interrupt
, hw
->io
+ KS884X_INTERRUPTS_STATUS
);
1504 static inline void hw_dis_intr(struct ksz_hw
*hw
)
1506 hw
->intr_blocked
= hw
->intr_mask
;
1507 writel(0, hw
->io
+ KS884X_INTERRUPTS_ENABLE
);
1508 hw
->intr_set
= readl(hw
->io
+ KS884X_INTERRUPTS_ENABLE
);
1511 static inline void hw_set_intr(struct ksz_hw
*hw
, uint interrupt
)
1513 hw
->intr_set
= interrupt
;
1514 writel(interrupt
, hw
->io
+ KS884X_INTERRUPTS_ENABLE
);
1517 static inline void hw_ena_intr(struct ksz_hw
*hw
)
1519 hw
->intr_blocked
= 0;
1520 hw_set_intr(hw
, hw
->intr_mask
);
1523 static inline void hw_dis_intr_bit(struct ksz_hw
*hw
, uint bit
)
1525 hw
->intr_mask
&= ~(bit
);
1528 static inline void hw_turn_off_intr(struct ksz_hw
*hw
, uint interrupt
)
1532 read_intr
= readl(hw
->io
+ KS884X_INTERRUPTS_ENABLE
);
1533 hw
->intr_set
= read_intr
& ~interrupt
;
1534 writel(hw
->intr_set
, hw
->io
+ KS884X_INTERRUPTS_ENABLE
);
1535 hw_dis_intr_bit(hw
, interrupt
);
1539 * hw_turn_on_intr - turn on specified interrupts
1540 * @hw: The hardware instance.
1541 * @bit: The interrupt bits to be on.
1543 * This routine turns on the specified interrupts in the interrupt mask so that
1544 * those interrupts will be enabled.
1546 static void hw_turn_on_intr(struct ksz_hw
*hw
, u32 bit
)
1548 hw
->intr_mask
|= bit
;
1550 if (!hw
->intr_blocked
)
1551 hw_set_intr(hw
, hw
->intr_mask
);
1554 static inline void hw_ena_intr_bit(struct ksz_hw
*hw
, uint interrupt
)
1558 read_intr
= readl(hw
->io
+ KS884X_INTERRUPTS_ENABLE
);
1559 hw
->intr_set
= read_intr
| interrupt
;
1560 writel(hw
->intr_set
, hw
->io
+ KS884X_INTERRUPTS_ENABLE
);
1563 static inline void hw_read_intr(struct ksz_hw
*hw
, uint
*status
)
1565 *status
= readl(hw
->io
+ KS884X_INTERRUPTS_STATUS
);
1566 *status
= *status
& hw
->intr_set
;
1569 static inline void hw_restore_intr(struct ksz_hw
*hw
, uint interrupt
)
1576 * hw_block_intr - block hardware interrupts
1578 * This function blocks all interrupts of the hardware and returns the current
1579 * interrupt enable mask so that interrupts can be restored later.
1581 * Return the current interrupt enable mask.
1583 static uint
hw_block_intr(struct ksz_hw
*hw
)
1587 if (!hw
->intr_blocked
) {
1589 interrupt
= hw
->intr_blocked
;
1595 * Hardware descriptor routines
1598 static inline void reset_desc(struct ksz_desc
*desc
, union desc_stat status
)
1600 status
.rx
.hw_owned
= 0;
1601 desc
->phw
->ctrl
.data
= cpu_to_le32(status
.data
);
1604 static inline void release_desc(struct ksz_desc
*desc
)
1606 desc
->sw
.ctrl
.tx
.hw_owned
= 1;
1607 if (desc
->sw
.buf_size
!= desc
->sw
.buf
.data
) {
1608 desc
->sw
.buf_size
= desc
->sw
.buf
.data
;
1609 desc
->phw
->buf
.data
= cpu_to_le32(desc
->sw
.buf
.data
);
1611 desc
->phw
->ctrl
.data
= cpu_to_le32(desc
->sw
.ctrl
.data
);
1614 static void get_rx_pkt(struct ksz_desc_info
*info
, struct ksz_desc
**desc
)
1616 *desc
= &info
->ring
[info
->last
];
1618 info
->last
&= info
->mask
;
1620 (*desc
)->sw
.buf
.data
&= ~KS_DESC_RX_MASK
;
1623 static inline void set_rx_buf(struct ksz_desc
*desc
, u32 addr
)
1625 desc
->phw
->addr
= cpu_to_le32(addr
);
1628 static inline void set_rx_len(struct ksz_desc
*desc
, u32 len
)
1630 desc
->sw
.buf
.rx
.buf_size
= len
;
1633 static inline void get_tx_pkt(struct ksz_desc_info
*info
,
1634 struct ksz_desc
**desc
)
1636 *desc
= &info
->ring
[info
->next
];
1638 info
->next
&= info
->mask
;
1640 (*desc
)->sw
.buf
.data
&= ~KS_DESC_TX_MASK
;
1643 static inline void set_tx_buf(struct ksz_desc
*desc
, u32 addr
)
1645 desc
->phw
->addr
= cpu_to_le32(addr
);
1648 static inline void set_tx_len(struct ksz_desc
*desc
, u32 len
)
1650 desc
->sw
.buf
.tx
.buf_size
= len
;
1653 /* Switch functions */
1655 #define TABLE_READ 0x10
1656 #define TABLE_SEL_SHIFT 2
1658 #define HW_DELAY(hw, reg) \
1661 dummy = readw(hw->io + reg); \
1665 * sw_r_table - read 4 bytes of data from switch table
1666 * @hw: The hardware instance.
1667 * @table: The table selector.
1668 * @addr: The address of the table entry.
1669 * @data: Buffer to store the read data.
1671 * This routine reads 4 bytes of data from the table of the switch.
1672 * Hardware interrupts are disabled to minimize corruption of read data.
1674 static void sw_r_table(struct ksz_hw
*hw
, int table
, u16 addr
, u32
*data
)
1679 ctrl_addr
= (((table
<< TABLE_SEL_SHIFT
) | TABLE_READ
) << 8) | addr
;
1681 interrupt
= hw_block_intr(hw
);
1683 writew(ctrl_addr
, hw
->io
+ KS884X_IACR_OFFSET
);
1684 HW_DELAY(hw
, KS884X_IACR_OFFSET
);
1685 *data
= readl(hw
->io
+ KS884X_ACC_DATA_0_OFFSET
);
1687 hw_restore_intr(hw
, interrupt
);
1691 * sw_w_table_64 - write 8 bytes of data to the switch table
1692 * @hw: The hardware instance.
1693 * @table: The table selector.
1694 * @addr: The address of the table entry.
1695 * @data_hi: The high part of data to be written (bit63 ~ bit32).
1696 * @data_lo: The low part of data to be written (bit31 ~ bit0).
1698 * This routine writes 8 bytes of data to the table of the switch.
1699 * Hardware interrupts are disabled to minimize corruption of written data.
1701 static void sw_w_table_64(struct ksz_hw
*hw
, int table
, u16 addr
, u32 data_hi
,
1707 ctrl_addr
= ((table
<< TABLE_SEL_SHIFT
) << 8) | addr
;
1709 interrupt
= hw_block_intr(hw
);
1711 writel(data_hi
, hw
->io
+ KS884X_ACC_DATA_4_OFFSET
);
1712 writel(data_lo
, hw
->io
+ KS884X_ACC_DATA_0_OFFSET
);
1714 writew(ctrl_addr
, hw
->io
+ KS884X_IACR_OFFSET
);
1715 HW_DELAY(hw
, KS884X_IACR_OFFSET
);
1717 hw_restore_intr(hw
, interrupt
);
1721 * sw_w_sta_mac_table - write to the static MAC table
1722 * @hw: The hardware instance.
1723 * @addr: The address of the table entry.
1724 * @mac_addr: The MAC address.
1725 * @ports: The port members.
1726 * @override: The flag to override the port receive/transmit settings.
1727 * @valid: The flag to indicate entry is valid.
1728 * @use_fid: The flag to indicate the FID is valid.
1729 * @fid: The FID value.
1731 * This routine writes an entry of the static MAC table of the switch. It
1732 * calls sw_w_table_64() to write the data.
1734 static void sw_w_sta_mac_table(struct ksz_hw
*hw
, u16 addr
, u8
*mac_addr
,
1735 u8 ports
, int override
, int valid
, int use_fid
, u8 fid
)
1740 data_lo
= ((u32
) mac_addr
[2] << 24) |
1741 ((u32
) mac_addr
[3] << 16) |
1742 ((u32
) mac_addr
[4] << 8) | mac_addr
[5];
1743 data_hi
= ((u32
) mac_addr
[0] << 8) | mac_addr
[1];
1744 data_hi
|= (u32
) ports
<< STATIC_MAC_FWD_PORTS_SHIFT
;
1747 data_hi
|= STATIC_MAC_TABLE_OVERRIDE
;
1749 data_hi
|= STATIC_MAC_TABLE_USE_FID
;
1750 data_hi
|= (u32
) fid
<< STATIC_MAC_FID_SHIFT
;
1753 data_hi
|= STATIC_MAC_TABLE_VALID
;
1755 sw_w_table_64(hw
, TABLE_STATIC_MAC
, addr
, data_hi
, data_lo
);
1759 * sw_r_vlan_table - read from the VLAN table
1760 * @hw: The hardware instance.
1761 * @addr: The address of the table entry.
1762 * @vid: Buffer to store the VID.
1763 * @fid: Buffer to store the VID.
1764 * @member: Buffer to store the port membership.
1766 * This function reads an entry of the VLAN table of the switch. It calls
1767 * sw_r_table() to get the data.
1769 * Return 0 if the entry is valid; otherwise -1.
1771 static int sw_r_vlan_table(struct ksz_hw
*hw
, u16 addr
, u16
*vid
, u8
*fid
,
1776 sw_r_table(hw
, TABLE_VLAN
, addr
, &data
);
1777 if (data
& VLAN_TABLE_VALID
) {
1778 *vid
= (u16
)(data
& VLAN_TABLE_VID
);
1779 *fid
= (u8
)((data
& VLAN_TABLE_FID
) >> VLAN_TABLE_FID_SHIFT
);
1780 *member
= (u8
)((data
& VLAN_TABLE_MEMBERSHIP
) >>
1781 VLAN_TABLE_MEMBERSHIP_SHIFT
);
1788 * port_r_mib_cnt - read MIB counter
1789 * @hw: The hardware instance.
1790 * @port: The port index.
1791 * @addr: The address of the counter.
1792 * @cnt: Buffer to store the counter.
1794 * This routine reads a MIB counter of the port.
1795 * Hardware interrupts are disabled to minimize corruption of read data.
1797 static void port_r_mib_cnt(struct ksz_hw
*hw
, int port
, u16 addr
, u64
*cnt
)
1804 ctrl_addr
= addr
+ PORT_COUNTER_NUM
* port
;
1806 interrupt
= hw_block_intr(hw
);
1808 ctrl_addr
|= (((TABLE_MIB
<< TABLE_SEL_SHIFT
) | TABLE_READ
) << 8);
1809 writew(ctrl_addr
, hw
->io
+ KS884X_IACR_OFFSET
);
1810 HW_DELAY(hw
, KS884X_IACR_OFFSET
);
1812 for (timeout
= 100; timeout
> 0; timeout
--) {
1813 data
= readl(hw
->io
+ KS884X_ACC_DATA_0_OFFSET
);
1815 if (data
& MIB_COUNTER_VALID
) {
1816 if (data
& MIB_COUNTER_OVERFLOW
)
1817 *cnt
+= MIB_COUNTER_VALUE
+ 1;
1818 *cnt
+= data
& MIB_COUNTER_VALUE
;
1823 hw_restore_intr(hw
, interrupt
);
1827 * port_r_mib_pkt - read dropped packet counts
1828 * @hw: The hardware instance.
1829 * @port: The port index.
1830 * @cnt: Buffer to store the receive and transmit dropped packet counts.
1832 * This routine reads the dropped packet counts of the port.
1833 * Hardware interrupts are disabled to minimize corruption of read data.
1835 static void port_r_mib_pkt(struct ksz_hw
*hw
, int port
, u32
*last
, u64
*cnt
)
1843 index
= KS_MIB_PACKET_DROPPED_RX_0
+ port
;
1845 interrupt
= hw_block_intr(hw
);
1847 ctrl_addr
= (u16
) index
;
1848 ctrl_addr
|= (((TABLE_MIB
<< TABLE_SEL_SHIFT
) | TABLE_READ
)
1850 writew(ctrl_addr
, hw
->io
+ KS884X_IACR_OFFSET
);
1851 HW_DELAY(hw
, KS884X_IACR_OFFSET
);
1852 data
= readl(hw
->io
+ KS884X_ACC_DATA_0_OFFSET
);
1854 hw_restore_intr(hw
, interrupt
);
1856 data
&= MIB_PACKET_DROPPED
;
1861 data
+= MIB_PACKET_DROPPED
+ 1;
1867 index
-= KS_MIB_PACKET_DROPPED_TX
-
1868 KS_MIB_PACKET_DROPPED_TX_0
+ 1;
1869 } while (index
>= KS_MIB_PACKET_DROPPED_TX_0
+ port
);
1873 * port_r_cnt - read MIB counters periodically
1874 * @hw: The hardware instance.
1875 * @port: The port index.
1877 * This routine is used to read the counters of the port periodically to avoid
1878 * counter overflow. The hardware should be acquired first before calling this
1881 * Return non-zero when not all counters not read.
1883 static int port_r_cnt(struct ksz_hw
*hw
, int port
)
1885 struct ksz_port_mib
*mib
= &hw
->port_mib
[port
];
1887 if (mib
->mib_start
< PORT_COUNTER_NUM
)
1888 while (mib
->cnt_ptr
< PORT_COUNTER_NUM
) {
1889 port_r_mib_cnt(hw
, port
, mib
->cnt_ptr
,
1890 &mib
->counter
[mib
->cnt_ptr
]);
1893 if (hw
->mib_cnt
> PORT_COUNTER_NUM
)
1894 port_r_mib_pkt(hw
, port
, mib
->dropped
,
1895 &mib
->counter
[PORT_COUNTER_NUM
]);
1901 * port_init_cnt - initialize MIB counter values
1902 * @hw: The hardware instance.
1903 * @port: The port index.
1905 * This routine is used to initialize all counters to zero if the hardware
1906 * cannot do it after reset.
1908 static void port_init_cnt(struct ksz_hw
*hw
, int port
)
1910 struct ksz_port_mib
*mib
= &hw
->port_mib
[port
];
1913 if (mib
->mib_start
< PORT_COUNTER_NUM
)
1915 port_r_mib_cnt(hw
, port
, mib
->cnt_ptr
,
1916 &mib
->counter
[mib
->cnt_ptr
]);
1918 } while (mib
->cnt_ptr
< PORT_COUNTER_NUM
);
1919 if (hw
->mib_cnt
> PORT_COUNTER_NUM
)
1920 port_r_mib_pkt(hw
, port
, mib
->dropped
,
1921 &mib
->counter
[PORT_COUNTER_NUM
]);
1922 memset((void *) mib
->counter
, 0, sizeof(u64
) * TOTAL_PORT_COUNTER_NUM
);
1931 * port_chk - check port register bits
1932 * @hw: The hardware instance.
1933 * @port: The port index.
1934 * @offset: The offset of the port register.
1935 * @bits: The data bits to check.
1937 * This function checks whether the specified bits of the port register are set
1940 * Return 0 if the bits are not set.
1942 static int port_chk(struct ksz_hw
*hw
, int port
, int offset
, u16 bits
)
1947 PORT_CTRL_ADDR(port
, addr
);
1949 data
= readw(hw
->io
+ addr
);
1950 return (data
& bits
) == bits
;
1954 * port_cfg - set port register bits
1955 * @hw: The hardware instance.
1956 * @port: The port index.
1957 * @offset: The offset of the port register.
1958 * @bits: The data bits to set.
1959 * @set: The flag indicating whether the bits are to be set or not.
1961 * This routine sets or resets the specified bits of the port register.
1963 static void port_cfg(struct ksz_hw
*hw
, int port
, int offset
, u16 bits
,
1969 PORT_CTRL_ADDR(port
, addr
);
1971 data
= readw(hw
->io
+ addr
);
1976 writew(data
, hw
->io
+ addr
);
1980 * port_chk_shift - check port bit
1981 * @hw: The hardware instance.
1982 * @port: The port index.
1983 * @offset: The offset of the register.
1984 * @shift: Number of bits to shift.
1986 * This function checks whether the specified port is set in the register or
1989 * Return 0 if the port is not set.
1991 static int port_chk_shift(struct ksz_hw
*hw
, int port
, u32 addr
, int shift
)
1994 u16 bit
= 1 << port
;
1996 data
= readw(hw
->io
+ addr
);
1998 return (data
& bit
) == bit
;
2002 * port_cfg_shift - set port bit
2003 * @hw: The hardware instance.
2004 * @port: The port index.
2005 * @offset: The offset of the register.
2006 * @shift: Number of bits to shift.
2007 * @set: The flag indicating whether the port is to be set or not.
2009 * This routine sets or resets the specified port in the register.
2011 static void port_cfg_shift(struct ksz_hw
*hw
, int port
, u32 addr
, int shift
,
2015 u16 bits
= 1 << port
;
2017 data
= readw(hw
->io
+ addr
);
2023 writew(data
, hw
->io
+ addr
);
2027 * port_r8 - read byte from port register
2028 * @hw: The hardware instance.
2029 * @port: The port index.
2030 * @offset: The offset of the port register.
2031 * @data: Buffer to store the data.
2033 * This routine reads a byte from the port register.
2035 static void port_r8(struct ksz_hw
*hw
, int port
, int offset
, u8
*data
)
2039 PORT_CTRL_ADDR(port
, addr
);
2041 *data
= readb(hw
->io
+ addr
);
2045 * port_r16 - read word from port register.
2046 * @hw: The hardware instance.
2047 * @port: The port index.
2048 * @offset: The offset of the port register.
2049 * @data: Buffer to store the data.
2051 * This routine reads a word from the port register.
2053 static void port_r16(struct ksz_hw
*hw
, int port
, int offset
, u16
*data
)
2057 PORT_CTRL_ADDR(port
, addr
);
2059 *data
= readw(hw
->io
+ addr
);
2063 * port_w16 - write word to port register.
2064 * @hw: The hardware instance.
2065 * @port: The port index.
2066 * @offset: The offset of the port register.
2067 * @data: Data to write.
2069 * This routine writes a word to the port register.
2071 static void port_w16(struct ksz_hw
*hw
, int port
, int offset
, u16 data
)
2075 PORT_CTRL_ADDR(port
, addr
);
2077 writew(data
, hw
->io
+ addr
);
2081 * sw_chk - check switch register bits
2082 * @hw: The hardware instance.
2083 * @addr: The address of the switch register.
2084 * @bits: The data bits to check.
2086 * This function checks whether the specified bits of the switch register are
2089 * Return 0 if the bits are not set.
2091 static int sw_chk(struct ksz_hw
*hw
, u32 addr
, u16 bits
)
2095 data
= readw(hw
->io
+ addr
);
2096 return (data
& bits
) == bits
;
2100 * sw_cfg - set switch register bits
2101 * @hw: The hardware instance.
2102 * @addr: The address of the switch register.
2103 * @bits: The data bits to set.
2104 * @set: The flag indicating whether the bits are to be set or not.
2106 * This function sets or resets the specified bits of the switch register.
2108 static void sw_cfg(struct ksz_hw
*hw
, u32 addr
, u16 bits
, int set
)
2112 data
= readw(hw
->io
+ addr
);
2117 writew(data
, hw
->io
+ addr
);
2122 static inline void port_cfg_broad_storm(struct ksz_hw
*hw
, int p
, int set
)
2125 KS8842_PORT_CTRL_1_OFFSET
, PORT_BROADCAST_STORM
, set
);
2128 static inline int port_chk_broad_storm(struct ksz_hw
*hw
, int p
)
2130 return port_chk(hw
, p
,
2131 KS8842_PORT_CTRL_1_OFFSET
, PORT_BROADCAST_STORM
);
2134 /* Driver set switch broadcast storm protection at 10% rate. */
2135 #define BROADCAST_STORM_PROTECTION_RATE 10
2137 /* 148,800 frames * 67 ms / 100 */
2138 #define BROADCAST_STORM_VALUE 9969
2141 * sw_cfg_broad_storm - configure broadcast storm threshold
2142 * @hw: The hardware instance.
2143 * @percent: Broadcast storm threshold in percent of transmit rate.
2145 * This routine configures the broadcast storm threshold of the switch.
2147 static void sw_cfg_broad_storm(struct ksz_hw
*hw
, u8 percent
)
2150 u32 value
= ((u32
) BROADCAST_STORM_VALUE
* (u32
) percent
/ 100);
2152 if (value
> BROADCAST_STORM_RATE
)
2153 value
= BROADCAST_STORM_RATE
;
2155 data
= readw(hw
->io
+ KS8842_SWITCH_CTRL_3_OFFSET
);
2156 data
&= ~(BROADCAST_STORM_RATE_LO
| BROADCAST_STORM_RATE_HI
);
2157 data
|= ((value
& 0x00FF) << 8) | ((value
& 0xFF00) >> 8);
2158 writew(data
, hw
->io
+ KS8842_SWITCH_CTRL_3_OFFSET
);
2162 * sw_get_board_storm - get broadcast storm threshold
2163 * @hw: The hardware instance.
2164 * @percent: Buffer to store the broadcast storm threshold percentage.
2166 * This routine retrieves the broadcast storm threshold of the switch.
2168 static void sw_get_broad_storm(struct ksz_hw
*hw
, u8
*percent
)
2173 data
= readw(hw
->io
+ KS8842_SWITCH_CTRL_3_OFFSET
);
2174 num
= (data
& BROADCAST_STORM_RATE_HI
);
2176 num
|= (data
& BROADCAST_STORM_RATE_LO
) >> 8;
2177 num
= (num
* 100 + BROADCAST_STORM_VALUE
/ 2) / BROADCAST_STORM_VALUE
;
2178 *percent
= (u8
) num
;
2182 * sw_dis_broad_storm - disable broadstorm
2183 * @hw: The hardware instance.
2184 * @port: The port index.
2186 * This routine disables the broadcast storm limit function of the switch.
2188 static void sw_dis_broad_storm(struct ksz_hw
*hw
, int port
)
2190 port_cfg_broad_storm(hw
, port
, 0);
2194 * sw_ena_broad_storm - enable broadcast storm
2195 * @hw: The hardware instance.
2196 * @port: The port index.
2198 * This routine enables the broadcast storm limit function of the switch.
2200 static void sw_ena_broad_storm(struct ksz_hw
*hw
, int port
)
2202 sw_cfg_broad_storm(hw
, hw
->ksz_switch
->broad_per
);
2203 port_cfg_broad_storm(hw
, port
, 1);
2207 * sw_init_broad_storm - initialize broadcast storm
2208 * @hw: The hardware instance.
2210 * This routine initializes the broadcast storm limit function of the switch.
2212 static void sw_init_broad_storm(struct ksz_hw
*hw
)
2216 hw
->ksz_switch
->broad_per
= 1;
2217 sw_cfg_broad_storm(hw
, hw
->ksz_switch
->broad_per
);
2218 for (port
= 0; port
< TOTAL_PORT_NUM
; port
++)
2219 sw_dis_broad_storm(hw
, port
);
2220 sw_cfg(hw
, KS8842_SWITCH_CTRL_2_OFFSET
, MULTICAST_STORM_DISABLE
, 1);
2224 * hw_cfg_broad_storm - configure broadcast storm
2225 * @hw: The hardware instance.
2226 * @percent: Broadcast storm threshold in percent of transmit rate.
2228 * This routine configures the broadcast storm threshold of the switch.
2229 * It is called by user functions. The hardware should be acquired first.
2231 static void hw_cfg_broad_storm(struct ksz_hw
*hw
, u8 percent
)
2236 sw_cfg_broad_storm(hw
, percent
);
2237 sw_get_broad_storm(hw
, &percent
);
2238 hw
->ksz_switch
->broad_per
= percent
;
2242 * sw_dis_prio_rate - disable switch priority rate
2243 * @hw: The hardware instance.
2244 * @port: The port index.
2246 * This routine disables the priority rate function of the switch.
2248 static void sw_dis_prio_rate(struct ksz_hw
*hw
, int port
)
2252 PORT_CTRL_ADDR(port
, addr
);
2253 addr
+= KS8842_PORT_IN_RATE_OFFSET
;
2254 writel(0, hw
->io
+ addr
);
2258 * sw_init_prio_rate - initialize switch prioirty rate
2259 * @hw: The hardware instance.
2261 * This routine initializes the priority rate function of the switch.
2263 static void sw_init_prio_rate(struct ksz_hw
*hw
)
2267 struct ksz_switch
*sw
= hw
->ksz_switch
;
2269 for (port
= 0; port
< TOTAL_PORT_NUM
; port
++) {
2270 for (prio
= 0; prio
< PRIO_QUEUES
; prio
++) {
2271 sw
->port_cfg
[port
].rx_rate
[prio
] =
2272 sw
->port_cfg
[port
].tx_rate
[prio
] = 0;
2274 sw_dis_prio_rate(hw
, port
);
2280 static inline void port_cfg_back_pressure(struct ksz_hw
*hw
, int p
, int set
)
2283 KS8842_PORT_CTRL_2_OFFSET
, PORT_BACK_PRESSURE
, set
);
2286 static inline void port_cfg_force_flow_ctrl(struct ksz_hw
*hw
, int p
, int set
)
2289 KS8842_PORT_CTRL_2_OFFSET
, PORT_FORCE_FLOW_CTRL
, set
);
2292 static inline int port_chk_back_pressure(struct ksz_hw
*hw
, int p
)
2294 return port_chk(hw
, p
,
2295 KS8842_PORT_CTRL_2_OFFSET
, PORT_BACK_PRESSURE
);
2298 static inline int port_chk_force_flow_ctrl(struct ksz_hw
*hw
, int p
)
2300 return port_chk(hw
, p
,
2301 KS8842_PORT_CTRL_2_OFFSET
, PORT_FORCE_FLOW_CTRL
);
2306 static inline void port_cfg_dis_learn(struct ksz_hw
*hw
, int p
, int set
)
2309 KS8842_PORT_CTRL_2_OFFSET
, PORT_LEARN_DISABLE
, set
);
2312 static inline void port_cfg_rx(struct ksz_hw
*hw
, int p
, int set
)
2315 KS8842_PORT_CTRL_2_OFFSET
, PORT_RX_ENABLE
, set
);
2318 static inline void port_cfg_tx(struct ksz_hw
*hw
, int p
, int set
)
2321 KS8842_PORT_CTRL_2_OFFSET
, PORT_TX_ENABLE
, set
);
2324 static inline void sw_cfg_fast_aging(struct ksz_hw
*hw
, int set
)
2326 sw_cfg(hw
, KS8842_SWITCH_CTRL_1_OFFSET
, SWITCH_FAST_AGING
, set
);
2329 static inline void sw_flush_dyn_mac_table(struct ksz_hw
*hw
)
2331 if (!(hw
->overrides
& FAST_AGING
)) {
2332 sw_cfg_fast_aging(hw
, 1);
2334 sw_cfg_fast_aging(hw
, 0);
2340 static inline void port_cfg_ins_tag(struct ksz_hw
*hw
, int p
, int insert
)
2343 KS8842_PORT_CTRL_1_OFFSET
, PORT_INSERT_TAG
, insert
);
2346 static inline void port_cfg_rmv_tag(struct ksz_hw
*hw
, int p
, int remove
)
2349 KS8842_PORT_CTRL_1_OFFSET
, PORT_REMOVE_TAG
, remove
);
2352 static inline int port_chk_ins_tag(struct ksz_hw
*hw
, int p
)
2354 return port_chk(hw
, p
,
2355 KS8842_PORT_CTRL_1_OFFSET
, PORT_INSERT_TAG
);
2358 static inline int port_chk_rmv_tag(struct ksz_hw
*hw
, int p
)
2360 return port_chk(hw
, p
,
2361 KS8842_PORT_CTRL_1_OFFSET
, PORT_REMOVE_TAG
);
2364 static inline void port_cfg_dis_non_vid(struct ksz_hw
*hw
, int p
, int set
)
2367 KS8842_PORT_CTRL_2_OFFSET
, PORT_DISCARD_NON_VID
, set
);
2370 static inline void port_cfg_in_filter(struct ksz_hw
*hw
, int p
, int set
)
2373 KS8842_PORT_CTRL_2_OFFSET
, PORT_INGRESS_VLAN_FILTER
, set
);
2376 static inline int port_chk_dis_non_vid(struct ksz_hw
*hw
, int p
)
2378 return port_chk(hw
, p
,
2379 KS8842_PORT_CTRL_2_OFFSET
, PORT_DISCARD_NON_VID
);
2382 static inline int port_chk_in_filter(struct ksz_hw
*hw
, int p
)
2384 return port_chk(hw
, p
,
2385 KS8842_PORT_CTRL_2_OFFSET
, PORT_INGRESS_VLAN_FILTER
);
2390 static inline void port_cfg_mirror_sniffer(struct ksz_hw
*hw
, int p
, int set
)
2393 KS8842_PORT_CTRL_2_OFFSET
, PORT_MIRROR_SNIFFER
, set
);
2396 static inline void port_cfg_mirror_rx(struct ksz_hw
*hw
, int p
, int set
)
2399 KS8842_PORT_CTRL_2_OFFSET
, PORT_MIRROR_RX
, set
);
2402 static inline void port_cfg_mirror_tx(struct ksz_hw
*hw
, int p
, int set
)
2405 KS8842_PORT_CTRL_2_OFFSET
, PORT_MIRROR_TX
, set
);
2408 static inline void sw_cfg_mirror_rx_tx(struct ksz_hw
*hw
, int set
)
2410 sw_cfg(hw
, KS8842_SWITCH_CTRL_2_OFFSET
, SWITCH_MIRROR_RX_TX
, set
);
2413 static void sw_init_mirror(struct ksz_hw
*hw
)
2417 for (port
= 0; port
< TOTAL_PORT_NUM
; port
++) {
2418 port_cfg_mirror_sniffer(hw
, port
, 0);
2419 port_cfg_mirror_rx(hw
, port
, 0);
2420 port_cfg_mirror_tx(hw
, port
, 0);
2422 sw_cfg_mirror_rx_tx(hw
, 0);
2425 static inline void sw_cfg_unk_def_deliver(struct ksz_hw
*hw
, int set
)
2427 sw_cfg(hw
, KS8842_SWITCH_CTRL_7_OFFSET
,
2428 SWITCH_UNK_DEF_PORT_ENABLE
, set
);
2431 static inline int sw_cfg_chk_unk_def_deliver(struct ksz_hw
*hw
)
2433 return sw_chk(hw
, KS8842_SWITCH_CTRL_7_OFFSET
,
2434 SWITCH_UNK_DEF_PORT_ENABLE
);
2437 static inline void sw_cfg_unk_def_port(struct ksz_hw
*hw
, int port
, int set
)
2439 port_cfg_shift(hw
, port
, KS8842_SWITCH_CTRL_7_OFFSET
, 0, set
);
2442 static inline int sw_chk_unk_def_port(struct ksz_hw
*hw
, int port
)
2444 return port_chk_shift(hw
, port
, KS8842_SWITCH_CTRL_7_OFFSET
, 0);
2449 static inline void port_cfg_diffserv(struct ksz_hw
*hw
, int p
, int set
)
2452 KS8842_PORT_CTRL_1_OFFSET
, PORT_DIFFSERV_ENABLE
, set
);
2455 static inline void port_cfg_802_1p(struct ksz_hw
*hw
, int p
, int set
)
2458 KS8842_PORT_CTRL_1_OFFSET
, PORT_802_1P_ENABLE
, set
);
2461 static inline void port_cfg_replace_vid(struct ksz_hw
*hw
, int p
, int set
)
2464 KS8842_PORT_CTRL_2_OFFSET
, PORT_USER_PRIORITY_CEILING
, set
);
2467 static inline void port_cfg_prio(struct ksz_hw
*hw
, int p
, int set
)
2470 KS8842_PORT_CTRL_1_OFFSET
, PORT_PRIO_QUEUE_ENABLE
, set
);
2473 static inline int port_chk_diffserv(struct ksz_hw
*hw
, int p
)
2475 return port_chk(hw
, p
,
2476 KS8842_PORT_CTRL_1_OFFSET
, PORT_DIFFSERV_ENABLE
);
2479 static inline int port_chk_802_1p(struct ksz_hw
*hw
, int p
)
2481 return port_chk(hw
, p
,
2482 KS8842_PORT_CTRL_1_OFFSET
, PORT_802_1P_ENABLE
);
2485 static inline int port_chk_replace_vid(struct ksz_hw
*hw
, int p
)
2487 return port_chk(hw
, p
,
2488 KS8842_PORT_CTRL_2_OFFSET
, PORT_USER_PRIORITY_CEILING
);
2491 static inline int port_chk_prio(struct ksz_hw
*hw
, int p
)
2493 return port_chk(hw
, p
,
2494 KS8842_PORT_CTRL_1_OFFSET
, PORT_PRIO_QUEUE_ENABLE
);
2498 * sw_dis_diffserv - disable switch DiffServ priority
2499 * @hw: The hardware instance.
2500 * @port: The port index.
2502 * This routine disables the DiffServ priority function of the switch.
2504 static void sw_dis_diffserv(struct ksz_hw
*hw
, int port
)
2506 port_cfg_diffserv(hw
, port
, 0);
2510 * sw_dis_802_1p - disable switch 802.1p priority
2511 * @hw: The hardware instance.
2512 * @port: The port index.
2514 * This routine disables the 802.1p priority function of the switch.
2516 static void sw_dis_802_1p(struct ksz_hw
*hw
, int port
)
2518 port_cfg_802_1p(hw
, port
, 0);
2522 * sw_cfg_replace_null_vid -
2523 * @hw: The hardware instance.
2524 * @set: The flag to disable or enable.
2527 static void sw_cfg_replace_null_vid(struct ksz_hw
*hw
, int set
)
2529 sw_cfg(hw
, KS8842_SWITCH_CTRL_3_OFFSET
, SWITCH_REPLACE_NULL_VID
, set
);
2533 * sw_cfg_replace_vid - enable switch 802.10 priority re-mapping
2534 * @hw: The hardware instance.
2535 * @port: The port index.
2536 * @set: The flag to disable or enable.
2538 * This routine enables the 802.1p priority re-mapping function of the switch.
2539 * That allows 802.1p priority field to be replaced with the port's default
2540 * tag's priority value if the ingress packet's 802.1p priority has a higher
2541 * priority than port's default tag's priority.
2543 static void sw_cfg_replace_vid(struct ksz_hw
*hw
, int port
, int set
)
2545 port_cfg_replace_vid(hw
, port
, set
);
2549 * sw_cfg_port_based - configure switch port based priority
2550 * @hw: The hardware instance.
2551 * @port: The port index.
2552 * @prio: The priority to set.
2554 * This routine configures the port based priority of the switch.
2556 static void sw_cfg_port_based(struct ksz_hw
*hw
, int port
, u8 prio
)
2560 if (prio
> PORT_BASED_PRIORITY_BASE
)
2561 prio
= PORT_BASED_PRIORITY_BASE
;
2563 hw
->ksz_switch
->port_cfg
[port
].port_prio
= prio
;
2565 port_r16(hw
, port
, KS8842_PORT_CTRL_1_OFFSET
, &data
);
2566 data
&= ~PORT_BASED_PRIORITY_MASK
;
2567 data
|= prio
<< PORT_BASED_PRIORITY_SHIFT
;
2568 port_w16(hw
, port
, KS8842_PORT_CTRL_1_OFFSET
, data
);
2572 * sw_dis_multi_queue - disable transmit multiple queues
2573 * @hw: The hardware instance.
2574 * @port: The port index.
2576 * This routine disables the transmit multiple queues selection of the switch
2577 * port. Only single transmit queue on the port.
2579 static void sw_dis_multi_queue(struct ksz_hw
*hw
, int port
)
2581 port_cfg_prio(hw
, port
, 0);
2585 * sw_init_prio - initialize switch priority
2586 * @hw: The hardware instance.
2588 * This routine initializes the switch QoS priority functions.
2590 static void sw_init_prio(struct ksz_hw
*hw
)
2594 struct ksz_switch
*sw
= hw
->ksz_switch
;
2597 * Init all the 802.1p tag priority value to be assigned to different
2600 sw
->p_802_1p
[0] = 0;
2601 sw
->p_802_1p
[1] = 0;
2602 sw
->p_802_1p
[2] = 1;
2603 sw
->p_802_1p
[3] = 1;
2604 sw
->p_802_1p
[4] = 2;
2605 sw
->p_802_1p
[5] = 2;
2606 sw
->p_802_1p
[6] = 3;
2607 sw
->p_802_1p
[7] = 3;
2610 * Init all the DiffServ priority value to be assigned to priority
2613 for (tos
= 0; tos
< DIFFSERV_ENTRIES
; tos
++)
2614 sw
->diffserv
[tos
] = 0;
2616 /* All QoS functions disabled. */
2617 for (port
= 0; port
< TOTAL_PORT_NUM
; port
++) {
2618 sw_dis_multi_queue(hw
, port
);
2619 sw_dis_diffserv(hw
, port
);
2620 sw_dis_802_1p(hw
, port
);
2621 sw_cfg_replace_vid(hw
, port
, 0);
2623 sw
->port_cfg
[port
].port_prio
= 0;
2624 sw_cfg_port_based(hw
, port
, sw
->port_cfg
[port
].port_prio
);
2626 sw_cfg_replace_null_vid(hw
, 0);
2630 * port_get_def_vid - get port default VID.
2631 * @hw: The hardware instance.
2632 * @port: The port index.
2633 * @vid: Buffer to store the VID.
2635 * This routine retrieves the default VID of the port.
2637 static void port_get_def_vid(struct ksz_hw
*hw
, int port
, u16
*vid
)
2641 PORT_CTRL_ADDR(port
, addr
);
2642 addr
+= KS8842_PORT_CTRL_VID_OFFSET
;
2643 *vid
= readw(hw
->io
+ addr
);
2647 * sw_init_vlan - initialize switch VLAN
2648 * @hw: The hardware instance.
2650 * This routine initializes the VLAN function of the switch.
2652 static void sw_init_vlan(struct ksz_hw
*hw
)
2656 struct ksz_switch
*sw
= hw
->ksz_switch
;
2658 /* Read 16 VLAN entries from device's VLAN table. */
2659 for (entry
= 0; entry
< VLAN_TABLE_ENTRIES
; entry
++) {
2660 sw_r_vlan_table(hw
, entry
,
2661 &sw
->vlan_table
[entry
].vid
,
2662 &sw
->vlan_table
[entry
].fid
,
2663 &sw
->vlan_table
[entry
].member
);
2666 for (port
= 0; port
< TOTAL_PORT_NUM
; port
++) {
2667 port_get_def_vid(hw
, port
, &sw
->port_cfg
[port
].vid
);
2668 sw
->port_cfg
[port
].member
= PORT_MASK
;
2673 * sw_cfg_port_base_vlan - configure port-based VLAN membership
2674 * @hw: The hardware instance.
2675 * @port: The port index.
2676 * @member: The port-based VLAN membership.
2678 * This routine configures the port-based VLAN membership of the port.
2680 static void sw_cfg_port_base_vlan(struct ksz_hw
*hw
, int port
, u8 member
)
2685 PORT_CTRL_ADDR(port
, addr
);
2686 addr
+= KS8842_PORT_CTRL_2_OFFSET
;
2688 data
= readb(hw
->io
+ addr
);
2689 data
&= ~PORT_VLAN_MEMBERSHIP
;
2690 data
|= (member
& PORT_MASK
);
2691 writeb(data
, hw
->io
+ addr
);
2693 hw
->ksz_switch
->port_cfg
[port
].member
= member
;
2697 * sw_get_addr - get the switch MAC address.
2698 * @hw: The hardware instance.
2699 * @mac_addr: Buffer to store the MAC address.
2701 * This function retrieves the MAC address of the switch.
2703 static inline void sw_get_addr(struct ksz_hw
*hw
, u8
*mac_addr
)
2707 for (i
= 0; i
< 6; i
+= 2) {
2708 mac_addr
[i
] = readb(hw
->io
+ KS8842_MAC_ADDR_0_OFFSET
+ i
);
2709 mac_addr
[1 + i
] = readb(hw
->io
+ KS8842_MAC_ADDR_1_OFFSET
+ i
);
2714 * sw_set_addr - configure switch MAC address
2715 * @hw: The hardware instance.
2716 * @mac_addr: The MAC address.
2718 * This function configures the MAC address of the switch.
2720 static void sw_set_addr(struct ksz_hw
*hw
, u8
*mac_addr
)
2724 for (i
= 0; i
< 6; i
+= 2) {
2725 writeb(mac_addr
[i
], hw
->io
+ KS8842_MAC_ADDR_0_OFFSET
+ i
);
2726 writeb(mac_addr
[1 + i
], hw
->io
+ KS8842_MAC_ADDR_1_OFFSET
+ i
);
2731 * sw_set_global_ctrl - set switch global control
2732 * @hw: The hardware instance.
2734 * This routine sets the global control of the switch function.
2736 static void sw_set_global_ctrl(struct ksz_hw
*hw
)
2740 /* Enable switch MII flow control. */
2741 data
= readw(hw
->io
+ KS8842_SWITCH_CTRL_3_OFFSET
);
2742 data
|= SWITCH_FLOW_CTRL
;
2743 writew(data
, hw
->io
+ KS8842_SWITCH_CTRL_3_OFFSET
);
2745 data
= readw(hw
->io
+ KS8842_SWITCH_CTRL_1_OFFSET
);
2747 /* Enable aggressive back off algorithm in half duplex mode. */
2748 data
|= SWITCH_AGGR_BACKOFF
;
2750 /* Enable automatic fast aging when link changed detected. */
2751 data
|= SWITCH_AGING_ENABLE
;
2752 data
|= SWITCH_LINK_AUTO_AGING
;
2754 if (hw
->overrides
& FAST_AGING
)
2755 data
|= SWITCH_FAST_AGING
;
2757 data
&= ~SWITCH_FAST_AGING
;
2758 writew(data
, hw
->io
+ KS8842_SWITCH_CTRL_1_OFFSET
);
2760 data
= readw(hw
->io
+ KS8842_SWITCH_CTRL_2_OFFSET
);
2762 /* Enable no excessive collision drop. */
2763 data
|= NO_EXC_COLLISION_DROP
;
2764 writew(data
, hw
->io
+ KS8842_SWITCH_CTRL_2_OFFSET
);
2768 STP_STATE_DISABLED
= 0,
2769 STP_STATE_LISTENING
,
2771 STP_STATE_FORWARDING
,
2777 * port_set_stp_state - configure port spanning tree state
2778 * @hw: The hardware instance.
2779 * @port: The port index.
2780 * @state: The spanning tree state.
2782 * This routine configures the spanning tree state of the port.
2784 static void port_set_stp_state(struct ksz_hw
*hw
, int port
, int state
)
2788 port_r16(hw
, port
, KS8842_PORT_CTRL_2_OFFSET
, &data
);
2790 case STP_STATE_DISABLED
:
2791 data
&= ~(PORT_TX_ENABLE
| PORT_RX_ENABLE
);
2792 data
|= PORT_LEARN_DISABLE
;
2794 case STP_STATE_LISTENING
:
2796 * No need to turn on transmit because of port direct mode.
2797 * Turning on receive is required if static MAC table is not setup.
2799 data
&= ~PORT_TX_ENABLE
;
2800 data
|= PORT_RX_ENABLE
;
2801 data
|= PORT_LEARN_DISABLE
;
2803 case STP_STATE_LEARNING
:
2804 data
&= ~PORT_TX_ENABLE
;
2805 data
|= PORT_RX_ENABLE
;
2806 data
&= ~PORT_LEARN_DISABLE
;
2808 case STP_STATE_FORWARDING
:
2809 data
|= (PORT_TX_ENABLE
| PORT_RX_ENABLE
);
2810 data
&= ~PORT_LEARN_DISABLE
;
2812 case STP_STATE_BLOCKED
:
2814 * Need to setup static MAC table with override to keep receiving BPDU
2815 * messages. See sw_init_stp routine.
2817 data
&= ~(PORT_TX_ENABLE
| PORT_RX_ENABLE
);
2818 data
|= PORT_LEARN_DISABLE
;
2820 case STP_STATE_SIMPLE
:
2821 data
|= (PORT_TX_ENABLE
| PORT_RX_ENABLE
);
2822 data
|= PORT_LEARN_DISABLE
;
2825 port_w16(hw
, port
, KS8842_PORT_CTRL_2_OFFSET
, data
);
2826 hw
->ksz_switch
->port_cfg
[port
].stp_state
= state
;
2830 #define BROADCAST_ENTRY 1
2831 #define BRIDGE_ADDR_ENTRY 2
2832 #define IPV6_ADDR_ENTRY 3
2835 * sw_clr_sta_mac_table - clear static MAC table
2836 * @hw: The hardware instance.
2838 * This routine clears the static MAC table.
2840 static void sw_clr_sta_mac_table(struct ksz_hw
*hw
)
2842 struct ksz_mac_table
*entry
;
2845 for (i
= 0; i
< STATIC_MAC_TABLE_ENTRIES
; i
++) {
2846 entry
= &hw
->ksz_switch
->mac_table
[i
];
2847 sw_w_sta_mac_table(hw
, i
,
2848 entry
->mac_addr
, entry
->ports
,
2850 entry
->use_fid
, entry
->fid
);
2855 * sw_init_stp - initialize switch spanning tree support
2856 * @hw: The hardware instance.
2858 * This routine initializes the spanning tree support of the switch.
2860 static void sw_init_stp(struct ksz_hw
*hw
)
2862 struct ksz_mac_table
*entry
;
2864 entry
= &hw
->ksz_switch
->mac_table
[STP_ENTRY
];
2865 entry
->mac_addr
[0] = 0x01;
2866 entry
->mac_addr
[1] = 0x80;
2867 entry
->mac_addr
[2] = 0xC2;
2868 entry
->mac_addr
[3] = 0x00;
2869 entry
->mac_addr
[4] = 0x00;
2870 entry
->mac_addr
[5] = 0x00;
2871 entry
->ports
= HOST_MASK
;
2872 entry
->override
= 1;
2874 sw_w_sta_mac_table(hw
, STP_ENTRY
,
2875 entry
->mac_addr
, entry
->ports
,
2876 entry
->override
, entry
->valid
,
2877 entry
->use_fid
, entry
->fid
);
2881 * sw_block_addr - block certain packets from the host port
2882 * @hw: The hardware instance.
2884 * This routine blocks certain packets from reaching to the host port.
2886 static void sw_block_addr(struct ksz_hw
*hw
)
2888 struct ksz_mac_table
*entry
;
2891 for (i
= BROADCAST_ENTRY
; i
<= IPV6_ADDR_ENTRY
; i
++) {
2892 entry
= &hw
->ksz_switch
->mac_table
[i
];
2894 sw_w_sta_mac_table(hw
, i
,
2895 entry
->mac_addr
, entry
->ports
,
2896 entry
->override
, entry
->valid
,
2897 entry
->use_fid
, entry
->fid
);
2901 #define PHY_LINK_SUPPORT \
2902 (PHY_AUTO_NEG_ASYM_PAUSE | \
2903 PHY_AUTO_NEG_SYM_PAUSE | \
2904 PHY_AUTO_NEG_100BT4 | \
2905 PHY_AUTO_NEG_100BTX_FD | \
2906 PHY_AUTO_NEG_100BTX | \
2907 PHY_AUTO_NEG_10BT_FD | \
2910 static inline void hw_r_phy_ctrl(struct ksz_hw
*hw
, int phy
, u16
*data
)
2912 *data
= readw(hw
->io
+ phy
+ KS884X_PHY_CTRL_OFFSET
);
2915 static inline void hw_w_phy_ctrl(struct ksz_hw
*hw
, int phy
, u16 data
)
2917 writew(data
, hw
->io
+ phy
+ KS884X_PHY_CTRL_OFFSET
);
2920 static inline void hw_r_phy_link_stat(struct ksz_hw
*hw
, int phy
, u16
*data
)
2922 *data
= readw(hw
->io
+ phy
+ KS884X_PHY_STATUS_OFFSET
);
2925 static inline void hw_r_phy_auto_neg(struct ksz_hw
*hw
, int phy
, u16
*data
)
2927 *data
= readw(hw
->io
+ phy
+ KS884X_PHY_AUTO_NEG_OFFSET
);
2930 static inline void hw_w_phy_auto_neg(struct ksz_hw
*hw
, int phy
, u16 data
)
2932 writew(data
, hw
->io
+ phy
+ KS884X_PHY_AUTO_NEG_OFFSET
);
2935 static inline void hw_r_phy_rem_cap(struct ksz_hw
*hw
, int phy
, u16
*data
)
2937 *data
= readw(hw
->io
+ phy
+ KS884X_PHY_REMOTE_CAP_OFFSET
);
2940 static inline void hw_r_phy_crossover(struct ksz_hw
*hw
, int phy
, u16
*data
)
2942 *data
= readw(hw
->io
+ phy
+ KS884X_PHY_CTRL_OFFSET
);
2945 static inline void hw_w_phy_crossover(struct ksz_hw
*hw
, int phy
, u16 data
)
2947 writew(data
, hw
->io
+ phy
+ KS884X_PHY_CTRL_OFFSET
);
2950 static inline void hw_r_phy_polarity(struct ksz_hw
*hw
, int phy
, u16
*data
)
2952 *data
= readw(hw
->io
+ phy
+ KS884X_PHY_PHY_CTRL_OFFSET
);
2955 static inline void hw_w_phy_polarity(struct ksz_hw
*hw
, int phy
, u16 data
)
2957 writew(data
, hw
->io
+ phy
+ KS884X_PHY_PHY_CTRL_OFFSET
);
2960 static inline void hw_r_phy_link_md(struct ksz_hw
*hw
, int phy
, u16
*data
)
2962 *data
= readw(hw
->io
+ phy
+ KS884X_PHY_LINK_MD_OFFSET
);
2965 static inline void hw_w_phy_link_md(struct ksz_hw
*hw
, int phy
, u16 data
)
2967 writew(data
, hw
->io
+ phy
+ KS884X_PHY_LINK_MD_OFFSET
);
2971 * hw_r_phy - read data from PHY register
2972 * @hw: The hardware instance.
2973 * @port: Port to read.
2974 * @reg: PHY register to read.
2975 * @val: Buffer to store the read data.
2977 * This routine reads data from the PHY register.
2979 static void hw_r_phy(struct ksz_hw
*hw
, int port
, u16 reg
, u16
*val
)
2983 phy
= KS884X_PHY_1_CTRL_OFFSET
+ port
* PHY_CTRL_INTERVAL
+ reg
;
2984 *val
= readw(hw
->io
+ phy
);
2988 * port_w_phy - write data to PHY register
2989 * @hw: The hardware instance.
2990 * @port: Port to write.
2991 * @reg: PHY register to write.
2992 * @val: Word data to write.
2994 * This routine writes data to the PHY register.
2996 static void hw_w_phy(struct ksz_hw
*hw
, int port
, u16 reg
, u16 val
)
3000 phy
= KS884X_PHY_1_CTRL_OFFSET
+ port
* PHY_CTRL_INTERVAL
+ reg
;
3001 writew(val
, hw
->io
+ phy
);
3005 * EEPROM access functions
3008 #define AT93C_CODE 0
3009 #define AT93C_WR_OFF 0x00
3010 #define AT93C_WR_ALL 0x10
3011 #define AT93C_ER_ALL 0x20
3012 #define AT93C_WR_ON 0x30
3014 #define AT93C_WRITE 1
3015 #define AT93C_READ 2
3016 #define AT93C_ERASE 3
3018 #define EEPROM_DELAY 4
3020 static inline void drop_gpio(struct ksz_hw
*hw
, u8 gpio
)
3024 data
= readw(hw
->io
+ KS884X_EEPROM_CTRL_OFFSET
);
3026 writew(data
, hw
->io
+ KS884X_EEPROM_CTRL_OFFSET
);
3029 static inline void raise_gpio(struct ksz_hw
*hw
, u8 gpio
)
3033 data
= readw(hw
->io
+ KS884X_EEPROM_CTRL_OFFSET
);
3035 writew(data
, hw
->io
+ KS884X_EEPROM_CTRL_OFFSET
);
3038 static inline u8
state_gpio(struct ksz_hw
*hw
, u8 gpio
)
3042 data
= readw(hw
->io
+ KS884X_EEPROM_CTRL_OFFSET
);
3043 return (u8
)(data
& gpio
);
3046 static void eeprom_clk(struct ksz_hw
*hw
)
3048 raise_gpio(hw
, EEPROM_SERIAL_CLOCK
);
3049 udelay(EEPROM_DELAY
);
3050 drop_gpio(hw
, EEPROM_SERIAL_CLOCK
);
3051 udelay(EEPROM_DELAY
);
3054 static u16
spi_r(struct ksz_hw
*hw
)
3059 for (i
= 15; i
>= 0; i
--) {
3060 raise_gpio(hw
, EEPROM_SERIAL_CLOCK
);
3061 udelay(EEPROM_DELAY
);
3063 temp
|= (state_gpio(hw
, EEPROM_DATA_IN
)) ? 1 << i
: 0;
3065 drop_gpio(hw
, EEPROM_SERIAL_CLOCK
);
3066 udelay(EEPROM_DELAY
);
3071 static void spi_w(struct ksz_hw
*hw
, u16 data
)
3075 for (i
= 15; i
>= 0; i
--) {
3076 (data
& (0x01 << i
)) ? raise_gpio(hw
, EEPROM_DATA_OUT
) :
3077 drop_gpio(hw
, EEPROM_DATA_OUT
);
3082 static void spi_reg(struct ksz_hw
*hw
, u8 data
, u8 reg
)
3086 /* Initial start bit */
3087 raise_gpio(hw
, EEPROM_DATA_OUT
);
3090 /* AT93C operation */
3091 for (i
= 1; i
>= 0; i
--) {
3092 (data
& (0x01 << i
)) ? raise_gpio(hw
, EEPROM_DATA_OUT
) :
3093 drop_gpio(hw
, EEPROM_DATA_OUT
);
3097 /* Address location */
3098 for (i
= 5; i
>= 0; i
--) {
3099 (reg
& (0x01 << i
)) ? raise_gpio(hw
, EEPROM_DATA_OUT
) :
3100 drop_gpio(hw
, EEPROM_DATA_OUT
);
3105 #define EEPROM_DATA_RESERVED 0
3106 #define EEPROM_DATA_MAC_ADDR_0 1
3107 #define EEPROM_DATA_MAC_ADDR_1 2
3108 #define EEPROM_DATA_MAC_ADDR_2 3
3109 #define EEPROM_DATA_SUBSYS_ID 4
3110 #define EEPROM_DATA_SUBSYS_VEN_ID 5
3111 #define EEPROM_DATA_PM_CAP 6
3113 /* User defined EEPROM data */
3114 #define EEPROM_DATA_OTHER_MAC_ADDR 9
3117 * eeprom_read - read from AT93C46 EEPROM
3118 * @hw: The hardware instance.
3119 * @reg: The register offset.
3121 * This function reads a word from the AT93C46 EEPROM.
3123 * Return the data value.
3125 static u16
eeprom_read(struct ksz_hw
*hw
, u8 reg
)
3129 raise_gpio(hw
, EEPROM_ACCESS_ENABLE
| EEPROM_CHIP_SELECT
);
3131 spi_reg(hw
, AT93C_READ
, reg
);
3134 drop_gpio(hw
, EEPROM_ACCESS_ENABLE
| EEPROM_CHIP_SELECT
);
3140 * eeprom_write - write to AT93C46 EEPROM
3141 * @hw: The hardware instance.
3142 * @reg: The register offset.
3143 * @data: The data value.
3145 * This procedure writes a word to the AT93C46 EEPROM.
3147 static void eeprom_write(struct ksz_hw
*hw
, u8 reg
, u16 data
)
3151 raise_gpio(hw
, EEPROM_ACCESS_ENABLE
| EEPROM_CHIP_SELECT
);
3154 spi_reg(hw
, AT93C_CODE
, AT93C_WR_ON
);
3155 drop_gpio(hw
, EEPROM_CHIP_SELECT
);
3158 /* Erase the register. */
3159 raise_gpio(hw
, EEPROM_CHIP_SELECT
);
3160 spi_reg(hw
, AT93C_ERASE
, reg
);
3161 drop_gpio(hw
, EEPROM_CHIP_SELECT
);
3164 /* Check operation complete. */
3165 raise_gpio(hw
, EEPROM_CHIP_SELECT
);
3170 } while (!state_gpio(hw
, EEPROM_DATA_IN
) && --timeout
);
3171 drop_gpio(hw
, EEPROM_CHIP_SELECT
);
3174 /* Write the register. */
3175 raise_gpio(hw
, EEPROM_CHIP_SELECT
);
3176 spi_reg(hw
, AT93C_WRITE
, reg
);
3178 drop_gpio(hw
, EEPROM_CHIP_SELECT
);
3181 /* Check operation complete. */
3182 raise_gpio(hw
, EEPROM_CHIP_SELECT
);
3187 } while (!state_gpio(hw
, EEPROM_DATA_IN
) && --timeout
);
3188 drop_gpio(hw
, EEPROM_CHIP_SELECT
);
3191 /* Disable write. */
3192 raise_gpio(hw
, EEPROM_CHIP_SELECT
);
3193 spi_reg(hw
, AT93C_CODE
, AT93C_WR_OFF
);
3195 drop_gpio(hw
, EEPROM_ACCESS_ENABLE
| EEPROM_CHIP_SELECT
);
3199 * Link detection routines
3202 static u16
advertised_flow_ctrl(struct ksz_port
*port
, u16 ctrl
)
3204 ctrl
&= ~PORT_AUTO_NEG_SYM_PAUSE
;
3205 switch (port
->flow_ctrl
) {
3207 ctrl
|= PORT_AUTO_NEG_SYM_PAUSE
;
3209 /* Not supported. */
3218 static void set_flow_ctrl(struct ksz_hw
*hw
, int rx
, int tx
)
3223 rx_cfg
= hw
->rx_cfg
;
3224 tx_cfg
= hw
->tx_cfg
;
3226 hw
->rx_cfg
|= DMA_RX_FLOW_ENABLE
;
3228 hw
->rx_cfg
&= ~DMA_RX_FLOW_ENABLE
;
3230 hw
->tx_cfg
|= DMA_TX_FLOW_ENABLE
;
3232 hw
->tx_cfg
&= ~DMA_TX_FLOW_ENABLE
;
3234 if (rx_cfg
!= hw
->rx_cfg
)
3235 writel(hw
->rx_cfg
, hw
->io
+ KS_DMA_RX_CTRL
);
3236 if (tx_cfg
!= hw
->tx_cfg
)
3237 writel(hw
->tx_cfg
, hw
->io
+ KS_DMA_TX_CTRL
);
3241 static void determine_flow_ctrl(struct ksz_hw
*hw
, struct ksz_port
*port
,
3242 u16 local
, u16 remote
)
3247 if (hw
->overrides
& PAUSE_FLOW_CTRL
)
3251 if (port
->force_link
)
3253 if (remote
& PHY_AUTO_NEG_SYM_PAUSE
) {
3254 if (local
& PHY_AUTO_NEG_SYM_PAUSE
) {
3256 } else if ((remote
& PHY_AUTO_NEG_ASYM_PAUSE
) &&
3257 (local
& PHY_AUTO_NEG_PAUSE
) ==
3258 PHY_AUTO_NEG_ASYM_PAUSE
) {
3261 } else if (remote
& PHY_AUTO_NEG_ASYM_PAUSE
) {
3262 if ((local
& PHY_AUTO_NEG_PAUSE
) == PHY_AUTO_NEG_PAUSE
)
3265 if (!hw
->ksz_switch
)
3266 set_flow_ctrl(hw
, rx
, tx
);
3269 static inline void port_cfg_change(struct ksz_hw
*hw
, struct ksz_port
*port
,
3270 struct ksz_port_info
*info
, u16 link_status
)
3272 if ((hw
->features
& HALF_DUPLEX_SIGNAL_BUG
) &&
3273 !(hw
->overrides
& PAUSE_FLOW_CTRL
)) {
3274 u32 cfg
= hw
->tx_cfg
;
3276 /* Disable flow control in the half duplex mode. */
3277 if (1 == info
->duplex
)
3278 hw
->tx_cfg
&= ~DMA_TX_FLOW_ENABLE
;
3279 if (hw
->enabled
&& cfg
!= hw
->tx_cfg
)
3280 writel(hw
->tx_cfg
, hw
->io
+ KS_DMA_TX_CTRL
);
3285 * port_get_link_speed - get current link status
3286 * @port: The port instance.
3288 * This routine reads PHY registers to determine the current link status of the
3291 static void port_get_link_speed(struct ksz_port
*port
)
3294 struct ksz_port_info
*info
;
3295 struct ksz_port_info
*linked
= NULL
;
3296 struct ksz_hw
*hw
= port
->hw
;
3305 interrupt
= hw_block_intr(hw
);
3307 for (i
= 0, p
= port
->first_port
; i
< port
->port_cnt
; i
++, p
++) {
3308 info
= &hw
->port_info
[p
];
3309 port_r16(hw
, p
, KS884X_PORT_CTRL_4_OFFSET
, &data
);
3310 port_r16(hw
, p
, KS884X_PORT_STATUS_OFFSET
, &status
);
3313 * Link status is changing all the time even when there is no
3316 remote
= status
& (PORT_AUTO_NEG_COMPLETE
|
3317 PORT_STATUS_LINK_GOOD
);
3320 /* No change to status. */
3321 if (local
== info
->advertised
&& remote
== info
->partner
)
3324 info
->advertised
= local
;
3325 info
->partner
= remote
;
3326 if (status
& PORT_STATUS_LINK_GOOD
) {
3328 /* Remember the first linked port. */
3332 info
->tx_rate
= 10 * TX_RATE_UNIT
;
3333 if (status
& PORT_STATUS_SPEED_100MBIT
)
3334 info
->tx_rate
= 100 * TX_RATE_UNIT
;
3337 if (status
& PORT_STATUS_FULL_DUPLEX
)
3340 if (media_connected
!= info
->state
) {
3341 hw_r_phy(hw
, p
, KS884X_PHY_AUTO_NEG_OFFSET
,
3343 hw_r_phy(hw
, p
, KS884X_PHY_REMOTE_CAP_OFFSET
,
3345 determine_flow_ctrl(hw
, port
, data
, status
);
3346 if (hw
->ksz_switch
) {
3347 port_cfg_back_pressure(hw
, p
,
3348 (1 == info
->duplex
));
3351 port_cfg_change(hw
, port
, info
, status
);
3353 info
->state
= media_connected
;
3355 if (media_disconnected
!= info
->state
) {
3358 /* Indicate the link just goes down. */
3359 hw
->port_mib
[p
].link_down
= 1;
3361 info
->state
= media_disconnected
;
3363 hw
->port_mib
[p
].state
= (u8
) info
->state
;
3366 if (linked
&& media_disconnected
== port
->linked
->state
)
3367 port
->linked
= linked
;
3369 hw_restore_intr(hw
, interrupt
);
3372 #define PHY_RESET_TIMEOUT 10
3375 * port_set_link_speed - set port speed
3376 * @port: The port instance.
3378 * This routine sets the link speed of the switch ports.
3380 static void port_set_link_speed(struct ksz_port
*port
)
3382 struct ksz_port_info
*info
;
3383 struct ksz_hw
*hw
= port
->hw
;
3390 for (i
= 0, p
= port
->first_port
; i
< port
->port_cnt
; i
++, p
++) {
3391 info
= &hw
->port_info
[p
];
3393 port_r16(hw
, p
, KS884X_PORT_CTRL_4_OFFSET
, &data
);
3394 port_r8(hw
, p
, KS884X_PORT_STATUS_OFFSET
, &status
);
3397 if (status
& PORT_STATUS_LINK_GOOD
)
3400 data
|= PORT_AUTO_NEG_ENABLE
;
3401 data
= advertised_flow_ctrl(port
, data
);
3403 data
|= PORT_AUTO_NEG_100BTX_FD
| PORT_AUTO_NEG_100BTX
|
3404 PORT_AUTO_NEG_10BT_FD
| PORT_AUTO_NEG_10BT
;
3406 /* Check if manual configuration is specified by the user. */
3407 if (port
->speed
|| port
->duplex
) {
3408 if (10 == port
->speed
)
3409 data
&= ~(PORT_AUTO_NEG_100BTX_FD
|
3410 PORT_AUTO_NEG_100BTX
);
3411 else if (100 == port
->speed
)
3412 data
&= ~(PORT_AUTO_NEG_10BT_FD
|
3413 PORT_AUTO_NEG_10BT
);
3414 if (1 == port
->duplex
)
3415 data
&= ~(PORT_AUTO_NEG_100BTX_FD
|
3416 PORT_AUTO_NEG_10BT_FD
);
3417 else if (2 == port
->duplex
)
3418 data
&= ~(PORT_AUTO_NEG_100BTX
|
3419 PORT_AUTO_NEG_10BT
);
3422 data
|= PORT_AUTO_NEG_RESTART
;
3423 port_w16(hw
, p
, KS884X_PORT_CTRL_4_OFFSET
, data
);
3429 * port_force_link_speed - force port speed
3430 * @port: The port instance.
3432 * This routine forces the link speed of the switch ports.
3434 static void port_force_link_speed(struct ksz_port
*port
)
3436 struct ksz_hw
*hw
= port
->hw
;
3442 for (i
= 0, p
= port
->first_port
; i
< port
->port_cnt
; i
++, p
++) {
3443 phy
= KS884X_PHY_1_CTRL_OFFSET
+ p
* PHY_CTRL_INTERVAL
;
3444 hw_r_phy_ctrl(hw
, phy
, &data
);
3446 data
&= ~PHY_AUTO_NEG_ENABLE
;
3448 if (10 == port
->speed
)
3449 data
&= ~PHY_SPEED_100MBIT
;
3450 else if (100 == port
->speed
)
3451 data
|= PHY_SPEED_100MBIT
;
3452 if (1 == port
->duplex
)
3453 data
&= ~PHY_FULL_DUPLEX
;
3454 else if (2 == port
->duplex
)
3455 data
|= PHY_FULL_DUPLEX
;
3456 hw_w_phy_ctrl(hw
, phy
, data
);
3460 static void port_set_power_saving(struct ksz_port
*port
, int enable
)
3462 struct ksz_hw
*hw
= port
->hw
;
3466 for (i
= 0, p
= port
->first_port
; i
< port
->port_cnt
; i
++, p
++)
3468 KS884X_PORT_CTRL_4_OFFSET
, PORT_POWER_DOWN
, enable
);
3472 * KSZ8841 power management functions
3476 * hw_chk_wol_pme_status - check PMEN pin
3477 * @hw: The hardware instance.
3479 * This function is used to check PMEN pin is asserted.
3481 * Return 1 if PMEN pin is asserted; otherwise, 0.
3483 static int hw_chk_wol_pme_status(struct ksz_hw
*hw
)
3485 struct dev_info
*hw_priv
= container_of(hw
, struct dev_info
, hw
);
3486 struct pci_dev
*pdev
= hw_priv
->pdev
;
3491 pci_read_config_word(pdev
, pdev
->pm_cap
+ PCI_PM_CTRL
, &data
);
3492 return (data
& PCI_PM_CTRL_PME_STATUS
) == PCI_PM_CTRL_PME_STATUS
;
3496 * hw_clr_wol_pme_status - clear PMEN pin
3497 * @hw: The hardware instance.
3499 * This routine is used to clear PME_Status to deassert PMEN pin.
3501 static void hw_clr_wol_pme_status(struct ksz_hw
*hw
)
3503 struct dev_info
*hw_priv
= container_of(hw
, struct dev_info
, hw
);
3504 struct pci_dev
*pdev
= hw_priv
->pdev
;
3510 /* Clear PME_Status to deassert PMEN pin. */
3511 pci_read_config_word(pdev
, pdev
->pm_cap
+ PCI_PM_CTRL
, &data
);
3512 data
|= PCI_PM_CTRL_PME_STATUS
;
3513 pci_write_config_word(pdev
, pdev
->pm_cap
+ PCI_PM_CTRL
, data
);
3517 * hw_cfg_wol_pme - enable or disable Wake-on-LAN
3518 * @hw: The hardware instance.
3519 * @set: The flag indicating whether to enable or disable.
3521 * This routine is used to enable or disable Wake-on-LAN.
3523 static void hw_cfg_wol_pme(struct ksz_hw
*hw
, int set
)
3525 struct dev_info
*hw_priv
= container_of(hw
, struct dev_info
, hw
);
3526 struct pci_dev
*pdev
= hw_priv
->pdev
;
3531 pci_read_config_word(pdev
, pdev
->pm_cap
+ PCI_PM_CTRL
, &data
);
3532 data
&= ~PCI_PM_CTRL_STATE_MASK
;
3534 data
|= PCI_PM_CTRL_PME_ENABLE
| PCI_D3hot
;
3536 data
&= ~PCI_PM_CTRL_PME_ENABLE
;
3537 pci_write_config_word(pdev
, pdev
->pm_cap
+ PCI_PM_CTRL
, data
);
3541 * hw_cfg_wol - configure Wake-on-LAN features
3542 * @hw: The hardware instance.
3543 * @frame: The pattern frame bit.
3544 * @set: The flag indicating whether to enable or disable.
3546 * This routine is used to enable or disable certain Wake-on-LAN features.
3548 static void hw_cfg_wol(struct ksz_hw
*hw
, u16 frame
, int set
)
3552 data
= readw(hw
->io
+ KS8841_WOL_CTRL_OFFSET
);
3557 writew(data
, hw
->io
+ KS8841_WOL_CTRL_OFFSET
);
3561 * hw_set_wol_frame - program Wake-on-LAN pattern
3562 * @hw: The hardware instance.
3563 * @i: The frame index.
3564 * @mask_size: The size of the mask.
3565 * @mask: Mask to ignore certain bytes in the pattern.
3566 * @frame_size: The size of the frame.
3567 * @pattern: The frame data.
3569 * This routine is used to program Wake-on-LAN pattern.
3571 static void hw_set_wol_frame(struct ksz_hw
*hw
, int i
, uint mask_size
,
3572 const u8
*mask
, uint frame_size
, const u8
*pattern
)
3582 if (frame_size
> mask_size
* 8)
3583 frame_size
= mask_size
* 8;
3584 if (frame_size
> 64)
3588 writel(0, hw
->io
+ KS8841_WOL_FRAME_BYTE0_OFFSET
+ i
);
3589 writel(0, hw
->io
+ KS8841_WOL_FRAME_BYTE2_OFFSET
+ i
);
3591 bits
= len
= from
= to
= 0;
3595 data
[to
++] = pattern
[from
];
3601 writeb(val
, hw
->io
+ KS8841_WOL_FRAME_BYTE0_OFFSET
+ i
3609 } while (from
< (int) frame_size
);
3611 bits
= mask
[len
- 1];
3614 writeb(bits
, hw
->io
+ KS8841_WOL_FRAME_BYTE0_OFFSET
+ i
+ len
-
3617 crc
= ether_crc(to
, data
);
3618 writel(crc
, hw
->io
+ KS8841_WOL_FRAME_CRC_OFFSET
+ i
);
3622 * hw_add_wol_arp - add ARP pattern
3623 * @hw: The hardware instance.
3624 * @ip_addr: The IPv4 address assigned to the device.
3626 * This routine is used to add ARP pattern for waking up the host.
3628 static void hw_add_wol_arp(struct ksz_hw
*hw
, const u8
*ip_addr
)
3630 static const u8 mask
[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 };
3632 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
3633 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3635 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01,
3636 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3637 0x00, 0x00, 0x00, 0x00,
3638 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3639 0x00, 0x00, 0x00, 0x00 };
3641 memcpy(&pattern
[38], ip_addr
, 4);
3642 hw_set_wol_frame(hw
, 3, 6, mask
, 42, pattern
);
3646 * hw_add_wol_bcast - add broadcast pattern
3647 * @hw: The hardware instance.
3649 * This routine is used to add broadcast pattern for waking up the host.
3651 static void hw_add_wol_bcast(struct ksz_hw
*hw
)
3653 static const u8 mask
[] = { 0x3F };
3654 static const u8 pattern
[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3656 hw_set_wol_frame(hw
, 2, 1, mask
, ETH_ALEN
, pattern
);
3660 * hw_add_wol_mcast - add multicast pattern
3661 * @hw: The hardware instance.
3663 * This routine is used to add multicast pattern for waking up the host.
3665 * It is assumed the multicast packet is the ICMPv6 neighbor solicitation used
3666 * by IPv6 ping command. Note that multicast packets are filtred through the
3667 * multicast hash table, so not all multicast packets can wake up the host.
3669 static void hw_add_wol_mcast(struct ksz_hw
*hw
)
3671 static const u8 mask
[] = { 0x3F };
3672 u8 pattern
[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 };
3674 memcpy(&pattern
[3], &hw
->override_addr
[3], 3);
3675 hw_set_wol_frame(hw
, 1, 1, mask
, 6, pattern
);
3679 * hw_add_wol_ucast - add unicast pattern
3680 * @hw: The hardware instance.
3682 * This routine is used to add unicast pattern to wakeup the host.
3684 * It is assumed the unicast packet is directed to the device, as the hardware
3685 * can only receive them in normal case.
3687 static void hw_add_wol_ucast(struct ksz_hw
*hw
)
3689 static const u8 mask
[] = { 0x3F };
3691 hw_set_wol_frame(hw
, 0, 1, mask
, ETH_ALEN
, hw
->override_addr
);
3695 * hw_enable_wol - enable Wake-on-LAN
3696 * @hw: The hardware instance.
3697 * @wol_enable: The Wake-on-LAN settings.
3698 * @net_addr: The IPv4 address assigned to the device.
3700 * This routine is used to enable Wake-on-LAN depending on driver settings.
3702 static void hw_enable_wol(struct ksz_hw
*hw
, u32 wol_enable
, const u8
*net_addr
)
3704 hw_cfg_wol(hw
, KS8841_WOL_MAGIC_ENABLE
, (wol_enable
& WAKE_MAGIC
));
3705 hw_cfg_wol(hw
, KS8841_WOL_FRAME0_ENABLE
, (wol_enable
& WAKE_UCAST
));
3706 hw_add_wol_ucast(hw
);
3707 hw_cfg_wol(hw
, KS8841_WOL_FRAME1_ENABLE
, (wol_enable
& WAKE_MCAST
));
3708 hw_add_wol_mcast(hw
);
3709 hw_cfg_wol(hw
, KS8841_WOL_FRAME2_ENABLE
, (wol_enable
& WAKE_BCAST
));
3710 hw_cfg_wol(hw
, KS8841_WOL_FRAME3_ENABLE
, (wol_enable
& WAKE_ARP
));
3711 hw_add_wol_arp(hw
, net_addr
);
3715 * hw_init - check driver is correct for the hardware
3716 * @hw: The hardware instance.
3718 * This function checks the hardware is correct for this driver and sets the
3719 * hardware up for proper initialization.
3721 * Return number of ports or 0 if not right.
3723 static int hw_init(struct ksz_hw
*hw
)
3729 /* Set bus speed to 125MHz. */
3730 writew(BUS_SPEED_125_MHZ
, hw
->io
+ KS884X_BUS_CTRL_OFFSET
);
3732 /* Check KSZ884x chip ID. */
3733 data
= readw(hw
->io
+ KS884X_CHIP_ID_OFFSET
);
3735 revision
= (data
& KS884X_REVISION_MASK
) >> KS884X_REVISION_SHIFT
;
3736 data
&= KS884X_CHIP_ID_MASK_41
;
3737 if (REG_CHIP_ID_41
== data
)
3739 else if (REG_CHIP_ID_42
== data
)
3744 /* Setup hardware features or bug workarounds. */
3745 if (revision
<= 1) {
3746 hw
->features
|= SMALL_PACKET_TX_BUG
;
3748 hw
->features
|= HALF_DUPLEX_SIGNAL_BUG
;
3754 * hw_reset - reset the hardware
3755 * @hw: The hardware instance.
3757 * This routine resets the hardware.
3759 static void hw_reset(struct ksz_hw
*hw
)
3761 writew(GLOBAL_SOFTWARE_RESET
, hw
->io
+ KS884X_GLOBAL_CTRL_OFFSET
);
3763 /* Wait for device to reset. */
3766 /* Write 0 to clear device reset. */
3767 writew(0, hw
->io
+ KS884X_GLOBAL_CTRL_OFFSET
);
3771 * hw_setup - setup the hardware
3772 * @hw: The hardware instance.
3774 * This routine setup the hardware for proper operation.
3776 static void hw_setup(struct ksz_hw
*hw
)
3781 /* Change default LED mode. */
3782 data
= readw(hw
->io
+ KS8842_SWITCH_CTRL_5_OFFSET
);
3784 data
|= SET_DEFAULT_LED
;
3785 writew(data
, hw
->io
+ KS8842_SWITCH_CTRL_5_OFFSET
);
3788 /* Setup transmit control. */
3789 hw
->tx_cfg
= (DMA_TX_PAD_ENABLE
| DMA_TX_CRC_ENABLE
|
3790 (DMA_BURST_DEFAULT
<< DMA_BURST_SHIFT
) | DMA_TX_ENABLE
);
3792 /* Setup receive control. */
3793 hw
->rx_cfg
= (DMA_RX_BROADCAST
| DMA_RX_UNICAST
|
3794 (DMA_BURST_DEFAULT
<< DMA_BURST_SHIFT
) | DMA_RX_ENABLE
);
3795 hw
->rx_cfg
|= KS884X_DMA_RX_MULTICAST
;
3797 /* Hardware cannot handle UDP packet in IP fragments. */
3798 hw
->rx_cfg
|= (DMA_RX_CSUM_TCP
| DMA_RX_CSUM_IP
);
3801 hw
->rx_cfg
|= DMA_RX_ALL_MULTICAST
;
3802 if (hw
->promiscuous
)
3803 hw
->rx_cfg
|= DMA_RX_PROMISCUOUS
;
3807 * hw_setup_intr - setup interrupt mask
3808 * @hw: The hardware instance.
3810 * This routine setup the interrupt mask for proper operation.
3812 static void hw_setup_intr(struct ksz_hw
*hw
)
3814 hw
->intr_mask
= KS884X_INT_MASK
| KS884X_INT_RX_OVERRUN
;
3817 static void ksz_check_desc_num(struct ksz_desc_info
*info
)
3819 #define MIN_DESC_SHIFT 2
3821 int alloc
= info
->alloc
;
3825 while (!(alloc
& 1)) {
3829 if (alloc
!= 1 || shift
< MIN_DESC_SHIFT
) {
3830 pr_alert("Hardware descriptor numbers not right!\n");
3835 if (shift
< MIN_DESC_SHIFT
)
3836 shift
= MIN_DESC_SHIFT
;
3838 info
->alloc
= alloc
;
3840 info
->mask
= info
->alloc
- 1;
3843 static void hw_init_desc(struct ksz_desc_info
*desc_info
, int transmit
)
3846 u32 phys
= desc_info
->ring_phys
;
3847 struct ksz_hw_desc
*desc
= desc_info
->ring_virt
;
3848 struct ksz_desc
*cur
= desc_info
->ring
;
3849 struct ksz_desc
*previous
= NULL
;
3851 for (i
= 0; i
< desc_info
->alloc
; i
++) {
3853 phys
+= desc_info
->size
;
3855 previous
->phw
->next
= cpu_to_le32(phys
);
3857 previous
->phw
->next
= cpu_to_le32(desc_info
->ring_phys
);
3858 previous
->sw
.buf
.rx
.end_of_ring
= 1;
3859 previous
->phw
->buf
.data
= cpu_to_le32(previous
->sw
.buf
.data
);
3861 desc_info
->avail
= desc_info
->alloc
;
3862 desc_info
->last
= desc_info
->next
= 0;
3864 desc_info
->cur
= desc_info
->ring
;
3868 * hw_set_desc_base - set descriptor base addresses
3869 * @hw: The hardware instance.
3870 * @tx_addr: The transmit descriptor base.
3871 * @rx_addr: The receive descriptor base.
3873 * This routine programs the descriptor base addresses after reset.
3875 static void hw_set_desc_base(struct ksz_hw
*hw
, u32 tx_addr
, u32 rx_addr
)
3877 /* Set base address of Tx/Rx descriptors. */
3878 writel(tx_addr
, hw
->io
+ KS_DMA_TX_ADDR
);
3879 writel(rx_addr
, hw
->io
+ KS_DMA_RX_ADDR
);
3882 static void hw_reset_pkts(struct ksz_desc_info
*info
)
3884 info
->cur
= info
->ring
;
3885 info
->avail
= info
->alloc
;
3886 info
->last
= info
->next
= 0;
3889 static inline void hw_resume_rx(struct ksz_hw
*hw
)
3891 writel(DMA_START
, hw
->io
+ KS_DMA_RX_START
);
3895 * hw_start_rx - start receiving
3896 * @hw: The hardware instance.
3898 * This routine starts the receive function of the hardware.
3900 static void hw_start_rx(struct ksz_hw
*hw
)
3902 writel(hw
->rx_cfg
, hw
->io
+ KS_DMA_RX_CTRL
);
3904 /* Notify when the receive stops. */
3905 hw
->intr_mask
|= KS884X_INT_RX_STOPPED
;
3907 writel(DMA_START
, hw
->io
+ KS_DMA_RX_START
);
3908 hw_ack_intr(hw
, KS884X_INT_RX_STOPPED
);
3911 /* Variable overflows. */
3912 if (0 == hw
->rx_stop
)
3917 * hw_stop_rx - stop receiving
3918 * @hw: The hardware instance.
3920 * This routine stops the receive function of the hardware.
3922 static void hw_stop_rx(struct ksz_hw
*hw
)
3925 hw_turn_off_intr(hw
, KS884X_INT_RX_STOPPED
);
3926 writel((hw
->rx_cfg
& ~DMA_RX_ENABLE
), hw
->io
+ KS_DMA_RX_CTRL
);
3930 * hw_start_tx - start transmitting
3931 * @hw: The hardware instance.
3933 * This routine starts the transmit function of the hardware.
3935 static void hw_start_tx(struct ksz_hw
*hw
)
3937 writel(hw
->tx_cfg
, hw
->io
+ KS_DMA_TX_CTRL
);
3941 * hw_stop_tx - stop transmitting
3942 * @hw: The hardware instance.
3944 * This routine stops the transmit function of the hardware.
3946 static void hw_stop_tx(struct ksz_hw
*hw
)
3948 writel((hw
->tx_cfg
& ~DMA_TX_ENABLE
), hw
->io
+ KS_DMA_TX_CTRL
);
3952 * hw_disable - disable hardware
3953 * @hw: The hardware instance.
3955 * This routine disables the hardware.
3957 static void hw_disable(struct ksz_hw
*hw
)
3965 * hw_enable - enable hardware
3966 * @hw: The hardware instance.
3968 * This routine enables the hardware.
3970 static void hw_enable(struct ksz_hw
*hw
)
3978 * hw_alloc_pkt - allocate enough descriptors for transmission
3979 * @hw: The hardware instance.
3980 * @length: The length of the packet.
3981 * @physical: Number of descriptors required.
3983 * This function allocates descriptors for transmission.
3985 * Return 0 if not successful; 1 for buffer copy; or number of descriptors.
3987 static int hw_alloc_pkt(struct ksz_hw
*hw
, int length
, int physical
)
3989 /* Always leave one descriptor free. */
3990 if (hw
->tx_desc_info
.avail
<= 1)
3993 /* Allocate a descriptor for transmission and mark it current. */
3994 get_tx_pkt(&hw
->tx_desc_info
, &hw
->tx_desc_info
.cur
);
3995 hw
->tx_desc_info
.cur
->sw
.buf
.tx
.first_seg
= 1;
3997 /* Keep track of number of transmit descriptors used so far. */
3999 hw
->tx_size
+= length
;
4001 /* Cannot hold on too much data. */
4002 if (hw
->tx_size
>= MAX_TX_HELD_SIZE
)
4003 hw
->tx_int_cnt
= hw
->tx_int_mask
+ 1;
4005 if (physical
> hw
->tx_desc_info
.avail
)
4008 return hw
->tx_desc_info
.avail
;
4012 * hw_send_pkt - mark packet for transmission
4013 * @hw: The hardware instance.
4015 * This routine marks the packet for transmission in PCI version.
4017 static void hw_send_pkt(struct ksz_hw
*hw
)
4019 struct ksz_desc
*cur
= hw
->tx_desc_info
.cur
;
4021 cur
->sw
.buf
.tx
.last_seg
= 1;
4023 /* Interrupt only after specified number of descriptors used. */
4024 if (hw
->tx_int_cnt
> hw
->tx_int_mask
) {
4025 cur
->sw
.buf
.tx
.intr
= 1;
4030 /* KSZ8842 supports port directed transmission. */
4031 cur
->sw
.buf
.tx
.dest_port
= hw
->dst_ports
;
4035 writel(0, hw
->io
+ KS_DMA_TX_START
);
4038 static int empty_addr(u8
*addr
)
4040 u32
*addr1
= (u32
*) addr
;
4041 u16
*addr2
= (u16
*) &addr
[4];
4043 return 0 == *addr1
&& 0 == *addr2
;
4047 * hw_set_addr - set MAC address
4048 * @hw: The hardware instance.
4050 * This routine programs the MAC address of the hardware when the address is
4053 static void hw_set_addr(struct ksz_hw
*hw
)
4057 for (i
= 0; i
< ETH_ALEN
; i
++)
4058 writeb(hw
->override_addr
[MAC_ADDR_ORDER(i
)],
4059 hw
->io
+ KS884X_ADDR_0_OFFSET
+ i
);
4061 sw_set_addr(hw
, hw
->override_addr
);
4065 * hw_read_addr - read MAC address
4066 * @hw: The hardware instance.
4068 * This routine retrieves the MAC address of the hardware.
4070 static void hw_read_addr(struct ksz_hw
*hw
)
4074 for (i
= 0; i
< ETH_ALEN
; i
++)
4075 hw
->perm_addr
[MAC_ADDR_ORDER(i
)] = readb(hw
->io
+
4076 KS884X_ADDR_0_OFFSET
+ i
);
4078 if (!hw
->mac_override
) {
4079 memcpy(hw
->override_addr
, hw
->perm_addr
, ETH_ALEN
);
4080 if (empty_addr(hw
->override_addr
)) {
4081 memcpy(hw
->perm_addr
, DEFAULT_MAC_ADDRESS
, ETH_ALEN
);
4082 memcpy(hw
->override_addr
, DEFAULT_MAC_ADDRESS
,
4084 hw
->override_addr
[5] += hw
->id
;
4090 static void hw_ena_add_addr(struct ksz_hw
*hw
, int index
, u8
*mac_addr
)
4097 for (i
= 0; i
< 2; i
++) {
4099 mac_addr_hi
|= mac_addr
[i
];
4101 mac_addr_hi
|= ADD_ADDR_ENABLE
;
4103 for (i
= 2; i
< 6; i
++) {
4105 mac_addr_lo
|= mac_addr
[i
];
4107 index
*= ADD_ADDR_INCR
;
4109 writel(mac_addr_lo
, hw
->io
+ index
+ KS_ADD_ADDR_0_LO
);
4110 writel(mac_addr_hi
, hw
->io
+ index
+ KS_ADD_ADDR_0_HI
);
4113 static void hw_set_add_addr(struct ksz_hw
*hw
)
4117 for (i
= 0; i
< ADDITIONAL_ENTRIES
; i
++) {
4118 if (empty_addr(hw
->address
[i
]))
4119 writel(0, hw
->io
+ ADD_ADDR_INCR
* i
+
4122 hw_ena_add_addr(hw
, i
, hw
->address
[i
]);
4126 static int hw_add_addr(struct ksz_hw
*hw
, u8
*mac_addr
)
4129 int j
= ADDITIONAL_ENTRIES
;
4131 if (ether_addr_equal(hw
->override_addr
, mac_addr
))
4133 for (i
= 0; i
< hw
->addr_list_size
; i
++) {
4134 if (ether_addr_equal(hw
->address
[i
], mac_addr
))
4136 if (ADDITIONAL_ENTRIES
== j
&& empty_addr(hw
->address
[i
]))
4139 if (j
< ADDITIONAL_ENTRIES
) {
4140 memcpy(hw
->address
[j
], mac_addr
, ETH_ALEN
);
4141 hw_ena_add_addr(hw
, j
, hw
->address
[j
]);
4147 static int hw_del_addr(struct ksz_hw
*hw
, u8
*mac_addr
)
4151 for (i
= 0; i
< hw
->addr_list_size
; i
++) {
4152 if (ether_addr_equal(hw
->address
[i
], mac_addr
)) {
4153 memset(hw
->address
[i
], 0, ETH_ALEN
);
4154 writel(0, hw
->io
+ ADD_ADDR_INCR
* i
+
4163 * hw_clr_multicast - clear multicast addresses
4164 * @hw: The hardware instance.
4166 * This routine removes all multicast addresses set in the hardware.
4168 static void hw_clr_multicast(struct ksz_hw
*hw
)
4172 for (i
= 0; i
< HW_MULTICAST_SIZE
; i
++) {
4173 hw
->multi_bits
[i
] = 0;
4175 writeb(0, hw
->io
+ KS884X_MULTICAST_0_OFFSET
+ i
);
4180 * hw_set_grp_addr - set multicast addresses
4181 * @hw: The hardware instance.
4183 * This routine programs multicast addresses for the hardware to accept those
4186 static void hw_set_grp_addr(struct ksz_hw
*hw
)
4193 memset(hw
->multi_bits
, 0, sizeof(u8
) * HW_MULTICAST_SIZE
);
4195 for (i
= 0; i
< hw
->multi_list_size
; i
++) {
4196 position
= (ether_crc(6, hw
->multi_list
[i
]) >> 26) & 0x3f;
4197 index
= position
>> 3;
4198 value
= 1 << (position
& 7);
4199 hw
->multi_bits
[index
] |= (u8
) value
;
4202 for (i
= 0; i
< HW_MULTICAST_SIZE
; i
++)
4203 writeb(hw
->multi_bits
[i
], hw
->io
+ KS884X_MULTICAST_0_OFFSET
+
4208 * hw_set_multicast - enable or disable all multicast receiving
4209 * @hw: The hardware instance.
4210 * @multicast: To turn on or off the all multicast feature.
4212 * This routine enables/disables the hardware to accept all multicast packets.
4214 static void hw_set_multicast(struct ksz_hw
*hw
, u8 multicast
)
4216 /* Stop receiving for reconfiguration. */
4220 hw
->rx_cfg
|= DMA_RX_ALL_MULTICAST
;
4222 hw
->rx_cfg
&= ~DMA_RX_ALL_MULTICAST
;
4229 * hw_set_promiscuous - enable or disable promiscuous receiving
4230 * @hw: The hardware instance.
4231 * @prom: To turn on or off the promiscuous feature.
4233 * This routine enables/disables the hardware to accept all packets.
4235 static void hw_set_promiscuous(struct ksz_hw
*hw
, u8 prom
)
4237 /* Stop receiving for reconfiguration. */
4241 hw
->rx_cfg
|= DMA_RX_PROMISCUOUS
;
4243 hw
->rx_cfg
&= ~DMA_RX_PROMISCUOUS
;
4250 * sw_enable - enable the switch
4251 * @hw: The hardware instance.
4252 * @enable: The flag to enable or disable the switch
4254 * This routine is used to enable/disable the switch in KSZ8842.
4256 static void sw_enable(struct ksz_hw
*hw
, int enable
)
4260 for (port
= 0; port
< SWITCH_PORT_NUM
; port
++) {
4261 if (hw
->dev_count
> 1) {
4262 /* Set port-base vlan membership with host port. */
4263 sw_cfg_port_base_vlan(hw
, port
,
4264 HOST_MASK
| (1 << port
));
4265 port_set_stp_state(hw
, port
, STP_STATE_DISABLED
);
4267 sw_cfg_port_base_vlan(hw
, port
, PORT_MASK
);
4268 port_set_stp_state(hw
, port
, STP_STATE_FORWARDING
);
4271 if (hw
->dev_count
> 1)
4272 port_set_stp_state(hw
, SWITCH_PORT_NUM
, STP_STATE_SIMPLE
);
4274 port_set_stp_state(hw
, SWITCH_PORT_NUM
, STP_STATE_FORWARDING
);
4277 enable
= KS8842_START
;
4278 writew(enable
, hw
->io
+ KS884X_CHIP_ID_OFFSET
);
4282 * sw_setup - setup the switch
4283 * @hw: The hardware instance.
4285 * This routine setup the hardware switch engine for default operation.
4287 static void sw_setup(struct ksz_hw
*hw
)
4291 sw_set_global_ctrl(hw
);
4293 /* Enable switch broadcast storm protection at 10% percent rate. */
4294 sw_init_broad_storm(hw
);
4295 hw_cfg_broad_storm(hw
, BROADCAST_STORM_PROTECTION_RATE
);
4296 for (port
= 0; port
< SWITCH_PORT_NUM
; port
++)
4297 sw_ena_broad_storm(hw
, port
);
4303 sw_init_prio_rate(hw
);
4307 if (hw
->features
& STP_SUPPORT
)
4309 if (!sw_chk(hw
, KS8842_SWITCH_CTRL_1_OFFSET
,
4310 SWITCH_TX_FLOW_CTRL
| SWITCH_RX_FLOW_CTRL
))
4311 hw
->overrides
|= PAUSE_FLOW_CTRL
;
4316 * ksz_start_timer - start kernel timer
4317 * @info: Kernel timer information.
4318 * @time: The time tick.
4320 * This routine starts the kernel timer after the specified time tick.
4322 static void ksz_start_timer(struct ksz_timer_info
*info
, int time
)
4325 info
->timer
.expires
= jiffies
+ time
;
4326 add_timer(&info
->timer
);
4333 * ksz_stop_timer - stop kernel timer
4334 * @info: Kernel timer information.
4336 * This routine stops the kernel timer.
4338 static void ksz_stop_timer(struct ksz_timer_info
*info
)
4342 del_timer_sync(&info
->timer
);
4346 static void ksz_init_timer(struct ksz_timer_info
*info
, int period
,
4347 void (*function
)(unsigned long), void *data
)
4350 info
->period
= period
;
4351 init_timer(&info
->timer
);
4352 info
->timer
.function
= function
;
4353 info
->timer
.data
= (unsigned long) data
;
4356 static void ksz_update_timer(struct ksz_timer_info
*info
)
4359 if (info
->max
> 0) {
4360 if (info
->cnt
< info
->max
) {
4361 info
->timer
.expires
= jiffies
+ info
->period
;
4362 add_timer(&info
->timer
);
4365 } else if (info
->max
< 0) {
4366 info
->timer
.expires
= jiffies
+ info
->period
;
4367 add_timer(&info
->timer
);
4372 * ksz_alloc_soft_desc - allocate software descriptors
4373 * @desc_info: Descriptor information structure.
4374 * @transmit: Indication that descriptors are for transmit.
4376 * This local function allocates software descriptors for manipulation in
4379 * Return 0 if successful.
4381 static int ksz_alloc_soft_desc(struct ksz_desc_info
*desc_info
, int transmit
)
4383 desc_info
->ring
= kzalloc(sizeof(struct ksz_desc
) * desc_info
->alloc
,
4385 if (!desc_info
->ring
)
4387 hw_init_desc(desc_info
, transmit
);
4392 * ksz_alloc_desc - allocate hardware descriptors
4393 * @adapter: Adapter information structure.
4395 * This local function allocates hardware descriptors for receiving and
4398 * Return 0 if successful.
4400 static int ksz_alloc_desc(struct dev_info
*adapter
)
4402 struct ksz_hw
*hw
= &adapter
->hw
;
4405 /* Allocate memory for RX & TX descriptors. */
4406 adapter
->desc_pool
.alloc_size
=
4407 hw
->rx_desc_info
.size
* hw
->rx_desc_info
.alloc
+
4408 hw
->tx_desc_info
.size
* hw
->tx_desc_info
.alloc
+
4411 adapter
->desc_pool
.alloc_virt
=
4412 pci_zalloc_consistent(adapter
->pdev
,
4413 adapter
->desc_pool
.alloc_size
,
4414 &adapter
->desc_pool
.dma_addr
);
4415 if (adapter
->desc_pool
.alloc_virt
== NULL
) {
4416 adapter
->desc_pool
.alloc_size
= 0;
4420 /* Align to the next cache line boundary. */
4421 offset
= (((ulong
) adapter
->desc_pool
.alloc_virt
% DESC_ALIGNMENT
) ?
4423 ((ulong
) adapter
->desc_pool
.alloc_virt
% DESC_ALIGNMENT
)) : 0);
4424 adapter
->desc_pool
.virt
= adapter
->desc_pool
.alloc_virt
+ offset
;
4425 adapter
->desc_pool
.phys
= adapter
->desc_pool
.dma_addr
+ offset
;
4427 /* Allocate receive/transmit descriptors. */
4428 hw
->rx_desc_info
.ring_virt
= (struct ksz_hw_desc
*)
4429 adapter
->desc_pool
.virt
;
4430 hw
->rx_desc_info
.ring_phys
= adapter
->desc_pool
.phys
;
4431 offset
= hw
->rx_desc_info
.alloc
* hw
->rx_desc_info
.size
;
4432 hw
->tx_desc_info
.ring_virt
= (struct ksz_hw_desc
*)
4433 (adapter
->desc_pool
.virt
+ offset
);
4434 hw
->tx_desc_info
.ring_phys
= adapter
->desc_pool
.phys
+ offset
;
4436 if (ksz_alloc_soft_desc(&hw
->rx_desc_info
, 0))
4438 if (ksz_alloc_soft_desc(&hw
->tx_desc_info
, 1))
4445 * free_dma_buf - release DMA buffer resources
4446 * @adapter: Adapter information structure.
4448 * This routine is just a helper function to release the DMA buffer resources.
4450 static void free_dma_buf(struct dev_info
*adapter
, struct ksz_dma_buf
*dma_buf
,
4453 pci_unmap_single(adapter
->pdev
, dma_buf
->dma
, dma_buf
->len
, direction
);
4454 dev_kfree_skb(dma_buf
->skb
);
4455 dma_buf
->skb
= NULL
;
4460 * ksz_init_rx_buffers - initialize receive descriptors
4461 * @adapter: Adapter information structure.
4463 * This routine initializes DMA buffers for receiving.
4465 static void ksz_init_rx_buffers(struct dev_info
*adapter
)
4468 struct ksz_desc
*desc
;
4469 struct ksz_dma_buf
*dma_buf
;
4470 struct ksz_hw
*hw
= &adapter
->hw
;
4471 struct ksz_desc_info
*info
= &hw
->rx_desc_info
;
4473 for (i
= 0; i
< hw
->rx_desc_info
.alloc
; i
++) {
4474 get_rx_pkt(info
, &desc
);
4476 dma_buf
= DMA_BUFFER(desc
);
4477 if (dma_buf
->skb
&& dma_buf
->len
!= adapter
->mtu
)
4478 free_dma_buf(adapter
, dma_buf
, PCI_DMA_FROMDEVICE
);
4479 dma_buf
->len
= adapter
->mtu
;
4481 dma_buf
->skb
= alloc_skb(dma_buf
->len
, GFP_ATOMIC
);
4482 if (dma_buf
->skb
&& !dma_buf
->dma
)
4483 dma_buf
->dma
= pci_map_single(
4485 skb_tail_pointer(dma_buf
->skb
),
4487 PCI_DMA_FROMDEVICE
);
4489 /* Set descriptor. */
4490 set_rx_buf(desc
, dma_buf
->dma
);
4491 set_rx_len(desc
, dma_buf
->len
);
4497 * ksz_alloc_mem - allocate memory for hardware descriptors
4498 * @adapter: Adapter information structure.
4500 * This function allocates memory for use by hardware descriptors for receiving
4503 * Return 0 if successful.
4505 static int ksz_alloc_mem(struct dev_info
*adapter
)
4507 struct ksz_hw
*hw
= &adapter
->hw
;
4509 /* Determine the number of receive and transmit descriptors. */
4510 hw
->rx_desc_info
.alloc
= NUM_OF_RX_DESC
;
4511 hw
->tx_desc_info
.alloc
= NUM_OF_TX_DESC
;
4513 /* Determine how many descriptors to skip transmit interrupt. */
4515 hw
->tx_int_mask
= NUM_OF_TX_DESC
/ 4;
4516 if (hw
->tx_int_mask
> 8)
4517 hw
->tx_int_mask
= 8;
4518 while (hw
->tx_int_mask
) {
4520 hw
->tx_int_mask
>>= 1;
4522 if (hw
->tx_int_cnt
) {
4523 hw
->tx_int_mask
= (1 << (hw
->tx_int_cnt
- 1)) - 1;
4527 /* Determine the descriptor size. */
4528 hw
->rx_desc_info
.size
=
4529 (((sizeof(struct ksz_hw_desc
) + DESC_ALIGNMENT
- 1) /
4530 DESC_ALIGNMENT
) * DESC_ALIGNMENT
);
4531 hw
->tx_desc_info
.size
=
4532 (((sizeof(struct ksz_hw_desc
) + DESC_ALIGNMENT
- 1) /
4533 DESC_ALIGNMENT
) * DESC_ALIGNMENT
);
4534 if (hw
->rx_desc_info
.size
!= sizeof(struct ksz_hw_desc
))
4535 pr_alert("Hardware descriptor size not right!\n");
4536 ksz_check_desc_num(&hw
->rx_desc_info
);
4537 ksz_check_desc_num(&hw
->tx_desc_info
);
4539 /* Allocate descriptors. */
4540 if (ksz_alloc_desc(adapter
))
4547 * ksz_free_desc - free software and hardware descriptors
4548 * @adapter: Adapter information structure.
4550 * This local routine frees the software and hardware descriptors allocated by
4553 static void ksz_free_desc(struct dev_info
*adapter
)
4555 struct ksz_hw
*hw
= &adapter
->hw
;
4557 /* Reset descriptor. */
4558 hw
->rx_desc_info
.ring_virt
= NULL
;
4559 hw
->tx_desc_info
.ring_virt
= NULL
;
4560 hw
->rx_desc_info
.ring_phys
= 0;
4561 hw
->tx_desc_info
.ring_phys
= 0;
4564 if (adapter
->desc_pool
.alloc_virt
)
4565 pci_free_consistent(
4567 adapter
->desc_pool
.alloc_size
,
4568 adapter
->desc_pool
.alloc_virt
,
4569 adapter
->desc_pool
.dma_addr
);
4571 /* Reset resource pool. */
4572 adapter
->desc_pool
.alloc_size
= 0;
4573 adapter
->desc_pool
.alloc_virt
= NULL
;
4575 kfree(hw
->rx_desc_info
.ring
);
4576 hw
->rx_desc_info
.ring
= NULL
;
4577 kfree(hw
->tx_desc_info
.ring
);
4578 hw
->tx_desc_info
.ring
= NULL
;
4582 * ksz_free_buffers - free buffers used in the descriptors
4583 * @adapter: Adapter information structure.
4584 * @desc_info: Descriptor information structure.
4586 * This local routine frees buffers used in the DMA buffers.
4588 static void ksz_free_buffers(struct dev_info
*adapter
,
4589 struct ksz_desc_info
*desc_info
, int direction
)
4592 struct ksz_dma_buf
*dma_buf
;
4593 struct ksz_desc
*desc
= desc_info
->ring
;
4595 for (i
= 0; i
< desc_info
->alloc
; i
++) {
4596 dma_buf
= DMA_BUFFER(desc
);
4598 free_dma_buf(adapter
, dma_buf
, direction
);
4604 * ksz_free_mem - free all resources used by descriptors
4605 * @adapter: Adapter information structure.
4607 * This local routine frees all the resources allocated by ksz_alloc_mem().
4609 static void ksz_free_mem(struct dev_info
*adapter
)
4611 /* Free transmit buffers. */
4612 ksz_free_buffers(adapter
, &adapter
->hw
.tx_desc_info
,
4615 /* Free receive buffers. */
4616 ksz_free_buffers(adapter
, &adapter
->hw
.rx_desc_info
,
4617 PCI_DMA_FROMDEVICE
);
4619 /* Free descriptors. */
4620 ksz_free_desc(adapter
);
4623 static void get_mib_counters(struct ksz_hw
*hw
, int first
, int cnt
,
4629 struct ksz_port_mib
*port_mib
;
4631 memset(counter
, 0, sizeof(u64
) * TOTAL_PORT_COUNTER_NUM
);
4632 for (i
= 0, port
= first
; i
< cnt
; i
++, port
++) {
4633 port_mib
= &hw
->port_mib
[port
];
4634 for (mib
= port_mib
->mib_start
; mib
< hw
->mib_cnt
; mib
++)
4635 counter
[mib
] += port_mib
->counter
[mib
];
4640 * send_packet - send packet
4641 * @skb: Socket buffer.
4642 * @dev: Network device.
4644 * This routine is used to send a packet out to the network.
4646 static void send_packet(struct sk_buff
*skb
, struct net_device
*dev
)
4648 struct ksz_desc
*desc
;
4649 struct ksz_desc
*first
;
4650 struct dev_priv
*priv
= netdev_priv(dev
);
4651 struct dev_info
*hw_priv
= priv
->adapter
;
4652 struct ksz_hw
*hw
= &hw_priv
->hw
;
4653 struct ksz_desc_info
*info
= &hw
->tx_desc_info
;
4654 struct ksz_dma_buf
*dma_buf
;
4656 int last_frag
= skb_shinfo(skb
)->nr_frags
;
4659 * KSZ8842 with multiple device interfaces needs to be told which port
4662 if (hw
->dev_count
> 1)
4663 hw
->dst_ports
= 1 << priv
->port
.first_port
;
4665 /* Hardware will pad the length to 60. */
4668 /* Remember the very first descriptor. */
4672 dma_buf
= DMA_BUFFER(desc
);
4675 skb_frag_t
*this_frag
;
4677 dma_buf
->len
= skb_headlen(skb
);
4679 dma_buf
->dma
= pci_map_single(
4680 hw_priv
->pdev
, skb
->data
, dma_buf
->len
,
4682 set_tx_buf(desc
, dma_buf
->dma
);
4683 set_tx_len(desc
, dma_buf
->len
);
4687 this_frag
= &skb_shinfo(skb
)->frags
[frag
];
4689 /* Get a new descriptor. */
4690 get_tx_pkt(info
, &desc
);
4692 /* Keep track of descriptors used so far. */
4695 dma_buf
= DMA_BUFFER(desc
);
4696 dma_buf
->len
= skb_frag_size(this_frag
);
4698 dma_buf
->dma
= pci_map_single(
4700 skb_frag_address(this_frag
),
4703 set_tx_buf(desc
, dma_buf
->dma
);
4704 set_tx_len(desc
, dma_buf
->len
);
4707 if (frag
== last_frag
)
4710 /* Do not release the last descriptor here. */
4714 /* current points to the last descriptor. */
4717 /* Release the first descriptor. */
4718 release_desc(first
);
4722 dma_buf
->dma
= pci_map_single(
4723 hw_priv
->pdev
, skb
->data
, dma_buf
->len
,
4725 set_tx_buf(desc
, dma_buf
->dma
);
4726 set_tx_len(desc
, dma_buf
->len
);
4729 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4730 (desc
)->sw
.buf
.tx
.csum_gen_tcp
= 1;
4731 (desc
)->sw
.buf
.tx
.csum_gen_udp
= 1;
4735 * The last descriptor holds the packet so that it can be returned to
4736 * network subsystem after all descriptors are transmitted.
4742 /* Update transmit statistics. */
4743 dev
->stats
.tx_packets
++;
4744 dev
->stats
.tx_bytes
+= len
;
4748 * transmit_cleanup - clean up transmit descriptors
4749 * @dev: Network device.
4751 * This routine is called to clean up the transmitted buffers.
4753 static void transmit_cleanup(struct dev_info
*hw_priv
, int normal
)
4756 union desc_stat status
;
4757 struct ksz_hw
*hw
= &hw_priv
->hw
;
4758 struct ksz_desc_info
*info
= &hw
->tx_desc_info
;
4759 struct ksz_desc
*desc
;
4760 struct ksz_dma_buf
*dma_buf
;
4761 struct net_device
*dev
= NULL
;
4763 spin_lock_irq(&hw_priv
->hwlock
);
4766 while (info
->avail
< info
->alloc
) {
4767 /* Get next descriptor which is not hardware owned. */
4768 desc
= &info
->ring
[last
];
4769 status
.data
= le32_to_cpu(desc
->phw
->ctrl
.data
);
4770 if (status
.tx
.hw_owned
) {
4774 reset_desc(desc
, status
);
4777 dma_buf
= DMA_BUFFER(desc
);
4779 hw_priv
->pdev
, dma_buf
->dma
, dma_buf
->len
,
4782 /* This descriptor contains the last buffer in the packet. */
4784 dev
= dma_buf
->skb
->dev
;
4786 /* Release the packet back to network subsystem. */
4787 dev_kfree_skb_irq(dma_buf
->skb
);
4788 dma_buf
->skb
= NULL
;
4791 /* Free the transmitted descriptor. */
4797 spin_unlock_irq(&hw_priv
->hwlock
);
4799 /* Notify the network subsystem that the packet has been sent. */
4801 dev
->trans_start
= jiffies
;
4805 * transmit_done - transmit done processing
4806 * @dev: Network device.
4808 * This routine is called when the transmit interrupt is triggered, indicating
4809 * either a packet is sent successfully or there are transmit errors.
4811 static void tx_done(struct dev_info
*hw_priv
)
4813 struct ksz_hw
*hw
= &hw_priv
->hw
;
4816 transmit_cleanup(hw_priv
, 1);
4818 for (port
= 0; port
< hw
->dev_count
; port
++) {
4819 struct net_device
*dev
= hw
->port_info
[port
].pdev
;
4821 if (netif_running(dev
) && netif_queue_stopped(dev
))
4822 netif_wake_queue(dev
);
4826 static inline void copy_old_skb(struct sk_buff
*old
, struct sk_buff
*skb
)
4828 skb
->dev
= old
->dev
;
4829 skb
->protocol
= old
->protocol
;
4830 skb
->ip_summed
= old
->ip_summed
;
4831 skb
->csum
= old
->csum
;
4832 skb_set_network_header(skb
, ETH_HLEN
);
4834 dev_consume_skb_any(old
);
4838 * netdev_tx - send out packet
4839 * @skb: Socket buffer.
4840 * @dev: Network device.
4842 * This function is used by the upper network layer to send out a packet.
4844 * Return 0 if successful; otherwise an error code indicating failure.
4846 static netdev_tx_t
netdev_tx(struct sk_buff
*skb
, struct net_device
*dev
)
4848 struct dev_priv
*priv
= netdev_priv(dev
);
4849 struct dev_info
*hw_priv
= priv
->adapter
;
4850 struct ksz_hw
*hw
= &hw_priv
->hw
;
4855 if (hw
->features
& SMALL_PACKET_TX_BUG
) {
4856 struct sk_buff
*org_skb
= skb
;
4858 if (skb
->len
<= 48) {
4859 if (skb_end_pointer(skb
) - skb
->data
>= 50) {
4860 memset(&skb
->data
[skb
->len
], 0, 50 - skb
->len
);
4863 skb
= netdev_alloc_skb(dev
, 50);
4865 return NETDEV_TX_BUSY
;
4866 memcpy(skb
->data
, org_skb
->data
, org_skb
->len
);
4867 memset(&skb
->data
[org_skb
->len
], 0,
4870 copy_old_skb(org_skb
, skb
);
4875 spin_lock_irq(&hw_priv
->hwlock
);
4877 num
= skb_shinfo(skb
)->nr_frags
+ 1;
4878 left
= hw_alloc_pkt(hw
, skb
->len
, num
);
4881 (CHECKSUM_PARTIAL
== skb
->ip_summed
&&
4882 skb
->protocol
== htons(ETH_P_IPV6
))) {
4883 struct sk_buff
*org_skb
= skb
;
4885 skb
= netdev_alloc_skb(dev
, org_skb
->len
);
4887 rc
= NETDEV_TX_BUSY
;
4890 skb_copy_and_csum_dev(org_skb
, skb
->data
);
4891 org_skb
->ip_summed
= CHECKSUM_NONE
;
4892 skb
->len
= org_skb
->len
;
4893 copy_old_skb(org_skb
, skb
);
4895 send_packet(skb
, dev
);
4897 netif_stop_queue(dev
);
4899 /* Stop the transmit queue until packet is allocated. */
4900 netif_stop_queue(dev
);
4901 rc
= NETDEV_TX_BUSY
;
4904 spin_unlock_irq(&hw_priv
->hwlock
);
4910 * netdev_tx_timeout - transmit timeout processing
4911 * @dev: Network device.
4913 * This routine is called when the transmit timer expires. That indicates the
4914 * hardware is not running correctly because transmit interrupts are not
4915 * triggered to free up resources so that the transmit routine can continue
4916 * sending out packets. The hardware is reset to correct the problem.
4918 static void netdev_tx_timeout(struct net_device
*dev
)
4920 static unsigned long last_reset
;
4922 struct dev_priv
*priv
= netdev_priv(dev
);
4923 struct dev_info
*hw_priv
= priv
->adapter
;
4924 struct ksz_hw
*hw
= &hw_priv
->hw
;
4927 if (hw
->dev_count
> 1) {
4929 * Only reset the hardware if time between calls is long
4932 if (time_before_eq(jiffies
, last_reset
+ dev
->watchdog_timeo
))
4936 last_reset
= jiffies
;
4941 transmit_cleanup(hw_priv
, 0);
4942 hw_reset_pkts(&hw
->rx_desc_info
);
4943 hw_reset_pkts(&hw
->tx_desc_info
);
4944 ksz_init_rx_buffers(hw_priv
);
4948 hw_set_desc_base(hw
,
4949 hw
->tx_desc_info
.ring_phys
,
4950 hw
->rx_desc_info
.ring_phys
);
4953 hw_set_multicast(hw
, hw
->all_multi
);
4954 else if (hw
->multi_list_size
)
4955 hw_set_grp_addr(hw
);
4957 if (hw
->dev_count
> 1) {
4958 hw_set_add_addr(hw
);
4959 for (port
= 0; port
< SWITCH_PORT_NUM
; port
++) {
4960 struct net_device
*port_dev
;
4962 port_set_stp_state(hw
, port
,
4963 STP_STATE_DISABLED
);
4965 port_dev
= hw
->port_info
[port
].pdev
;
4966 if (netif_running(port_dev
))
4967 port_set_stp_state(hw
, port
,
4976 dev
->trans_start
= jiffies
;
4977 netif_wake_queue(dev
);
4980 static inline void csum_verified(struct sk_buff
*skb
)
4982 unsigned short protocol
;
4985 protocol
= skb
->protocol
;
4986 skb_reset_network_header(skb
);
4987 iph
= (struct iphdr
*) skb_network_header(skb
);
4988 if (protocol
== htons(ETH_P_8021Q
)) {
4989 protocol
= iph
->tot_len
;
4990 skb_set_network_header(skb
, VLAN_HLEN
);
4991 iph
= (struct iphdr
*) skb_network_header(skb
);
4993 if (protocol
== htons(ETH_P_IP
)) {
4994 if (iph
->protocol
== IPPROTO_TCP
)
4995 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4999 static inline int rx_proc(struct net_device
*dev
, struct ksz_hw
* hw
,
5000 struct ksz_desc
*desc
, union desc_stat status
)
5003 struct dev_priv
*priv
= netdev_priv(dev
);
5004 struct dev_info
*hw_priv
= priv
->adapter
;
5005 struct ksz_dma_buf
*dma_buf
;
5006 struct sk_buff
*skb
;
5009 /* Received length includes 4-byte CRC. */
5010 packet_len
= status
.rx
.frame_len
- 4;
5012 dma_buf
= DMA_BUFFER(desc
);
5013 pci_dma_sync_single_for_cpu(
5014 hw_priv
->pdev
, dma_buf
->dma
, packet_len
+ 4,
5015 PCI_DMA_FROMDEVICE
);
5018 /* skb->data != skb->head */
5019 skb
= netdev_alloc_skb(dev
, packet_len
+ 2);
5021 dev
->stats
.rx_dropped
++;
5026 * Align socket buffer in 4-byte boundary for better
5029 skb_reserve(skb
, 2);
5031 memcpy(skb_put(skb
, packet_len
),
5032 dma_buf
->skb
->data
, packet_len
);
5035 skb
->protocol
= eth_type_trans(skb
, dev
);
5037 if (hw
->rx_cfg
& (DMA_RX_CSUM_UDP
| DMA_RX_CSUM_TCP
))
5040 /* Update receive statistics. */
5041 dev
->stats
.rx_packets
++;
5042 dev
->stats
.rx_bytes
+= packet_len
;
5044 /* Notify upper layer for received packet. */
5045 rx_status
= netif_rx(skb
);
5050 static int dev_rcv_packets(struct dev_info
*hw_priv
)
5053 union desc_stat status
;
5054 struct ksz_hw
*hw
= &hw_priv
->hw
;
5055 struct net_device
*dev
= hw
->port_info
[0].pdev
;
5056 struct ksz_desc_info
*info
= &hw
->rx_desc_info
;
5057 int left
= info
->alloc
;
5058 struct ksz_desc
*desc
;
5063 /* Get next descriptor which is not hardware owned. */
5064 desc
= &info
->ring
[next
];
5065 status
.data
= le32_to_cpu(desc
->phw
->ctrl
.data
);
5066 if (status
.rx
.hw_owned
)
5069 /* Status valid only when last descriptor bit is set. */
5070 if (status
.rx
.last_desc
&& status
.rx
.first_desc
) {
5071 if (rx_proc(dev
, hw
, desc
, status
))
5072 goto release_packet
;
5086 static int port_rcv_packets(struct dev_info
*hw_priv
)
5089 union desc_stat status
;
5090 struct ksz_hw
*hw
= &hw_priv
->hw
;
5091 struct net_device
*dev
= hw
->port_info
[0].pdev
;
5092 struct ksz_desc_info
*info
= &hw
->rx_desc_info
;
5093 int left
= info
->alloc
;
5094 struct ksz_desc
*desc
;
5099 /* Get next descriptor which is not hardware owned. */
5100 desc
= &info
->ring
[next
];
5101 status
.data
= le32_to_cpu(desc
->phw
->ctrl
.data
);
5102 if (status
.rx
.hw_owned
)
5105 if (hw
->dev_count
> 1) {
5106 /* Get received port number. */
5107 int p
= HW_TO_DEV_PORT(status
.rx
.src_port
);
5109 dev
= hw
->port_info
[p
].pdev
;
5110 if (!netif_running(dev
))
5111 goto release_packet
;
5114 /* Status valid only when last descriptor bit is set. */
5115 if (status
.rx
.last_desc
&& status
.rx
.first_desc
) {
5116 if (rx_proc(dev
, hw
, desc
, status
))
5117 goto release_packet
;
5131 static int dev_rcv_special(struct dev_info
*hw_priv
)
5134 union desc_stat status
;
5135 struct ksz_hw
*hw
= &hw_priv
->hw
;
5136 struct net_device
*dev
= hw
->port_info
[0].pdev
;
5137 struct ksz_desc_info
*info
= &hw
->rx_desc_info
;
5138 int left
= info
->alloc
;
5139 struct ksz_desc
*desc
;
5144 /* Get next descriptor which is not hardware owned. */
5145 desc
= &info
->ring
[next
];
5146 status
.data
= le32_to_cpu(desc
->phw
->ctrl
.data
);
5147 if (status
.rx
.hw_owned
)
5150 if (hw
->dev_count
> 1) {
5151 /* Get received port number. */
5152 int p
= HW_TO_DEV_PORT(status
.rx
.src_port
);
5154 dev
= hw
->port_info
[p
].pdev
;
5155 if (!netif_running(dev
))
5156 goto release_packet
;
5159 /* Status valid only when last descriptor bit is set. */
5160 if (status
.rx
.last_desc
&& status
.rx
.first_desc
) {
5162 * Receive without error. With receive errors
5163 * disabled, packets with receive errors will be
5164 * dropped, so no need to check the error bit.
5166 if (!status
.rx
.error
|| (status
.data
&
5167 KS_DESC_RX_ERROR_COND
) ==
5168 KS_DESC_RX_ERROR_TOO_LONG
) {
5169 if (rx_proc(dev
, hw
, desc
, status
))
5170 goto release_packet
;
5173 struct dev_priv
*priv
= netdev_priv(dev
);
5175 /* Update receive error statistics. */
5176 priv
->port
.counter
[OID_COUNTER_RCV_ERROR
]++;
5190 static void rx_proc_task(unsigned long data
)
5192 struct dev_info
*hw_priv
= (struct dev_info
*) data
;
5193 struct ksz_hw
*hw
= &hw_priv
->hw
;
5197 if (unlikely(!hw_priv
->dev_rcv(hw_priv
))) {
5199 /* In case receive process is suspended because of overrun. */
5202 /* tasklets are interruptible. */
5203 spin_lock_irq(&hw_priv
->hwlock
);
5204 hw_turn_on_intr(hw
, KS884X_INT_RX_MASK
);
5205 spin_unlock_irq(&hw_priv
->hwlock
);
5207 hw_ack_intr(hw
, KS884X_INT_RX
);
5208 tasklet_schedule(&hw_priv
->rx_tasklet
);
5212 static void tx_proc_task(unsigned long data
)
5214 struct dev_info
*hw_priv
= (struct dev_info
*) data
;
5215 struct ksz_hw
*hw
= &hw_priv
->hw
;
5217 hw_ack_intr(hw
, KS884X_INT_TX_MASK
);
5221 /* tasklets are interruptible. */
5222 spin_lock_irq(&hw_priv
->hwlock
);
5223 hw_turn_on_intr(hw
, KS884X_INT_TX
);
5224 spin_unlock_irq(&hw_priv
->hwlock
);
5227 static inline void handle_rx_stop(struct ksz_hw
*hw
)
5229 /* Receive just has been stopped. */
5230 if (0 == hw
->rx_stop
)
5231 hw
->intr_mask
&= ~KS884X_INT_RX_STOPPED
;
5232 else if (hw
->rx_stop
> 1) {
5233 if (hw
->enabled
&& (hw
->rx_cfg
& DMA_RX_ENABLE
)) {
5236 hw
->intr_mask
&= ~KS884X_INT_RX_STOPPED
;
5240 /* Receive just has been started. */
5245 * netdev_intr - interrupt handling
5246 * @irq: Interrupt number.
5247 * @dev_id: Network device.
5249 * This function is called by upper network layer to signal interrupt.
5251 * Return IRQ_HANDLED if interrupt is handled.
5253 static irqreturn_t
netdev_intr(int irq
, void *dev_id
)
5255 uint int_enable
= 0;
5256 struct net_device
*dev
= (struct net_device
*) dev_id
;
5257 struct dev_priv
*priv
= netdev_priv(dev
);
5258 struct dev_info
*hw_priv
= priv
->adapter
;
5259 struct ksz_hw
*hw
= &hw_priv
->hw
;
5261 spin_lock(&hw_priv
->hwlock
);
5263 hw_read_intr(hw
, &int_enable
);
5265 /* Not our interrupt! */
5267 spin_unlock(&hw_priv
->hwlock
);
5272 hw_ack_intr(hw
, int_enable
);
5273 int_enable
&= hw
->intr_mask
;
5275 if (unlikely(int_enable
& KS884X_INT_TX_MASK
)) {
5276 hw_dis_intr_bit(hw
, KS884X_INT_TX_MASK
);
5277 tasklet_schedule(&hw_priv
->tx_tasklet
);
5280 if (likely(int_enable
& KS884X_INT_RX
)) {
5281 hw_dis_intr_bit(hw
, KS884X_INT_RX
);
5282 tasklet_schedule(&hw_priv
->rx_tasklet
);
5285 if (unlikely(int_enable
& KS884X_INT_RX_OVERRUN
)) {
5286 dev
->stats
.rx_fifo_errors
++;
5290 if (unlikely(int_enable
& KS884X_INT_PHY
)) {
5291 struct ksz_port
*port
= &priv
->port
;
5293 hw
->features
|= LINK_INT_WORKING
;
5294 port_get_link_speed(port
);
5297 if (unlikely(int_enable
& KS884X_INT_RX_STOPPED
)) {
5302 if (unlikely(int_enable
& KS884X_INT_TX_STOPPED
)) {
5305 hw
->intr_mask
&= ~KS884X_INT_TX_STOPPED
;
5306 pr_info("Tx stopped\n");
5307 data
= readl(hw
->io
+ KS_DMA_TX_CTRL
);
5308 if (!(data
& DMA_TX_ENABLE
))
5309 pr_info("Tx disabled\n");
5316 spin_unlock(&hw_priv
->hwlock
);
5322 * Linux network device functions
5325 static unsigned long next_jiffies
;
5327 #ifdef CONFIG_NET_POLL_CONTROLLER
5328 static void netdev_netpoll(struct net_device
*dev
)
5330 struct dev_priv
*priv
= netdev_priv(dev
);
5331 struct dev_info
*hw_priv
= priv
->adapter
;
5333 hw_dis_intr(&hw_priv
->hw
);
5334 netdev_intr(dev
->irq
, dev
);
5338 static void bridge_change(struct ksz_hw
*hw
)
5342 struct ksz_switch
*sw
= hw
->ksz_switch
;
5344 /* No ports in forwarding state. */
5346 port_set_stp_state(hw
, SWITCH_PORT_NUM
, STP_STATE_SIMPLE
);
5349 for (port
= 0; port
< SWITCH_PORT_NUM
; port
++) {
5350 if (STP_STATE_FORWARDING
== sw
->port_cfg
[port
].stp_state
)
5351 member
= HOST_MASK
| sw
->member
;
5353 member
= HOST_MASK
| (1 << port
);
5354 if (member
!= sw
->port_cfg
[port
].member
)
5355 sw_cfg_port_base_vlan(hw
, port
, member
);
5360 * netdev_close - close network device
5361 * @dev: Network device.
5363 * This function process the close operation of network device. This is caused
5364 * by the user command "ifconfig ethX down."
5366 * Return 0 if successful; otherwise an error code indicating failure.
5368 static int netdev_close(struct net_device
*dev
)
5370 struct dev_priv
*priv
= netdev_priv(dev
);
5371 struct dev_info
*hw_priv
= priv
->adapter
;
5372 struct ksz_port
*port
= &priv
->port
;
5373 struct ksz_hw
*hw
= &hw_priv
->hw
;
5376 netif_stop_queue(dev
);
5378 ksz_stop_timer(&priv
->monitor_timer_info
);
5380 /* Need to shut the port manually in multiple device interfaces mode. */
5381 if (hw
->dev_count
> 1) {
5382 port_set_stp_state(hw
, port
->first_port
, STP_STATE_DISABLED
);
5384 /* Port is closed. Need to change bridge setting. */
5385 if (hw
->features
& STP_SUPPORT
) {
5386 pi
= 1 << port
->first_port
;
5387 if (hw
->ksz_switch
->member
& pi
) {
5388 hw
->ksz_switch
->member
&= ~pi
;
5393 if (port
->first_port
> 0)
5394 hw_del_addr(hw
, dev
->dev_addr
);
5395 if (!hw_priv
->wol_enable
)
5396 port_set_power_saving(port
, true);
5398 if (priv
->multicast
)
5400 if (priv
->promiscuous
)
5404 if (!(hw_priv
->opened
)) {
5405 ksz_stop_timer(&hw_priv
->mib_timer_info
);
5406 flush_work(&hw_priv
->mib_read
);
5410 hw_clr_multicast(hw
);
5412 /* Delay for receive task to stop scheduling itself. */
5415 tasklet_kill(&hw_priv
->rx_tasklet
);
5416 tasklet_kill(&hw_priv
->tx_tasklet
);
5417 free_irq(dev
->irq
, hw_priv
->dev
);
5419 transmit_cleanup(hw_priv
, 0);
5420 hw_reset_pkts(&hw
->rx_desc_info
);
5421 hw_reset_pkts(&hw
->tx_desc_info
);
5423 /* Clean out static MAC table when the switch is shutdown. */
5424 if (hw
->features
& STP_SUPPORT
)
5425 sw_clr_sta_mac_table(hw
);
5431 static void hw_cfg_huge_frame(struct dev_info
*hw_priv
, struct ksz_hw
*hw
)
5433 if (hw
->ksz_switch
) {
5436 data
= readw(hw
->io
+ KS8842_SWITCH_CTRL_2_OFFSET
);
5437 if (hw
->features
& RX_HUGE_FRAME
)
5438 data
|= SWITCH_HUGE_PACKET
;
5440 data
&= ~SWITCH_HUGE_PACKET
;
5441 writew(data
, hw
->io
+ KS8842_SWITCH_CTRL_2_OFFSET
);
5443 if (hw
->features
& RX_HUGE_FRAME
) {
5444 hw
->rx_cfg
|= DMA_RX_ERROR
;
5445 hw_priv
->dev_rcv
= dev_rcv_special
;
5447 hw
->rx_cfg
&= ~DMA_RX_ERROR
;
5448 if (hw
->dev_count
> 1)
5449 hw_priv
->dev_rcv
= port_rcv_packets
;
5451 hw_priv
->dev_rcv
= dev_rcv_packets
;
5455 static int prepare_hardware(struct net_device
*dev
)
5457 struct dev_priv
*priv
= netdev_priv(dev
);
5458 struct dev_info
*hw_priv
= priv
->adapter
;
5459 struct ksz_hw
*hw
= &hw_priv
->hw
;
5462 /* Remember the network device that requests interrupts. */
5464 rc
= request_irq(dev
->irq
, netdev_intr
, IRQF_SHARED
, dev
->name
, dev
);
5467 tasklet_init(&hw_priv
->rx_tasklet
, rx_proc_task
,
5468 (unsigned long) hw_priv
);
5469 tasklet_init(&hw_priv
->tx_tasklet
, tx_proc_task
,
5470 (unsigned long) hw_priv
);
5472 hw
->promiscuous
= 0;
5474 hw
->multi_list_size
= 0;
5478 hw_set_desc_base(hw
,
5479 hw
->tx_desc_info
.ring_phys
, hw
->rx_desc_info
.ring_phys
);
5481 hw_cfg_huge_frame(hw_priv
, hw
);
5482 ksz_init_rx_buffers(hw_priv
);
5486 static void set_media_state(struct net_device
*dev
, int media_state
)
5488 struct dev_priv
*priv
= netdev_priv(dev
);
5490 if (media_state
== priv
->media_state
)
5491 netif_carrier_on(dev
);
5493 netif_carrier_off(dev
);
5494 netif_info(priv
, link
, dev
, "link %s\n",
5495 media_state
== priv
->media_state
? "on" : "off");
5499 * netdev_open - open network device
5500 * @dev: Network device.
5502 * This function process the open operation of network device. This is caused
5503 * by the user command "ifconfig ethX up."
5505 * Return 0 if successful; otherwise an error code indicating failure.
5507 static int netdev_open(struct net_device
*dev
)
5509 struct dev_priv
*priv
= netdev_priv(dev
);
5510 struct dev_info
*hw_priv
= priv
->adapter
;
5511 struct ksz_hw
*hw
= &hw_priv
->hw
;
5512 struct ksz_port
*port
= &priv
->port
;
5517 priv
->multicast
= 0;
5518 priv
->promiscuous
= 0;
5520 /* Reset device statistics. */
5521 memset(&dev
->stats
, 0, sizeof(struct net_device_stats
));
5522 memset((void *) port
->counter
, 0,
5523 (sizeof(u64
) * OID_COUNTER_LAST
));
5525 if (!(hw_priv
->opened
)) {
5526 rc
= prepare_hardware(dev
);
5529 for (i
= 0; i
< hw
->mib_port_cnt
; i
++) {
5530 if (next_jiffies
< jiffies
)
5531 next_jiffies
= jiffies
+ HZ
* 2;
5533 next_jiffies
+= HZ
* 1;
5534 hw_priv
->counter
[i
].time
= next_jiffies
;
5535 hw
->port_mib
[i
].state
= media_disconnected
;
5536 port_init_cnt(hw
, i
);
5539 hw
->port_mib
[HOST_PORT
].state
= media_connected
;
5541 hw_add_wol_bcast(hw
);
5542 hw_cfg_wol_pme(hw
, 0);
5543 hw_clr_wol_pme_status(&hw_priv
->hw
);
5546 port_set_power_saving(port
, false);
5548 for (i
= 0, p
= port
->first_port
; i
< port
->port_cnt
; i
++, p
++) {
5550 * Initialize to invalid value so that link detection
5553 hw
->port_info
[p
].partner
= 0xFF;
5554 hw
->port_info
[p
].state
= media_disconnected
;
5557 /* Need to open the port in multiple device interfaces mode. */
5558 if (hw
->dev_count
> 1) {
5559 port_set_stp_state(hw
, port
->first_port
, STP_STATE_SIMPLE
);
5560 if (port
->first_port
> 0)
5561 hw_add_addr(hw
, dev
->dev_addr
);
5564 port_get_link_speed(port
);
5565 if (port
->force_link
)
5566 port_force_link_speed(port
);
5568 port_set_link_speed(port
);
5570 if (!(hw_priv
->opened
)) {
5575 if (hw
->mib_port_cnt
)
5576 ksz_start_timer(&hw_priv
->mib_timer_info
,
5577 hw_priv
->mib_timer_info
.period
);
5582 ksz_start_timer(&priv
->monitor_timer_info
,
5583 priv
->monitor_timer_info
.period
);
5585 priv
->media_state
= port
->linked
->state
;
5587 set_media_state(dev
, media_connected
);
5588 netif_start_queue(dev
);
5593 /* RX errors = rx_errors */
5594 /* RX dropped = rx_dropped */
5595 /* RX overruns = rx_fifo_errors */
5596 /* RX frame = rx_crc_errors + rx_frame_errors + rx_length_errors */
5597 /* TX errors = tx_errors */
5598 /* TX dropped = tx_dropped */
5599 /* TX overruns = tx_fifo_errors */
5600 /* TX carrier = tx_aborted_errors + tx_carrier_errors + tx_window_errors */
5601 /* collisions = collisions */
5604 * netdev_query_statistics - query network device statistics
5605 * @dev: Network device.
5607 * This function returns the statistics of the network device. The device
5608 * needs not be opened.
5610 * Return network device statistics.
5612 static struct net_device_stats
*netdev_query_statistics(struct net_device
*dev
)
5614 struct dev_priv
*priv
= netdev_priv(dev
);
5615 struct ksz_port
*port
= &priv
->port
;
5616 struct ksz_hw
*hw
= &priv
->adapter
->hw
;
5617 struct ksz_port_mib
*mib
;
5621 dev
->stats
.rx_errors
= port
->counter
[OID_COUNTER_RCV_ERROR
];
5622 dev
->stats
.tx_errors
= port
->counter
[OID_COUNTER_XMIT_ERROR
];
5624 /* Reset to zero to add count later. */
5625 dev
->stats
.multicast
= 0;
5626 dev
->stats
.collisions
= 0;
5627 dev
->stats
.rx_length_errors
= 0;
5628 dev
->stats
.rx_crc_errors
= 0;
5629 dev
->stats
.rx_frame_errors
= 0;
5630 dev
->stats
.tx_window_errors
= 0;
5632 for (i
= 0, p
= port
->first_port
; i
< port
->mib_port_cnt
; i
++, p
++) {
5633 mib
= &hw
->port_mib
[p
];
5635 dev
->stats
.multicast
+= (unsigned long)
5636 mib
->counter
[MIB_COUNTER_RX_MULTICAST
];
5638 dev
->stats
.collisions
+= (unsigned long)
5639 mib
->counter
[MIB_COUNTER_TX_TOTAL_COLLISION
];
5641 dev
->stats
.rx_length_errors
+= (unsigned long)(
5642 mib
->counter
[MIB_COUNTER_RX_UNDERSIZE
] +
5643 mib
->counter
[MIB_COUNTER_RX_FRAGMENT
] +
5644 mib
->counter
[MIB_COUNTER_RX_OVERSIZE
] +
5645 mib
->counter
[MIB_COUNTER_RX_JABBER
]);
5646 dev
->stats
.rx_crc_errors
+= (unsigned long)
5647 mib
->counter
[MIB_COUNTER_RX_CRC_ERR
];
5648 dev
->stats
.rx_frame_errors
+= (unsigned long)(
5649 mib
->counter
[MIB_COUNTER_RX_ALIGNMENT_ERR
] +
5650 mib
->counter
[MIB_COUNTER_RX_SYMBOL_ERR
]);
5652 dev
->stats
.tx_window_errors
+= (unsigned long)
5653 mib
->counter
[MIB_COUNTER_TX_LATE_COLLISION
];
5660 * netdev_set_mac_address - set network device MAC address
5661 * @dev: Network device.
5662 * @addr: Buffer of MAC address.
5664 * This function is used to set the MAC address of the network device.
5666 * Return 0 to indicate success.
5668 static int netdev_set_mac_address(struct net_device
*dev
, void *addr
)
5670 struct dev_priv
*priv
= netdev_priv(dev
);
5671 struct dev_info
*hw_priv
= priv
->adapter
;
5672 struct ksz_hw
*hw
= &hw_priv
->hw
;
5673 struct sockaddr
*mac
= addr
;
5676 if (priv
->port
.first_port
> 0)
5677 hw_del_addr(hw
, dev
->dev_addr
);
5679 hw
->mac_override
= 1;
5680 memcpy(hw
->override_addr
, mac
->sa_data
, ETH_ALEN
);
5683 memcpy(dev
->dev_addr
, mac
->sa_data
, ETH_ALEN
);
5685 interrupt
= hw_block_intr(hw
);
5687 if (priv
->port
.first_port
> 0)
5688 hw_add_addr(hw
, dev
->dev_addr
);
5691 hw_restore_intr(hw
, interrupt
);
5696 static void dev_set_promiscuous(struct net_device
*dev
, struct dev_priv
*priv
,
5697 struct ksz_hw
*hw
, int promiscuous
)
5699 if (promiscuous
!= priv
->promiscuous
) {
5700 u8 prev_state
= hw
->promiscuous
;
5706 priv
->promiscuous
= promiscuous
;
5708 /* Turn on/off promiscuous mode. */
5709 if (hw
->promiscuous
<= 1 && prev_state
<= 1)
5710 hw_set_promiscuous(hw
, hw
->promiscuous
);
5713 * Port is not in promiscuous mode, meaning it is released
5716 if ((hw
->features
& STP_SUPPORT
) && !promiscuous
&&
5717 (dev
->priv_flags
& IFF_BRIDGE_PORT
)) {
5718 struct ksz_switch
*sw
= hw
->ksz_switch
;
5719 int port
= priv
->port
.first_port
;
5721 port_set_stp_state(hw
, port
, STP_STATE_DISABLED
);
5723 if (sw
->member
& port
) {
5724 sw
->member
&= ~port
;
5731 static void dev_set_multicast(struct dev_priv
*priv
, struct ksz_hw
*hw
,
5734 if (multicast
!= priv
->multicast
) {
5735 u8 all_multi
= hw
->all_multi
;
5741 priv
->multicast
= multicast
;
5743 /* Turn on/off all multicast mode. */
5744 if (hw
->all_multi
<= 1 && all_multi
<= 1)
5745 hw_set_multicast(hw
, hw
->all_multi
);
5750 * netdev_set_rx_mode
5751 * @dev: Network device.
5753 * This routine is used to set multicast addresses or put the network device
5754 * into promiscuous mode.
5756 static void netdev_set_rx_mode(struct net_device
*dev
)
5758 struct dev_priv
*priv
= netdev_priv(dev
);
5759 struct dev_info
*hw_priv
= priv
->adapter
;
5760 struct ksz_hw
*hw
= &hw_priv
->hw
;
5761 struct netdev_hw_addr
*ha
;
5762 int multicast
= (dev
->flags
& IFF_ALLMULTI
);
5764 dev_set_promiscuous(dev
, priv
, hw
, (dev
->flags
& IFF_PROMISC
));
5766 if (hw_priv
->hw
.dev_count
> 1)
5767 multicast
|= (dev
->flags
& IFF_MULTICAST
);
5768 dev_set_multicast(priv
, hw
, multicast
);
5770 /* Cannot use different hashes in multiple device interfaces mode. */
5771 if (hw_priv
->hw
.dev_count
> 1)
5774 if ((dev
->flags
& IFF_MULTICAST
) && !netdev_mc_empty(dev
)) {
5777 /* List too big to support so turn on all multicast mode. */
5778 if (netdev_mc_count(dev
) > MAX_MULTICAST_LIST
) {
5779 if (MAX_MULTICAST_LIST
!= hw
->multi_list_size
) {
5780 hw
->multi_list_size
= MAX_MULTICAST_LIST
;
5782 hw_set_multicast(hw
, hw
->all_multi
);
5787 netdev_for_each_mc_addr(ha
, dev
) {
5788 if (i
>= MAX_MULTICAST_LIST
)
5790 memcpy(hw
->multi_list
[i
++], ha
->addr
, ETH_ALEN
);
5792 hw
->multi_list_size
= (u8
) i
;
5793 hw_set_grp_addr(hw
);
5795 if (MAX_MULTICAST_LIST
== hw
->multi_list_size
) {
5797 hw_set_multicast(hw
, hw
->all_multi
);
5799 hw
->multi_list_size
= 0;
5800 hw_clr_multicast(hw
);
5804 static int netdev_change_mtu(struct net_device
*dev
, int new_mtu
)
5806 struct dev_priv
*priv
= netdev_priv(dev
);
5807 struct dev_info
*hw_priv
= priv
->adapter
;
5808 struct ksz_hw
*hw
= &hw_priv
->hw
;
5811 if (netif_running(dev
))
5814 /* Cannot use different MTU in multiple device interfaces mode. */
5815 if (hw
->dev_count
> 1)
5816 if (dev
!= hw_priv
->dev
)
5821 if (dev
->mtu
!= new_mtu
) {
5822 hw_mtu
= new_mtu
+ ETHERNET_HEADER_SIZE
+ 4;
5823 if (hw_mtu
> MAX_RX_BUF_SIZE
)
5825 if (hw_mtu
> REGULAR_RX_BUF_SIZE
) {
5826 hw
->features
|= RX_HUGE_FRAME
;
5827 hw_mtu
= MAX_RX_BUF_SIZE
;
5829 hw
->features
&= ~RX_HUGE_FRAME
;
5830 hw_mtu
= REGULAR_RX_BUF_SIZE
;
5832 hw_mtu
= (hw_mtu
+ 3) & ~3;
5833 hw_priv
->mtu
= hw_mtu
;
5840 * netdev_ioctl - I/O control processing
5841 * @dev: Network device.
5842 * @ifr: Interface request structure.
5843 * @cmd: I/O control code.
5845 * This function is used to process I/O control calls.
5847 * Return 0 to indicate success.
5849 static int netdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
5851 struct dev_priv
*priv
= netdev_priv(dev
);
5852 struct dev_info
*hw_priv
= priv
->adapter
;
5853 struct ksz_hw
*hw
= &hw_priv
->hw
;
5854 struct ksz_port
*port
= &priv
->port
;
5856 struct mii_ioctl_data
*data
= if_mii(ifr
);
5858 if (down_interruptible(&priv
->proc_sem
))
5859 return -ERESTARTSYS
;
5862 /* Get address of MII PHY in use. */
5864 data
->phy_id
= priv
->id
;
5866 /* Fallthrough... */
5868 /* Read MII PHY register. */
5870 if (data
->phy_id
!= priv
->id
|| data
->reg_num
>= 6)
5873 hw_r_phy(hw
, port
->linked
->port_id
, data
->reg_num
,
5877 /* Write MII PHY register. */
5879 if (!capable(CAP_NET_ADMIN
))
5881 else if (data
->phy_id
!= priv
->id
|| data
->reg_num
>= 6)
5884 hw_w_phy(hw
, port
->linked
->port_id
, data
->reg_num
,
5889 result
= -EOPNOTSUPP
;
5892 up(&priv
->proc_sem
);
5902 * mdio_read - read PHY register
5903 * @dev: Network device.
5904 * @phy_id: The PHY id.
5905 * @reg_num: The register number.
5907 * This function returns the PHY register value.
5909 * Return the register value.
5911 static int mdio_read(struct net_device
*dev
, int phy_id
, int reg_num
)
5913 struct dev_priv
*priv
= netdev_priv(dev
);
5914 struct ksz_port
*port
= &priv
->port
;
5915 struct ksz_hw
*hw
= port
->hw
;
5918 hw_r_phy(hw
, port
->linked
->port_id
, reg_num
<< 1, &val_out
);
5923 * mdio_write - set PHY register
5924 * @dev: Network device.
5925 * @phy_id: The PHY id.
5926 * @reg_num: The register number.
5927 * @val: The register value.
5929 * This procedure sets the PHY register value.
5931 static void mdio_write(struct net_device
*dev
, int phy_id
, int reg_num
, int val
)
5933 struct dev_priv
*priv
= netdev_priv(dev
);
5934 struct ksz_port
*port
= &priv
->port
;
5935 struct ksz_hw
*hw
= port
->hw
;
5939 for (i
= 0, pi
= port
->first_port
; i
< port
->port_cnt
; i
++, pi
++)
5940 hw_w_phy(hw
, pi
, reg_num
<< 1, val
);
5947 #define EEPROM_SIZE 0x40
5949 static u16 eeprom_data
[EEPROM_SIZE
] = { 0 };
5951 #define ADVERTISED_ALL \
5952 (ADVERTISED_10baseT_Half | \
5953 ADVERTISED_10baseT_Full | \
5954 ADVERTISED_100baseT_Half | \
5955 ADVERTISED_100baseT_Full)
5957 /* These functions use the MII functions in mii.c. */
5960 * netdev_get_settings - get network device settings
5961 * @dev: Network device.
5962 * @cmd: Ethtool command.
5964 * This function queries the PHY and returns its state in the ethtool command.
5966 * Return 0 if successful; otherwise an error code.
5968 static int netdev_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
5970 struct dev_priv
*priv
= netdev_priv(dev
);
5971 struct dev_info
*hw_priv
= priv
->adapter
;
5973 mutex_lock(&hw_priv
->lock
);
5974 mii_ethtool_gset(&priv
->mii_if
, cmd
);
5975 cmd
->advertising
|= SUPPORTED_TP
;
5976 mutex_unlock(&hw_priv
->lock
);
5978 /* Save advertised settings for workaround in next function. */
5979 priv
->advertising
= cmd
->advertising
;
5984 * netdev_set_settings - set network device settings
5985 * @dev: Network device.
5986 * @cmd: Ethtool command.
5988 * This function sets the PHY according to the ethtool command.
5990 * Return 0 if successful; otherwise an error code.
5992 static int netdev_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
5994 struct dev_priv
*priv
= netdev_priv(dev
);
5995 struct dev_info
*hw_priv
= priv
->adapter
;
5996 struct ksz_port
*port
= &priv
->port
;
5997 u32 speed
= ethtool_cmd_speed(cmd
);
6001 * ethtool utility does not change advertised setting if auto
6002 * negotiation is not specified explicitly.
6004 if (cmd
->autoneg
&& priv
->advertising
== cmd
->advertising
) {
6005 cmd
->advertising
|= ADVERTISED_ALL
;
6008 ~(ADVERTISED_100baseT_Full
|
6009 ADVERTISED_100baseT_Half
);
6010 else if (100 == speed
)
6012 ~(ADVERTISED_10baseT_Full
|
6013 ADVERTISED_10baseT_Half
);
6014 if (0 == cmd
->duplex
)
6016 ~(ADVERTISED_100baseT_Full
|
6017 ADVERTISED_10baseT_Full
);
6018 else if (1 == cmd
->duplex
)
6020 ~(ADVERTISED_100baseT_Half
|
6021 ADVERTISED_10baseT_Half
);
6023 mutex_lock(&hw_priv
->lock
);
6025 (cmd
->advertising
& ADVERTISED_ALL
) ==
6029 port
->force_link
= 0;
6031 port
->duplex
= cmd
->duplex
+ 1;
6033 port
->speed
= speed
;
6035 port
->force_link
= 0;
6037 port
->force_link
= 1;
6039 rc
= mii_ethtool_sset(&priv
->mii_if
, cmd
);
6040 mutex_unlock(&hw_priv
->lock
);
6045 * netdev_nway_reset - restart auto-negotiation
6046 * @dev: Network device.
6048 * This function restarts the PHY for auto-negotiation.
6050 * Return 0 if successful; otherwise an error code.
6052 static int netdev_nway_reset(struct net_device
*dev
)
6054 struct dev_priv
*priv
= netdev_priv(dev
);
6055 struct dev_info
*hw_priv
= priv
->adapter
;
6058 mutex_lock(&hw_priv
->lock
);
6059 rc
= mii_nway_restart(&priv
->mii_if
);
6060 mutex_unlock(&hw_priv
->lock
);
6065 * netdev_get_link - get network device link status
6066 * @dev: Network device.
6068 * This function gets the link status from the PHY.
6070 * Return true if PHY is linked and false otherwise.
6072 static u32
netdev_get_link(struct net_device
*dev
)
6074 struct dev_priv
*priv
= netdev_priv(dev
);
6077 rc
= mii_link_ok(&priv
->mii_if
);
6082 * netdev_get_drvinfo - get network driver information
6083 * @dev: Network device.
6084 * @info: Ethtool driver info data structure.
6086 * This procedure returns the driver information.
6088 static void netdev_get_drvinfo(struct net_device
*dev
,
6089 struct ethtool_drvinfo
*info
)
6091 struct dev_priv
*priv
= netdev_priv(dev
);
6092 struct dev_info
*hw_priv
= priv
->adapter
;
6094 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
6095 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
6096 strlcpy(info
->bus_info
, pci_name(hw_priv
->pdev
),
6097 sizeof(info
->bus_info
));
6101 * netdev_get_regs_len - get length of register dump
6102 * @dev: Network device.
6104 * This function returns the length of the register dump.
6106 * Return length of the register dump.
6108 static struct hw_regs
{
6111 } hw_regs_range
[] = {
6112 { KS_DMA_TX_CTRL
, KS884X_INTERRUPTS_STATUS
},
6113 { KS_ADD_ADDR_0_LO
, KS_ADD_ADDR_F_HI
},
6114 { KS884X_ADDR_0_OFFSET
, KS8841_WOL_FRAME_BYTE2_OFFSET
},
6115 { KS884X_SIDER_P
, KS8842_SGCR7_P
},
6116 { KS8842_MACAR1_P
, KS8842_TOSR8_P
},
6117 { KS884X_P1MBCR_P
, KS8842_P3ERCR_P
},
6121 static int netdev_get_regs_len(struct net_device
*dev
)
6123 struct hw_regs
*range
= hw_regs_range
;
6124 int regs_len
= 0x10 * sizeof(u32
);
6126 while (range
->end
> range
->start
) {
6127 regs_len
+= (range
->end
- range
->start
+ 3) / 4 * 4;
6134 * netdev_get_regs - get register dump
6135 * @dev: Network device.
6136 * @regs: Ethtool registers data structure.
6137 * @ptr: Buffer to store the register values.
6139 * This procedure dumps the register values in the provided buffer.
6141 static void netdev_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
6144 struct dev_priv
*priv
= netdev_priv(dev
);
6145 struct dev_info
*hw_priv
= priv
->adapter
;
6146 struct ksz_hw
*hw
= &hw_priv
->hw
;
6147 int *buf
= (int *) ptr
;
6148 struct hw_regs
*range
= hw_regs_range
;
6151 mutex_lock(&hw_priv
->lock
);
6153 for (len
= 0; len
< 0x40; len
+= 4) {
6154 pci_read_config_dword(hw_priv
->pdev
, len
, buf
);
6157 while (range
->end
> range
->start
) {
6158 for (len
= range
->start
; len
< range
->end
; len
+= 4) {
6159 *buf
= readl(hw
->io
+ len
);
6164 mutex_unlock(&hw_priv
->lock
);
6167 #define WOL_SUPPORT \
6168 (WAKE_PHY | WAKE_MAGIC | \
6169 WAKE_UCAST | WAKE_MCAST | \
6170 WAKE_BCAST | WAKE_ARP)
6173 * netdev_get_wol - get Wake-on-LAN support
6174 * @dev: Network device.
6175 * @wol: Ethtool Wake-on-LAN data structure.
6177 * This procedure returns Wake-on-LAN support.
6179 static void netdev_get_wol(struct net_device
*dev
,
6180 struct ethtool_wolinfo
*wol
)
6182 struct dev_priv
*priv
= netdev_priv(dev
);
6183 struct dev_info
*hw_priv
= priv
->adapter
;
6185 wol
->supported
= hw_priv
->wol_support
;
6186 wol
->wolopts
= hw_priv
->wol_enable
;
6187 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
6191 * netdev_set_wol - set Wake-on-LAN support
6192 * @dev: Network device.
6193 * @wol: Ethtool Wake-on-LAN data structure.
6195 * This function sets Wake-on-LAN support.
6197 * Return 0 if successful; otherwise an error code.
6199 static int netdev_set_wol(struct net_device
*dev
,
6200 struct ethtool_wolinfo
*wol
)
6202 struct dev_priv
*priv
= netdev_priv(dev
);
6203 struct dev_info
*hw_priv
= priv
->adapter
;
6205 /* Need to find a way to retrieve the device IP address. */
6206 static const u8 net_addr
[] = { 192, 168, 1, 1 };
6208 if (wol
->wolopts
& ~hw_priv
->wol_support
)
6211 hw_priv
->wol_enable
= wol
->wolopts
;
6213 /* Link wakeup cannot really be disabled. */
6215 hw_priv
->wol_enable
|= WAKE_PHY
;
6216 hw_enable_wol(&hw_priv
->hw
, hw_priv
->wol_enable
, net_addr
);
6221 * netdev_get_msglevel - get debug message level
6222 * @dev: Network device.
6224 * This function returns current debug message level.
6226 * Return current debug message flags.
6228 static u32
netdev_get_msglevel(struct net_device
*dev
)
6230 struct dev_priv
*priv
= netdev_priv(dev
);
6232 return priv
->msg_enable
;
6236 * netdev_set_msglevel - set debug message level
6237 * @dev: Network device.
6238 * @value: Debug message flags.
6240 * This procedure sets debug message level.
6242 static void netdev_set_msglevel(struct net_device
*dev
, u32 value
)
6244 struct dev_priv
*priv
= netdev_priv(dev
);
6246 priv
->msg_enable
= value
;
6250 * netdev_get_eeprom_len - get EEPROM length
6251 * @dev: Network device.
6253 * This function returns the length of the EEPROM.
6255 * Return length of the EEPROM.
6257 static int netdev_get_eeprom_len(struct net_device
*dev
)
6259 return EEPROM_SIZE
* 2;
6263 * netdev_get_eeprom - get EEPROM data
6264 * @dev: Network device.
6265 * @eeprom: Ethtool EEPROM data structure.
6266 * @data: Buffer to store the EEPROM data.
6268 * This function dumps the EEPROM data in the provided buffer.
6270 * Return 0 if successful; otherwise an error code.
6272 #define EEPROM_MAGIC 0x10A18842
6274 static int netdev_get_eeprom(struct net_device
*dev
,
6275 struct ethtool_eeprom
*eeprom
, u8
*data
)
6277 struct dev_priv
*priv
= netdev_priv(dev
);
6278 struct dev_info
*hw_priv
= priv
->adapter
;
6279 u8
*eeprom_byte
= (u8
*) eeprom_data
;
6283 len
= (eeprom
->offset
+ eeprom
->len
+ 1) / 2;
6284 for (i
= eeprom
->offset
/ 2; i
< len
; i
++)
6285 eeprom_data
[i
] = eeprom_read(&hw_priv
->hw
, i
);
6286 eeprom
->magic
= EEPROM_MAGIC
;
6287 memcpy(data
, &eeprom_byte
[eeprom
->offset
], eeprom
->len
);
6293 * netdev_set_eeprom - write EEPROM data
6294 * @dev: Network device.
6295 * @eeprom: Ethtool EEPROM data structure.
6296 * @data: Data buffer.
6298 * This function modifies the EEPROM data one byte at a time.
6300 * Return 0 if successful; otherwise an error code.
6302 static int netdev_set_eeprom(struct net_device
*dev
,
6303 struct ethtool_eeprom
*eeprom
, u8
*data
)
6305 struct dev_priv
*priv
= netdev_priv(dev
);
6306 struct dev_info
*hw_priv
= priv
->adapter
;
6307 u16 eeprom_word
[EEPROM_SIZE
];
6308 u8
*eeprom_byte
= (u8
*) eeprom_word
;
6312 if (eeprom
->magic
!= EEPROM_MAGIC
)
6315 len
= (eeprom
->offset
+ eeprom
->len
+ 1) / 2;
6316 for (i
= eeprom
->offset
/ 2; i
< len
; i
++)
6317 eeprom_data
[i
] = eeprom_read(&hw_priv
->hw
, i
);
6318 memcpy(eeprom_word
, eeprom_data
, EEPROM_SIZE
* 2);
6319 memcpy(&eeprom_byte
[eeprom
->offset
], data
, eeprom
->len
);
6320 for (i
= 0; i
< EEPROM_SIZE
; i
++)
6321 if (eeprom_word
[i
] != eeprom_data
[i
]) {
6322 eeprom_data
[i
] = eeprom_word
[i
];
6323 eeprom_write(&hw_priv
->hw
, i
, eeprom_data
[i
]);
6330 * netdev_get_pauseparam - get flow control parameters
6331 * @dev: Network device.
6332 * @pause: Ethtool PAUSE settings data structure.
6334 * This procedure returns the PAUSE control flow settings.
6336 static void netdev_get_pauseparam(struct net_device
*dev
,
6337 struct ethtool_pauseparam
*pause
)
6339 struct dev_priv
*priv
= netdev_priv(dev
);
6340 struct dev_info
*hw_priv
= priv
->adapter
;
6341 struct ksz_hw
*hw
= &hw_priv
->hw
;
6343 pause
->autoneg
= (hw
->overrides
& PAUSE_FLOW_CTRL
) ? 0 : 1;
6344 if (!hw
->ksz_switch
) {
6346 (hw
->rx_cfg
& DMA_RX_FLOW_ENABLE
) ? 1 : 0;
6348 (hw
->tx_cfg
& DMA_TX_FLOW_ENABLE
) ? 1 : 0;
6351 (sw_chk(hw
, KS8842_SWITCH_CTRL_1_OFFSET
,
6352 SWITCH_RX_FLOW_CTRL
)) ? 1 : 0;
6354 (sw_chk(hw
, KS8842_SWITCH_CTRL_1_OFFSET
,
6355 SWITCH_TX_FLOW_CTRL
)) ? 1 : 0;
6360 * netdev_set_pauseparam - set flow control parameters
6361 * @dev: Network device.
6362 * @pause: Ethtool PAUSE settings data structure.
6364 * This function sets the PAUSE control flow settings.
6365 * Not implemented yet.
6367 * Return 0 if successful; otherwise an error code.
6369 static int netdev_set_pauseparam(struct net_device
*dev
,
6370 struct ethtool_pauseparam
*pause
)
6372 struct dev_priv
*priv
= netdev_priv(dev
);
6373 struct dev_info
*hw_priv
= priv
->adapter
;
6374 struct ksz_hw
*hw
= &hw_priv
->hw
;
6375 struct ksz_port
*port
= &priv
->port
;
6377 mutex_lock(&hw_priv
->lock
);
6378 if (pause
->autoneg
) {
6379 if (!pause
->rx_pause
&& !pause
->tx_pause
)
6380 port
->flow_ctrl
= PHY_NO_FLOW_CTRL
;
6382 port
->flow_ctrl
= PHY_FLOW_CTRL
;
6383 hw
->overrides
&= ~PAUSE_FLOW_CTRL
;
6384 port
->force_link
= 0;
6385 if (hw
->ksz_switch
) {
6386 sw_cfg(hw
, KS8842_SWITCH_CTRL_1_OFFSET
,
6387 SWITCH_RX_FLOW_CTRL
, 1);
6388 sw_cfg(hw
, KS8842_SWITCH_CTRL_1_OFFSET
,
6389 SWITCH_TX_FLOW_CTRL
, 1);
6391 port_set_link_speed(port
);
6393 hw
->overrides
|= PAUSE_FLOW_CTRL
;
6394 if (hw
->ksz_switch
) {
6395 sw_cfg(hw
, KS8842_SWITCH_CTRL_1_OFFSET
,
6396 SWITCH_RX_FLOW_CTRL
, pause
->rx_pause
);
6397 sw_cfg(hw
, KS8842_SWITCH_CTRL_1_OFFSET
,
6398 SWITCH_TX_FLOW_CTRL
, pause
->tx_pause
);
6400 set_flow_ctrl(hw
, pause
->rx_pause
, pause
->tx_pause
);
6402 mutex_unlock(&hw_priv
->lock
);
6408 * netdev_get_ringparam - get tx/rx ring parameters
6409 * @dev: Network device.
6410 * @pause: Ethtool RING settings data structure.
6412 * This procedure returns the TX/RX ring settings.
6414 static void netdev_get_ringparam(struct net_device
*dev
,
6415 struct ethtool_ringparam
*ring
)
6417 struct dev_priv
*priv
= netdev_priv(dev
);
6418 struct dev_info
*hw_priv
= priv
->adapter
;
6419 struct ksz_hw
*hw
= &hw_priv
->hw
;
6421 ring
->tx_max_pending
= (1 << 9);
6422 ring
->tx_pending
= hw
->tx_desc_info
.alloc
;
6423 ring
->rx_max_pending
= (1 << 9);
6424 ring
->rx_pending
= hw
->rx_desc_info
.alloc
;
6427 #define STATS_LEN (TOTAL_PORT_COUNTER_NUM)
6430 char string
[ETH_GSTRING_LEN
];
6431 } ethtool_stats_keys
[STATS_LEN
] = {
6432 { "rx_lo_priority_octets" },
6433 { "rx_hi_priority_octets" },
6434 { "rx_undersize_packets" },
6436 { "rx_oversize_packets" },
6438 { "rx_symbol_errors" },
6439 { "rx_crc_errors" },
6440 { "rx_align_errors" },
6441 { "rx_mac_ctrl_packets" },
6442 { "rx_pause_packets" },
6443 { "rx_bcast_packets" },
6444 { "rx_mcast_packets" },
6445 { "rx_ucast_packets" },
6446 { "rx_64_or_less_octet_packets" },
6447 { "rx_65_to_127_octet_packets" },
6448 { "rx_128_to_255_octet_packets" },
6449 { "rx_256_to_511_octet_packets" },
6450 { "rx_512_to_1023_octet_packets" },
6451 { "rx_1024_to_1522_octet_packets" },
6453 { "tx_lo_priority_octets" },
6454 { "tx_hi_priority_octets" },
6455 { "tx_late_collisions" },
6456 { "tx_pause_packets" },
6457 { "tx_bcast_packets" },
6458 { "tx_mcast_packets" },
6459 { "tx_ucast_packets" },
6461 { "tx_total_collisions" },
6462 { "tx_excessive_collisions" },
6463 { "tx_single_collisions" },
6464 { "tx_mult_collisions" },
6471 * netdev_get_strings - get statistics identity strings
6472 * @dev: Network device.
6473 * @stringset: String set identifier.
6474 * @buf: Buffer to store the strings.
6476 * This procedure returns the strings used to identify the statistics.
6478 static void netdev_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
6480 struct dev_priv
*priv
= netdev_priv(dev
);
6481 struct dev_info
*hw_priv
= priv
->adapter
;
6482 struct ksz_hw
*hw
= &hw_priv
->hw
;
6484 if (ETH_SS_STATS
== stringset
)
6485 memcpy(buf
, ðtool_stats_keys
,
6486 ETH_GSTRING_LEN
* hw
->mib_cnt
);
6490 * netdev_get_sset_count - get statistics size
6491 * @dev: Network device.
6492 * @sset: The statistics set number.
6494 * This function returns the size of the statistics to be reported.
6496 * Return size of the statistics to be reported.
6498 static int netdev_get_sset_count(struct net_device
*dev
, int sset
)
6500 struct dev_priv
*priv
= netdev_priv(dev
);
6501 struct dev_info
*hw_priv
= priv
->adapter
;
6502 struct ksz_hw
*hw
= &hw_priv
->hw
;
6513 * netdev_get_ethtool_stats - get network device statistics
6514 * @dev: Network device.
6515 * @stats: Ethtool statistics data structure.
6516 * @data: Buffer to store the statistics.
6518 * This procedure returns the statistics.
6520 static void netdev_get_ethtool_stats(struct net_device
*dev
,
6521 struct ethtool_stats
*stats
, u64
*data
)
6523 struct dev_priv
*priv
= netdev_priv(dev
);
6524 struct dev_info
*hw_priv
= priv
->adapter
;
6525 struct ksz_hw
*hw
= &hw_priv
->hw
;
6526 struct ksz_port
*port
= &priv
->port
;
6527 int n_stats
= stats
->n_stats
;
6532 u64 counter
[TOTAL_PORT_COUNTER_NUM
];
6534 mutex_lock(&hw_priv
->lock
);
6535 n
= SWITCH_PORT_NUM
;
6536 for (i
= 0, p
= port
->first_port
; i
< port
->mib_port_cnt
; i
++, p
++) {
6537 if (media_connected
== hw
->port_mib
[p
].state
) {
6538 hw_priv
->counter
[p
].read
= 1;
6540 /* Remember first port that requests read. */
6541 if (n
== SWITCH_PORT_NUM
)
6545 mutex_unlock(&hw_priv
->lock
);
6547 if (n
< SWITCH_PORT_NUM
)
6548 schedule_work(&hw_priv
->mib_read
);
6550 if (1 == port
->mib_port_cnt
&& n
< SWITCH_PORT_NUM
) {
6552 rc
= wait_event_interruptible_timeout(
6553 hw_priv
->counter
[p
].counter
,
6554 2 == hw_priv
->counter
[p
].read
,
6557 for (i
= 0, p
= n
; i
< port
->mib_port_cnt
- n
; i
++, p
++) {
6559 rc
= wait_event_interruptible_timeout(
6560 hw_priv
->counter
[p
].counter
,
6561 2 == hw_priv
->counter
[p
].read
,
6563 } else if (hw
->port_mib
[p
].cnt_ptr
) {
6564 rc
= wait_event_interruptible_timeout(
6565 hw_priv
->counter
[p
].counter
,
6566 2 == hw_priv
->counter
[p
].read
,
6571 get_mib_counters(hw
, port
->first_port
, port
->mib_port_cnt
, counter
);
6576 for (i
= 0; i
< n
; i
++)
6577 *data
++ = counter
[i
];
6581 * netdev_set_features - set receive checksum support
6582 * @dev: Network device.
6583 * @features: New device features (offloads).
6585 * This function sets receive checksum support setting.
6587 * Return 0 if successful; otherwise an error code.
6589 static int netdev_set_features(struct net_device
*dev
,
6590 netdev_features_t features
)
6592 struct dev_priv
*priv
= netdev_priv(dev
);
6593 struct dev_info
*hw_priv
= priv
->adapter
;
6594 struct ksz_hw
*hw
= &hw_priv
->hw
;
6596 mutex_lock(&hw_priv
->lock
);
6598 /* see note in hw_setup() */
6599 if (features
& NETIF_F_RXCSUM
)
6600 hw
->rx_cfg
|= DMA_RX_CSUM_TCP
| DMA_RX_CSUM_IP
;
6602 hw
->rx_cfg
&= ~(DMA_RX_CSUM_TCP
| DMA_RX_CSUM_IP
);
6605 writel(hw
->rx_cfg
, hw
->io
+ KS_DMA_RX_CTRL
);
6607 mutex_unlock(&hw_priv
->lock
);
6612 static const struct ethtool_ops netdev_ethtool_ops
= {
6613 .get_settings
= netdev_get_settings
,
6614 .set_settings
= netdev_set_settings
,
6615 .nway_reset
= netdev_nway_reset
,
6616 .get_link
= netdev_get_link
,
6617 .get_drvinfo
= netdev_get_drvinfo
,
6618 .get_regs_len
= netdev_get_regs_len
,
6619 .get_regs
= netdev_get_regs
,
6620 .get_wol
= netdev_get_wol
,
6621 .set_wol
= netdev_set_wol
,
6622 .get_msglevel
= netdev_get_msglevel
,
6623 .set_msglevel
= netdev_set_msglevel
,
6624 .get_eeprom_len
= netdev_get_eeprom_len
,
6625 .get_eeprom
= netdev_get_eeprom
,
6626 .set_eeprom
= netdev_set_eeprom
,
6627 .get_pauseparam
= netdev_get_pauseparam
,
6628 .set_pauseparam
= netdev_set_pauseparam
,
6629 .get_ringparam
= netdev_get_ringparam
,
6630 .get_strings
= netdev_get_strings
,
6631 .get_sset_count
= netdev_get_sset_count
,
6632 .get_ethtool_stats
= netdev_get_ethtool_stats
,
6636 * Hardware monitoring
6639 static void update_link(struct net_device
*dev
, struct dev_priv
*priv
,
6640 struct ksz_port
*port
)
6642 if (priv
->media_state
!= port
->linked
->state
) {
6643 priv
->media_state
= port
->linked
->state
;
6644 if (netif_running(dev
))
6645 set_media_state(dev
, media_connected
);
6649 static void mib_read_work(struct work_struct
*work
)
6651 struct dev_info
*hw_priv
=
6652 container_of(work
, struct dev_info
, mib_read
);
6653 struct ksz_hw
*hw
= &hw_priv
->hw
;
6654 struct ksz_port_mib
*mib
;
6657 next_jiffies
= jiffies
;
6658 for (i
= 0; i
< hw
->mib_port_cnt
; i
++) {
6659 mib
= &hw
->port_mib
[i
];
6661 /* Reading MIB counters or requested to read. */
6662 if (mib
->cnt_ptr
|| 1 == hw_priv
->counter
[i
].read
) {
6664 /* Need to process receive interrupt. */
6665 if (port_r_cnt(hw
, i
))
6667 hw_priv
->counter
[i
].read
= 0;
6669 /* Finish reading counters. */
6670 if (0 == mib
->cnt_ptr
) {
6671 hw_priv
->counter
[i
].read
= 2;
6672 wake_up_interruptible(
6673 &hw_priv
->counter
[i
].counter
);
6675 } else if (jiffies
>= hw_priv
->counter
[i
].time
) {
6676 /* Only read MIB counters when the port is connected. */
6677 if (media_connected
== mib
->state
)
6678 hw_priv
->counter
[i
].read
= 1;
6679 next_jiffies
+= HZ
* 1 * hw
->mib_port_cnt
;
6680 hw_priv
->counter
[i
].time
= next_jiffies
;
6682 /* Port is just disconnected. */
6683 } else if (mib
->link_down
) {
6686 /* Read counters one last time after link is lost. */
6687 hw_priv
->counter
[i
].read
= 1;
6692 static void mib_monitor(unsigned long ptr
)
6694 struct dev_info
*hw_priv
= (struct dev_info
*) ptr
;
6696 mib_read_work(&hw_priv
->mib_read
);
6698 /* This is used to verify Wake-on-LAN is working. */
6699 if (hw_priv
->pme_wait
) {
6700 if (hw_priv
->pme_wait
<= jiffies
) {
6701 hw_clr_wol_pme_status(&hw_priv
->hw
);
6702 hw_priv
->pme_wait
= 0;
6704 } else if (hw_chk_wol_pme_status(&hw_priv
->hw
)) {
6706 /* PME is asserted. Wait 2 seconds to clear it. */
6707 hw_priv
->pme_wait
= jiffies
+ HZ
* 2;
6710 ksz_update_timer(&hw_priv
->mib_timer_info
);
6714 * dev_monitor - periodic monitoring
6715 * @ptr: Network device pointer.
6717 * This routine is run in a kernel timer to monitor the network device.
6719 static void dev_monitor(unsigned long ptr
)
6721 struct net_device
*dev
= (struct net_device
*) ptr
;
6722 struct dev_priv
*priv
= netdev_priv(dev
);
6723 struct dev_info
*hw_priv
= priv
->adapter
;
6724 struct ksz_hw
*hw
= &hw_priv
->hw
;
6725 struct ksz_port
*port
= &priv
->port
;
6727 if (!(hw
->features
& LINK_INT_WORKING
))
6728 port_get_link_speed(port
);
6729 update_link(dev
, priv
, port
);
6731 ksz_update_timer(&priv
->monitor_timer_info
);
6735 * Linux network device interface functions
6738 /* Driver exported variables */
6740 static int msg_enable
;
6742 static char *macaddr
= ":";
6743 static char *mac1addr
= ":";
6746 * This enables multiple network device mode for KSZ8842, which contains a
6747 * switch with two physical ports. Some users like to take control of the
6748 * ports for running Spanning Tree Protocol. The driver will create an
6749 * additional eth? device for the other port.
6751 * Some limitations are the network devices cannot have different MTU and
6752 * multicast hash tables.
6754 static int multi_dev
;
6757 * As most users select multiple network device mode to use Spanning Tree
6758 * Protocol, this enables a feature in which most unicast and multicast packets
6759 * are forwarded inside the switch and not passed to the host. Only packets
6760 * that need the host's attention are passed to it. This prevents the host
6761 * wasting CPU time to examine each and every incoming packets and do the
6762 * forwarding itself.
6764 * As the hack requires the private bridge header, the driver cannot compile
6765 * with just the kernel headers.
6767 * Enabling STP support also turns on multiple network device mode.
6772 * This enables fast aging in the KSZ8842 switch. Not sure what situation
6773 * needs that. However, fast aging is used to flush the dynamic MAC table when
6774 * STP support is enabled.
6776 static int fast_aging
;
6779 * netdev_init - initialize network device.
6780 * @dev: Network device.
6782 * This function initializes the network device.
6784 * Return 0 if successful; otherwise an error code indicating failure.
6786 static int __init
netdev_init(struct net_device
*dev
)
6788 struct dev_priv
*priv
= netdev_priv(dev
);
6790 /* 500 ms timeout */
6791 ksz_init_timer(&priv
->monitor_timer_info
, 500 * HZ
/ 1000,
6794 /* 500 ms timeout */
6795 dev
->watchdog_timeo
= HZ
/ 2;
6797 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_RXCSUM
;
6800 * Hardware does not really support IPv6 checksum generation, but
6801 * driver actually runs faster with this on.
6803 dev
->hw_features
|= NETIF_F_IPV6_CSUM
;
6805 dev
->features
|= dev
->hw_features
;
6807 sema_init(&priv
->proc_sem
, 1);
6809 priv
->mii_if
.phy_id_mask
= 0x1;
6810 priv
->mii_if
.reg_num_mask
= 0x7;
6811 priv
->mii_if
.dev
= dev
;
6812 priv
->mii_if
.mdio_read
= mdio_read
;
6813 priv
->mii_if
.mdio_write
= mdio_write
;
6814 priv
->mii_if
.phy_id
= priv
->port
.first_port
+ 1;
6816 priv
->msg_enable
= netif_msg_init(msg_enable
,
6817 (NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
));
6822 static const struct net_device_ops netdev_ops
= {
6823 .ndo_init
= netdev_init
,
6824 .ndo_open
= netdev_open
,
6825 .ndo_stop
= netdev_close
,
6826 .ndo_get_stats
= netdev_query_statistics
,
6827 .ndo_start_xmit
= netdev_tx
,
6828 .ndo_tx_timeout
= netdev_tx_timeout
,
6829 .ndo_change_mtu
= netdev_change_mtu
,
6830 .ndo_set_features
= netdev_set_features
,
6831 .ndo_set_mac_address
= netdev_set_mac_address
,
6832 .ndo_validate_addr
= eth_validate_addr
,
6833 .ndo_do_ioctl
= netdev_ioctl
,
6834 .ndo_set_rx_mode
= netdev_set_rx_mode
,
6835 #ifdef CONFIG_NET_POLL_CONTROLLER
6836 .ndo_poll_controller
= netdev_netpoll
,
6840 static void netdev_free(struct net_device
*dev
)
6842 if (dev
->watchdog_timeo
)
6843 unregister_netdev(dev
);
6848 struct platform_info
{
6849 struct dev_info dev_info
;
6850 struct net_device
*netdev
[SWITCH_PORT_NUM
];
6853 static int net_device_present
;
6855 static void get_mac_addr(struct dev_info
*hw_priv
, u8
*macaddr
, int port
)
6862 i
= j
= num
= got_num
= 0;
6863 while (j
< ETH_ALEN
) {
6868 digit
= hex_to_bin(macaddr
[i
]);
6870 num
= num
* 16 + digit
;
6871 else if (':' == macaddr
[i
])
6880 if (MAIN_PORT
== port
) {
6881 hw_priv
->hw
.override_addr
[j
++] = (u8
) num
;
6882 hw_priv
->hw
.override_addr
[5] +=
6885 hw_priv
->hw
.ksz_switch
->other_addr
[j
++] =
6887 hw_priv
->hw
.ksz_switch
->other_addr
[5] +=
6894 if (ETH_ALEN
== j
) {
6895 if (MAIN_PORT
== port
)
6896 hw_priv
->hw
.mac_override
= 1;
6900 #define KS884X_DMA_MASK (~0x0UL)
6902 static void read_other_addr(struct ksz_hw
*hw
)
6906 struct ksz_switch
*sw
= hw
->ksz_switch
;
6908 for (i
= 0; i
< 3; i
++)
6909 data
[i
] = eeprom_read(hw
, i
+ EEPROM_DATA_OTHER_MAC_ADDR
);
6910 if ((data
[0] || data
[1] || data
[2]) && data
[0] != 0xffff) {
6911 sw
->other_addr
[5] = (u8
) data
[0];
6912 sw
->other_addr
[4] = (u8
)(data
[0] >> 8);
6913 sw
->other_addr
[3] = (u8
) data
[1];
6914 sw
->other_addr
[2] = (u8
)(data
[1] >> 8);
6915 sw
->other_addr
[1] = (u8
) data
[2];
6916 sw
->other_addr
[0] = (u8
)(data
[2] >> 8);
6920 #ifndef PCI_VENDOR_ID_MICREL_KS
6921 #define PCI_VENDOR_ID_MICREL_KS 0x16c6
6924 static int pcidev_init(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
6926 struct net_device
*dev
;
6927 struct dev_priv
*priv
;
6928 struct dev_info
*hw_priv
;
6930 struct platform_info
*info
;
6931 struct ksz_port
*port
;
6932 unsigned long reg_base
;
6933 unsigned long reg_len
;
6940 char banner
[sizeof(version
)];
6941 struct ksz_switch
*sw
= NULL
;
6943 result
= pci_enable_device(pdev
);
6949 if (pci_set_dma_mask(pdev
, DMA_BIT_MASK(32)) ||
6950 pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)))
6953 reg_base
= pci_resource_start(pdev
, 0);
6954 reg_len
= pci_resource_len(pdev
, 0);
6955 if ((pci_resource_flags(pdev
, 0) & IORESOURCE_IO
) != 0)
6958 if (!request_mem_region(reg_base
, reg_len
, DRV_NAME
))
6960 pci_set_master(pdev
);
6964 info
= kzalloc(sizeof(struct platform_info
), GFP_KERNEL
);
6966 goto pcidev_init_dev_err
;
6968 hw_priv
= &info
->dev_info
;
6969 hw_priv
->pdev
= pdev
;
6973 hw
->io
= ioremap(reg_base
, reg_len
);
6975 goto pcidev_init_io_err
;
6979 if (msg_enable
& NETIF_MSG_PROBE
)
6980 pr_alert("chip not detected\n");
6982 goto pcidev_init_alloc_err
;
6985 snprintf(banner
, sizeof(banner
), "%s", version
);
6986 banner
[13] = cnt
+ '0'; /* Replace x in "Micrel KSZ884x" */
6987 dev_info(&hw_priv
->pdev
->dev
, "%s\n", banner
);
6988 dev_dbg(&hw_priv
->pdev
->dev
, "Mem = %p; IRQ = %d\n", hw
->io
, pdev
->irq
);
6990 /* Assume device is KSZ8841. */
6994 hw
->addr_list_size
= 0;
6995 hw
->mib_cnt
= PORT_COUNTER_NUM
;
6996 hw
->mib_port_cnt
= 1;
6998 /* KSZ8842 has a switch with multiple ports. */
7001 hw
->overrides
|= FAST_AGING
;
7003 hw
->mib_cnt
= TOTAL_PORT_COUNTER_NUM
;
7005 /* Multiple network device interfaces are required. */
7007 hw
->dev_count
= SWITCH_PORT_NUM
;
7008 hw
->addr_list_size
= SWITCH_PORT_NUM
- 1;
7011 /* Single network device has multiple ports. */
7012 if (1 == hw
->dev_count
) {
7013 port_count
= SWITCH_PORT_NUM
;
7014 mib_port_count
= SWITCH_PORT_NUM
;
7016 hw
->mib_port_cnt
= TOTAL_PORT_NUM
;
7017 hw
->ksz_switch
= kzalloc(sizeof(struct ksz_switch
), GFP_KERNEL
);
7018 if (!hw
->ksz_switch
)
7019 goto pcidev_init_alloc_err
;
7021 sw
= hw
->ksz_switch
;
7023 for (i
= 0; i
< hw
->mib_port_cnt
; i
++)
7024 hw
->port_mib
[i
].mib_start
= 0;
7026 hw
->parent
= hw_priv
;
7028 /* Default MTU is 1500. */
7029 hw_priv
->mtu
= (REGULAR_RX_BUF_SIZE
+ 3) & ~3;
7031 if (ksz_alloc_mem(hw_priv
))
7032 goto pcidev_init_mem_err
;
7034 hw_priv
->hw
.id
= net_device_present
;
7036 spin_lock_init(&hw_priv
->hwlock
);
7037 mutex_init(&hw_priv
->lock
);
7039 for (i
= 0; i
< TOTAL_PORT_NUM
; i
++)
7040 init_waitqueue_head(&hw_priv
->counter
[i
].counter
);
7042 if (macaddr
[0] != ':')
7043 get_mac_addr(hw_priv
, macaddr
, MAIN_PORT
);
7045 /* Read MAC address and initialize override address if not overrided. */
7048 /* Multiple device interfaces mode requires a second MAC address. */
7049 if (hw
->dev_count
> 1) {
7050 memcpy(sw
->other_addr
, hw
->override_addr
, ETH_ALEN
);
7051 read_other_addr(hw
);
7052 if (mac1addr
[0] != ':')
7053 get_mac_addr(hw_priv
, mac1addr
, OTHER_PORT
);
7060 hw_priv
->wol_support
= WOL_SUPPORT
;
7061 hw_priv
->wol_enable
= 0;
7064 INIT_WORK(&hw_priv
->mib_read
, mib_read_work
);
7066 /* 500 ms timeout */
7067 ksz_init_timer(&hw_priv
->mib_timer_info
, 500 * HZ
/ 1000,
7068 mib_monitor
, hw_priv
);
7070 for (i
= 0; i
< hw
->dev_count
; i
++) {
7071 dev
= alloc_etherdev(sizeof(struct dev_priv
));
7073 goto pcidev_init_reg_err
;
7074 SET_NETDEV_DEV(dev
, &pdev
->dev
);
7075 info
->netdev
[i
] = dev
;
7077 priv
= netdev_priv(dev
);
7078 priv
->adapter
= hw_priv
;
7079 priv
->id
= net_device_present
++;
7082 port
->port_cnt
= port_count
;
7083 port
->mib_port_cnt
= mib_port_count
;
7084 port
->first_port
= i
;
7085 port
->flow_ctrl
= PHY_FLOW_CTRL
;
7088 port
->linked
= &hw
->port_info
[port
->first_port
];
7090 for (cnt
= 0, pi
= i
; cnt
< port_count
; cnt
++, pi
++) {
7091 hw
->port_info
[pi
].port_id
= pi
;
7092 hw
->port_info
[pi
].pdev
= dev
;
7093 hw
->port_info
[pi
].state
= media_disconnected
;
7096 dev
->mem_start
= (unsigned long) hw
->io
;
7097 dev
->mem_end
= dev
->mem_start
+ reg_len
- 1;
7098 dev
->irq
= pdev
->irq
;
7100 memcpy(dev
->dev_addr
, hw_priv
->hw
.override_addr
,
7103 memcpy(dev
->dev_addr
, sw
->other_addr
, ETH_ALEN
);
7104 if (ether_addr_equal(sw
->other_addr
, hw
->override_addr
))
7105 dev
->dev_addr
[5] += port
->first_port
;
7108 dev
->netdev_ops
= &netdev_ops
;
7109 dev
->ethtool_ops
= &netdev_ethtool_ops
;
7110 if (register_netdev(dev
))
7111 goto pcidev_init_reg_err
;
7112 port_set_power_saving(port
, true);
7115 pci_dev_get(hw_priv
->pdev
);
7116 pci_set_drvdata(pdev
, info
);
7119 pcidev_init_reg_err
:
7120 for (i
= 0; i
< hw
->dev_count
; i
++) {
7121 if (info
->netdev
[i
]) {
7122 netdev_free(info
->netdev
[i
]);
7123 info
->netdev
[i
] = NULL
;
7127 pcidev_init_mem_err
:
7128 ksz_free_mem(hw_priv
);
7129 kfree(hw
->ksz_switch
);
7131 pcidev_init_alloc_err
:
7137 pcidev_init_dev_err
:
7138 release_mem_region(reg_base
, reg_len
);
7143 static void pcidev_exit(struct pci_dev
*pdev
)
7146 struct platform_info
*info
= pci_get_drvdata(pdev
);
7147 struct dev_info
*hw_priv
= &info
->dev_info
;
7149 release_mem_region(pci_resource_start(pdev
, 0),
7150 pci_resource_len(pdev
, 0));
7151 for (i
= 0; i
< hw_priv
->hw
.dev_count
; i
++) {
7152 if (info
->netdev
[i
])
7153 netdev_free(info
->netdev
[i
]);
7156 iounmap(hw_priv
->hw
.io
);
7157 ksz_free_mem(hw_priv
);
7158 kfree(hw_priv
->hw
.ksz_switch
);
7159 pci_dev_put(hw_priv
->pdev
);
7164 static int pcidev_resume(struct pci_dev
*pdev
)
7167 struct platform_info
*info
= pci_get_drvdata(pdev
);
7168 struct dev_info
*hw_priv
= &info
->dev_info
;
7169 struct ksz_hw
*hw
= &hw_priv
->hw
;
7171 pci_set_power_state(pdev
, PCI_D0
);
7172 pci_restore_state(pdev
);
7173 pci_enable_wake(pdev
, PCI_D0
, 0);
7175 if (hw_priv
->wol_enable
)
7176 hw_cfg_wol_pme(hw
, 0);
7177 for (i
= 0; i
< hw
->dev_count
; i
++) {
7178 if (info
->netdev
[i
]) {
7179 struct net_device
*dev
= info
->netdev
[i
];
7181 if (netif_running(dev
)) {
7183 netif_device_attach(dev
);
7190 static int pcidev_suspend(struct pci_dev
*pdev
, pm_message_t state
)
7193 struct platform_info
*info
= pci_get_drvdata(pdev
);
7194 struct dev_info
*hw_priv
= &info
->dev_info
;
7195 struct ksz_hw
*hw
= &hw_priv
->hw
;
7197 /* Need to find a way to retrieve the device IP address. */
7198 static const u8 net_addr
[] = { 192, 168, 1, 1 };
7200 for (i
= 0; i
< hw
->dev_count
; i
++) {
7201 if (info
->netdev
[i
]) {
7202 struct net_device
*dev
= info
->netdev
[i
];
7204 if (netif_running(dev
)) {
7205 netif_device_detach(dev
);
7210 if (hw_priv
->wol_enable
) {
7211 hw_enable_wol(hw
, hw_priv
->wol_enable
, net_addr
);
7212 hw_cfg_wol_pme(hw
, 1);
7215 pci_save_state(pdev
);
7216 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), 1);
7217 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
7222 static char pcidev_name
[] = "ksz884xp";
7224 static const struct pci_device_id pcidev_table
[] = {
7225 { PCI_VENDOR_ID_MICREL_KS
, 0x8841,
7226 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
7227 { PCI_VENDOR_ID_MICREL_KS
, 0x8842,
7228 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
7232 MODULE_DEVICE_TABLE(pci
, pcidev_table
);
7234 static struct pci_driver pci_device_driver
= {
7236 .suspend
= pcidev_suspend
,
7237 .resume
= pcidev_resume
,
7239 .name
= pcidev_name
,
7240 .id_table
= pcidev_table
,
7241 .probe
= pcidev_init
,
7242 .remove
= pcidev_exit
7245 module_pci_driver(pci_device_driver
);
7247 MODULE_DESCRIPTION("KSZ8841/2 PCI network driver");
7248 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@micrel.com>");
7249 MODULE_LICENSE("GPL");
7251 module_param_named(message
, msg_enable
, int, 0);
7252 MODULE_PARM_DESC(message
, "Message verbosity level (0=none, 31=all)");
7254 module_param(macaddr
, charp
, 0);
7255 module_param(mac1addr
, charp
, 0);
7256 module_param(fast_aging
, int, 0);
7257 module_param(multi_dev
, int, 0);
7258 module_param(stp
, int, 0);
7259 MODULE_PARM_DESC(macaddr
, "MAC address");
7260 MODULE_PARM_DESC(mac1addr
, "Second MAC address");
7261 MODULE_PARM_DESC(fast_aging
, "Fast aging");
7262 MODULE_PARM_DESC(multi_dev
, "Multiple device interfaces");
7263 MODULE_PARM_DESC(stp
, "STP support");