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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[deliverable/linux.git] / drivers / net / ethernet / oki-semi / pch_gbe / pch_gbe_main.c
1 /*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
4 *
5 * This code was derived from the Intel e1000e Linux driver.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include "pch_gbe.h"
22 #include "pch_gbe_api.h"
23 #include <linux/module.h>
24 #include <linux/net_tstamp.h>
25 #include <linux/ptp_classify.h>
26 #include <linux/gpio.h>
27
28 #define DRV_VERSION "1.01"
29 const char pch_driver_version[] = DRV_VERSION;
30
31 #define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
32 #define PCH_GBE_MAR_ENTRIES 16
33 #define PCH_GBE_SHORT_PKT 64
34 #define DSC_INIT16 0xC000
35 #define PCH_GBE_DMA_ALIGN 0
36 #define PCH_GBE_DMA_PADDING 2
37 #define PCH_GBE_WATCHDOG_PERIOD (5 * HZ) /* watchdog time */
38 #define PCH_GBE_COPYBREAK_DEFAULT 256
39 #define PCH_GBE_PCI_BAR 1
40 #define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */
41
42 /* Macros for ML7223 */
43 #define PCI_VENDOR_ID_ROHM 0x10db
44 #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
45
46 /* Macros for ML7831 */
47 #define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802
48
49 #define PCH_GBE_TX_WEIGHT 64
50 #define PCH_GBE_RX_WEIGHT 64
51 #define PCH_GBE_RX_BUFFER_WRITE 16
52
53 /* Initialize the wake-on-LAN settings */
54 #define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
55
56 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
57 PCH_GBE_CHIP_TYPE_INTERNAL | \
58 PCH_GBE_RGMII_MODE_RGMII \
59 )
60
61 /* Ethertype field values */
62 #define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880
63 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
64 #define PCH_GBE_FRAME_SIZE_2048 2048
65 #define PCH_GBE_FRAME_SIZE_4096 4096
66 #define PCH_GBE_FRAME_SIZE_8192 8192
67
68 #define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
69 #define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
70 #define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
71 #define PCH_GBE_DESC_UNUSED(R) \
72 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
73 (R)->next_to_clean - (R)->next_to_use - 1)
74
75 /* Pause packet value */
76 #define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
77 #define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
78 #define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
79 #define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
80
81
82 /* This defines the bits that are set in the Interrupt Mask
83 * Set/Read Register. Each bit is documented below:
84 * o RXT0 = Receiver Timer Interrupt (ring 0)
85 * o TXDW = Transmit Descriptor Written Back
86 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
87 * o RXSEQ = Receive Sequence Error
88 * o LSC = Link Status Change
89 */
90 #define PCH_GBE_INT_ENABLE_MASK ( \
91 PCH_GBE_INT_RX_DMA_CMPLT | \
92 PCH_GBE_INT_RX_DSC_EMP | \
93 PCH_GBE_INT_RX_FIFO_ERR | \
94 PCH_GBE_INT_WOL_DET | \
95 PCH_GBE_INT_TX_CMPLT \
96 )
97
98 #define PCH_GBE_INT_DISABLE_ALL 0
99
100 /* Macros for ieee1588 */
101 /* 0x40 Time Synchronization Channel Control Register Bits */
102 #define MASTER_MODE (1<<0)
103 #define SLAVE_MODE (0)
104 #define V2_MODE (1<<31)
105 #define CAP_MODE0 (0)
106 #define CAP_MODE2 (1<<17)
107
108 /* 0x44 Time Synchronization Channel Event Register Bits */
109 #define TX_SNAPSHOT_LOCKED (1<<0)
110 #define RX_SNAPSHOT_LOCKED (1<<1)
111
112 #define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81"
113 #define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00"
114
115 #define MINNOW_PHY_RESET_GPIO 13
116
117 static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
118
119 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
120 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
121 int data);
122 static void pch_gbe_set_multi(struct net_device *netdev);
123
124 static struct sock_filter ptp_filter[] = {
125 PTP_FILTER
126 };
127
128 static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
129 {
130 u8 *data = skb->data;
131 unsigned int offset;
132 u16 *hi, *id;
133 u32 lo;
134
135 if (sk_run_filter(skb, ptp_filter) == PTP_CLASS_NONE)
136 return 0;
137
138 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
139
140 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
141 return 0;
142
143 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
144 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
145
146 memcpy(&lo, &hi[1], sizeof(lo));
147
148 return (uid_hi == *hi &&
149 uid_lo == lo &&
150 seqid == *id);
151 }
152
153 static void
154 pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
155 {
156 struct skb_shared_hwtstamps *shhwtstamps;
157 struct pci_dev *pdev;
158 u64 ns;
159 u32 hi, lo, val;
160 u16 uid, seq;
161
162 if (!adapter->hwts_rx_en)
163 return;
164
165 /* Get ieee1588's dev information */
166 pdev = adapter->ptp_pdev;
167
168 val = pch_ch_event_read(pdev);
169
170 if (!(val & RX_SNAPSHOT_LOCKED))
171 return;
172
173 lo = pch_src_uuid_lo_read(pdev);
174 hi = pch_src_uuid_hi_read(pdev);
175
176 uid = hi & 0xffff;
177 seq = (hi >> 16) & 0xffff;
178
179 if (!pch_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
180 goto out;
181
182 ns = pch_rx_snap_read(pdev);
183
184 shhwtstamps = skb_hwtstamps(skb);
185 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
186 shhwtstamps->hwtstamp = ns_to_ktime(ns);
187 out:
188 pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
189 }
190
191 static void
192 pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
193 {
194 struct skb_shared_hwtstamps shhwtstamps;
195 struct pci_dev *pdev;
196 struct skb_shared_info *shtx;
197 u64 ns;
198 u32 cnt, val;
199
200 shtx = skb_shinfo(skb);
201 if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)))
202 return;
203
204 shtx->tx_flags |= SKBTX_IN_PROGRESS;
205
206 /* Get ieee1588's dev information */
207 pdev = adapter->ptp_pdev;
208
209 /*
210 * This really stinks, but we have to poll for the Tx time stamp.
211 */
212 for (cnt = 0; cnt < 100; cnt++) {
213 val = pch_ch_event_read(pdev);
214 if (val & TX_SNAPSHOT_LOCKED)
215 break;
216 udelay(1);
217 }
218 if (!(val & TX_SNAPSHOT_LOCKED)) {
219 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
220 return;
221 }
222
223 ns = pch_tx_snap_read(pdev);
224
225 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
226 shhwtstamps.hwtstamp = ns_to_ktime(ns);
227 skb_tstamp_tx(skb, &shhwtstamps);
228
229 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
230 }
231
232 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
233 {
234 struct hwtstamp_config cfg;
235 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
236 struct pci_dev *pdev;
237 u8 station[20];
238
239 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
240 return -EFAULT;
241
242 if (cfg.flags) /* reserved for future extensions */
243 return -EINVAL;
244
245 /* Get ieee1588's dev information */
246 pdev = adapter->ptp_pdev;
247
248 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
249 return -ERANGE;
250
251 switch (cfg.rx_filter) {
252 case HWTSTAMP_FILTER_NONE:
253 adapter->hwts_rx_en = 0;
254 break;
255 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
256 adapter->hwts_rx_en = 0;
257 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0);
258 break;
259 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
260 adapter->hwts_rx_en = 1;
261 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0);
262 break;
263 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
264 adapter->hwts_rx_en = 1;
265 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
266 strcpy(station, PTP_L4_MULTICAST_SA);
267 pch_set_station_address(station, pdev);
268 break;
269 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
270 adapter->hwts_rx_en = 1;
271 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
272 strcpy(station, PTP_L2_MULTICAST_SA);
273 pch_set_station_address(station, pdev);
274 break;
275 default:
276 return -ERANGE;
277 }
278
279 adapter->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
280
281 /* Clear out any old time stamps. */
282 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
283
284 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
285 }
286
287 static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
288 {
289 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
290 }
291
292 /**
293 * pch_gbe_mac_read_mac_addr - Read MAC address
294 * @hw: Pointer to the HW structure
295 * Returns:
296 * 0: Successful.
297 */
298 s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
299 {
300 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
301 u32 adr1a, adr1b;
302
303 adr1a = ioread32(&hw->reg->mac_adr[0].high);
304 adr1b = ioread32(&hw->reg->mac_adr[0].low);
305
306 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
307 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
308 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
309 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
310 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
311 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
312
313 netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr);
314 return 0;
315 }
316
317 /**
318 * pch_gbe_wait_clr_bit - Wait to clear a bit
319 * @reg: Pointer of register
320 * @busy: Busy bit
321 */
322 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
323 {
324 u32 tmp;
325
326 /* wait busy */
327 tmp = 1000;
328 while ((ioread32(reg) & bit) && --tmp)
329 cpu_relax();
330 if (!tmp)
331 pr_err("Error: busy bit is not cleared\n");
332 }
333
334 /**
335 * pch_gbe_mac_mar_set - Set MAC address register
336 * @hw: Pointer to the HW structure
337 * @addr: Pointer to the MAC address
338 * @index: MAC address array register
339 */
340 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
341 {
342 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
343 u32 mar_low, mar_high, adrmask;
344
345 netdev_dbg(adapter->netdev, "index : 0x%x\n", index);
346
347 /*
348 * HW expects these in little endian so we reverse the byte order
349 * from network order (big endian) to little endian
350 */
351 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
352 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
353 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
354 /* Stop the MAC Address of index. */
355 adrmask = ioread32(&hw->reg->ADDR_MASK);
356 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
357 /* wait busy */
358 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
359 /* Set the MAC address to the MAC address 1A/1B register */
360 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
361 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
362 /* Start the MAC address of index */
363 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
364 /* wait busy */
365 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
366 }
367
368 /**
369 * pch_gbe_mac_reset_hw - Reset hardware
370 * @hw: Pointer to the HW structure
371 */
372 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
373 {
374 /* Read the MAC address. and store to the private data */
375 pch_gbe_mac_read_mac_addr(hw);
376 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
377 #ifdef PCH_GBE_MAC_IFOP_RGMII
378 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
379 #endif
380 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
381 /* Setup the receive addresses */
382 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
383 return;
384 }
385
386 static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw)
387 {
388 u32 rctl;
389 /* Disables Receive MAC */
390 rctl = ioread32(&hw->reg->MAC_RX_EN);
391 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
392 }
393
394 static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw)
395 {
396 u32 rctl;
397 /* Enables Receive MAC */
398 rctl = ioread32(&hw->reg->MAC_RX_EN);
399 iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
400 }
401
402 /**
403 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
404 * @hw: Pointer to the HW structure
405 * @mar_count: Receive address registers
406 */
407 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
408 {
409 u32 i;
410
411 /* Setup the receive address */
412 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
413
414 /* Zero out the other receive addresses */
415 for (i = 1; i < mar_count; i++) {
416 iowrite32(0, &hw->reg->mac_adr[i].high);
417 iowrite32(0, &hw->reg->mac_adr[i].low);
418 }
419 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
420 /* wait busy */
421 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
422 }
423
424
425 /**
426 * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
427 * @hw: Pointer to the HW structure
428 * @mc_addr_list: Array of multicast addresses to program
429 * @mc_addr_count: Number of multicast addresses to program
430 * @mar_used_count: The first MAC Address register free to program
431 * @mar_total_num: Total number of supported MAC Address Registers
432 */
433 static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
434 u8 *mc_addr_list, u32 mc_addr_count,
435 u32 mar_used_count, u32 mar_total_num)
436 {
437 u32 i, adrmask;
438
439 /* Load the first set of multicast addresses into the exact
440 * filters (RAR). If there are not enough to fill the RAR
441 * array, clear the filters.
442 */
443 for (i = mar_used_count; i < mar_total_num; i++) {
444 if (mc_addr_count) {
445 pch_gbe_mac_mar_set(hw, mc_addr_list, i);
446 mc_addr_count--;
447 mc_addr_list += ETH_ALEN;
448 } else {
449 /* Clear MAC address mask */
450 adrmask = ioread32(&hw->reg->ADDR_MASK);
451 iowrite32((adrmask | (0x0001 << i)),
452 &hw->reg->ADDR_MASK);
453 /* wait busy */
454 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
455 /* Clear MAC address */
456 iowrite32(0, &hw->reg->mac_adr[i].high);
457 iowrite32(0, &hw->reg->mac_adr[i].low);
458 }
459 }
460 }
461
462 /**
463 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
464 * @hw: Pointer to the HW structure
465 * Returns:
466 * 0: Successful.
467 * Negative value: Failed.
468 */
469 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
470 {
471 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
472 struct pch_gbe_mac_info *mac = &hw->mac;
473 u32 rx_fctrl;
474
475 netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc);
476
477 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
478
479 switch (mac->fc) {
480 case PCH_GBE_FC_NONE:
481 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
482 mac->tx_fc_enable = false;
483 break;
484 case PCH_GBE_FC_RX_PAUSE:
485 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
486 mac->tx_fc_enable = false;
487 break;
488 case PCH_GBE_FC_TX_PAUSE:
489 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
490 mac->tx_fc_enable = true;
491 break;
492 case PCH_GBE_FC_FULL:
493 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
494 mac->tx_fc_enable = true;
495 break;
496 default:
497 netdev_err(adapter->netdev,
498 "Flow control param set incorrectly\n");
499 return -EINVAL;
500 }
501 if (mac->link_duplex == DUPLEX_HALF)
502 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
503 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
504 netdev_dbg(adapter->netdev,
505 "RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
506 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
507 return 0;
508 }
509
510 /**
511 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
512 * @hw: Pointer to the HW structure
513 * @wu_evt: Wake up event
514 */
515 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
516 {
517 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
518 u32 addr_mask;
519
520 netdev_dbg(adapter->netdev, "wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
521 wu_evt, ioread32(&hw->reg->ADDR_MASK));
522
523 if (wu_evt) {
524 /* Set Wake-On-Lan address mask */
525 addr_mask = ioread32(&hw->reg->ADDR_MASK);
526 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
527 /* wait busy */
528 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
529 iowrite32(0, &hw->reg->WOL_ST);
530 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
531 iowrite32(0x02, &hw->reg->TCPIP_ACC);
532 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
533 } else {
534 iowrite32(0, &hw->reg->WOL_CTRL);
535 iowrite32(0, &hw->reg->WOL_ST);
536 }
537 return;
538 }
539
540 /**
541 * pch_gbe_mac_ctrl_miim - Control MIIM interface
542 * @hw: Pointer to the HW structure
543 * @addr: Address of PHY
544 * @dir: Operetion. (Write or Read)
545 * @reg: Access register of PHY
546 * @data: Write data.
547 *
548 * Returns: Read date.
549 */
550 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
551 u16 data)
552 {
553 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
554 u32 data_out = 0;
555 unsigned int i;
556 unsigned long flags;
557
558 spin_lock_irqsave(&hw->miim_lock, flags);
559
560 for (i = 100; i; --i) {
561 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
562 break;
563 udelay(20);
564 }
565 if (i == 0) {
566 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n");
567 spin_unlock_irqrestore(&hw->miim_lock, flags);
568 return 0; /* No way to indicate timeout error */
569 }
570 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
571 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
572 dir | data), &hw->reg->MIIM);
573 for (i = 0; i < 100; i++) {
574 udelay(20);
575 data_out = ioread32(&hw->reg->MIIM);
576 if ((data_out & PCH_GBE_MIIM_OPER_READY))
577 break;
578 }
579 spin_unlock_irqrestore(&hw->miim_lock, flags);
580
581 netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n",
582 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
583 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
584 return (u16) data_out;
585 }
586
587 /**
588 * pch_gbe_mac_set_pause_packet - Set pause packet
589 * @hw: Pointer to the HW structure
590 */
591 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
592 {
593 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
594 unsigned long tmp2, tmp3;
595
596 /* Set Pause packet */
597 tmp2 = hw->mac.addr[1];
598 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
599 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
600
601 tmp3 = hw->mac.addr[5];
602 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
603 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
604 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
605
606 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
607 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
608 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
609 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
610 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
611
612 /* Transmit Pause Packet */
613 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
614
615 netdev_dbg(adapter->netdev,
616 "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
617 ioread32(&hw->reg->PAUSE_PKT1),
618 ioread32(&hw->reg->PAUSE_PKT2),
619 ioread32(&hw->reg->PAUSE_PKT3),
620 ioread32(&hw->reg->PAUSE_PKT4),
621 ioread32(&hw->reg->PAUSE_PKT5));
622
623 return;
624 }
625
626
627 /**
628 * pch_gbe_alloc_queues - Allocate memory for all rings
629 * @adapter: Board private structure to initialize
630 * Returns:
631 * 0: Successfully
632 * Negative value: Failed
633 */
634 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
635 {
636 adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev,
637 sizeof(*adapter->tx_ring), GFP_KERNEL);
638 if (!adapter->tx_ring)
639 return -ENOMEM;
640
641 adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev,
642 sizeof(*adapter->rx_ring), GFP_KERNEL);
643 if (!adapter->rx_ring)
644 return -ENOMEM;
645 return 0;
646 }
647
648 /**
649 * pch_gbe_init_stats - Initialize status
650 * @adapter: Board private structure to initialize
651 */
652 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
653 {
654 memset(&adapter->stats, 0, sizeof(adapter->stats));
655 return;
656 }
657
658 /**
659 * pch_gbe_init_phy - Initialize PHY
660 * @adapter: Board private structure to initialize
661 * Returns:
662 * 0: Successfully
663 * Negative value: Failed
664 */
665 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
666 {
667 struct net_device *netdev = adapter->netdev;
668 u32 addr;
669 u16 bmcr, stat;
670
671 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
672 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
673 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
674 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
675 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
676 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
677 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
678 break;
679 }
680 adapter->hw.phy.addr = adapter->mii.phy_id;
681 netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id);
682 if (addr == PCH_GBE_PHY_REGS_LEN)
683 return -EAGAIN;
684 /* Selected the phy and isolate the rest */
685 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
686 if (addr != adapter->mii.phy_id) {
687 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
688 BMCR_ISOLATE);
689 } else {
690 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
691 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
692 bmcr & ~BMCR_ISOLATE);
693 }
694 }
695
696 /* MII setup */
697 adapter->mii.phy_id_mask = 0x1F;
698 adapter->mii.reg_num_mask = 0x1F;
699 adapter->mii.dev = adapter->netdev;
700 adapter->mii.mdio_read = pch_gbe_mdio_read;
701 adapter->mii.mdio_write = pch_gbe_mdio_write;
702 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
703 return 0;
704 }
705
706 /**
707 * pch_gbe_mdio_read - The read function for mii
708 * @netdev: Network interface device structure
709 * @addr: Phy ID
710 * @reg: Access location
711 * Returns:
712 * 0: Successfully
713 * Negative value: Failed
714 */
715 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
716 {
717 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
718 struct pch_gbe_hw *hw = &adapter->hw;
719
720 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
721 (u16) 0);
722 }
723
724 /**
725 * pch_gbe_mdio_write - The write function for mii
726 * @netdev: Network interface device structure
727 * @addr: Phy ID (not used)
728 * @reg: Access location
729 * @data: Write data
730 */
731 static void pch_gbe_mdio_write(struct net_device *netdev,
732 int addr, int reg, int data)
733 {
734 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
735 struct pch_gbe_hw *hw = &adapter->hw;
736
737 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
738 }
739
740 /**
741 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
742 * @work: Pointer of board private structure
743 */
744 static void pch_gbe_reset_task(struct work_struct *work)
745 {
746 struct pch_gbe_adapter *adapter;
747 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
748
749 rtnl_lock();
750 pch_gbe_reinit_locked(adapter);
751 rtnl_unlock();
752 }
753
754 /**
755 * pch_gbe_reinit_locked- Re-initialization
756 * @adapter: Board private structure
757 */
758 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
759 {
760 pch_gbe_down(adapter);
761 pch_gbe_up(adapter);
762 }
763
764 /**
765 * pch_gbe_reset - Reset GbE
766 * @adapter: Board private structure
767 */
768 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
769 {
770 struct net_device *netdev = adapter->netdev;
771
772 pch_gbe_mac_reset_hw(&adapter->hw);
773 /* reprogram multicast address register after reset */
774 pch_gbe_set_multi(netdev);
775 /* Setup the receive address. */
776 pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
777 if (pch_gbe_hal_init_hw(&adapter->hw))
778 netdev_err(netdev, "Hardware Error\n");
779 }
780
781 /**
782 * pch_gbe_free_irq - Free an interrupt
783 * @adapter: Board private structure
784 */
785 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
786 {
787 struct net_device *netdev = adapter->netdev;
788
789 free_irq(adapter->pdev->irq, netdev);
790 if (adapter->have_msi) {
791 pci_disable_msi(adapter->pdev);
792 netdev_dbg(netdev, "call pci_disable_msi\n");
793 }
794 }
795
796 /**
797 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
798 * @adapter: Board private structure
799 */
800 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
801 {
802 struct pch_gbe_hw *hw = &adapter->hw;
803
804 atomic_inc(&adapter->irq_sem);
805 iowrite32(0, &hw->reg->INT_EN);
806 ioread32(&hw->reg->INT_ST);
807 synchronize_irq(adapter->pdev->irq);
808
809 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
810 ioread32(&hw->reg->INT_EN));
811 }
812
813 /**
814 * pch_gbe_irq_enable - Enable default interrupt generation settings
815 * @adapter: Board private structure
816 */
817 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
818 {
819 struct pch_gbe_hw *hw = &adapter->hw;
820
821 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
822 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
823 ioread32(&hw->reg->INT_ST);
824 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
825 ioread32(&hw->reg->INT_EN));
826 }
827
828
829
830 /**
831 * pch_gbe_setup_tctl - configure the Transmit control registers
832 * @adapter: Board private structure
833 */
834 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
835 {
836 struct pch_gbe_hw *hw = &adapter->hw;
837 u32 tx_mode, tcpip;
838
839 tx_mode = PCH_GBE_TM_LONG_PKT |
840 PCH_GBE_TM_ST_AND_FD |
841 PCH_GBE_TM_SHORT_PKT |
842 PCH_GBE_TM_TH_TX_STRT_8 |
843 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
844
845 iowrite32(tx_mode, &hw->reg->TX_MODE);
846
847 tcpip = ioread32(&hw->reg->TCPIP_ACC);
848 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
849 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
850 return;
851 }
852
853 /**
854 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
855 * @adapter: Board private structure
856 */
857 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
858 {
859 struct pch_gbe_hw *hw = &adapter->hw;
860 u32 tdba, tdlen, dctrl;
861
862 netdev_dbg(adapter->netdev, "dma addr = 0x%08llx size = 0x%08x\n",
863 (unsigned long long)adapter->tx_ring->dma,
864 adapter->tx_ring->size);
865
866 /* Setup the HW Tx Head and Tail descriptor pointers */
867 tdba = adapter->tx_ring->dma;
868 tdlen = adapter->tx_ring->size - 0x10;
869 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
870 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
871 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
872
873 /* Enables Transmission DMA */
874 dctrl = ioread32(&hw->reg->DMA_CTRL);
875 dctrl |= PCH_GBE_TX_DMA_EN;
876 iowrite32(dctrl, &hw->reg->DMA_CTRL);
877 }
878
879 /**
880 * pch_gbe_setup_rctl - Configure the receive control registers
881 * @adapter: Board private structure
882 */
883 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
884 {
885 struct pch_gbe_hw *hw = &adapter->hw;
886 u32 rx_mode, tcpip;
887
888 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
889 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
890
891 iowrite32(rx_mode, &hw->reg->RX_MODE);
892
893 tcpip = ioread32(&hw->reg->TCPIP_ACC);
894
895 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
896 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
897 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
898 return;
899 }
900
901 /**
902 * pch_gbe_configure_rx - Configure Receive Unit after Reset
903 * @adapter: Board private structure
904 */
905 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
906 {
907 struct pch_gbe_hw *hw = &adapter->hw;
908 u32 rdba, rdlen, rxdma;
909
910 netdev_dbg(adapter->netdev, "dma adr = 0x%08llx size = 0x%08x\n",
911 (unsigned long long)adapter->rx_ring->dma,
912 adapter->rx_ring->size);
913
914 pch_gbe_mac_force_mac_fc(hw);
915
916 pch_gbe_disable_mac_rx(hw);
917
918 /* Disables Receive DMA */
919 rxdma = ioread32(&hw->reg->DMA_CTRL);
920 rxdma &= ~PCH_GBE_RX_DMA_EN;
921 iowrite32(rxdma, &hw->reg->DMA_CTRL);
922
923 netdev_dbg(adapter->netdev,
924 "MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
925 ioread32(&hw->reg->MAC_RX_EN),
926 ioread32(&hw->reg->DMA_CTRL));
927
928 /* Setup the HW Rx Head and Tail Descriptor Pointers and
929 * the Base and Length of the Rx Descriptor Ring */
930 rdba = adapter->rx_ring->dma;
931 rdlen = adapter->rx_ring->size - 0x10;
932 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
933 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
934 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
935 }
936
937 /**
938 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
939 * @adapter: Board private structure
940 * @buffer_info: Buffer information structure
941 */
942 static void pch_gbe_unmap_and_free_tx_resource(
943 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
944 {
945 if (buffer_info->mapped) {
946 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
947 buffer_info->length, DMA_TO_DEVICE);
948 buffer_info->mapped = false;
949 }
950 if (buffer_info->skb) {
951 dev_kfree_skb_any(buffer_info->skb);
952 buffer_info->skb = NULL;
953 }
954 }
955
956 /**
957 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
958 * @adapter: Board private structure
959 * @buffer_info: Buffer information structure
960 */
961 static void pch_gbe_unmap_and_free_rx_resource(
962 struct pch_gbe_adapter *adapter,
963 struct pch_gbe_buffer *buffer_info)
964 {
965 if (buffer_info->mapped) {
966 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
967 buffer_info->length, DMA_FROM_DEVICE);
968 buffer_info->mapped = false;
969 }
970 if (buffer_info->skb) {
971 dev_kfree_skb_any(buffer_info->skb);
972 buffer_info->skb = NULL;
973 }
974 }
975
976 /**
977 * pch_gbe_clean_tx_ring - Free Tx Buffers
978 * @adapter: Board private structure
979 * @tx_ring: Ring to be cleaned
980 */
981 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
982 struct pch_gbe_tx_ring *tx_ring)
983 {
984 struct pch_gbe_hw *hw = &adapter->hw;
985 struct pch_gbe_buffer *buffer_info;
986 unsigned long size;
987 unsigned int i;
988
989 /* Free all the Tx ring sk_buffs */
990 for (i = 0; i < tx_ring->count; i++) {
991 buffer_info = &tx_ring->buffer_info[i];
992 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
993 }
994 netdev_dbg(adapter->netdev,
995 "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
996
997 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
998 memset(tx_ring->buffer_info, 0, size);
999
1000 /* Zero out the descriptor ring */
1001 memset(tx_ring->desc, 0, tx_ring->size);
1002 tx_ring->next_to_use = 0;
1003 tx_ring->next_to_clean = 0;
1004 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
1005 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
1006 }
1007
1008 /**
1009 * pch_gbe_clean_rx_ring - Free Rx Buffers
1010 * @adapter: Board private structure
1011 * @rx_ring: Ring to free buffers from
1012 */
1013 static void
1014 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
1015 struct pch_gbe_rx_ring *rx_ring)
1016 {
1017 struct pch_gbe_hw *hw = &adapter->hw;
1018 struct pch_gbe_buffer *buffer_info;
1019 unsigned long size;
1020 unsigned int i;
1021
1022 /* Free all the Rx ring sk_buffs */
1023 for (i = 0; i < rx_ring->count; i++) {
1024 buffer_info = &rx_ring->buffer_info[i];
1025 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
1026 }
1027 netdev_dbg(adapter->netdev,
1028 "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
1029 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1030 memset(rx_ring->buffer_info, 0, size);
1031
1032 /* Zero out the descriptor ring */
1033 memset(rx_ring->desc, 0, rx_ring->size);
1034 rx_ring->next_to_clean = 0;
1035 rx_ring->next_to_use = 0;
1036 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
1037 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
1038 }
1039
1040 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
1041 u16 duplex)
1042 {
1043 struct pch_gbe_hw *hw = &adapter->hw;
1044 unsigned long rgmii = 0;
1045
1046 /* Set the RGMII control. */
1047 #ifdef PCH_GBE_MAC_IFOP_RGMII
1048 switch (speed) {
1049 case SPEED_10:
1050 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
1051 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1052 break;
1053 case SPEED_100:
1054 rgmii = (PCH_GBE_RGMII_RATE_25M |
1055 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1056 break;
1057 case SPEED_1000:
1058 rgmii = (PCH_GBE_RGMII_RATE_125M |
1059 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1060 break;
1061 }
1062 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1063 #else /* GMII */
1064 rgmii = 0;
1065 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1066 #endif
1067 }
1068 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
1069 u16 duplex)
1070 {
1071 struct net_device *netdev = adapter->netdev;
1072 struct pch_gbe_hw *hw = &adapter->hw;
1073 unsigned long mode = 0;
1074
1075 /* Set the communication mode */
1076 switch (speed) {
1077 case SPEED_10:
1078 mode = PCH_GBE_MODE_MII_ETHER;
1079 netdev->tx_queue_len = 10;
1080 break;
1081 case SPEED_100:
1082 mode = PCH_GBE_MODE_MII_ETHER;
1083 netdev->tx_queue_len = 100;
1084 break;
1085 case SPEED_1000:
1086 mode = PCH_GBE_MODE_GMII_ETHER;
1087 break;
1088 }
1089 if (duplex == DUPLEX_FULL)
1090 mode |= PCH_GBE_MODE_FULL_DUPLEX;
1091 else
1092 mode |= PCH_GBE_MODE_HALF_DUPLEX;
1093 iowrite32(mode, &hw->reg->MODE);
1094 }
1095
1096 /**
1097 * pch_gbe_watchdog - Watchdog process
1098 * @data: Board private structure
1099 */
1100 static void pch_gbe_watchdog(unsigned long data)
1101 {
1102 struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
1103 struct net_device *netdev = adapter->netdev;
1104 struct pch_gbe_hw *hw = &adapter->hw;
1105
1106 netdev_dbg(netdev, "right now = %ld\n", jiffies);
1107
1108 pch_gbe_update_stats(adapter);
1109 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
1110 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1111 netdev->tx_queue_len = adapter->tx_queue_len;
1112 /* mii library handles link maintenance tasks */
1113 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
1114 netdev_err(netdev, "ethtool get setting Error\n");
1115 mod_timer(&adapter->watchdog_timer,
1116 round_jiffies(jiffies +
1117 PCH_GBE_WATCHDOG_PERIOD));
1118 return;
1119 }
1120 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
1121 hw->mac.link_duplex = cmd.duplex;
1122 /* Set the RGMII control. */
1123 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
1124 hw->mac.link_duplex);
1125 /* Set the communication mode */
1126 pch_gbe_set_mode(adapter, hw->mac.link_speed,
1127 hw->mac.link_duplex);
1128 netdev_dbg(netdev,
1129 "Link is Up %d Mbps %s-Duplex\n",
1130 hw->mac.link_speed,
1131 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1132 netif_carrier_on(netdev);
1133 netif_wake_queue(netdev);
1134 } else if ((!mii_link_ok(&adapter->mii)) &&
1135 (netif_carrier_ok(netdev))) {
1136 netdev_dbg(netdev, "NIC Link is Down\n");
1137 hw->mac.link_speed = SPEED_10;
1138 hw->mac.link_duplex = DUPLEX_HALF;
1139 netif_carrier_off(netdev);
1140 netif_stop_queue(netdev);
1141 }
1142 mod_timer(&adapter->watchdog_timer,
1143 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
1144 }
1145
1146 /**
1147 * pch_gbe_tx_queue - Carry out queuing of the transmission data
1148 * @adapter: Board private structure
1149 * @tx_ring: Tx descriptor ring structure
1150 * @skb: Sockt buffer structure
1151 */
1152 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
1153 struct pch_gbe_tx_ring *tx_ring,
1154 struct sk_buff *skb)
1155 {
1156 struct pch_gbe_hw *hw = &adapter->hw;
1157 struct pch_gbe_tx_desc *tx_desc;
1158 struct pch_gbe_buffer *buffer_info;
1159 struct sk_buff *tmp_skb;
1160 unsigned int frame_ctrl;
1161 unsigned int ring_num;
1162
1163 /*-- Set frame control --*/
1164 frame_ctrl = 0;
1165 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
1166 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
1167 if (skb->ip_summed == CHECKSUM_NONE)
1168 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1169
1170 /* Performs checksum processing */
1171 /*
1172 * It is because the hardware accelerator does not support a checksum,
1173 * when the received data size is less than 64 bytes.
1174 */
1175 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
1176 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
1177 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1178 if (skb->protocol == htons(ETH_P_IP)) {
1179 struct iphdr *iph = ip_hdr(skb);
1180 unsigned int offset;
1181 offset = skb_transport_offset(skb);
1182 if (iph->protocol == IPPROTO_TCP) {
1183 skb->csum = 0;
1184 tcp_hdr(skb)->check = 0;
1185 skb->csum = skb_checksum(skb, offset,
1186 skb->len - offset, 0);
1187 tcp_hdr(skb)->check =
1188 csum_tcpudp_magic(iph->saddr,
1189 iph->daddr,
1190 skb->len - offset,
1191 IPPROTO_TCP,
1192 skb->csum);
1193 } else if (iph->protocol == IPPROTO_UDP) {
1194 skb->csum = 0;
1195 udp_hdr(skb)->check = 0;
1196 skb->csum =
1197 skb_checksum(skb, offset,
1198 skb->len - offset, 0);
1199 udp_hdr(skb)->check =
1200 csum_tcpudp_magic(iph->saddr,
1201 iph->daddr,
1202 skb->len - offset,
1203 IPPROTO_UDP,
1204 skb->csum);
1205 }
1206 }
1207 }
1208
1209 ring_num = tx_ring->next_to_use;
1210 if (unlikely((ring_num + 1) == tx_ring->count))
1211 tx_ring->next_to_use = 0;
1212 else
1213 tx_ring->next_to_use = ring_num + 1;
1214
1215
1216 buffer_info = &tx_ring->buffer_info[ring_num];
1217 tmp_skb = buffer_info->skb;
1218
1219 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1220 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1221 tmp_skb->data[ETH_HLEN] = 0x00;
1222 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1223 tmp_skb->len = skb->len;
1224 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1225 (skb->len - ETH_HLEN));
1226 /*-- Set Buffer information --*/
1227 buffer_info->length = tmp_skb->len;
1228 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1229 buffer_info->length,
1230 DMA_TO_DEVICE);
1231 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1232 netdev_err(adapter->netdev, "TX DMA map failed\n");
1233 buffer_info->dma = 0;
1234 buffer_info->time_stamp = 0;
1235 tx_ring->next_to_use = ring_num;
1236 return;
1237 }
1238 buffer_info->mapped = true;
1239 buffer_info->time_stamp = jiffies;
1240
1241 /*-- Set Tx descriptor --*/
1242 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1243 tx_desc->buffer_addr = (buffer_info->dma);
1244 tx_desc->length = (tmp_skb->len);
1245 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1246 tx_desc->tx_frame_ctrl = (frame_ctrl);
1247 tx_desc->gbec_status = (DSC_INIT16);
1248
1249 if (unlikely(++ring_num == tx_ring->count))
1250 ring_num = 0;
1251
1252 /* Update software pointer of TX descriptor */
1253 iowrite32(tx_ring->dma +
1254 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1255 &hw->reg->TX_DSC_SW_P);
1256
1257 pch_tx_timestamp(adapter, skb);
1258
1259 dev_kfree_skb_any(skb);
1260 }
1261
1262 /**
1263 * pch_gbe_update_stats - Update the board statistics counters
1264 * @adapter: Board private structure
1265 */
1266 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1267 {
1268 struct net_device *netdev = adapter->netdev;
1269 struct pci_dev *pdev = adapter->pdev;
1270 struct pch_gbe_hw_stats *stats = &adapter->stats;
1271 unsigned long flags;
1272
1273 /*
1274 * Prevent stats update while adapter is being reset, or if the pci
1275 * connection is down.
1276 */
1277 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1278 return;
1279
1280 spin_lock_irqsave(&adapter->stats_lock, flags);
1281
1282 /* Update device status "adapter->stats" */
1283 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1284 stats->tx_errors = stats->tx_length_errors +
1285 stats->tx_aborted_errors +
1286 stats->tx_carrier_errors + stats->tx_timeout_count;
1287
1288 /* Update network device status "adapter->net_stats" */
1289 netdev->stats.rx_packets = stats->rx_packets;
1290 netdev->stats.rx_bytes = stats->rx_bytes;
1291 netdev->stats.rx_dropped = stats->rx_dropped;
1292 netdev->stats.tx_packets = stats->tx_packets;
1293 netdev->stats.tx_bytes = stats->tx_bytes;
1294 netdev->stats.tx_dropped = stats->tx_dropped;
1295 /* Fill out the OS statistics structure */
1296 netdev->stats.multicast = stats->multicast;
1297 netdev->stats.collisions = stats->collisions;
1298 /* Rx Errors */
1299 netdev->stats.rx_errors = stats->rx_errors;
1300 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1301 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1302 /* Tx Errors */
1303 netdev->stats.tx_errors = stats->tx_errors;
1304 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1305 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1306
1307 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1308 }
1309
1310 static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
1311 {
1312 u32 rxdma;
1313
1314 /* Disable Receive DMA */
1315 rxdma = ioread32(&hw->reg->DMA_CTRL);
1316 rxdma &= ~PCH_GBE_RX_DMA_EN;
1317 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1318 }
1319
1320 static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
1321 {
1322 u32 rxdma;
1323
1324 /* Enables Receive DMA */
1325 rxdma = ioread32(&hw->reg->DMA_CTRL);
1326 rxdma |= PCH_GBE_RX_DMA_EN;
1327 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1328 }
1329
1330 /**
1331 * pch_gbe_intr - Interrupt Handler
1332 * @irq: Interrupt number
1333 * @data: Pointer to a network interface device structure
1334 * Returns:
1335 * - IRQ_HANDLED: Our interrupt
1336 * - IRQ_NONE: Not our interrupt
1337 */
1338 static irqreturn_t pch_gbe_intr(int irq, void *data)
1339 {
1340 struct net_device *netdev = data;
1341 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1342 struct pch_gbe_hw *hw = &adapter->hw;
1343 u32 int_st;
1344 u32 int_en;
1345
1346 /* Check request status */
1347 int_st = ioread32(&hw->reg->INT_ST);
1348 int_st = int_st & ioread32(&hw->reg->INT_EN);
1349 /* When request status is no interruption factor */
1350 if (unlikely(!int_st))
1351 return IRQ_NONE; /* Not our interrupt. End processing. */
1352 netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st);
1353 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1354 adapter->stats.intr_rx_frame_err_count++;
1355 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1356 if (!adapter->rx_stop_flag) {
1357 adapter->stats.intr_rx_fifo_err_count++;
1358 netdev_dbg(netdev, "Rx fifo over run\n");
1359 adapter->rx_stop_flag = true;
1360 int_en = ioread32(&hw->reg->INT_EN);
1361 iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1362 &hw->reg->INT_EN);
1363 pch_gbe_disable_dma_rx(&adapter->hw);
1364 int_st |= ioread32(&hw->reg->INT_ST);
1365 int_st = int_st & ioread32(&hw->reg->INT_EN);
1366 }
1367 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1368 adapter->stats.intr_rx_dma_err_count++;
1369 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1370 adapter->stats.intr_tx_fifo_err_count++;
1371 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1372 adapter->stats.intr_tx_dma_err_count++;
1373 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1374 adapter->stats.intr_tcpip_err_count++;
1375 /* When Rx descriptor is empty */
1376 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1377 adapter->stats.intr_rx_dsc_empty_count++;
1378 netdev_dbg(netdev, "Rx descriptor is empty\n");
1379 int_en = ioread32(&hw->reg->INT_EN);
1380 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1381 if (hw->mac.tx_fc_enable) {
1382 /* Set Pause packet */
1383 pch_gbe_mac_set_pause_packet(hw);
1384 }
1385 }
1386
1387 /* When request status is Receive interruption */
1388 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
1389 (adapter->rx_stop_flag)) {
1390 if (likely(napi_schedule_prep(&adapter->napi))) {
1391 /* Enable only Rx Descriptor empty */
1392 atomic_inc(&adapter->irq_sem);
1393 int_en = ioread32(&hw->reg->INT_EN);
1394 int_en &=
1395 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1396 iowrite32(int_en, &hw->reg->INT_EN);
1397 /* Start polling for NAPI */
1398 __napi_schedule(&adapter->napi);
1399 }
1400 }
1401 netdev_dbg(netdev, "return = 0x%08x INT_EN reg = 0x%08x\n",
1402 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1403 return IRQ_HANDLED;
1404 }
1405
1406 /**
1407 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1408 * @adapter: Board private structure
1409 * @rx_ring: Rx descriptor ring
1410 * @cleaned_count: Cleaned count
1411 */
1412 static void
1413 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1414 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1415 {
1416 struct net_device *netdev = adapter->netdev;
1417 struct pci_dev *pdev = adapter->pdev;
1418 struct pch_gbe_hw *hw = &adapter->hw;
1419 struct pch_gbe_rx_desc *rx_desc;
1420 struct pch_gbe_buffer *buffer_info;
1421 struct sk_buff *skb;
1422 unsigned int i;
1423 unsigned int bufsz;
1424
1425 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1426 i = rx_ring->next_to_use;
1427
1428 while ((cleaned_count--)) {
1429 buffer_info = &rx_ring->buffer_info[i];
1430 skb = netdev_alloc_skb(netdev, bufsz);
1431 if (unlikely(!skb)) {
1432 /* Better luck next round */
1433 adapter->stats.rx_alloc_buff_failed++;
1434 break;
1435 }
1436 /* align */
1437 skb_reserve(skb, NET_IP_ALIGN);
1438 buffer_info->skb = skb;
1439
1440 buffer_info->dma = dma_map_single(&pdev->dev,
1441 buffer_info->rx_buffer,
1442 buffer_info->length,
1443 DMA_FROM_DEVICE);
1444 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1445 dev_kfree_skb(skb);
1446 buffer_info->skb = NULL;
1447 buffer_info->dma = 0;
1448 adapter->stats.rx_alloc_buff_failed++;
1449 break; /* while !buffer_info->skb */
1450 }
1451 buffer_info->mapped = true;
1452 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1453 rx_desc->buffer_addr = (buffer_info->dma);
1454 rx_desc->gbec_status = DSC_INIT16;
1455
1456 netdev_dbg(netdev,
1457 "i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1458 i, (unsigned long long)buffer_info->dma,
1459 buffer_info->length);
1460
1461 if (unlikely(++i == rx_ring->count))
1462 i = 0;
1463 }
1464 if (likely(rx_ring->next_to_use != i)) {
1465 rx_ring->next_to_use = i;
1466 if (unlikely(i-- == 0))
1467 i = (rx_ring->count - 1);
1468 iowrite32(rx_ring->dma +
1469 (int)sizeof(struct pch_gbe_rx_desc) * i,
1470 &hw->reg->RX_DSC_SW_P);
1471 }
1472 return;
1473 }
1474
1475 static int
1476 pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1477 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1478 {
1479 struct pci_dev *pdev = adapter->pdev;
1480 struct pch_gbe_buffer *buffer_info;
1481 unsigned int i;
1482 unsigned int bufsz;
1483 unsigned int size;
1484
1485 bufsz = adapter->rx_buffer_len;
1486
1487 size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1488 rx_ring->rx_buff_pool =
1489 dma_zalloc_coherent(&pdev->dev, size,
1490 &rx_ring->rx_buff_pool_logic, GFP_KERNEL);
1491 if (!rx_ring->rx_buff_pool)
1492 return -ENOMEM;
1493
1494 rx_ring->rx_buff_pool_size = size;
1495 for (i = 0; i < rx_ring->count; i++) {
1496 buffer_info = &rx_ring->buffer_info[i];
1497 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1498 buffer_info->length = bufsz;
1499 }
1500 return 0;
1501 }
1502
1503 /**
1504 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1505 * @adapter: Board private structure
1506 * @tx_ring: Tx descriptor ring
1507 */
1508 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1509 struct pch_gbe_tx_ring *tx_ring)
1510 {
1511 struct pch_gbe_buffer *buffer_info;
1512 struct sk_buff *skb;
1513 unsigned int i;
1514 unsigned int bufsz;
1515 struct pch_gbe_tx_desc *tx_desc;
1516
1517 bufsz =
1518 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1519
1520 for (i = 0; i < tx_ring->count; i++) {
1521 buffer_info = &tx_ring->buffer_info[i];
1522 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1523 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1524 buffer_info->skb = skb;
1525 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1526 tx_desc->gbec_status = (DSC_INIT16);
1527 }
1528 return;
1529 }
1530
1531 /**
1532 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1533 * @adapter: Board private structure
1534 * @tx_ring: Tx descriptor ring
1535 * Returns:
1536 * true: Cleaned the descriptor
1537 * false: Not cleaned the descriptor
1538 */
1539 static bool
1540 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1541 struct pch_gbe_tx_ring *tx_ring)
1542 {
1543 struct pch_gbe_tx_desc *tx_desc;
1544 struct pch_gbe_buffer *buffer_info;
1545 struct sk_buff *skb;
1546 unsigned int i;
1547 unsigned int cleaned_count = 0;
1548 bool cleaned = false;
1549 int unused, thresh;
1550
1551 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1552 tx_ring->next_to_clean);
1553
1554 i = tx_ring->next_to_clean;
1555 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1556 netdev_dbg(adapter->netdev, "gbec_status:0x%04x dma_status:0x%04x\n",
1557 tx_desc->gbec_status, tx_desc->dma_status);
1558
1559 unused = PCH_GBE_DESC_UNUSED(tx_ring);
1560 thresh = tx_ring->count - PCH_GBE_TX_WEIGHT;
1561 if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh))
1562 { /* current marked clean, tx queue filling up, do extra clean */
1563 int j, k;
1564 if (unused < 8) { /* tx queue nearly full */
1565 netdev_dbg(adapter->netdev,
1566 "clean_tx: transmit queue warning (%x,%x) unused=%d\n",
1567 tx_ring->next_to_clean, tx_ring->next_to_use,
1568 unused);
1569 }
1570
1571 /* current marked clean, scan for more that need cleaning. */
1572 k = i;
1573 for (j = 0; j < PCH_GBE_TX_WEIGHT; j++)
1574 {
1575 tx_desc = PCH_GBE_TX_DESC(*tx_ring, k);
1576 if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/
1577 if (++k >= tx_ring->count) k = 0; /*increment, wrap*/
1578 }
1579 if (j < PCH_GBE_TX_WEIGHT) {
1580 netdev_dbg(adapter->netdev,
1581 "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n",
1582 unused, j, i, k, tx_ring->next_to_use,
1583 tx_desc->gbec_status);
1584 i = k; /*found one to clean, usu gbec_status==2000.*/
1585 }
1586 }
1587
1588 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1589 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n",
1590 tx_desc->gbec_status);
1591 buffer_info = &tx_ring->buffer_info[i];
1592 skb = buffer_info->skb;
1593 cleaned = true;
1594
1595 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1596 adapter->stats.tx_aborted_errors++;
1597 netdev_err(adapter->netdev, "Transfer Abort Error\n");
1598 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1599 ) {
1600 adapter->stats.tx_carrier_errors++;
1601 netdev_err(adapter->netdev,
1602 "Transfer Carrier Sense Error\n");
1603 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1604 ) {
1605 adapter->stats.tx_aborted_errors++;
1606 netdev_err(adapter->netdev,
1607 "Transfer Collision Abort Error\n");
1608 } else if ((tx_desc->gbec_status &
1609 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1610 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1611 adapter->stats.collisions++;
1612 adapter->stats.tx_packets++;
1613 adapter->stats.tx_bytes += skb->len;
1614 netdev_dbg(adapter->netdev, "Transfer Collision\n");
1615 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1616 ) {
1617 adapter->stats.tx_packets++;
1618 adapter->stats.tx_bytes += skb->len;
1619 }
1620 if (buffer_info->mapped) {
1621 netdev_dbg(adapter->netdev,
1622 "unmap buffer_info->dma : %d\n", i);
1623 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1624 buffer_info->length, DMA_TO_DEVICE);
1625 buffer_info->mapped = false;
1626 }
1627 if (buffer_info->skb) {
1628 netdev_dbg(adapter->netdev,
1629 "trim buffer_info->skb : %d\n", i);
1630 skb_trim(buffer_info->skb, 0);
1631 }
1632 tx_desc->gbec_status = DSC_INIT16;
1633 if (unlikely(++i == tx_ring->count))
1634 i = 0;
1635 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1636
1637 /* weight of a sort for tx, to avoid endless transmit cleanup */
1638 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1639 cleaned = false;
1640 break;
1641 }
1642 }
1643 netdev_dbg(adapter->netdev,
1644 "called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1645 cleaned_count);
1646 if (cleaned_count > 0) { /*skip this if nothing cleaned*/
1647 /* Recover from running out of Tx resources in xmit_frame */
1648 spin_lock(&tx_ring->tx_lock);
1649 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev))))
1650 {
1651 netif_wake_queue(adapter->netdev);
1652 adapter->stats.tx_restart_count++;
1653 netdev_dbg(adapter->netdev, "Tx wake queue\n");
1654 }
1655
1656 tx_ring->next_to_clean = i;
1657
1658 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1659 tx_ring->next_to_clean);
1660 spin_unlock(&tx_ring->tx_lock);
1661 }
1662 return cleaned;
1663 }
1664
1665 /**
1666 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1667 * @adapter: Board private structure
1668 * @rx_ring: Rx descriptor ring
1669 * @work_done: Completed count
1670 * @work_to_do: Request count
1671 * Returns:
1672 * true: Cleaned the descriptor
1673 * false: Not cleaned the descriptor
1674 */
1675 static bool
1676 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1677 struct pch_gbe_rx_ring *rx_ring,
1678 int *work_done, int work_to_do)
1679 {
1680 struct net_device *netdev = adapter->netdev;
1681 struct pci_dev *pdev = adapter->pdev;
1682 struct pch_gbe_buffer *buffer_info;
1683 struct pch_gbe_rx_desc *rx_desc;
1684 u32 length;
1685 unsigned int i;
1686 unsigned int cleaned_count = 0;
1687 bool cleaned = false;
1688 struct sk_buff *skb;
1689 u8 dma_status;
1690 u16 gbec_status;
1691 u32 tcp_ip_status;
1692
1693 i = rx_ring->next_to_clean;
1694
1695 while (*work_done < work_to_do) {
1696 /* Check Rx descriptor status */
1697 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1698 if (rx_desc->gbec_status == DSC_INIT16)
1699 break;
1700 cleaned = true;
1701 cleaned_count++;
1702
1703 dma_status = rx_desc->dma_status;
1704 gbec_status = rx_desc->gbec_status;
1705 tcp_ip_status = rx_desc->tcp_ip_status;
1706 rx_desc->gbec_status = DSC_INIT16;
1707 buffer_info = &rx_ring->buffer_info[i];
1708 skb = buffer_info->skb;
1709 buffer_info->skb = NULL;
1710
1711 /* unmap dma */
1712 dma_unmap_single(&pdev->dev, buffer_info->dma,
1713 buffer_info->length, DMA_FROM_DEVICE);
1714 buffer_info->mapped = false;
1715
1716 netdev_dbg(netdev,
1717 "RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x] BufInf = 0x%p\n",
1718 i, dma_status, gbec_status, tcp_ip_status,
1719 buffer_info);
1720 /* Error check */
1721 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1722 adapter->stats.rx_frame_errors++;
1723 netdev_err(netdev, "Receive Not Octal Error\n");
1724 } else if (unlikely(gbec_status &
1725 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1726 adapter->stats.rx_frame_errors++;
1727 netdev_err(netdev, "Receive Nibble Error\n");
1728 } else if (unlikely(gbec_status &
1729 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1730 adapter->stats.rx_crc_errors++;
1731 netdev_err(netdev, "Receive CRC Error\n");
1732 } else {
1733 /* get receive length */
1734 /* length convert[-3], length includes FCS length */
1735 length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1736 if (rx_desc->rx_words_eob & 0x02)
1737 length = length - 4;
1738 /*
1739 * buffer_info->rx_buffer: [Header:14][payload]
1740 * skb->data: [Reserve:2][Header:14][payload]
1741 */
1742 memcpy(skb->data, buffer_info->rx_buffer, length);
1743
1744 /* update status of driver */
1745 adapter->stats.rx_bytes += length;
1746 adapter->stats.rx_packets++;
1747 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1748 adapter->stats.multicast++;
1749 /* Write meta date of skb */
1750 skb_put(skb, length);
1751
1752 pch_rx_timestamp(adapter, skb);
1753
1754 skb->protocol = eth_type_trans(skb, netdev);
1755 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1756 skb->ip_summed = CHECKSUM_UNNECESSARY;
1757 else
1758 skb->ip_summed = CHECKSUM_NONE;
1759
1760 napi_gro_receive(&adapter->napi, skb);
1761 (*work_done)++;
1762 netdev_dbg(netdev,
1763 "Receive skb->ip_summed: %d length: %d\n",
1764 skb->ip_summed, length);
1765 }
1766 /* return some buffers to hardware, one at a time is too slow */
1767 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1768 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1769 cleaned_count);
1770 cleaned_count = 0;
1771 }
1772 if (++i == rx_ring->count)
1773 i = 0;
1774 }
1775 rx_ring->next_to_clean = i;
1776 if (cleaned_count)
1777 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1778 return cleaned;
1779 }
1780
1781 /**
1782 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1783 * @adapter: Board private structure
1784 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
1785 * Returns:
1786 * 0: Successfully
1787 * Negative value: Failed
1788 */
1789 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1790 struct pch_gbe_tx_ring *tx_ring)
1791 {
1792 struct pci_dev *pdev = adapter->pdev;
1793 struct pch_gbe_tx_desc *tx_desc;
1794 int size;
1795 int desNo;
1796
1797 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1798 tx_ring->buffer_info = vzalloc(size);
1799 if (!tx_ring->buffer_info)
1800 return -ENOMEM;
1801
1802 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1803
1804 tx_ring->desc = dma_zalloc_coherent(&pdev->dev, tx_ring->size,
1805 &tx_ring->dma, GFP_KERNEL);
1806 if (!tx_ring->desc) {
1807 vfree(tx_ring->buffer_info);
1808 return -ENOMEM;
1809 }
1810
1811 tx_ring->next_to_use = 0;
1812 tx_ring->next_to_clean = 0;
1813 spin_lock_init(&tx_ring->tx_lock);
1814
1815 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1816 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1817 tx_desc->gbec_status = DSC_INIT16;
1818 }
1819 netdev_dbg(adapter->netdev,
1820 "tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1821 tx_ring->desc, (unsigned long long)tx_ring->dma,
1822 tx_ring->next_to_clean, tx_ring->next_to_use);
1823 return 0;
1824 }
1825
1826 /**
1827 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1828 * @adapter: Board private structure
1829 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1830 * Returns:
1831 * 0: Successfully
1832 * Negative value: Failed
1833 */
1834 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1835 struct pch_gbe_rx_ring *rx_ring)
1836 {
1837 struct pci_dev *pdev = adapter->pdev;
1838 struct pch_gbe_rx_desc *rx_desc;
1839 int size;
1840 int desNo;
1841
1842 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1843 rx_ring->buffer_info = vzalloc(size);
1844 if (!rx_ring->buffer_info)
1845 return -ENOMEM;
1846
1847 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1848 rx_ring->desc = dma_zalloc_coherent(&pdev->dev, rx_ring->size,
1849 &rx_ring->dma, GFP_KERNEL);
1850 if (!rx_ring->desc) {
1851 vfree(rx_ring->buffer_info);
1852 return -ENOMEM;
1853 }
1854 rx_ring->next_to_clean = 0;
1855 rx_ring->next_to_use = 0;
1856 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1857 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1858 rx_desc->gbec_status = DSC_INIT16;
1859 }
1860 netdev_dbg(adapter->netdev,
1861 "rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1862 rx_ring->desc, (unsigned long long)rx_ring->dma,
1863 rx_ring->next_to_clean, rx_ring->next_to_use);
1864 return 0;
1865 }
1866
1867 /**
1868 * pch_gbe_free_tx_resources - Free Tx Resources
1869 * @adapter: Board private structure
1870 * @tx_ring: Tx descriptor ring for a specific queue
1871 */
1872 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1873 struct pch_gbe_tx_ring *tx_ring)
1874 {
1875 struct pci_dev *pdev = adapter->pdev;
1876
1877 pch_gbe_clean_tx_ring(adapter, tx_ring);
1878 vfree(tx_ring->buffer_info);
1879 tx_ring->buffer_info = NULL;
1880 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1881 tx_ring->desc = NULL;
1882 }
1883
1884 /**
1885 * pch_gbe_free_rx_resources - Free Rx Resources
1886 * @adapter: Board private structure
1887 * @rx_ring: Ring to clean the resources from
1888 */
1889 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1890 struct pch_gbe_rx_ring *rx_ring)
1891 {
1892 struct pci_dev *pdev = adapter->pdev;
1893
1894 pch_gbe_clean_rx_ring(adapter, rx_ring);
1895 vfree(rx_ring->buffer_info);
1896 rx_ring->buffer_info = NULL;
1897 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1898 rx_ring->desc = NULL;
1899 }
1900
1901 /**
1902 * pch_gbe_request_irq - Allocate an interrupt line
1903 * @adapter: Board private structure
1904 * Returns:
1905 * 0: Successfully
1906 * Negative value: Failed
1907 */
1908 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1909 {
1910 struct net_device *netdev = adapter->netdev;
1911 int err;
1912 int flags;
1913
1914 flags = IRQF_SHARED;
1915 adapter->have_msi = false;
1916 err = pci_enable_msi(adapter->pdev);
1917 netdev_dbg(netdev, "call pci_enable_msi\n");
1918 if (err) {
1919 netdev_dbg(netdev, "call pci_enable_msi - Error: %d\n", err);
1920 } else {
1921 flags = 0;
1922 adapter->have_msi = true;
1923 }
1924 err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1925 flags, netdev->name, netdev);
1926 if (err)
1927 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n",
1928 err);
1929 netdev_dbg(netdev,
1930 "adapter->have_msi : %d flags : 0x%04x return : 0x%04x\n",
1931 adapter->have_msi, flags, err);
1932 return err;
1933 }
1934
1935
1936 /**
1937 * pch_gbe_up - Up GbE network device
1938 * @adapter: Board private structure
1939 * Returns:
1940 * 0: Successfully
1941 * Negative value: Failed
1942 */
1943 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1944 {
1945 struct net_device *netdev = adapter->netdev;
1946 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1947 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1948 int err = -EINVAL;
1949
1950 /* Ensure we have a valid MAC */
1951 if (!is_valid_ether_addr(adapter->hw.mac.addr)) {
1952 netdev_err(netdev, "Error: Invalid MAC address\n");
1953 goto out;
1954 }
1955
1956 /* hardware has been reset, we need to reload some things */
1957 pch_gbe_set_multi(netdev);
1958
1959 pch_gbe_setup_tctl(adapter);
1960 pch_gbe_configure_tx(adapter);
1961 pch_gbe_setup_rctl(adapter);
1962 pch_gbe_configure_rx(adapter);
1963
1964 err = pch_gbe_request_irq(adapter);
1965 if (err) {
1966 netdev_err(netdev,
1967 "Error: can't bring device up - irq request failed\n");
1968 goto out;
1969 }
1970 err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1971 if (err) {
1972 netdev_err(netdev,
1973 "Error: can't bring device up - alloc rx buffers pool failed\n");
1974 goto freeirq;
1975 }
1976 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1977 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1978 adapter->tx_queue_len = netdev->tx_queue_len;
1979 pch_gbe_enable_dma_rx(&adapter->hw);
1980 pch_gbe_enable_mac_rx(&adapter->hw);
1981
1982 mod_timer(&adapter->watchdog_timer, jiffies);
1983
1984 napi_enable(&adapter->napi);
1985 pch_gbe_irq_enable(adapter);
1986 netif_start_queue(adapter->netdev);
1987
1988 return 0;
1989
1990 freeirq:
1991 pch_gbe_free_irq(adapter);
1992 out:
1993 return err;
1994 }
1995
1996 /**
1997 * pch_gbe_down - Down GbE network device
1998 * @adapter: Board private structure
1999 */
2000 void pch_gbe_down(struct pch_gbe_adapter *adapter)
2001 {
2002 struct net_device *netdev = adapter->netdev;
2003 struct pci_dev *pdev = adapter->pdev;
2004 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
2005
2006 /* signal that we're down so the interrupt handler does not
2007 * reschedule our watchdog timer */
2008 napi_disable(&adapter->napi);
2009 atomic_set(&adapter->irq_sem, 0);
2010
2011 pch_gbe_irq_disable(adapter);
2012 pch_gbe_free_irq(adapter);
2013
2014 del_timer_sync(&adapter->watchdog_timer);
2015
2016 netdev->tx_queue_len = adapter->tx_queue_len;
2017 netif_carrier_off(netdev);
2018 netif_stop_queue(netdev);
2019
2020 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
2021 pch_gbe_reset(adapter);
2022 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
2023 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
2024
2025 pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
2026 rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
2027 rx_ring->rx_buff_pool_logic = 0;
2028 rx_ring->rx_buff_pool_size = 0;
2029 rx_ring->rx_buff_pool = NULL;
2030 }
2031
2032 /**
2033 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
2034 * @adapter: Board private structure to initialize
2035 * Returns:
2036 * 0: Successfully
2037 * Negative value: Failed
2038 */
2039 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
2040 {
2041 struct pch_gbe_hw *hw = &adapter->hw;
2042 struct net_device *netdev = adapter->netdev;
2043
2044 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2045 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2046 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2047
2048 /* Initialize the hardware-specific values */
2049 if (pch_gbe_hal_setup_init_funcs(hw)) {
2050 netdev_err(netdev, "Hardware Initialization Failure\n");
2051 return -EIO;
2052 }
2053 if (pch_gbe_alloc_queues(adapter)) {
2054 netdev_err(netdev, "Unable to allocate memory for queues\n");
2055 return -ENOMEM;
2056 }
2057 spin_lock_init(&adapter->hw.miim_lock);
2058 spin_lock_init(&adapter->stats_lock);
2059 spin_lock_init(&adapter->ethtool_lock);
2060 atomic_set(&adapter->irq_sem, 0);
2061 pch_gbe_irq_disable(adapter);
2062
2063 pch_gbe_init_stats(adapter);
2064
2065 netdev_dbg(netdev,
2066 "rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
2067 (u32) adapter->rx_buffer_len,
2068 hw->mac.min_frame_size, hw->mac.max_frame_size);
2069 return 0;
2070 }
2071
2072 /**
2073 * pch_gbe_open - Called when a network interface is made active
2074 * @netdev: Network interface device structure
2075 * Returns:
2076 * 0: Successfully
2077 * Negative value: Failed
2078 */
2079 static int pch_gbe_open(struct net_device *netdev)
2080 {
2081 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2082 struct pch_gbe_hw *hw = &adapter->hw;
2083 int err;
2084
2085 /* allocate transmit descriptors */
2086 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
2087 if (err)
2088 goto err_setup_tx;
2089 /* allocate receive descriptors */
2090 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
2091 if (err)
2092 goto err_setup_rx;
2093 pch_gbe_hal_power_up_phy(hw);
2094 err = pch_gbe_up(adapter);
2095 if (err)
2096 goto err_up;
2097 netdev_dbg(netdev, "Success End\n");
2098 return 0;
2099
2100 err_up:
2101 if (!adapter->wake_up_evt)
2102 pch_gbe_hal_power_down_phy(hw);
2103 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2104 err_setup_rx:
2105 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2106 err_setup_tx:
2107 pch_gbe_reset(adapter);
2108 netdev_err(netdev, "Error End\n");
2109 return err;
2110 }
2111
2112 /**
2113 * pch_gbe_stop - Disables a network interface
2114 * @netdev: Network interface device structure
2115 * Returns:
2116 * 0: Successfully
2117 */
2118 static int pch_gbe_stop(struct net_device *netdev)
2119 {
2120 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2121 struct pch_gbe_hw *hw = &adapter->hw;
2122
2123 pch_gbe_down(adapter);
2124 if (!adapter->wake_up_evt)
2125 pch_gbe_hal_power_down_phy(hw);
2126 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2127 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2128 return 0;
2129 }
2130
2131 /**
2132 * pch_gbe_xmit_frame - Packet transmitting start
2133 * @skb: Socket buffer structure
2134 * @netdev: Network interface device structure
2135 * Returns:
2136 * - NETDEV_TX_OK: Normal end
2137 * - NETDEV_TX_BUSY: Error end
2138 */
2139 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2140 {
2141 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2142 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
2143 unsigned long flags;
2144
2145 if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
2146 /* Collision - tell upper layer to requeue */
2147 return NETDEV_TX_LOCKED;
2148 }
2149 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
2150 netif_stop_queue(netdev);
2151 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
2152 netdev_dbg(netdev,
2153 "Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
2154 tx_ring->next_to_use, tx_ring->next_to_clean);
2155 return NETDEV_TX_BUSY;
2156 }
2157
2158 /* CRC,ITAG no support */
2159 pch_gbe_tx_queue(adapter, tx_ring, skb);
2160 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
2161 return NETDEV_TX_OK;
2162 }
2163
2164 /**
2165 * pch_gbe_get_stats - Get System Network Statistics
2166 * @netdev: Network interface device structure
2167 * Returns: The current stats
2168 */
2169 static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
2170 {
2171 /* only return the current stats */
2172 return &netdev->stats;
2173 }
2174
2175 /**
2176 * pch_gbe_set_multi - Multicast and Promiscuous mode set
2177 * @netdev: Network interface device structure
2178 */
2179 static void pch_gbe_set_multi(struct net_device *netdev)
2180 {
2181 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2182 struct pch_gbe_hw *hw = &adapter->hw;
2183 struct netdev_hw_addr *ha;
2184 u8 *mta_list;
2185 u32 rctl;
2186 int i;
2187 int mc_count;
2188
2189 netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
2190
2191 /* Check for Promiscuous and All Multicast modes */
2192 rctl = ioread32(&hw->reg->RX_MODE);
2193 mc_count = netdev_mc_count(netdev);
2194 if ((netdev->flags & IFF_PROMISC)) {
2195 rctl &= ~PCH_GBE_ADD_FIL_EN;
2196 rctl &= ~PCH_GBE_MLT_FIL_EN;
2197 } else if ((netdev->flags & IFF_ALLMULTI)) {
2198 /* all the multicasting receive permissions */
2199 rctl |= PCH_GBE_ADD_FIL_EN;
2200 rctl &= ~PCH_GBE_MLT_FIL_EN;
2201 } else {
2202 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
2203 /* all the multicasting receive permissions */
2204 rctl |= PCH_GBE_ADD_FIL_EN;
2205 rctl &= ~PCH_GBE_MLT_FIL_EN;
2206 } else {
2207 rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
2208 }
2209 }
2210 iowrite32(rctl, &hw->reg->RX_MODE);
2211
2212 if (mc_count >= PCH_GBE_MAR_ENTRIES)
2213 return;
2214 mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
2215 if (!mta_list)
2216 return;
2217
2218 /* The shared function expects a packed array of only addresses. */
2219 i = 0;
2220 netdev_for_each_mc_addr(ha, netdev) {
2221 if (i == mc_count)
2222 break;
2223 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
2224 }
2225 pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
2226 PCH_GBE_MAR_ENTRIES);
2227 kfree(mta_list);
2228
2229 netdev_dbg(netdev,
2230 "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
2231 ioread32(&hw->reg->RX_MODE), mc_count);
2232 }
2233
2234 /**
2235 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2236 * @netdev: Network interface device structure
2237 * @addr: Pointer to an address structure
2238 * Returns:
2239 * 0: Successfully
2240 * -EADDRNOTAVAIL: Failed
2241 */
2242 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2243 {
2244 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2245 struct sockaddr *skaddr = addr;
2246 int ret_val;
2247
2248 if (!is_valid_ether_addr(skaddr->sa_data)) {
2249 ret_val = -EADDRNOTAVAIL;
2250 } else {
2251 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2252 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2253 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2254 ret_val = 0;
2255 }
2256 netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val);
2257 netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr);
2258 netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr);
2259 netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2260 ioread32(&adapter->hw.reg->mac_adr[0].high),
2261 ioread32(&adapter->hw.reg->mac_adr[0].low));
2262 return ret_val;
2263 }
2264
2265 /**
2266 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2267 * @netdev: Network interface device structure
2268 * @new_mtu: New value for maximum frame size
2269 * Returns:
2270 * 0: Successfully
2271 * -EINVAL: Failed
2272 */
2273 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2274 {
2275 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2276 int max_frame;
2277 unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2278 int err;
2279
2280 max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2281 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2282 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2283 netdev_err(netdev, "Invalid MTU setting\n");
2284 return -EINVAL;
2285 }
2286 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2287 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2288 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2289 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2290 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2291 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2292 else
2293 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
2294
2295 if (netif_running(netdev)) {
2296 pch_gbe_down(adapter);
2297 err = pch_gbe_up(adapter);
2298 if (err) {
2299 adapter->rx_buffer_len = old_rx_buffer_len;
2300 pch_gbe_up(adapter);
2301 return err;
2302 } else {
2303 netdev->mtu = new_mtu;
2304 adapter->hw.mac.max_frame_size = max_frame;
2305 }
2306 } else {
2307 pch_gbe_reset(adapter);
2308 netdev->mtu = new_mtu;
2309 adapter->hw.mac.max_frame_size = max_frame;
2310 }
2311
2312 netdev_dbg(netdev,
2313 "max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2314 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2315 adapter->hw.mac.max_frame_size);
2316 return 0;
2317 }
2318
2319 /**
2320 * pch_gbe_set_features - Reset device after features changed
2321 * @netdev: Network interface device structure
2322 * @features: New features
2323 * Returns:
2324 * 0: HW state updated successfully
2325 */
2326 static int pch_gbe_set_features(struct net_device *netdev,
2327 netdev_features_t features)
2328 {
2329 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2330 netdev_features_t changed = features ^ netdev->features;
2331
2332 if (!(changed & NETIF_F_RXCSUM))
2333 return 0;
2334
2335 if (netif_running(netdev))
2336 pch_gbe_reinit_locked(adapter);
2337 else
2338 pch_gbe_reset(adapter);
2339
2340 return 0;
2341 }
2342
2343 /**
2344 * pch_gbe_ioctl - Controls register through a MII interface
2345 * @netdev: Network interface device structure
2346 * @ifr: Pointer to ifr structure
2347 * @cmd: Control command
2348 * Returns:
2349 * 0: Successfully
2350 * Negative value: Failed
2351 */
2352 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2353 {
2354 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2355
2356 netdev_dbg(netdev, "cmd : 0x%04x\n", cmd);
2357
2358 if (cmd == SIOCSHWTSTAMP)
2359 return hwtstamp_ioctl(netdev, ifr, cmd);
2360
2361 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2362 }
2363
2364 /**
2365 * pch_gbe_tx_timeout - Respond to a Tx Hang
2366 * @netdev: Network interface device structure
2367 */
2368 static void pch_gbe_tx_timeout(struct net_device *netdev)
2369 {
2370 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2371
2372 /* Do the reset outside of interrupt context */
2373 adapter->stats.tx_timeout_count++;
2374 schedule_work(&adapter->reset_task);
2375 }
2376
2377 /**
2378 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2379 * @napi: Pointer of polling device struct
2380 * @budget: The maximum number of a packet
2381 * Returns:
2382 * false: Exit the polling mode
2383 * true: Continue the polling mode
2384 */
2385 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2386 {
2387 struct pch_gbe_adapter *adapter =
2388 container_of(napi, struct pch_gbe_adapter, napi);
2389 int work_done = 0;
2390 bool poll_end_flag = false;
2391 bool cleaned = false;
2392
2393 netdev_dbg(adapter->netdev, "budget : %d\n", budget);
2394
2395 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2396 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2397
2398 if (cleaned)
2399 work_done = budget;
2400 /* If no Tx and not enough Rx work done,
2401 * exit the polling mode
2402 */
2403 if (work_done < budget)
2404 poll_end_flag = true;
2405
2406 if (poll_end_flag) {
2407 napi_complete(napi);
2408 pch_gbe_irq_enable(adapter);
2409 }
2410
2411 if (adapter->rx_stop_flag) {
2412 adapter->rx_stop_flag = false;
2413 pch_gbe_enable_dma_rx(&adapter->hw);
2414 }
2415
2416 netdev_dbg(adapter->netdev,
2417 "poll_end_flag : %d work_done : %d budget : %d\n",
2418 poll_end_flag, work_done, budget);
2419
2420 return work_done;
2421 }
2422
2423 #ifdef CONFIG_NET_POLL_CONTROLLER
2424 /**
2425 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2426 * @netdev: Network interface device structure
2427 */
2428 static void pch_gbe_netpoll(struct net_device *netdev)
2429 {
2430 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2431
2432 disable_irq(adapter->pdev->irq);
2433 pch_gbe_intr(adapter->pdev->irq, netdev);
2434 enable_irq(adapter->pdev->irq);
2435 }
2436 #endif
2437
2438 static const struct net_device_ops pch_gbe_netdev_ops = {
2439 .ndo_open = pch_gbe_open,
2440 .ndo_stop = pch_gbe_stop,
2441 .ndo_start_xmit = pch_gbe_xmit_frame,
2442 .ndo_get_stats = pch_gbe_get_stats,
2443 .ndo_set_mac_address = pch_gbe_set_mac,
2444 .ndo_tx_timeout = pch_gbe_tx_timeout,
2445 .ndo_change_mtu = pch_gbe_change_mtu,
2446 .ndo_set_features = pch_gbe_set_features,
2447 .ndo_do_ioctl = pch_gbe_ioctl,
2448 .ndo_set_rx_mode = pch_gbe_set_multi,
2449 #ifdef CONFIG_NET_POLL_CONTROLLER
2450 .ndo_poll_controller = pch_gbe_netpoll,
2451 #endif
2452 };
2453
2454 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2455 pci_channel_state_t state)
2456 {
2457 struct net_device *netdev = pci_get_drvdata(pdev);
2458 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2459
2460 netif_device_detach(netdev);
2461 if (netif_running(netdev))
2462 pch_gbe_down(adapter);
2463 pci_disable_device(pdev);
2464 /* Request a slot slot reset. */
2465 return PCI_ERS_RESULT_NEED_RESET;
2466 }
2467
2468 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2469 {
2470 struct net_device *netdev = pci_get_drvdata(pdev);
2471 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2472 struct pch_gbe_hw *hw = &adapter->hw;
2473
2474 if (pci_enable_device(pdev)) {
2475 netdev_err(netdev, "Cannot re-enable PCI device after reset\n");
2476 return PCI_ERS_RESULT_DISCONNECT;
2477 }
2478 pci_set_master(pdev);
2479 pci_enable_wake(pdev, PCI_D0, 0);
2480 pch_gbe_hal_power_up_phy(hw);
2481 pch_gbe_reset(adapter);
2482 /* Clear wake up status */
2483 pch_gbe_mac_set_wol_event(hw, 0);
2484
2485 return PCI_ERS_RESULT_RECOVERED;
2486 }
2487
2488 static void pch_gbe_io_resume(struct pci_dev *pdev)
2489 {
2490 struct net_device *netdev = pci_get_drvdata(pdev);
2491 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2492
2493 if (netif_running(netdev)) {
2494 if (pch_gbe_up(adapter)) {
2495 netdev_dbg(netdev,
2496 "can't bring device back up after reset\n");
2497 return;
2498 }
2499 }
2500 netif_device_attach(netdev);
2501 }
2502
2503 static int __pch_gbe_suspend(struct pci_dev *pdev)
2504 {
2505 struct net_device *netdev = pci_get_drvdata(pdev);
2506 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2507 struct pch_gbe_hw *hw = &adapter->hw;
2508 u32 wufc = adapter->wake_up_evt;
2509 int retval = 0;
2510
2511 netif_device_detach(netdev);
2512 if (netif_running(netdev))
2513 pch_gbe_down(adapter);
2514 if (wufc) {
2515 pch_gbe_set_multi(netdev);
2516 pch_gbe_setup_rctl(adapter);
2517 pch_gbe_configure_rx(adapter);
2518 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2519 hw->mac.link_duplex);
2520 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2521 hw->mac.link_duplex);
2522 pch_gbe_mac_set_wol_event(hw, wufc);
2523 pci_disable_device(pdev);
2524 } else {
2525 pch_gbe_hal_power_down_phy(hw);
2526 pch_gbe_mac_set_wol_event(hw, wufc);
2527 pci_disable_device(pdev);
2528 }
2529 return retval;
2530 }
2531
2532 #ifdef CONFIG_PM
2533 static int pch_gbe_suspend(struct device *device)
2534 {
2535 struct pci_dev *pdev = to_pci_dev(device);
2536
2537 return __pch_gbe_suspend(pdev);
2538 }
2539
2540 static int pch_gbe_resume(struct device *device)
2541 {
2542 struct pci_dev *pdev = to_pci_dev(device);
2543 struct net_device *netdev = pci_get_drvdata(pdev);
2544 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2545 struct pch_gbe_hw *hw = &adapter->hw;
2546 u32 err;
2547
2548 err = pci_enable_device(pdev);
2549 if (err) {
2550 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
2551 return err;
2552 }
2553 pci_set_master(pdev);
2554 pch_gbe_hal_power_up_phy(hw);
2555 pch_gbe_reset(adapter);
2556 /* Clear wake on lan control and status */
2557 pch_gbe_mac_set_wol_event(hw, 0);
2558
2559 if (netif_running(netdev))
2560 pch_gbe_up(adapter);
2561 netif_device_attach(netdev);
2562
2563 return 0;
2564 }
2565 #endif /* CONFIG_PM */
2566
2567 static void pch_gbe_shutdown(struct pci_dev *pdev)
2568 {
2569 __pch_gbe_suspend(pdev);
2570 if (system_state == SYSTEM_POWER_OFF) {
2571 pci_wake_from_d3(pdev, true);
2572 pci_set_power_state(pdev, PCI_D3hot);
2573 }
2574 }
2575
2576 static void pch_gbe_remove(struct pci_dev *pdev)
2577 {
2578 struct net_device *netdev = pci_get_drvdata(pdev);
2579 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2580
2581 cancel_work_sync(&adapter->reset_task);
2582 unregister_netdev(netdev);
2583
2584 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2585
2586 free_netdev(netdev);
2587 }
2588
2589 static int pch_gbe_probe(struct pci_dev *pdev,
2590 const struct pci_device_id *pci_id)
2591 {
2592 struct net_device *netdev;
2593 struct pch_gbe_adapter *adapter;
2594 int ret;
2595
2596 ret = pcim_enable_device(pdev);
2597 if (ret)
2598 return ret;
2599
2600 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2601 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2602 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2603 if (ret) {
2604 ret = pci_set_consistent_dma_mask(pdev,
2605 DMA_BIT_MASK(32));
2606 if (ret) {
2607 dev_err(&pdev->dev, "ERR: No usable DMA "
2608 "configuration, aborting\n");
2609 return ret;
2610 }
2611 }
2612 }
2613
2614 ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev));
2615 if (ret) {
2616 dev_err(&pdev->dev,
2617 "ERR: Can't reserve PCI I/O and memory resources\n");
2618 return ret;
2619 }
2620 pci_set_master(pdev);
2621
2622 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2623 if (!netdev)
2624 return -ENOMEM;
2625 SET_NETDEV_DEV(netdev, &pdev->dev);
2626
2627 pci_set_drvdata(pdev, netdev);
2628 adapter = netdev_priv(netdev);
2629 adapter->netdev = netdev;
2630 adapter->pdev = pdev;
2631 adapter->hw.back = adapter;
2632 adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
2633 adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
2634 if (adapter->pdata && adapter->pdata->platform_init)
2635 adapter->pdata->platform_init(pdev);
2636
2637 adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
2638 PCI_DEVFN(12, 4));
2639 if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
2640 dev_err(&pdev->dev, "Bad ptp filter\n");
2641 ret = -EINVAL;
2642 goto err_free_netdev;
2643 }
2644
2645 netdev->netdev_ops = &pch_gbe_netdev_ops;
2646 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2647 netif_napi_add(netdev, &adapter->napi,
2648 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2649 netdev->hw_features = NETIF_F_RXCSUM |
2650 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2651 netdev->features = netdev->hw_features;
2652 pch_gbe_set_ethtool_ops(netdev);
2653
2654 pch_gbe_mac_load_mac_addr(&adapter->hw);
2655 pch_gbe_mac_reset_hw(&adapter->hw);
2656
2657 /* setup the private structure */
2658 ret = pch_gbe_sw_init(adapter);
2659 if (ret)
2660 goto err_free_netdev;
2661
2662 /* Initialize PHY */
2663 ret = pch_gbe_init_phy(adapter);
2664 if (ret) {
2665 dev_err(&pdev->dev, "PHY initialize error\n");
2666 goto err_free_adapter;
2667 }
2668 pch_gbe_hal_get_bus_info(&adapter->hw);
2669
2670 /* Read the MAC address. and store to the private data */
2671 ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2672 if (ret) {
2673 dev_err(&pdev->dev, "MAC address Read Error\n");
2674 goto err_free_adapter;
2675 }
2676
2677 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2678 if (!is_valid_ether_addr(netdev->dev_addr)) {
2679 /*
2680 * If the MAC is invalid (or just missing), display a warning
2681 * but do not abort setting up the device. pch_gbe_up will
2682 * prevent the interface from being brought up until a valid MAC
2683 * is set.
2684 */
2685 dev_err(&pdev->dev, "Invalid MAC address, "
2686 "interface disabled.\n");
2687 }
2688 setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2689 (unsigned long)adapter);
2690
2691 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2692
2693 pch_gbe_check_options(adapter);
2694
2695 /* initialize the wol settings based on the eeprom settings */
2696 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2697 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2698
2699 /* reset the hardware with the new settings */
2700 pch_gbe_reset(adapter);
2701
2702 ret = register_netdev(netdev);
2703 if (ret)
2704 goto err_free_adapter;
2705 /* tell the stack to leave us alone until pch_gbe_open() is called */
2706 netif_carrier_off(netdev);
2707 netif_stop_queue(netdev);
2708
2709 dev_dbg(&pdev->dev, "PCH Network Connection\n");
2710
2711 /* Disable hibernation on certain platforms */
2712 if (adapter->pdata && adapter->pdata->phy_disable_hibernate)
2713 pch_gbe_phy_disable_hibernate(&adapter->hw);
2714
2715 device_set_wakeup_enable(&pdev->dev, 1);
2716 return 0;
2717
2718 err_free_adapter:
2719 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2720 err_free_netdev:
2721 free_netdev(netdev);
2722 return ret;
2723 }
2724
2725 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
2726 * ensure it is awake for probe and init. Request the line and reset the PHY.
2727 */
2728 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
2729 {
2730 unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
2731 unsigned gpio = MINNOW_PHY_RESET_GPIO;
2732 int ret;
2733
2734 ret = devm_gpio_request_one(&pdev->dev, gpio, flags,
2735 "minnow_phy_reset");
2736 if (ret) {
2737 dev_err(&pdev->dev,
2738 "ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
2739 return ret;
2740 }
2741
2742 gpio_set_value(gpio, 0);
2743 usleep_range(1250, 1500);
2744 gpio_set_value(gpio, 1);
2745 usleep_range(1250, 1500);
2746
2747 return ret;
2748 }
2749
2750 static struct pch_gbe_privdata pch_gbe_minnow_privdata = {
2751 .phy_tx_clk_delay = true,
2752 .phy_disable_hibernate = true,
2753 .platform_init = pch_gbe_minnow_platform_init,
2754 };
2755
2756 static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
2757 {.vendor = PCI_VENDOR_ID_INTEL,
2758 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2759 .subvendor = PCI_VENDOR_ID_CIRCUITCO,
2760 .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD,
2761 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2762 .class_mask = (0xFFFF00),
2763 .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata
2764 },
2765 {.vendor = PCI_VENDOR_ID_INTEL,
2766 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2767 .subvendor = PCI_ANY_ID,
2768 .subdevice = PCI_ANY_ID,
2769 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2770 .class_mask = (0xFFFF00)
2771 },
2772 {.vendor = PCI_VENDOR_ID_ROHM,
2773 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2774 .subvendor = PCI_ANY_ID,
2775 .subdevice = PCI_ANY_ID,
2776 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2777 .class_mask = (0xFFFF00)
2778 },
2779 {.vendor = PCI_VENDOR_ID_ROHM,
2780 .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2781 .subvendor = PCI_ANY_ID,
2782 .subdevice = PCI_ANY_ID,
2783 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2784 .class_mask = (0xFFFF00)
2785 },
2786 /* required last entry */
2787 {0}
2788 };
2789
2790 #ifdef CONFIG_PM
2791 static const struct dev_pm_ops pch_gbe_pm_ops = {
2792 .suspend = pch_gbe_suspend,
2793 .resume = pch_gbe_resume,
2794 .freeze = pch_gbe_suspend,
2795 .thaw = pch_gbe_resume,
2796 .poweroff = pch_gbe_suspend,
2797 .restore = pch_gbe_resume,
2798 };
2799 #endif
2800
2801 static const struct pci_error_handlers pch_gbe_err_handler = {
2802 .error_detected = pch_gbe_io_error_detected,
2803 .slot_reset = pch_gbe_io_slot_reset,
2804 .resume = pch_gbe_io_resume
2805 };
2806
2807 static struct pci_driver pch_gbe_driver = {
2808 .name = KBUILD_MODNAME,
2809 .id_table = pch_gbe_pcidev_id,
2810 .probe = pch_gbe_probe,
2811 .remove = pch_gbe_remove,
2812 #ifdef CONFIG_PM
2813 .driver.pm = &pch_gbe_pm_ops,
2814 #endif
2815 .shutdown = pch_gbe_shutdown,
2816 .err_handler = &pch_gbe_err_handler
2817 };
2818
2819
2820 static int __init pch_gbe_init_module(void)
2821 {
2822 int ret;
2823
2824 pr_info("EG20T PCH Gigabit Ethernet Driver - version %s\n",DRV_VERSION);
2825 ret = pci_register_driver(&pch_gbe_driver);
2826 if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2827 if (copybreak == 0) {
2828 pr_info("copybreak disabled\n");
2829 } else {
2830 pr_info("copybreak enabled for packets <= %u bytes\n",
2831 copybreak);
2832 }
2833 }
2834 return ret;
2835 }
2836
2837 static void __exit pch_gbe_exit_module(void)
2838 {
2839 pci_unregister_driver(&pch_gbe_driver);
2840 }
2841
2842 module_init(pch_gbe_init_module);
2843 module_exit(pch_gbe_exit_module);
2844
2845 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2846 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
2847 MODULE_LICENSE("GPL");
2848 MODULE_VERSION(DRV_VERSION);
2849 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2850
2851 module_param(copybreak, uint, 0644);
2852 MODULE_PARM_DESC(copybreak,
2853 "Maximum size of packet that is copied to a new buffer on receive");
2854
2855 /* pch_gbe_main.c */
Linux kernel - Deliverables
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