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Merge tag 'random_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tytso...
[deliverable/linux.git] / drivers / net / ethernet / oki-semi / pch_gbe / pch_gbe_main.c
1 /*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
4 *
5 * This code was derived from the Intel e1000e Linux driver.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include "pch_gbe.h"
22 #include "pch_gbe_api.h"
23 #include <linux/module.h>
24 #include <linux/net_tstamp.h>
25 #include <linux/ptp_classify.h>
26 #include <linux/gpio.h>
27
28 #define DRV_VERSION "1.01"
29 const char pch_driver_version[] = DRV_VERSION;
30
31 #define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 /* Pci device ID */
32 #define PCH_GBE_MAR_ENTRIES 16
33 #define PCH_GBE_SHORT_PKT 64
34 #define DSC_INIT16 0xC000
35 #define PCH_GBE_DMA_ALIGN 0
36 #define PCH_GBE_DMA_PADDING 2
37 #define PCH_GBE_WATCHDOG_PERIOD (5 * HZ) /* watchdog time */
38 #define PCH_GBE_COPYBREAK_DEFAULT 256
39 #define PCH_GBE_PCI_BAR 1
40 #define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */
41
42 /* Macros for ML7223 */
43 #define PCI_VENDOR_ID_ROHM 0x10db
44 #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013
45
46 /* Macros for ML7831 */
47 #define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802
48
49 #define PCH_GBE_TX_WEIGHT 64
50 #define PCH_GBE_RX_WEIGHT 64
51 #define PCH_GBE_RX_BUFFER_WRITE 16
52
53 /* Initialize the wake-on-LAN settings */
54 #define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP)
55
56 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
57 PCH_GBE_CHIP_TYPE_INTERNAL | \
58 PCH_GBE_RGMII_MODE_RGMII \
59 )
60
61 /* Ethertype field values */
62 #define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880
63 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318
64 #define PCH_GBE_FRAME_SIZE_2048 2048
65 #define PCH_GBE_FRAME_SIZE_4096 4096
66 #define PCH_GBE_FRAME_SIZE_8192 8192
67
68 #define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
69 #define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
70 #define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
71 #define PCH_GBE_DESC_UNUSED(R) \
72 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
73 (R)->next_to_clean - (R)->next_to_use - 1)
74
75 /* Pause packet value */
76 #define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001
77 #define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100
78 #define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888
79 #define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF
80
81
82 /* This defines the bits that are set in the Interrupt Mask
83 * Set/Read Register. Each bit is documented below:
84 * o RXT0 = Receiver Timer Interrupt (ring 0)
85 * o TXDW = Transmit Descriptor Written Back
86 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
87 * o RXSEQ = Receive Sequence Error
88 * o LSC = Link Status Change
89 */
90 #define PCH_GBE_INT_ENABLE_MASK ( \
91 PCH_GBE_INT_RX_DMA_CMPLT | \
92 PCH_GBE_INT_RX_DSC_EMP | \
93 PCH_GBE_INT_RX_FIFO_ERR | \
94 PCH_GBE_INT_WOL_DET | \
95 PCH_GBE_INT_TX_CMPLT \
96 )
97
98 #define PCH_GBE_INT_DISABLE_ALL 0
99
100 /* Macros for ieee1588 */
101 /* 0x40 Time Synchronization Channel Control Register Bits */
102 #define MASTER_MODE (1<<0)
103 #define SLAVE_MODE (0)
104 #define V2_MODE (1<<31)
105 #define CAP_MODE0 (0)
106 #define CAP_MODE2 (1<<17)
107
108 /* 0x44 Time Synchronization Channel Event Register Bits */
109 #define TX_SNAPSHOT_LOCKED (1<<0)
110 #define RX_SNAPSHOT_LOCKED (1<<1)
111
112 #define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81"
113 #define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00"
114
115 #define MINNOW_PHY_RESET_GPIO 13
116
117 static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
118
119 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
120 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
121 int data);
122 static void pch_gbe_set_multi(struct net_device *netdev);
123
124 static struct sock_filter ptp_filter[] = {
125 PTP_FILTER
126 };
127
128 static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
129 {
130 u8 *data = skb->data;
131 unsigned int offset;
132 u16 *hi, *id;
133 u32 lo;
134
135 if (sk_run_filter(skb, ptp_filter) == PTP_CLASS_NONE)
136 return 0;
137
138 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
139
140 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
141 return 0;
142
143 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
144 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
145
146 memcpy(&lo, &hi[1], sizeof(lo));
147
148 return (uid_hi == *hi &&
149 uid_lo == lo &&
150 seqid == *id);
151 }
152
153 static void
154 pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
155 {
156 struct skb_shared_hwtstamps *shhwtstamps;
157 struct pci_dev *pdev;
158 u64 ns;
159 u32 hi, lo, val;
160 u16 uid, seq;
161
162 if (!adapter->hwts_rx_en)
163 return;
164
165 /* Get ieee1588's dev information */
166 pdev = adapter->ptp_pdev;
167
168 val = pch_ch_event_read(pdev);
169
170 if (!(val & RX_SNAPSHOT_LOCKED))
171 return;
172
173 lo = pch_src_uuid_lo_read(pdev);
174 hi = pch_src_uuid_hi_read(pdev);
175
176 uid = hi & 0xffff;
177 seq = (hi >> 16) & 0xffff;
178
179 if (!pch_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
180 goto out;
181
182 ns = pch_rx_snap_read(pdev);
183
184 shhwtstamps = skb_hwtstamps(skb);
185 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
186 shhwtstamps->hwtstamp = ns_to_ktime(ns);
187 out:
188 pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
189 }
190
191 static void
192 pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
193 {
194 struct skb_shared_hwtstamps shhwtstamps;
195 struct pci_dev *pdev;
196 struct skb_shared_info *shtx;
197 u64 ns;
198 u32 cnt, val;
199
200 shtx = skb_shinfo(skb);
201 if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)))
202 return;
203
204 shtx->tx_flags |= SKBTX_IN_PROGRESS;
205
206 /* Get ieee1588's dev information */
207 pdev = adapter->ptp_pdev;
208
209 /*
210 * This really stinks, but we have to poll for the Tx time stamp.
211 */
212 for (cnt = 0; cnt < 100; cnt++) {
213 val = pch_ch_event_read(pdev);
214 if (val & TX_SNAPSHOT_LOCKED)
215 break;
216 udelay(1);
217 }
218 if (!(val & TX_SNAPSHOT_LOCKED)) {
219 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
220 return;
221 }
222
223 ns = pch_tx_snap_read(pdev);
224
225 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
226 shhwtstamps.hwtstamp = ns_to_ktime(ns);
227 skb_tstamp_tx(skb, &shhwtstamps);
228
229 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
230 }
231
232 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
233 {
234 struct hwtstamp_config cfg;
235 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
236 struct pci_dev *pdev;
237 u8 station[20];
238
239 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
240 return -EFAULT;
241
242 if (cfg.flags) /* reserved for future extensions */
243 return -EINVAL;
244
245 /* Get ieee1588's dev information */
246 pdev = adapter->ptp_pdev;
247
248 switch (cfg.tx_type) {
249 case HWTSTAMP_TX_OFF:
250 adapter->hwts_tx_en = 0;
251 break;
252 case HWTSTAMP_TX_ON:
253 adapter->hwts_tx_en = 1;
254 break;
255 default:
256 return -ERANGE;
257 }
258
259 switch (cfg.rx_filter) {
260 case HWTSTAMP_FILTER_NONE:
261 adapter->hwts_rx_en = 0;
262 break;
263 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
264 adapter->hwts_rx_en = 0;
265 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0);
266 break;
267 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
268 adapter->hwts_rx_en = 1;
269 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0);
270 break;
271 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
272 adapter->hwts_rx_en = 1;
273 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
274 strcpy(station, PTP_L4_MULTICAST_SA);
275 pch_set_station_address(station, pdev);
276 break;
277 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
278 adapter->hwts_rx_en = 1;
279 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
280 strcpy(station, PTP_L2_MULTICAST_SA);
281 pch_set_station_address(station, pdev);
282 break;
283 default:
284 return -ERANGE;
285 }
286
287 /* Clear out any old time stamps. */
288 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
289
290 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
291 }
292
293 static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
294 {
295 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
296 }
297
298 /**
299 * pch_gbe_mac_read_mac_addr - Read MAC address
300 * @hw: Pointer to the HW structure
301 * Returns:
302 * 0: Successful.
303 */
304 s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
305 {
306 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
307 u32 adr1a, adr1b;
308
309 adr1a = ioread32(&hw->reg->mac_adr[0].high);
310 adr1b = ioread32(&hw->reg->mac_adr[0].low);
311
312 hw->mac.addr[0] = (u8)(adr1a & 0xFF);
313 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
314 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
315 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
316 hw->mac.addr[4] = (u8)(adr1b & 0xFF);
317 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
318
319 netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr);
320 return 0;
321 }
322
323 /**
324 * pch_gbe_wait_clr_bit - Wait to clear a bit
325 * @reg: Pointer of register
326 * @busy: Busy bit
327 */
328 static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
329 {
330 u32 tmp;
331
332 /* wait busy */
333 tmp = 1000;
334 while ((ioread32(reg) & bit) && --tmp)
335 cpu_relax();
336 if (!tmp)
337 pr_err("Error: busy bit is not cleared\n");
338 }
339
340 /**
341 * pch_gbe_mac_mar_set - Set MAC address register
342 * @hw: Pointer to the HW structure
343 * @addr: Pointer to the MAC address
344 * @index: MAC address array register
345 */
346 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
347 {
348 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
349 u32 mar_low, mar_high, adrmask;
350
351 netdev_dbg(adapter->netdev, "index : 0x%x\n", index);
352
353 /*
354 * HW expects these in little endian so we reverse the byte order
355 * from network order (big endian) to little endian
356 */
357 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
358 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
359 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
360 /* Stop the MAC Address of index. */
361 adrmask = ioread32(&hw->reg->ADDR_MASK);
362 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
363 /* wait busy */
364 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
365 /* Set the MAC address to the MAC address 1A/1B register */
366 iowrite32(mar_high, &hw->reg->mac_adr[index].high);
367 iowrite32(mar_low, &hw->reg->mac_adr[index].low);
368 /* Start the MAC address of index */
369 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
370 /* wait busy */
371 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
372 }
373
374 /**
375 * pch_gbe_mac_reset_hw - Reset hardware
376 * @hw: Pointer to the HW structure
377 */
378 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
379 {
380 /* Read the MAC address. and store to the private data */
381 pch_gbe_mac_read_mac_addr(hw);
382 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
383 #ifdef PCH_GBE_MAC_IFOP_RGMII
384 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
385 #endif
386 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
387 /* Setup the receive addresses */
388 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
389 return;
390 }
391
392 static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw)
393 {
394 u32 rctl;
395 /* Disables Receive MAC */
396 rctl = ioread32(&hw->reg->MAC_RX_EN);
397 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
398 }
399
400 static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw)
401 {
402 u32 rctl;
403 /* Enables Receive MAC */
404 rctl = ioread32(&hw->reg->MAC_RX_EN);
405 iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
406 }
407
408 /**
409 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
410 * @hw: Pointer to the HW structure
411 * @mar_count: Receive address registers
412 */
413 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
414 {
415 u32 i;
416
417 /* Setup the receive address */
418 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
419
420 /* Zero out the other receive addresses */
421 for (i = 1; i < mar_count; i++) {
422 iowrite32(0, &hw->reg->mac_adr[i].high);
423 iowrite32(0, &hw->reg->mac_adr[i].low);
424 }
425 iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
426 /* wait busy */
427 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
428 }
429
430
431 /**
432 * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
433 * @hw: Pointer to the HW structure
434 * @mc_addr_list: Array of multicast addresses to program
435 * @mc_addr_count: Number of multicast addresses to program
436 * @mar_used_count: The first MAC Address register free to program
437 * @mar_total_num: Total number of supported MAC Address Registers
438 */
439 static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
440 u8 *mc_addr_list, u32 mc_addr_count,
441 u32 mar_used_count, u32 mar_total_num)
442 {
443 u32 i, adrmask;
444
445 /* Load the first set of multicast addresses into the exact
446 * filters (RAR). If there are not enough to fill the RAR
447 * array, clear the filters.
448 */
449 for (i = mar_used_count; i < mar_total_num; i++) {
450 if (mc_addr_count) {
451 pch_gbe_mac_mar_set(hw, mc_addr_list, i);
452 mc_addr_count--;
453 mc_addr_list += ETH_ALEN;
454 } else {
455 /* Clear MAC address mask */
456 adrmask = ioread32(&hw->reg->ADDR_MASK);
457 iowrite32((adrmask | (0x0001 << i)),
458 &hw->reg->ADDR_MASK);
459 /* wait busy */
460 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
461 /* Clear MAC address */
462 iowrite32(0, &hw->reg->mac_adr[i].high);
463 iowrite32(0, &hw->reg->mac_adr[i].low);
464 }
465 }
466 }
467
468 /**
469 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
470 * @hw: Pointer to the HW structure
471 * Returns:
472 * 0: Successful.
473 * Negative value: Failed.
474 */
475 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
476 {
477 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
478 struct pch_gbe_mac_info *mac = &hw->mac;
479 u32 rx_fctrl;
480
481 netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc);
482
483 rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
484
485 switch (mac->fc) {
486 case PCH_GBE_FC_NONE:
487 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
488 mac->tx_fc_enable = false;
489 break;
490 case PCH_GBE_FC_RX_PAUSE:
491 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
492 mac->tx_fc_enable = false;
493 break;
494 case PCH_GBE_FC_TX_PAUSE:
495 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
496 mac->tx_fc_enable = true;
497 break;
498 case PCH_GBE_FC_FULL:
499 rx_fctrl |= PCH_GBE_FL_CTRL_EN;
500 mac->tx_fc_enable = true;
501 break;
502 default:
503 netdev_err(adapter->netdev,
504 "Flow control param set incorrectly\n");
505 return -EINVAL;
506 }
507 if (mac->link_duplex == DUPLEX_HALF)
508 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
509 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
510 netdev_dbg(adapter->netdev,
511 "RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n",
512 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
513 return 0;
514 }
515
516 /**
517 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
518 * @hw: Pointer to the HW structure
519 * @wu_evt: Wake up event
520 */
521 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
522 {
523 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
524 u32 addr_mask;
525
526 netdev_dbg(adapter->netdev, "wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n",
527 wu_evt, ioread32(&hw->reg->ADDR_MASK));
528
529 if (wu_evt) {
530 /* Set Wake-On-Lan address mask */
531 addr_mask = ioread32(&hw->reg->ADDR_MASK);
532 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
533 /* wait busy */
534 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
535 iowrite32(0, &hw->reg->WOL_ST);
536 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
537 iowrite32(0x02, &hw->reg->TCPIP_ACC);
538 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
539 } else {
540 iowrite32(0, &hw->reg->WOL_CTRL);
541 iowrite32(0, &hw->reg->WOL_ST);
542 }
543 return;
544 }
545
546 /**
547 * pch_gbe_mac_ctrl_miim - Control MIIM interface
548 * @hw: Pointer to the HW structure
549 * @addr: Address of PHY
550 * @dir: Operetion. (Write or Read)
551 * @reg: Access register of PHY
552 * @data: Write data.
553 *
554 * Returns: Read date.
555 */
556 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
557 u16 data)
558 {
559 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
560 u32 data_out = 0;
561 unsigned int i;
562 unsigned long flags;
563
564 spin_lock_irqsave(&hw->miim_lock, flags);
565
566 for (i = 100; i; --i) {
567 if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
568 break;
569 udelay(20);
570 }
571 if (i == 0) {
572 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n");
573 spin_unlock_irqrestore(&hw->miim_lock, flags);
574 return 0; /* No way to indicate timeout error */
575 }
576 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
577 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
578 dir | data), &hw->reg->MIIM);
579 for (i = 0; i < 100; i++) {
580 udelay(20);
581 data_out = ioread32(&hw->reg->MIIM);
582 if ((data_out & PCH_GBE_MIIM_OPER_READY))
583 break;
584 }
585 spin_unlock_irqrestore(&hw->miim_lock, flags);
586
587 netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n",
588 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
589 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
590 return (u16) data_out;
591 }
592
593 /**
594 * pch_gbe_mac_set_pause_packet - Set pause packet
595 * @hw: Pointer to the HW structure
596 */
597 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
598 {
599 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
600 unsigned long tmp2, tmp3;
601
602 /* Set Pause packet */
603 tmp2 = hw->mac.addr[1];
604 tmp2 = (tmp2 << 8) | hw->mac.addr[0];
605 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
606
607 tmp3 = hw->mac.addr[5];
608 tmp3 = (tmp3 << 8) | hw->mac.addr[4];
609 tmp3 = (tmp3 << 8) | hw->mac.addr[3];
610 tmp3 = (tmp3 << 8) | hw->mac.addr[2];
611
612 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
613 iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
614 iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
615 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
616 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
617
618 /* Transmit Pause Packet */
619 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
620
621 netdev_dbg(adapter->netdev,
622 "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
623 ioread32(&hw->reg->PAUSE_PKT1),
624 ioread32(&hw->reg->PAUSE_PKT2),
625 ioread32(&hw->reg->PAUSE_PKT3),
626 ioread32(&hw->reg->PAUSE_PKT4),
627 ioread32(&hw->reg->PAUSE_PKT5));
628
629 return;
630 }
631
632
633 /**
634 * pch_gbe_alloc_queues - Allocate memory for all rings
635 * @adapter: Board private structure to initialize
636 * Returns:
637 * 0: Successfully
638 * Negative value: Failed
639 */
640 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
641 {
642 adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev,
643 sizeof(*adapter->tx_ring), GFP_KERNEL);
644 if (!adapter->tx_ring)
645 return -ENOMEM;
646
647 adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev,
648 sizeof(*adapter->rx_ring), GFP_KERNEL);
649 if (!adapter->rx_ring)
650 return -ENOMEM;
651 return 0;
652 }
653
654 /**
655 * pch_gbe_init_stats - Initialize status
656 * @adapter: Board private structure to initialize
657 */
658 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
659 {
660 memset(&adapter->stats, 0, sizeof(adapter->stats));
661 return;
662 }
663
664 /**
665 * pch_gbe_init_phy - Initialize PHY
666 * @adapter: Board private structure to initialize
667 * Returns:
668 * 0: Successfully
669 * Negative value: Failed
670 */
671 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
672 {
673 struct net_device *netdev = adapter->netdev;
674 u32 addr;
675 u16 bmcr, stat;
676
677 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
678 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
679 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
680 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
681 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
682 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
683 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
684 break;
685 }
686 adapter->hw.phy.addr = adapter->mii.phy_id;
687 netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id);
688 if (addr == PCH_GBE_PHY_REGS_LEN)
689 return -EAGAIN;
690 /* Selected the phy and isolate the rest */
691 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
692 if (addr != adapter->mii.phy_id) {
693 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
694 BMCR_ISOLATE);
695 } else {
696 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
697 pch_gbe_mdio_write(netdev, addr, MII_BMCR,
698 bmcr & ~BMCR_ISOLATE);
699 }
700 }
701
702 /* MII setup */
703 adapter->mii.phy_id_mask = 0x1F;
704 adapter->mii.reg_num_mask = 0x1F;
705 adapter->mii.dev = adapter->netdev;
706 adapter->mii.mdio_read = pch_gbe_mdio_read;
707 adapter->mii.mdio_write = pch_gbe_mdio_write;
708 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
709 return 0;
710 }
711
712 /**
713 * pch_gbe_mdio_read - The read function for mii
714 * @netdev: Network interface device structure
715 * @addr: Phy ID
716 * @reg: Access location
717 * Returns:
718 * 0: Successfully
719 * Negative value: Failed
720 */
721 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
722 {
723 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
724 struct pch_gbe_hw *hw = &adapter->hw;
725
726 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
727 (u16) 0);
728 }
729
730 /**
731 * pch_gbe_mdio_write - The write function for mii
732 * @netdev: Network interface device structure
733 * @addr: Phy ID (not used)
734 * @reg: Access location
735 * @data: Write data
736 */
737 static void pch_gbe_mdio_write(struct net_device *netdev,
738 int addr, int reg, int data)
739 {
740 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
741 struct pch_gbe_hw *hw = &adapter->hw;
742
743 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
744 }
745
746 /**
747 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
748 * @work: Pointer of board private structure
749 */
750 static void pch_gbe_reset_task(struct work_struct *work)
751 {
752 struct pch_gbe_adapter *adapter;
753 adapter = container_of(work, struct pch_gbe_adapter, reset_task);
754
755 rtnl_lock();
756 pch_gbe_reinit_locked(adapter);
757 rtnl_unlock();
758 }
759
760 /**
761 * pch_gbe_reinit_locked- Re-initialization
762 * @adapter: Board private structure
763 */
764 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
765 {
766 pch_gbe_down(adapter);
767 pch_gbe_up(adapter);
768 }
769
770 /**
771 * pch_gbe_reset - Reset GbE
772 * @adapter: Board private structure
773 */
774 void pch_gbe_reset(struct pch_gbe_adapter *adapter)
775 {
776 struct net_device *netdev = adapter->netdev;
777
778 pch_gbe_mac_reset_hw(&adapter->hw);
779 /* reprogram multicast address register after reset */
780 pch_gbe_set_multi(netdev);
781 /* Setup the receive address. */
782 pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
783 if (pch_gbe_hal_init_hw(&adapter->hw))
784 netdev_err(netdev, "Hardware Error\n");
785 }
786
787 /**
788 * pch_gbe_free_irq - Free an interrupt
789 * @adapter: Board private structure
790 */
791 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
792 {
793 struct net_device *netdev = adapter->netdev;
794
795 free_irq(adapter->pdev->irq, netdev);
796 if (adapter->have_msi) {
797 pci_disable_msi(adapter->pdev);
798 netdev_dbg(netdev, "call pci_disable_msi\n");
799 }
800 }
801
802 /**
803 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
804 * @adapter: Board private structure
805 */
806 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
807 {
808 struct pch_gbe_hw *hw = &adapter->hw;
809
810 atomic_inc(&adapter->irq_sem);
811 iowrite32(0, &hw->reg->INT_EN);
812 ioread32(&hw->reg->INT_ST);
813 synchronize_irq(adapter->pdev->irq);
814
815 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
816 ioread32(&hw->reg->INT_EN));
817 }
818
819 /**
820 * pch_gbe_irq_enable - Enable default interrupt generation settings
821 * @adapter: Board private structure
822 */
823 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
824 {
825 struct pch_gbe_hw *hw = &adapter->hw;
826
827 if (likely(atomic_dec_and_test(&adapter->irq_sem)))
828 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
829 ioread32(&hw->reg->INT_ST);
830 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
831 ioread32(&hw->reg->INT_EN));
832 }
833
834
835
836 /**
837 * pch_gbe_setup_tctl - configure the Transmit control registers
838 * @adapter: Board private structure
839 */
840 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
841 {
842 struct pch_gbe_hw *hw = &adapter->hw;
843 u32 tx_mode, tcpip;
844
845 tx_mode = PCH_GBE_TM_LONG_PKT |
846 PCH_GBE_TM_ST_AND_FD |
847 PCH_GBE_TM_SHORT_PKT |
848 PCH_GBE_TM_TH_TX_STRT_8 |
849 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
850
851 iowrite32(tx_mode, &hw->reg->TX_MODE);
852
853 tcpip = ioread32(&hw->reg->TCPIP_ACC);
854 tcpip |= PCH_GBE_TX_TCPIPACC_EN;
855 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
856 return;
857 }
858
859 /**
860 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
861 * @adapter: Board private structure
862 */
863 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
864 {
865 struct pch_gbe_hw *hw = &adapter->hw;
866 u32 tdba, tdlen, dctrl;
867
868 netdev_dbg(adapter->netdev, "dma addr = 0x%08llx size = 0x%08x\n",
869 (unsigned long long)adapter->tx_ring->dma,
870 adapter->tx_ring->size);
871
872 /* Setup the HW Tx Head and Tail descriptor pointers */
873 tdba = adapter->tx_ring->dma;
874 tdlen = adapter->tx_ring->size - 0x10;
875 iowrite32(tdba, &hw->reg->TX_DSC_BASE);
876 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
877 iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
878
879 /* Enables Transmission DMA */
880 dctrl = ioread32(&hw->reg->DMA_CTRL);
881 dctrl |= PCH_GBE_TX_DMA_EN;
882 iowrite32(dctrl, &hw->reg->DMA_CTRL);
883 }
884
885 /**
886 * pch_gbe_setup_rctl - Configure the receive control registers
887 * @adapter: Board private structure
888 */
889 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
890 {
891 struct pch_gbe_hw *hw = &adapter->hw;
892 u32 rx_mode, tcpip;
893
894 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
895 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
896
897 iowrite32(rx_mode, &hw->reg->RX_MODE);
898
899 tcpip = ioread32(&hw->reg->TCPIP_ACC);
900
901 tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
902 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
903 iowrite32(tcpip, &hw->reg->TCPIP_ACC);
904 return;
905 }
906
907 /**
908 * pch_gbe_configure_rx - Configure Receive Unit after Reset
909 * @adapter: Board private structure
910 */
911 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
912 {
913 struct pch_gbe_hw *hw = &adapter->hw;
914 u32 rdba, rdlen, rxdma;
915
916 netdev_dbg(adapter->netdev, "dma adr = 0x%08llx size = 0x%08x\n",
917 (unsigned long long)adapter->rx_ring->dma,
918 adapter->rx_ring->size);
919
920 pch_gbe_mac_force_mac_fc(hw);
921
922 pch_gbe_disable_mac_rx(hw);
923
924 /* Disables Receive DMA */
925 rxdma = ioread32(&hw->reg->DMA_CTRL);
926 rxdma &= ~PCH_GBE_RX_DMA_EN;
927 iowrite32(rxdma, &hw->reg->DMA_CTRL);
928
929 netdev_dbg(adapter->netdev,
930 "MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n",
931 ioread32(&hw->reg->MAC_RX_EN),
932 ioread32(&hw->reg->DMA_CTRL));
933
934 /* Setup the HW Rx Head and Tail Descriptor Pointers and
935 * the Base and Length of the Rx Descriptor Ring */
936 rdba = adapter->rx_ring->dma;
937 rdlen = adapter->rx_ring->size - 0x10;
938 iowrite32(rdba, &hw->reg->RX_DSC_BASE);
939 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
940 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
941 }
942
943 /**
944 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
945 * @adapter: Board private structure
946 * @buffer_info: Buffer information structure
947 */
948 static void pch_gbe_unmap_and_free_tx_resource(
949 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
950 {
951 if (buffer_info->mapped) {
952 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
953 buffer_info->length, DMA_TO_DEVICE);
954 buffer_info->mapped = false;
955 }
956 if (buffer_info->skb) {
957 dev_kfree_skb_any(buffer_info->skb);
958 buffer_info->skb = NULL;
959 }
960 }
961
962 /**
963 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
964 * @adapter: Board private structure
965 * @buffer_info: Buffer information structure
966 */
967 static void pch_gbe_unmap_and_free_rx_resource(
968 struct pch_gbe_adapter *adapter,
969 struct pch_gbe_buffer *buffer_info)
970 {
971 if (buffer_info->mapped) {
972 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
973 buffer_info->length, DMA_FROM_DEVICE);
974 buffer_info->mapped = false;
975 }
976 if (buffer_info->skb) {
977 dev_kfree_skb_any(buffer_info->skb);
978 buffer_info->skb = NULL;
979 }
980 }
981
982 /**
983 * pch_gbe_clean_tx_ring - Free Tx Buffers
984 * @adapter: Board private structure
985 * @tx_ring: Ring to be cleaned
986 */
987 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
988 struct pch_gbe_tx_ring *tx_ring)
989 {
990 struct pch_gbe_hw *hw = &adapter->hw;
991 struct pch_gbe_buffer *buffer_info;
992 unsigned long size;
993 unsigned int i;
994
995 /* Free all the Tx ring sk_buffs */
996 for (i = 0; i < tx_ring->count; i++) {
997 buffer_info = &tx_ring->buffer_info[i];
998 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
999 }
1000 netdev_dbg(adapter->netdev,
1001 "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
1002
1003 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1004 memset(tx_ring->buffer_info, 0, size);
1005
1006 /* Zero out the descriptor ring */
1007 memset(tx_ring->desc, 0, tx_ring->size);
1008 tx_ring->next_to_use = 0;
1009 tx_ring->next_to_clean = 0;
1010 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
1011 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
1012 }
1013
1014 /**
1015 * pch_gbe_clean_rx_ring - Free Rx Buffers
1016 * @adapter: Board private structure
1017 * @rx_ring: Ring to free buffers from
1018 */
1019 static void
1020 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
1021 struct pch_gbe_rx_ring *rx_ring)
1022 {
1023 struct pch_gbe_hw *hw = &adapter->hw;
1024 struct pch_gbe_buffer *buffer_info;
1025 unsigned long size;
1026 unsigned int i;
1027
1028 /* Free all the Rx ring sk_buffs */
1029 for (i = 0; i < rx_ring->count; i++) {
1030 buffer_info = &rx_ring->buffer_info[i];
1031 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
1032 }
1033 netdev_dbg(adapter->netdev,
1034 "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
1035 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1036 memset(rx_ring->buffer_info, 0, size);
1037
1038 /* Zero out the descriptor ring */
1039 memset(rx_ring->desc, 0, rx_ring->size);
1040 rx_ring->next_to_clean = 0;
1041 rx_ring->next_to_use = 0;
1042 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
1043 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
1044 }
1045
1046 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
1047 u16 duplex)
1048 {
1049 struct pch_gbe_hw *hw = &adapter->hw;
1050 unsigned long rgmii = 0;
1051
1052 /* Set the RGMII control. */
1053 #ifdef PCH_GBE_MAC_IFOP_RGMII
1054 switch (speed) {
1055 case SPEED_10:
1056 rgmii = (PCH_GBE_RGMII_RATE_2_5M |
1057 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1058 break;
1059 case SPEED_100:
1060 rgmii = (PCH_GBE_RGMII_RATE_25M |
1061 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1062 break;
1063 case SPEED_1000:
1064 rgmii = (PCH_GBE_RGMII_RATE_125M |
1065 PCH_GBE_MAC_RGMII_CTRL_SETTING);
1066 break;
1067 }
1068 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1069 #else /* GMII */
1070 rgmii = 0;
1071 iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1072 #endif
1073 }
1074 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
1075 u16 duplex)
1076 {
1077 struct net_device *netdev = adapter->netdev;
1078 struct pch_gbe_hw *hw = &adapter->hw;
1079 unsigned long mode = 0;
1080
1081 /* Set the communication mode */
1082 switch (speed) {
1083 case SPEED_10:
1084 mode = PCH_GBE_MODE_MII_ETHER;
1085 netdev->tx_queue_len = 10;
1086 break;
1087 case SPEED_100:
1088 mode = PCH_GBE_MODE_MII_ETHER;
1089 netdev->tx_queue_len = 100;
1090 break;
1091 case SPEED_1000:
1092 mode = PCH_GBE_MODE_GMII_ETHER;
1093 break;
1094 }
1095 if (duplex == DUPLEX_FULL)
1096 mode |= PCH_GBE_MODE_FULL_DUPLEX;
1097 else
1098 mode |= PCH_GBE_MODE_HALF_DUPLEX;
1099 iowrite32(mode, &hw->reg->MODE);
1100 }
1101
1102 /**
1103 * pch_gbe_watchdog - Watchdog process
1104 * @data: Board private structure
1105 */
1106 static void pch_gbe_watchdog(unsigned long data)
1107 {
1108 struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
1109 struct net_device *netdev = adapter->netdev;
1110 struct pch_gbe_hw *hw = &adapter->hw;
1111
1112 netdev_dbg(netdev, "right now = %ld\n", jiffies);
1113
1114 pch_gbe_update_stats(adapter);
1115 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
1116 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1117 netdev->tx_queue_len = adapter->tx_queue_len;
1118 /* mii library handles link maintenance tasks */
1119 if (mii_ethtool_gset(&adapter->mii, &cmd)) {
1120 netdev_err(netdev, "ethtool get setting Error\n");
1121 mod_timer(&adapter->watchdog_timer,
1122 round_jiffies(jiffies +
1123 PCH_GBE_WATCHDOG_PERIOD));
1124 return;
1125 }
1126 hw->mac.link_speed = ethtool_cmd_speed(&cmd);
1127 hw->mac.link_duplex = cmd.duplex;
1128 /* Set the RGMII control. */
1129 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
1130 hw->mac.link_duplex);
1131 /* Set the communication mode */
1132 pch_gbe_set_mode(adapter, hw->mac.link_speed,
1133 hw->mac.link_duplex);
1134 netdev_dbg(netdev,
1135 "Link is Up %d Mbps %s-Duplex\n",
1136 hw->mac.link_speed,
1137 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1138 netif_carrier_on(netdev);
1139 netif_wake_queue(netdev);
1140 } else if ((!mii_link_ok(&adapter->mii)) &&
1141 (netif_carrier_ok(netdev))) {
1142 netdev_dbg(netdev, "NIC Link is Down\n");
1143 hw->mac.link_speed = SPEED_10;
1144 hw->mac.link_duplex = DUPLEX_HALF;
1145 netif_carrier_off(netdev);
1146 netif_stop_queue(netdev);
1147 }
1148 mod_timer(&adapter->watchdog_timer,
1149 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
1150 }
1151
1152 /**
1153 * pch_gbe_tx_queue - Carry out queuing of the transmission data
1154 * @adapter: Board private structure
1155 * @tx_ring: Tx descriptor ring structure
1156 * @skb: Sockt buffer structure
1157 */
1158 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
1159 struct pch_gbe_tx_ring *tx_ring,
1160 struct sk_buff *skb)
1161 {
1162 struct pch_gbe_hw *hw = &adapter->hw;
1163 struct pch_gbe_tx_desc *tx_desc;
1164 struct pch_gbe_buffer *buffer_info;
1165 struct sk_buff *tmp_skb;
1166 unsigned int frame_ctrl;
1167 unsigned int ring_num;
1168
1169 /*-- Set frame control --*/
1170 frame_ctrl = 0;
1171 if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
1172 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
1173 if (skb->ip_summed == CHECKSUM_NONE)
1174 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1175
1176 /* Performs checksum processing */
1177 /*
1178 * It is because the hardware accelerator does not support a checksum,
1179 * when the received data size is less than 64 bytes.
1180 */
1181 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
1182 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
1183 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1184 if (skb->protocol == htons(ETH_P_IP)) {
1185 struct iphdr *iph = ip_hdr(skb);
1186 unsigned int offset;
1187 offset = skb_transport_offset(skb);
1188 if (iph->protocol == IPPROTO_TCP) {
1189 skb->csum = 0;
1190 tcp_hdr(skb)->check = 0;
1191 skb->csum = skb_checksum(skb, offset,
1192 skb->len - offset, 0);
1193 tcp_hdr(skb)->check =
1194 csum_tcpudp_magic(iph->saddr,
1195 iph->daddr,
1196 skb->len - offset,
1197 IPPROTO_TCP,
1198 skb->csum);
1199 } else if (iph->protocol == IPPROTO_UDP) {
1200 skb->csum = 0;
1201 udp_hdr(skb)->check = 0;
1202 skb->csum =
1203 skb_checksum(skb, offset,
1204 skb->len - offset, 0);
1205 udp_hdr(skb)->check =
1206 csum_tcpudp_magic(iph->saddr,
1207 iph->daddr,
1208 skb->len - offset,
1209 IPPROTO_UDP,
1210 skb->csum);
1211 }
1212 }
1213 }
1214
1215 ring_num = tx_ring->next_to_use;
1216 if (unlikely((ring_num + 1) == tx_ring->count))
1217 tx_ring->next_to_use = 0;
1218 else
1219 tx_ring->next_to_use = ring_num + 1;
1220
1221
1222 buffer_info = &tx_ring->buffer_info[ring_num];
1223 tmp_skb = buffer_info->skb;
1224
1225 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */
1226 memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1227 tmp_skb->data[ETH_HLEN] = 0x00;
1228 tmp_skb->data[ETH_HLEN + 1] = 0x00;
1229 tmp_skb->len = skb->len;
1230 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1231 (skb->len - ETH_HLEN));
1232 /*-- Set Buffer information --*/
1233 buffer_info->length = tmp_skb->len;
1234 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1235 buffer_info->length,
1236 DMA_TO_DEVICE);
1237 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1238 netdev_err(adapter->netdev, "TX DMA map failed\n");
1239 buffer_info->dma = 0;
1240 buffer_info->time_stamp = 0;
1241 tx_ring->next_to_use = ring_num;
1242 return;
1243 }
1244 buffer_info->mapped = true;
1245 buffer_info->time_stamp = jiffies;
1246
1247 /*-- Set Tx descriptor --*/
1248 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1249 tx_desc->buffer_addr = (buffer_info->dma);
1250 tx_desc->length = (tmp_skb->len);
1251 tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1252 tx_desc->tx_frame_ctrl = (frame_ctrl);
1253 tx_desc->gbec_status = (DSC_INIT16);
1254
1255 if (unlikely(++ring_num == tx_ring->count))
1256 ring_num = 0;
1257
1258 /* Update software pointer of TX descriptor */
1259 iowrite32(tx_ring->dma +
1260 (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1261 &hw->reg->TX_DSC_SW_P);
1262
1263 pch_tx_timestamp(adapter, skb);
1264
1265 dev_kfree_skb_any(skb);
1266 }
1267
1268 /**
1269 * pch_gbe_update_stats - Update the board statistics counters
1270 * @adapter: Board private structure
1271 */
1272 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1273 {
1274 struct net_device *netdev = adapter->netdev;
1275 struct pci_dev *pdev = adapter->pdev;
1276 struct pch_gbe_hw_stats *stats = &adapter->stats;
1277 unsigned long flags;
1278
1279 /*
1280 * Prevent stats update while adapter is being reset, or if the pci
1281 * connection is down.
1282 */
1283 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1284 return;
1285
1286 spin_lock_irqsave(&adapter->stats_lock, flags);
1287
1288 /* Update device status "adapter->stats" */
1289 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1290 stats->tx_errors = stats->tx_length_errors +
1291 stats->tx_aborted_errors +
1292 stats->tx_carrier_errors + stats->tx_timeout_count;
1293
1294 /* Update network device status "adapter->net_stats" */
1295 netdev->stats.rx_packets = stats->rx_packets;
1296 netdev->stats.rx_bytes = stats->rx_bytes;
1297 netdev->stats.rx_dropped = stats->rx_dropped;
1298 netdev->stats.tx_packets = stats->tx_packets;
1299 netdev->stats.tx_bytes = stats->tx_bytes;
1300 netdev->stats.tx_dropped = stats->tx_dropped;
1301 /* Fill out the OS statistics structure */
1302 netdev->stats.multicast = stats->multicast;
1303 netdev->stats.collisions = stats->collisions;
1304 /* Rx Errors */
1305 netdev->stats.rx_errors = stats->rx_errors;
1306 netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1307 netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1308 /* Tx Errors */
1309 netdev->stats.tx_errors = stats->tx_errors;
1310 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1311 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1312
1313 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1314 }
1315
1316 static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
1317 {
1318 u32 rxdma;
1319
1320 /* Disable Receive DMA */
1321 rxdma = ioread32(&hw->reg->DMA_CTRL);
1322 rxdma &= ~PCH_GBE_RX_DMA_EN;
1323 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1324 }
1325
1326 static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
1327 {
1328 u32 rxdma;
1329
1330 /* Enables Receive DMA */
1331 rxdma = ioread32(&hw->reg->DMA_CTRL);
1332 rxdma |= PCH_GBE_RX_DMA_EN;
1333 iowrite32(rxdma, &hw->reg->DMA_CTRL);
1334 }
1335
1336 /**
1337 * pch_gbe_intr - Interrupt Handler
1338 * @irq: Interrupt number
1339 * @data: Pointer to a network interface device structure
1340 * Returns:
1341 * - IRQ_HANDLED: Our interrupt
1342 * - IRQ_NONE: Not our interrupt
1343 */
1344 static irqreturn_t pch_gbe_intr(int irq, void *data)
1345 {
1346 struct net_device *netdev = data;
1347 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1348 struct pch_gbe_hw *hw = &adapter->hw;
1349 u32 int_st;
1350 u32 int_en;
1351
1352 /* Check request status */
1353 int_st = ioread32(&hw->reg->INT_ST);
1354 int_st = int_st & ioread32(&hw->reg->INT_EN);
1355 /* When request status is no interruption factor */
1356 if (unlikely(!int_st))
1357 return IRQ_NONE; /* Not our interrupt. End processing. */
1358 netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st);
1359 if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1360 adapter->stats.intr_rx_frame_err_count++;
1361 if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1362 if (!adapter->rx_stop_flag) {
1363 adapter->stats.intr_rx_fifo_err_count++;
1364 netdev_dbg(netdev, "Rx fifo over run\n");
1365 adapter->rx_stop_flag = true;
1366 int_en = ioread32(&hw->reg->INT_EN);
1367 iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1368 &hw->reg->INT_EN);
1369 pch_gbe_disable_dma_rx(&adapter->hw);
1370 int_st |= ioread32(&hw->reg->INT_ST);
1371 int_st = int_st & ioread32(&hw->reg->INT_EN);
1372 }
1373 if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1374 adapter->stats.intr_rx_dma_err_count++;
1375 if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1376 adapter->stats.intr_tx_fifo_err_count++;
1377 if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1378 adapter->stats.intr_tx_dma_err_count++;
1379 if (int_st & PCH_GBE_INT_TCPIP_ERR)
1380 adapter->stats.intr_tcpip_err_count++;
1381 /* When Rx descriptor is empty */
1382 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1383 adapter->stats.intr_rx_dsc_empty_count++;
1384 netdev_dbg(netdev, "Rx descriptor is empty\n");
1385 int_en = ioread32(&hw->reg->INT_EN);
1386 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1387 if (hw->mac.tx_fc_enable) {
1388 /* Set Pause packet */
1389 pch_gbe_mac_set_pause_packet(hw);
1390 }
1391 }
1392
1393 /* When request status is Receive interruption */
1394 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
1395 (adapter->rx_stop_flag)) {
1396 if (likely(napi_schedule_prep(&adapter->napi))) {
1397 /* Enable only Rx Descriptor empty */
1398 atomic_inc(&adapter->irq_sem);
1399 int_en = ioread32(&hw->reg->INT_EN);
1400 int_en &=
1401 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1402 iowrite32(int_en, &hw->reg->INT_EN);
1403 /* Start polling for NAPI */
1404 __napi_schedule(&adapter->napi);
1405 }
1406 }
1407 netdev_dbg(netdev, "return = 0x%08x INT_EN reg = 0x%08x\n",
1408 IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1409 return IRQ_HANDLED;
1410 }
1411
1412 /**
1413 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1414 * @adapter: Board private structure
1415 * @rx_ring: Rx descriptor ring
1416 * @cleaned_count: Cleaned count
1417 */
1418 static void
1419 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1420 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1421 {
1422 struct net_device *netdev = adapter->netdev;
1423 struct pci_dev *pdev = adapter->pdev;
1424 struct pch_gbe_hw *hw = &adapter->hw;
1425 struct pch_gbe_rx_desc *rx_desc;
1426 struct pch_gbe_buffer *buffer_info;
1427 struct sk_buff *skb;
1428 unsigned int i;
1429 unsigned int bufsz;
1430
1431 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1432 i = rx_ring->next_to_use;
1433
1434 while ((cleaned_count--)) {
1435 buffer_info = &rx_ring->buffer_info[i];
1436 skb = netdev_alloc_skb(netdev, bufsz);
1437 if (unlikely(!skb)) {
1438 /* Better luck next round */
1439 adapter->stats.rx_alloc_buff_failed++;
1440 break;
1441 }
1442 /* align */
1443 skb_reserve(skb, NET_IP_ALIGN);
1444 buffer_info->skb = skb;
1445
1446 buffer_info->dma = dma_map_single(&pdev->dev,
1447 buffer_info->rx_buffer,
1448 buffer_info->length,
1449 DMA_FROM_DEVICE);
1450 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1451 dev_kfree_skb(skb);
1452 buffer_info->skb = NULL;
1453 buffer_info->dma = 0;
1454 adapter->stats.rx_alloc_buff_failed++;
1455 break; /* while !buffer_info->skb */
1456 }
1457 buffer_info->mapped = true;
1458 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1459 rx_desc->buffer_addr = (buffer_info->dma);
1460 rx_desc->gbec_status = DSC_INIT16;
1461
1462 netdev_dbg(netdev,
1463 "i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n",
1464 i, (unsigned long long)buffer_info->dma,
1465 buffer_info->length);
1466
1467 if (unlikely(++i == rx_ring->count))
1468 i = 0;
1469 }
1470 if (likely(rx_ring->next_to_use != i)) {
1471 rx_ring->next_to_use = i;
1472 if (unlikely(i-- == 0))
1473 i = (rx_ring->count - 1);
1474 iowrite32(rx_ring->dma +
1475 (int)sizeof(struct pch_gbe_rx_desc) * i,
1476 &hw->reg->RX_DSC_SW_P);
1477 }
1478 return;
1479 }
1480
1481 static int
1482 pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1483 struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1484 {
1485 struct pci_dev *pdev = adapter->pdev;
1486 struct pch_gbe_buffer *buffer_info;
1487 unsigned int i;
1488 unsigned int bufsz;
1489 unsigned int size;
1490
1491 bufsz = adapter->rx_buffer_len;
1492
1493 size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1494 rx_ring->rx_buff_pool =
1495 dma_zalloc_coherent(&pdev->dev, size,
1496 &rx_ring->rx_buff_pool_logic, GFP_KERNEL);
1497 if (!rx_ring->rx_buff_pool)
1498 return -ENOMEM;
1499
1500 rx_ring->rx_buff_pool_size = size;
1501 for (i = 0; i < rx_ring->count; i++) {
1502 buffer_info = &rx_ring->buffer_info[i];
1503 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1504 buffer_info->length = bufsz;
1505 }
1506 return 0;
1507 }
1508
1509 /**
1510 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1511 * @adapter: Board private structure
1512 * @tx_ring: Tx descriptor ring
1513 */
1514 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1515 struct pch_gbe_tx_ring *tx_ring)
1516 {
1517 struct pch_gbe_buffer *buffer_info;
1518 struct sk_buff *skb;
1519 unsigned int i;
1520 unsigned int bufsz;
1521 struct pch_gbe_tx_desc *tx_desc;
1522
1523 bufsz =
1524 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1525
1526 for (i = 0; i < tx_ring->count; i++) {
1527 buffer_info = &tx_ring->buffer_info[i];
1528 skb = netdev_alloc_skb(adapter->netdev, bufsz);
1529 skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1530 buffer_info->skb = skb;
1531 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1532 tx_desc->gbec_status = (DSC_INIT16);
1533 }
1534 return;
1535 }
1536
1537 /**
1538 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1539 * @adapter: Board private structure
1540 * @tx_ring: Tx descriptor ring
1541 * Returns:
1542 * true: Cleaned the descriptor
1543 * false: Not cleaned the descriptor
1544 */
1545 static bool
1546 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1547 struct pch_gbe_tx_ring *tx_ring)
1548 {
1549 struct pch_gbe_tx_desc *tx_desc;
1550 struct pch_gbe_buffer *buffer_info;
1551 struct sk_buff *skb;
1552 unsigned int i;
1553 unsigned int cleaned_count = 0;
1554 bool cleaned = false;
1555 int unused, thresh;
1556
1557 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1558 tx_ring->next_to_clean);
1559
1560 i = tx_ring->next_to_clean;
1561 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1562 netdev_dbg(adapter->netdev, "gbec_status:0x%04x dma_status:0x%04x\n",
1563 tx_desc->gbec_status, tx_desc->dma_status);
1564
1565 unused = PCH_GBE_DESC_UNUSED(tx_ring);
1566 thresh = tx_ring->count - PCH_GBE_TX_WEIGHT;
1567 if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh))
1568 { /* current marked clean, tx queue filling up, do extra clean */
1569 int j, k;
1570 if (unused < 8) { /* tx queue nearly full */
1571 netdev_dbg(adapter->netdev,
1572 "clean_tx: transmit queue warning (%x,%x) unused=%d\n",
1573 tx_ring->next_to_clean, tx_ring->next_to_use,
1574 unused);
1575 }
1576
1577 /* current marked clean, scan for more that need cleaning. */
1578 k = i;
1579 for (j = 0; j < PCH_GBE_TX_WEIGHT; j++)
1580 {
1581 tx_desc = PCH_GBE_TX_DESC(*tx_ring, k);
1582 if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/
1583 if (++k >= tx_ring->count) k = 0; /*increment, wrap*/
1584 }
1585 if (j < PCH_GBE_TX_WEIGHT) {
1586 netdev_dbg(adapter->netdev,
1587 "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n",
1588 unused, j, i, k, tx_ring->next_to_use,
1589 tx_desc->gbec_status);
1590 i = k; /*found one to clean, usu gbec_status==2000.*/
1591 }
1592 }
1593
1594 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1595 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n",
1596 tx_desc->gbec_status);
1597 buffer_info = &tx_ring->buffer_info[i];
1598 skb = buffer_info->skb;
1599 cleaned = true;
1600
1601 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1602 adapter->stats.tx_aborted_errors++;
1603 netdev_err(adapter->netdev, "Transfer Abort Error\n");
1604 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1605 ) {
1606 adapter->stats.tx_carrier_errors++;
1607 netdev_err(adapter->netdev,
1608 "Transfer Carrier Sense Error\n");
1609 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1610 ) {
1611 adapter->stats.tx_aborted_errors++;
1612 netdev_err(adapter->netdev,
1613 "Transfer Collision Abort Error\n");
1614 } else if ((tx_desc->gbec_status &
1615 (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1616 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1617 adapter->stats.collisions++;
1618 adapter->stats.tx_packets++;
1619 adapter->stats.tx_bytes += skb->len;
1620 netdev_dbg(adapter->netdev, "Transfer Collision\n");
1621 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1622 ) {
1623 adapter->stats.tx_packets++;
1624 adapter->stats.tx_bytes += skb->len;
1625 }
1626 if (buffer_info->mapped) {
1627 netdev_dbg(adapter->netdev,
1628 "unmap buffer_info->dma : %d\n", i);
1629 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1630 buffer_info->length, DMA_TO_DEVICE);
1631 buffer_info->mapped = false;
1632 }
1633 if (buffer_info->skb) {
1634 netdev_dbg(adapter->netdev,
1635 "trim buffer_info->skb : %d\n", i);
1636 skb_trim(buffer_info->skb, 0);
1637 }
1638 tx_desc->gbec_status = DSC_INIT16;
1639 if (unlikely(++i == tx_ring->count))
1640 i = 0;
1641 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1642
1643 /* weight of a sort for tx, to avoid endless transmit cleanup */
1644 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1645 cleaned = false;
1646 break;
1647 }
1648 }
1649 netdev_dbg(adapter->netdev,
1650 "called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1651 cleaned_count);
1652 if (cleaned_count > 0) { /*skip this if nothing cleaned*/
1653 /* Recover from running out of Tx resources in xmit_frame */
1654 spin_lock(&tx_ring->tx_lock);
1655 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev))))
1656 {
1657 netif_wake_queue(adapter->netdev);
1658 adapter->stats.tx_restart_count++;
1659 netdev_dbg(adapter->netdev, "Tx wake queue\n");
1660 }
1661
1662 tx_ring->next_to_clean = i;
1663
1664 netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1665 tx_ring->next_to_clean);
1666 spin_unlock(&tx_ring->tx_lock);
1667 }
1668 return cleaned;
1669 }
1670
1671 /**
1672 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1673 * @adapter: Board private structure
1674 * @rx_ring: Rx descriptor ring
1675 * @work_done: Completed count
1676 * @work_to_do: Request count
1677 * Returns:
1678 * true: Cleaned the descriptor
1679 * false: Not cleaned the descriptor
1680 */
1681 static bool
1682 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1683 struct pch_gbe_rx_ring *rx_ring,
1684 int *work_done, int work_to_do)
1685 {
1686 struct net_device *netdev = adapter->netdev;
1687 struct pci_dev *pdev = adapter->pdev;
1688 struct pch_gbe_buffer *buffer_info;
1689 struct pch_gbe_rx_desc *rx_desc;
1690 u32 length;
1691 unsigned int i;
1692 unsigned int cleaned_count = 0;
1693 bool cleaned = false;
1694 struct sk_buff *skb;
1695 u8 dma_status;
1696 u16 gbec_status;
1697 u32 tcp_ip_status;
1698
1699 i = rx_ring->next_to_clean;
1700
1701 while (*work_done < work_to_do) {
1702 /* Check Rx descriptor status */
1703 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1704 if (rx_desc->gbec_status == DSC_INIT16)
1705 break;
1706 cleaned = true;
1707 cleaned_count++;
1708
1709 dma_status = rx_desc->dma_status;
1710 gbec_status = rx_desc->gbec_status;
1711 tcp_ip_status = rx_desc->tcp_ip_status;
1712 rx_desc->gbec_status = DSC_INIT16;
1713 buffer_info = &rx_ring->buffer_info[i];
1714 skb = buffer_info->skb;
1715 buffer_info->skb = NULL;
1716
1717 /* unmap dma */
1718 dma_unmap_single(&pdev->dev, buffer_info->dma,
1719 buffer_info->length, DMA_FROM_DEVICE);
1720 buffer_info->mapped = false;
1721
1722 netdev_dbg(netdev,
1723 "RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x] BufInf = 0x%p\n",
1724 i, dma_status, gbec_status, tcp_ip_status,
1725 buffer_info);
1726 /* Error check */
1727 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1728 adapter->stats.rx_frame_errors++;
1729 netdev_err(netdev, "Receive Not Octal Error\n");
1730 } else if (unlikely(gbec_status &
1731 PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1732 adapter->stats.rx_frame_errors++;
1733 netdev_err(netdev, "Receive Nibble Error\n");
1734 } else if (unlikely(gbec_status &
1735 PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1736 adapter->stats.rx_crc_errors++;
1737 netdev_err(netdev, "Receive CRC Error\n");
1738 } else {
1739 /* get receive length */
1740 /* length convert[-3], length includes FCS length */
1741 length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1742 if (rx_desc->rx_words_eob & 0x02)
1743 length = length - 4;
1744 /*
1745 * buffer_info->rx_buffer: [Header:14][payload]
1746 * skb->data: [Reserve:2][Header:14][payload]
1747 */
1748 memcpy(skb->data, buffer_info->rx_buffer, length);
1749
1750 /* update status of driver */
1751 adapter->stats.rx_bytes += length;
1752 adapter->stats.rx_packets++;
1753 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1754 adapter->stats.multicast++;
1755 /* Write meta date of skb */
1756 skb_put(skb, length);
1757
1758 pch_rx_timestamp(adapter, skb);
1759
1760 skb->protocol = eth_type_trans(skb, netdev);
1761 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1762 skb->ip_summed = CHECKSUM_UNNECESSARY;
1763 else
1764 skb->ip_summed = CHECKSUM_NONE;
1765
1766 napi_gro_receive(&adapter->napi, skb);
1767 (*work_done)++;
1768 netdev_dbg(netdev,
1769 "Receive skb->ip_summed: %d length: %d\n",
1770 skb->ip_summed, length);
1771 }
1772 /* return some buffers to hardware, one at a time is too slow */
1773 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1774 pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1775 cleaned_count);
1776 cleaned_count = 0;
1777 }
1778 if (++i == rx_ring->count)
1779 i = 0;
1780 }
1781 rx_ring->next_to_clean = i;
1782 if (cleaned_count)
1783 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1784 return cleaned;
1785 }
1786
1787 /**
1788 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1789 * @adapter: Board private structure
1790 * @tx_ring: Tx descriptor ring (for a specific queue) to setup
1791 * Returns:
1792 * 0: Successfully
1793 * Negative value: Failed
1794 */
1795 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1796 struct pch_gbe_tx_ring *tx_ring)
1797 {
1798 struct pci_dev *pdev = adapter->pdev;
1799 struct pch_gbe_tx_desc *tx_desc;
1800 int size;
1801 int desNo;
1802
1803 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1804 tx_ring->buffer_info = vzalloc(size);
1805 if (!tx_ring->buffer_info)
1806 return -ENOMEM;
1807
1808 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1809
1810 tx_ring->desc = dma_zalloc_coherent(&pdev->dev, tx_ring->size,
1811 &tx_ring->dma, GFP_KERNEL);
1812 if (!tx_ring->desc) {
1813 vfree(tx_ring->buffer_info);
1814 return -ENOMEM;
1815 }
1816
1817 tx_ring->next_to_use = 0;
1818 tx_ring->next_to_clean = 0;
1819 spin_lock_init(&tx_ring->tx_lock);
1820
1821 for (desNo = 0; desNo < tx_ring->count; desNo++) {
1822 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1823 tx_desc->gbec_status = DSC_INIT16;
1824 }
1825 netdev_dbg(adapter->netdev,
1826 "tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1827 tx_ring->desc, (unsigned long long)tx_ring->dma,
1828 tx_ring->next_to_clean, tx_ring->next_to_use);
1829 return 0;
1830 }
1831
1832 /**
1833 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1834 * @adapter: Board private structure
1835 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1836 * Returns:
1837 * 0: Successfully
1838 * Negative value: Failed
1839 */
1840 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1841 struct pch_gbe_rx_ring *rx_ring)
1842 {
1843 struct pci_dev *pdev = adapter->pdev;
1844 struct pch_gbe_rx_desc *rx_desc;
1845 int size;
1846 int desNo;
1847
1848 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1849 rx_ring->buffer_info = vzalloc(size);
1850 if (!rx_ring->buffer_info)
1851 return -ENOMEM;
1852
1853 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1854 rx_ring->desc = dma_zalloc_coherent(&pdev->dev, rx_ring->size,
1855 &rx_ring->dma, GFP_KERNEL);
1856 if (!rx_ring->desc) {
1857 vfree(rx_ring->buffer_info);
1858 return -ENOMEM;
1859 }
1860 rx_ring->next_to_clean = 0;
1861 rx_ring->next_to_use = 0;
1862 for (desNo = 0; desNo < rx_ring->count; desNo++) {
1863 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1864 rx_desc->gbec_status = DSC_INIT16;
1865 }
1866 netdev_dbg(adapter->netdev,
1867 "rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n",
1868 rx_ring->desc, (unsigned long long)rx_ring->dma,
1869 rx_ring->next_to_clean, rx_ring->next_to_use);
1870 return 0;
1871 }
1872
1873 /**
1874 * pch_gbe_free_tx_resources - Free Tx Resources
1875 * @adapter: Board private structure
1876 * @tx_ring: Tx descriptor ring for a specific queue
1877 */
1878 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1879 struct pch_gbe_tx_ring *tx_ring)
1880 {
1881 struct pci_dev *pdev = adapter->pdev;
1882
1883 pch_gbe_clean_tx_ring(adapter, tx_ring);
1884 vfree(tx_ring->buffer_info);
1885 tx_ring->buffer_info = NULL;
1886 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1887 tx_ring->desc = NULL;
1888 }
1889
1890 /**
1891 * pch_gbe_free_rx_resources - Free Rx Resources
1892 * @adapter: Board private structure
1893 * @rx_ring: Ring to clean the resources from
1894 */
1895 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1896 struct pch_gbe_rx_ring *rx_ring)
1897 {
1898 struct pci_dev *pdev = adapter->pdev;
1899
1900 pch_gbe_clean_rx_ring(adapter, rx_ring);
1901 vfree(rx_ring->buffer_info);
1902 rx_ring->buffer_info = NULL;
1903 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1904 rx_ring->desc = NULL;
1905 }
1906
1907 /**
1908 * pch_gbe_request_irq - Allocate an interrupt line
1909 * @adapter: Board private structure
1910 * Returns:
1911 * 0: Successfully
1912 * Negative value: Failed
1913 */
1914 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1915 {
1916 struct net_device *netdev = adapter->netdev;
1917 int err;
1918 int flags;
1919
1920 flags = IRQF_SHARED;
1921 adapter->have_msi = false;
1922 err = pci_enable_msi(adapter->pdev);
1923 netdev_dbg(netdev, "call pci_enable_msi\n");
1924 if (err) {
1925 netdev_dbg(netdev, "call pci_enable_msi - Error: %d\n", err);
1926 } else {
1927 flags = 0;
1928 adapter->have_msi = true;
1929 }
1930 err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1931 flags, netdev->name, netdev);
1932 if (err)
1933 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n",
1934 err);
1935 netdev_dbg(netdev,
1936 "adapter->have_msi : %d flags : 0x%04x return : 0x%04x\n",
1937 adapter->have_msi, flags, err);
1938 return err;
1939 }
1940
1941
1942 /**
1943 * pch_gbe_up - Up GbE network device
1944 * @adapter: Board private structure
1945 * Returns:
1946 * 0: Successfully
1947 * Negative value: Failed
1948 */
1949 int pch_gbe_up(struct pch_gbe_adapter *adapter)
1950 {
1951 struct net_device *netdev = adapter->netdev;
1952 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1953 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1954 int err = -EINVAL;
1955
1956 /* Ensure we have a valid MAC */
1957 if (!is_valid_ether_addr(adapter->hw.mac.addr)) {
1958 netdev_err(netdev, "Error: Invalid MAC address\n");
1959 goto out;
1960 }
1961
1962 /* hardware has been reset, we need to reload some things */
1963 pch_gbe_set_multi(netdev);
1964
1965 pch_gbe_setup_tctl(adapter);
1966 pch_gbe_configure_tx(adapter);
1967 pch_gbe_setup_rctl(adapter);
1968 pch_gbe_configure_rx(adapter);
1969
1970 err = pch_gbe_request_irq(adapter);
1971 if (err) {
1972 netdev_err(netdev,
1973 "Error: can't bring device up - irq request failed\n");
1974 goto out;
1975 }
1976 err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1977 if (err) {
1978 netdev_err(netdev,
1979 "Error: can't bring device up - alloc rx buffers pool failed\n");
1980 goto freeirq;
1981 }
1982 pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1983 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1984 adapter->tx_queue_len = netdev->tx_queue_len;
1985 pch_gbe_enable_dma_rx(&adapter->hw);
1986 pch_gbe_enable_mac_rx(&adapter->hw);
1987
1988 mod_timer(&adapter->watchdog_timer, jiffies);
1989
1990 napi_enable(&adapter->napi);
1991 pch_gbe_irq_enable(adapter);
1992 netif_start_queue(adapter->netdev);
1993
1994 return 0;
1995
1996 freeirq:
1997 pch_gbe_free_irq(adapter);
1998 out:
1999 return err;
2000 }
2001
2002 /**
2003 * pch_gbe_down - Down GbE network device
2004 * @adapter: Board private structure
2005 */
2006 void pch_gbe_down(struct pch_gbe_adapter *adapter)
2007 {
2008 struct net_device *netdev = adapter->netdev;
2009 struct pci_dev *pdev = adapter->pdev;
2010 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
2011
2012 /* signal that we're down so the interrupt handler does not
2013 * reschedule our watchdog timer */
2014 napi_disable(&adapter->napi);
2015 atomic_set(&adapter->irq_sem, 0);
2016
2017 pch_gbe_irq_disable(adapter);
2018 pch_gbe_free_irq(adapter);
2019
2020 del_timer_sync(&adapter->watchdog_timer);
2021
2022 netdev->tx_queue_len = adapter->tx_queue_len;
2023 netif_carrier_off(netdev);
2024 netif_stop_queue(netdev);
2025
2026 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
2027 pch_gbe_reset(adapter);
2028 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
2029 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
2030
2031 pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
2032 rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
2033 rx_ring->rx_buff_pool_logic = 0;
2034 rx_ring->rx_buff_pool_size = 0;
2035 rx_ring->rx_buff_pool = NULL;
2036 }
2037
2038 /**
2039 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
2040 * @adapter: Board private structure to initialize
2041 * Returns:
2042 * 0: Successfully
2043 * Negative value: Failed
2044 */
2045 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
2046 {
2047 struct pch_gbe_hw *hw = &adapter->hw;
2048 struct net_device *netdev = adapter->netdev;
2049
2050 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2051 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2052 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2053
2054 /* Initialize the hardware-specific values */
2055 if (pch_gbe_hal_setup_init_funcs(hw)) {
2056 netdev_err(netdev, "Hardware Initialization Failure\n");
2057 return -EIO;
2058 }
2059 if (pch_gbe_alloc_queues(adapter)) {
2060 netdev_err(netdev, "Unable to allocate memory for queues\n");
2061 return -ENOMEM;
2062 }
2063 spin_lock_init(&adapter->hw.miim_lock);
2064 spin_lock_init(&adapter->stats_lock);
2065 spin_lock_init(&adapter->ethtool_lock);
2066 atomic_set(&adapter->irq_sem, 0);
2067 pch_gbe_irq_disable(adapter);
2068
2069 pch_gbe_init_stats(adapter);
2070
2071 netdev_dbg(netdev,
2072 "rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n",
2073 (u32) adapter->rx_buffer_len,
2074 hw->mac.min_frame_size, hw->mac.max_frame_size);
2075 return 0;
2076 }
2077
2078 /**
2079 * pch_gbe_open - Called when a network interface is made active
2080 * @netdev: Network interface device structure
2081 * Returns:
2082 * 0: Successfully
2083 * Negative value: Failed
2084 */
2085 static int pch_gbe_open(struct net_device *netdev)
2086 {
2087 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2088 struct pch_gbe_hw *hw = &adapter->hw;
2089 int err;
2090
2091 /* allocate transmit descriptors */
2092 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
2093 if (err)
2094 goto err_setup_tx;
2095 /* allocate receive descriptors */
2096 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
2097 if (err)
2098 goto err_setup_rx;
2099 pch_gbe_hal_power_up_phy(hw);
2100 err = pch_gbe_up(adapter);
2101 if (err)
2102 goto err_up;
2103 netdev_dbg(netdev, "Success End\n");
2104 return 0;
2105
2106 err_up:
2107 if (!adapter->wake_up_evt)
2108 pch_gbe_hal_power_down_phy(hw);
2109 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2110 err_setup_rx:
2111 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2112 err_setup_tx:
2113 pch_gbe_reset(adapter);
2114 netdev_err(netdev, "Error End\n");
2115 return err;
2116 }
2117
2118 /**
2119 * pch_gbe_stop - Disables a network interface
2120 * @netdev: Network interface device structure
2121 * Returns:
2122 * 0: Successfully
2123 */
2124 static int pch_gbe_stop(struct net_device *netdev)
2125 {
2126 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2127 struct pch_gbe_hw *hw = &adapter->hw;
2128
2129 pch_gbe_down(adapter);
2130 if (!adapter->wake_up_evt)
2131 pch_gbe_hal_power_down_phy(hw);
2132 pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2133 pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2134 return 0;
2135 }
2136
2137 /**
2138 * pch_gbe_xmit_frame - Packet transmitting start
2139 * @skb: Socket buffer structure
2140 * @netdev: Network interface device structure
2141 * Returns:
2142 * - NETDEV_TX_OK: Normal end
2143 * - NETDEV_TX_BUSY: Error end
2144 */
2145 static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2146 {
2147 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2148 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
2149 unsigned long flags;
2150
2151 if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
2152 /* Collision - tell upper layer to requeue */
2153 return NETDEV_TX_LOCKED;
2154 }
2155 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
2156 netif_stop_queue(netdev);
2157 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
2158 netdev_dbg(netdev,
2159 "Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n",
2160 tx_ring->next_to_use, tx_ring->next_to_clean);
2161 return NETDEV_TX_BUSY;
2162 }
2163
2164 /* CRC,ITAG no support */
2165 pch_gbe_tx_queue(adapter, tx_ring, skb);
2166 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
2167 return NETDEV_TX_OK;
2168 }
2169
2170 /**
2171 * pch_gbe_get_stats - Get System Network Statistics
2172 * @netdev: Network interface device structure
2173 * Returns: The current stats
2174 */
2175 static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
2176 {
2177 /* only return the current stats */
2178 return &netdev->stats;
2179 }
2180
2181 /**
2182 * pch_gbe_set_multi - Multicast and Promiscuous mode set
2183 * @netdev: Network interface device structure
2184 */
2185 static void pch_gbe_set_multi(struct net_device *netdev)
2186 {
2187 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2188 struct pch_gbe_hw *hw = &adapter->hw;
2189 struct netdev_hw_addr *ha;
2190 u8 *mta_list;
2191 u32 rctl;
2192 int i;
2193 int mc_count;
2194
2195 netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
2196
2197 /* Check for Promiscuous and All Multicast modes */
2198 rctl = ioread32(&hw->reg->RX_MODE);
2199 mc_count = netdev_mc_count(netdev);
2200 if ((netdev->flags & IFF_PROMISC)) {
2201 rctl &= ~PCH_GBE_ADD_FIL_EN;
2202 rctl &= ~PCH_GBE_MLT_FIL_EN;
2203 } else if ((netdev->flags & IFF_ALLMULTI)) {
2204 /* all the multicasting receive permissions */
2205 rctl |= PCH_GBE_ADD_FIL_EN;
2206 rctl &= ~PCH_GBE_MLT_FIL_EN;
2207 } else {
2208 if (mc_count >= PCH_GBE_MAR_ENTRIES) {
2209 /* all the multicasting receive permissions */
2210 rctl |= PCH_GBE_ADD_FIL_EN;
2211 rctl &= ~PCH_GBE_MLT_FIL_EN;
2212 } else {
2213 rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
2214 }
2215 }
2216 iowrite32(rctl, &hw->reg->RX_MODE);
2217
2218 if (mc_count >= PCH_GBE_MAR_ENTRIES)
2219 return;
2220 mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
2221 if (!mta_list)
2222 return;
2223
2224 /* The shared function expects a packed array of only addresses. */
2225 i = 0;
2226 netdev_for_each_mc_addr(ha, netdev) {
2227 if (i == mc_count)
2228 break;
2229 memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
2230 }
2231 pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
2232 PCH_GBE_MAR_ENTRIES);
2233 kfree(mta_list);
2234
2235 netdev_dbg(netdev,
2236 "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n",
2237 ioread32(&hw->reg->RX_MODE), mc_count);
2238 }
2239
2240 /**
2241 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2242 * @netdev: Network interface device structure
2243 * @addr: Pointer to an address structure
2244 * Returns:
2245 * 0: Successfully
2246 * -EADDRNOTAVAIL: Failed
2247 */
2248 static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2249 {
2250 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2251 struct sockaddr *skaddr = addr;
2252 int ret_val;
2253
2254 if (!is_valid_ether_addr(skaddr->sa_data)) {
2255 ret_val = -EADDRNOTAVAIL;
2256 } else {
2257 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2258 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2259 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2260 ret_val = 0;
2261 }
2262 netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val);
2263 netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr);
2264 netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr);
2265 netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2266 ioread32(&adapter->hw.reg->mac_adr[0].high),
2267 ioread32(&adapter->hw.reg->mac_adr[0].low));
2268 return ret_val;
2269 }
2270
2271 /**
2272 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2273 * @netdev: Network interface device structure
2274 * @new_mtu: New value for maximum frame size
2275 * Returns:
2276 * 0: Successfully
2277 * -EINVAL: Failed
2278 */
2279 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2280 {
2281 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2282 int max_frame;
2283 unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2284 int err;
2285
2286 max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2287 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2288 (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2289 netdev_err(netdev, "Invalid MTU setting\n");
2290 return -EINVAL;
2291 }
2292 if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2293 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2294 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2295 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2296 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2297 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2298 else
2299 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
2300
2301 if (netif_running(netdev)) {
2302 pch_gbe_down(adapter);
2303 err = pch_gbe_up(adapter);
2304 if (err) {
2305 adapter->rx_buffer_len = old_rx_buffer_len;
2306 pch_gbe_up(adapter);
2307 return err;
2308 } else {
2309 netdev->mtu = new_mtu;
2310 adapter->hw.mac.max_frame_size = max_frame;
2311 }
2312 } else {
2313 pch_gbe_reset(adapter);
2314 netdev->mtu = new_mtu;
2315 adapter->hw.mac.max_frame_size = max_frame;
2316 }
2317
2318 netdev_dbg(netdev,
2319 "max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n",
2320 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2321 adapter->hw.mac.max_frame_size);
2322 return 0;
2323 }
2324
2325 /**
2326 * pch_gbe_set_features - Reset device after features changed
2327 * @netdev: Network interface device structure
2328 * @features: New features
2329 * Returns:
2330 * 0: HW state updated successfully
2331 */
2332 static int pch_gbe_set_features(struct net_device *netdev,
2333 netdev_features_t features)
2334 {
2335 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2336 netdev_features_t changed = features ^ netdev->features;
2337
2338 if (!(changed & NETIF_F_RXCSUM))
2339 return 0;
2340
2341 if (netif_running(netdev))
2342 pch_gbe_reinit_locked(adapter);
2343 else
2344 pch_gbe_reset(adapter);
2345
2346 return 0;
2347 }
2348
2349 /**
2350 * pch_gbe_ioctl - Controls register through a MII interface
2351 * @netdev: Network interface device structure
2352 * @ifr: Pointer to ifr structure
2353 * @cmd: Control command
2354 * Returns:
2355 * 0: Successfully
2356 * Negative value: Failed
2357 */
2358 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2359 {
2360 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2361
2362 netdev_dbg(netdev, "cmd : 0x%04x\n", cmd);
2363
2364 if (cmd == SIOCSHWTSTAMP)
2365 return hwtstamp_ioctl(netdev, ifr, cmd);
2366
2367 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2368 }
2369
2370 /**
2371 * pch_gbe_tx_timeout - Respond to a Tx Hang
2372 * @netdev: Network interface device structure
2373 */
2374 static void pch_gbe_tx_timeout(struct net_device *netdev)
2375 {
2376 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2377
2378 /* Do the reset outside of interrupt context */
2379 adapter->stats.tx_timeout_count++;
2380 schedule_work(&adapter->reset_task);
2381 }
2382
2383 /**
2384 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2385 * @napi: Pointer of polling device struct
2386 * @budget: The maximum number of a packet
2387 * Returns:
2388 * false: Exit the polling mode
2389 * true: Continue the polling mode
2390 */
2391 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2392 {
2393 struct pch_gbe_adapter *adapter =
2394 container_of(napi, struct pch_gbe_adapter, napi);
2395 int work_done = 0;
2396 bool poll_end_flag = false;
2397 bool cleaned = false;
2398
2399 netdev_dbg(adapter->netdev, "budget : %d\n", budget);
2400
2401 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2402 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2403
2404 if (cleaned)
2405 work_done = budget;
2406 /* If no Tx and not enough Rx work done,
2407 * exit the polling mode
2408 */
2409 if (work_done < budget)
2410 poll_end_flag = true;
2411
2412 if (poll_end_flag) {
2413 napi_complete(napi);
2414 pch_gbe_irq_enable(adapter);
2415 }
2416
2417 if (adapter->rx_stop_flag) {
2418 adapter->rx_stop_flag = false;
2419 pch_gbe_enable_dma_rx(&adapter->hw);
2420 }
2421
2422 netdev_dbg(adapter->netdev,
2423 "poll_end_flag : %d work_done : %d budget : %d\n",
2424 poll_end_flag, work_done, budget);
2425
2426 return work_done;
2427 }
2428
2429 #ifdef CONFIG_NET_POLL_CONTROLLER
2430 /**
2431 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2432 * @netdev: Network interface device structure
2433 */
2434 static void pch_gbe_netpoll(struct net_device *netdev)
2435 {
2436 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2437
2438 disable_irq(adapter->pdev->irq);
2439 pch_gbe_intr(adapter->pdev->irq, netdev);
2440 enable_irq(adapter->pdev->irq);
2441 }
2442 #endif
2443
2444 static const struct net_device_ops pch_gbe_netdev_ops = {
2445 .ndo_open = pch_gbe_open,
2446 .ndo_stop = pch_gbe_stop,
2447 .ndo_start_xmit = pch_gbe_xmit_frame,
2448 .ndo_get_stats = pch_gbe_get_stats,
2449 .ndo_set_mac_address = pch_gbe_set_mac,
2450 .ndo_tx_timeout = pch_gbe_tx_timeout,
2451 .ndo_change_mtu = pch_gbe_change_mtu,
2452 .ndo_set_features = pch_gbe_set_features,
2453 .ndo_do_ioctl = pch_gbe_ioctl,
2454 .ndo_set_rx_mode = pch_gbe_set_multi,
2455 #ifdef CONFIG_NET_POLL_CONTROLLER
2456 .ndo_poll_controller = pch_gbe_netpoll,
2457 #endif
2458 };
2459
2460 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2461 pci_channel_state_t state)
2462 {
2463 struct net_device *netdev = pci_get_drvdata(pdev);
2464 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2465
2466 netif_device_detach(netdev);
2467 if (netif_running(netdev))
2468 pch_gbe_down(adapter);
2469 pci_disable_device(pdev);
2470 /* Request a slot slot reset. */
2471 return PCI_ERS_RESULT_NEED_RESET;
2472 }
2473
2474 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2475 {
2476 struct net_device *netdev = pci_get_drvdata(pdev);
2477 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2478 struct pch_gbe_hw *hw = &adapter->hw;
2479
2480 if (pci_enable_device(pdev)) {
2481 netdev_err(netdev, "Cannot re-enable PCI device after reset\n");
2482 return PCI_ERS_RESULT_DISCONNECT;
2483 }
2484 pci_set_master(pdev);
2485 pci_enable_wake(pdev, PCI_D0, 0);
2486 pch_gbe_hal_power_up_phy(hw);
2487 pch_gbe_reset(adapter);
2488 /* Clear wake up status */
2489 pch_gbe_mac_set_wol_event(hw, 0);
2490
2491 return PCI_ERS_RESULT_RECOVERED;
2492 }
2493
2494 static void pch_gbe_io_resume(struct pci_dev *pdev)
2495 {
2496 struct net_device *netdev = pci_get_drvdata(pdev);
2497 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2498
2499 if (netif_running(netdev)) {
2500 if (pch_gbe_up(adapter)) {
2501 netdev_dbg(netdev,
2502 "can't bring device back up after reset\n");
2503 return;
2504 }
2505 }
2506 netif_device_attach(netdev);
2507 }
2508
2509 static int __pch_gbe_suspend(struct pci_dev *pdev)
2510 {
2511 struct net_device *netdev = pci_get_drvdata(pdev);
2512 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2513 struct pch_gbe_hw *hw = &adapter->hw;
2514 u32 wufc = adapter->wake_up_evt;
2515 int retval = 0;
2516
2517 netif_device_detach(netdev);
2518 if (netif_running(netdev))
2519 pch_gbe_down(adapter);
2520 if (wufc) {
2521 pch_gbe_set_multi(netdev);
2522 pch_gbe_setup_rctl(adapter);
2523 pch_gbe_configure_rx(adapter);
2524 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2525 hw->mac.link_duplex);
2526 pch_gbe_set_mode(adapter, hw->mac.link_speed,
2527 hw->mac.link_duplex);
2528 pch_gbe_mac_set_wol_event(hw, wufc);
2529 pci_disable_device(pdev);
2530 } else {
2531 pch_gbe_hal_power_down_phy(hw);
2532 pch_gbe_mac_set_wol_event(hw, wufc);
2533 pci_disable_device(pdev);
2534 }
2535 return retval;
2536 }
2537
2538 #ifdef CONFIG_PM
2539 static int pch_gbe_suspend(struct device *device)
2540 {
2541 struct pci_dev *pdev = to_pci_dev(device);
2542
2543 return __pch_gbe_suspend(pdev);
2544 }
2545
2546 static int pch_gbe_resume(struct device *device)
2547 {
2548 struct pci_dev *pdev = to_pci_dev(device);
2549 struct net_device *netdev = pci_get_drvdata(pdev);
2550 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2551 struct pch_gbe_hw *hw = &adapter->hw;
2552 u32 err;
2553
2554 err = pci_enable_device(pdev);
2555 if (err) {
2556 netdev_err(netdev, "Cannot enable PCI device from suspend\n");
2557 return err;
2558 }
2559 pci_set_master(pdev);
2560 pch_gbe_hal_power_up_phy(hw);
2561 pch_gbe_reset(adapter);
2562 /* Clear wake on lan control and status */
2563 pch_gbe_mac_set_wol_event(hw, 0);
2564
2565 if (netif_running(netdev))
2566 pch_gbe_up(adapter);
2567 netif_device_attach(netdev);
2568
2569 return 0;
2570 }
2571 #endif /* CONFIG_PM */
2572
2573 static void pch_gbe_shutdown(struct pci_dev *pdev)
2574 {
2575 __pch_gbe_suspend(pdev);
2576 if (system_state == SYSTEM_POWER_OFF) {
2577 pci_wake_from_d3(pdev, true);
2578 pci_set_power_state(pdev, PCI_D3hot);
2579 }
2580 }
2581
2582 static void pch_gbe_remove(struct pci_dev *pdev)
2583 {
2584 struct net_device *netdev = pci_get_drvdata(pdev);
2585 struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2586
2587 cancel_work_sync(&adapter->reset_task);
2588 unregister_netdev(netdev);
2589
2590 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2591
2592 free_netdev(netdev);
2593 }
2594
2595 static int pch_gbe_probe(struct pci_dev *pdev,
2596 const struct pci_device_id *pci_id)
2597 {
2598 struct net_device *netdev;
2599 struct pch_gbe_adapter *adapter;
2600 int ret;
2601
2602 ret = pcim_enable_device(pdev);
2603 if (ret)
2604 return ret;
2605
2606 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2607 || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2608 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2609 if (ret) {
2610 ret = pci_set_consistent_dma_mask(pdev,
2611 DMA_BIT_MASK(32));
2612 if (ret) {
2613 dev_err(&pdev->dev, "ERR: No usable DMA "
2614 "configuration, aborting\n");
2615 return ret;
2616 }
2617 }
2618 }
2619
2620 ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev));
2621 if (ret) {
2622 dev_err(&pdev->dev,
2623 "ERR: Can't reserve PCI I/O and memory resources\n");
2624 return ret;
2625 }
2626 pci_set_master(pdev);
2627
2628 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2629 if (!netdev)
2630 return -ENOMEM;
2631 SET_NETDEV_DEV(netdev, &pdev->dev);
2632
2633 pci_set_drvdata(pdev, netdev);
2634 adapter = netdev_priv(netdev);
2635 adapter->netdev = netdev;
2636 adapter->pdev = pdev;
2637 adapter->hw.back = adapter;
2638 adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
2639 adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
2640 if (adapter->pdata && adapter->pdata->platform_init)
2641 adapter->pdata->platform_init(pdev);
2642
2643 adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
2644 PCI_DEVFN(12, 4));
2645 if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
2646 dev_err(&pdev->dev, "Bad ptp filter\n");
2647 ret = -EINVAL;
2648 goto err_free_netdev;
2649 }
2650
2651 netdev->netdev_ops = &pch_gbe_netdev_ops;
2652 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2653 netif_napi_add(netdev, &adapter->napi,
2654 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2655 netdev->hw_features = NETIF_F_RXCSUM |
2656 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2657 netdev->features = netdev->hw_features;
2658 pch_gbe_set_ethtool_ops(netdev);
2659
2660 pch_gbe_mac_load_mac_addr(&adapter->hw);
2661 pch_gbe_mac_reset_hw(&adapter->hw);
2662
2663 /* setup the private structure */
2664 ret = pch_gbe_sw_init(adapter);
2665 if (ret)
2666 goto err_free_netdev;
2667
2668 /* Initialize PHY */
2669 ret = pch_gbe_init_phy(adapter);
2670 if (ret) {
2671 dev_err(&pdev->dev, "PHY initialize error\n");
2672 goto err_free_adapter;
2673 }
2674 pch_gbe_hal_get_bus_info(&adapter->hw);
2675
2676 /* Read the MAC address. and store to the private data */
2677 ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2678 if (ret) {
2679 dev_err(&pdev->dev, "MAC address Read Error\n");
2680 goto err_free_adapter;
2681 }
2682
2683 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2684 if (!is_valid_ether_addr(netdev->dev_addr)) {
2685 /*
2686 * If the MAC is invalid (or just missing), display a warning
2687 * but do not abort setting up the device. pch_gbe_up will
2688 * prevent the interface from being brought up until a valid MAC
2689 * is set.
2690 */
2691 dev_err(&pdev->dev, "Invalid MAC address, "
2692 "interface disabled.\n");
2693 }
2694 setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2695 (unsigned long)adapter);
2696
2697 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2698
2699 pch_gbe_check_options(adapter);
2700
2701 /* initialize the wol settings based on the eeprom settings */
2702 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2703 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2704
2705 /* reset the hardware with the new settings */
2706 pch_gbe_reset(adapter);
2707
2708 ret = register_netdev(netdev);
2709 if (ret)
2710 goto err_free_adapter;
2711 /* tell the stack to leave us alone until pch_gbe_open() is called */
2712 netif_carrier_off(netdev);
2713 netif_stop_queue(netdev);
2714
2715 dev_dbg(&pdev->dev, "PCH Network Connection\n");
2716
2717 /* Disable hibernation on certain platforms */
2718 if (adapter->pdata && adapter->pdata->phy_disable_hibernate)
2719 pch_gbe_phy_disable_hibernate(&adapter->hw);
2720
2721 device_set_wakeup_enable(&pdev->dev, 1);
2722 return 0;
2723
2724 err_free_adapter:
2725 pch_gbe_hal_phy_hw_reset(&adapter->hw);
2726 err_free_netdev:
2727 free_netdev(netdev);
2728 return ret;
2729 }
2730
2731 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
2732 * ensure it is awake for probe and init. Request the line and reset the PHY.
2733 */
2734 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
2735 {
2736 unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
2737 unsigned gpio = MINNOW_PHY_RESET_GPIO;
2738 int ret;
2739
2740 ret = devm_gpio_request_one(&pdev->dev, gpio, flags,
2741 "minnow_phy_reset");
2742 if (ret) {
2743 dev_err(&pdev->dev,
2744 "ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
2745 return ret;
2746 }
2747
2748 gpio_set_value(gpio, 0);
2749 usleep_range(1250, 1500);
2750 gpio_set_value(gpio, 1);
2751 usleep_range(1250, 1500);
2752
2753 return ret;
2754 }
2755
2756 static struct pch_gbe_privdata pch_gbe_minnow_privdata = {
2757 .phy_tx_clk_delay = true,
2758 .phy_disable_hibernate = true,
2759 .platform_init = pch_gbe_minnow_platform_init,
2760 };
2761
2762 static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = {
2763 {.vendor = PCI_VENDOR_ID_INTEL,
2764 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2765 .subvendor = PCI_VENDOR_ID_CIRCUITCO,
2766 .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD,
2767 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2768 .class_mask = (0xFFFF00),
2769 .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata
2770 },
2771 {.vendor = PCI_VENDOR_ID_INTEL,
2772 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2773 .subvendor = PCI_ANY_ID,
2774 .subdevice = PCI_ANY_ID,
2775 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2776 .class_mask = (0xFFFF00)
2777 },
2778 {.vendor = PCI_VENDOR_ID_ROHM,
2779 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2780 .subvendor = PCI_ANY_ID,
2781 .subdevice = PCI_ANY_ID,
2782 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2783 .class_mask = (0xFFFF00)
2784 },
2785 {.vendor = PCI_VENDOR_ID_ROHM,
2786 .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2787 .subvendor = PCI_ANY_ID,
2788 .subdevice = PCI_ANY_ID,
2789 .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2790 .class_mask = (0xFFFF00)
2791 },
2792 /* required last entry */
2793 {0}
2794 };
2795
2796 #ifdef CONFIG_PM
2797 static const struct dev_pm_ops pch_gbe_pm_ops = {
2798 .suspend = pch_gbe_suspend,
2799 .resume = pch_gbe_resume,
2800 .freeze = pch_gbe_suspend,
2801 .thaw = pch_gbe_resume,
2802 .poweroff = pch_gbe_suspend,
2803 .restore = pch_gbe_resume,
2804 };
2805 #endif
2806
2807 static const struct pci_error_handlers pch_gbe_err_handler = {
2808 .error_detected = pch_gbe_io_error_detected,
2809 .slot_reset = pch_gbe_io_slot_reset,
2810 .resume = pch_gbe_io_resume
2811 };
2812
2813 static struct pci_driver pch_gbe_driver = {
2814 .name = KBUILD_MODNAME,
2815 .id_table = pch_gbe_pcidev_id,
2816 .probe = pch_gbe_probe,
2817 .remove = pch_gbe_remove,
2818 #ifdef CONFIG_PM
2819 .driver.pm = &pch_gbe_pm_ops,
2820 #endif
2821 .shutdown = pch_gbe_shutdown,
2822 .err_handler = &pch_gbe_err_handler
2823 };
2824
2825
2826 static int __init pch_gbe_init_module(void)
2827 {
2828 int ret;
2829
2830 pr_info("EG20T PCH Gigabit Ethernet Driver - version %s\n",DRV_VERSION);
2831 ret = pci_register_driver(&pch_gbe_driver);
2832 if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2833 if (copybreak == 0) {
2834 pr_info("copybreak disabled\n");
2835 } else {
2836 pr_info("copybreak enabled for packets <= %u bytes\n",
2837 copybreak);
2838 }
2839 }
2840 return ret;
2841 }
2842
2843 static void __exit pch_gbe_exit_module(void)
2844 {
2845 pci_unregister_driver(&pch_gbe_driver);
2846 }
2847
2848 module_init(pch_gbe_init_module);
2849 module_exit(pch_gbe_exit_module);
2850
2851 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2852 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
2853 MODULE_LICENSE("GPL");
2854 MODULE_VERSION(DRV_VERSION);
2855 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2856
2857 module_param(copybreak, uint, 0644);
2858 MODULE_PARM_DESC(copybreak,
2859 "Maximum size of packet that is copied to a new buffer on receive");
2860
2861 /* pch_gbe_main.c */
Linux kernel - Deliverables
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