1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
9 #include <linux/types.h>
10 #include <asm/byteorder.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
16 #include <linux/mutex.h>
17 #include <linux/pci.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/vmalloc.h>
21 #include <linux/etherdevice.h>
22 #include <linux/qed/qed_chain.h>
23 #include <linux/qed/qed_if.h>
27 #include "qed_dev_api.h"
30 #include "qed_init_ops.h"
33 #include "qed_reg_addr.h"
35 #include "qed_sriov.h"
38 static spinlock_t qm_lock
;
39 static bool qm_lock_init
= false;
41 /* API common to all protocols */
43 BAR_ID_0
, /* used for GRC */
44 BAR_ID_1
/* Used for doorbells */
47 static u32
qed_hw_bar_size(struct qed_hwfn
*p_hwfn
,
50 u32 bar_reg
= (bar_id
== BAR_ID_0
?
51 PGLUE_B_REG_PF_BAR0_SIZE
: PGLUE_B_REG_PF_BAR1_SIZE
);
54 if (IS_VF(p_hwfn
->cdev
))
57 val
= qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
, bar_reg
);
59 return 1 << (val
+ 15);
61 /* Old MFW initialized above registered only conditionally */
62 if (p_hwfn
->cdev
->num_hwfns
> 1) {
64 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n");
65 return BAR_ID_0
? 256 * 1024 : 512 * 1024;
68 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n");
73 void qed_init_dp(struct qed_dev
*cdev
,
74 u32 dp_module
, u8 dp_level
)
78 cdev
->dp_level
= dp_level
;
79 cdev
->dp_module
= dp_module
;
80 for (i
= 0; i
< MAX_HWFNS_PER_DEVICE
; i
++) {
81 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
83 p_hwfn
->dp_level
= dp_level
;
84 p_hwfn
->dp_module
= dp_module
;
88 void qed_init_struct(struct qed_dev
*cdev
)
92 for (i
= 0; i
< MAX_HWFNS_PER_DEVICE
; i
++) {
93 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
97 p_hwfn
->b_active
= false;
99 mutex_init(&p_hwfn
->dmae_info
.mutex
);
102 /* hwfn 0 is always active */
103 cdev
->hwfns
[0].b_active
= true;
105 /* set the default cache alignment to 128 */
106 cdev
->cache_shift
= 7;
109 static void qed_qm_info_free(struct qed_hwfn
*p_hwfn
)
111 struct qed_qm_info
*qm_info
= &p_hwfn
->qm_info
;
113 kfree(qm_info
->qm_pq_params
);
114 qm_info
->qm_pq_params
= NULL
;
115 kfree(qm_info
->qm_vport_params
);
116 qm_info
->qm_vport_params
= NULL
;
117 kfree(qm_info
->qm_port_params
);
118 qm_info
->qm_port_params
= NULL
;
119 kfree(qm_info
->wfq_data
);
120 qm_info
->wfq_data
= NULL
;
123 void qed_resc_free(struct qed_dev
*cdev
)
130 kfree(cdev
->fw_data
);
131 cdev
->fw_data
= NULL
;
133 kfree(cdev
->reset_stats
);
135 for_each_hwfn(cdev
, i
) {
136 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
138 kfree(p_hwfn
->p_tx_cids
);
139 p_hwfn
->p_tx_cids
= NULL
;
140 kfree(p_hwfn
->p_rx_cids
);
141 p_hwfn
->p_rx_cids
= NULL
;
144 for_each_hwfn(cdev
, i
) {
145 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
147 qed_cxt_mngr_free(p_hwfn
);
148 qed_qm_info_free(p_hwfn
);
149 qed_spq_free(p_hwfn
);
150 qed_eq_free(p_hwfn
, p_hwfn
->p_eq
);
151 qed_consq_free(p_hwfn
, p_hwfn
->p_consq
);
152 qed_int_free(p_hwfn
);
153 qed_iov_free(p_hwfn
);
154 qed_dmae_info_free(p_hwfn
);
155 qed_dcbx_info_free(p_hwfn
, p_hwfn
->p_dcbx_info
);
159 static int qed_init_qm_info(struct qed_hwfn
*p_hwfn
, bool b_sleepable
)
161 u8 num_vports
, vf_offset
= 0, i
, vport_id
, num_ports
, curr_queue
= 0;
162 struct qed_qm_info
*qm_info
= &p_hwfn
->qm_info
;
163 struct init_qm_port_params
*p_qm_port
;
164 bool init_rdma_offload_pq
= false;
165 bool init_pure_ack_pq
= false;
166 bool init_ooo_pq
= false;
167 u16 num_pqs
, multi_cos_tcs
= 1;
168 u8 pf_wfq
= qm_info
->pf_wfq
;
169 u32 pf_rl
= qm_info
->pf_rl
;
173 #ifdef CONFIG_QED_SRIOV
174 if (p_hwfn
->cdev
->p_iov_info
)
175 num_vfs
= p_hwfn
->cdev
->p_iov_info
->total_vfs
;
177 memset(qm_info
, 0, sizeof(*qm_info
));
179 num_pqs
= multi_cos_tcs
+ num_vfs
+ 1; /* The '1' is for pure-LB */
180 num_vports
= (u8
)RESC_NUM(p_hwfn
, QED_VPORT
);
182 if (p_hwfn
->hw_info
.personality
== QED_PCI_ETH_ROCE
) {
183 num_pqs
++; /* for RoCE queue */
184 init_rdma_offload_pq
= true;
185 /* we subtract num_vfs because each require a rate limiter,
186 * and one default rate limiter
188 if (p_hwfn
->pf_params
.rdma_pf_params
.enable_dcqcn
)
189 num_pf_rls
= RESC_NUM(p_hwfn
, QED_RL
) - num_vfs
- 1;
191 num_pqs
+= num_pf_rls
;
192 qm_info
->num_pf_rls
= (u8
) num_pf_rls
;
195 if (p_hwfn
->hw_info
.personality
== QED_PCI_ISCSI
) {
196 num_pqs
+= 2; /* for iSCSI pure-ACK / OOO queue */
197 init_pure_ack_pq
= true;
201 /* Sanity checking that setup requires legal number of resources */
202 if (num_pqs
> RESC_NUM(p_hwfn
, QED_PQ
)) {
204 "Need too many Physical queues - 0x%04x when only %04x are available\n",
205 num_pqs
, RESC_NUM(p_hwfn
, QED_PQ
));
209 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete.
211 qm_info
->qm_pq_params
= kcalloc(num_pqs
,
212 sizeof(struct init_qm_pq_params
),
213 b_sleepable
? GFP_KERNEL
: GFP_ATOMIC
);
214 if (!qm_info
->qm_pq_params
)
217 qm_info
->qm_vport_params
= kcalloc(num_vports
,
218 sizeof(struct init_qm_vport_params
),
219 b_sleepable
? GFP_KERNEL
221 if (!qm_info
->qm_vport_params
)
224 qm_info
->qm_port_params
= kcalloc(MAX_NUM_PORTS
,
225 sizeof(struct init_qm_port_params
),
226 b_sleepable
? GFP_KERNEL
228 if (!qm_info
->qm_port_params
)
231 qm_info
->wfq_data
= kcalloc(num_vports
, sizeof(struct qed_wfq_data
),
232 b_sleepable
? GFP_KERNEL
: GFP_ATOMIC
);
233 if (!qm_info
->wfq_data
)
236 vport_id
= (u8
)RESC_START(p_hwfn
, QED_VPORT
);
238 /* First init rate limited queues */
239 for (curr_queue
= 0; curr_queue
< num_pf_rls
; curr_queue
++) {
240 qm_info
->qm_pq_params
[curr_queue
].vport_id
= vport_id
++;
241 qm_info
->qm_pq_params
[curr_queue
].tc_id
=
242 p_hwfn
->hw_info
.non_offload_tc
;
243 qm_info
->qm_pq_params
[curr_queue
].wrr_group
= 1;
244 qm_info
->qm_pq_params
[curr_queue
].rl_valid
= 1;
247 /* First init per-TC PQs */
248 for (i
= 0; i
< multi_cos_tcs
; i
++) {
249 struct init_qm_pq_params
*params
=
250 &qm_info
->qm_pq_params
[curr_queue
++];
252 if (p_hwfn
->hw_info
.personality
== QED_PCI_ETH_ROCE
||
253 p_hwfn
->hw_info
.personality
== QED_PCI_ETH
) {
254 params
->vport_id
= vport_id
;
255 params
->tc_id
= p_hwfn
->hw_info
.non_offload_tc
;
256 params
->wrr_group
= 1;
258 params
->vport_id
= vport_id
;
259 params
->tc_id
= p_hwfn
->hw_info
.offload_tc
;
260 params
->wrr_group
= 1;
264 /* Then init pure-LB PQ */
265 qm_info
->pure_lb_pq
= curr_queue
;
266 qm_info
->qm_pq_params
[curr_queue
].vport_id
=
267 (u8
) RESC_START(p_hwfn
, QED_VPORT
);
268 qm_info
->qm_pq_params
[curr_queue
].tc_id
= PURE_LB_TC
;
269 qm_info
->qm_pq_params
[curr_queue
].wrr_group
= 1;
272 qm_info
->offload_pq
= 0;
273 if (init_rdma_offload_pq
) {
274 qm_info
->offload_pq
= curr_queue
;
275 qm_info
->qm_pq_params
[curr_queue
].vport_id
= vport_id
;
276 qm_info
->qm_pq_params
[curr_queue
].tc_id
=
277 p_hwfn
->hw_info
.offload_tc
;
278 qm_info
->qm_pq_params
[curr_queue
].wrr_group
= 1;
282 if (init_pure_ack_pq
) {
283 qm_info
->pure_ack_pq
= curr_queue
;
284 qm_info
->qm_pq_params
[curr_queue
].vport_id
= vport_id
;
285 qm_info
->qm_pq_params
[curr_queue
].tc_id
=
286 p_hwfn
->hw_info
.offload_tc
;
287 qm_info
->qm_pq_params
[curr_queue
].wrr_group
= 1;
292 qm_info
->ooo_pq
= curr_queue
;
293 qm_info
->qm_pq_params
[curr_queue
].vport_id
= vport_id
;
294 qm_info
->qm_pq_params
[curr_queue
].tc_id
= DCBX_ISCSI_OOO_TC
;
295 qm_info
->qm_pq_params
[curr_queue
].wrr_group
= 1;
299 /* Then init per-VF PQs */
300 vf_offset
= curr_queue
;
301 for (i
= 0; i
< num_vfs
; i
++) {
302 /* First vport is used by the PF */
303 qm_info
->qm_pq_params
[curr_queue
].vport_id
= vport_id
+ i
+ 1;
304 qm_info
->qm_pq_params
[curr_queue
].tc_id
=
305 p_hwfn
->hw_info
.non_offload_tc
;
306 qm_info
->qm_pq_params
[curr_queue
].wrr_group
= 1;
307 qm_info
->qm_pq_params
[curr_queue
].rl_valid
= 1;
311 qm_info
->vf_queues_offset
= vf_offset
;
312 qm_info
->num_pqs
= num_pqs
;
313 qm_info
->num_vports
= num_vports
;
315 /* Initialize qm port parameters */
316 num_ports
= p_hwfn
->cdev
->num_ports_in_engines
;
317 for (i
= 0; i
< num_ports
; i
++) {
318 p_qm_port
= &qm_info
->qm_port_params
[i
];
319 p_qm_port
->active
= 1;
321 p_qm_port
->active_phys_tcs
= 0x7;
323 p_qm_port
->active_phys_tcs
= 0x9f;
324 p_qm_port
->num_pbf_cmd_lines
= PBF_MAX_CMD_LINES
/ num_ports
;
325 p_qm_port
->num_btb_blocks
= BTB_MAX_BLOCKS
/ num_ports
;
328 qm_info
->max_phys_tcs_per_port
= NUM_OF_PHYS_TCS
;
330 qm_info
->start_pq
= (u16
)RESC_START(p_hwfn
, QED_PQ
);
332 qm_info
->num_vf_pqs
= num_vfs
;
333 qm_info
->start_vport
= (u8
) RESC_START(p_hwfn
, QED_VPORT
);
335 for (i
= 0; i
< qm_info
->num_vports
; i
++)
336 qm_info
->qm_vport_params
[i
].vport_wfq
= 1;
338 qm_info
->vport_rl_en
= 1;
339 qm_info
->vport_wfq_en
= 1;
340 qm_info
->pf_rl
= pf_rl
;
341 qm_info
->pf_wfq
= pf_wfq
;
346 DP_NOTICE(p_hwfn
, "Failed to allocate memory for QM params\n");
347 qed_qm_info_free(p_hwfn
);
351 /* This function reconfigures the QM pf on the fly.
352 * For this purpose we:
353 * 1. reconfigure the QM database
354 * 2. set new values to runtime arrat
355 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM
356 * 4. activate init tool in QM_PF stage
357 * 5. send an sdm_qm_cmd through rbc interface to release the QM
359 int qed_qm_reconf(struct qed_hwfn
*p_hwfn
, struct qed_ptt
*p_ptt
)
361 struct qed_qm_info
*qm_info
= &p_hwfn
->qm_info
;
365 /* qm_info is allocated in qed_init_qm_info() which is already called
366 * from qed_resc_alloc() or previous call of qed_qm_reconf().
367 * The allocated size may change each init, so we free it before next
370 qed_qm_info_free(p_hwfn
);
372 /* initialize qed's qm data structure */
373 rc
= qed_init_qm_info(p_hwfn
, false);
377 /* stop PF's qm queues */
378 spin_lock_bh(&qm_lock
);
379 b_rc
= qed_send_qm_stop_cmd(p_hwfn
, p_ptt
, false, true,
380 qm_info
->start_pq
, qm_info
->num_pqs
);
381 spin_unlock_bh(&qm_lock
);
385 /* clear the QM_PF runtime phase leftovers from previous init */
386 qed_init_clear_rt_data(p_hwfn
);
388 /* prepare QM portion of runtime array */
389 qed_qm_init_pf(p_hwfn
);
391 /* activate init tool on runtime array */
392 rc
= qed_init_run(p_hwfn
, p_ptt
, PHASE_QM_PF
, p_hwfn
->rel_pf_id
,
393 p_hwfn
->hw_info
.hw_mode
);
397 /* start PF's qm queues */
398 spin_lock_bh(&qm_lock
);
399 b_rc
= qed_send_qm_stop_cmd(p_hwfn
, p_ptt
, true, true,
400 qm_info
->start_pq
, qm_info
->num_pqs
);
401 spin_unlock_bh(&qm_lock
);
408 int qed_resc_alloc(struct qed_dev
*cdev
)
410 struct qed_consq
*p_consq
;
417 cdev
->fw_data
= kzalloc(sizeof(*cdev
->fw_data
), GFP_KERNEL
);
421 /* Allocate Memory for the Queue->CID mapping */
422 for_each_hwfn(cdev
, i
) {
423 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
424 int tx_size
= sizeof(struct qed_hw_cid_data
) *
425 RESC_NUM(p_hwfn
, QED_L2_QUEUE
);
426 int rx_size
= sizeof(struct qed_hw_cid_data
) *
427 RESC_NUM(p_hwfn
, QED_L2_QUEUE
);
429 p_hwfn
->p_tx_cids
= kzalloc(tx_size
, GFP_KERNEL
);
430 if (!p_hwfn
->p_tx_cids
) {
432 "Failed to allocate memory for Tx Cids\n");
436 p_hwfn
->p_rx_cids
= kzalloc(rx_size
, GFP_KERNEL
);
437 if (!p_hwfn
->p_rx_cids
) {
439 "Failed to allocate memory for Rx Cids\n");
444 for_each_hwfn(cdev
, i
) {
445 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
446 u32 n_eqes
, num_cons
;
448 /* First allocate the context manager structure */
449 rc
= qed_cxt_mngr_alloc(p_hwfn
);
453 /* Set the HW cid/tid numbers (in the contest manager)
454 * Must be done prior to any further computations.
456 rc
= qed_cxt_set_pf_params(p_hwfn
);
460 /* Prepare and process QM requirements */
461 rc
= qed_init_qm_info(p_hwfn
, true);
465 /* Compute the ILT client partition */
466 rc
= qed_cxt_cfg_ilt_compute(p_hwfn
);
470 /* CID map / ILT shadow table / T2
471 * The talbes sizes are determined by the computations above
473 rc
= qed_cxt_tables_alloc(p_hwfn
);
477 /* SPQ, must follow ILT because initializes SPQ context */
478 rc
= qed_spq_alloc(p_hwfn
);
482 /* SP status block allocation */
483 p_hwfn
->p_dpc_ptt
= qed_get_reserved_ptt(p_hwfn
,
486 rc
= qed_int_alloc(p_hwfn
, p_hwfn
->p_main_ptt
);
490 rc
= qed_iov_alloc(p_hwfn
);
495 n_eqes
= qed_chain_get_capacity(&p_hwfn
->p_spq
->chain
);
496 if (p_hwfn
->hw_info
.personality
== QED_PCI_ETH_ROCE
) {
497 num_cons
= qed_cxt_get_proto_cid_count(p_hwfn
,
500 n_eqes
+= num_cons
+ 2 * MAX_NUM_VFS_BB
;
501 } else if (p_hwfn
->hw_info
.personality
== QED_PCI_ISCSI
) {
503 qed_cxt_get_proto_cid_count(p_hwfn
,
504 PROTOCOLID_ISCSI
, 0);
505 n_eqes
+= 2 * num_cons
;
508 if (n_eqes
> 0xFFFF) {
510 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n",
515 p_eq
= qed_eq_alloc(p_hwfn
, (u16
) n_eqes
);
520 p_consq
= qed_consq_alloc(p_hwfn
);
523 p_hwfn
->p_consq
= p_consq
;
525 /* DMA info initialization */
526 rc
= qed_dmae_info_alloc(p_hwfn
);
529 "Failed to allocate memory for dmae_info structure\n");
533 /* DCBX initialization */
534 rc
= qed_dcbx_info_alloc(p_hwfn
);
537 "Failed to allocate memory for dcbx structure\n");
542 cdev
->reset_stats
= kzalloc(sizeof(*cdev
->reset_stats
), GFP_KERNEL
);
543 if (!cdev
->reset_stats
) {
544 DP_NOTICE(cdev
, "Failed to allocate reset statistics\n");
558 void qed_resc_setup(struct qed_dev
*cdev
)
565 for_each_hwfn(cdev
, i
) {
566 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
568 qed_cxt_mngr_setup(p_hwfn
);
569 qed_spq_setup(p_hwfn
);
570 qed_eq_setup(p_hwfn
, p_hwfn
->p_eq
);
571 qed_consq_setup(p_hwfn
, p_hwfn
->p_consq
);
573 /* Read shadow of current MFW mailbox */
574 qed_mcp_read_mb(p_hwfn
, p_hwfn
->p_main_ptt
);
575 memcpy(p_hwfn
->mcp_info
->mfw_mb_shadow
,
576 p_hwfn
->mcp_info
->mfw_mb_cur
,
577 p_hwfn
->mcp_info
->mfw_mb_length
);
579 qed_int_setup(p_hwfn
, p_hwfn
->p_main_ptt
);
581 qed_iov_setup(p_hwfn
, p_hwfn
->p_main_ptt
);
585 #define FINAL_CLEANUP_POLL_CNT (100)
586 #define FINAL_CLEANUP_POLL_TIME (10)
587 int qed_final_cleanup(struct qed_hwfn
*p_hwfn
,
588 struct qed_ptt
*p_ptt
, u16 id
, bool is_vf
)
590 u32 command
= 0, addr
, count
= FINAL_CLEANUP_POLL_CNT
;
593 addr
= GTT_BAR0_MAP_REG_USDM_RAM
+
594 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn
->rel_pf_id
);
599 command
|= X_FINAL_CLEANUP_AGG_INT
<<
600 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT
;
601 command
|= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT
;
602 command
|= id
<< SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT
;
603 command
|= SDM_COMP_TYPE_AGG_INT
<< SDM_OP_GEN_COMP_TYPE_SHIFT
;
605 /* Make sure notification is not set before initiating final cleanup */
606 if (REG_RD(p_hwfn
, addr
)) {
609 "Unexpected; Found final cleanup notification before initiating final cleanup\n");
610 REG_WR(p_hwfn
, addr
, 0);
613 DP_VERBOSE(p_hwfn
, QED_MSG_IOV
,
614 "Sending final cleanup for PFVF[%d] [Command %08x\n]",
617 qed_wr(p_hwfn
, p_ptt
, XSDM_REG_OPERATION_GEN
, command
);
619 /* Poll until completion */
620 while (!REG_RD(p_hwfn
, addr
) && count
--)
621 msleep(FINAL_CLEANUP_POLL_TIME
);
623 if (REG_RD(p_hwfn
, addr
))
627 "Failed to receive FW final cleanup notification\n");
629 /* Cleanup afterwards */
630 REG_WR(p_hwfn
, addr
, 0);
635 static void qed_calc_hw_mode(struct qed_hwfn
*p_hwfn
)
639 hw_mode
= (1 << MODE_BB_B0
);
641 switch (p_hwfn
->cdev
->num_ports_in_engines
) {
643 hw_mode
|= 1 << MODE_PORTS_PER_ENG_1
;
646 hw_mode
|= 1 << MODE_PORTS_PER_ENG_2
;
649 hw_mode
|= 1 << MODE_PORTS_PER_ENG_4
;
652 DP_NOTICE(p_hwfn
, "num_ports_in_engine = %d not supported\n",
653 p_hwfn
->cdev
->num_ports_in_engines
);
657 switch (p_hwfn
->cdev
->mf_mode
) {
660 hw_mode
|= 1 << MODE_MF_SI
;
663 hw_mode
|= 1 << MODE_MF_SD
;
666 DP_NOTICE(p_hwfn
, "Unsupported MF mode, init as DEFAULT\n");
667 hw_mode
|= 1 << MODE_MF_SI
;
670 hw_mode
|= 1 << MODE_ASIC
;
672 if (p_hwfn
->cdev
->num_hwfns
> 1)
673 hw_mode
|= 1 << MODE_100G
;
675 p_hwfn
->hw_info
.hw_mode
= hw_mode
;
677 DP_VERBOSE(p_hwfn
, (NETIF_MSG_PROBE
| NETIF_MSG_IFUP
),
678 "Configuring function for hw_mode: 0x%08x\n",
679 p_hwfn
->hw_info
.hw_mode
);
682 /* Init run time data for all PFs on an engine. */
683 static void qed_init_cau_rt_data(struct qed_dev
*cdev
)
685 u32 offset
= CAU_REG_SB_VAR_MEMORY_RT_OFFSET
;
688 for_each_hwfn(cdev
, i
) {
689 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
690 struct qed_igu_info
*p_igu_info
;
691 struct qed_igu_block
*p_block
;
692 struct cau_sb_entry sb_entry
;
694 p_igu_info
= p_hwfn
->hw_info
.p_igu_info
;
696 for (sb_id
= 0; sb_id
< QED_MAPPING_MEMORY_SIZE(cdev
);
698 p_block
= &p_igu_info
->igu_map
.igu_blocks
[sb_id
];
702 qed_init_cau_sb_entry(p_hwfn
, &sb_entry
,
703 p_block
->function_id
,
705 STORE_RT_REG_AGG(p_hwfn
, offset
+ sb_id
* 2,
711 static int qed_hw_init_common(struct qed_hwfn
*p_hwfn
,
712 struct qed_ptt
*p_ptt
,
715 struct qed_qm_info
*qm_info
= &p_hwfn
->qm_info
;
716 struct qed_qm_common_rt_init_params params
;
717 struct qed_dev
*cdev
= p_hwfn
->cdev
;
723 qed_init_cau_rt_data(cdev
);
725 /* Program GTT windows */
726 qed_gtt_init(p_hwfn
);
728 if (p_hwfn
->mcp_info
) {
729 if (p_hwfn
->mcp_info
->func_info
.bandwidth_max
)
730 qm_info
->pf_rl_en
= 1;
731 if (p_hwfn
->mcp_info
->func_info
.bandwidth_min
)
732 qm_info
->pf_wfq_en
= 1;
735 memset(¶ms
, 0, sizeof(params
));
736 params
.max_ports_per_engine
= p_hwfn
->cdev
->num_ports_in_engines
;
737 params
.max_phys_tcs_per_port
= qm_info
->max_phys_tcs_per_port
;
738 params
.pf_rl_en
= qm_info
->pf_rl_en
;
739 params
.pf_wfq_en
= qm_info
->pf_wfq_en
;
740 params
.vport_rl_en
= qm_info
->vport_rl_en
;
741 params
.vport_wfq_en
= qm_info
->vport_wfq_en
;
742 params
.port_params
= qm_info
->qm_port_params
;
744 qed_qm_common_rt_init(p_hwfn
, ¶ms
);
746 qed_cxt_hw_init_common(p_hwfn
);
748 /* Close gate from NIG to BRB/Storm; By default they are open, but
749 * we close them to prevent NIG from passing data to reset blocks.
750 * Should have been done in the ENGINE phase, but init-tool lacks
751 * proper port-pretend capabilities.
753 qed_wr(p_hwfn
, p_ptt
, NIG_REG_RX_BRB_OUT_EN
, 0);
754 qed_wr(p_hwfn
, p_ptt
, NIG_REG_STORM_OUT_EN
, 0);
755 qed_port_pretend(p_hwfn
, p_ptt
, p_hwfn
->port_id
^ 1);
756 qed_wr(p_hwfn
, p_ptt
, NIG_REG_RX_BRB_OUT_EN
, 0);
757 qed_wr(p_hwfn
, p_ptt
, NIG_REG_STORM_OUT_EN
, 0);
758 qed_port_unpretend(p_hwfn
, p_ptt
);
760 rc
= qed_init_run(p_hwfn
, p_ptt
, PHASE_ENGINE
, ANY_PHASE_ID
, hw_mode
);
764 qed_wr(p_hwfn
, p_ptt
, PSWRQ2_REG_L2P_VALIDATE_VFID
, 0);
765 qed_wr(p_hwfn
, p_ptt
, PGLUE_B_REG_USE_CLIENTID_IN_TAG
, 1);
767 if (QED_IS_BB(p_hwfn
->cdev
)) {
768 num_pfs
= NUM_OF_ENG_PFS(p_hwfn
->cdev
);
769 for (pf_id
= 0; pf_id
< num_pfs
; pf_id
++) {
770 qed_fid_pretend(p_hwfn
, p_ptt
, pf_id
);
771 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_ROCE
, 0x0);
772 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_TCP
, 0x0);
774 /* pretend to original PF */
775 qed_fid_pretend(p_hwfn
, p_ptt
, p_hwfn
->rel_pf_id
);
778 for (vf_id
= 0; vf_id
< MAX_NUM_VFS_BB
; vf_id
++) {
779 concrete_fid
= qed_vfid_to_concrete(p_hwfn
, vf_id
);
780 qed_fid_pretend(p_hwfn
, p_ptt
, (u16
) concrete_fid
);
781 qed_wr(p_hwfn
, p_ptt
, CCFC_REG_STRONG_ENABLE_VF
, 0x1);
783 /* pretend to original PF */
784 qed_fid_pretend(p_hwfn
, p_ptt
, p_hwfn
->rel_pf_id
);
789 static int qed_hw_init_port(struct qed_hwfn
*p_hwfn
,
790 struct qed_ptt
*p_ptt
,
795 rc
= qed_init_run(p_hwfn
, p_ptt
, PHASE_PORT
, p_hwfn
->port_id
, hw_mode
);
799 if (hw_mode
& (1 << MODE_MF_SI
)) {
802 if (!qed_hw_init_first_eth(p_hwfn
, p_ptt
, &pf_id
)) {
803 DP_VERBOSE(p_hwfn
, NETIF_MSG_IFUP
,
804 "PF[%08x] is first eth on engine\n", pf_id
);
806 /* We should have configured BIT for ppfid, i.e., the
807 * relative function number in the port. But there's a
808 * bug in LLH in BB where the ppfid is actually engine
809 * based, so we need to take this into account.
811 qed_wr(p_hwfn
, p_ptt
,
812 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR
, 1 << pf_id
);
815 /* Take the protocol-based hit vector if there is a hit,
816 * otherwise take the other vector.
818 qed_wr(p_hwfn
, p_ptt
, NIG_REG_LLH_CLS_TYPE_DUALMODE
, 0x2);
823 static int qed_hw_init_pf(struct qed_hwfn
*p_hwfn
,
824 struct qed_ptt
*p_ptt
,
825 struct qed_tunn_start_params
*p_tunn
,
828 enum qed_int_mode int_mode
,
829 bool allow_npar_tx_switch
)
831 u8 rel_pf_id
= p_hwfn
->rel_pf_id
;
834 if (p_hwfn
->mcp_info
) {
835 struct qed_mcp_function_info
*p_info
;
837 p_info
= &p_hwfn
->mcp_info
->func_info
;
838 if (p_info
->bandwidth_min
)
839 p_hwfn
->qm_info
.pf_wfq
= p_info
->bandwidth_min
;
841 /* Update rate limit once we'll actually have a link */
842 p_hwfn
->qm_info
.pf_rl
= 100000;
845 qed_cxt_hw_init_pf(p_hwfn
);
847 qed_int_igu_init_rt(p_hwfn
);
849 /* Set VLAN in NIG if needed */
850 if (hw_mode
& (1 << MODE_MF_SD
)) {
851 DP_VERBOSE(p_hwfn
, NETIF_MSG_HW
, "Configuring LLH_FUNC_TAG\n");
852 STORE_RT_REG(p_hwfn
, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET
, 1);
853 STORE_RT_REG(p_hwfn
, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET
,
854 p_hwfn
->hw_info
.ovlan
);
857 /* Enable classification by MAC if needed */
858 if (hw_mode
& (1 << MODE_MF_SI
)) {
859 DP_VERBOSE(p_hwfn
, NETIF_MSG_HW
,
860 "Configuring TAGMAC_CLS_TYPE\n");
862 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET
, 1);
865 /* Protocl Configuration */
866 STORE_RT_REG(p_hwfn
, PRS_REG_SEARCH_TCP_RT_OFFSET
,
867 (p_hwfn
->hw_info
.personality
== QED_PCI_ISCSI
) ? 1 : 0);
868 STORE_RT_REG(p_hwfn
, PRS_REG_SEARCH_FCOE_RT_OFFSET
, 0);
869 STORE_RT_REG(p_hwfn
, PRS_REG_SEARCH_ROCE_RT_OFFSET
, 0);
871 /* Cleanup chip from previous driver if such remains exist */
872 rc
= qed_final_cleanup(p_hwfn
, p_ptt
, rel_pf_id
, false);
876 /* PF Init sequence */
877 rc
= qed_init_run(p_hwfn
, p_ptt
, PHASE_PF
, rel_pf_id
, hw_mode
);
881 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */
882 rc
= qed_init_run(p_hwfn
, p_ptt
, PHASE_QM_PF
, rel_pf_id
, hw_mode
);
886 /* Pure runtime initializations - directly to the HW */
887 qed_int_igu_init_pure_rt(p_hwfn
, p_ptt
, true, true);
889 if (hw_mode
& (1 << MODE_MF_SI
)) {
893 if (!qed_hw_init_first_eth(p_hwfn
, p_ptt
, &pf_id
)) {
894 if (p_hwfn
->rel_pf_id
== pf_id
) {
895 DP_VERBOSE(p_hwfn
, NETIF_MSG_IFUP
,
896 "PF[%d] is first ETH on engine\n",
900 qed_wr(p_hwfn
, p_ptt
, PRS_REG_MSG_INFO
, val
);
905 /* enable interrupts */
906 qed_int_igu_enable(p_hwfn
, p_ptt
, int_mode
);
908 /* send function start command */
909 rc
= qed_sp_pf_start(p_hwfn
, p_tunn
, p_hwfn
->cdev
->mf_mode
,
910 allow_npar_tx_switch
);
912 DP_NOTICE(p_hwfn
, "Function start ramrod failed\n");
917 static int qed_change_pci_hwfn(struct qed_hwfn
*p_hwfn
,
918 struct qed_ptt
*p_ptt
,
921 u32 delay_idx
= 0, val
, set_val
= enable
? 1 : 0;
923 /* Change PF in PXP */
924 qed_wr(p_hwfn
, p_ptt
,
925 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, set_val
);
927 /* wait until value is set - try for 1 second every 50us */
928 for (delay_idx
= 0; delay_idx
< 20000; delay_idx
++) {
929 val
= qed_rd(p_hwfn
, p_ptt
,
930 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
);
934 usleep_range(50, 60);
937 if (val
!= set_val
) {
939 "PFID_ENABLE_MASTER wasn't changed after a second\n");
946 static void qed_reset_mb_shadow(struct qed_hwfn
*p_hwfn
,
947 struct qed_ptt
*p_main_ptt
)
949 /* Read shadow of current MFW mailbox */
950 qed_mcp_read_mb(p_hwfn
, p_main_ptt
);
951 memcpy(p_hwfn
->mcp_info
->mfw_mb_shadow
,
952 p_hwfn
->mcp_info
->mfw_mb_cur
,
953 p_hwfn
->mcp_info
->mfw_mb_length
);
956 int qed_hw_init(struct qed_dev
*cdev
,
957 struct qed_tunn_start_params
*p_tunn
,
959 enum qed_int_mode int_mode
,
960 bool allow_npar_tx_switch
,
961 const u8
*bin_fw_data
)
963 u32 load_code
, param
;
966 if ((int_mode
== QED_INT_MODE_MSI
) && (cdev
->num_hwfns
> 1)) {
967 DP_NOTICE(cdev
, "MSI mode is not supported for CMT devices\n");
972 rc
= qed_init_fw_data(cdev
, bin_fw_data
);
977 for_each_hwfn(cdev
, i
) {
978 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
981 p_hwfn
->b_int_enabled
= 1;
985 /* Enable DMAE in PXP */
986 rc
= qed_change_pci_hwfn(p_hwfn
, p_hwfn
->p_main_ptt
, true);
988 qed_calc_hw_mode(p_hwfn
);
990 rc
= qed_mcp_load_req(p_hwfn
, p_hwfn
->p_main_ptt
,
993 DP_NOTICE(p_hwfn
, "Failed sending LOAD_REQ command\n");
997 qed_reset_mb_shadow(p_hwfn
, p_hwfn
->p_main_ptt
);
999 DP_VERBOSE(p_hwfn
, QED_MSG_SP
,
1000 "Load request was sent. Resp:0x%x, Load code: 0x%x\n",
1003 p_hwfn
->first_on_engine
= (load_code
==
1004 FW_MSG_CODE_DRV_LOAD_ENGINE
);
1006 if (!qm_lock_init
) {
1007 spin_lock_init(&qm_lock
);
1008 qm_lock_init
= true;
1011 switch (load_code
) {
1012 case FW_MSG_CODE_DRV_LOAD_ENGINE
:
1013 rc
= qed_hw_init_common(p_hwfn
, p_hwfn
->p_main_ptt
,
1014 p_hwfn
->hw_info
.hw_mode
);
1018 case FW_MSG_CODE_DRV_LOAD_PORT
:
1019 rc
= qed_hw_init_port(p_hwfn
, p_hwfn
->p_main_ptt
,
1020 p_hwfn
->hw_info
.hw_mode
);
1025 case FW_MSG_CODE_DRV_LOAD_FUNCTION
:
1026 rc
= qed_hw_init_pf(p_hwfn
, p_hwfn
->p_main_ptt
,
1027 p_tunn
, p_hwfn
->hw_info
.hw_mode
,
1028 b_hw_start
, int_mode
,
1029 allow_npar_tx_switch
);
1038 "init phase failed for loadcode 0x%x (rc %d)\n",
1041 /* ACK mfw regardless of success or failure of initialization */
1042 mfw_rc
= qed_mcp_cmd(p_hwfn
, p_hwfn
->p_main_ptt
,
1043 DRV_MSG_CODE_LOAD_DONE
,
1044 0, &load_code
, ¶m
);
1048 DP_NOTICE(p_hwfn
, "Failed sending LOAD_DONE command\n");
1052 /* send DCBX attention request command */
1055 "sending phony dcbx set command to trigger DCBx attention handling\n");
1056 mfw_rc
= qed_mcp_cmd(p_hwfn
, p_hwfn
->p_main_ptt
,
1057 DRV_MSG_CODE_SET_DCBX
,
1058 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT
,
1059 &load_code
, ¶m
);
1062 "Failed to send DCBX attention request\n");
1066 p_hwfn
->hw_init_done
= true;
1072 #define QED_HW_STOP_RETRY_LIMIT (10)
1073 static inline void qed_hw_timers_stop(struct qed_dev
*cdev
,
1074 struct qed_hwfn
*p_hwfn
,
1075 struct qed_ptt
*p_ptt
)
1080 qed_wr(p_hwfn
, p_ptt
, TM_REG_PF_ENABLE_CONN
, 0x0);
1081 qed_wr(p_hwfn
, p_ptt
, TM_REG_PF_ENABLE_TASK
, 0x0);
1083 for (i
= 0; i
< QED_HW_STOP_RETRY_LIMIT
; i
++) {
1084 if ((!qed_rd(p_hwfn
, p_ptt
,
1085 TM_REG_PF_SCAN_ACTIVE_CONN
)) &&
1086 (!qed_rd(p_hwfn
, p_ptt
,
1087 TM_REG_PF_SCAN_ACTIVE_TASK
)))
1090 /* Dependent on number of connection/tasks, possibly
1091 * 1ms sleep is required between polls
1093 usleep_range(1000, 2000);
1096 if (i
< QED_HW_STOP_RETRY_LIMIT
)
1100 "Timers linear scans are not over [Connection %02x Tasks %02x]\n",
1101 (u8
)qed_rd(p_hwfn
, p_ptt
, TM_REG_PF_SCAN_ACTIVE_CONN
),
1102 (u8
)qed_rd(p_hwfn
, p_ptt
, TM_REG_PF_SCAN_ACTIVE_TASK
));
1105 void qed_hw_timers_stop_all(struct qed_dev
*cdev
)
1109 for_each_hwfn(cdev
, j
) {
1110 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[j
];
1111 struct qed_ptt
*p_ptt
= p_hwfn
->p_main_ptt
;
1113 qed_hw_timers_stop(cdev
, p_hwfn
, p_ptt
);
1117 int qed_hw_stop(struct qed_dev
*cdev
)
1122 for_each_hwfn(cdev
, j
) {
1123 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[j
];
1124 struct qed_ptt
*p_ptt
= p_hwfn
->p_main_ptt
;
1126 DP_VERBOSE(p_hwfn
, NETIF_MSG_IFDOWN
, "Stopping hw/fw\n");
1129 qed_vf_pf_int_cleanup(p_hwfn
);
1133 /* mark the hw as uninitialized... */
1134 p_hwfn
->hw_init_done
= false;
1136 rc
= qed_sp_pf_stop(p_hwfn
);
1139 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n");
1141 qed_wr(p_hwfn
, p_ptt
,
1142 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF
, 0x1);
1144 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_TCP
, 0x0);
1145 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_UDP
, 0x0);
1146 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_FCOE
, 0x0);
1147 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_ROCE
, 0x0);
1148 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_OPENFLOW
, 0x0);
1150 qed_hw_timers_stop(cdev
, p_hwfn
, p_ptt
);
1152 /* Disable Attention Generation */
1153 qed_int_igu_disable_int(p_hwfn
, p_ptt
);
1155 qed_wr(p_hwfn
, p_ptt
, IGU_REG_LEADING_EDGE_LATCH
, 0);
1156 qed_wr(p_hwfn
, p_ptt
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
1158 qed_int_igu_init_pure_rt(p_hwfn
, p_ptt
, false, true);
1160 /* Need to wait 1ms to guarantee SBs are cleared */
1161 usleep_range(1000, 2000);
1165 /* Disable DMAE in PXP - in CMT, this should only be done for
1166 * first hw-function, and only after all transactions have
1167 * stopped for all active hw-functions.
1169 t_rc
= qed_change_pci_hwfn(&cdev
->hwfns
[0],
1170 cdev
->hwfns
[0].p_main_ptt
, false);
1178 void qed_hw_stop_fastpath(struct qed_dev
*cdev
)
1182 for_each_hwfn(cdev
, j
) {
1183 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[j
];
1184 struct qed_ptt
*p_ptt
= p_hwfn
->p_main_ptt
;
1187 qed_vf_pf_int_cleanup(p_hwfn
);
1193 "Shutting down the fastpath\n");
1195 qed_wr(p_hwfn
, p_ptt
,
1196 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF
, 0x1);
1198 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_TCP
, 0x0);
1199 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_UDP
, 0x0);
1200 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_FCOE
, 0x0);
1201 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_ROCE
, 0x0);
1202 qed_wr(p_hwfn
, p_ptt
, PRS_REG_SEARCH_OPENFLOW
, 0x0);
1204 qed_int_igu_init_pure_rt(p_hwfn
, p_ptt
, false, false);
1206 /* Need to wait 1ms to guarantee SBs are cleared */
1207 usleep_range(1000, 2000);
1211 void qed_hw_start_fastpath(struct qed_hwfn
*p_hwfn
)
1213 if (IS_VF(p_hwfn
->cdev
))
1216 /* Re-open incoming traffic */
1217 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
1218 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF
, 0x0);
1221 static int qed_reg_assert(struct qed_hwfn
*hwfn
,
1222 struct qed_ptt
*ptt
, u32 reg
,
1225 u32 assert_val
= qed_rd(hwfn
, ptt
, reg
);
1227 if (assert_val
!= expected
) {
1228 DP_NOTICE(hwfn
, "Value at address 0x%x != 0x%08x\n",
1236 int qed_hw_reset(struct qed_dev
*cdev
)
1239 u32 unload_resp
, unload_param
;
1242 for_each_hwfn(cdev
, i
) {
1243 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
1246 rc
= qed_vf_pf_reset(p_hwfn
);
1252 DP_VERBOSE(p_hwfn
, NETIF_MSG_IFDOWN
, "Resetting hw/fw\n");
1254 /* Check for incorrect states */
1255 qed_reg_assert(p_hwfn
, p_hwfn
->p_main_ptt
,
1256 QM_REG_USG_CNT_PF_TX
, 0);
1257 qed_reg_assert(p_hwfn
, p_hwfn
->p_main_ptt
,
1258 QM_REG_USG_CNT_PF_OTHER
, 0);
1260 /* Disable PF in HW blocks */
1261 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, DORQ_REG_PF_DB_ENABLE
, 0);
1262 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, QM_REG_PF_EN
, 0);
1263 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
1264 TCFC_REG_STRONG_ENABLE_PF
, 0);
1265 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
1266 CCFC_REG_STRONG_ENABLE_PF
, 0);
1268 /* Send unload command to MCP */
1269 rc
= qed_mcp_cmd(p_hwfn
, p_hwfn
->p_main_ptt
,
1270 DRV_MSG_CODE_UNLOAD_REQ
,
1271 DRV_MB_PARAM_UNLOAD_WOL_MCP
,
1272 &unload_resp
, &unload_param
);
1274 DP_NOTICE(p_hwfn
, "qed_hw_reset: UNLOAD_REQ failed\n");
1275 unload_resp
= FW_MSG_CODE_DRV_UNLOAD_ENGINE
;
1278 rc
= qed_mcp_cmd(p_hwfn
, p_hwfn
->p_main_ptt
,
1279 DRV_MSG_CODE_UNLOAD_DONE
,
1280 0, &unload_resp
, &unload_param
);
1282 DP_NOTICE(p_hwfn
, "qed_hw_reset: UNLOAD_DONE failed\n");
1290 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */
1291 static void qed_hw_hwfn_free(struct qed_hwfn
*p_hwfn
)
1293 qed_ptt_pool_free(p_hwfn
);
1294 kfree(p_hwfn
->hw_info
.p_igu_info
);
1297 /* Setup bar access */
1298 static void qed_hw_hwfn_prepare(struct qed_hwfn
*p_hwfn
)
1300 /* clear indirect access */
1301 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, PGLUE_B_REG_PGL_ADDR_88_F0
, 0);
1302 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, PGLUE_B_REG_PGL_ADDR_8C_F0
, 0);
1303 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, PGLUE_B_REG_PGL_ADDR_90_F0
, 0);
1304 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
, PGLUE_B_REG_PGL_ADDR_94_F0
, 0);
1306 /* Clean Previous errors if such exist */
1307 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
1308 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR
,
1309 1 << p_hwfn
->abs_pf_id
);
1311 /* enable internal target-read */
1312 qed_wr(p_hwfn
, p_hwfn
->p_main_ptt
,
1313 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
1316 static void get_function_id(struct qed_hwfn
*p_hwfn
)
1319 p_hwfn
->hw_info
.opaque_fid
= (u16
)REG_RD(p_hwfn
, PXP_PF_ME_OPAQUE_ADDR
);
1321 p_hwfn
->hw_info
.concrete_fid
= REG_RD(p_hwfn
, PXP_PF_ME_CONCRETE_ADDR
);
1323 p_hwfn
->abs_pf_id
= (p_hwfn
->hw_info
.concrete_fid
>> 16) & 0xf;
1324 p_hwfn
->rel_pf_id
= GET_FIELD(p_hwfn
->hw_info
.concrete_fid
,
1325 PXP_CONCRETE_FID_PFID
);
1326 p_hwfn
->port_id
= GET_FIELD(p_hwfn
->hw_info
.concrete_fid
,
1327 PXP_CONCRETE_FID_PORT
);
1330 static void qed_hw_set_feat(struct qed_hwfn
*p_hwfn
)
1332 u32
*feat_num
= p_hwfn
->hw_info
.feat_num
;
1333 int num_features
= 1;
1335 feat_num
[QED_PF_L2_QUE
] = min_t(u32
, RESC_NUM(p_hwfn
, QED_SB
) /
1337 RESC_NUM(p_hwfn
, QED_L2_QUEUE
));
1338 DP_VERBOSE(p_hwfn
, NETIF_MSG_PROBE
,
1339 "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n",
1340 feat_num
[QED_PF_L2_QUE
], RESC_NUM(p_hwfn
, QED_SB
),
1344 static int qed_hw_get_resc(struct qed_hwfn
*p_hwfn
)
1346 u8 enabled_func_idx
= p_hwfn
->enabled_func_idx
;
1347 u32
*resc_start
= p_hwfn
->hw_info
.resc_start
;
1348 u8 num_funcs
= p_hwfn
->num_funcs_on_engine
;
1349 u32
*resc_num
= p_hwfn
->hw_info
.resc_num
;
1350 struct qed_sb_cnt_info sb_cnt_info
;
1351 int i
, max_vf_vlan_filters
;
1353 memset(&sb_cnt_info
, 0, sizeof(sb_cnt_info
));
1355 #ifdef CONFIG_QED_SRIOV
1356 max_vf_vlan_filters
= QED_ETH_MAX_VF_NUM_VLAN_FILTERS
;
1358 max_vf_vlan_filters
= 0;
1361 qed_int_get_num_sbs(p_hwfn
, &sb_cnt_info
);
1363 resc_num
[QED_SB
] = min_t(u32
,
1364 (MAX_SB_PER_PATH_BB
/ num_funcs
),
1365 sb_cnt_info
.sb_cnt
);
1366 resc_num
[QED_L2_QUEUE
] = MAX_NUM_L2_QUEUES_BB
/ num_funcs
;
1367 resc_num
[QED_VPORT
] = MAX_NUM_VPORTS_BB
/ num_funcs
;
1368 resc_num
[QED_RSS_ENG
] = ETH_RSS_ENGINE_NUM_BB
/ num_funcs
;
1369 resc_num
[QED_PQ
] = MAX_QM_TX_QUEUES_BB
/ num_funcs
;
1370 resc_num
[QED_RL
] = min_t(u32
, 64, resc_num
[QED_VPORT
]);
1371 resc_num
[QED_MAC
] = ETH_NUM_MAC_FILTERS
/ num_funcs
;
1372 resc_num
[QED_VLAN
] = (ETH_NUM_VLAN_FILTERS
- 1 /*For vlan0*/) /
1374 resc_num
[QED_ILT
] = PXP_NUM_ILT_RECORDS_BB
/ num_funcs
;
1376 for (i
= 0; i
< QED_MAX_RESC
; i
++)
1377 resc_start
[i
] = resc_num
[i
] * enabled_func_idx
;
1379 /* Sanity for ILT */
1380 if (RESC_END(p_hwfn
, QED_ILT
) > PXP_NUM_ILT_RECORDS_BB
) {
1381 DP_NOTICE(p_hwfn
, "Can't assign ILT pages [%08x,...,%08x]\n",
1382 RESC_START(p_hwfn
, QED_ILT
),
1383 RESC_END(p_hwfn
, QED_ILT
) - 1);
1387 qed_hw_set_feat(p_hwfn
);
1389 DP_VERBOSE(p_hwfn
, NETIF_MSG_PROBE
,
1390 "The numbers for each resource are:\n"
1391 "SB = %d start = %d\n"
1392 "L2_QUEUE = %d start = %d\n"
1393 "VPORT = %d start = %d\n"
1394 "PQ = %d start = %d\n"
1395 "RL = %d start = %d\n"
1396 "MAC = %d start = %d\n"
1397 "VLAN = %d start = %d\n"
1398 "ILT = %d start = %d\n",
1399 p_hwfn
->hw_info
.resc_num
[QED_SB
],
1400 p_hwfn
->hw_info
.resc_start
[QED_SB
],
1401 p_hwfn
->hw_info
.resc_num
[QED_L2_QUEUE
],
1402 p_hwfn
->hw_info
.resc_start
[QED_L2_QUEUE
],
1403 p_hwfn
->hw_info
.resc_num
[QED_VPORT
],
1404 p_hwfn
->hw_info
.resc_start
[QED_VPORT
],
1405 p_hwfn
->hw_info
.resc_num
[QED_PQ
],
1406 p_hwfn
->hw_info
.resc_start
[QED_PQ
],
1407 p_hwfn
->hw_info
.resc_num
[QED_RL
],
1408 p_hwfn
->hw_info
.resc_start
[QED_RL
],
1409 p_hwfn
->hw_info
.resc_num
[QED_MAC
],
1410 p_hwfn
->hw_info
.resc_start
[QED_MAC
],
1411 p_hwfn
->hw_info
.resc_num
[QED_VLAN
],
1412 p_hwfn
->hw_info
.resc_start
[QED_VLAN
],
1413 p_hwfn
->hw_info
.resc_num
[QED_ILT
],
1414 p_hwfn
->hw_info
.resc_start
[QED_ILT
]);
1419 static int qed_hw_get_nvm_info(struct qed_hwfn
*p_hwfn
,
1420 struct qed_ptt
*p_ptt
)
1422 u32 nvm_cfg1_offset
, mf_mode
, addr
, generic_cont0
, core_cfg
;
1423 u32 port_cfg_addr
, link_temp
, nvm_cfg_addr
, device_capabilities
;
1424 struct qed_mcp_link_params
*link
;
1426 /* Read global nvm_cfg address */
1427 nvm_cfg_addr
= qed_rd(p_hwfn
, p_ptt
, MISC_REG_GEN_PURP_CR0
);
1429 /* Verify MCP has initialized it */
1430 if (!nvm_cfg_addr
) {
1431 DP_NOTICE(p_hwfn
, "Shared memory not initialized\n");
1435 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */
1436 nvm_cfg1_offset
= qed_rd(p_hwfn
, p_ptt
, nvm_cfg_addr
+ 4);
1438 addr
= MCP_REG_SCRATCH
+ nvm_cfg1_offset
+
1439 offsetof(struct nvm_cfg1
, glob
) +
1440 offsetof(struct nvm_cfg1_glob
, core_cfg
);
1442 core_cfg
= qed_rd(p_hwfn
, p_ptt
, addr
);
1444 switch ((core_cfg
& NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK
) >>
1445 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET
) {
1446 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G
:
1447 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_2X40G
;
1449 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G
:
1450 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_2X50G
;
1452 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G
:
1453 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_1X100G
;
1455 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F
:
1456 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_4X10G_F
;
1458 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E
:
1459 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_4X10G_E
;
1461 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G
:
1462 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_4X20G
;
1464 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G
:
1465 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_1X40G
;
1467 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G
:
1468 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_2X25G
;
1470 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G
:
1471 p_hwfn
->hw_info
.port_mode
= QED_PORT_MODE_DE_1X25G
;
1474 DP_NOTICE(p_hwfn
, "Unknown port mode in 0x%08x\n",
1479 /* Read default link configuration */
1480 link
= &p_hwfn
->mcp_info
->link_input
;
1481 port_cfg_addr
= MCP_REG_SCRATCH
+ nvm_cfg1_offset
+
1482 offsetof(struct nvm_cfg1
, port
[MFW_PORT(p_hwfn
)]);
1483 link_temp
= qed_rd(p_hwfn
, p_ptt
,
1485 offsetof(struct nvm_cfg1_port
, speed_cap_mask
));
1486 link
->speed
.advertised_speeds
=
1487 link_temp
& NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK
;
1489 p_hwfn
->mcp_info
->link_capabilities
.speed_capabilities
=
1490 link
->speed
.advertised_speeds
;
1492 link_temp
= qed_rd(p_hwfn
, p_ptt
,
1494 offsetof(struct nvm_cfg1_port
, link_settings
));
1495 switch ((link_temp
& NVM_CFG1_PORT_DRV_LINK_SPEED_MASK
) >>
1496 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET
) {
1497 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG
:
1498 link
->speed
.autoneg
= true;
1500 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G
:
1501 link
->speed
.forced_speed
= 1000;
1503 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G
:
1504 link
->speed
.forced_speed
= 10000;
1506 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G
:
1507 link
->speed
.forced_speed
= 25000;
1509 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G
:
1510 link
->speed
.forced_speed
= 40000;
1512 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G
:
1513 link
->speed
.forced_speed
= 50000;
1515 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G
:
1516 link
->speed
.forced_speed
= 100000;
1519 DP_NOTICE(p_hwfn
, "Unknown Speed in 0x%08x\n",
1523 link_temp
&= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK
;
1524 link_temp
>>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET
;
1525 link
->pause
.autoneg
= !!(link_temp
&
1526 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG
);
1527 link
->pause
.forced_rx
= !!(link_temp
&
1528 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX
);
1529 link
->pause
.forced_tx
= !!(link_temp
&
1530 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX
);
1531 link
->loopback_mode
= 0;
1533 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
1534 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n",
1535 link
->speed
.forced_speed
, link
->speed
.advertised_speeds
,
1536 link
->speed
.autoneg
, link
->pause
.autoneg
);
1538 /* Read Multi-function information from shmem */
1539 addr
= MCP_REG_SCRATCH
+ nvm_cfg1_offset
+
1540 offsetof(struct nvm_cfg1
, glob
) +
1541 offsetof(struct nvm_cfg1_glob
, generic_cont0
);
1543 generic_cont0
= qed_rd(p_hwfn
, p_ptt
, addr
);
1545 mf_mode
= (generic_cont0
& NVM_CFG1_GLOB_MF_MODE_MASK
) >>
1546 NVM_CFG1_GLOB_MF_MODE_OFFSET
;
1549 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED
:
1550 p_hwfn
->cdev
->mf_mode
= QED_MF_OVLAN
;
1552 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0
:
1553 p_hwfn
->cdev
->mf_mode
= QED_MF_NPAR
;
1555 case NVM_CFG1_GLOB_MF_MODE_DEFAULT
:
1556 p_hwfn
->cdev
->mf_mode
= QED_MF_DEFAULT
;
1559 DP_INFO(p_hwfn
, "Multi function mode is %08x\n",
1560 p_hwfn
->cdev
->mf_mode
);
1562 /* Read Multi-function information from shmem */
1563 addr
= MCP_REG_SCRATCH
+ nvm_cfg1_offset
+
1564 offsetof(struct nvm_cfg1
, glob
) +
1565 offsetof(struct nvm_cfg1_glob
, device_capabilities
);
1567 device_capabilities
= qed_rd(p_hwfn
, p_ptt
, addr
);
1568 if (device_capabilities
& NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET
)
1569 __set_bit(QED_DEV_CAP_ETH
,
1570 &p_hwfn
->hw_info
.device_capabilities
);
1571 if (device_capabilities
& NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI
)
1572 __set_bit(QED_DEV_CAP_ISCSI
,
1573 &p_hwfn
->hw_info
.device_capabilities
);
1574 if (device_capabilities
& NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE
)
1575 __set_bit(QED_DEV_CAP_ROCE
,
1576 &p_hwfn
->hw_info
.device_capabilities
);
1578 return qed_mcp_fill_shmem_func_info(p_hwfn
, p_ptt
);
1581 static void qed_get_num_funcs(struct qed_hwfn
*p_hwfn
, struct qed_ptt
*p_ptt
)
1583 u8 num_funcs
, enabled_func_idx
= p_hwfn
->rel_pf_id
;
1584 u32 reg_function_hide
, tmp
, eng_mask
, low_pfs_mask
;
1586 num_funcs
= MAX_NUM_PFS_BB
;
1588 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values
1589 * in the other bits are selected.
1590 * Bits 1-15 are for functions 1-15, respectively, and their value is
1591 * '0' only for enabled functions (function 0 always exists and
1593 * In case of CMT, only the "even" functions are enabled, and thus the
1594 * number of functions for both hwfns is learnt from the same bits.
1596 reg_function_hide
= qed_rd(p_hwfn
, p_ptt
, MISCS_REG_FUNCTION_HIDE
);
1598 if (reg_function_hide
& 0x1) {
1599 if (QED_PATH_ID(p_hwfn
) && p_hwfn
->cdev
->num_hwfns
== 1) {
1607 /* Get the number of the enabled functions on the engine */
1608 tmp
= (reg_function_hide
^ 0xffffffff) & eng_mask
;
1615 /* Get the PF index within the enabled functions */
1616 low_pfs_mask
= (0x1 << p_hwfn
->abs_pf_id
) - 1;
1617 tmp
= reg_function_hide
& eng_mask
& low_pfs_mask
;
1625 p_hwfn
->num_funcs_on_engine
= num_funcs
;
1626 p_hwfn
->enabled_func_idx
= enabled_func_idx
;
1630 "PF [rel_id %d, abs_id %d] within the %d enabled functions on the engine\n",
1633 p_hwfn
->num_funcs_on_engine
);
1637 qed_get_hw_info(struct qed_hwfn
*p_hwfn
,
1638 struct qed_ptt
*p_ptt
,
1639 enum qed_pci_personality personality
)
1644 /* Since all information is common, only first hwfns should do this */
1645 if (IS_LEAD_HWFN(p_hwfn
)) {
1646 rc
= qed_iov_hw_info(p_hwfn
);
1651 /* Read the port mode */
1652 port_mode
= qed_rd(p_hwfn
, p_ptt
,
1653 CNIG_REG_NW_PORT_MODE_BB_B0
);
1655 if (port_mode
< 3) {
1656 p_hwfn
->cdev
->num_ports_in_engines
= 1;
1657 } else if (port_mode
<= 5) {
1658 p_hwfn
->cdev
->num_ports_in_engines
= 2;
1660 DP_NOTICE(p_hwfn
, "PORT MODE: %d not supported\n",
1661 p_hwfn
->cdev
->num_ports_in_engines
);
1663 /* Default num_ports_in_engines to something */
1664 p_hwfn
->cdev
->num_ports_in_engines
= 1;
1667 qed_hw_get_nvm_info(p_hwfn
, p_ptt
);
1669 rc
= qed_int_igu_read_cam(p_hwfn
, p_ptt
);
1673 if (qed_mcp_is_init(p_hwfn
))
1674 ether_addr_copy(p_hwfn
->hw_info
.hw_mac_addr
,
1675 p_hwfn
->mcp_info
->func_info
.mac
);
1677 eth_random_addr(p_hwfn
->hw_info
.hw_mac_addr
);
1679 if (qed_mcp_is_init(p_hwfn
)) {
1680 if (p_hwfn
->mcp_info
->func_info
.ovlan
!= QED_MCP_VLAN_UNSET
)
1681 p_hwfn
->hw_info
.ovlan
=
1682 p_hwfn
->mcp_info
->func_info
.ovlan
;
1684 qed_mcp_cmd_port_init(p_hwfn
, p_ptt
);
1687 if (qed_mcp_is_init(p_hwfn
)) {
1688 enum qed_pci_personality protocol
;
1690 protocol
= p_hwfn
->mcp_info
->func_info
.protocol
;
1691 p_hwfn
->hw_info
.personality
= protocol
;
1694 qed_get_num_funcs(p_hwfn
, p_ptt
);
1696 return qed_hw_get_resc(p_hwfn
);
1699 static int qed_get_dev_info(struct qed_dev
*cdev
)
1701 struct qed_hwfn
*p_hwfn
= QED_LEADING_HWFN(cdev
);
1704 /* Read Vendor Id / Device Id */
1705 pci_read_config_word(cdev
->pdev
, PCI_VENDOR_ID
,
1707 pci_read_config_word(cdev
->pdev
, PCI_DEVICE_ID
,
1709 cdev
->chip_num
= (u16
)qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1710 MISCS_REG_CHIP_NUM
);
1711 cdev
->chip_rev
= (u16
)qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1712 MISCS_REG_CHIP_REV
);
1713 MASK_FIELD(CHIP_REV
, cdev
->chip_rev
);
1715 cdev
->type
= QED_DEV_TYPE_BB
;
1716 /* Learn number of HW-functions */
1717 tmp
= qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1718 MISCS_REG_CMT_ENABLED_FOR_PAIR
);
1720 if (tmp
& (1 << p_hwfn
->rel_pf_id
)) {
1721 DP_NOTICE(cdev
->hwfns
, "device in CMT mode\n");
1722 cdev
->num_hwfns
= 2;
1724 cdev
->num_hwfns
= 1;
1727 cdev
->chip_bond_id
= qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1728 MISCS_REG_CHIP_TEST_REG
) >> 4;
1729 MASK_FIELD(CHIP_BOND_ID
, cdev
->chip_bond_id
);
1730 cdev
->chip_metal
= (u16
)qed_rd(p_hwfn
, p_hwfn
->p_main_ptt
,
1731 MISCS_REG_CHIP_METAL
);
1732 MASK_FIELD(CHIP_METAL
, cdev
->chip_metal
);
1734 DP_INFO(cdev
->hwfns
,
1735 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n",
1736 cdev
->chip_num
, cdev
->chip_rev
,
1737 cdev
->chip_bond_id
, cdev
->chip_metal
);
1739 if (QED_IS_BB(cdev
) && CHIP_REV_IS_A0(cdev
)) {
1740 DP_NOTICE(cdev
->hwfns
,
1741 "The chip type/rev (BB A0) is not supported!\n");
1748 static int qed_hw_prepare_single(struct qed_hwfn
*p_hwfn
,
1749 void __iomem
*p_regview
,
1750 void __iomem
*p_doorbells
,
1751 enum qed_pci_personality personality
)
1755 /* Split PCI bars evenly between hwfns */
1756 p_hwfn
->regview
= p_regview
;
1757 p_hwfn
->doorbells
= p_doorbells
;
1759 if (IS_VF(p_hwfn
->cdev
))
1760 return qed_vf_hw_prepare(p_hwfn
);
1762 /* Validate that chip access is feasible */
1763 if (REG_RD(p_hwfn
, PXP_PF_ME_OPAQUE_ADDR
) == 0xffffffff) {
1765 "Reading the ME register returns all Fs; Preventing further chip access\n");
1769 get_function_id(p_hwfn
);
1771 /* Allocate PTT pool */
1772 rc
= qed_ptt_pool_alloc(p_hwfn
);
1774 DP_NOTICE(p_hwfn
, "Failed to prepare hwfn's hw\n");
1778 /* Allocate the main PTT */
1779 p_hwfn
->p_main_ptt
= qed_get_reserved_ptt(p_hwfn
, RESERVED_PTT_MAIN
);
1781 /* First hwfn learns basic information, e.g., number of hwfns */
1782 if (!p_hwfn
->my_id
) {
1783 rc
= qed_get_dev_info(p_hwfn
->cdev
);
1788 qed_hw_hwfn_prepare(p_hwfn
);
1790 /* Initialize MCP structure */
1791 rc
= qed_mcp_cmd_init(p_hwfn
, p_hwfn
->p_main_ptt
);
1793 DP_NOTICE(p_hwfn
, "Failed initializing mcp command\n");
1797 /* Read the device configuration information from the HW and SHMEM */
1798 rc
= qed_get_hw_info(p_hwfn
, p_hwfn
->p_main_ptt
, personality
);
1800 DP_NOTICE(p_hwfn
, "Failed to get HW information\n");
1804 /* Allocate the init RT array and initialize the init-ops engine */
1805 rc
= qed_init_alloc(p_hwfn
);
1807 DP_NOTICE(p_hwfn
, "Failed to allocate the init array\n");
1813 if (IS_LEAD_HWFN(p_hwfn
))
1814 qed_iov_free_hw_info(p_hwfn
->cdev
);
1815 qed_mcp_free(p_hwfn
);
1817 qed_hw_hwfn_free(p_hwfn
);
1822 int qed_hw_prepare(struct qed_dev
*cdev
,
1825 struct qed_hwfn
*p_hwfn
= QED_LEADING_HWFN(cdev
);
1828 /* Store the precompiled init data ptrs */
1830 qed_init_iro_array(cdev
);
1832 /* Initialize the first hwfn - will learn number of hwfns */
1833 rc
= qed_hw_prepare_single(p_hwfn
,
1835 cdev
->doorbells
, personality
);
1839 personality
= p_hwfn
->hw_info
.personality
;
1841 /* Initialize the rest of the hwfns */
1842 if (cdev
->num_hwfns
> 1) {
1843 void __iomem
*p_regview
, *p_doorbell
;
1846 /* adjust bar offset for second engine */
1847 addr
= cdev
->regview
+ qed_hw_bar_size(p_hwfn
, BAR_ID_0
) / 2;
1850 /* adjust doorbell bar offset for second engine */
1851 addr
= cdev
->doorbells
+ qed_hw_bar_size(p_hwfn
, BAR_ID_1
) / 2;
1854 /* prepare second hw function */
1855 rc
= qed_hw_prepare_single(&cdev
->hwfns
[1], p_regview
,
1856 p_doorbell
, personality
);
1858 /* in case of error, need to free the previously
1859 * initiliazed hwfn 0.
1863 qed_init_free(p_hwfn
);
1864 qed_mcp_free(p_hwfn
);
1865 qed_hw_hwfn_free(p_hwfn
);
1873 void qed_hw_remove(struct qed_dev
*cdev
)
1877 for_each_hwfn(cdev
, i
) {
1878 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
1881 qed_vf_pf_release(p_hwfn
);
1885 qed_init_free(p_hwfn
);
1886 qed_hw_hwfn_free(p_hwfn
);
1887 qed_mcp_free(p_hwfn
);
1890 qed_iov_free_hw_info(cdev
);
1893 static void qed_chain_free_next_ptr(struct qed_dev
*cdev
,
1894 struct qed_chain
*p_chain
)
1896 void *p_virt
= p_chain
->p_virt_addr
, *p_virt_next
= NULL
;
1897 dma_addr_t p_phys
= p_chain
->p_phys_addr
, p_phys_next
= 0;
1898 struct qed_chain_next
*p_next
;
1904 size
= p_chain
->elem_size
* p_chain
->usable_per_page
;
1906 for (i
= 0; i
< p_chain
->page_cnt
; i
++) {
1910 p_next
= (struct qed_chain_next
*)((u8
*)p_virt
+ size
);
1911 p_virt_next
= p_next
->next_virt
;
1912 p_phys_next
= HILO_DMA_REGPAIR(p_next
->next_phys
);
1914 dma_free_coherent(&cdev
->pdev
->dev
,
1915 QED_CHAIN_PAGE_SIZE
, p_virt
, p_phys
);
1917 p_virt
= p_virt_next
;
1918 p_phys
= p_phys_next
;
1922 static void qed_chain_free_single(struct qed_dev
*cdev
,
1923 struct qed_chain
*p_chain
)
1925 if (!p_chain
->p_virt_addr
)
1928 dma_free_coherent(&cdev
->pdev
->dev
,
1929 QED_CHAIN_PAGE_SIZE
,
1930 p_chain
->p_virt_addr
, p_chain
->p_phys_addr
);
1933 static void qed_chain_free_pbl(struct qed_dev
*cdev
, struct qed_chain
*p_chain
)
1935 void **pp_virt_addr_tbl
= p_chain
->pbl
.pp_virt_addr_tbl
;
1936 u32 page_cnt
= p_chain
->page_cnt
, i
, pbl_size
;
1937 u8
*p_pbl_virt
= p_chain
->pbl
.p_virt_table
;
1939 if (!pp_virt_addr_tbl
)
1942 if (!p_chain
->pbl
.p_virt_table
)
1945 for (i
= 0; i
< page_cnt
; i
++) {
1946 if (!pp_virt_addr_tbl
[i
])
1949 dma_free_coherent(&cdev
->pdev
->dev
,
1950 QED_CHAIN_PAGE_SIZE
,
1951 pp_virt_addr_tbl
[i
],
1952 *(dma_addr_t
*)p_pbl_virt
);
1954 p_pbl_virt
+= QED_CHAIN_PBL_ENTRY_SIZE
;
1957 pbl_size
= page_cnt
* QED_CHAIN_PBL_ENTRY_SIZE
;
1958 dma_free_coherent(&cdev
->pdev
->dev
,
1960 p_chain
->pbl
.p_virt_table
, p_chain
->pbl
.p_phys_table
);
1962 vfree(p_chain
->pbl
.pp_virt_addr_tbl
);
1965 void qed_chain_free(struct qed_dev
*cdev
, struct qed_chain
*p_chain
)
1967 switch (p_chain
->mode
) {
1968 case QED_CHAIN_MODE_NEXT_PTR
:
1969 qed_chain_free_next_ptr(cdev
, p_chain
);
1971 case QED_CHAIN_MODE_SINGLE
:
1972 qed_chain_free_single(cdev
, p_chain
);
1974 case QED_CHAIN_MODE_PBL
:
1975 qed_chain_free_pbl(cdev
, p_chain
);
1981 qed_chain_alloc_sanity_check(struct qed_dev
*cdev
,
1982 enum qed_chain_cnt_type cnt_type
,
1983 size_t elem_size
, u32 page_cnt
)
1985 u64 chain_size
= ELEMS_PER_PAGE(elem_size
) * page_cnt
;
1987 /* The actual chain size can be larger than the maximal possible value
1988 * after rounding up the requested elements number to pages, and after
1989 * taking into acount the unusuable elements (next-ptr elements).
1990 * The size of a "u16" chain can be (U16_MAX + 1) since the chain
1991 * size/capacity fields are of a u32 type.
1993 if ((cnt_type
== QED_CHAIN_CNT_TYPE_U16
&&
1994 chain_size
> 0x10000) ||
1995 (cnt_type
== QED_CHAIN_CNT_TYPE_U32
&&
1996 chain_size
> 0x100000000ULL
)) {
1998 "The actual chain size (0x%llx) is larger than the maximal possible value\n",
2007 qed_chain_alloc_next_ptr(struct qed_dev
*cdev
, struct qed_chain
*p_chain
)
2009 void *p_virt
= NULL
, *p_virt_prev
= NULL
;
2010 dma_addr_t p_phys
= 0;
2013 for (i
= 0; i
< p_chain
->page_cnt
; i
++) {
2014 p_virt
= dma_alloc_coherent(&cdev
->pdev
->dev
,
2015 QED_CHAIN_PAGE_SIZE
,
2016 &p_phys
, GFP_KERNEL
);
2018 DP_NOTICE(cdev
, "Failed to allocate chain memory\n");
2023 qed_chain_init_mem(p_chain
, p_virt
, p_phys
);
2024 qed_chain_reset(p_chain
);
2026 qed_chain_init_next_ptr_elem(p_chain
, p_virt_prev
,
2030 p_virt_prev
= p_virt
;
2032 /* Last page's next element should point to the beginning of the
2035 qed_chain_init_next_ptr_elem(p_chain
, p_virt_prev
,
2036 p_chain
->p_virt_addr
,
2037 p_chain
->p_phys_addr
);
2043 qed_chain_alloc_single(struct qed_dev
*cdev
, struct qed_chain
*p_chain
)
2045 dma_addr_t p_phys
= 0;
2046 void *p_virt
= NULL
;
2048 p_virt
= dma_alloc_coherent(&cdev
->pdev
->dev
,
2049 QED_CHAIN_PAGE_SIZE
, &p_phys
, GFP_KERNEL
);
2051 DP_NOTICE(cdev
, "Failed to allocate chain memory\n");
2055 qed_chain_init_mem(p_chain
, p_virt
, p_phys
);
2056 qed_chain_reset(p_chain
);
2061 static int qed_chain_alloc_pbl(struct qed_dev
*cdev
, struct qed_chain
*p_chain
)
2063 u32 page_cnt
= p_chain
->page_cnt
, size
, i
;
2064 dma_addr_t p_phys
= 0, p_pbl_phys
= 0;
2065 void **pp_virt_addr_tbl
= NULL
;
2066 u8
*p_pbl_virt
= NULL
;
2067 void *p_virt
= NULL
;
2069 size
= page_cnt
* sizeof(*pp_virt_addr_tbl
);
2070 pp_virt_addr_tbl
= vmalloc(size
);
2071 if (!pp_virt_addr_tbl
) {
2073 "Failed to allocate memory for the chain virtual addresses table\n");
2076 memset(pp_virt_addr_tbl
, 0, size
);
2078 /* The allocation of the PBL table is done with its full size, since it
2079 * is expected to be successive.
2080 * qed_chain_init_pbl_mem() is called even in a case of an allocation
2081 * failure, since pp_virt_addr_tbl was previously allocated, and it
2082 * should be saved to allow its freeing during the error flow.
2084 size
= page_cnt
* QED_CHAIN_PBL_ENTRY_SIZE
;
2085 p_pbl_virt
= dma_alloc_coherent(&cdev
->pdev
->dev
,
2086 size
, &p_pbl_phys
, GFP_KERNEL
);
2087 qed_chain_init_pbl_mem(p_chain
, p_pbl_virt
, p_pbl_phys
,
2090 DP_NOTICE(cdev
, "Failed to allocate chain pbl memory\n");
2094 for (i
= 0; i
< page_cnt
; i
++) {
2095 p_virt
= dma_alloc_coherent(&cdev
->pdev
->dev
,
2096 QED_CHAIN_PAGE_SIZE
,
2097 &p_phys
, GFP_KERNEL
);
2099 DP_NOTICE(cdev
, "Failed to allocate chain memory\n");
2104 qed_chain_init_mem(p_chain
, p_virt
, p_phys
);
2105 qed_chain_reset(p_chain
);
2108 /* Fill the PBL table with the physical address of the page */
2109 *(dma_addr_t
*)p_pbl_virt
= p_phys
;
2110 /* Keep the virtual address of the page */
2111 p_chain
->pbl
.pp_virt_addr_tbl
[i
] = p_virt
;
2113 p_pbl_virt
+= QED_CHAIN_PBL_ENTRY_SIZE
;
2119 int qed_chain_alloc(struct qed_dev
*cdev
,
2120 enum qed_chain_use_mode intended_use
,
2121 enum qed_chain_mode mode
,
2122 enum qed_chain_cnt_type cnt_type
,
2123 u32 num_elems
, size_t elem_size
, struct qed_chain
*p_chain
)
2128 if (mode
== QED_CHAIN_MODE_SINGLE
)
2131 page_cnt
= QED_CHAIN_PAGE_CNT(num_elems
, elem_size
, mode
);
2133 rc
= qed_chain_alloc_sanity_check(cdev
, cnt_type
, elem_size
, page_cnt
);
2136 "Cannot allocate a chain with the given arguments:\n"
2137 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n",
2138 intended_use
, mode
, cnt_type
, num_elems
, elem_size
);
2142 qed_chain_init_params(p_chain
, page_cnt
, (u8
) elem_size
, intended_use
,
2146 case QED_CHAIN_MODE_NEXT_PTR
:
2147 rc
= qed_chain_alloc_next_ptr(cdev
, p_chain
);
2149 case QED_CHAIN_MODE_SINGLE
:
2150 rc
= qed_chain_alloc_single(cdev
, p_chain
);
2152 case QED_CHAIN_MODE_PBL
:
2153 rc
= qed_chain_alloc_pbl(cdev
, p_chain
);
2162 qed_chain_free(cdev
, p_chain
);
2166 int qed_fw_l2_queue(struct qed_hwfn
*p_hwfn
, u16 src_id
, u16
*dst_id
)
2168 if (src_id
>= RESC_NUM(p_hwfn
, QED_L2_QUEUE
)) {
2171 min
= (u16
) RESC_START(p_hwfn
, QED_L2_QUEUE
);
2172 max
= min
+ RESC_NUM(p_hwfn
, QED_L2_QUEUE
);
2174 "l2_queue id [%d] is not valid, available indices [%d - %d]\n",
2180 *dst_id
= RESC_START(p_hwfn
, QED_L2_QUEUE
) + src_id
;
2185 int qed_fw_vport(struct qed_hwfn
*p_hwfn
,
2186 u8 src_id
, u8
*dst_id
)
2188 if (src_id
>= RESC_NUM(p_hwfn
, QED_VPORT
)) {
2191 min
= (u8
)RESC_START(p_hwfn
, QED_VPORT
);
2192 max
= min
+ RESC_NUM(p_hwfn
, QED_VPORT
);
2194 "vport id [%d] is not valid, available indices [%d - %d]\n",
2200 *dst_id
= RESC_START(p_hwfn
, QED_VPORT
) + src_id
;
2205 int qed_fw_rss_eng(struct qed_hwfn
*p_hwfn
,
2206 u8 src_id
, u8
*dst_id
)
2208 if (src_id
>= RESC_NUM(p_hwfn
, QED_RSS_ENG
)) {
2211 min
= (u8
)RESC_START(p_hwfn
, QED_RSS_ENG
);
2212 max
= min
+ RESC_NUM(p_hwfn
, QED_RSS_ENG
);
2214 "rss_eng id [%d] is not valid, available indices [%d - %d]\n",
2220 *dst_id
= RESC_START(p_hwfn
, QED_RSS_ENG
) + src_id
;
2225 static int qed_set_coalesce(struct qed_hwfn
*p_hwfn
, struct qed_ptt
*p_ptt
,
2226 u32 hw_addr
, void *p_eth_qzone
,
2227 size_t eth_qzone_size
, u8 timeset
)
2229 struct coalescing_timeset
*p_coal_timeset
;
2231 if (p_hwfn
->cdev
->int_coalescing_mode
!= QED_COAL_MODE_ENABLE
) {
2232 DP_NOTICE(p_hwfn
, "Coalescing configuration not enabled\n");
2236 p_coal_timeset
= p_eth_qzone
;
2237 memset(p_coal_timeset
, 0, eth_qzone_size
);
2238 SET_FIELD(p_coal_timeset
->value
, COALESCING_TIMESET_TIMESET
, timeset
);
2239 SET_FIELD(p_coal_timeset
->value
, COALESCING_TIMESET_VALID
, 1);
2240 qed_memcpy_to(p_hwfn
, p_ptt
, hw_addr
, p_eth_qzone
, eth_qzone_size
);
2245 int qed_set_rxq_coalesce(struct qed_hwfn
*p_hwfn
, struct qed_ptt
*p_ptt
,
2246 u16 coalesce
, u8 qid
, u16 sb_id
)
2248 struct ustorm_eth_queue_zone eth_qzone
;
2249 u8 timeset
, timer_res
;
2254 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2255 if (coalesce
<= 0x7F) {
2257 } else if (coalesce
<= 0xFF) {
2259 } else if (coalesce
<= 0x1FF) {
2262 DP_ERR(p_hwfn
, "Invalid coalesce value - %d\n", coalesce
);
2265 timeset
= (u8
)(coalesce
>> timer_res
);
2267 rc
= qed_fw_l2_queue(p_hwfn
, (u16
)qid
, &fw_qid
);
2271 rc
= qed_int_set_timer_res(p_hwfn
, p_ptt
, timer_res
, sb_id
, false);
2275 address
= BAR0_MAP_REG_USDM_RAM
+ USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid
);
2277 rc
= qed_set_coalesce(p_hwfn
, p_ptt
, address
, ð_qzone
,
2278 sizeof(struct ustorm_eth_queue_zone
), timeset
);
2282 p_hwfn
->cdev
->rx_coalesce_usecs
= coalesce
;
2287 int qed_set_txq_coalesce(struct qed_hwfn
*p_hwfn
, struct qed_ptt
*p_ptt
,
2288 u16 coalesce
, u8 qid
, u16 sb_id
)
2290 struct xstorm_eth_queue_zone eth_qzone
;
2291 u8 timeset
, timer_res
;
2296 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */
2297 if (coalesce
<= 0x7F) {
2299 } else if (coalesce
<= 0xFF) {
2301 } else if (coalesce
<= 0x1FF) {
2304 DP_ERR(p_hwfn
, "Invalid coalesce value - %d\n", coalesce
);
2307 timeset
= (u8
)(coalesce
>> timer_res
);
2309 rc
= qed_fw_l2_queue(p_hwfn
, (u16
)qid
, &fw_qid
);
2313 rc
= qed_int_set_timer_res(p_hwfn
, p_ptt
, timer_res
, sb_id
, true);
2317 address
= BAR0_MAP_REG_XSDM_RAM
+ XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid
);
2319 rc
= qed_set_coalesce(p_hwfn
, p_ptt
, address
, ð_qzone
,
2320 sizeof(struct xstorm_eth_queue_zone
), timeset
);
2324 p_hwfn
->cdev
->tx_coalesce_usecs
= coalesce
;
2329 /* Calculate final WFQ values for all vports and configure them.
2330 * After this configuration each vport will have
2331 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT)
2333 static void qed_configure_wfq_for_all_vports(struct qed_hwfn
*p_hwfn
,
2334 struct qed_ptt
*p_ptt
,
2337 struct init_qm_vport_params
*vport_params
;
2340 vport_params
= p_hwfn
->qm_info
.qm_vport_params
;
2342 for (i
= 0; i
< p_hwfn
->qm_info
.num_vports
; i
++) {
2343 u32 wfq_speed
= p_hwfn
->qm_info
.wfq_data
[i
].min_speed
;
2345 vport_params
[i
].vport_wfq
= (wfq_speed
* QED_WFQ_UNIT
) /
2347 qed_init_vport_wfq(p_hwfn
, p_ptt
,
2348 vport_params
[i
].first_tx_pq_id
,
2349 vport_params
[i
].vport_wfq
);
2353 static void qed_init_wfq_default_param(struct qed_hwfn
*p_hwfn
,
2359 for (i
= 0; i
< p_hwfn
->qm_info
.num_vports
; i
++)
2360 p_hwfn
->qm_info
.qm_vport_params
[i
].vport_wfq
= 1;
2363 static void qed_disable_wfq_for_all_vports(struct qed_hwfn
*p_hwfn
,
2364 struct qed_ptt
*p_ptt
,
2367 struct init_qm_vport_params
*vport_params
;
2370 vport_params
= p_hwfn
->qm_info
.qm_vport_params
;
2372 for (i
= 0; i
< p_hwfn
->qm_info
.num_vports
; i
++) {
2373 qed_init_wfq_default_param(p_hwfn
, min_pf_rate
);
2374 qed_init_vport_wfq(p_hwfn
, p_ptt
,
2375 vport_params
[i
].first_tx_pq_id
,
2376 vport_params
[i
].vport_wfq
);
2380 /* This function performs several validations for WFQ
2381 * configuration and required min rate for a given vport
2382 * 1. req_rate must be greater than one percent of min_pf_rate.
2383 * 2. req_rate should not cause other vports [not configured for WFQ explicitly]
2384 * rates to get less than one percent of min_pf_rate.
2385 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate.
2387 static int qed_init_wfq_param(struct qed_hwfn
*p_hwfn
,
2388 u16 vport_id
, u32 req_rate
,
2391 u32 total_req_min_rate
= 0, total_left_rate
= 0, left_rate_per_vp
= 0;
2392 int non_requested_count
= 0, req_count
= 0, i
, num_vports
;
2394 num_vports
= p_hwfn
->qm_info
.num_vports
;
2396 /* Accounting for the vports which are configured for WFQ explicitly */
2397 for (i
= 0; i
< num_vports
; i
++) {
2400 if ((i
!= vport_id
) &&
2401 p_hwfn
->qm_info
.wfq_data
[i
].configured
) {
2403 tmp_speed
= p_hwfn
->qm_info
.wfq_data
[i
].min_speed
;
2404 total_req_min_rate
+= tmp_speed
;
2408 /* Include current vport data as well */
2410 total_req_min_rate
+= req_rate
;
2411 non_requested_count
= num_vports
- req_count
;
2413 if (req_rate
< min_pf_rate
/ QED_WFQ_UNIT
) {
2414 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
2415 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2416 vport_id
, req_rate
, min_pf_rate
);
2420 if (num_vports
> QED_WFQ_UNIT
) {
2421 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
2422 "Number of vports is greater than %d\n",
2427 if (total_req_min_rate
> min_pf_rate
) {
2428 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
2429 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n",
2430 total_req_min_rate
, min_pf_rate
);
2434 total_left_rate
= min_pf_rate
- total_req_min_rate
;
2436 left_rate_per_vp
= total_left_rate
/ non_requested_count
;
2437 if (left_rate_per_vp
< min_pf_rate
/ QED_WFQ_UNIT
) {
2438 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
2439 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n",
2440 left_rate_per_vp
, min_pf_rate
);
2444 p_hwfn
->qm_info
.wfq_data
[vport_id
].min_speed
= req_rate
;
2445 p_hwfn
->qm_info
.wfq_data
[vport_id
].configured
= true;
2447 for (i
= 0; i
< num_vports
; i
++) {
2448 if (p_hwfn
->qm_info
.wfq_data
[i
].configured
)
2451 p_hwfn
->qm_info
.wfq_data
[i
].min_speed
= left_rate_per_vp
;
2457 static int __qed_configure_vport_wfq(struct qed_hwfn
*p_hwfn
,
2458 struct qed_ptt
*p_ptt
, u16 vp_id
, u32 rate
)
2460 struct qed_mcp_link_state
*p_link
;
2463 p_link
= &p_hwfn
->cdev
->hwfns
[0].mcp_info
->link_output
;
2465 if (!p_link
->min_pf_rate
) {
2466 p_hwfn
->qm_info
.wfq_data
[vp_id
].min_speed
= rate
;
2467 p_hwfn
->qm_info
.wfq_data
[vp_id
].configured
= true;
2471 rc
= qed_init_wfq_param(p_hwfn
, vp_id
, rate
, p_link
->min_pf_rate
);
2474 qed_configure_wfq_for_all_vports(p_hwfn
, p_ptt
,
2475 p_link
->min_pf_rate
);
2478 "Validation failed while configuring min rate\n");
2483 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn
*p_hwfn
,
2484 struct qed_ptt
*p_ptt
,
2487 bool use_wfq
= false;
2491 /* Validate all pre configured vports for wfq */
2492 for (i
= 0; i
< p_hwfn
->qm_info
.num_vports
; i
++) {
2495 if (!p_hwfn
->qm_info
.wfq_data
[i
].configured
)
2498 rate
= p_hwfn
->qm_info
.wfq_data
[i
].min_speed
;
2501 rc
= qed_init_wfq_param(p_hwfn
, i
, rate
, min_pf_rate
);
2504 "WFQ validation failed while configuring min rate\n");
2510 qed_configure_wfq_for_all_vports(p_hwfn
, p_ptt
, min_pf_rate
);
2512 qed_disable_wfq_for_all_vports(p_hwfn
, p_ptt
, min_pf_rate
);
2517 /* Main API for qed clients to configure vport min rate.
2518 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)]
2519 * rate - Speed in Mbps needs to be assigned to a given vport.
2521 int qed_configure_vport_wfq(struct qed_dev
*cdev
, u16 vp_id
, u32 rate
)
2523 int i
, rc
= -EINVAL
;
2525 /* Currently not supported; Might change in future */
2526 if (cdev
->num_hwfns
> 1) {
2528 "WFQ configuration is not supported for this device\n");
2532 for_each_hwfn(cdev
, i
) {
2533 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
2534 struct qed_ptt
*p_ptt
;
2536 p_ptt
= qed_ptt_acquire(p_hwfn
);
2540 rc
= __qed_configure_vport_wfq(p_hwfn
, p_ptt
, vp_id
, rate
);
2543 qed_ptt_release(p_hwfn
, p_ptt
);
2547 qed_ptt_release(p_hwfn
, p_ptt
);
2553 /* API to configure WFQ from mcp link change */
2554 void qed_configure_vp_wfq_on_link_change(struct qed_dev
*cdev
, u32 min_pf_rate
)
2558 if (cdev
->num_hwfns
> 1) {
2561 "WFQ configuration is not supported for this device\n");
2565 for_each_hwfn(cdev
, i
) {
2566 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
2568 __qed_configure_vp_wfq_on_link_change(p_hwfn
,
2574 int __qed_configure_pf_max_bandwidth(struct qed_hwfn
*p_hwfn
,
2575 struct qed_ptt
*p_ptt
,
2576 struct qed_mcp_link_state
*p_link
,
2581 p_hwfn
->mcp_info
->func_info
.bandwidth_max
= max_bw
;
2583 if (!p_link
->line_speed
&& (max_bw
!= 100))
2586 p_link
->speed
= (p_link
->line_speed
* max_bw
) / 100;
2587 p_hwfn
->qm_info
.pf_rl
= p_link
->speed
;
2589 /* Since the limiter also affects Tx-switched traffic, we don't want it
2590 * to limit such traffic in case there's no actual limit.
2591 * In that case, set limit to imaginary high boundary.
2594 p_hwfn
->qm_info
.pf_rl
= 100000;
2596 rc
= qed_init_pf_rl(p_hwfn
, p_ptt
, p_hwfn
->rel_pf_id
,
2597 p_hwfn
->qm_info
.pf_rl
);
2599 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
2600 "Configured MAX bandwidth to be %08x Mb/sec\n",
2606 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */
2607 int qed_configure_pf_max_bandwidth(struct qed_dev
*cdev
, u8 max_bw
)
2609 int i
, rc
= -EINVAL
;
2611 if (max_bw
< 1 || max_bw
> 100) {
2612 DP_NOTICE(cdev
, "PF max bw valid range is [1-100]\n");
2616 for_each_hwfn(cdev
, i
) {
2617 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
2618 struct qed_hwfn
*p_lead
= QED_LEADING_HWFN(cdev
);
2619 struct qed_mcp_link_state
*p_link
;
2620 struct qed_ptt
*p_ptt
;
2622 p_link
= &p_lead
->mcp_info
->link_output
;
2624 p_ptt
= qed_ptt_acquire(p_hwfn
);
2628 rc
= __qed_configure_pf_max_bandwidth(p_hwfn
, p_ptt
,
2631 qed_ptt_release(p_hwfn
, p_ptt
);
2640 int __qed_configure_pf_min_bandwidth(struct qed_hwfn
*p_hwfn
,
2641 struct qed_ptt
*p_ptt
,
2642 struct qed_mcp_link_state
*p_link
,
2647 p_hwfn
->mcp_info
->func_info
.bandwidth_min
= min_bw
;
2648 p_hwfn
->qm_info
.pf_wfq
= min_bw
;
2650 if (!p_link
->line_speed
)
2653 p_link
->min_pf_rate
= (p_link
->line_speed
* min_bw
) / 100;
2655 rc
= qed_init_pf_wfq(p_hwfn
, p_ptt
, p_hwfn
->rel_pf_id
, min_bw
);
2657 DP_VERBOSE(p_hwfn
, NETIF_MSG_LINK
,
2658 "Configured MIN bandwidth to be %d Mb/sec\n",
2659 p_link
->min_pf_rate
);
2664 /* Main API to configure PF min bandwidth where bw range is [1-100] */
2665 int qed_configure_pf_min_bandwidth(struct qed_dev
*cdev
, u8 min_bw
)
2667 int i
, rc
= -EINVAL
;
2669 if (min_bw
< 1 || min_bw
> 100) {
2670 DP_NOTICE(cdev
, "PF min bw valid range is [1-100]\n");
2674 for_each_hwfn(cdev
, i
) {
2675 struct qed_hwfn
*p_hwfn
= &cdev
->hwfns
[i
];
2676 struct qed_hwfn
*p_lead
= QED_LEADING_HWFN(cdev
);
2677 struct qed_mcp_link_state
*p_link
;
2678 struct qed_ptt
*p_ptt
;
2680 p_link
= &p_lead
->mcp_info
->link_output
;
2682 p_ptt
= qed_ptt_acquire(p_hwfn
);
2686 rc
= __qed_configure_pf_min_bandwidth(p_hwfn
, p_ptt
,
2689 qed_ptt_release(p_hwfn
, p_ptt
);
2693 if (p_link
->min_pf_rate
) {
2694 u32 min_rate
= p_link
->min_pf_rate
;
2696 rc
= __qed_configure_vp_wfq_on_link_change(p_hwfn
,
2701 qed_ptt_release(p_hwfn
, p_ptt
);
2707 void qed_clean_wfq_db(struct qed_hwfn
*p_hwfn
, struct qed_ptt
*p_ptt
)
2709 struct qed_mcp_link_state
*p_link
;
2711 p_link
= &p_hwfn
->mcp_info
->link_output
;
2713 if (p_link
->min_pf_rate
)
2714 qed_disable_wfq_for_all_vports(p_hwfn
, p_ptt
,
2715 p_link
->min_pf_rate
);
2717 memset(p_hwfn
->qm_info
.wfq_data
, 0,
2718 sizeof(*p_hwfn
->qm_info
.wfq_data
) * p_hwfn
->qm_info
.num_vports
);