aa08ddbd95df0fe3aa75ed4a34edb566ef98cbce
1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
12 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
15 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \
18 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
21 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \
24 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
27 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
30 #define CDU_REG_SEGMENT0_PARAMS \
32 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \
34 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \
36 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \
38 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \
40 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \
42 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \
44 #define CDU_REG_SEGMENT1_PARAMS \
46 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \
48 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \
50 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \
52 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \
54 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \
56 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \
59 #define XSDM_REG_OPERATION_GEN \
61 #define NIG_REG_RX_BRB_OUT_EN \
63 #define NIG_REG_STORM_OUT_EN \
65 #define PSWRQ2_REG_L2P_VALIDATE_VFID \
67 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \
69 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
71 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
73 #define PSWHST_REG_ZONE_PERMISSION_TABLE \
75 #define BAR0_MAP_REG_MSDM_RAM \
77 #define BAR0_MAP_REG_USDM_RAM \
79 #define BAR0_MAP_REG_PSDM_RAM \
81 #define BAR0_MAP_REG_TSDM_RAM \
83 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
85 #define PRS_REG_SEARCH_TCP \
87 #define PRS_REG_SEARCH_UDP \
89 #define PRS_REG_SEARCH_FCOE \
91 #define PRS_REG_SEARCH_ROCE \
93 #define PRS_REG_SEARCH_OPENFLOW \
95 #define TM_REG_PF_ENABLE_CONN \
97 #define TM_REG_PF_ENABLE_TASK \
99 #define TM_REG_PF_SCAN_ACTIVE_CONN \
101 #define TM_REG_PF_SCAN_ACTIVE_TASK \
103 #define IGU_REG_LEADING_EDGE_LATCH \
105 #define IGU_REG_TRAILING_EDGE_LATCH \
107 #define QM_REG_USG_CNT_PF_TX \
109 #define QM_REG_USG_CNT_PF_OTHER \
111 #define DORQ_REG_PF_DB_ENABLE \
113 #define DORQ_REG_VF_USAGE_CNT \
115 #define QM_REG_PF_EN \
117 #define TCFC_REG_STRONG_ENABLE_PF \
119 #define CCFC_REG_STRONG_ENABLE_PF \
121 #define PGLUE_B_REG_PGL_ADDR_88_F0 \
123 #define PGLUE_B_REG_PGL_ADDR_8C_F0 \
125 #define PGLUE_B_REG_PGL_ADDR_90_F0 \
127 #define PGLUE_B_REG_PGL_ADDR_94_F0 \
129 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
131 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
133 #define MISC_REG_GEN_PURP_CR0 \
135 #define MCP_REG_SCRATCH \
137 #define CNIG_REG_NW_PORT_MODE_BB_B0 \
139 #define MISCS_REG_CHIP_NUM \
141 #define MISCS_REG_CHIP_REV \
143 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \
145 #define MISCS_REG_CHIP_TEST_REG \
147 #define MISCS_REG_CHIP_METAL \
149 #define MISCS_REG_FUNCTION_HIDE \
151 #define BRB_REG_HEADER_SIZE \
153 #define BTB_REG_HEADER_SIZE \
155 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \
157 #define CCFC_REG_ACTIVITY_COUNTER \
159 #define CCFC_REG_STRONG_ENABLE_VF \
161 #define CDU_REG_CID_ADDR_PARAMS \
163 #define DBG_REG_CLIENT_ENABLE \
165 #define DMAE_REG_INIT \
167 #define DORQ_REG_IFEN \
169 #define DORQ_REG_DB_DROP_REASON \
171 #define DORQ_REG_DB_DROP_DETAILS \
173 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
175 #define GRC_REG_TIMEOUT_EN \
177 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
179 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
181 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
183 #define IGU_REG_BLOCK_CONFIGURATION \
185 #define MCM_REG_INIT \
187 #define MCP2_REG_DBG_DWORD_ENABLE \
189 #define MISC_REG_PORT_MODE \
191 #define MISCS_REG_CLK_100G_MODE \
193 #define MSDM_REG_ENABLE_IN1 \
195 #define MSEM_REG_ENABLE_IN \
197 #define NIG_REG_CM_HDR \
199 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \
201 #define NIG_REG_LLH_CLS_TYPE_DUALMODE \
203 #define NCSI_REG_CONFIG \
205 #define PBF_REG_INIT \
207 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \
209 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \
211 #define PTU_REG_ATC_INIT_ARRAY \
213 #define PCM_REG_INIT \
215 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \
217 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
219 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
221 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
223 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \
225 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
227 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
229 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \
231 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
233 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
235 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
237 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
239 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
241 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
243 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
245 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
247 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
249 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \
251 #define PRM_REG_DISABLE_PRM \
253 #define PRS_REG_SOFT_RST \
255 #define PRS_REG_MSG_INFO \
257 #define PRS_REG_ROCE_DEST_QP_MAX_PF \
259 #define PSDM_REG_ENABLE_IN1 \
261 #define PSEM_REG_ENABLE_IN \
263 #define PSWRQ_REG_DBG_SELECT \
265 #define PSWRQ2_REG_CDUT_P_SIZE \
267 #define PSWRQ2_REG_ILT_MEMORY \
269 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \
271 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
273 #define PSWHST_REG_INCORRECT_ACCESS_VALID \
275 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
277 #define PSWHST_REG_INCORRECT_ACCESS_DATA \
279 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
281 #define PSWRD_REG_DBG_SELECT \
283 #define PSWRD2_REG_CONF11 \
285 #define PSWWR_REG_USDM_FULL_TH \
287 #define PSWWR2_REG_CDU_FULL_TH2 \
289 #define QM_REG_MAXPQSIZE_0 \
291 #define RSS_REG_RSS_INIT_EN \
293 #define RDIF_REG_STOP_ON_ERROR \
295 #define SRC_REG_SOFT_RST \
297 #define TCFC_REG_ACTIVITY_COUNTER \
299 #define TCM_REG_INIT \
301 #define TM_REG_PXP_READ_DATA_FIFO_INIT \
303 #define TSDM_REG_ENABLE_IN1 \
305 #define TSEM_REG_ENABLE_IN \
307 #define TDIF_REG_STOP_ON_ERROR \
309 #define UCM_REG_INIT \
311 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
313 #define USDM_REG_ENABLE_IN1 \
315 #define USEM_REG_ENABLE_IN \
317 #define XCM_REG_INIT \
319 #define XSDM_REG_ENABLE_IN1 \
321 #define XSEM_REG_ENABLE_IN \
323 #define YCM_REG_INIT \
325 #define YSDM_REG_ENABLE_IN1 \
327 #define YSEM_REG_ENABLE_IN \
329 #define XYLD_REG_SCBD_STRICT_PRIO \
331 #define TMLD_REG_SCBD_STRICT_PRIO \
333 #define MULD_REG_SCBD_STRICT_PRIO \
335 #define YULD_REG_SCBD_STRICT_PRIO \
337 #define MISC_REG_SHARED_MEM_ADDR \
339 #define DMAE_REG_GO_C0 \
341 #define DMAE_REG_GO_C1 \
343 #define DMAE_REG_GO_C2 \
345 #define DMAE_REG_GO_C3 \
347 #define DMAE_REG_GO_C4 \
349 #define DMAE_REG_GO_C5 \
351 #define DMAE_REG_GO_C6 \
353 #define DMAE_REG_GO_C7 \
355 #define DMAE_REG_GO_C8 \
357 #define DMAE_REG_GO_C9 \
359 #define DMAE_REG_GO_C10 \
361 #define DMAE_REG_GO_C11 \
363 #define DMAE_REG_GO_C12 \
365 #define DMAE_REG_GO_C13 \
367 #define DMAE_REG_GO_C14 \
369 #define DMAE_REG_GO_C15 \
371 #define DMAE_REG_GO_C16 \
373 #define DMAE_REG_GO_C17 \
375 #define DMAE_REG_GO_C18 \
377 #define DMAE_REG_GO_C19 \
379 #define DMAE_REG_GO_C20 \
381 #define DMAE_REG_GO_C21 \
383 #define DMAE_REG_GO_C22 \
385 #define DMAE_REG_GO_C23 \
387 #define DMAE_REG_GO_C24 \
389 #define DMAE_REG_GO_C25 \
391 #define DMAE_REG_GO_C26 \
393 #define DMAE_REG_GO_C27 \
395 #define DMAE_REG_GO_C28 \
397 #define DMAE_REG_GO_C29 \
399 #define DMAE_REG_GO_C30 \
401 #define DMAE_REG_GO_C31 \
403 #define DMAE_REG_CMD_MEM \
405 #define QM_REG_MAXPQSIZETXSEL_0 \
407 #define QM_REG_SDMCMDREADY \
409 #define QM_REG_SDMCMDADDR \
411 #define QM_REG_SDMCMDDATALSB \
413 #define QM_REG_SDMCMDDATAMSB \
415 #define QM_REG_SDMCMDGO \
417 #define QM_REG_RLPFCRD \
419 #define QM_REG_RLPFINCVAL \
421 #define QM_REG_RLGLBLCRD \
423 #define QM_REG_RLGLBLINCVAL \
425 #define IGU_REG_ATTENTION_ENABLE \
427 #define IGU_REG_ATTN_MSG_ADDR_L \
429 #define IGU_REG_ATTN_MSG_ADDR_H \
431 #define MISC_REG_AEU_GENERAL_ATTN_0 \
433 #define CAU_REG_SB_ADDR_MEMORY \
435 #define CAU_REG_SB_VAR_MEMORY \
437 #define CAU_REG_PI_MEMORY \
439 #define IGU_REG_PF_CONFIGURATION \
441 #define IGU_REG_VF_CONFIGURATION \
443 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
445 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \
447 #define MISC_REG_AEU_MASK_ATTN_IGU \
449 #define IGU_REG_CLEANUP_STATUS_0 \
451 #define IGU_REG_CLEANUP_STATUS_1 \
453 #define IGU_REG_CLEANUP_STATUS_2 \
455 #define IGU_REG_CLEANUP_STATUS_3 \
457 #define IGU_REG_CLEANUP_STATUS_4 \
459 #define IGU_REG_COMMAND_REG_32LSB_DATA \
461 #define IGU_REG_COMMAND_REG_CTRL \
463 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \
465 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \
467 #define IGU_REG_MAPPING_MEMORY \
469 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \
471 #define IGU_REG_WRITE_DONE_PENDING \
473 #define MISCS_REG_GENERIC_POR_0 \
475 #define MCP_REG_NVM_CFG4 \
477 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \
479 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
481 #define MCP_REG_CPU_STATE \
483 #define MCP_REG_CPU_EVENT_MASK \
485 #define PGLUE_B_REG_PF_BAR0_SIZE \
487 #define PGLUE_B_REG_PF_BAR1_SIZE \
489 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
490 #define PRS_REG_GRE_PROTOCOL 0x1f0734UL
491 #define PRS_REG_VXLAN_PORT 0x1f0738UL
492 #define PRS_REG_OUTPUT_FORMAT_4_0 0x1f099cUL
493 #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
495 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0)
496 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0
497 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1)
498 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1
499 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2)
500 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2
502 #define NIG_REG_VXLAN_CTRL 0x50105cUL
503 #define PBF_REG_VXLAN_PORT 0xd80518UL
504 #define PBF_REG_NGE_PORT 0xd8051cUL
505 #define PRS_REG_NGE_PORT 0x1f086cUL
506 #define NIG_REG_NGE_PORT 0x508b38UL
508 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
509 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
510 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
511 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN 0x10092cUL
512 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN 0x100930UL
514 #define NIG_REG_NGE_IP_ENABLE 0x508b28UL
515 #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
516 #define NIG_REG_NGE_COMP_VER 0x508b30UL
517 #define PBF_REG_NGE_COMP_VER 0xd80524UL
518 #define PRS_REG_NGE_COMP_VER 0x1f0878UL
520 #define QM_REG_WFQPFWEIGHT 0x2f4e80UL
521 #define QM_REG_WFQVPWEIGHT 0x2fa000UL
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