2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
9 #include "qlcnic_sriov.h"
10 #include <linux/if_vlan.h>
11 #include <linux/ipv6.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
15 #define QLCNIC_MAX_TX_QUEUES 1
16 #define RSS_HASHTYPE_IP_TCP 0x3
17 #define QLC_83XX_FW_MBX_CMD 0
19 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl
[] = {
20 {QLCNIC_CMD_CONFIGURE_IP_ADDR
, 6, 1},
21 {QLCNIC_CMD_CONFIG_INTRPT
, 18, 34},
22 {QLCNIC_CMD_CREATE_RX_CTX
, 136, 27},
23 {QLCNIC_CMD_DESTROY_RX_CTX
, 2, 1},
24 {QLCNIC_CMD_CREATE_TX_CTX
, 54, 18},
25 {QLCNIC_CMD_DESTROY_TX_CTX
, 2, 1},
26 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING
, 2, 1},
27 {QLCNIC_CMD_INTRPT_TEST
, 22, 12},
28 {QLCNIC_CMD_SET_MTU
, 3, 1},
29 {QLCNIC_CMD_READ_PHY
, 4, 2},
30 {QLCNIC_CMD_WRITE_PHY
, 5, 1},
31 {QLCNIC_CMD_READ_HW_REG
, 4, 1},
32 {QLCNIC_CMD_GET_FLOW_CTL
, 4, 2},
33 {QLCNIC_CMD_SET_FLOW_CTL
, 4, 1},
34 {QLCNIC_CMD_READ_MAX_MTU
, 4, 2},
35 {QLCNIC_CMD_READ_MAX_LRO
, 4, 2},
36 {QLCNIC_CMD_MAC_ADDRESS
, 4, 3},
37 {QLCNIC_CMD_GET_PCI_INFO
, 1, 66},
38 {QLCNIC_CMD_GET_NIC_INFO
, 2, 19},
39 {QLCNIC_CMD_SET_NIC_INFO
, 32, 1},
40 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY
, 4, 3},
41 {QLCNIC_CMD_TOGGLE_ESWITCH
, 4, 1},
42 {QLCNIC_CMD_GET_ESWITCH_STATUS
, 4, 3},
43 {QLCNIC_CMD_SET_PORTMIRRORING
, 4, 1},
44 {QLCNIC_CMD_CONFIGURE_ESWITCH
, 4, 1},
45 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG
, 4, 3},
46 {QLCNIC_CMD_GET_ESWITCH_STATS
, 5, 1},
47 {QLCNIC_CMD_CONFIG_PORT
, 4, 1},
48 {QLCNIC_CMD_TEMP_SIZE
, 1, 4},
49 {QLCNIC_CMD_GET_TEMP_HDR
, 5, 5},
50 {QLCNIC_CMD_GET_LINK_EVENT
, 2, 1},
51 {QLCNIC_CMD_CONFIG_MAC_VLAN
, 4, 3},
52 {QLCNIC_CMD_CONFIG_INTR_COAL
, 6, 1},
53 {QLCNIC_CMD_CONFIGURE_RSS
, 14, 1},
54 {QLCNIC_CMD_CONFIGURE_LED
, 2, 1},
55 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE
, 2, 1},
56 {QLCNIC_CMD_CONFIGURE_HW_LRO
, 2, 1},
57 {QLCNIC_CMD_GET_STATISTICS
, 2, 80},
58 {QLCNIC_CMD_SET_PORT_CONFIG
, 2, 1},
59 {QLCNIC_CMD_GET_PORT_CONFIG
, 2, 2},
60 {QLCNIC_CMD_GET_LINK_STATUS
, 2, 4},
61 {QLCNIC_CMD_IDC_ACK
, 5, 1},
62 {QLCNIC_CMD_INIT_NIC_FUNC
, 2, 1},
63 {QLCNIC_CMD_STOP_NIC_FUNC
, 2, 1},
64 {QLCNIC_CMD_SET_LED_CONFIG
, 5, 1},
65 {QLCNIC_CMD_GET_LED_CONFIG
, 1, 5},
66 {QLCNIC_CMD_83XX_SET_DRV_VER
, 4, 1},
67 {QLCNIC_CMD_ADD_RCV_RINGS
, 130, 26},
68 {QLCNIC_CMD_CONFIG_VPORT
, 4, 4},
69 {QLCNIC_CMD_BC_EVENT_SETUP
, 2, 1},
72 const u32 qlcnic_83xx_ext_reg_tbl
[] = {
73 0x38CC, /* Global Reset */
74 0x38F0, /* Wildcard */
75 0x38FC, /* Informant */
76 0x3038, /* Host MBX ctrl */
77 0x303C, /* FW MBX ctrl */
78 0x355C, /* BOOT LOADER ADDRESS REG */
79 0x3560, /* BOOT LOADER SIZE REG */
80 0x3564, /* FW IMAGE ADDR REG */
81 0x1000, /* MBX intr enable */
82 0x1200, /* Default Intr mask */
83 0x1204, /* Default Interrupt ID */
84 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
85 0x3784, /* QLC_83XX_IDC_DEV_STATE */
86 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
87 0x378C, /* QLC_83XX_IDC_DRV_ACK */
88 0x3790, /* QLC_83XX_IDC_CTRL */
89 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
90 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
91 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
92 0x37A0, /* QLC_83XX_IDC_PF_0 */
93 0x37A4, /* QLC_83XX_IDC_PF_1 */
94 0x37A8, /* QLC_83XX_IDC_PF_2 */
95 0x37AC, /* QLC_83XX_IDC_PF_3 */
96 0x37B0, /* QLC_83XX_IDC_PF_4 */
97 0x37B4, /* QLC_83XX_IDC_PF_5 */
98 0x37B8, /* QLC_83XX_IDC_PF_6 */
99 0x37BC, /* QLC_83XX_IDC_PF_7 */
100 0x37C0, /* QLC_83XX_IDC_PF_8 */
101 0x37C4, /* QLC_83XX_IDC_PF_9 */
102 0x37C8, /* QLC_83XX_IDC_PF_10 */
103 0x37CC, /* QLC_83XX_IDC_PF_11 */
104 0x37D0, /* QLC_83XX_IDC_PF_12 */
105 0x37D4, /* QLC_83XX_IDC_PF_13 */
106 0x37D8, /* QLC_83XX_IDC_PF_14 */
107 0x37DC, /* QLC_83XX_IDC_PF_15 */
108 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
109 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
110 0x37F0, /* QLC_83XX_DRV_OP_MODE */
111 0x37F4, /* QLC_83XX_VNIC_STATE */
112 0x3868, /* QLC_83XX_DRV_LOCK */
113 0x386C, /* QLC_83XX_DRV_UNLOCK */
114 0x3504, /* QLC_83XX_DRV_LOCK_ID */
115 0x34A4, /* QLC_83XX_ASIC_TEMP */
118 const u32 qlcnic_83xx_reg_tbl
[] = {
119 0x34A8, /* PEG_HALT_STAT1 */
120 0x34AC, /* PEG_HALT_STAT2 */
121 0x34B0, /* FW_HEARTBEAT */
122 0x3500, /* FLASH LOCK_ID */
123 0x3528, /* FW_CAPABILITIES */
124 0x3538, /* Driver active, DRV_REG0 */
125 0x3540, /* Device state, DRV_REG1 */
126 0x3544, /* Driver state, DRV_REG2 */
127 0x3548, /* Driver scratch, DRV_REG3 */
128 0x354C, /* Device partiton info, DRV_REG4 */
129 0x3524, /* Driver IDC ver, DRV_REG5 */
130 0x3550, /* FW_VER_MAJOR */
131 0x3554, /* FW_VER_MINOR */
132 0x3558, /* FW_VER_SUB */
133 0x359C, /* NPAR STATE */
134 0x35FC, /* FW_IMG_VALID */
135 0x3650, /* CMD_PEG_STATE */
136 0x373C, /* RCV_PEG_STATE */
137 0x37B4, /* ASIC TEMP */
139 0x3570, /* DRV OP MODE */
140 0x3850, /* FLASH LOCK */
141 0x3854, /* FLASH UNLOCK */
144 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops
= {
145 .read_crb
= qlcnic_83xx_read_crb
,
146 .write_crb
= qlcnic_83xx_write_crb
,
147 .read_reg
= qlcnic_83xx_rd_reg_indirect
,
148 .write_reg
= qlcnic_83xx_wrt_reg_indirect
,
149 .get_mac_address
= qlcnic_83xx_get_mac_address
,
150 .setup_intr
= qlcnic_83xx_setup_intr
,
151 .alloc_mbx_args
= qlcnic_83xx_alloc_mbx_args
,
152 .mbx_cmd
= qlcnic_83xx_issue_cmd
,
153 .get_func_no
= qlcnic_83xx_get_func_no
,
154 .api_lock
= qlcnic_83xx_cam_lock
,
155 .api_unlock
= qlcnic_83xx_cam_unlock
,
156 .add_sysfs
= qlcnic_83xx_add_sysfs
,
157 .remove_sysfs
= qlcnic_83xx_remove_sysfs
,
158 .process_lb_rcv_ring_diag
= qlcnic_83xx_process_rcv_ring_diag
,
159 .create_rx_ctx
= qlcnic_83xx_create_rx_ctx
,
160 .create_tx_ctx
= qlcnic_83xx_create_tx_ctx
,
161 .del_rx_ctx
= qlcnic_83xx_del_rx_ctx
,
162 .del_tx_ctx
= qlcnic_83xx_del_tx_ctx
,
163 .setup_link_event
= qlcnic_83xx_setup_link_event
,
164 .get_nic_info
= qlcnic_83xx_get_nic_info
,
165 .get_pci_info
= qlcnic_83xx_get_pci_info
,
166 .set_nic_info
= qlcnic_83xx_set_nic_info
,
167 .change_macvlan
= qlcnic_83xx_sre_macaddr_change
,
168 .napi_enable
= qlcnic_83xx_napi_enable
,
169 .napi_disable
= qlcnic_83xx_napi_disable
,
170 .config_intr_coal
= qlcnic_83xx_config_intr_coal
,
171 .config_rss
= qlcnic_83xx_config_rss
,
172 .config_hw_lro
= qlcnic_83xx_config_hw_lro
,
173 .config_promisc_mode
= qlcnic_83xx_nic_set_promisc
,
174 .change_l2_filter
= qlcnic_83xx_change_l2_filter
,
175 .get_board_info
= qlcnic_83xx_get_port_info
,
176 .set_mac_filter_count
= qlcnic_83xx_set_mac_filter_count
,
177 .free_mac_list
= qlcnic_82xx_free_mac_list
,
180 static struct qlcnic_nic_template qlcnic_83xx_ops
= {
181 .config_bridged_mode
= qlcnic_config_bridged_mode
,
182 .config_led
= qlcnic_config_led
,
183 .request_reset
= qlcnic_83xx_idc_request_reset
,
184 .cancel_idc_work
= qlcnic_83xx_idc_exit
,
185 .napi_add
= qlcnic_83xx_napi_add
,
186 .napi_del
= qlcnic_83xx_napi_del
,
187 .config_ipaddr
= qlcnic_83xx_config_ipaddr
,
188 .clear_legacy_intr
= qlcnic_83xx_clear_legacy_intr
,
189 .shutdown
= qlcnic_83xx_shutdown
,
190 .resume
= qlcnic_83xx_resume
,
193 void qlcnic_83xx_register_map(struct qlcnic_hardware_context
*ahw
)
195 ahw
->hw_ops
= &qlcnic_83xx_hw_ops
;
196 ahw
->reg_tbl
= (u32
*)qlcnic_83xx_reg_tbl
;
197 ahw
->ext_reg_tbl
= (u32
*)qlcnic_83xx_ext_reg_tbl
;
200 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter
*adapter
)
202 u32 fw_major
, fw_minor
, fw_build
;
203 struct pci_dev
*pdev
= adapter
->pdev
;
205 fw_major
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MAJOR
);
206 fw_minor
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MINOR
);
207 fw_build
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_SUB
);
208 adapter
->fw_version
= QLCNIC_VERSION_CODE(fw_major
, fw_minor
, fw_build
);
210 dev_info(&pdev
->dev
, "Driver v%s, firmware version %d.%d.%d\n",
211 QLCNIC_LINUX_VERSIONID
, fw_major
, fw_minor
, fw_build
);
213 return adapter
->fw_version
;
216 static int __qlcnic_set_win_base(struct qlcnic_adapter
*adapter
, u32 addr
)
221 base
= adapter
->ahw
->pci_base0
+
222 QLC_83XX_CRB_WIN_FUNC(adapter
->ahw
->pci_func
);
231 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter
*adapter
, ulong addr
,
234 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
236 *err
= __qlcnic_set_win_base(adapter
, (u32
) addr
);
238 return QLCRDX(ahw
, QLCNIC_WILDCARD
);
240 dev_err(&adapter
->pdev
->dev
,
241 "%s failed, addr = 0x%lx\n", __func__
, addr
);
246 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter
*adapter
, ulong addr
,
250 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
252 err
= __qlcnic_set_win_base(adapter
, (u32
) addr
);
254 QLCWRX(ahw
, QLCNIC_WILDCARD
, data
);
257 dev_err(&adapter
->pdev
->dev
,
258 "%s failed, addr = 0x%x data = 0x%x\n",
259 __func__
, (int)addr
, data
);
264 int qlcnic_83xx_setup_intr(struct qlcnic_adapter
*adapter
, u8 num_intr
)
266 int err
, i
, num_msix
;
267 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
270 num_intr
= QLCNIC_DEF_NUM_STS_DESC_RINGS
;
271 num_msix
= rounddown_pow_of_two(min_t(int, num_online_cpus(),
273 /* account for AEN interrupt MSI-X based interrupts */
276 if (!(adapter
->flags
& QLCNIC_TX_INTR_SHARED
))
277 num_msix
+= adapter
->max_drv_tx_rings
;
279 err
= qlcnic_enable_msix(adapter
, num_msix
);
282 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
283 num_msix
= adapter
->ahw
->num_msix
;
285 if (qlcnic_sriov_vf_check(adapter
))
289 /* setup interrupt mapping table for fw */
290 ahw
->intr_tbl
= vzalloc(num_msix
*
291 sizeof(struct qlcnic_intrpt_config
));
294 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
)) {
295 /* MSI-X enablement failed, use legacy interrupt */
296 adapter
->tgt_status_reg
= ahw
->pci_base0
+ QLC_83XX_INTX_PTR
;
297 adapter
->tgt_mask_reg
= ahw
->pci_base0
+ QLC_83XX_INTX_MASK
;
298 adapter
->isr_int_vec
= ahw
->pci_base0
+ QLC_83XX_INTX_TRGR
;
299 adapter
->msix_entries
[0].vector
= adapter
->pdev
->irq
;
300 dev_info(&adapter
->pdev
->dev
, "using legacy interrupt\n");
303 for (i
= 0; i
< num_msix
; i
++) {
304 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
305 ahw
->intr_tbl
[i
].type
= QLCNIC_INTRPT_MSIX
;
307 ahw
->intr_tbl
[i
].type
= QLCNIC_INTRPT_INTX
;
308 ahw
->intr_tbl
[i
].id
= i
;
309 ahw
->intr_tbl
[i
].src
= 0;
314 inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter
*adapter
)
316 writel(0, adapter
->tgt_mask_reg
);
319 inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter
*adapter
)
321 writel(1, adapter
->tgt_mask_reg
);
324 /* Enable MSI-x and INT-x interrupts */
325 void qlcnic_83xx_enable_intr(struct qlcnic_adapter
*adapter
,
326 struct qlcnic_host_sds_ring
*sds_ring
)
328 writel(0, sds_ring
->crb_intr_mask
);
331 /* Disable MSI-x and INT-x interrupts */
332 void qlcnic_83xx_disable_intr(struct qlcnic_adapter
*adapter
,
333 struct qlcnic_host_sds_ring
*sds_ring
)
335 writel(1, sds_ring
->crb_intr_mask
);
338 inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
343 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
344 * source register. We could be here before contexts are created
345 * and sds_ring->crb_intr_mask has not been initialized, calculate
346 * BAR offset for Interrupt Source Register
348 mask
= QLCRDX(adapter
->ahw
, QLCNIC_DEF_INT_MASK
);
349 writel(0, adapter
->ahw
->pci_base0
+ mask
);
352 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter
*adapter
)
356 mask
= QLCRDX(adapter
->ahw
, QLCNIC_DEF_INT_MASK
);
357 writel(1, adapter
->ahw
->pci_base0
+ mask
);
358 QLCWRX(adapter
->ahw
, QLCNIC_MBX_INTR_ENBL
, 0);
361 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter
*adapter
,
362 struct qlcnic_cmd_args
*cmd
)
366 if (cmd
->op_type
== QLC_83XX_MBX_POST_BC_OP
)
369 for (i
= 0; i
< cmd
->rsp
.num
; i
++)
370 cmd
->rsp
.arg
[i
] = readl(QLCNIC_MBX_FW(adapter
->ahw
, i
));
373 irqreturn_t
qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter
*adapter
)
376 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
379 intr_val
= readl(adapter
->tgt_status_reg
);
381 if (!QLC_83XX_VALID_INTX_BIT31(intr_val
))
384 if (QLC_83XX_INTX_FUNC(intr_val
) != adapter
->ahw
->pci_func
) {
385 adapter
->stats
.spurious_intr
++;
388 /* The barrier is required to ensure writes to the registers */
391 /* clear the interrupt trigger control register */
392 writel(0, adapter
->isr_int_vec
);
393 intr_val
= readl(adapter
->isr_int_vec
);
395 intr_val
= readl(adapter
->tgt_status_reg
);
396 if (QLC_83XX_INTX_FUNC(intr_val
) != ahw
->pci_func
)
399 } while (QLC_83XX_VALID_INTX_BIT30(intr_val
) &&
400 (retries
< QLC_83XX_LEGACY_INTX_MAX_RETRY
));
405 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox
*mbx
)
407 atomic_set(&mbx
->rsp_status
, QLC_83XX_MBX_RESPONSE_ARRIVED
);
408 complete(&mbx
->completion
);
411 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter
*adapter
)
413 u32 resp
, event
, rsp_status
= QLC_83XX_MBX_RESPONSE_ARRIVED
;
414 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
417 spin_lock_irqsave(&mbx
->aen_lock
, flags
);
418 resp
= QLCRDX(adapter
->ahw
, QLCNIC_FW_MBX_CTRL
);
419 if (!(resp
& QLCNIC_SET_OWNER
))
422 event
= readl(QLCNIC_MBX_FW(adapter
->ahw
, 0));
423 if (event
& QLCNIC_MBX_ASYNC_EVENT
) {
424 __qlcnic_83xx_process_aen(adapter
);
426 if (atomic_read(&mbx
->rsp_status
) != rsp_status
)
427 qlcnic_83xx_notify_mbx_response(mbx
);
430 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
431 spin_unlock_irqrestore(&mbx
->aen_lock
, flags
);
434 irqreturn_t
qlcnic_83xx_intr(int irq
, void *data
)
436 struct qlcnic_adapter
*adapter
= data
;
437 struct qlcnic_host_sds_ring
*sds_ring
;
438 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
440 if (qlcnic_83xx_clear_legacy_intr(adapter
) == IRQ_NONE
)
443 qlcnic_83xx_poll_process_aen(adapter
);
445 if (ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
) {
447 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
451 if (!test_bit(__QLCNIC_DEV_UP
, &adapter
->state
)) {
452 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
454 sds_ring
= &adapter
->recv_ctx
->sds_rings
[0];
455 napi_schedule(&sds_ring
->napi
);
461 irqreturn_t
qlcnic_83xx_tmp_intr(int irq
, void *data
)
463 struct qlcnic_host_sds_ring
*sds_ring
= data
;
464 struct qlcnic_adapter
*adapter
= sds_ring
->adapter
;
466 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
469 if (adapter
->nic_ops
->clear_legacy_intr(adapter
) == IRQ_NONE
)
473 adapter
->ahw
->diag_cnt
++;
474 qlcnic_83xx_enable_intr(adapter
, sds_ring
);
479 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter
*adapter
)
483 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
484 qlcnic_83xx_set_legacy_intr_mask(adapter
);
486 qlcnic_83xx_disable_mbx_intr(adapter
);
488 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
489 num_msix
= adapter
->ahw
->num_msix
- 1;
494 synchronize_irq(adapter
->msix_entries
[num_msix
].vector
);
495 free_irq(adapter
->msix_entries
[num_msix
].vector
, adapter
);
498 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter
*adapter
)
500 irq_handler_t handler
;
503 unsigned long flags
= 0;
505 if (!(adapter
->flags
& QLCNIC_MSI_ENABLED
) &&
506 !(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
507 flags
|= IRQF_SHARED
;
509 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
) {
510 handler
= qlcnic_83xx_handle_aen
;
511 val
= adapter
->msix_entries
[adapter
->ahw
->num_msix
- 1].vector
;
512 err
= request_irq(val
, handler
, flags
, "qlcnic-MB", adapter
);
514 dev_err(&adapter
->pdev
->dev
,
515 "failed to register MBX interrupt\n");
519 handler
= qlcnic_83xx_intr
;
520 val
= adapter
->msix_entries
[0].vector
;
521 err
= request_irq(val
, handler
, flags
, "qlcnic", adapter
);
523 dev_err(&adapter
->pdev
->dev
,
524 "failed to register INTx interrupt\n");
527 qlcnic_83xx_clear_legacy_intr_mask(adapter
);
530 /* Enable mailbox interrupt */
531 qlcnic_83xx_enable_mbx_interrupt(adapter
);
536 void qlcnic_83xx_get_func_no(struct qlcnic_adapter
*adapter
)
538 u32 val
= QLCRDX(adapter
->ahw
, QLCNIC_INFORMANT
);
539 adapter
->ahw
->pci_func
= (val
>> 24) & 0xff;
542 int qlcnic_83xx_cam_lock(struct qlcnic_adapter
*adapter
)
547 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
549 addr
= ahw
->pci_base0
+ QLC_83XX_SEM_LOCK_FUNC(ahw
->pci_func
);
553 /* write the function number to register */
554 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FLASH_LOCK_OWNER
,
558 usleep_range(1000, 2000);
559 } while (++limit
<= QLCNIC_PCIE_SEM_TIMEOUT
);
564 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter
*adapter
)
568 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
570 addr
= ahw
->pci_base0
+ QLC_83XX_SEM_UNLOCK_FUNC(ahw
->pci_func
);
574 void qlcnic_83xx_read_crb(struct qlcnic_adapter
*adapter
, char *buf
,
575 loff_t offset
, size_t size
)
580 if (qlcnic_api_lock(adapter
)) {
581 dev_err(&adapter
->pdev
->dev
,
582 "%s: failed to acquire lock. addr offset 0x%x\n",
583 __func__
, (u32
)offset
);
587 data
= QLCRD32(adapter
, (u32
) offset
, &ret
);
588 qlcnic_api_unlock(adapter
);
591 dev_err(&adapter
->pdev
->dev
,
592 "%s: failed. addr offset 0x%x\n",
593 __func__
, (u32
)offset
);
596 memcpy(buf
, &data
, size
);
599 void qlcnic_83xx_write_crb(struct qlcnic_adapter
*adapter
, char *buf
,
600 loff_t offset
, size_t size
)
604 memcpy(&data
, buf
, size
);
605 qlcnic_83xx_wrt_reg_indirect(adapter
, (u32
) offset
, data
);
608 int qlcnic_83xx_get_port_info(struct qlcnic_adapter
*adapter
)
612 status
= qlcnic_83xx_get_port_config(adapter
);
614 dev_err(&adapter
->pdev
->dev
,
615 "Get Port Info failed\n");
617 if (QLC_83XX_SFP_10G_CAPABLE(adapter
->ahw
->port_config
))
618 adapter
->ahw
->port_type
= QLCNIC_XGBE
;
620 adapter
->ahw
->port_type
= QLCNIC_GBE
;
622 if (QLC_83XX_AUTONEG(adapter
->ahw
->port_config
))
623 adapter
->ahw
->link_autoneg
= AUTONEG_ENABLE
;
628 void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter
*adapter
)
630 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
631 u16 act_pci_fn
= ahw
->act_pci_func
;
634 ahw
->max_mc_count
= QLC_83XX_MAX_MC_COUNT
;
636 count
= (QLC_83XX_MAX_UC_COUNT
- QLC_83XX_MAX_MC_COUNT
) /
639 count
= (QLC_83XX_LB_MAX_FILTERS
- QLC_83XX_MAX_MC_COUNT
) /
641 ahw
->max_uc_count
= count
;
644 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter
*adapter
)
648 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
649 val
= BIT_2
| ((adapter
->ahw
->num_msix
- 1) << 8);
653 QLCWRX(adapter
->ahw
, QLCNIC_MBX_INTR_ENBL
, val
);
654 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter
);
657 void qlcnic_83xx_check_vf(struct qlcnic_adapter
*adapter
,
658 const struct pci_device_id
*ent
)
660 u32 op_mode
, priv_level
;
661 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
663 ahw
->fw_hal_version
= 2;
664 qlcnic_get_func_no(adapter
);
666 if (qlcnic_sriov_vf_check(adapter
)) {
667 qlcnic_sriov_vf_set_ops(adapter
);
671 /* Determine function privilege level */
672 op_mode
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_OP_MODE
);
673 if (op_mode
== QLC_83XX_DEFAULT_OPMODE
)
674 priv_level
= QLCNIC_MGMT_FUNC
;
676 priv_level
= QLC_83XX_GET_FUNC_PRIVILEGE(op_mode
,
679 if (priv_level
== QLCNIC_NON_PRIV_FUNC
) {
680 ahw
->op_mode
= QLCNIC_NON_PRIV_FUNC
;
681 dev_info(&adapter
->pdev
->dev
,
682 "HAL Version: %d Non Privileged function\n",
683 ahw
->fw_hal_version
);
684 adapter
->nic_ops
= &qlcnic_vf_ops
;
686 if (pci_find_ext_capability(adapter
->pdev
,
687 PCI_EXT_CAP_ID_SRIOV
))
688 set_bit(__QLCNIC_SRIOV_CAPABLE
, &adapter
->state
);
689 adapter
->nic_ops
= &qlcnic_83xx_ops
;
693 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter
*adapter
,
695 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter
*adapter
,
698 static void qlcnic_dump_mbx(struct qlcnic_adapter
*adapter
,
699 struct qlcnic_cmd_args
*cmd
)
703 if (cmd
->op_type
== QLC_83XX_MBX_POST_BC_OP
)
706 dev_info(&adapter
->pdev
->dev
,
707 "Host MBX regs(%d)\n", cmd
->req
.num
);
708 for (i
= 0; i
< cmd
->req
.num
; i
++) {
711 pr_info("%08x ", cmd
->req
.arg
[i
]);
714 dev_info(&adapter
->pdev
->dev
,
715 "FW MBX regs(%d)\n", cmd
->rsp
.num
);
716 for (i
= 0; i
< cmd
->rsp
.num
; i
++) {
719 pr_info("%08x ", cmd
->rsp
.arg
[i
]);
725 qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter
*adapter
,
726 struct qlcnic_cmd_args
*cmd
)
728 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
729 int opcode
= LSW(cmd
->req
.arg
[0]);
730 unsigned long max_loops
;
732 max_loops
= cmd
->total_cmds
* QLC_83XX_MBX_CMD_LOOP
;
734 for (; max_loops
; max_loops
--) {
735 if (atomic_read(&cmd
->rsp_status
) ==
736 QLC_83XX_MBX_RESPONSE_ARRIVED
)
742 dev_err(&adapter
->pdev
->dev
,
743 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
744 __func__
, opcode
, cmd
->type
, ahw
->pci_func
, ahw
->op_mode
);
745 flush_workqueue(ahw
->mailbox
->work_q
);
749 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter
*adapter
,
750 struct qlcnic_cmd_args
*cmd
)
752 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
753 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
754 int cmd_type
, err
, opcode
;
755 unsigned long timeout
;
757 opcode
= LSW(cmd
->req
.arg
[0]);
758 cmd_type
= cmd
->type
;
759 err
= mbx
->ops
->enqueue_cmd(adapter
, cmd
, &timeout
);
761 dev_err(&adapter
->pdev
->dev
,
762 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
763 __func__
, opcode
, cmd
->type
, ahw
->pci_func
,
769 case QLC_83XX_MBX_CMD_WAIT
:
770 if (!wait_for_completion_timeout(&cmd
->completion
, timeout
)) {
771 dev_err(&adapter
->pdev
->dev
,
772 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
773 __func__
, opcode
, cmd_type
, ahw
->pci_func
,
775 flush_workqueue(mbx
->work_q
);
778 case QLC_83XX_MBX_CMD_NO_WAIT
:
780 case QLC_83XX_MBX_CMD_BUSY_WAIT
:
781 qlcnic_83xx_poll_for_mbx_completion(adapter
, cmd
);
784 dev_err(&adapter
->pdev
->dev
,
785 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
786 __func__
, opcode
, cmd_type
, ahw
->pci_func
,
788 qlcnic_83xx_detach_mailbox_work(adapter
);
791 return cmd
->rsp_opcode
;
794 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args
*mbx
,
795 struct qlcnic_adapter
*adapter
, u32 type
)
799 const struct qlcnic_mailbox_metadata
*mbx_tbl
;
801 memset(mbx
, 0, sizeof(struct qlcnic_cmd_args
));
802 mbx_tbl
= qlcnic_83xx_mbx_tbl
;
803 size
= ARRAY_SIZE(qlcnic_83xx_mbx_tbl
);
804 for (i
= 0; i
< size
; i
++) {
805 if (type
== mbx_tbl
[i
].cmd
) {
806 mbx
->op_type
= QLC_83XX_FW_MBX_CMD
;
807 mbx
->req
.num
= mbx_tbl
[i
].in_args
;
808 mbx
->rsp
.num
= mbx_tbl
[i
].out_args
;
809 mbx
->req
.arg
= kcalloc(mbx
->req
.num
, sizeof(u32
),
813 mbx
->rsp
.arg
= kcalloc(mbx
->rsp
.num
, sizeof(u32
),
820 memset(mbx
->req
.arg
, 0, sizeof(u32
) * mbx
->req
.num
);
821 memset(mbx
->rsp
.arg
, 0, sizeof(u32
) * mbx
->rsp
.num
);
822 temp
= adapter
->ahw
->fw_hal_version
<< 29;
823 mbx
->req
.arg
[0] = (type
| (mbx
->req
.num
<< 16) | temp
);
831 void qlcnic_83xx_idc_aen_work(struct work_struct
*work
)
833 struct qlcnic_adapter
*adapter
;
834 struct qlcnic_cmd_args cmd
;
837 adapter
= container_of(work
, struct qlcnic_adapter
, idc_aen_work
.work
);
838 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_IDC_ACK
);
842 for (i
= 1; i
< QLC_83XX_MBX_AEN_CNT
; i
++)
843 cmd
.req
.arg
[i
] = adapter
->ahw
->mbox_aen
[i
];
845 err
= qlcnic_issue_cmd(adapter
, &cmd
);
847 dev_info(&adapter
->pdev
->dev
,
848 "%s: Mailbox IDC ACK failed.\n", __func__
);
849 qlcnic_free_mbx_args(&cmd
);
852 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter
*adapter
,
855 dev_dbg(&adapter
->pdev
->dev
, "Completion AEN:0x%x.\n",
856 QLCNIC_MBX_RSP(data
[0]));
857 clear_bit(QLC_83XX_IDC_COMP_AEN
, &adapter
->ahw
->idc
.status
);
861 void __qlcnic_83xx_process_aen(struct qlcnic_adapter
*adapter
)
863 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
864 u32 event
[QLC_83XX_MBX_AEN_CNT
];
867 for (i
= 0; i
< QLC_83XX_MBX_AEN_CNT
; i
++)
868 event
[i
] = readl(QLCNIC_MBX_FW(ahw
, i
));
870 switch (QLCNIC_MBX_RSP(event
[0])) {
872 case QLCNIC_MBX_LINK_EVENT
:
873 qlcnic_83xx_handle_link_aen(adapter
, event
);
875 case QLCNIC_MBX_COMP_EVENT
:
876 qlcnic_83xx_handle_idc_comp_aen(adapter
, event
);
878 case QLCNIC_MBX_REQUEST_EVENT
:
879 for (i
= 0; i
< QLC_83XX_MBX_AEN_CNT
; i
++)
880 adapter
->ahw
->mbox_aen
[i
] = QLCNIC_MBX_RSP(event
[i
]);
881 queue_delayed_work(adapter
->qlcnic_wq
,
882 &adapter
->idc_aen_work
, 0);
884 case QLCNIC_MBX_TIME_EXTEND_EVENT
:
885 ahw
->extend_lb_time
= event
[1] >> 8 & 0xf;
887 case QLCNIC_MBX_BC_EVENT
:
888 qlcnic_sriov_handle_bc_event(adapter
, event
[1]);
890 case QLCNIC_MBX_SFP_INSERT_EVENT
:
891 dev_info(&adapter
->pdev
->dev
, "SFP+ Insert AEN:0x%x.\n",
892 QLCNIC_MBX_RSP(event
[0]));
894 case QLCNIC_MBX_SFP_REMOVE_EVENT
:
895 dev_info(&adapter
->pdev
->dev
, "SFP Removed AEN:0x%x.\n",
896 QLCNIC_MBX_RSP(event
[0]));
899 dev_dbg(&adapter
->pdev
->dev
, "Unsupported AEN:0x%x.\n",
900 QLCNIC_MBX_RSP(event
[0]));
904 QLCWRX(ahw
, QLCNIC_FW_MBX_CTRL
, QLCNIC_CLR_OWNER
);
907 static void qlcnic_83xx_process_aen(struct qlcnic_adapter
*adapter
)
909 u32 resp
, event
, rsp_status
= QLC_83XX_MBX_RESPONSE_ARRIVED
;
910 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
911 struct qlcnic_mailbox
*mbx
= ahw
->mailbox
;
914 spin_lock_irqsave(&mbx
->aen_lock
, flags
);
915 resp
= QLCRDX(ahw
, QLCNIC_FW_MBX_CTRL
);
916 if (resp
& QLCNIC_SET_OWNER
) {
917 event
= readl(QLCNIC_MBX_FW(ahw
, 0));
918 if (event
& QLCNIC_MBX_ASYNC_EVENT
) {
919 __qlcnic_83xx_process_aen(adapter
);
921 if (atomic_read(&mbx
->rsp_status
) != rsp_status
)
922 qlcnic_83xx_notify_mbx_response(mbx
);
925 spin_unlock_irqrestore(&mbx
->aen_lock
, flags
);
928 static void qlcnic_83xx_mbx_poll_work(struct work_struct
*work
)
930 struct qlcnic_adapter
*adapter
;
932 adapter
= container_of(work
, struct qlcnic_adapter
, mbx_poll_work
.work
);
934 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE
, &adapter
->state
))
937 qlcnic_83xx_process_aen(adapter
);
938 queue_delayed_work(adapter
->qlcnic_wq
, &adapter
->mbx_poll_work
,
942 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter
*adapter
)
944 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE
, &adapter
->state
))
947 INIT_DELAYED_WORK(&adapter
->mbx_poll_work
, qlcnic_83xx_mbx_poll_work
);
948 queue_delayed_work(adapter
->qlcnic_wq
, &adapter
->mbx_poll_work
, 0);
951 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter
*adapter
)
953 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE
, &adapter
->state
))
955 cancel_delayed_work_sync(&adapter
->mbx_poll_work
);
958 static int qlcnic_83xx_add_rings(struct qlcnic_adapter
*adapter
)
960 int index
, i
, err
, sds_mbx_size
;
961 u32
*buf
, intrpt_id
, intr_mask
;
964 struct qlcnic_cmd_args cmd
;
965 struct qlcnic_host_sds_ring
*sds
;
966 struct qlcnic_sds_mbx sds_mbx
;
967 struct qlcnic_add_rings_mbx_out
*mbx_out
;
968 struct qlcnic_recv_context
*recv_ctx
= adapter
->recv_ctx
;
969 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
971 sds_mbx_size
= sizeof(struct qlcnic_sds_mbx
);
972 context_id
= recv_ctx
->context_id
;
973 num_sds
= (adapter
->max_sds_rings
- QLCNIC_MAX_RING_SETS
);
974 ahw
->hw_ops
->alloc_mbx_args(&cmd
, adapter
,
975 QLCNIC_CMD_ADD_RCV_RINGS
);
976 cmd
.req
.arg
[1] = 0 | (num_sds
<< 8) | (context_id
<< 16);
978 /* set up status rings, mbx 2-81 */
980 for (i
= 8; i
< adapter
->max_sds_rings
; i
++) {
981 memset(&sds_mbx
, 0, sds_mbx_size
);
982 sds
= &recv_ctx
->sds_rings
[i
];
984 memset(sds
->desc_head
, 0, STATUS_DESC_RINGSIZE(sds
));
985 sds_mbx
.phy_addr_low
= LSD(sds
->phys_addr
);
986 sds_mbx
.phy_addr_high
= MSD(sds
->phys_addr
);
987 sds_mbx
.sds_ring_size
= sds
->num_desc
;
989 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
990 intrpt_id
= ahw
->intr_tbl
[i
].id
;
992 intrpt_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
994 if (adapter
->ahw
->diag_test
!= QLCNIC_LOOPBACK_TEST
)
995 sds_mbx
.intrpt_id
= intrpt_id
;
997 sds_mbx
.intrpt_id
= 0xffff;
998 sds_mbx
.intrpt_val
= 0;
999 buf
= &cmd
.req
.arg
[index
];
1000 memcpy(buf
, &sds_mbx
, sds_mbx_size
);
1001 index
+= sds_mbx_size
/ sizeof(u32
);
1004 /* send the mailbox command */
1005 err
= ahw
->hw_ops
->mbx_cmd(adapter
, &cmd
);
1007 dev_err(&adapter
->pdev
->dev
,
1008 "Failed to add rings %d\n", err
);
1012 mbx_out
= (struct qlcnic_add_rings_mbx_out
*)&cmd
.rsp
.arg
[1];
1014 /* status descriptor ring */
1015 for (i
= 8; i
< adapter
->max_sds_rings
; i
++) {
1016 sds
= &recv_ctx
->sds_rings
[i
];
1017 sds
->crb_sts_consumer
= ahw
->pci_base0
+
1018 mbx_out
->host_csmr
[index
];
1019 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
1020 intr_mask
= ahw
->intr_tbl
[i
].src
;
1022 intr_mask
= QLCRDX(ahw
, QLCNIC_DEF_INT_MASK
);
1024 sds
->crb_intr_mask
= ahw
->pci_base0
+ intr_mask
;
1028 qlcnic_free_mbx_args(&cmd
);
1032 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter
*adapter
)
1036 struct qlcnic_cmd_args cmd
;
1037 struct qlcnic_recv_context
*recv_ctx
= adapter
->recv_ctx
;
1039 if (qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_DESTROY_RX_CTX
))
1042 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1043 cmd
.req
.arg
[0] |= (0x3 << 29);
1045 if (qlcnic_sriov_pf_check(adapter
))
1046 qlcnic_pf_set_interface_id_del_rx_ctx(adapter
, &temp
);
1048 cmd
.req
.arg
[1] = recv_ctx
->context_id
| temp
;
1049 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1051 dev_err(&adapter
->pdev
->dev
,
1052 "Failed to destroy rx ctx in firmware\n");
1054 recv_ctx
->state
= QLCNIC_HOST_CTX_STATE_FREED
;
1055 qlcnic_free_mbx_args(&cmd
);
1058 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter
*adapter
)
1060 int i
, err
, index
, sds_mbx_size
, rds_mbx_size
;
1061 u8 num_sds
, num_rds
;
1062 u32
*buf
, intrpt_id
, intr_mask
, cap
= 0;
1063 struct qlcnic_host_sds_ring
*sds
;
1064 struct qlcnic_host_rds_ring
*rds
;
1065 struct qlcnic_sds_mbx sds_mbx
;
1066 struct qlcnic_rds_mbx rds_mbx
;
1067 struct qlcnic_cmd_args cmd
;
1068 struct qlcnic_rcv_mbx_out
*mbx_out
;
1069 struct qlcnic_recv_context
*recv_ctx
= adapter
->recv_ctx
;
1070 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1071 num_rds
= adapter
->max_rds_rings
;
1073 if (adapter
->max_sds_rings
<= QLCNIC_MAX_RING_SETS
)
1074 num_sds
= adapter
->max_sds_rings
;
1076 num_sds
= QLCNIC_MAX_RING_SETS
;
1078 sds_mbx_size
= sizeof(struct qlcnic_sds_mbx
);
1079 rds_mbx_size
= sizeof(struct qlcnic_rds_mbx
);
1080 cap
= QLCNIC_CAP0_LEGACY_CONTEXT
;
1082 if (adapter
->flags
& QLCNIC_FW_LRO_MSS_CAP
)
1083 cap
|= QLC_83XX_FW_CAP_LRO_MSS
;
1085 /* set mailbox hdr and capabilities */
1086 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1087 QLCNIC_CMD_CREATE_RX_CTX
);
1091 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1092 cmd
.req
.arg
[0] |= (0x3 << 29);
1094 cmd
.req
.arg
[1] = cap
;
1095 cmd
.req
.arg
[5] = 1 | (num_rds
<< 5) | (num_sds
<< 8) |
1096 (QLC_83XX_HOST_RDS_MODE_UNIQUE
<< 16);
1098 if (qlcnic_sriov_pf_check(adapter
))
1099 qlcnic_pf_set_interface_id_create_rx_ctx(adapter
,
1101 /* set up status rings, mbx 8-57/87 */
1102 index
= QLC_83XX_HOST_SDS_MBX_IDX
;
1103 for (i
= 0; i
< num_sds
; i
++) {
1104 memset(&sds_mbx
, 0, sds_mbx_size
);
1105 sds
= &recv_ctx
->sds_rings
[i
];
1107 memset(sds
->desc_head
, 0, STATUS_DESC_RINGSIZE(sds
));
1108 sds_mbx
.phy_addr_low
= LSD(sds
->phys_addr
);
1109 sds_mbx
.phy_addr_high
= MSD(sds
->phys_addr
);
1110 sds_mbx
.sds_ring_size
= sds
->num_desc
;
1111 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
1112 intrpt_id
= ahw
->intr_tbl
[i
].id
;
1114 intrpt_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
1115 if (adapter
->ahw
->diag_test
!= QLCNIC_LOOPBACK_TEST
)
1116 sds_mbx
.intrpt_id
= intrpt_id
;
1118 sds_mbx
.intrpt_id
= 0xffff;
1119 sds_mbx
.intrpt_val
= 0;
1120 buf
= &cmd
.req
.arg
[index
];
1121 memcpy(buf
, &sds_mbx
, sds_mbx_size
);
1122 index
+= sds_mbx_size
/ sizeof(u32
);
1124 /* set up receive rings, mbx 88-111/135 */
1125 index
= QLCNIC_HOST_RDS_MBX_IDX
;
1126 rds
= &recv_ctx
->rds_rings
[0];
1128 memset(&rds_mbx
, 0, rds_mbx_size
);
1129 rds_mbx
.phy_addr_reg_low
= LSD(rds
->phys_addr
);
1130 rds_mbx
.phy_addr_reg_high
= MSD(rds
->phys_addr
);
1131 rds_mbx
.reg_ring_sz
= rds
->dma_size
;
1132 rds_mbx
.reg_ring_len
= rds
->num_desc
;
1134 rds
= &recv_ctx
->rds_rings
[1];
1136 rds_mbx
.phy_addr_jmb_low
= LSD(rds
->phys_addr
);
1137 rds_mbx
.phy_addr_jmb_high
= MSD(rds
->phys_addr
);
1138 rds_mbx
.jmb_ring_sz
= rds
->dma_size
;
1139 rds_mbx
.jmb_ring_len
= rds
->num_desc
;
1140 buf
= &cmd
.req
.arg
[index
];
1141 memcpy(buf
, &rds_mbx
, rds_mbx_size
);
1143 /* send the mailbox command */
1144 err
= ahw
->hw_ops
->mbx_cmd(adapter
, &cmd
);
1146 dev_err(&adapter
->pdev
->dev
,
1147 "Failed to create Rx ctx in firmware%d\n", err
);
1150 mbx_out
= (struct qlcnic_rcv_mbx_out
*)&cmd
.rsp
.arg
[1];
1151 recv_ctx
->context_id
= mbx_out
->ctx_id
;
1152 recv_ctx
->state
= mbx_out
->state
;
1153 recv_ctx
->virt_port
= mbx_out
->vport_id
;
1154 dev_info(&adapter
->pdev
->dev
, "Rx Context[%d] Created, state:0x%x\n",
1155 recv_ctx
->context_id
, recv_ctx
->state
);
1156 /* Receive descriptor ring */
1158 rds
= &recv_ctx
->rds_rings
[0];
1159 rds
->crb_rcv_producer
= ahw
->pci_base0
+
1160 mbx_out
->host_prod
[0].reg_buf
;
1162 rds
= &recv_ctx
->rds_rings
[1];
1163 rds
->crb_rcv_producer
= ahw
->pci_base0
+
1164 mbx_out
->host_prod
[0].jmb_buf
;
1165 /* status descriptor ring */
1166 for (i
= 0; i
< num_sds
; i
++) {
1167 sds
= &recv_ctx
->sds_rings
[i
];
1168 sds
->crb_sts_consumer
= ahw
->pci_base0
+
1169 mbx_out
->host_csmr
[i
];
1170 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
1171 intr_mask
= ahw
->intr_tbl
[i
].src
;
1173 intr_mask
= QLCRDX(ahw
, QLCNIC_DEF_INT_MASK
);
1174 sds
->crb_intr_mask
= ahw
->pci_base0
+ intr_mask
;
1177 if (adapter
->max_sds_rings
> QLCNIC_MAX_RING_SETS
)
1178 err
= qlcnic_83xx_add_rings(adapter
);
1180 qlcnic_free_mbx_args(&cmd
);
1184 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter
*adapter
,
1185 struct qlcnic_host_tx_ring
*tx_ring
)
1187 struct qlcnic_cmd_args cmd
;
1190 if (qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_DESTROY_TX_CTX
))
1193 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1194 cmd
.req
.arg
[0] |= (0x3 << 29);
1196 if (qlcnic_sriov_pf_check(adapter
))
1197 qlcnic_pf_set_interface_id_del_tx_ctx(adapter
, &temp
);
1199 cmd
.req
.arg
[1] = tx_ring
->ctx_id
| temp
;
1200 if (qlcnic_issue_cmd(adapter
, &cmd
))
1201 dev_err(&adapter
->pdev
->dev
,
1202 "Failed to destroy tx ctx in firmware\n");
1203 qlcnic_free_mbx_args(&cmd
);
1206 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter
*adapter
,
1207 struct qlcnic_host_tx_ring
*tx
, int ring
)
1211 u32
*buf
, intr_mask
, temp
= 0;
1212 struct qlcnic_cmd_args cmd
;
1213 struct qlcnic_tx_mbx mbx
;
1214 struct qlcnic_tx_mbx_out
*mbx_out
;
1215 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1218 /* Reset host resources */
1220 tx
->sw_consumer
= 0;
1221 *(tx
->hw_consumer
) = 0;
1223 memset(&mbx
, 0, sizeof(struct qlcnic_tx_mbx
));
1225 /* setup mailbox inbox registerss */
1226 mbx
.phys_addr_low
= LSD(tx
->phys_addr
);
1227 mbx
.phys_addr_high
= MSD(tx
->phys_addr
);
1228 mbx
.cnsmr_index_low
= LSD(tx
->hw_cons_phys_addr
);
1229 mbx
.cnsmr_index_high
= MSD(tx
->hw_cons_phys_addr
);
1230 mbx
.size
= tx
->num_desc
;
1231 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
) {
1232 if (!(adapter
->flags
& QLCNIC_TX_INTR_SHARED
))
1233 msix_vector
= adapter
->max_sds_rings
+ ring
;
1235 msix_vector
= adapter
->max_sds_rings
- 1;
1236 msix_id
= ahw
->intr_tbl
[msix_vector
].id
;
1238 msix_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
1241 if (adapter
->ahw
->diag_test
!= QLCNIC_LOOPBACK_TEST
)
1242 mbx
.intr_id
= msix_id
;
1244 mbx
.intr_id
= 0xffff;
1247 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CREATE_TX_CTX
);
1251 if (qlcnic_sriov_pf_check(adapter
) || qlcnic_sriov_vf_check(adapter
))
1252 cmd
.req
.arg
[0] |= (0x3 << 29);
1254 if (qlcnic_sriov_pf_check(adapter
))
1255 qlcnic_pf_set_interface_id_create_tx_ctx(adapter
, &temp
);
1257 cmd
.req
.arg
[1] = QLCNIC_CAP0_LEGACY_CONTEXT
;
1258 cmd
.req
.arg
[5] = QLCNIC_MAX_TX_QUEUES
| temp
;
1259 buf
= &cmd
.req
.arg
[6];
1260 memcpy(buf
, &mbx
, sizeof(struct qlcnic_tx_mbx
));
1261 /* send the mailbox command*/
1262 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1264 dev_err(&adapter
->pdev
->dev
,
1265 "Failed to create Tx ctx in firmware 0x%x\n", err
);
1268 mbx_out
= (struct qlcnic_tx_mbx_out
*)&cmd
.rsp
.arg
[2];
1269 tx
->crb_cmd_producer
= ahw
->pci_base0
+ mbx_out
->host_prod
;
1270 tx
->ctx_id
= mbx_out
->ctx_id
;
1271 if ((adapter
->flags
& QLCNIC_MSIX_ENABLED
) &&
1272 !(adapter
->flags
& QLCNIC_TX_INTR_SHARED
)) {
1273 intr_mask
= ahw
->intr_tbl
[adapter
->max_sds_rings
+ ring
].src
;
1274 tx
->crb_intr_mask
= ahw
->pci_base0
+ intr_mask
;
1276 dev_info(&adapter
->pdev
->dev
, "Tx Context[0x%x] Created, state:0x%x\n",
1277 tx
->ctx_id
, mbx_out
->state
);
1279 qlcnic_free_mbx_args(&cmd
);
1283 static int qlcnic_83xx_diag_alloc_res(struct net_device
*netdev
, int test
,
1286 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1287 struct qlcnic_host_sds_ring
*sds_ring
;
1288 struct qlcnic_host_rds_ring
*rds_ring
;
1289 u16 adapter_state
= adapter
->is_up
;
1293 netif_device_detach(netdev
);
1295 if (netif_running(netdev
))
1296 __qlcnic_down(adapter
, netdev
);
1298 qlcnic_detach(adapter
);
1300 adapter
->max_sds_rings
= 1;
1301 adapter
->ahw
->diag_test
= test
;
1302 adapter
->ahw
->linkup
= 0;
1304 ret
= qlcnic_attach(adapter
);
1306 netif_device_attach(netdev
);
1310 ret
= qlcnic_fw_create_ctx(adapter
);
1312 qlcnic_detach(adapter
);
1313 if (adapter_state
== QLCNIC_ADAPTER_UP_MAGIC
) {
1314 adapter
->max_sds_rings
= num_sds_ring
;
1315 qlcnic_attach(adapter
);
1317 netif_device_attach(netdev
);
1321 for (ring
= 0; ring
< adapter
->max_rds_rings
; ring
++) {
1322 rds_ring
= &adapter
->recv_ctx
->rds_rings
[ring
];
1323 qlcnic_post_rx_buffers(adapter
, rds_ring
, ring
);
1326 if (adapter
->ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
) {
1327 for (ring
= 0; ring
< adapter
->max_sds_rings
; ring
++) {
1328 sds_ring
= &adapter
->recv_ctx
->sds_rings
[ring
];
1329 qlcnic_83xx_enable_intr(adapter
, sds_ring
);
1333 if (adapter
->ahw
->diag_test
== QLCNIC_LOOPBACK_TEST
) {
1334 /* disable and free mailbox interrupt */
1335 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
)) {
1336 qlcnic_83xx_enable_mbx_poll(adapter
);
1337 qlcnic_83xx_free_mbx_intr(adapter
);
1339 adapter
->ahw
->loopback_state
= 0;
1340 adapter
->ahw
->hw_ops
->setup_link_event(adapter
, 1);
1343 set_bit(__QLCNIC_DEV_UP
, &adapter
->state
);
1347 static void qlcnic_83xx_diag_free_res(struct net_device
*netdev
,
1350 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1351 struct qlcnic_host_sds_ring
*sds_ring
;
1354 clear_bit(__QLCNIC_DEV_UP
, &adapter
->state
);
1355 if (adapter
->ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
) {
1356 for (ring
= 0; ring
< adapter
->max_sds_rings
; ring
++) {
1357 sds_ring
= &adapter
->recv_ctx
->sds_rings
[ring
];
1358 qlcnic_83xx_disable_intr(adapter
, sds_ring
);
1359 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
1360 qlcnic_83xx_enable_mbx_poll(adapter
);
1364 qlcnic_fw_destroy_ctx(adapter
);
1365 qlcnic_detach(adapter
);
1367 if (adapter
->ahw
->diag_test
== QLCNIC_LOOPBACK_TEST
) {
1368 if (!(adapter
->flags
& QLCNIC_MSIX_ENABLED
)) {
1369 err
= qlcnic_83xx_setup_mbx_intr(adapter
);
1370 qlcnic_83xx_disable_mbx_poll(adapter
);
1372 dev_err(&adapter
->pdev
->dev
,
1373 "%s: failed to setup mbx interrupt\n",
1379 adapter
->ahw
->diag_test
= 0;
1380 adapter
->max_sds_rings
= max_sds_rings
;
1382 if (qlcnic_attach(adapter
))
1385 if (netif_running(netdev
))
1386 __qlcnic_up(adapter
, netdev
);
1388 if (adapter
->ahw
->diag_test
== QLCNIC_INTERRUPT_TEST
&&
1389 !(adapter
->flags
& QLCNIC_MSIX_ENABLED
))
1390 qlcnic_83xx_disable_mbx_poll(adapter
);
1392 netif_device_attach(netdev
);
1395 int qlcnic_83xx_config_led(struct qlcnic_adapter
*adapter
, u32 state
,
1398 struct qlcnic_cmd_args cmd
;
1403 /* Get LED configuration */
1404 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1405 QLCNIC_CMD_GET_LED_CONFIG
);
1409 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1411 dev_err(&adapter
->pdev
->dev
,
1412 "Get led config failed.\n");
1415 for (i
= 0; i
< 4; i
++)
1416 adapter
->ahw
->mbox_reg
[i
] = cmd
.rsp
.arg
[i
+1];
1418 qlcnic_free_mbx_args(&cmd
);
1419 /* Set LED Configuration */
1420 mbx_in
= (LSW(QLC_83XX_LED_CONFIG
) << 16) |
1421 LSW(QLC_83XX_LED_CONFIG
);
1422 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1423 QLCNIC_CMD_SET_LED_CONFIG
);
1427 cmd
.req
.arg
[1] = mbx_in
;
1428 cmd
.req
.arg
[2] = mbx_in
;
1429 cmd
.req
.arg
[3] = mbx_in
;
1431 cmd
.req
.arg
[4] = QLC_83XX_ENABLE_BEACON
;
1432 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1434 dev_err(&adapter
->pdev
->dev
,
1435 "Set led config failed.\n");
1438 qlcnic_free_mbx_args(&cmd
);
1442 /* Restoring default LED configuration */
1443 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1444 QLCNIC_CMD_SET_LED_CONFIG
);
1448 cmd
.req
.arg
[1] = adapter
->ahw
->mbox_reg
[0];
1449 cmd
.req
.arg
[2] = adapter
->ahw
->mbox_reg
[1];
1450 cmd
.req
.arg
[3] = adapter
->ahw
->mbox_reg
[2];
1452 cmd
.req
.arg
[4] = adapter
->ahw
->mbox_reg
[3];
1453 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1455 dev_err(&adapter
->pdev
->dev
,
1456 "Restoring led config failed.\n");
1457 qlcnic_free_mbx_args(&cmd
);
1462 int qlcnic_83xx_set_led(struct net_device
*netdev
,
1463 enum ethtool_phys_id_state state
)
1465 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1466 int err
= -EIO
, active
= 1;
1468 if (adapter
->ahw
->op_mode
== QLCNIC_NON_PRIV_FUNC
) {
1470 "LED test is not supported in non-privileged mode\n");
1475 case ETHTOOL_ID_ACTIVE
:
1476 if (test_and_set_bit(__QLCNIC_LED_ENABLE
, &adapter
->state
))
1479 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
))
1482 err
= qlcnic_83xx_config_led(adapter
, active
, 0);
1484 netdev_err(netdev
, "Failed to set LED blink state\n");
1486 case ETHTOOL_ID_INACTIVE
:
1489 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
))
1492 err
= qlcnic_83xx_config_led(adapter
, active
, 0);
1494 netdev_err(netdev
, "Failed to reset LED blink state\n");
1502 clear_bit(__QLCNIC_LED_ENABLE
, &adapter
->state
);
1507 void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter
*adapter
,
1510 struct qlcnic_cmd_args cmd
;
1513 if (qlcnic_sriov_vf_check(adapter
))
1517 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1518 QLCNIC_CMD_INIT_NIC_FUNC
);
1522 cmd
.req
.arg
[1] = BIT_0
| BIT_31
;
1524 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1525 QLCNIC_CMD_STOP_NIC_FUNC
);
1529 cmd
.req
.arg
[1] = BIT_0
| BIT_31
;
1531 status
= qlcnic_issue_cmd(adapter
, &cmd
);
1533 dev_err(&adapter
->pdev
->dev
,
1534 "Failed to %s in NIC IDC function event.\n",
1535 (enable
? "register" : "unregister"));
1537 qlcnic_free_mbx_args(&cmd
);
1540 int qlcnic_83xx_set_port_config(struct qlcnic_adapter
*adapter
)
1542 struct qlcnic_cmd_args cmd
;
1545 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_SET_PORT_CONFIG
);
1549 cmd
.req
.arg
[1] = adapter
->ahw
->port_config
;
1550 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1552 dev_info(&adapter
->pdev
->dev
, "Set Port Config failed.\n");
1553 qlcnic_free_mbx_args(&cmd
);
1557 int qlcnic_83xx_get_port_config(struct qlcnic_adapter
*adapter
)
1559 struct qlcnic_cmd_args cmd
;
1562 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_PORT_CONFIG
);
1566 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1568 dev_info(&adapter
->pdev
->dev
, "Get Port config failed\n");
1570 adapter
->ahw
->port_config
= cmd
.rsp
.arg
[1];
1571 qlcnic_free_mbx_args(&cmd
);
1575 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter
*adapter
, int enable
)
1579 struct qlcnic_cmd_args cmd
;
1581 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_LINK_EVENT
);
1585 temp
= adapter
->recv_ctx
->context_id
<< 16;
1586 cmd
.req
.arg
[1] = (enable
? 1 : 0) | BIT_8
| temp
;
1587 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1589 dev_info(&adapter
->pdev
->dev
,
1590 "Setup linkevent mailbox failed\n");
1591 qlcnic_free_mbx_args(&cmd
);
1595 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter
*adapter
,
1598 if (qlcnic_sriov_pf_check(adapter
)) {
1599 qlcnic_pf_set_interface_id_promisc(adapter
, interface_id
);
1601 if (!qlcnic_sriov_vf_check(adapter
))
1602 *interface_id
= adapter
->recv_ctx
->context_id
<< 16;
1606 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter
*adapter
, u32 mode
)
1608 struct qlcnic_cmd_args
*cmd
= NULL
;
1612 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
1615 cmd
= kzalloc(sizeof(*cmd
), GFP_ATOMIC
);
1619 err
= qlcnic_alloc_mbx_args(cmd
, adapter
,
1620 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE
);
1624 cmd
->type
= QLC_83XX_MBX_CMD_NO_WAIT
;
1625 qlcnic_83xx_set_interface_id_promisc(adapter
, &temp
);
1626 cmd
->req
.arg
[1] = (mode
? 1 : 0) | temp
;
1627 err
= qlcnic_issue_cmd(adapter
, cmd
);
1631 qlcnic_free_mbx_args(cmd
);
1638 int qlcnic_83xx_loopback_test(struct net_device
*netdev
, u8 mode
)
1640 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1641 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1642 int ret
= 0, loop
= 0, max_sds_rings
= adapter
->max_sds_rings
;
1644 if (ahw
->op_mode
== QLCNIC_NON_PRIV_FUNC
) {
1646 "Loopback test not supported in non privileged mode\n");
1650 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1651 netdev_info(netdev
, "Device is resetting\n");
1655 if (qlcnic_get_diag_lock(adapter
)) {
1656 netdev_info(netdev
, "Device is in diagnostics mode\n");
1660 netdev_info(netdev
, "%s loopback test in progress\n",
1661 mode
== QLCNIC_ILB_MODE
? "internal" : "external");
1663 ret
= qlcnic_83xx_diag_alloc_res(netdev
, QLCNIC_LOOPBACK_TEST
,
1666 goto fail_diag_alloc
;
1668 ret
= qlcnic_83xx_set_lb_mode(adapter
, mode
);
1672 /* Poll for link up event before running traffic */
1674 msleep(QLC_83XX_LB_MSLEEP_COUNT
);
1676 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1678 "Device is resetting, free LB test resources\n");
1682 if (loop
++ > QLC_83XX_LB_WAIT_COUNT
) {
1684 "Firmware didn't sent link up event to loopback request\n");
1686 qlcnic_83xx_clear_lb_mode(adapter
, mode
);
1689 } while ((adapter
->ahw
->linkup
&& ahw
->has_link_events
) != 1);
1691 /* Make sure carrier is off and queue is stopped during loopback */
1692 if (netif_running(netdev
)) {
1693 netif_carrier_off(netdev
);
1694 netif_stop_queue(netdev
);
1697 ret
= qlcnic_do_lb_test(adapter
, mode
);
1699 qlcnic_83xx_clear_lb_mode(adapter
, mode
);
1702 qlcnic_83xx_diag_free_res(netdev
, max_sds_rings
);
1705 adapter
->max_sds_rings
= max_sds_rings
;
1706 qlcnic_release_diag_lock(adapter
);
1710 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter
*adapter
,
1711 u32
*max_wait_count
)
1713 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1716 netdev_info(adapter
->netdev
, "Recieved loopback IDC time extend event for 0x%x seconds\n",
1717 ahw
->extend_lb_time
);
1718 temp
= ahw
->extend_lb_time
* 1000;
1719 *max_wait_count
+= temp
/ QLC_83XX_LB_MSLEEP_COUNT
;
1720 ahw
->extend_lb_time
= 0;
1723 int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter
*adapter
, u8 mode
)
1725 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1726 struct net_device
*netdev
= adapter
->netdev
;
1727 u32 config
, max_wait_count
;
1728 int status
= 0, loop
= 0;
1730 ahw
->extend_lb_time
= 0;
1731 max_wait_count
= QLC_83XX_LB_WAIT_COUNT
;
1732 status
= qlcnic_83xx_get_port_config(adapter
);
1736 config
= ahw
->port_config
;
1738 /* Check if port is already in loopback mode */
1739 if ((config
& QLC_83XX_CFG_LOOPBACK_HSS
) ||
1740 (config
& QLC_83XX_CFG_LOOPBACK_EXT
)) {
1742 "Port already in Loopback mode.\n");
1743 return -EINPROGRESS
;
1746 set_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1748 if (mode
== QLCNIC_ILB_MODE
)
1749 ahw
->port_config
|= QLC_83XX_CFG_LOOPBACK_HSS
;
1750 if (mode
== QLCNIC_ELB_MODE
)
1751 ahw
->port_config
|= QLC_83XX_CFG_LOOPBACK_EXT
;
1753 status
= qlcnic_83xx_set_port_config(adapter
);
1756 "Failed to Set Loopback Mode = 0x%x.\n",
1758 ahw
->port_config
= config
;
1759 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1763 /* Wait for Link and IDC Completion AEN */
1765 msleep(QLC_83XX_LB_MSLEEP_COUNT
);
1767 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1769 "Device is resetting, free LB test resources\n");
1770 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1774 if (ahw
->extend_lb_time
)
1775 qlcnic_extend_lb_idc_cmpltn_wait(adapter
,
1778 if (loop
++ > max_wait_count
) {
1779 netdev_err(netdev
, "%s: Did not receive loopback IDC completion AEN\n",
1781 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1782 qlcnic_83xx_clear_lb_mode(adapter
, mode
);
1785 } while (test_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
));
1787 qlcnic_sre_macaddr_change(adapter
, adapter
->mac_addr
, 0,
1792 int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter
*adapter
, u8 mode
)
1794 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
1795 u32 config
= ahw
->port_config
, max_wait_count
;
1796 struct net_device
*netdev
= adapter
->netdev
;
1797 int status
= 0, loop
= 0;
1799 ahw
->extend_lb_time
= 0;
1800 max_wait_count
= QLC_83XX_LB_WAIT_COUNT
;
1801 set_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1802 if (mode
== QLCNIC_ILB_MODE
)
1803 ahw
->port_config
&= ~QLC_83XX_CFG_LOOPBACK_HSS
;
1804 if (mode
== QLCNIC_ELB_MODE
)
1805 ahw
->port_config
&= ~QLC_83XX_CFG_LOOPBACK_EXT
;
1807 status
= qlcnic_83xx_set_port_config(adapter
);
1810 "Failed to Clear Loopback Mode = 0x%x.\n",
1812 ahw
->port_config
= config
;
1813 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1817 /* Wait for Link and IDC Completion AEN */
1819 msleep(QLC_83XX_LB_MSLEEP_COUNT
);
1821 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
1823 "Device is resetting, free LB test resources\n");
1824 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1828 if (ahw
->extend_lb_time
)
1829 qlcnic_extend_lb_idc_cmpltn_wait(adapter
,
1832 if (loop
++ > max_wait_count
) {
1833 netdev_err(netdev
, "%s: Did not receive loopback IDC completion AEN\n",
1835 clear_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
);
1838 } while (test_bit(QLC_83XX_IDC_COMP_AEN
, &ahw
->idc
.status
));
1840 qlcnic_sre_macaddr_change(adapter
, adapter
->mac_addr
, 0,
1845 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter
*adapter
,
1848 if (qlcnic_sriov_pf_check(adapter
)) {
1849 qlcnic_pf_set_interface_id_ipaddr(adapter
, interface_id
);
1851 if (!qlcnic_sriov_vf_check(adapter
))
1852 *interface_id
= adapter
->recv_ctx
->context_id
<< 16;
1856 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter
*adapter
, __be32 ip
,
1860 u32 temp
= 0, temp_ip
;
1861 struct qlcnic_cmd_args cmd
;
1863 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1864 QLCNIC_CMD_CONFIGURE_IP_ADDR
);
1868 qlcnic_83xx_set_interface_id_ipaddr(adapter
, &temp
);
1870 if (mode
== QLCNIC_IP_UP
)
1871 cmd
.req
.arg
[1] = 1 | temp
;
1873 cmd
.req
.arg
[1] = 2 | temp
;
1876 * Adapter needs IP address in network byte order.
1877 * But hardware mailbox registers go through writel(), hence IP address
1878 * gets swapped on big endian architecture.
1879 * To negate swapping of writel() on big endian architecture
1880 * use swab32(value).
1883 temp_ip
= swab32(ntohl(ip
));
1884 memcpy(&cmd
.req
.arg
[2], &temp_ip
, sizeof(u32
));
1885 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1886 if (err
!= QLCNIC_RCODE_SUCCESS
)
1887 dev_err(&adapter
->netdev
->dev
,
1888 "could not notify %s IP 0x%x request\n",
1889 (mode
== QLCNIC_IP_UP
) ? "Add" : "Remove", ip
);
1891 qlcnic_free_mbx_args(&cmd
);
1894 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter
*adapter
, int mode
)
1898 struct qlcnic_cmd_args cmd
;
1901 lro_bit_mask
= (mode
? (BIT_0
| BIT_1
| BIT_2
| BIT_3
) : 0);
1903 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
1906 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIGURE_HW_LRO
);
1910 temp
= adapter
->recv_ctx
->context_id
<< 16;
1911 arg1
= lro_bit_mask
| temp
;
1912 cmd
.req
.arg
[1] = arg1
;
1914 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1916 dev_info(&adapter
->pdev
->dev
, "LRO config failed\n");
1917 qlcnic_free_mbx_args(&cmd
);
1922 int qlcnic_83xx_config_rss(struct qlcnic_adapter
*adapter
, int enable
)
1926 struct qlcnic_cmd_args cmd
;
1927 const u64 key
[] = { 0xbeac01fa6a42b73bULL
, 0x8030f20c77cb2da3ULL
,
1928 0xae7b30b4d0ca2bcbULL
, 0x43a38fb04167253dULL
,
1929 0x255b0ec26d5a56daULL
};
1931 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIGURE_RSS
);
1937 * 5-4: hash_type_ipv4
1938 * 7-6: hash_type_ipv6
1940 * 9: use indirection table
1941 * 16-31: indirection table mask
1943 word
= ((u32
)(RSS_HASHTYPE_IP_TCP
& 0x3) << 4) |
1944 ((u32
)(RSS_HASHTYPE_IP_TCP
& 0x3) << 6) |
1945 ((u32
)(enable
& 0x1) << 8) |
1947 cmd
.req
.arg
[1] = (adapter
->recv_ctx
->context_id
);
1948 cmd
.req
.arg
[2] = word
;
1949 memcpy(&cmd
.req
.arg
[4], key
, sizeof(key
));
1951 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1954 dev_info(&adapter
->pdev
->dev
, "RSS config failed\n");
1955 qlcnic_free_mbx_args(&cmd
);
1961 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter
*adapter
,
1964 if (qlcnic_sriov_pf_check(adapter
)) {
1965 qlcnic_pf_set_interface_id_macaddr(adapter
, interface_id
);
1967 if (!qlcnic_sriov_vf_check(adapter
))
1968 *interface_id
= adapter
->recv_ctx
->context_id
<< 16;
1972 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter
*adapter
, u8
*addr
,
1975 struct qlcnic_cmd_args
*cmd
= NULL
;
1976 struct qlcnic_macvlan_mbx mv
;
1980 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
1983 cmd
= kzalloc(sizeof(*cmd
), GFP_ATOMIC
);
1987 err
= qlcnic_alloc_mbx_args(cmd
, adapter
, QLCNIC_CMD_CONFIG_MAC_VLAN
);
1991 cmd
->type
= QLC_83XX_MBX_CMD_NO_WAIT
;
1994 op
= (op
== QLCNIC_MAC_ADD
|| op
== QLCNIC_MAC_VLAN_ADD
) ?
1995 QLCNIC_MAC_VLAN_ADD
: QLCNIC_MAC_VLAN_DEL
;
1997 cmd
->req
.arg
[1] = op
| (1 << 8);
1998 qlcnic_83xx_set_interface_id_macaddr(adapter
, &temp
);
1999 cmd
->req
.arg
[1] |= temp
;
2001 mv
.mac_addr0
= addr
[0];
2002 mv
.mac_addr1
= addr
[1];
2003 mv
.mac_addr2
= addr
[2];
2004 mv
.mac_addr3
= addr
[3];
2005 mv
.mac_addr4
= addr
[4];
2006 mv
.mac_addr5
= addr
[5];
2007 buf
= &cmd
->req
.arg
[2];
2008 memcpy(buf
, &mv
, sizeof(struct qlcnic_macvlan_mbx
));
2009 err
= qlcnic_issue_cmd(adapter
, cmd
);
2013 qlcnic_free_mbx_args(cmd
);
2019 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter
*adapter
, u64
*addr
,
2023 memcpy(&mac
, addr
, ETH_ALEN
);
2024 qlcnic_83xx_sre_macaddr_change(adapter
, mac
, vlan_id
, QLCNIC_MAC_ADD
);
2027 void qlcnic_83xx_configure_mac(struct qlcnic_adapter
*adapter
, u8
*mac
,
2028 u8 type
, struct qlcnic_cmd_args
*cmd
)
2031 case QLCNIC_SET_STATION_MAC
:
2032 case QLCNIC_SET_FAC_DEF_MAC
:
2033 memcpy(&cmd
->req
.arg
[2], mac
, sizeof(u32
));
2034 memcpy(&cmd
->req
.arg
[3], &mac
[4], sizeof(u16
));
2037 cmd
->req
.arg
[1] = type
;
2040 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter
*adapter
, u8
*mac
)
2043 struct qlcnic_cmd_args cmd
;
2044 u32 mac_low
, mac_high
;
2046 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_MAC_ADDRESS
);
2050 qlcnic_83xx_configure_mac(adapter
, mac
, QLCNIC_GET_CURRENT_MAC
, &cmd
);
2051 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2053 if (err
== QLCNIC_RCODE_SUCCESS
) {
2054 mac_low
= cmd
.rsp
.arg
[1];
2055 mac_high
= cmd
.rsp
.arg
[2];
2057 for (i
= 0; i
< 2; i
++)
2058 mac
[i
] = (u8
) (mac_high
>> ((1 - i
) * 8));
2059 for (i
= 2; i
< 6; i
++)
2060 mac
[i
] = (u8
) (mac_low
>> ((5 - i
) * 8));
2062 dev_err(&adapter
->pdev
->dev
, "Failed to get mac address%d\n",
2066 qlcnic_free_mbx_args(&cmd
);
2070 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter
*adapter
)
2074 struct qlcnic_cmd_args cmd
;
2075 struct qlcnic_nic_intr_coalesce
*coal
= &adapter
->ahw
->coal
;
2077 if (adapter
->recv_ctx
->state
== QLCNIC_HOST_CTX_STATE_FREED
)
2080 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIG_INTR_COAL
);
2084 if (coal
->type
== QLCNIC_INTR_COAL_TYPE_RX
) {
2085 temp
= adapter
->recv_ctx
->context_id
;
2086 cmd
.req
.arg
[1] = QLCNIC_INTR_COAL_TYPE_RX
| temp
<< 16;
2087 temp
= coal
->rx_time_us
;
2088 cmd
.req
.arg
[2] = coal
->rx_packets
| temp
<< 16;
2089 } else if (coal
->type
== QLCNIC_INTR_COAL_TYPE_TX
) {
2090 temp
= adapter
->tx_ring
->ctx_id
;
2091 cmd
.req
.arg
[1] = QLCNIC_INTR_COAL_TYPE_TX
| temp
<< 16;
2092 temp
= coal
->tx_time_us
;
2093 cmd
.req
.arg
[2] = coal
->tx_packets
| temp
<< 16;
2095 cmd
.req
.arg
[3] = coal
->flag
;
2096 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2097 if (err
!= QLCNIC_RCODE_SUCCESS
)
2098 dev_info(&adapter
->pdev
->dev
,
2099 "Failed to send interrupt coalescence parameters\n");
2100 qlcnic_free_mbx_args(&cmd
);
2103 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter
*adapter
,
2106 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2107 u8 link_status
, duplex
;
2109 link_status
= LSB(data
[3]) & 1;
2111 ahw
->link_speed
= MSW(data
[2]);
2112 duplex
= LSB(MSW(data
[3]));
2114 ahw
->link_duplex
= DUPLEX_FULL
;
2116 ahw
->link_duplex
= DUPLEX_HALF
;
2118 ahw
->link_speed
= SPEED_UNKNOWN
;
2119 ahw
->link_duplex
= DUPLEX_UNKNOWN
;
2122 ahw
->link_autoneg
= MSB(MSW(data
[3]));
2123 ahw
->module_type
= MSB(LSW(data
[3]));
2124 ahw
->has_link_events
= 1;
2125 qlcnic_advert_link_change(adapter
, link_status
);
2128 irqreturn_t
qlcnic_83xx_handle_aen(int irq
, void *data
)
2130 struct qlcnic_adapter
*adapter
= data
;
2131 struct qlcnic_mailbox
*mbx
;
2132 u32 mask
, resp
, event
;
2133 unsigned long flags
;
2135 mbx
= adapter
->ahw
->mailbox
;
2136 spin_lock_irqsave(&mbx
->aen_lock
, flags
);
2137 resp
= QLCRDX(adapter
->ahw
, QLCNIC_FW_MBX_CTRL
);
2138 if (!(resp
& QLCNIC_SET_OWNER
))
2141 event
= readl(QLCNIC_MBX_FW(adapter
->ahw
, 0));
2142 if (event
& QLCNIC_MBX_ASYNC_EVENT
)
2143 __qlcnic_83xx_process_aen(adapter
);
2145 qlcnic_83xx_notify_mbx_response(mbx
);
2148 mask
= QLCRDX(adapter
->ahw
, QLCNIC_DEF_INT_MASK
);
2149 writel(0, adapter
->ahw
->pci_base0
+ mask
);
2150 spin_unlock_irqrestore(&mbx
->aen_lock
, flags
);
2154 int qlcnic_enable_eswitch(struct qlcnic_adapter
*adapter
, u8 port
, u8 enable
)
2157 struct qlcnic_cmd_args cmd
;
2159 if (adapter
->ahw
->op_mode
!= QLCNIC_MGMT_FUNC
) {
2160 dev_err(&adapter
->pdev
->dev
,
2161 "%s: Error, invoked by non management func\n",
2166 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_TOGGLE_ESWITCH
);
2170 cmd
.req
.arg
[1] = (port
& 0xf) | BIT_4
;
2171 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2173 if (err
!= QLCNIC_RCODE_SUCCESS
) {
2174 dev_err(&adapter
->pdev
->dev
, "Failed to enable eswitch%d\n",
2178 qlcnic_free_mbx_args(&cmd
);
2184 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter
*adapter
,
2185 struct qlcnic_info
*nic
)
2188 struct qlcnic_cmd_args cmd
;
2190 if (adapter
->ahw
->op_mode
!= QLCNIC_MGMT_FUNC
) {
2191 dev_err(&adapter
->pdev
->dev
,
2192 "%s: Error, invoked by non management func\n",
2197 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_SET_NIC_INFO
);
2201 cmd
.req
.arg
[1] = (nic
->pci_func
<< 16);
2202 cmd
.req
.arg
[2] = 0x1 << 16;
2203 cmd
.req
.arg
[3] = nic
->phys_port
| (nic
->switch_mode
<< 16);
2204 cmd
.req
.arg
[4] = nic
->capabilities
;
2205 cmd
.req
.arg
[5] = (nic
->max_mac_filters
& 0xFF) | ((nic
->max_mtu
) << 16);
2206 cmd
.req
.arg
[6] = (nic
->max_tx_ques
) | ((nic
->max_rx_ques
) << 16);
2207 cmd
.req
.arg
[7] = (nic
->min_tx_bw
) | ((nic
->max_tx_bw
) << 16);
2208 for (i
= 8; i
< 32; i
++)
2211 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2213 if (err
!= QLCNIC_RCODE_SUCCESS
) {
2214 dev_err(&adapter
->pdev
->dev
, "Failed to set nic info%d\n",
2219 qlcnic_free_mbx_args(&cmd
);
2224 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter
*adapter
,
2225 struct qlcnic_info
*npar_info
, u8 func_id
)
2230 struct qlcnic_cmd_args cmd
;
2231 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2233 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_NIC_INFO
);
2237 if (func_id
!= ahw
->pci_func
) {
2238 temp
= func_id
<< 16;
2239 cmd
.req
.arg
[1] = op
| BIT_31
| temp
;
2241 cmd
.req
.arg
[1] = ahw
->pci_func
<< 16;
2243 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2245 dev_info(&adapter
->pdev
->dev
,
2246 "Failed to get nic info %d\n", err
);
2250 npar_info
->op_type
= cmd
.rsp
.arg
[1];
2251 npar_info
->pci_func
= cmd
.rsp
.arg
[2] & 0xFFFF;
2252 npar_info
->op_mode
= (cmd
.rsp
.arg
[2] & 0xFFFF0000) >> 16;
2253 npar_info
->phys_port
= cmd
.rsp
.arg
[3] & 0xFFFF;
2254 npar_info
->switch_mode
= (cmd
.rsp
.arg
[3] & 0xFFFF0000) >> 16;
2255 npar_info
->capabilities
= cmd
.rsp
.arg
[4];
2256 npar_info
->max_mac_filters
= cmd
.rsp
.arg
[5] & 0xFF;
2257 npar_info
->max_mtu
= (cmd
.rsp
.arg
[5] & 0xFFFF0000) >> 16;
2258 npar_info
->max_tx_ques
= cmd
.rsp
.arg
[6] & 0xFFFF;
2259 npar_info
->max_rx_ques
= (cmd
.rsp
.arg
[6] & 0xFFFF0000) >> 16;
2260 npar_info
->min_tx_bw
= cmd
.rsp
.arg
[7] & 0xFFFF;
2261 npar_info
->max_tx_bw
= (cmd
.rsp
.arg
[7] & 0xFFFF0000) >> 16;
2262 if (cmd
.rsp
.arg
[8] & 0x1)
2263 npar_info
->max_bw_reg_offset
= (cmd
.rsp
.arg
[8] & 0x7FFE) >> 1;
2264 if (cmd
.rsp
.arg
[8] & 0x10000) {
2265 temp
= (cmd
.rsp
.arg
[8] & 0x7FFE0000) >> 17;
2266 npar_info
->max_linkspeed_reg_offset
= temp
;
2268 if (npar_info
->capabilities
& QLCNIC_FW_CAPABILITY_MORE_CAPS
)
2269 memcpy(ahw
->extra_capability
, &cmd
.rsp
.arg
[16],
2270 sizeof(ahw
->extra_capability
));
2273 qlcnic_free_mbx_args(&cmd
);
2277 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter
*adapter
,
2278 struct qlcnic_pci_info
*pci_info
)
2280 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2281 struct device
*dev
= &adapter
->pdev
->dev
;
2282 struct qlcnic_cmd_args cmd
;
2283 int i
, err
= 0, j
= 0;
2286 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_PCI_INFO
);
2290 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2292 ahw
->act_pci_func
= 0;
2293 if (err
== QLCNIC_RCODE_SUCCESS
) {
2294 ahw
->max_pci_func
= cmd
.rsp
.arg
[1] & 0xFF;
2295 for (i
= 2, j
= 0; j
< QLCNIC_MAX_PCI_FUNC
; j
++, pci_info
++) {
2296 pci_info
->id
= cmd
.rsp
.arg
[i
] & 0xFFFF;
2297 pci_info
->active
= (cmd
.rsp
.arg
[i
] & 0xFFFF0000) >> 16;
2299 pci_info
->type
= cmd
.rsp
.arg
[i
] & 0xFFFF;
2300 if (pci_info
->type
== QLCNIC_TYPE_NIC
)
2301 ahw
->act_pci_func
++;
2302 temp
= (cmd
.rsp
.arg
[i
] & 0xFFFF0000) >> 16;
2303 pci_info
->default_port
= temp
;
2305 pci_info
->tx_min_bw
= cmd
.rsp
.arg
[i
] & 0xFFFF;
2306 temp
= (cmd
.rsp
.arg
[i
] & 0xFFFF0000) >> 16;
2307 pci_info
->tx_max_bw
= temp
;
2309 memcpy(pci_info
->mac
, &cmd
.rsp
.arg
[i
], ETH_ALEN
- 2);
2311 memcpy(pci_info
->mac
+ sizeof(u32
), &cmd
.rsp
.arg
[i
], 2);
2313 if (ahw
->op_mode
== QLCNIC_MGMT_FUNC
)
2314 dev_info(dev
, "id = %d active = %d type = %d\n"
2315 "\tport = %d min bw = %d max bw = %d\n"
2316 "\tmac_addr = %pM\n", pci_info
->id
,
2317 pci_info
->active
, pci_info
->type
,
2318 pci_info
->default_port
,
2319 pci_info
->tx_min_bw
,
2320 pci_info
->tx_max_bw
, pci_info
->mac
);
2322 if (ahw
->op_mode
== QLCNIC_MGMT_FUNC
)
2323 dev_info(dev
, "Max vNIC functions = %d, active vNIC functions = %d\n",
2324 ahw
->max_pci_func
, ahw
->act_pci_func
);
2327 dev_err(dev
, "Failed to get PCI Info, error = %d\n", err
);
2331 qlcnic_free_mbx_args(&cmd
);
2336 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter
*adapter
, bool op_type
)
2340 u32 val
, temp
, type
;
2341 struct qlcnic_cmd_args cmd
;
2343 max_ints
= adapter
->ahw
->num_msix
- 1;
2344 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_CONFIG_INTRPT
);
2348 cmd
.req
.arg
[1] = max_ints
;
2350 if (qlcnic_sriov_vf_check(adapter
))
2351 cmd
.req
.arg
[1] |= (adapter
->ahw
->pci_func
<< 8) | BIT_16
;
2353 for (i
= 0, index
= 2; i
< max_ints
; i
++) {
2354 type
= op_type
? QLCNIC_INTRPT_ADD
: QLCNIC_INTRPT_DEL
;
2355 val
= type
| (adapter
->ahw
->intr_tbl
[i
].type
<< 4);
2356 if (adapter
->ahw
->intr_tbl
[i
].type
== QLCNIC_INTRPT_MSIX
)
2357 val
|= (adapter
->ahw
->intr_tbl
[i
].id
<< 16);
2358 cmd
.req
.arg
[index
++] = val
;
2360 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2362 dev_err(&adapter
->pdev
->dev
,
2363 "Failed to configure interrupts 0x%x\n", err
);
2367 max_ints
= cmd
.rsp
.arg
[1];
2368 for (i
= 0, index
= 2; i
< max_ints
; i
++, index
+= 2) {
2369 val
= cmd
.rsp
.arg
[index
];
2371 dev_info(&adapter
->pdev
->dev
,
2372 "Can't configure interrupt %d\n",
2373 adapter
->ahw
->intr_tbl
[i
].id
);
2377 adapter
->ahw
->intr_tbl
[i
].id
= MSW(val
);
2378 adapter
->ahw
->intr_tbl
[i
].enabled
= 1;
2379 temp
= cmd
.rsp
.arg
[index
+ 1];
2380 adapter
->ahw
->intr_tbl
[i
].src
= temp
;
2382 adapter
->ahw
->intr_tbl
[i
].id
= i
;
2383 adapter
->ahw
->intr_tbl
[i
].enabled
= 0;
2384 adapter
->ahw
->intr_tbl
[i
].src
= 0;
2388 qlcnic_free_mbx_args(&cmd
);
2392 int qlcnic_83xx_lock_flash(struct qlcnic_adapter
*adapter
)
2394 int id
, timeout
= 0;
2397 while (status
== 0) {
2398 status
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FLASH_LOCK
);
2402 if (++timeout
>= QLC_83XX_FLASH_LOCK_TIMEOUT
) {
2403 id
= QLC_SHARED_REG_RD32(adapter
,
2404 QLCNIC_FLASH_LOCK_OWNER
);
2405 dev_err(&adapter
->pdev
->dev
,
2406 "%s: failed, lock held by %d\n", __func__
, id
);
2409 usleep_range(1000, 2000);
2412 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FLASH_LOCK_OWNER
, adapter
->portnum
);
2416 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter
*adapter
)
2418 QLC_SHARED_REG_RD32(adapter
, QLCNIC_FLASH_UNLOCK
);
2419 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FLASH_LOCK_OWNER
, 0xFF);
2422 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter
*adapter
,
2423 u32 flash_addr
, u8
*p_data
,
2426 u32 word
, range
, flash_offset
, addr
= flash_addr
, ret
;
2427 ulong indirect_add
, direct_window
;
2430 flash_offset
= addr
& (QLCNIC_FLASH_SECTOR_SIZE
- 1);
2432 dev_err(&adapter
->pdev
->dev
, "Illegal addr = 0x%x\n", addr
);
2436 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_DIRECT_WINDOW
,
2439 range
= flash_offset
+ (count
* sizeof(u32
));
2440 /* Check if data is spread across multiple sectors */
2441 if (range
> (QLCNIC_FLASH_SECTOR_SIZE
- 1)) {
2443 /* Multi sector read */
2444 for (i
= 0; i
< count
; i
++) {
2445 indirect_add
= QLC_83XX_FLASH_DIRECT_DATA(addr
);
2446 ret
= QLCRD32(adapter
, indirect_add
, &err
);
2451 *(u32
*)p_data
= word
;
2452 p_data
= p_data
+ 4;
2454 flash_offset
= flash_offset
+ 4;
2456 if (flash_offset
> (QLCNIC_FLASH_SECTOR_SIZE
- 1)) {
2457 direct_window
= QLC_83XX_FLASH_DIRECT_WINDOW
;
2458 /* This write is needed once for each sector */
2459 qlcnic_83xx_wrt_reg_indirect(adapter
,
2466 /* Single sector read */
2467 for (i
= 0; i
< count
; i
++) {
2468 indirect_add
= QLC_83XX_FLASH_DIRECT_DATA(addr
);
2469 ret
= QLCRD32(adapter
, indirect_add
, &err
);
2474 *(u32
*)p_data
= word
;
2475 p_data
= p_data
+ 4;
2483 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter
*adapter
)
2486 int retries
= QLC_83XX_FLASH_READ_RETRY_COUNT
;
2490 status
= QLCRD32(adapter
, QLC_83XX_FLASH_STATUS
, &err
);
2494 if ((status
& QLC_83XX_FLASH_STATUS_READY
) ==
2495 QLC_83XX_FLASH_STATUS_READY
)
2498 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY
);
2499 } while (--retries
);
2507 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter
*adapter
)
2511 cmd
= adapter
->ahw
->fdt
.write_statusreg_cmd
;
2512 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2513 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG
| cmd
));
2514 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2515 adapter
->ahw
->fdt
.write_enable_bits
);
2516 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2517 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL
);
2518 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2525 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter
*adapter
)
2529 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2530 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG
|
2531 adapter
->ahw
->fdt
.write_statusreg_cmd
));
2532 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2533 adapter
->ahw
->fdt
.write_disable_bits
);
2534 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2535 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL
);
2536 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2543 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter
*adapter
)
2548 if (qlcnic_83xx_lock_flash(adapter
))
2551 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2552 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL
);
2553 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2554 QLC_83XX_FLASH_READ_CTRL
);
2555 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2557 qlcnic_83xx_unlock_flash(adapter
);
2561 mfg_id
= QLCRD32(adapter
, QLC_83XX_FLASH_RDDATA
, &err
);
2563 qlcnic_83xx_unlock_flash(adapter
);
2567 adapter
->flash_mfg_id
= (mfg_id
& 0xFF);
2568 qlcnic_83xx_unlock_flash(adapter
);
2573 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter
*adapter
)
2575 int count
, fdt_size
, ret
= 0;
2577 fdt_size
= sizeof(struct qlcnic_fdt
);
2578 count
= fdt_size
/ sizeof(u32
);
2580 if (qlcnic_83xx_lock_flash(adapter
))
2583 memset(&adapter
->ahw
->fdt
, 0, fdt_size
);
2584 ret
= qlcnic_83xx_lockless_flash_read32(adapter
, QLCNIC_FDT_LOCATION
,
2585 (u8
*)&adapter
->ahw
->fdt
,
2588 qlcnic_83xx_unlock_flash(adapter
);
2592 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter
*adapter
,
2593 u32 sector_start_addr
)
2595 u32 reversed_addr
, addr1
, addr2
, cmd
;
2598 if (qlcnic_83xx_lock_flash(adapter
) != 0)
2601 if (adapter
->ahw
->fdt
.mfg_id
== adapter
->flash_mfg_id
) {
2602 ret
= qlcnic_83xx_enable_flash_write(adapter
);
2604 qlcnic_83xx_unlock_flash(adapter
);
2605 dev_err(&adapter
->pdev
->dev
,
2606 "%s failed at %d\n",
2607 __func__
, __LINE__
);
2612 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2614 qlcnic_83xx_unlock_flash(adapter
);
2615 dev_err(&adapter
->pdev
->dev
,
2616 "%s: failed at %d\n", __func__
, __LINE__
);
2620 addr1
= (sector_start_addr
& 0xFF) << 16;
2621 addr2
= (sector_start_addr
& 0xFF0000) >> 16;
2622 reversed_addr
= addr1
| addr2
;
2624 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2626 cmd
= QLC_83XX_FLASH_FDT_ERASE_DEF_SIG
| adapter
->ahw
->fdt
.erase_cmd
;
2627 if (adapter
->ahw
->fdt
.mfg_id
== adapter
->flash_mfg_id
)
2628 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
, cmd
);
2630 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2631 QLC_83XX_FLASH_OEM_ERASE_SIG
);
2632 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2633 QLC_83XX_FLASH_LAST_ERASE_MS_VAL
);
2635 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2637 qlcnic_83xx_unlock_flash(adapter
);
2638 dev_err(&adapter
->pdev
->dev
,
2639 "%s: failed at %d\n", __func__
, __LINE__
);
2643 if (adapter
->ahw
->fdt
.mfg_id
== adapter
->flash_mfg_id
) {
2644 ret
= qlcnic_83xx_disable_flash_write(adapter
);
2646 qlcnic_83xx_unlock_flash(adapter
);
2647 dev_err(&adapter
->pdev
->dev
,
2648 "%s: failed at %d\n", __func__
, __LINE__
);
2653 qlcnic_83xx_unlock_flash(adapter
);
2658 int qlcnic_83xx_flash_write32(struct qlcnic_adapter
*adapter
, u32 addr
,
2662 u32 addr1
= 0x00800000 | (addr
>> 2);
2664 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
, addr1
);
2665 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
, *p_data
);
2666 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2667 QLC_83XX_FLASH_LAST_ERASE_MS_VAL
);
2668 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2670 dev_err(&adapter
->pdev
->dev
,
2671 "%s: failed at %d\n", __func__
, __LINE__
);
2678 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter
*adapter
, u32 addr
,
2679 u32
*p_data
, int count
)
2682 int ret
= -EIO
, err
= 0;
2684 if ((count
< QLC_83XX_FLASH_WRITE_MIN
) ||
2685 (count
> QLC_83XX_FLASH_WRITE_MAX
)) {
2686 dev_err(&adapter
->pdev
->dev
,
2687 "%s: Invalid word count\n", __func__
);
2691 temp
= QLCRD32(adapter
, QLC_83XX_FLASH_SPI_CONTROL
, &err
);
2695 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_SPI_CONTROL
,
2696 (temp
| QLC_83XX_FLASH_SPI_CTRL
));
2697 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2698 QLC_83XX_FLASH_ADDR_TEMP_VAL
);
2700 /* First DWORD write */
2701 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
, *p_data
++);
2702 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2703 QLC_83XX_FLASH_FIRST_MS_PATTERN
);
2704 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2706 dev_err(&adapter
->pdev
->dev
,
2707 "%s: failed at %d\n", __func__
, __LINE__
);
2712 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2713 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL
);
2714 /* Second to N-1 DWORD writes */
2715 while (count
!= 1) {
2716 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
,
2718 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2719 QLC_83XX_FLASH_SECOND_MS_PATTERN
);
2720 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2722 dev_err(&adapter
->pdev
->dev
,
2723 "%s: failed at %d\n", __func__
, __LINE__
);
2729 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
2730 QLC_83XX_FLASH_ADDR_TEMP_VAL
|
2732 /* Last DWORD write */
2733 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_WRDATA
, *p_data
++);
2734 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
2735 QLC_83XX_FLASH_LAST_MS_PATTERN
);
2736 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
2738 dev_err(&adapter
->pdev
->dev
,
2739 "%s: failed at %d\n", __func__
, __LINE__
);
2743 ret
= QLCRD32(adapter
, QLC_83XX_FLASH_SPI_STATUS
, &err
);
2747 if ((ret
& QLC_83XX_FLASH_SPI_CTRL
) == QLC_83XX_FLASH_SPI_CTRL
) {
2748 dev_err(&adapter
->pdev
->dev
, "%s: failed at %d\n",
2749 __func__
, __LINE__
);
2750 /* Operation failed, clear error bit */
2751 temp
= QLCRD32(adapter
, QLC_83XX_FLASH_SPI_CONTROL
, &err
);
2755 qlcnic_83xx_wrt_reg_indirect(adapter
,
2756 QLC_83XX_FLASH_SPI_CONTROL
,
2757 (temp
| QLC_83XX_FLASH_SPI_CTRL
));
2763 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter
*adapter
)
2767 val
= QLCRDX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
);
2769 /* Check if recovery need to be performed by the calling function */
2770 if ((val
& QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK
) == 0) {
2772 val
= val
| ((adapter
->portnum
<< 2) |
2773 QLC_83XX_NEED_DRV_LOCK_RECOVERY
);
2774 QLCWRX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
, val
);
2775 dev_info(&adapter
->pdev
->dev
,
2776 "%s: lock recovery initiated\n", __func__
);
2777 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY
);
2778 val
= QLCRDX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
);
2779 id
= ((val
>> 2) & 0xF);
2780 if (id
== adapter
->portnum
) {
2781 val
= val
& ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK
;
2782 val
= val
| QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS
;
2783 QLCWRX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
, val
);
2784 /* Force release the lock */
2785 QLCRDX(adapter
->ahw
, QLC_83XX_DRV_UNLOCK
);
2786 /* Clear recovery bits */
2788 QLCWRX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
, val
);
2789 dev_info(&adapter
->pdev
->dev
,
2790 "%s: lock recovery completed\n", __func__
);
2792 dev_info(&adapter
->pdev
->dev
,
2793 "%s: func %d to resume lock recovery process\n",
2797 dev_info(&adapter
->pdev
->dev
,
2798 "%s: lock recovery initiated by other functions\n",
2803 int qlcnic_83xx_lock_driver(struct qlcnic_adapter
*adapter
)
2805 u32 lock_alive_counter
, val
, id
, i
= 0, status
= 0, temp
= 0;
2806 int max_attempt
= 0;
2808 while (status
== 0) {
2809 status
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK
);
2813 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY
);
2817 temp
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2819 if (i
== QLC_83XX_DRV_LOCK_WAIT_COUNTER
) {
2820 val
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2823 dev_info(&adapter
->pdev
->dev
,
2824 "%s: lock to be recovered from %d\n",
2826 qlcnic_83xx_recover_driver_lock(adapter
);
2830 dev_err(&adapter
->pdev
->dev
,
2831 "%s: failed to get lock\n", __func__
);
2836 /* Force exit from while loop after few attempts */
2837 if (max_attempt
== QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT
) {
2838 dev_err(&adapter
->pdev
->dev
,
2839 "%s: failed to get lock\n", __func__
);
2844 val
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2845 lock_alive_counter
= val
>> 8;
2846 lock_alive_counter
++;
2847 val
= lock_alive_counter
<< 8 | adapter
->portnum
;
2848 QLCWRX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
, val
);
2853 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter
*adapter
)
2855 u32 val
, lock_alive_counter
, id
;
2857 val
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
2859 lock_alive_counter
= val
>> 8;
2861 if (id
!= adapter
->portnum
)
2862 dev_err(&adapter
->pdev
->dev
,
2863 "%s:Warning func %d is unlocking lock owned by %d\n",
2864 __func__
, adapter
->portnum
, id
);
2866 val
= (lock_alive_counter
<< 8) | 0xFF;
2867 QLCWRX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
, val
);
2868 QLCRDX(adapter
->ahw
, QLC_83XX_DRV_UNLOCK
);
2871 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter
*adapter
, u64 addr
,
2872 u32
*data
, u32 count
)
2878 /* Check alignment */
2882 mutex_lock(&adapter
->ahw
->mem_lock
);
2883 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_ADDR_HI
, 0);
2885 for (i
= 0; i
< count
; i
++, addr
+= 16) {
2886 if (!((ADDR_IN_RANGE(addr
, QLCNIC_ADDR_QDR_NET
,
2887 QLCNIC_ADDR_QDR_NET_MAX
)) ||
2888 (ADDR_IN_RANGE(addr
, QLCNIC_ADDR_DDR_NET
,
2889 QLCNIC_ADDR_DDR_NET_MAX
)))) {
2890 mutex_unlock(&adapter
->ahw
->mem_lock
);
2894 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_ADDR_LO
, addr
);
2895 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_LO
,
2897 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_HI
,
2899 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_ULO
,
2901 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_WRTDATA_UHI
,
2903 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_CTRL
,
2904 QLCNIC_TA_WRITE_ENABLE
);
2905 qlcnic_83xx_wrt_reg_indirect(adapter
, QLCNIC_MS_CTRL
,
2906 QLCNIC_TA_WRITE_START
);
2908 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
2909 temp
= QLCRD32(adapter
, QLCNIC_MS_CTRL
, &err
);
2911 mutex_unlock(&adapter
->ahw
->mem_lock
);
2915 if ((temp
& TA_CTL_BUSY
) == 0)
2919 /* Status check failure */
2920 if (j
>= MAX_CTL_CHECK
) {
2921 printk_ratelimited(KERN_WARNING
2922 "MS memory write failed\n");
2923 mutex_unlock(&adapter
->ahw
->mem_lock
);
2928 mutex_unlock(&adapter
->ahw
->mem_lock
);
2933 int qlcnic_83xx_flash_read32(struct qlcnic_adapter
*adapter
, u32 flash_addr
,
2934 u8
*p_data
, int count
)
2936 u32 word
, addr
= flash_addr
, ret
;
2937 ulong indirect_addr
;
2940 if (qlcnic_83xx_lock_flash(adapter
) != 0)
2944 dev_err(&adapter
->pdev
->dev
, "Illegal addr = 0x%x\n", addr
);
2945 qlcnic_83xx_unlock_flash(adapter
);
2949 for (i
= 0; i
< count
; i
++) {
2950 if (qlcnic_83xx_wrt_reg_indirect(adapter
,
2951 QLC_83XX_FLASH_DIRECT_WINDOW
,
2953 qlcnic_83xx_unlock_flash(adapter
);
2957 indirect_addr
= QLC_83XX_FLASH_DIRECT_DATA(addr
);
2958 ret
= QLCRD32(adapter
, indirect_addr
, &err
);
2963 *(u32
*)p_data
= word
;
2964 p_data
= p_data
+ 4;
2968 qlcnic_83xx_unlock_flash(adapter
);
2973 int qlcnic_83xx_test_link(struct qlcnic_adapter
*adapter
)
2977 u32 config
= 0, state
;
2978 struct qlcnic_cmd_args cmd
;
2979 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2981 if (qlcnic_sriov_vf_check(adapter
))
2982 pci_func
= adapter
->portnum
;
2984 pci_func
= ahw
->pci_func
;
2986 state
= readl(ahw
->pci_base0
+ QLC_83XX_LINK_STATE(pci_func
));
2987 if (!QLC_83xx_FUNC_VAL(state
, pci_func
)) {
2988 dev_info(&adapter
->pdev
->dev
, "link state down\n");
2992 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_LINK_STATUS
);
2996 err
= qlcnic_issue_cmd(adapter
, &cmd
);
2998 dev_info(&adapter
->pdev
->dev
,
2999 "Get Link Status Command failed: 0x%x\n", err
);
3002 config
= cmd
.rsp
.arg
[1];
3003 switch (QLC_83XX_CURRENT_LINK_SPEED(config
)) {
3004 case QLC_83XX_10M_LINK
:
3005 ahw
->link_speed
= SPEED_10
;
3007 case QLC_83XX_100M_LINK
:
3008 ahw
->link_speed
= SPEED_100
;
3010 case QLC_83XX_1G_LINK
:
3011 ahw
->link_speed
= SPEED_1000
;
3013 case QLC_83XX_10G_LINK
:
3014 ahw
->link_speed
= SPEED_10000
;
3017 ahw
->link_speed
= 0;
3020 config
= cmd
.rsp
.arg
[3];
3021 if (QLC_83XX_SFP_PRESENT(config
)) {
3022 switch (ahw
->module_type
) {
3023 case LINKEVENT_MODULE_OPTICAL_UNKNOWN
:
3024 case LINKEVENT_MODULE_OPTICAL_SRLR
:
3025 case LINKEVENT_MODULE_OPTICAL_LRM
:
3026 case LINKEVENT_MODULE_OPTICAL_SFP_1G
:
3027 ahw
->supported_type
= PORT_FIBRE
;
3029 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE
:
3030 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN
:
3031 case LINKEVENT_MODULE_TWINAX
:
3032 ahw
->supported_type
= PORT_TP
;
3035 ahw
->supported_type
= PORT_OTHER
;
3042 qlcnic_free_mbx_args(&cmd
);
3046 int qlcnic_83xx_get_settings(struct qlcnic_adapter
*adapter
,
3047 struct ethtool_cmd
*ecmd
)
3051 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3053 /* Get port configuration info */
3054 status
= qlcnic_83xx_get_port_info(adapter
);
3055 /* Get Link Status related info */
3056 config
= qlcnic_83xx_test_link(adapter
);
3057 ahw
->module_type
= QLC_83XX_SFP_MODULE_TYPE(config
);
3058 /* hard code until there is a way to get it from flash */
3059 ahw
->board_type
= QLCNIC_BRDTYPE_83XX_10G
;
3061 if (netif_running(adapter
->netdev
) && ahw
->has_link_events
) {
3062 ethtool_cmd_speed_set(ecmd
, ahw
->link_speed
);
3063 ecmd
->duplex
= ahw
->link_duplex
;
3064 ecmd
->autoneg
= ahw
->link_autoneg
;
3066 ethtool_cmd_speed_set(ecmd
, SPEED_UNKNOWN
);
3067 ecmd
->duplex
= DUPLEX_UNKNOWN
;
3068 ecmd
->autoneg
= AUTONEG_DISABLE
;
3071 if (ahw
->port_type
== QLCNIC_XGBE
) {
3072 ecmd
->supported
= SUPPORTED_10000baseT_Full
;
3073 ecmd
->advertising
= ADVERTISED_10000baseT_Full
;
3075 ecmd
->supported
= (SUPPORTED_10baseT_Half
|
3076 SUPPORTED_10baseT_Full
|
3077 SUPPORTED_100baseT_Half
|
3078 SUPPORTED_100baseT_Full
|
3079 SUPPORTED_1000baseT_Half
|
3080 SUPPORTED_1000baseT_Full
);
3081 ecmd
->advertising
= (ADVERTISED_100baseT_Half
|
3082 ADVERTISED_100baseT_Full
|
3083 ADVERTISED_1000baseT_Half
|
3084 ADVERTISED_1000baseT_Full
);
3087 switch (ahw
->supported_type
) {
3089 ecmd
->supported
|= SUPPORTED_FIBRE
;
3090 ecmd
->advertising
|= ADVERTISED_FIBRE
;
3091 ecmd
->port
= PORT_FIBRE
;
3092 ecmd
->transceiver
= XCVR_EXTERNAL
;
3095 ecmd
->supported
|= SUPPORTED_TP
;
3096 ecmd
->advertising
|= ADVERTISED_TP
;
3097 ecmd
->port
= PORT_TP
;
3098 ecmd
->transceiver
= XCVR_INTERNAL
;
3101 ecmd
->supported
|= SUPPORTED_FIBRE
;
3102 ecmd
->advertising
|= ADVERTISED_FIBRE
;
3103 ecmd
->port
= PORT_OTHER
;
3104 ecmd
->transceiver
= XCVR_EXTERNAL
;
3107 ecmd
->phy_address
= ahw
->physical_port
;
3111 int qlcnic_83xx_set_settings(struct qlcnic_adapter
*adapter
,
3112 struct ethtool_cmd
*ecmd
)
3115 u32 config
= adapter
->ahw
->port_config
;
3118 adapter
->ahw
->port_config
|= BIT_15
;
3120 switch (ethtool_cmd_speed(ecmd
)) {
3122 adapter
->ahw
->port_config
|= BIT_8
;
3125 adapter
->ahw
->port_config
|= BIT_9
;
3128 adapter
->ahw
->port_config
|= BIT_10
;
3131 adapter
->ahw
->port_config
|= BIT_11
;
3137 status
= qlcnic_83xx_set_port_config(adapter
);
3139 dev_info(&adapter
->pdev
->dev
,
3140 "Faild to Set Link Speed and autoneg.\n");
3141 adapter
->ahw
->port_config
= config
;
3146 static inline u64
*qlcnic_83xx_copy_stats(struct qlcnic_cmd_args
*cmd
,
3147 u64
*data
, int index
)
3152 low
= cmd
->rsp
.arg
[index
];
3153 hi
= cmd
->rsp
.arg
[index
+ 1];
3154 val
= (((u64
) low
) | (((u64
) hi
) << 32));
3159 static u64
*qlcnic_83xx_fill_stats(struct qlcnic_adapter
*adapter
,
3160 struct qlcnic_cmd_args
*cmd
, u64
*data
,
3163 int err
, k
, total_regs
;
3166 err
= qlcnic_issue_cmd(adapter
, cmd
);
3167 if (err
!= QLCNIC_RCODE_SUCCESS
) {
3168 dev_info(&adapter
->pdev
->dev
,
3169 "Error in get statistics mailbox command\n");
3173 total_regs
= cmd
->rsp
.num
;
3175 case QLC_83XX_STAT_MAC
:
3176 /* fill in MAC tx counters */
3177 for (k
= 2; k
< 28; k
+= 2)
3178 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3179 /* skip 24 bytes of reserved area */
3180 /* fill in MAC rx counters */
3181 for (k
+= 6; k
< 60; k
+= 2)
3182 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3183 /* skip 24 bytes of reserved area */
3184 /* fill in MAC rx frame stats */
3185 for (k
+= 6; k
< 80; k
+= 2)
3186 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3187 /* fill in eSwitch stats */
3188 for (; k
< total_regs
; k
+= 2)
3189 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3191 case QLC_83XX_STAT_RX
:
3192 for (k
= 2; k
< 8; k
+= 2)
3193 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3194 /* skip 8 bytes of reserved data */
3195 for (k
+= 2; k
< 24; k
+= 2)
3196 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3197 /* skip 8 bytes containing RE1FBQ error data */
3198 for (k
+= 2; k
< total_regs
; k
+= 2)
3199 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3201 case QLC_83XX_STAT_TX
:
3202 for (k
= 2; k
< 10; k
+= 2)
3203 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3204 /* skip 8 bytes of reserved data */
3205 for (k
+= 2; k
< total_regs
; k
+= 2)
3206 data
= qlcnic_83xx_copy_stats(cmd
, data
, k
);
3209 dev_warn(&adapter
->pdev
->dev
, "Unknown get statistics mode\n");
3215 void qlcnic_83xx_get_stats(struct qlcnic_adapter
*adapter
, u64
*data
)
3217 struct qlcnic_cmd_args cmd
;
3218 struct net_device
*netdev
= adapter
->netdev
;
3221 ret
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_STATISTICS
);
3225 cmd
.req
.arg
[1] = BIT_1
| (adapter
->tx_ring
->ctx_id
<< 16);
3226 cmd
.rsp
.num
= QLC_83XX_TX_STAT_REGS
;
3227 data
= qlcnic_83xx_fill_stats(adapter
, &cmd
, data
,
3228 QLC_83XX_STAT_TX
, &ret
);
3230 netdev_err(netdev
, "Error getting Tx stats\n");
3234 cmd
.req
.arg
[1] = BIT_2
| (adapter
->portnum
<< 16);
3235 cmd
.rsp
.num
= QLC_83XX_MAC_STAT_REGS
;
3236 memset(cmd
.rsp
.arg
, 0, sizeof(u32
) * cmd
.rsp
.num
);
3237 data
= qlcnic_83xx_fill_stats(adapter
, &cmd
, data
,
3238 QLC_83XX_STAT_MAC
, &ret
);
3240 netdev_err(netdev
, "Error getting MAC stats\n");
3244 cmd
.req
.arg
[1] = adapter
->recv_ctx
->context_id
<< 16;
3245 cmd
.rsp
.num
= QLC_83XX_RX_STAT_REGS
;
3246 memset(cmd
.rsp
.arg
, 0, sizeof(u32
) * cmd
.rsp
.num
);
3247 data
= qlcnic_83xx_fill_stats(adapter
, &cmd
, data
,
3248 QLC_83XX_STAT_RX
, &ret
);
3250 netdev_err(netdev
, "Error getting Rx stats\n");
3252 qlcnic_free_mbx_args(&cmd
);
3255 int qlcnic_83xx_reg_test(struct qlcnic_adapter
*adapter
)
3257 u32 major
, minor
, sub
;
3259 major
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MAJOR
);
3260 minor
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_MINOR
);
3261 sub
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_FW_VERSION_SUB
);
3263 if (adapter
->fw_version
!= QLCNIC_VERSION_CODE(major
, minor
, sub
)) {
3264 dev_info(&adapter
->pdev
->dev
, "%s: Reg test failed\n",
3271 int qlcnic_83xx_get_regs_len(struct qlcnic_adapter
*adapter
)
3273 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl
) *
3274 sizeof(adapter
->ahw
->ext_reg_tbl
)) +
3275 (ARRAY_SIZE(qlcnic_83xx_reg_tbl
) +
3276 sizeof(adapter
->ahw
->reg_tbl
));
3279 int qlcnic_83xx_get_registers(struct qlcnic_adapter
*adapter
, u32
*regs_buff
)
3283 for (i
= QLCNIC_DEV_INFO_SIZE
+ 1;
3284 j
< ARRAY_SIZE(qlcnic_83xx_reg_tbl
); i
++, j
++)
3285 regs_buff
[i
] = QLC_SHARED_REG_RD32(adapter
, j
);
3287 for (j
= 0; j
< ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl
); j
++)
3288 regs_buff
[i
++] = QLCRDX(adapter
->ahw
, j
);
3292 int qlcnic_83xx_interrupt_test(struct net_device
*netdev
)
3294 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
3295 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3296 struct qlcnic_cmd_args cmd
;
3300 int ret
, max_sds_rings
= adapter
->max_sds_rings
;
3302 if (test_bit(__QLCNIC_RESETTING
, &adapter
->state
)) {
3303 netdev_info(netdev
, "Device is resetting\n");
3307 if (qlcnic_get_diag_lock(adapter
)) {
3308 netdev_info(netdev
, "Device in diagnostics mode\n");
3312 ret
= qlcnic_83xx_diag_alloc_res(netdev
, QLCNIC_INTERRUPT_TEST
,
3318 ret
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_INTRPT_TEST
);
3322 if (adapter
->flags
& QLCNIC_MSIX_ENABLED
)
3323 intrpt_id
= ahw
->intr_tbl
[0].id
;
3325 intrpt_id
= QLCRDX(ahw
, QLCNIC_DEF_INT_ID
);
3328 cmd
.req
.arg
[2] = intrpt_id
;
3329 cmd
.req
.arg
[3] = BIT_0
;
3331 ret
= qlcnic_issue_cmd(adapter
, &cmd
);
3332 data
= cmd
.rsp
.arg
[2];
3334 val
= LSB(MSW(data
));
3335 if (id
!= intrpt_id
)
3336 dev_info(&adapter
->pdev
->dev
,
3337 "Interrupt generated: 0x%x, requested:0x%x\n",
3340 dev_err(&adapter
->pdev
->dev
,
3341 "Interrupt test error: 0x%x\n", val
);
3346 ret
= !ahw
->diag_cnt
;
3349 qlcnic_free_mbx_args(&cmd
);
3350 qlcnic_83xx_diag_free_res(netdev
, max_sds_rings
);
3353 adapter
->max_sds_rings
= max_sds_rings
;
3354 qlcnic_release_diag_lock(adapter
);
3358 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter
*adapter
,
3359 struct ethtool_pauseparam
*pause
)
3361 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3365 status
= qlcnic_83xx_get_port_config(adapter
);
3367 dev_err(&adapter
->pdev
->dev
,
3368 "%s: Get Pause Config failed\n", __func__
);
3371 config
= ahw
->port_config
;
3372 if (config
& QLC_83XX_CFG_STD_PAUSE
) {
3373 if (config
& QLC_83XX_CFG_STD_TX_PAUSE
)
3374 pause
->tx_pause
= 1;
3375 if (config
& QLC_83XX_CFG_STD_RX_PAUSE
)
3376 pause
->rx_pause
= 1;
3379 if (QLC_83XX_AUTONEG(config
))
3383 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter
*adapter
,
3384 struct ethtool_pauseparam
*pause
)
3386 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3390 status
= qlcnic_83xx_get_port_config(adapter
);
3392 dev_err(&adapter
->pdev
->dev
,
3393 "%s: Get Pause Config failed.\n", __func__
);
3396 config
= ahw
->port_config
;
3398 if (ahw
->port_type
== QLCNIC_GBE
) {
3400 ahw
->port_config
|= QLC_83XX_ENABLE_AUTONEG
;
3401 if (!pause
->autoneg
)
3402 ahw
->port_config
&= ~QLC_83XX_ENABLE_AUTONEG
;
3403 } else if ((ahw
->port_type
== QLCNIC_XGBE
) && (pause
->autoneg
)) {
3407 if (!(config
& QLC_83XX_CFG_STD_PAUSE
))
3408 ahw
->port_config
|= QLC_83XX_CFG_STD_PAUSE
;
3410 if (pause
->rx_pause
&& pause
->tx_pause
) {
3411 ahw
->port_config
|= QLC_83XX_CFG_STD_TX_RX_PAUSE
;
3412 } else if (pause
->rx_pause
&& !pause
->tx_pause
) {
3413 ahw
->port_config
&= ~QLC_83XX_CFG_STD_TX_PAUSE
;
3414 ahw
->port_config
|= QLC_83XX_CFG_STD_RX_PAUSE
;
3415 } else if (pause
->tx_pause
&& !pause
->rx_pause
) {
3416 ahw
->port_config
&= ~QLC_83XX_CFG_STD_RX_PAUSE
;
3417 ahw
->port_config
|= QLC_83XX_CFG_STD_TX_PAUSE
;
3418 } else if (!pause
->rx_pause
&& !pause
->tx_pause
) {
3419 ahw
->port_config
&= ~QLC_83XX_CFG_STD_TX_RX_PAUSE
;
3421 status
= qlcnic_83xx_set_port_config(adapter
);
3423 dev_err(&adapter
->pdev
->dev
,
3424 "%s: Set Pause Config failed.\n", __func__
);
3425 ahw
->port_config
= config
;
3430 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter
*adapter
)
3435 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_ADDR
,
3436 QLC_83XX_FLASH_OEM_READ_SIG
);
3437 qlcnic_83xx_wrt_reg_indirect(adapter
, QLC_83XX_FLASH_CONTROL
,
3438 QLC_83XX_FLASH_READ_CTRL
);
3439 ret
= qlcnic_83xx_poll_flash_status_reg(adapter
);
3443 temp
= QLCRD32(adapter
, QLC_83XX_FLASH_RDDATA
, &err
);
3450 int qlcnic_83xx_flash_test(struct qlcnic_adapter
*adapter
)
3454 status
= qlcnic_83xx_read_flash_status_reg(adapter
);
3455 if (status
== -EIO
) {
3456 dev_info(&adapter
->pdev
->dev
, "%s: EEPROM test failed.\n",
3463 int qlcnic_83xx_shutdown(struct pci_dev
*pdev
)
3465 struct qlcnic_adapter
*adapter
= pci_get_drvdata(pdev
);
3466 struct net_device
*netdev
= adapter
->netdev
;
3469 netif_device_detach(netdev
);
3470 qlcnic_cancel_idc_work(adapter
);
3472 if (netif_running(netdev
))
3473 qlcnic_down(adapter
, netdev
);
3475 qlcnic_83xx_disable_mbx_intr(adapter
);
3476 cancel_delayed_work_sync(&adapter
->idc_aen_work
);
3478 retval
= pci_save_state(pdev
);
3485 int qlcnic_83xx_resume(struct qlcnic_adapter
*adapter
)
3487 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3488 struct qlc_83xx_idc
*idc
= &ahw
->idc
;
3491 err
= qlcnic_83xx_idc_init(adapter
);
3495 if (ahw
->nic_mode
== QLC_83XX_VIRTUAL_NIC_MODE
) {
3496 if (ahw
->op_mode
== QLCNIC_MGMT_FUNC
) {
3497 qlcnic_83xx_set_vnic_opmode(adapter
);
3499 err
= qlcnic_83xx_check_vnic_state(adapter
);
3505 err
= qlcnic_83xx_idc_reattach_driver(adapter
);
3509 qlcnic_schedule_work(adapter
, qlcnic_83xx_idc_poll_dev_state
,
3514 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox
*mbx
)
3516 INIT_COMPLETION(mbx
->completion
);
3517 set_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3520 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox
*mbx
)
3522 destroy_workqueue(mbx
->work_q
);
3527 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter
*adapter
,
3528 struct qlcnic_cmd_args
*cmd
)
3530 atomic_set(&cmd
->rsp_status
, QLC_83XX_MBX_RESPONSE_ARRIVED
);
3532 if (cmd
->type
== QLC_83XX_MBX_CMD_NO_WAIT
) {
3533 qlcnic_free_mbx_args(cmd
);
3537 complete(&cmd
->completion
);
3540 static inline void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter
*adapter
)
3542 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3543 struct list_head
*head
= &mbx
->cmd_q
;
3544 struct qlcnic_cmd_args
*cmd
= NULL
;
3546 spin_lock(&mbx
->queue_lock
);
3548 while (!list_empty(head
)) {
3549 cmd
= list_entry(head
->next
, struct qlcnic_cmd_args
, list
);
3550 dev_info(&adapter
->pdev
->dev
, "%s: Mailbox command 0x%x\n",
3551 __func__
, cmd
->cmd_op
);
3552 list_del(&cmd
->list
);
3554 qlcnic_83xx_notify_cmd_completion(adapter
, cmd
);
3557 spin_unlock(&mbx
->queue_lock
);
3560 static inline int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter
*adapter
)
3562 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3563 struct qlcnic_mailbox
*mbx
= ahw
->mailbox
;
3566 if (!test_bit(QLC_83XX_MBX_READY
, &mbx
->status
))
3569 host_mbx_ctrl
= QLCRDX(ahw
, QLCNIC_HOST_MBX_CTRL
);
3570 if (host_mbx_ctrl
) {
3571 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3572 ahw
->idc
.collect_dump
= 1;
3579 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter
*adapter
,
3583 QLCWRX(adapter
->ahw
, QLCNIC_HOST_MBX_CTRL
, QLCNIC_SET_OWNER
);
3585 QLCWRX(adapter
->ahw
, QLCNIC_FW_MBX_CTRL
, QLCNIC_CLR_OWNER
);
3588 static inline void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter
*adapter
,
3589 struct qlcnic_cmd_args
*cmd
)
3591 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3593 spin_lock(&mbx
->queue_lock
);
3595 list_del(&cmd
->list
);
3598 spin_unlock(&mbx
->queue_lock
);
3600 qlcnic_83xx_notify_cmd_completion(adapter
, cmd
);
3603 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter
*adapter
,
3604 struct qlcnic_cmd_args
*cmd
)
3606 u32 mbx_cmd
, fw_hal_version
, hdr_size
, total_size
, tmp
;
3607 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3610 if (cmd
->op_type
!= QLC_83XX_MBX_POST_BC_OP
) {
3611 mbx_cmd
= cmd
->req
.arg
[0];
3612 writel(mbx_cmd
, QLCNIC_MBX_HOST(ahw
, 0));
3613 for (i
= 1; i
< cmd
->req
.num
; i
++)
3614 writel(cmd
->req
.arg
[i
], QLCNIC_MBX_HOST(ahw
, i
));
3616 fw_hal_version
= ahw
->fw_hal_version
;
3617 hdr_size
= sizeof(struct qlcnic_bc_hdr
) / sizeof(u32
);
3618 total_size
= cmd
->pay_size
+ hdr_size
;
3619 tmp
= QLCNIC_CMD_BC_EVENT_SETUP
| total_size
<< 16;
3620 mbx_cmd
= tmp
| fw_hal_version
<< 29;
3621 writel(mbx_cmd
, QLCNIC_MBX_HOST(ahw
, 0));
3623 /* Back channel specific operations bits */
3624 mbx_cmd
= 0x1 | 1 << 4;
3626 if (qlcnic_sriov_pf_check(adapter
))
3627 mbx_cmd
|= cmd
->func_num
<< 5;
3629 writel(mbx_cmd
, QLCNIC_MBX_HOST(ahw
, 1));
3631 for (i
= 2, j
= 0; j
< hdr_size
; i
++, j
++)
3632 writel(*(cmd
->hdr
++), QLCNIC_MBX_HOST(ahw
, i
));
3633 for (j
= 0; j
< cmd
->pay_size
; j
++, i
++)
3634 writel(*(cmd
->pay
++), QLCNIC_MBX_HOST(ahw
, i
));
3638 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter
*adapter
)
3640 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3642 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3643 complete(&mbx
->completion
);
3644 cancel_work_sync(&mbx
->work
);
3645 flush_workqueue(mbx
->work_q
);
3646 qlcnic_83xx_flush_mbx_queue(adapter
);
3649 static inline int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter
*adapter
,
3650 struct qlcnic_cmd_args
*cmd
,
3651 unsigned long *timeout
)
3653 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
3655 if (test_bit(QLC_83XX_MBX_READY
, &mbx
->status
)) {
3656 atomic_set(&cmd
->rsp_status
, QLC_83XX_MBX_RESPONSE_WAIT
);
3657 init_completion(&cmd
->completion
);
3658 cmd
->rsp_opcode
= QLC_83XX_MBX_RESPONSE_UNKNOWN
;
3660 spin_lock(&mbx
->queue_lock
);
3662 list_add_tail(&cmd
->list
, &mbx
->cmd_q
);
3664 cmd
->total_cmds
= mbx
->num_cmds
;
3665 *timeout
= cmd
->total_cmds
* QLC_83XX_MBX_TIMEOUT
;
3666 queue_work(mbx
->work_q
, &mbx
->work
);
3668 spin_unlock(&mbx
->queue_lock
);
3676 static inline int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter
*adapter
,
3677 struct qlcnic_cmd_args
*cmd
)
3682 if (cmd
->cmd_op
== QLCNIC_CMD_CONFIG_MAC_VLAN
) {
3683 fw_data
= readl(QLCNIC_MBX_FW(adapter
->ahw
, 2));
3684 mac_cmd_rcode
= (u8
)fw_data
;
3685 if (mac_cmd_rcode
== QLC_83XX_NO_NIC_RESOURCE
||
3686 mac_cmd_rcode
== QLC_83XX_MAC_PRESENT
||
3687 mac_cmd_rcode
== QLC_83XX_MAC_ABSENT
) {
3688 cmd
->rsp_opcode
= QLCNIC_RCODE_SUCCESS
;
3689 return QLCNIC_RCODE_SUCCESS
;
3696 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter
*adapter
,
3697 struct qlcnic_cmd_args
*cmd
)
3699 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3700 struct device
*dev
= &adapter
->pdev
->dev
;
3704 fw_data
= readl(QLCNIC_MBX_FW(ahw
, 0));
3705 mbx_err_code
= QLCNIC_MBX_STATUS(fw_data
);
3706 qlcnic_83xx_get_mbx_data(adapter
, cmd
);
3708 switch (mbx_err_code
) {
3709 case QLCNIC_MBX_RSP_OK
:
3710 case QLCNIC_MBX_PORT_RSP_OK
:
3711 cmd
->rsp_opcode
= QLCNIC_RCODE_SUCCESS
;
3714 if (!qlcnic_83xx_check_mac_rcode(adapter
, cmd
))
3717 dev_err(dev
, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3718 __func__
, cmd
->cmd_op
, cmd
->type
, ahw
->pci_func
,
3719 ahw
->op_mode
, mbx_err_code
);
3720 cmd
->rsp_opcode
= QLC_83XX_MBX_RESPONSE_FAILED
;
3721 qlcnic_dump_mbx(adapter
, cmd
);
3727 static void qlcnic_83xx_mailbox_worker(struct work_struct
*work
)
3729 struct qlcnic_mailbox
*mbx
= container_of(work
, struct qlcnic_mailbox
,
3731 struct qlcnic_adapter
*adapter
= mbx
->adapter
;
3732 struct qlcnic_mbx_ops
*mbx_ops
= mbx
->ops
;
3733 struct device
*dev
= &adapter
->pdev
->dev
;
3734 atomic_t
*rsp_status
= &mbx
->rsp_status
;
3735 struct list_head
*head
= &mbx
->cmd_q
;
3736 struct qlcnic_hardware_context
*ahw
;
3737 struct qlcnic_cmd_args
*cmd
= NULL
;
3742 if (qlcnic_83xx_check_mbx_status(adapter
)) {
3743 qlcnic_83xx_flush_mbx_queue(adapter
);
3747 atomic_set(rsp_status
, QLC_83XX_MBX_RESPONSE_WAIT
);
3749 spin_lock(&mbx
->queue_lock
);
3751 if (list_empty(head
)) {
3752 spin_unlock(&mbx
->queue_lock
);
3755 cmd
= list_entry(head
->next
, struct qlcnic_cmd_args
, list
);
3757 spin_unlock(&mbx
->queue_lock
);
3759 mbx_ops
->encode_cmd(adapter
, cmd
);
3760 mbx_ops
->nofity_fw(adapter
, QLC_83XX_MBX_REQUEST
);
3762 if (wait_for_completion_timeout(&mbx
->completion
,
3763 QLC_83XX_MBX_TIMEOUT
)) {
3764 mbx_ops
->decode_resp(adapter
, cmd
);
3765 mbx_ops
->nofity_fw(adapter
, QLC_83XX_MBX_COMPLETION
);
3767 dev_err(dev
, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3768 __func__
, cmd
->cmd_op
, cmd
->type
, ahw
->pci_func
,
3770 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
3771 qlcnic_dump_mbx(adapter
, cmd
);
3772 qlcnic_83xx_idc_request_reset(adapter
,
3773 QLCNIC_FORCE_FW_DUMP_KEY
);
3774 cmd
->rsp_opcode
= QLCNIC_RCODE_TIMEOUT
;
3776 mbx_ops
->dequeue_cmd(adapter
, cmd
);
3780 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops
= {
3781 .enqueue_cmd
= qlcnic_83xx_enqueue_mbx_cmd
,
3782 .dequeue_cmd
= qlcnic_83xx_dequeue_mbx_cmd
,
3783 .decode_resp
= qlcnic_83xx_decode_mbx_rsp
,
3784 .encode_cmd
= qlcnic_83xx_encode_mbx_cmd
,
3785 .nofity_fw
= qlcnic_83xx_signal_mbx_cmd
,
3788 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter
*adapter
)
3790 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
3791 struct qlcnic_mailbox
*mbx
;
3793 ahw
->mailbox
= kzalloc(sizeof(*mbx
), GFP_KERNEL
);
3798 mbx
->ops
= &qlcnic_83xx_mbx_ops
;
3799 mbx
->adapter
= adapter
;
3801 spin_lock_init(&mbx
->queue_lock
);
3802 spin_lock_init(&mbx
->aen_lock
);
3803 INIT_LIST_HEAD(&mbx
->cmd_q
);
3804 init_completion(&mbx
->completion
);
3806 mbx
->work_q
= create_singlethread_workqueue("qlcnic_mailbox");
3807 if (mbx
->work_q
== NULL
) {
3812 INIT_WORK(&mbx
->work
, qlcnic_83xx_mailbox_worker
);
3813 set_bit(QLC_83XX_MBX_READY
, &mbx
->status
);