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[deliverable/linux.git] / drivers / net / ethernet / qlogic / qlcnic / qlcnic_83xx_hw.c
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #include "qlcnic.h"
9 #include "qlcnic_sriov.h"
10 #include <linux/if_vlan.h>
11 #include <linux/ipv6.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14 #include <linux/aer.h>
15
16 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *);
17 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
18 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
19 struct qlcnic_cmd_args *);
20 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
21 static irqreturn_t qlcnic_83xx_handle_aen(int, void *);
22 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *,
23 pci_channel_state_t);
24 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
25 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *);
26 static void qlcnic_83xx_io_resume(struct pci_dev *);
27 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
28 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *);
29 static int qlcnic_83xx_resume(struct qlcnic_adapter *);
30 static int qlcnic_83xx_shutdown(struct pci_dev *);
31 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *);
32
33 #define RSS_HASHTYPE_IP_TCP 0x3
34 #define QLC_83XX_FW_MBX_CMD 0
35 #define QLC_SKIP_INACTIVE_PCI_REGS 7
36
37 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
38 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
39 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
40 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
41 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
42 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
43 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
44 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
45 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
46 {QLCNIC_CMD_SET_MTU, 3, 1},
47 {QLCNIC_CMD_READ_PHY, 4, 2},
48 {QLCNIC_CMD_WRITE_PHY, 5, 1},
49 {QLCNIC_CMD_READ_HW_REG, 4, 1},
50 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
51 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
52 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
53 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
54 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
55 {QLCNIC_CMD_GET_PCI_INFO, 1, 129},
56 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
57 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
58 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
59 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
60 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
61 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
62 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
63 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
64 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
65 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
66 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
67 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
68 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
69 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
70 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
71 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
72 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
73 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
74 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
75 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
76 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
77 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
78 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
79 {QLCNIC_CMD_IDC_ACK, 5, 1},
80 {QLCNIC_CMD_INIT_NIC_FUNC, 2, 1},
81 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
82 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
83 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
84 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
85 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
86 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
87 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
88 {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
89 {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
90 };
91
92 const u32 qlcnic_83xx_ext_reg_tbl[] = {
93 0x38CC, /* Global Reset */
94 0x38F0, /* Wildcard */
95 0x38FC, /* Informant */
96 0x3038, /* Host MBX ctrl */
97 0x303C, /* FW MBX ctrl */
98 0x355C, /* BOOT LOADER ADDRESS REG */
99 0x3560, /* BOOT LOADER SIZE REG */
100 0x3564, /* FW IMAGE ADDR REG */
101 0x1000, /* MBX intr enable */
102 0x1200, /* Default Intr mask */
103 0x1204, /* Default Interrupt ID */
104 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
105 0x3784, /* QLC_83XX_IDC_DEV_STATE */
106 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
107 0x378C, /* QLC_83XX_IDC_DRV_ACK */
108 0x3790, /* QLC_83XX_IDC_CTRL */
109 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
110 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
111 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
112 0x37A0, /* QLC_83XX_IDC_PF_0 */
113 0x37A4, /* QLC_83XX_IDC_PF_1 */
114 0x37A8, /* QLC_83XX_IDC_PF_2 */
115 0x37AC, /* QLC_83XX_IDC_PF_3 */
116 0x37B0, /* QLC_83XX_IDC_PF_4 */
117 0x37B4, /* QLC_83XX_IDC_PF_5 */
118 0x37B8, /* QLC_83XX_IDC_PF_6 */
119 0x37BC, /* QLC_83XX_IDC_PF_7 */
120 0x37C0, /* QLC_83XX_IDC_PF_8 */
121 0x37C4, /* QLC_83XX_IDC_PF_9 */
122 0x37C8, /* QLC_83XX_IDC_PF_10 */
123 0x37CC, /* QLC_83XX_IDC_PF_11 */
124 0x37D0, /* QLC_83XX_IDC_PF_12 */
125 0x37D4, /* QLC_83XX_IDC_PF_13 */
126 0x37D8, /* QLC_83XX_IDC_PF_14 */
127 0x37DC, /* QLC_83XX_IDC_PF_15 */
128 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
129 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
130 0x37F0, /* QLC_83XX_DRV_OP_MODE */
131 0x37F4, /* QLC_83XX_VNIC_STATE */
132 0x3868, /* QLC_83XX_DRV_LOCK */
133 0x386C, /* QLC_83XX_DRV_UNLOCK */
134 0x3504, /* QLC_83XX_DRV_LOCK_ID */
135 0x34A4, /* QLC_83XX_ASIC_TEMP */
136 };
137
138 const u32 qlcnic_83xx_reg_tbl[] = {
139 0x34A8, /* PEG_HALT_STAT1 */
140 0x34AC, /* PEG_HALT_STAT2 */
141 0x34B0, /* FW_HEARTBEAT */
142 0x3500, /* FLASH LOCK_ID */
143 0x3528, /* FW_CAPABILITIES */
144 0x3538, /* Driver active, DRV_REG0 */
145 0x3540, /* Device state, DRV_REG1 */
146 0x3544, /* Driver state, DRV_REG2 */
147 0x3548, /* Driver scratch, DRV_REG3 */
148 0x354C, /* Device partiton info, DRV_REG4 */
149 0x3524, /* Driver IDC ver, DRV_REG5 */
150 0x3550, /* FW_VER_MAJOR */
151 0x3554, /* FW_VER_MINOR */
152 0x3558, /* FW_VER_SUB */
153 0x359C, /* NPAR STATE */
154 0x35FC, /* FW_IMG_VALID */
155 0x3650, /* CMD_PEG_STATE */
156 0x373C, /* RCV_PEG_STATE */
157 0x37B4, /* ASIC TEMP */
158 0x356C, /* FW API */
159 0x3570, /* DRV OP MODE */
160 0x3850, /* FLASH LOCK */
161 0x3854, /* FLASH UNLOCK */
162 };
163
164 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
165 .read_crb = qlcnic_83xx_read_crb,
166 .write_crb = qlcnic_83xx_write_crb,
167 .read_reg = qlcnic_83xx_rd_reg_indirect,
168 .write_reg = qlcnic_83xx_wrt_reg_indirect,
169 .get_mac_address = qlcnic_83xx_get_mac_address,
170 .setup_intr = qlcnic_83xx_setup_intr,
171 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
172 .mbx_cmd = qlcnic_83xx_issue_cmd,
173 .get_func_no = qlcnic_83xx_get_func_no,
174 .api_lock = qlcnic_83xx_cam_lock,
175 .api_unlock = qlcnic_83xx_cam_unlock,
176 .add_sysfs = qlcnic_83xx_add_sysfs,
177 .remove_sysfs = qlcnic_83xx_remove_sysfs,
178 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
179 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
180 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
181 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
182 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
183 .setup_link_event = qlcnic_83xx_setup_link_event,
184 .get_nic_info = qlcnic_83xx_get_nic_info,
185 .get_pci_info = qlcnic_83xx_get_pci_info,
186 .set_nic_info = qlcnic_83xx_set_nic_info,
187 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
188 .napi_enable = qlcnic_83xx_napi_enable,
189 .napi_disable = qlcnic_83xx_napi_disable,
190 .config_intr_coal = qlcnic_83xx_config_intr_coal,
191 .config_rss = qlcnic_83xx_config_rss,
192 .config_hw_lro = qlcnic_83xx_config_hw_lro,
193 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
194 .change_l2_filter = qlcnic_83xx_change_l2_filter,
195 .get_board_info = qlcnic_83xx_get_port_info,
196 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count,
197 .free_mac_list = qlcnic_82xx_free_mac_list,
198 .io_error_detected = qlcnic_83xx_io_error_detected,
199 .io_slot_reset = qlcnic_83xx_io_slot_reset,
200 .io_resume = qlcnic_83xx_io_resume,
201 .get_beacon_state = qlcnic_83xx_get_beacon_state,
202 .enable_sds_intr = qlcnic_83xx_enable_sds_intr,
203 .disable_sds_intr = qlcnic_83xx_disable_sds_intr,
204 .enable_tx_intr = qlcnic_83xx_enable_tx_intr,
205 .disable_tx_intr = qlcnic_83xx_disable_tx_intr,
206
207 };
208
209 static struct qlcnic_nic_template qlcnic_83xx_ops = {
210 .config_bridged_mode = qlcnic_config_bridged_mode,
211 .config_led = qlcnic_config_led,
212 .request_reset = qlcnic_83xx_idc_request_reset,
213 .cancel_idc_work = qlcnic_83xx_idc_exit,
214 .napi_add = qlcnic_83xx_napi_add,
215 .napi_del = qlcnic_83xx_napi_del,
216 .config_ipaddr = qlcnic_83xx_config_ipaddr,
217 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
218 .shutdown = qlcnic_83xx_shutdown,
219 .resume = qlcnic_83xx_resume,
220 };
221
222 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
223 {
224 ahw->hw_ops = &qlcnic_83xx_hw_ops;
225 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
226 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
227 }
228
229 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
230 {
231 u32 fw_major, fw_minor, fw_build;
232 struct pci_dev *pdev = adapter->pdev;
233
234 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
235 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
236 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
237 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
238
239 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
240 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
241
242 return adapter->fw_version;
243 }
244
245 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
246 {
247 void __iomem *base;
248 u32 val;
249
250 base = adapter->ahw->pci_base0 +
251 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
252 writel(addr, base);
253 val = readl(base);
254 if (val != addr)
255 return -EIO;
256
257 return 0;
258 }
259
260 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
261 int *err)
262 {
263 struct qlcnic_hardware_context *ahw = adapter->ahw;
264
265 *err = __qlcnic_set_win_base(adapter, (u32) addr);
266 if (!*err) {
267 return QLCRDX(ahw, QLCNIC_WILDCARD);
268 } else {
269 dev_err(&adapter->pdev->dev,
270 "%s failed, addr = 0x%lx\n", __func__, addr);
271 return -EIO;
272 }
273 }
274
275 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
276 u32 data)
277 {
278 int err;
279 struct qlcnic_hardware_context *ahw = adapter->ahw;
280
281 err = __qlcnic_set_win_base(adapter, (u32) addr);
282 if (!err) {
283 QLCWRX(ahw, QLCNIC_WILDCARD, data);
284 return 0;
285 } else {
286 dev_err(&adapter->pdev->dev,
287 "%s failed, addr = 0x%x data = 0x%x\n",
288 __func__, (int)addr, data);
289 return err;
290 }
291 }
292
293 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
294 {
295 int err, i, num_msix;
296 struct qlcnic_hardware_context *ahw = adapter->ahw;
297
298 num_msix = adapter->drv_sds_rings;
299
300 /* account for AEN interrupt MSI-X based interrupts */
301 num_msix += 1;
302
303 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
304 num_msix += adapter->drv_tx_rings;
305
306 err = qlcnic_enable_msix(adapter, num_msix);
307 if (err == -ENOMEM)
308 return err;
309 if (adapter->flags & QLCNIC_MSIX_ENABLED)
310 num_msix = adapter->ahw->num_msix;
311 else {
312 if (qlcnic_sriov_vf_check(adapter))
313 return -EINVAL;
314 num_msix = 1;
315 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
316 }
317 /* setup interrupt mapping table for fw */
318 ahw->intr_tbl = vzalloc(num_msix *
319 sizeof(struct qlcnic_intrpt_config));
320 if (!ahw->intr_tbl)
321 return -ENOMEM;
322 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
323 /* MSI-X enablement failed, use legacy interrupt */
324 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
325 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
326 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
327 adapter->msix_entries[0].vector = adapter->pdev->irq;
328 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
329 }
330
331 for (i = 0; i < num_msix; i++) {
332 if (adapter->flags & QLCNIC_MSIX_ENABLED)
333 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
334 else
335 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
336 ahw->intr_tbl[i].id = i;
337 ahw->intr_tbl[i].src = 0;
338 }
339 return 0;
340 }
341
342 static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
343 {
344 writel(0, adapter->tgt_mask_reg);
345 }
346
347 static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
348 {
349 if (adapter->tgt_mask_reg)
350 writel(1, adapter->tgt_mask_reg);
351 }
352
353 static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
354 *adapter)
355 {
356 u32 mask;
357
358 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
359 * source register. We could be here before contexts are created
360 * and sds_ring->crb_intr_mask has not been initialized, calculate
361 * BAR offset for Interrupt Source Register
362 */
363 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
364 writel(0, adapter->ahw->pci_base0 + mask);
365 }
366
367 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
368 {
369 u32 mask;
370
371 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
372 writel(1, adapter->ahw->pci_base0 + mask);
373 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
374 }
375
376 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
377 struct qlcnic_cmd_args *cmd)
378 {
379 int i;
380
381 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
382 return;
383
384 for (i = 0; i < cmd->rsp.num; i++)
385 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
386 }
387
388 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
389 {
390 u32 intr_val;
391 struct qlcnic_hardware_context *ahw = adapter->ahw;
392 int retries = 0;
393
394 intr_val = readl(adapter->tgt_status_reg);
395
396 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
397 return IRQ_NONE;
398
399 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
400 adapter->stats.spurious_intr++;
401 return IRQ_NONE;
402 }
403 /* The barrier is required to ensure writes to the registers */
404 wmb();
405
406 /* clear the interrupt trigger control register */
407 writel(0, adapter->isr_int_vec);
408 intr_val = readl(adapter->isr_int_vec);
409 do {
410 intr_val = readl(adapter->tgt_status_reg);
411 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
412 break;
413 retries++;
414 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
415 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
416
417 return IRQ_HANDLED;
418 }
419
420 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
421 {
422 atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
423 complete(&mbx->completion);
424 }
425
426 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
427 {
428 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
429 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
430 unsigned long flags;
431
432 spin_lock_irqsave(&mbx->aen_lock, flags);
433 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
434 if (!(resp & QLCNIC_SET_OWNER))
435 goto out;
436
437 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
438 if (event & QLCNIC_MBX_ASYNC_EVENT) {
439 __qlcnic_83xx_process_aen(adapter);
440 } else {
441 if (atomic_read(&mbx->rsp_status) != rsp_status)
442 qlcnic_83xx_notify_mbx_response(mbx);
443 }
444 out:
445 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
446 spin_unlock_irqrestore(&mbx->aen_lock, flags);
447 }
448
449 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
450 {
451 struct qlcnic_adapter *adapter = data;
452 struct qlcnic_host_sds_ring *sds_ring;
453 struct qlcnic_hardware_context *ahw = adapter->ahw;
454
455 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
456 return IRQ_NONE;
457
458 qlcnic_83xx_poll_process_aen(adapter);
459
460 if (ahw->diag_test) {
461 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
462 ahw->diag_cnt++;
463 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
464 return IRQ_HANDLED;
465 }
466
467 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
468 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
469 } else {
470 sds_ring = &adapter->recv_ctx->sds_rings[0];
471 napi_schedule(&sds_ring->napi);
472 }
473
474 return IRQ_HANDLED;
475 }
476
477 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
478 {
479 struct qlcnic_host_sds_ring *sds_ring = data;
480 struct qlcnic_adapter *adapter = sds_ring->adapter;
481
482 if (adapter->flags & QLCNIC_MSIX_ENABLED)
483 goto done;
484
485 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
486 return IRQ_NONE;
487
488 done:
489 adapter->ahw->diag_cnt++;
490 qlcnic_enable_sds_intr(adapter, sds_ring);
491
492 return IRQ_HANDLED;
493 }
494
495 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
496 {
497 u32 num_msix;
498
499 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
500 qlcnic_83xx_set_legacy_intr_mask(adapter);
501
502 qlcnic_83xx_disable_mbx_intr(adapter);
503
504 if (adapter->flags & QLCNIC_MSIX_ENABLED)
505 num_msix = adapter->ahw->num_msix - 1;
506 else
507 num_msix = 0;
508
509 msleep(20);
510
511 if (adapter->msix_entries) {
512 synchronize_irq(adapter->msix_entries[num_msix].vector);
513 free_irq(adapter->msix_entries[num_msix].vector, adapter);
514 }
515 }
516
517 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
518 {
519 irq_handler_t handler;
520 u32 val;
521 int err = 0;
522 unsigned long flags = 0;
523
524 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
525 !(adapter->flags & QLCNIC_MSIX_ENABLED))
526 flags |= IRQF_SHARED;
527
528 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
529 handler = qlcnic_83xx_handle_aen;
530 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
531 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
532 if (err) {
533 dev_err(&adapter->pdev->dev,
534 "failed to register MBX interrupt\n");
535 return err;
536 }
537 } else {
538 handler = qlcnic_83xx_intr;
539 val = adapter->msix_entries[0].vector;
540 err = request_irq(val, handler, flags, "qlcnic", adapter);
541 if (err) {
542 dev_err(&adapter->pdev->dev,
543 "failed to register INTx interrupt\n");
544 return err;
545 }
546 qlcnic_83xx_clear_legacy_intr_mask(adapter);
547 }
548
549 /* Enable mailbox interrupt */
550 qlcnic_83xx_enable_mbx_interrupt(adapter);
551
552 return err;
553 }
554
555 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
556 {
557 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
558 adapter->ahw->pci_func = (val >> 24) & 0xff;
559 }
560
561 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
562 {
563 void __iomem *addr;
564 u32 val, limit = 0;
565
566 struct qlcnic_hardware_context *ahw = adapter->ahw;
567
568 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
569 do {
570 val = readl(addr);
571 if (val) {
572 /* write the function number to register */
573 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
574 ahw->pci_func);
575 return 0;
576 }
577 usleep_range(1000, 2000);
578 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
579
580 return -EIO;
581 }
582
583 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
584 {
585 void __iomem *addr;
586 u32 val;
587 struct qlcnic_hardware_context *ahw = adapter->ahw;
588
589 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
590 val = readl(addr);
591 }
592
593 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
594 loff_t offset, size_t size)
595 {
596 int ret = 0;
597 u32 data;
598
599 if (qlcnic_api_lock(adapter)) {
600 dev_err(&adapter->pdev->dev,
601 "%s: failed to acquire lock. addr offset 0x%x\n",
602 __func__, (u32)offset);
603 return;
604 }
605
606 data = QLCRD32(adapter, (u32) offset, &ret);
607 qlcnic_api_unlock(adapter);
608
609 if (ret == -EIO) {
610 dev_err(&adapter->pdev->dev,
611 "%s: failed. addr offset 0x%x\n",
612 __func__, (u32)offset);
613 return;
614 }
615 memcpy(buf, &data, size);
616 }
617
618 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
619 loff_t offset, size_t size)
620 {
621 u32 data;
622
623 memcpy(&data, buf, size);
624 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
625 }
626
627 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
628 {
629 int status;
630
631 status = qlcnic_83xx_get_port_config(adapter);
632 if (status) {
633 dev_err(&adapter->pdev->dev,
634 "Get Port Info failed\n");
635 } else {
636 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
637 adapter->ahw->port_type = QLCNIC_XGBE;
638 else
639 adapter->ahw->port_type = QLCNIC_GBE;
640
641 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
642 adapter->ahw->link_autoneg = AUTONEG_ENABLE;
643 }
644 return status;
645 }
646
647 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
648 {
649 struct qlcnic_hardware_context *ahw = adapter->ahw;
650 u16 act_pci_fn = ahw->total_nic_func;
651 u16 count;
652
653 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
654 if (act_pci_fn <= 2)
655 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
656 act_pci_fn;
657 else
658 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
659 act_pci_fn;
660 ahw->max_uc_count = count;
661 }
662
663 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
664 {
665 u32 val;
666
667 if (adapter->flags & QLCNIC_MSIX_ENABLED)
668 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
669 else
670 val = BIT_2;
671
672 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
673 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
674 }
675
676 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
677 const struct pci_device_id *ent)
678 {
679 u32 op_mode, priv_level;
680 struct qlcnic_hardware_context *ahw = adapter->ahw;
681
682 ahw->fw_hal_version = 2;
683 qlcnic_get_func_no(adapter);
684
685 if (qlcnic_sriov_vf_check(adapter)) {
686 qlcnic_sriov_vf_set_ops(adapter);
687 return;
688 }
689
690 /* Determine function privilege level */
691 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
692 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
693 priv_level = QLCNIC_MGMT_FUNC;
694 else
695 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
696 ahw->pci_func);
697
698 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
699 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
700 dev_info(&adapter->pdev->dev,
701 "HAL Version: %d Non Privileged function\n",
702 ahw->fw_hal_version);
703 adapter->nic_ops = &qlcnic_vf_ops;
704 } else {
705 if (pci_find_ext_capability(adapter->pdev,
706 PCI_EXT_CAP_ID_SRIOV))
707 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
708 adapter->nic_ops = &qlcnic_83xx_ops;
709 }
710 }
711
712 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
713 u32 data[]);
714 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
715 u32 data[]);
716
717 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
718 struct qlcnic_cmd_args *cmd)
719 {
720 int i;
721
722 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
723 return;
724
725 dev_info(&adapter->pdev->dev,
726 "Host MBX regs(%d)\n", cmd->req.num);
727 for (i = 0; i < cmd->req.num; i++) {
728 if (i && !(i % 8))
729 pr_info("\n");
730 pr_info("%08x ", cmd->req.arg[i]);
731 }
732 pr_info("\n");
733 dev_info(&adapter->pdev->dev,
734 "FW MBX regs(%d)\n", cmd->rsp.num);
735 for (i = 0; i < cmd->rsp.num; i++) {
736 if (i && !(i % 8))
737 pr_info("\n");
738 pr_info("%08x ", cmd->rsp.arg[i]);
739 }
740 pr_info("\n");
741 }
742
743 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
744 struct qlcnic_cmd_args *cmd)
745 {
746 struct qlcnic_hardware_context *ahw = adapter->ahw;
747 int opcode = LSW(cmd->req.arg[0]);
748 unsigned long max_loops;
749
750 max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
751
752 for (; max_loops; max_loops--) {
753 if (atomic_read(&cmd->rsp_status) ==
754 QLC_83XX_MBX_RESPONSE_ARRIVED)
755 return;
756
757 udelay(1);
758 }
759
760 dev_err(&adapter->pdev->dev,
761 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
762 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
763 flush_workqueue(ahw->mailbox->work_q);
764 return;
765 }
766
767 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
768 struct qlcnic_cmd_args *cmd)
769 {
770 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
771 struct qlcnic_hardware_context *ahw = adapter->ahw;
772 int cmd_type, err, opcode;
773 unsigned long timeout;
774
775 if (!mbx)
776 return -EIO;
777
778 opcode = LSW(cmd->req.arg[0]);
779 cmd_type = cmd->type;
780 err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
781 if (err) {
782 dev_err(&adapter->pdev->dev,
783 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
784 __func__, opcode, cmd->type, ahw->pci_func,
785 ahw->op_mode);
786 return err;
787 }
788
789 switch (cmd_type) {
790 case QLC_83XX_MBX_CMD_WAIT:
791 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
792 dev_err(&adapter->pdev->dev,
793 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
794 __func__, opcode, cmd_type, ahw->pci_func,
795 ahw->op_mode);
796 flush_workqueue(mbx->work_q);
797 }
798 break;
799 case QLC_83XX_MBX_CMD_NO_WAIT:
800 return 0;
801 case QLC_83XX_MBX_CMD_BUSY_WAIT:
802 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
803 break;
804 default:
805 dev_err(&adapter->pdev->dev,
806 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
807 __func__, opcode, cmd_type, ahw->pci_func,
808 ahw->op_mode);
809 qlcnic_83xx_detach_mailbox_work(adapter);
810 }
811
812 return cmd->rsp_opcode;
813 }
814
815 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
816 struct qlcnic_adapter *adapter, u32 type)
817 {
818 int i, size;
819 u32 temp;
820 const struct qlcnic_mailbox_metadata *mbx_tbl;
821
822 memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
823 mbx_tbl = qlcnic_83xx_mbx_tbl;
824 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
825 for (i = 0; i < size; i++) {
826 if (type == mbx_tbl[i].cmd) {
827 mbx->op_type = QLC_83XX_FW_MBX_CMD;
828 mbx->req.num = mbx_tbl[i].in_args;
829 mbx->rsp.num = mbx_tbl[i].out_args;
830 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
831 GFP_ATOMIC);
832 if (!mbx->req.arg)
833 return -ENOMEM;
834 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
835 GFP_ATOMIC);
836 if (!mbx->rsp.arg) {
837 kfree(mbx->req.arg);
838 mbx->req.arg = NULL;
839 return -ENOMEM;
840 }
841 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
842 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
843 temp = adapter->ahw->fw_hal_version << 29;
844 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
845 mbx->cmd_op = type;
846 return 0;
847 }
848 }
849 return -EINVAL;
850 }
851
852 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
853 {
854 struct qlcnic_adapter *adapter;
855 struct qlcnic_cmd_args cmd;
856 int i, err = 0;
857
858 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
859 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
860 if (err)
861 return;
862
863 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
864 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
865
866 err = qlcnic_issue_cmd(adapter, &cmd);
867 if (err)
868 dev_info(&adapter->pdev->dev,
869 "%s: Mailbox IDC ACK failed.\n", __func__);
870 qlcnic_free_mbx_args(&cmd);
871 }
872
873 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
874 u32 data[])
875 {
876 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
877 QLCNIC_MBX_RSP(data[0]));
878 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
879 return;
880 }
881
882 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
883 {
884 struct qlcnic_hardware_context *ahw = adapter->ahw;
885 u32 event[QLC_83XX_MBX_AEN_CNT];
886 int i;
887
888 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
889 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
890
891 switch (QLCNIC_MBX_RSP(event[0])) {
892
893 case QLCNIC_MBX_LINK_EVENT:
894 qlcnic_83xx_handle_link_aen(adapter, event);
895 break;
896 case QLCNIC_MBX_COMP_EVENT:
897 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
898 break;
899 case QLCNIC_MBX_REQUEST_EVENT:
900 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
901 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
902 queue_delayed_work(adapter->qlcnic_wq,
903 &adapter->idc_aen_work, 0);
904 break;
905 case QLCNIC_MBX_TIME_EXTEND_EVENT:
906 ahw->extend_lb_time = event[1] >> 8 & 0xf;
907 break;
908 case QLCNIC_MBX_BC_EVENT:
909 qlcnic_sriov_handle_bc_event(adapter, event[1]);
910 break;
911 case QLCNIC_MBX_SFP_INSERT_EVENT:
912 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
913 QLCNIC_MBX_RSP(event[0]));
914 break;
915 case QLCNIC_MBX_SFP_REMOVE_EVENT:
916 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
917 QLCNIC_MBX_RSP(event[0]));
918 break;
919 case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
920 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
921 break;
922 default:
923 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
924 QLCNIC_MBX_RSP(event[0]));
925 break;
926 }
927
928 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
929 }
930
931 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
932 {
933 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
934 struct qlcnic_hardware_context *ahw = adapter->ahw;
935 struct qlcnic_mailbox *mbx = ahw->mailbox;
936 unsigned long flags;
937
938 spin_lock_irqsave(&mbx->aen_lock, flags);
939 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
940 if (resp & QLCNIC_SET_OWNER) {
941 event = readl(QLCNIC_MBX_FW(ahw, 0));
942 if (event & QLCNIC_MBX_ASYNC_EVENT) {
943 __qlcnic_83xx_process_aen(adapter);
944 } else {
945 if (atomic_read(&mbx->rsp_status) != rsp_status)
946 qlcnic_83xx_notify_mbx_response(mbx);
947 }
948 }
949 spin_unlock_irqrestore(&mbx->aen_lock, flags);
950 }
951
952 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
953 {
954 struct qlcnic_adapter *adapter;
955
956 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
957
958 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
959 return;
960
961 qlcnic_83xx_process_aen(adapter);
962 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
963 (HZ / 10));
964 }
965
966 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
967 {
968 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
969 return;
970
971 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
972 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
973 }
974
975 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
976 {
977 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
978 return;
979 cancel_delayed_work_sync(&adapter->mbx_poll_work);
980 }
981
982 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
983 {
984 int index, i, err, sds_mbx_size;
985 u32 *buf, intrpt_id, intr_mask;
986 u16 context_id;
987 u8 num_sds;
988 struct qlcnic_cmd_args cmd;
989 struct qlcnic_host_sds_ring *sds;
990 struct qlcnic_sds_mbx sds_mbx;
991 struct qlcnic_add_rings_mbx_out *mbx_out;
992 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
993 struct qlcnic_hardware_context *ahw = adapter->ahw;
994
995 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
996 context_id = recv_ctx->context_id;
997 num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
998 ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
999 QLCNIC_CMD_ADD_RCV_RINGS);
1000 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
1001
1002 /* set up status rings, mbx 2-81 */
1003 index = 2;
1004 for (i = 8; i < adapter->drv_sds_rings; i++) {
1005 memset(&sds_mbx, 0, sds_mbx_size);
1006 sds = &recv_ctx->sds_rings[i];
1007 sds->consumer = 0;
1008 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1009 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1010 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1011 sds_mbx.sds_ring_size = sds->num_desc;
1012
1013 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1014 intrpt_id = ahw->intr_tbl[i].id;
1015 else
1016 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1017
1018 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1019 sds_mbx.intrpt_id = intrpt_id;
1020 else
1021 sds_mbx.intrpt_id = 0xffff;
1022 sds_mbx.intrpt_val = 0;
1023 buf = &cmd.req.arg[index];
1024 memcpy(buf, &sds_mbx, sds_mbx_size);
1025 index += sds_mbx_size / sizeof(u32);
1026 }
1027
1028 /* send the mailbox command */
1029 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1030 if (err) {
1031 dev_err(&adapter->pdev->dev,
1032 "Failed to add rings %d\n", err);
1033 goto out;
1034 }
1035
1036 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1037 index = 0;
1038 /* status descriptor ring */
1039 for (i = 8; i < adapter->drv_sds_rings; i++) {
1040 sds = &recv_ctx->sds_rings[i];
1041 sds->crb_sts_consumer = ahw->pci_base0 +
1042 mbx_out->host_csmr[index];
1043 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1044 intr_mask = ahw->intr_tbl[i].src;
1045 else
1046 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1047
1048 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1049 index++;
1050 }
1051 out:
1052 qlcnic_free_mbx_args(&cmd);
1053 return err;
1054 }
1055
1056 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1057 {
1058 int err;
1059 u32 temp = 0;
1060 struct qlcnic_cmd_args cmd;
1061 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1062
1063 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1064 return;
1065
1066 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1067 cmd.req.arg[0] |= (0x3 << 29);
1068
1069 if (qlcnic_sriov_pf_check(adapter))
1070 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1071
1072 cmd.req.arg[1] = recv_ctx->context_id | temp;
1073 err = qlcnic_issue_cmd(adapter, &cmd);
1074 if (err)
1075 dev_err(&adapter->pdev->dev,
1076 "Failed to destroy rx ctx in firmware\n");
1077
1078 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1079 qlcnic_free_mbx_args(&cmd);
1080 }
1081
1082 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1083 {
1084 int i, err, index, sds_mbx_size, rds_mbx_size;
1085 u8 num_sds, num_rds;
1086 u32 *buf, intrpt_id, intr_mask, cap = 0;
1087 struct qlcnic_host_sds_ring *sds;
1088 struct qlcnic_host_rds_ring *rds;
1089 struct qlcnic_sds_mbx sds_mbx;
1090 struct qlcnic_rds_mbx rds_mbx;
1091 struct qlcnic_cmd_args cmd;
1092 struct qlcnic_rcv_mbx_out *mbx_out;
1093 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1094 struct qlcnic_hardware_context *ahw = adapter->ahw;
1095 num_rds = adapter->max_rds_rings;
1096
1097 if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1098 num_sds = adapter->drv_sds_rings;
1099 else
1100 num_sds = QLCNIC_MAX_SDS_RINGS;
1101
1102 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1103 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1104 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1105
1106 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1107 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1108
1109 /* set mailbox hdr and capabilities */
1110 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1111 QLCNIC_CMD_CREATE_RX_CTX);
1112 if (err)
1113 return err;
1114
1115 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1116 cmd.req.arg[0] |= (0x3 << 29);
1117
1118 cmd.req.arg[1] = cap;
1119 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1120 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1121
1122 if (qlcnic_sriov_pf_check(adapter))
1123 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1124 &cmd.req.arg[6]);
1125 /* set up status rings, mbx 8-57/87 */
1126 index = QLC_83XX_HOST_SDS_MBX_IDX;
1127 for (i = 0; i < num_sds; i++) {
1128 memset(&sds_mbx, 0, sds_mbx_size);
1129 sds = &recv_ctx->sds_rings[i];
1130 sds->consumer = 0;
1131 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1132 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1133 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1134 sds_mbx.sds_ring_size = sds->num_desc;
1135 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1136 intrpt_id = ahw->intr_tbl[i].id;
1137 else
1138 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1139 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1140 sds_mbx.intrpt_id = intrpt_id;
1141 else
1142 sds_mbx.intrpt_id = 0xffff;
1143 sds_mbx.intrpt_val = 0;
1144 buf = &cmd.req.arg[index];
1145 memcpy(buf, &sds_mbx, sds_mbx_size);
1146 index += sds_mbx_size / sizeof(u32);
1147 }
1148 /* set up receive rings, mbx 88-111/135 */
1149 index = QLCNIC_HOST_RDS_MBX_IDX;
1150 rds = &recv_ctx->rds_rings[0];
1151 rds->producer = 0;
1152 memset(&rds_mbx, 0, rds_mbx_size);
1153 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1154 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1155 rds_mbx.reg_ring_sz = rds->dma_size;
1156 rds_mbx.reg_ring_len = rds->num_desc;
1157 /* Jumbo ring */
1158 rds = &recv_ctx->rds_rings[1];
1159 rds->producer = 0;
1160 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1161 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1162 rds_mbx.jmb_ring_sz = rds->dma_size;
1163 rds_mbx.jmb_ring_len = rds->num_desc;
1164 buf = &cmd.req.arg[index];
1165 memcpy(buf, &rds_mbx, rds_mbx_size);
1166
1167 /* send the mailbox command */
1168 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1169 if (err) {
1170 dev_err(&adapter->pdev->dev,
1171 "Failed to create Rx ctx in firmware%d\n", err);
1172 goto out;
1173 }
1174 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1175 recv_ctx->context_id = mbx_out->ctx_id;
1176 recv_ctx->state = mbx_out->state;
1177 recv_ctx->virt_port = mbx_out->vport_id;
1178 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1179 recv_ctx->context_id, recv_ctx->state);
1180 /* Receive descriptor ring */
1181 /* Standard ring */
1182 rds = &recv_ctx->rds_rings[0];
1183 rds->crb_rcv_producer = ahw->pci_base0 +
1184 mbx_out->host_prod[0].reg_buf;
1185 /* Jumbo ring */
1186 rds = &recv_ctx->rds_rings[1];
1187 rds->crb_rcv_producer = ahw->pci_base0 +
1188 mbx_out->host_prod[0].jmb_buf;
1189 /* status descriptor ring */
1190 for (i = 0; i < num_sds; i++) {
1191 sds = &recv_ctx->sds_rings[i];
1192 sds->crb_sts_consumer = ahw->pci_base0 +
1193 mbx_out->host_csmr[i];
1194 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1195 intr_mask = ahw->intr_tbl[i].src;
1196 else
1197 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1198 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1199 }
1200
1201 if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1202 err = qlcnic_83xx_add_rings(adapter);
1203 out:
1204 qlcnic_free_mbx_args(&cmd);
1205 return err;
1206 }
1207
1208 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1209 struct qlcnic_host_tx_ring *tx_ring)
1210 {
1211 struct qlcnic_cmd_args cmd;
1212 u32 temp = 0;
1213
1214 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1215 return;
1216
1217 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1218 cmd.req.arg[0] |= (0x3 << 29);
1219
1220 if (qlcnic_sriov_pf_check(adapter))
1221 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1222
1223 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1224 if (qlcnic_issue_cmd(adapter, &cmd))
1225 dev_err(&adapter->pdev->dev,
1226 "Failed to destroy tx ctx in firmware\n");
1227 qlcnic_free_mbx_args(&cmd);
1228 }
1229
1230 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1231 struct qlcnic_host_tx_ring *tx, int ring)
1232 {
1233 int err;
1234 u16 msix_id;
1235 u32 *buf, intr_mask, temp = 0;
1236 struct qlcnic_cmd_args cmd;
1237 struct qlcnic_tx_mbx mbx;
1238 struct qlcnic_tx_mbx_out *mbx_out;
1239 struct qlcnic_hardware_context *ahw = adapter->ahw;
1240 u32 msix_vector;
1241
1242 /* Reset host resources */
1243 tx->producer = 0;
1244 tx->sw_consumer = 0;
1245 *(tx->hw_consumer) = 0;
1246
1247 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1248
1249 /* setup mailbox inbox registerss */
1250 mbx.phys_addr_low = LSD(tx->phys_addr);
1251 mbx.phys_addr_high = MSD(tx->phys_addr);
1252 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1253 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1254 mbx.size = tx->num_desc;
1255 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1256 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1257 msix_vector = adapter->drv_sds_rings + ring;
1258 else
1259 msix_vector = adapter->drv_sds_rings - 1;
1260 msix_id = ahw->intr_tbl[msix_vector].id;
1261 } else {
1262 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1263 }
1264
1265 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1266 mbx.intr_id = msix_id;
1267 else
1268 mbx.intr_id = 0xffff;
1269 mbx.src = 0;
1270
1271 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1272 if (err)
1273 return err;
1274
1275 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1276 cmd.req.arg[0] |= (0x3 << 29);
1277
1278 if (qlcnic_sriov_pf_check(adapter))
1279 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1280
1281 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1282 cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1283
1284 buf = &cmd.req.arg[6];
1285 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1286 /* send the mailbox command*/
1287 err = qlcnic_issue_cmd(adapter, &cmd);
1288 if (err) {
1289 dev_err(&adapter->pdev->dev,
1290 "Failed to create Tx ctx in firmware 0x%x\n", err);
1291 goto out;
1292 }
1293 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1294 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1295 tx->ctx_id = mbx_out->ctx_id;
1296 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1297 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1298 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1299 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1300 }
1301 dev_info(&adapter->pdev->dev, "Tx Context[0x%x] Created, state:0x%x\n",
1302 tx->ctx_id, mbx_out->state);
1303 out:
1304 qlcnic_free_mbx_args(&cmd);
1305 return err;
1306 }
1307
1308 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1309 u8 num_sds_ring)
1310 {
1311 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1312 struct qlcnic_host_sds_ring *sds_ring;
1313 struct qlcnic_host_rds_ring *rds_ring;
1314 u16 adapter_state = adapter->is_up;
1315 u8 ring;
1316 int ret;
1317
1318 netif_device_detach(netdev);
1319
1320 if (netif_running(netdev))
1321 __qlcnic_down(adapter, netdev);
1322
1323 qlcnic_detach(adapter);
1324
1325 adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1326 adapter->ahw->diag_test = test;
1327 adapter->ahw->linkup = 0;
1328
1329 ret = qlcnic_attach(adapter);
1330 if (ret) {
1331 netif_device_attach(netdev);
1332 return ret;
1333 }
1334
1335 ret = qlcnic_fw_create_ctx(adapter);
1336 if (ret) {
1337 qlcnic_detach(adapter);
1338 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1339 adapter->drv_sds_rings = num_sds_ring;
1340 qlcnic_attach(adapter);
1341 }
1342 netif_device_attach(netdev);
1343 return ret;
1344 }
1345
1346 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1347 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1348 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1349 }
1350
1351 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1352 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1353 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1354 qlcnic_enable_sds_intr(adapter, sds_ring);
1355 }
1356 }
1357
1358 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1359 adapter->ahw->loopback_state = 0;
1360 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1361 }
1362
1363 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1364 return 0;
1365 }
1366
1367 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1368 u8 drv_sds_rings)
1369 {
1370 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1371 struct qlcnic_host_sds_ring *sds_ring;
1372 int ring;
1373
1374 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1375 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1376 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1377 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1378 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1379 qlcnic_disable_sds_intr(adapter, sds_ring);
1380 }
1381 }
1382
1383 qlcnic_fw_destroy_ctx(adapter);
1384 qlcnic_detach(adapter);
1385
1386 adapter->ahw->diag_test = 0;
1387 adapter->drv_sds_rings = drv_sds_rings;
1388
1389 if (qlcnic_attach(adapter))
1390 goto out;
1391
1392 if (netif_running(netdev))
1393 __qlcnic_up(adapter, netdev);
1394
1395 out:
1396 netif_device_attach(netdev);
1397 }
1398
1399 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *adapter)
1400 {
1401 struct qlcnic_hardware_context *ahw = adapter->ahw;
1402 struct qlcnic_cmd_args cmd;
1403 u8 beacon_state;
1404 int err = 0;
1405
1406 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_CONFIG);
1407 if (!err) {
1408 err = qlcnic_issue_cmd(adapter, &cmd);
1409 if (!err) {
1410 beacon_state = cmd.rsp.arg[4];
1411 if (beacon_state == QLCNIC_BEACON_DISABLE)
1412 ahw->beacon_state = QLC_83XX_BEACON_OFF;
1413 else if (beacon_state == QLC_83XX_ENABLE_BEACON)
1414 ahw->beacon_state = QLC_83XX_BEACON_ON;
1415 }
1416 } else {
1417 netdev_err(adapter->netdev, "Get beacon state failed, err=%d\n",
1418 err);
1419 }
1420
1421 qlcnic_free_mbx_args(&cmd);
1422
1423 return;
1424 }
1425
1426 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1427 u32 beacon)
1428 {
1429 struct qlcnic_cmd_args cmd;
1430 u32 mbx_in;
1431 int i, status = 0;
1432
1433 if (state) {
1434 /* Get LED configuration */
1435 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1436 QLCNIC_CMD_GET_LED_CONFIG);
1437 if (status)
1438 return status;
1439
1440 status = qlcnic_issue_cmd(adapter, &cmd);
1441 if (status) {
1442 dev_err(&adapter->pdev->dev,
1443 "Get led config failed.\n");
1444 goto mbx_err;
1445 } else {
1446 for (i = 0; i < 4; i++)
1447 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1448 }
1449 qlcnic_free_mbx_args(&cmd);
1450 /* Set LED Configuration */
1451 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1452 LSW(QLC_83XX_LED_CONFIG);
1453 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1454 QLCNIC_CMD_SET_LED_CONFIG);
1455 if (status)
1456 return status;
1457
1458 cmd.req.arg[1] = mbx_in;
1459 cmd.req.arg[2] = mbx_in;
1460 cmd.req.arg[3] = mbx_in;
1461 if (beacon)
1462 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1463 status = qlcnic_issue_cmd(adapter, &cmd);
1464 if (status) {
1465 dev_err(&adapter->pdev->dev,
1466 "Set led config failed.\n");
1467 }
1468 mbx_err:
1469 qlcnic_free_mbx_args(&cmd);
1470 return status;
1471
1472 } else {
1473 /* Restoring default LED configuration */
1474 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1475 QLCNIC_CMD_SET_LED_CONFIG);
1476 if (status)
1477 return status;
1478
1479 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1480 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1481 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1482 if (beacon)
1483 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1484 status = qlcnic_issue_cmd(adapter, &cmd);
1485 if (status)
1486 dev_err(&adapter->pdev->dev,
1487 "Restoring led config failed.\n");
1488 qlcnic_free_mbx_args(&cmd);
1489 return status;
1490 }
1491 }
1492
1493 int qlcnic_83xx_set_led(struct net_device *netdev,
1494 enum ethtool_phys_id_state state)
1495 {
1496 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1497 int err = -EIO, active = 1;
1498
1499 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1500 netdev_warn(netdev,
1501 "LED test is not supported in non-privileged mode\n");
1502 return -EOPNOTSUPP;
1503 }
1504
1505 switch (state) {
1506 case ETHTOOL_ID_ACTIVE:
1507 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1508 return -EBUSY;
1509
1510 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1511 break;
1512
1513 err = qlcnic_83xx_config_led(adapter, active, 0);
1514 if (err)
1515 netdev_err(netdev, "Failed to set LED blink state\n");
1516 break;
1517 case ETHTOOL_ID_INACTIVE:
1518 active = 0;
1519
1520 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1521 break;
1522
1523 err = qlcnic_83xx_config_led(adapter, active, 0);
1524 if (err)
1525 netdev_err(netdev, "Failed to reset LED blink state\n");
1526 break;
1527
1528 default:
1529 return -EINVAL;
1530 }
1531
1532 if (!active || err)
1533 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1534
1535 return err;
1536 }
1537
1538 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable)
1539 {
1540 struct qlcnic_cmd_args cmd;
1541 int status;
1542
1543 if (qlcnic_sriov_vf_check(adapter))
1544 return;
1545
1546 if (enable)
1547 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1548 QLCNIC_CMD_INIT_NIC_FUNC);
1549 else
1550 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1551 QLCNIC_CMD_STOP_NIC_FUNC);
1552
1553 if (status)
1554 return;
1555
1556 cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES;
1557
1558 if (adapter->dcb)
1559 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1560
1561 status = qlcnic_issue_cmd(adapter, &cmd);
1562 if (status)
1563 dev_err(&adapter->pdev->dev,
1564 "Failed to %s in NIC IDC function event.\n",
1565 (enable ? "register" : "unregister"));
1566
1567 qlcnic_free_mbx_args(&cmd);
1568 }
1569
1570 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1571 {
1572 struct qlcnic_cmd_args cmd;
1573 int err;
1574
1575 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1576 if (err)
1577 return err;
1578
1579 cmd.req.arg[1] = adapter->ahw->port_config;
1580 err = qlcnic_issue_cmd(adapter, &cmd);
1581 if (err)
1582 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1583 qlcnic_free_mbx_args(&cmd);
1584 return err;
1585 }
1586
1587 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1588 {
1589 struct qlcnic_cmd_args cmd;
1590 int err;
1591
1592 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1593 if (err)
1594 return err;
1595
1596 err = qlcnic_issue_cmd(adapter, &cmd);
1597 if (err)
1598 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1599 else
1600 adapter->ahw->port_config = cmd.rsp.arg[1];
1601 qlcnic_free_mbx_args(&cmd);
1602 return err;
1603 }
1604
1605 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1606 {
1607 int err;
1608 u32 temp;
1609 struct qlcnic_cmd_args cmd;
1610
1611 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1612 if (err)
1613 return err;
1614
1615 temp = adapter->recv_ctx->context_id << 16;
1616 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1617 err = qlcnic_issue_cmd(adapter, &cmd);
1618 if (err)
1619 dev_info(&adapter->pdev->dev,
1620 "Setup linkevent mailbox failed\n");
1621 qlcnic_free_mbx_args(&cmd);
1622 return err;
1623 }
1624
1625 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1626 u32 *interface_id)
1627 {
1628 if (qlcnic_sriov_pf_check(adapter)) {
1629 qlcnic_alloc_lb_filters_mem(adapter);
1630 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1631 adapter->rx_mac_learn = true;
1632 } else {
1633 if (!qlcnic_sriov_vf_check(adapter))
1634 *interface_id = adapter->recv_ctx->context_id << 16;
1635 }
1636 }
1637
1638 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1639 {
1640 struct qlcnic_cmd_args *cmd = NULL;
1641 u32 temp = 0;
1642 int err;
1643
1644 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1645 return -EIO;
1646
1647 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1648 if (!cmd)
1649 return -ENOMEM;
1650
1651 err = qlcnic_alloc_mbx_args(cmd, adapter,
1652 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1653 if (err)
1654 goto out;
1655
1656 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1657 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1658
1659 if (qlcnic_84xx_check(adapter) && qlcnic_sriov_pf_check(adapter))
1660 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1661
1662 cmd->req.arg[1] = mode | temp;
1663 err = qlcnic_issue_cmd(adapter, cmd);
1664 if (!err)
1665 return err;
1666
1667 qlcnic_free_mbx_args(cmd);
1668
1669 out:
1670 kfree(cmd);
1671 return err;
1672 }
1673
1674 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1675 {
1676 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1677 struct qlcnic_hardware_context *ahw = adapter->ahw;
1678 u8 drv_sds_rings = adapter->drv_sds_rings;
1679 u8 drv_tx_rings = adapter->drv_tx_rings;
1680 int ret = 0, loop = 0;
1681
1682 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1683 netdev_warn(netdev,
1684 "Loopback test not supported in non privileged mode\n");
1685 return -ENOTSUPP;
1686 }
1687
1688 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1689 netdev_info(netdev, "Device is resetting\n");
1690 return -EBUSY;
1691 }
1692
1693 if (qlcnic_get_diag_lock(adapter)) {
1694 netdev_info(netdev, "Device is in diagnostics mode\n");
1695 return -EBUSY;
1696 }
1697
1698 netdev_info(netdev, "%s loopback test in progress\n",
1699 mode == QLCNIC_ILB_MODE ? "internal" : "external");
1700
1701 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1702 drv_sds_rings);
1703 if (ret)
1704 goto fail_diag_alloc;
1705
1706 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1707 if (ret)
1708 goto free_diag_res;
1709
1710 /* Poll for link up event before running traffic */
1711 do {
1712 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1713
1714 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1715 netdev_info(netdev,
1716 "Device is resetting, free LB test resources\n");
1717 ret = -EBUSY;
1718 goto free_diag_res;
1719 }
1720 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1721 netdev_info(netdev,
1722 "Firmware didn't sent link up event to loopback request\n");
1723 ret = -ETIMEDOUT;
1724 qlcnic_83xx_clear_lb_mode(adapter, mode);
1725 goto free_diag_res;
1726 }
1727 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1728
1729 ret = qlcnic_do_lb_test(adapter, mode);
1730
1731 qlcnic_83xx_clear_lb_mode(adapter, mode);
1732
1733 free_diag_res:
1734 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1735
1736 fail_diag_alloc:
1737 adapter->drv_sds_rings = drv_sds_rings;
1738 adapter->drv_tx_rings = drv_tx_rings;
1739 qlcnic_release_diag_lock(adapter);
1740 return ret;
1741 }
1742
1743 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1744 u32 *max_wait_count)
1745 {
1746 struct qlcnic_hardware_context *ahw = adapter->ahw;
1747 int temp;
1748
1749 netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1750 ahw->extend_lb_time);
1751 temp = ahw->extend_lb_time * 1000;
1752 *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1753 ahw->extend_lb_time = 0;
1754 }
1755
1756 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1757 {
1758 struct qlcnic_hardware_context *ahw = adapter->ahw;
1759 struct net_device *netdev = adapter->netdev;
1760 u32 config, max_wait_count;
1761 int status = 0, loop = 0;
1762
1763 ahw->extend_lb_time = 0;
1764 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1765 status = qlcnic_83xx_get_port_config(adapter);
1766 if (status)
1767 return status;
1768
1769 config = ahw->port_config;
1770
1771 /* Check if port is already in loopback mode */
1772 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1773 (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1774 netdev_err(netdev,
1775 "Port already in Loopback mode.\n");
1776 return -EINPROGRESS;
1777 }
1778
1779 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1780
1781 if (mode == QLCNIC_ILB_MODE)
1782 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1783 if (mode == QLCNIC_ELB_MODE)
1784 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1785
1786 status = qlcnic_83xx_set_port_config(adapter);
1787 if (status) {
1788 netdev_err(netdev,
1789 "Failed to Set Loopback Mode = 0x%x.\n",
1790 ahw->port_config);
1791 ahw->port_config = config;
1792 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1793 return status;
1794 }
1795
1796 /* Wait for Link and IDC Completion AEN */
1797 do {
1798 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1799
1800 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1801 netdev_info(netdev,
1802 "Device is resetting, free LB test resources\n");
1803 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1804 return -EBUSY;
1805 }
1806
1807 if (ahw->extend_lb_time)
1808 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1809 &max_wait_count);
1810
1811 if (loop++ > max_wait_count) {
1812 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1813 __func__);
1814 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1815 qlcnic_83xx_clear_lb_mode(adapter, mode);
1816 return -ETIMEDOUT;
1817 }
1818 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1819
1820 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1821 QLCNIC_MAC_ADD);
1822 return status;
1823 }
1824
1825 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1826 {
1827 struct qlcnic_hardware_context *ahw = adapter->ahw;
1828 u32 config = ahw->port_config, max_wait_count;
1829 struct net_device *netdev = adapter->netdev;
1830 int status = 0, loop = 0;
1831
1832 ahw->extend_lb_time = 0;
1833 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1834 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1835 if (mode == QLCNIC_ILB_MODE)
1836 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1837 if (mode == QLCNIC_ELB_MODE)
1838 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1839
1840 status = qlcnic_83xx_set_port_config(adapter);
1841 if (status) {
1842 netdev_err(netdev,
1843 "Failed to Clear Loopback Mode = 0x%x.\n",
1844 ahw->port_config);
1845 ahw->port_config = config;
1846 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1847 return status;
1848 }
1849
1850 /* Wait for Link and IDC Completion AEN */
1851 do {
1852 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1853
1854 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1855 netdev_info(netdev,
1856 "Device is resetting, free LB test resources\n");
1857 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1858 return -EBUSY;
1859 }
1860
1861 if (ahw->extend_lb_time)
1862 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1863 &max_wait_count);
1864
1865 if (loop++ > max_wait_count) {
1866 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1867 __func__);
1868 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1869 return -ETIMEDOUT;
1870 }
1871 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1872
1873 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1874 QLCNIC_MAC_DEL);
1875 return status;
1876 }
1877
1878 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1879 u32 *interface_id)
1880 {
1881 if (qlcnic_sriov_pf_check(adapter)) {
1882 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1883 } else {
1884 if (!qlcnic_sriov_vf_check(adapter))
1885 *interface_id = adapter->recv_ctx->context_id << 16;
1886 }
1887 }
1888
1889 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1890 int mode)
1891 {
1892 int err;
1893 u32 temp = 0, temp_ip;
1894 struct qlcnic_cmd_args cmd;
1895
1896 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1897 QLCNIC_CMD_CONFIGURE_IP_ADDR);
1898 if (err)
1899 return;
1900
1901 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1902
1903 if (mode == QLCNIC_IP_UP)
1904 cmd.req.arg[1] = 1 | temp;
1905 else
1906 cmd.req.arg[1] = 2 | temp;
1907
1908 /*
1909 * Adapter needs IP address in network byte order.
1910 * But hardware mailbox registers go through writel(), hence IP address
1911 * gets swapped on big endian architecture.
1912 * To negate swapping of writel() on big endian architecture
1913 * use swab32(value).
1914 */
1915
1916 temp_ip = swab32(ntohl(ip));
1917 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1918 err = qlcnic_issue_cmd(adapter, &cmd);
1919 if (err != QLCNIC_RCODE_SUCCESS)
1920 dev_err(&adapter->netdev->dev,
1921 "could not notify %s IP 0x%x request\n",
1922 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1923
1924 qlcnic_free_mbx_args(&cmd);
1925 }
1926
1927 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1928 {
1929 int err;
1930 u32 temp, arg1;
1931 struct qlcnic_cmd_args cmd;
1932 int lro_bit_mask;
1933
1934 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1935
1936 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1937 return 0;
1938
1939 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1940 if (err)
1941 return err;
1942
1943 temp = adapter->recv_ctx->context_id << 16;
1944 arg1 = lro_bit_mask | temp;
1945 cmd.req.arg[1] = arg1;
1946
1947 err = qlcnic_issue_cmd(adapter, &cmd);
1948 if (err)
1949 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1950 qlcnic_free_mbx_args(&cmd);
1951
1952 return err;
1953 }
1954
1955 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
1956 {
1957 int err;
1958 u32 word;
1959 struct qlcnic_cmd_args cmd;
1960 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
1961 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
1962 0x255b0ec26d5a56daULL };
1963
1964 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
1965 if (err)
1966 return err;
1967 /*
1968 * RSS request:
1969 * bits 3-0: Rsvd
1970 * 5-4: hash_type_ipv4
1971 * 7-6: hash_type_ipv6
1972 * 8: enable
1973 * 9: use indirection table
1974 * 16-31: indirection table mask
1975 */
1976 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
1977 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
1978 ((u32)(enable & 0x1) << 8) |
1979 ((0x7ULL) << 16);
1980 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
1981 cmd.req.arg[2] = word;
1982 memcpy(&cmd.req.arg[4], key, sizeof(key));
1983
1984 err = qlcnic_issue_cmd(adapter, &cmd);
1985
1986 if (err)
1987 dev_info(&adapter->pdev->dev, "RSS config failed\n");
1988 qlcnic_free_mbx_args(&cmd);
1989
1990 return err;
1991
1992 }
1993
1994 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
1995 u32 *interface_id)
1996 {
1997 if (qlcnic_sriov_pf_check(adapter)) {
1998 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
1999 } else {
2000 if (!qlcnic_sriov_vf_check(adapter))
2001 *interface_id = adapter->recv_ctx->context_id << 16;
2002 }
2003 }
2004
2005 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
2006 u16 vlan_id, u8 op)
2007 {
2008 struct qlcnic_cmd_args *cmd = NULL;
2009 struct qlcnic_macvlan_mbx mv;
2010 u32 *buf, temp = 0;
2011 int err;
2012
2013 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2014 return -EIO;
2015
2016 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
2017 if (!cmd)
2018 return -ENOMEM;
2019
2020 err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
2021 if (err)
2022 goto out;
2023
2024 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
2025
2026 if (vlan_id)
2027 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2028 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2029
2030 cmd->req.arg[1] = op | (1 << 8);
2031 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
2032 cmd->req.arg[1] |= temp;
2033 mv.vlan = vlan_id;
2034 mv.mac_addr0 = addr[0];
2035 mv.mac_addr1 = addr[1];
2036 mv.mac_addr2 = addr[2];
2037 mv.mac_addr3 = addr[3];
2038 mv.mac_addr4 = addr[4];
2039 mv.mac_addr5 = addr[5];
2040 buf = &cmd->req.arg[2];
2041 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2042 err = qlcnic_issue_cmd(adapter, cmd);
2043 if (!err)
2044 return err;
2045
2046 qlcnic_free_mbx_args(cmd);
2047 out:
2048 kfree(cmd);
2049 return err;
2050 }
2051
2052 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2053 u16 vlan_id)
2054 {
2055 u8 mac[ETH_ALEN];
2056 memcpy(&mac, addr, ETH_ALEN);
2057 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2058 }
2059
2060 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2061 u8 type, struct qlcnic_cmd_args *cmd)
2062 {
2063 switch (type) {
2064 case QLCNIC_SET_STATION_MAC:
2065 case QLCNIC_SET_FAC_DEF_MAC:
2066 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2067 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2068 break;
2069 }
2070 cmd->req.arg[1] = type;
2071 }
2072
2073 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2074 u8 function)
2075 {
2076 int err, i;
2077 struct qlcnic_cmd_args cmd;
2078 u32 mac_low, mac_high;
2079
2080 function = 0;
2081 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2082 if (err)
2083 return err;
2084
2085 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2086 err = qlcnic_issue_cmd(adapter, &cmd);
2087
2088 if (err == QLCNIC_RCODE_SUCCESS) {
2089 mac_low = cmd.rsp.arg[1];
2090 mac_high = cmd.rsp.arg[2];
2091
2092 for (i = 0; i < 2; i++)
2093 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2094 for (i = 2; i < 6; i++)
2095 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2096 } else {
2097 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2098 err);
2099 err = -EIO;
2100 }
2101 qlcnic_free_mbx_args(&cmd);
2102 return err;
2103 }
2104
2105 void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter)
2106 {
2107 int err;
2108 u16 temp;
2109 struct qlcnic_cmd_args cmd;
2110 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2111
2112 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2113 return;
2114
2115 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2116 if (err)
2117 return;
2118
2119 if (coal->type == QLCNIC_INTR_COAL_TYPE_RX) {
2120 temp = adapter->recv_ctx->context_id;
2121 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2122 temp = coal->rx_time_us;
2123 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2124 } else if (coal->type == QLCNIC_INTR_COAL_TYPE_TX) {
2125 temp = adapter->tx_ring->ctx_id;
2126 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2127 temp = coal->tx_time_us;
2128 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2129 }
2130 cmd.req.arg[3] = coal->flag;
2131 err = qlcnic_issue_cmd(adapter, &cmd);
2132 if (err != QLCNIC_RCODE_SUCCESS)
2133 dev_info(&adapter->pdev->dev,
2134 "Failed to send interrupt coalescence parameters\n");
2135 qlcnic_free_mbx_args(&cmd);
2136 }
2137
2138 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2139 u32 data[])
2140 {
2141 struct qlcnic_hardware_context *ahw = adapter->ahw;
2142 u8 link_status, duplex;
2143 /* link speed */
2144 link_status = LSB(data[3]) & 1;
2145 if (link_status) {
2146 ahw->link_speed = MSW(data[2]);
2147 duplex = LSB(MSW(data[3]));
2148 if (duplex)
2149 ahw->link_duplex = DUPLEX_FULL;
2150 else
2151 ahw->link_duplex = DUPLEX_HALF;
2152 } else {
2153 ahw->link_speed = SPEED_UNKNOWN;
2154 ahw->link_duplex = DUPLEX_UNKNOWN;
2155 }
2156
2157 ahw->link_autoneg = MSB(MSW(data[3]));
2158 ahw->module_type = MSB(LSW(data[3]));
2159 ahw->has_link_events = 1;
2160 ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK;
2161 qlcnic_advert_link_change(adapter, link_status);
2162 }
2163
2164 static irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2165 {
2166 struct qlcnic_adapter *adapter = data;
2167 struct qlcnic_mailbox *mbx;
2168 u32 mask, resp, event;
2169 unsigned long flags;
2170
2171 mbx = adapter->ahw->mailbox;
2172 spin_lock_irqsave(&mbx->aen_lock, flags);
2173 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2174 if (!(resp & QLCNIC_SET_OWNER))
2175 goto out;
2176
2177 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2178 if (event & QLCNIC_MBX_ASYNC_EVENT)
2179 __qlcnic_83xx_process_aen(adapter);
2180 else
2181 qlcnic_83xx_notify_mbx_response(mbx);
2182
2183 out:
2184 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2185 writel(0, adapter->ahw->pci_base0 + mask);
2186 spin_unlock_irqrestore(&mbx->aen_lock, flags);
2187 return IRQ_HANDLED;
2188 }
2189
2190 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2191 struct qlcnic_info *nic)
2192 {
2193 int i, err = -EIO;
2194 struct qlcnic_cmd_args cmd;
2195
2196 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2197 dev_err(&adapter->pdev->dev,
2198 "%s: Error, invoked by non management func\n",
2199 __func__);
2200 return err;
2201 }
2202
2203 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2204 if (err)
2205 return err;
2206
2207 cmd.req.arg[1] = (nic->pci_func << 16);
2208 cmd.req.arg[2] = 0x1 << 16;
2209 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2210 cmd.req.arg[4] = nic->capabilities;
2211 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2212 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2213 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2214 for (i = 8; i < 32; i++)
2215 cmd.req.arg[i] = 0;
2216
2217 err = qlcnic_issue_cmd(adapter, &cmd);
2218
2219 if (err != QLCNIC_RCODE_SUCCESS) {
2220 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2221 err);
2222 err = -EIO;
2223 }
2224
2225 qlcnic_free_mbx_args(&cmd);
2226
2227 return err;
2228 }
2229
2230 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2231 struct qlcnic_info *npar_info, u8 func_id)
2232 {
2233 int err;
2234 u32 temp;
2235 u8 op = 0;
2236 struct qlcnic_cmd_args cmd;
2237 struct qlcnic_hardware_context *ahw = adapter->ahw;
2238
2239 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2240 if (err)
2241 return err;
2242
2243 if (func_id != ahw->pci_func) {
2244 temp = func_id << 16;
2245 cmd.req.arg[1] = op | BIT_31 | temp;
2246 } else {
2247 cmd.req.arg[1] = ahw->pci_func << 16;
2248 }
2249 err = qlcnic_issue_cmd(adapter, &cmd);
2250 if (err) {
2251 dev_info(&adapter->pdev->dev,
2252 "Failed to get nic info %d\n", err);
2253 goto out;
2254 }
2255
2256 npar_info->op_type = cmd.rsp.arg[1];
2257 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2258 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2259 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2260 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2261 npar_info->capabilities = cmd.rsp.arg[4];
2262 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2263 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2264 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2265 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2266 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2267 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2268 if (cmd.rsp.arg[8] & 0x1)
2269 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2270 if (cmd.rsp.arg[8] & 0x10000) {
2271 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2272 npar_info->max_linkspeed_reg_offset = temp;
2273 }
2274
2275 memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2276 sizeof(ahw->extra_capability));
2277
2278 out:
2279 qlcnic_free_mbx_args(&cmd);
2280 return err;
2281 }
2282
2283 int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type,
2284 u16 *nic, u16 *fcoe, u16 *iscsi)
2285 {
2286 struct device *dev = &adapter->pdev->dev;
2287 int err = 0;
2288
2289 switch (type) {
2290 case QLCNIC_TYPE_NIC:
2291 (*nic)++;
2292 break;
2293 case QLCNIC_TYPE_FCOE:
2294 (*fcoe)++;
2295 break;
2296 case QLCNIC_TYPE_ISCSI:
2297 (*iscsi)++;
2298 break;
2299 default:
2300 dev_err(dev, "%s: Unknown PCI type[%x]\n",
2301 __func__, type);
2302 err = -EIO;
2303 }
2304
2305 return err;
2306 }
2307
2308 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2309 struct qlcnic_pci_info *pci_info)
2310 {
2311 struct qlcnic_hardware_context *ahw = adapter->ahw;
2312 struct device *dev = &adapter->pdev->dev;
2313 u16 nic = 0, fcoe = 0, iscsi = 0;
2314 struct qlcnic_cmd_args cmd;
2315 int i, err = 0, j = 0;
2316 u32 temp;
2317
2318 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2319 if (err)
2320 return err;
2321
2322 err = qlcnic_issue_cmd(adapter, &cmd);
2323
2324 ahw->total_nic_func = 0;
2325 if (err == QLCNIC_RCODE_SUCCESS) {
2326 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2327 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) {
2328 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2329 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2330 i++;
2331 if (!pci_info->active) {
2332 i += QLC_SKIP_INACTIVE_PCI_REGS;
2333 continue;
2334 }
2335 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2336 err = qlcnic_get_pci_func_type(adapter, pci_info->type,
2337 &nic, &fcoe, &iscsi);
2338 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2339 pci_info->default_port = temp;
2340 i++;
2341 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2342 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2343 pci_info->tx_max_bw = temp;
2344 i = i + 2;
2345 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2346 i++;
2347 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2348 i = i + 3;
2349 }
2350 } else {
2351 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2352 err = -EIO;
2353 }
2354
2355 ahw->total_nic_func = nic;
2356 ahw->total_pci_func = nic + fcoe + iscsi;
2357 if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
2358 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
2359 __func__, ahw->total_nic_func, ahw->total_pci_func);
2360 err = -EIO;
2361 }
2362 qlcnic_free_mbx_args(&cmd);
2363
2364 return err;
2365 }
2366
2367 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2368 {
2369 int i, index, err;
2370 u8 max_ints;
2371 u32 val, temp, type;
2372 struct qlcnic_cmd_args cmd;
2373
2374 max_ints = adapter->ahw->num_msix - 1;
2375 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2376 if (err)
2377 return err;
2378
2379 cmd.req.arg[1] = max_ints;
2380
2381 if (qlcnic_sriov_vf_check(adapter))
2382 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2383
2384 for (i = 0, index = 2; i < max_ints; i++) {
2385 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2386 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2387 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2388 val |= (adapter->ahw->intr_tbl[i].id << 16);
2389 cmd.req.arg[index++] = val;
2390 }
2391 err = qlcnic_issue_cmd(adapter, &cmd);
2392 if (err) {
2393 dev_err(&adapter->pdev->dev,
2394 "Failed to configure interrupts 0x%x\n", err);
2395 goto out;
2396 }
2397
2398 max_ints = cmd.rsp.arg[1];
2399 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2400 val = cmd.rsp.arg[index];
2401 if (LSB(val)) {
2402 dev_info(&adapter->pdev->dev,
2403 "Can't configure interrupt %d\n",
2404 adapter->ahw->intr_tbl[i].id);
2405 continue;
2406 }
2407 if (op_type) {
2408 adapter->ahw->intr_tbl[i].id = MSW(val);
2409 adapter->ahw->intr_tbl[i].enabled = 1;
2410 temp = cmd.rsp.arg[index + 1];
2411 adapter->ahw->intr_tbl[i].src = temp;
2412 } else {
2413 adapter->ahw->intr_tbl[i].id = i;
2414 adapter->ahw->intr_tbl[i].enabled = 0;
2415 adapter->ahw->intr_tbl[i].src = 0;
2416 }
2417 }
2418 out:
2419 qlcnic_free_mbx_args(&cmd);
2420 return err;
2421 }
2422
2423 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2424 {
2425 int id, timeout = 0;
2426 u32 status = 0;
2427
2428 while (status == 0) {
2429 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2430 if (status)
2431 break;
2432
2433 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2434 id = QLC_SHARED_REG_RD32(adapter,
2435 QLCNIC_FLASH_LOCK_OWNER);
2436 dev_err(&adapter->pdev->dev,
2437 "%s: failed, lock held by %d\n", __func__, id);
2438 return -EIO;
2439 }
2440 usleep_range(1000, 2000);
2441 }
2442
2443 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2444 return 0;
2445 }
2446
2447 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2448 {
2449 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2450 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2451 }
2452
2453 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2454 u32 flash_addr, u8 *p_data,
2455 int count)
2456 {
2457 u32 word, range, flash_offset, addr = flash_addr, ret;
2458 ulong indirect_add, direct_window;
2459 int i, err = 0;
2460
2461 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2462 if (addr & 0x3) {
2463 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2464 return -EIO;
2465 }
2466
2467 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2468 (addr));
2469
2470 range = flash_offset + (count * sizeof(u32));
2471 /* Check if data is spread across multiple sectors */
2472 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2473
2474 /* Multi sector read */
2475 for (i = 0; i < count; i++) {
2476 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2477 ret = QLCRD32(adapter, indirect_add, &err);
2478 if (err == -EIO)
2479 return err;
2480
2481 word = ret;
2482 *(u32 *)p_data = word;
2483 p_data = p_data + 4;
2484 addr = addr + 4;
2485 flash_offset = flash_offset + 4;
2486
2487 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2488 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2489 /* This write is needed once for each sector */
2490 qlcnic_83xx_wrt_reg_indirect(adapter,
2491 direct_window,
2492 (addr));
2493 flash_offset = 0;
2494 }
2495 }
2496 } else {
2497 /* Single sector read */
2498 for (i = 0; i < count; i++) {
2499 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2500 ret = QLCRD32(adapter, indirect_add, &err);
2501 if (err == -EIO)
2502 return err;
2503
2504 word = ret;
2505 *(u32 *)p_data = word;
2506 p_data = p_data + 4;
2507 addr = addr + 4;
2508 }
2509 }
2510
2511 return 0;
2512 }
2513
2514 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2515 {
2516 u32 status;
2517 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2518 int err = 0;
2519
2520 do {
2521 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2522 if (err == -EIO)
2523 return err;
2524
2525 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2526 QLC_83XX_FLASH_STATUS_READY)
2527 break;
2528
2529 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2530 } while (--retries);
2531
2532 if (!retries)
2533 return -EIO;
2534
2535 return 0;
2536 }
2537
2538 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2539 {
2540 int ret;
2541 u32 cmd;
2542 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2543 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2544 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2545 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2546 adapter->ahw->fdt.write_enable_bits);
2547 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2548 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2549 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2550 if (ret)
2551 return -EIO;
2552
2553 return 0;
2554 }
2555
2556 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2557 {
2558 int ret;
2559
2560 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2561 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2562 adapter->ahw->fdt.write_statusreg_cmd));
2563 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2564 adapter->ahw->fdt.write_disable_bits);
2565 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2566 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2567 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2568 if (ret)
2569 return -EIO;
2570
2571 return 0;
2572 }
2573
2574 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2575 {
2576 int ret, err = 0;
2577 u32 mfg_id;
2578
2579 if (qlcnic_83xx_lock_flash(adapter))
2580 return -EIO;
2581
2582 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2583 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2584 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2585 QLC_83XX_FLASH_READ_CTRL);
2586 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2587 if (ret) {
2588 qlcnic_83xx_unlock_flash(adapter);
2589 return -EIO;
2590 }
2591
2592 mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2593 if (err == -EIO) {
2594 qlcnic_83xx_unlock_flash(adapter);
2595 return err;
2596 }
2597
2598 adapter->flash_mfg_id = (mfg_id & 0xFF);
2599 qlcnic_83xx_unlock_flash(adapter);
2600
2601 return 0;
2602 }
2603
2604 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2605 {
2606 int count, fdt_size, ret = 0;
2607
2608 fdt_size = sizeof(struct qlcnic_fdt);
2609 count = fdt_size / sizeof(u32);
2610
2611 if (qlcnic_83xx_lock_flash(adapter))
2612 return -EIO;
2613
2614 memset(&adapter->ahw->fdt, 0, fdt_size);
2615 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2616 (u8 *)&adapter->ahw->fdt,
2617 count);
2618
2619 qlcnic_83xx_unlock_flash(adapter);
2620 return ret;
2621 }
2622
2623 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2624 u32 sector_start_addr)
2625 {
2626 u32 reversed_addr, addr1, addr2, cmd;
2627 int ret = -EIO;
2628
2629 if (qlcnic_83xx_lock_flash(adapter) != 0)
2630 return -EIO;
2631
2632 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2633 ret = qlcnic_83xx_enable_flash_write(adapter);
2634 if (ret) {
2635 qlcnic_83xx_unlock_flash(adapter);
2636 dev_err(&adapter->pdev->dev,
2637 "%s failed at %d\n",
2638 __func__, __LINE__);
2639 return ret;
2640 }
2641 }
2642
2643 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2644 if (ret) {
2645 qlcnic_83xx_unlock_flash(adapter);
2646 dev_err(&adapter->pdev->dev,
2647 "%s: failed at %d\n", __func__, __LINE__);
2648 return -EIO;
2649 }
2650
2651 addr1 = (sector_start_addr & 0xFF) << 16;
2652 addr2 = (sector_start_addr & 0xFF0000) >> 16;
2653 reversed_addr = addr1 | addr2;
2654
2655 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2656 reversed_addr);
2657 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2658 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2659 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2660 else
2661 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2662 QLC_83XX_FLASH_OEM_ERASE_SIG);
2663 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2664 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2665
2666 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2667 if (ret) {
2668 qlcnic_83xx_unlock_flash(adapter);
2669 dev_err(&adapter->pdev->dev,
2670 "%s: failed at %d\n", __func__, __LINE__);
2671 return -EIO;
2672 }
2673
2674 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2675 ret = qlcnic_83xx_disable_flash_write(adapter);
2676 if (ret) {
2677 qlcnic_83xx_unlock_flash(adapter);
2678 dev_err(&adapter->pdev->dev,
2679 "%s: failed at %d\n", __func__, __LINE__);
2680 return ret;
2681 }
2682 }
2683
2684 qlcnic_83xx_unlock_flash(adapter);
2685
2686 return 0;
2687 }
2688
2689 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2690 u32 *p_data)
2691 {
2692 int ret = -EIO;
2693 u32 addr1 = 0x00800000 | (addr >> 2);
2694
2695 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2696 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2697 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2698 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2699 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2700 if (ret) {
2701 dev_err(&adapter->pdev->dev,
2702 "%s: failed at %d\n", __func__, __LINE__);
2703 return -EIO;
2704 }
2705
2706 return 0;
2707 }
2708
2709 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2710 u32 *p_data, int count)
2711 {
2712 u32 temp;
2713 int ret = -EIO, err = 0;
2714
2715 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2716 (count > QLC_83XX_FLASH_WRITE_MAX)) {
2717 dev_err(&adapter->pdev->dev,
2718 "%s: Invalid word count\n", __func__);
2719 return -EIO;
2720 }
2721
2722 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2723 if (err == -EIO)
2724 return err;
2725
2726 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2727 (temp | QLC_83XX_FLASH_SPI_CTRL));
2728 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2729 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2730
2731 /* First DWORD write */
2732 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2733 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2734 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2735 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2736 if (ret) {
2737 dev_err(&adapter->pdev->dev,
2738 "%s: failed at %d\n", __func__, __LINE__);
2739 return -EIO;
2740 }
2741
2742 count--;
2743 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2744 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2745 /* Second to N-1 DWORD writes */
2746 while (count != 1) {
2747 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2748 *p_data++);
2749 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2750 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2751 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2752 if (ret) {
2753 dev_err(&adapter->pdev->dev,
2754 "%s: failed at %d\n", __func__, __LINE__);
2755 return -EIO;
2756 }
2757 count--;
2758 }
2759
2760 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2761 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2762 (addr >> 2));
2763 /* Last DWORD write */
2764 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2765 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2766 QLC_83XX_FLASH_LAST_MS_PATTERN);
2767 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2768 if (ret) {
2769 dev_err(&adapter->pdev->dev,
2770 "%s: failed at %d\n", __func__, __LINE__);
2771 return -EIO;
2772 }
2773
2774 ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2775 if (err == -EIO)
2776 return err;
2777
2778 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2779 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2780 __func__, __LINE__);
2781 /* Operation failed, clear error bit */
2782 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2783 if (err == -EIO)
2784 return err;
2785
2786 qlcnic_83xx_wrt_reg_indirect(adapter,
2787 QLC_83XX_FLASH_SPI_CONTROL,
2788 (temp | QLC_83XX_FLASH_SPI_CTRL));
2789 }
2790
2791 return 0;
2792 }
2793
2794 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2795 {
2796 u32 val, id;
2797
2798 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2799
2800 /* Check if recovery need to be performed by the calling function */
2801 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2802 val = val & ~0x3F;
2803 val = val | ((adapter->portnum << 2) |
2804 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2805 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2806 dev_info(&adapter->pdev->dev,
2807 "%s: lock recovery initiated\n", __func__);
2808 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2809 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2810 id = ((val >> 2) & 0xF);
2811 if (id == adapter->portnum) {
2812 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2813 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2814 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2815 /* Force release the lock */
2816 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2817 /* Clear recovery bits */
2818 val = val & ~0x3F;
2819 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2820 dev_info(&adapter->pdev->dev,
2821 "%s: lock recovery completed\n", __func__);
2822 } else {
2823 dev_info(&adapter->pdev->dev,
2824 "%s: func %d to resume lock recovery process\n",
2825 __func__, id);
2826 }
2827 } else {
2828 dev_info(&adapter->pdev->dev,
2829 "%s: lock recovery initiated by other functions\n",
2830 __func__);
2831 }
2832 }
2833
2834 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2835 {
2836 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2837 int max_attempt = 0;
2838
2839 while (status == 0) {
2840 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2841 if (status)
2842 break;
2843
2844 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2845 i++;
2846
2847 if (i == 1)
2848 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2849
2850 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2851 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2852 if (val == temp) {
2853 id = val & 0xFF;
2854 dev_info(&adapter->pdev->dev,
2855 "%s: lock to be recovered from %d\n",
2856 __func__, id);
2857 qlcnic_83xx_recover_driver_lock(adapter);
2858 i = 0;
2859 max_attempt++;
2860 } else {
2861 dev_err(&adapter->pdev->dev,
2862 "%s: failed to get lock\n", __func__);
2863 return -EIO;
2864 }
2865 }
2866
2867 /* Force exit from while loop after few attempts */
2868 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
2869 dev_err(&adapter->pdev->dev,
2870 "%s: failed to get lock\n", __func__);
2871 return -EIO;
2872 }
2873 }
2874
2875 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2876 lock_alive_counter = val >> 8;
2877 lock_alive_counter++;
2878 val = lock_alive_counter << 8 | adapter->portnum;
2879 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2880
2881 return 0;
2882 }
2883
2884 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
2885 {
2886 u32 val, lock_alive_counter, id;
2887
2888 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2889 id = val & 0xFF;
2890 lock_alive_counter = val >> 8;
2891
2892 if (id != adapter->portnum)
2893 dev_err(&adapter->pdev->dev,
2894 "%s:Warning func %d is unlocking lock owned by %d\n",
2895 __func__, adapter->portnum, id);
2896
2897 val = (lock_alive_counter << 8) | 0xFF;
2898 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
2899 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2900 }
2901
2902 int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
2903 u32 *data, u32 count)
2904 {
2905 int i, j, ret = 0;
2906 u32 temp;
2907 int err = 0;
2908
2909 /* Check alignment */
2910 if (addr & 0xF)
2911 return -EIO;
2912
2913 mutex_lock(&adapter->ahw->mem_lock);
2914 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_HI, 0);
2915
2916 for (i = 0; i < count; i++, addr += 16) {
2917 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
2918 QLCNIC_ADDR_QDR_NET_MAX)) ||
2919 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
2920 QLCNIC_ADDR_DDR_NET_MAX)))) {
2921 mutex_unlock(&adapter->ahw->mem_lock);
2922 return -EIO;
2923 }
2924
2925 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_ADDR_LO, addr);
2926 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_LO,
2927 *data++);
2928 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_HI,
2929 *data++);
2930 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_ULO,
2931 *data++);
2932 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_WRTDATA_UHI,
2933 *data++);
2934 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2935 QLCNIC_TA_WRITE_ENABLE);
2936 qlcnic_83xx_wrt_reg_indirect(adapter, QLCNIC_MS_CTRL,
2937 QLCNIC_TA_WRITE_START);
2938
2939 for (j = 0; j < MAX_CTL_CHECK; j++) {
2940 temp = QLCRD32(adapter, QLCNIC_MS_CTRL, &err);
2941 if (err == -EIO) {
2942 mutex_unlock(&adapter->ahw->mem_lock);
2943 return err;
2944 }
2945
2946 if ((temp & TA_CTL_BUSY) == 0)
2947 break;
2948 }
2949
2950 /* Status check failure */
2951 if (j >= MAX_CTL_CHECK) {
2952 printk_ratelimited(KERN_WARNING
2953 "MS memory write failed\n");
2954 mutex_unlock(&adapter->ahw->mem_lock);
2955 return -EIO;
2956 }
2957 }
2958
2959 mutex_unlock(&adapter->ahw->mem_lock);
2960
2961 return ret;
2962 }
2963
2964 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
2965 u8 *p_data, int count)
2966 {
2967 u32 word, addr = flash_addr, ret;
2968 ulong indirect_addr;
2969 int i, err = 0;
2970
2971 if (qlcnic_83xx_lock_flash(adapter) != 0)
2972 return -EIO;
2973
2974 if (addr & 0x3) {
2975 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2976 qlcnic_83xx_unlock_flash(adapter);
2977 return -EIO;
2978 }
2979
2980 for (i = 0; i < count; i++) {
2981 if (qlcnic_83xx_wrt_reg_indirect(adapter,
2982 QLC_83XX_FLASH_DIRECT_WINDOW,
2983 (addr))) {
2984 qlcnic_83xx_unlock_flash(adapter);
2985 return -EIO;
2986 }
2987
2988 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
2989 ret = QLCRD32(adapter, indirect_addr, &err);
2990 if (err == -EIO)
2991 return err;
2992
2993 word = ret;
2994 *(u32 *)p_data = word;
2995 p_data = p_data + 4;
2996 addr = addr + 4;
2997 }
2998
2999 qlcnic_83xx_unlock_flash(adapter);
3000
3001 return 0;
3002 }
3003
3004 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
3005 {
3006 u8 pci_func;
3007 int err;
3008 u32 config = 0, state;
3009 struct qlcnic_cmd_args cmd;
3010 struct qlcnic_hardware_context *ahw = adapter->ahw;
3011
3012 if (qlcnic_sriov_vf_check(adapter))
3013 pci_func = adapter->portnum;
3014 else
3015 pci_func = ahw->pci_func;
3016
3017 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
3018 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
3019 dev_info(&adapter->pdev->dev, "link state down\n");
3020 return config;
3021 }
3022
3023 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3024 if (err)
3025 return err;
3026
3027 err = qlcnic_issue_cmd(adapter, &cmd);
3028 if (err) {
3029 dev_info(&adapter->pdev->dev,
3030 "Get Link Status Command failed: 0x%x\n", err);
3031 goto out;
3032 } else {
3033 config = cmd.rsp.arg[1];
3034 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3035 case QLC_83XX_10M_LINK:
3036 ahw->link_speed = SPEED_10;
3037 break;
3038 case QLC_83XX_100M_LINK:
3039 ahw->link_speed = SPEED_100;
3040 break;
3041 case QLC_83XX_1G_LINK:
3042 ahw->link_speed = SPEED_1000;
3043 break;
3044 case QLC_83XX_10G_LINK:
3045 ahw->link_speed = SPEED_10000;
3046 break;
3047 default:
3048 ahw->link_speed = 0;
3049 break;
3050 }
3051 config = cmd.rsp.arg[3];
3052 if (QLC_83XX_SFP_PRESENT(config)) {
3053 switch (ahw->module_type) {
3054 case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
3055 case LINKEVENT_MODULE_OPTICAL_SRLR:
3056 case LINKEVENT_MODULE_OPTICAL_LRM:
3057 case LINKEVENT_MODULE_OPTICAL_SFP_1G:
3058 ahw->supported_type = PORT_FIBRE;
3059 break;
3060 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
3061 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
3062 case LINKEVENT_MODULE_TWINAX:
3063 ahw->supported_type = PORT_TP;
3064 break;
3065 default:
3066 ahw->supported_type = PORT_OTHER;
3067 }
3068 }
3069 if (config & 1)
3070 err = 1;
3071 }
3072 out:
3073 qlcnic_free_mbx_args(&cmd);
3074 return config;
3075 }
3076
3077 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3078 struct ethtool_cmd *ecmd)
3079 {
3080 u32 config = 0;
3081 int status = 0;
3082 struct qlcnic_hardware_context *ahw = adapter->ahw;
3083
3084 if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3085 /* Get port configuration info */
3086 status = qlcnic_83xx_get_port_info(adapter);
3087 /* Get Link Status related info */
3088 config = qlcnic_83xx_test_link(adapter);
3089 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3090 }
3091
3092 /* hard code until there is a way to get it from flash */
3093 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3094
3095 if (netif_running(adapter->netdev) && ahw->has_link_events) {
3096 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3097 ecmd->duplex = ahw->link_duplex;
3098 ecmd->autoneg = ahw->link_autoneg;
3099 } else {
3100 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3101 ecmd->duplex = DUPLEX_UNKNOWN;
3102 ecmd->autoneg = AUTONEG_DISABLE;
3103 }
3104
3105 if (ahw->port_type == QLCNIC_XGBE) {
3106 ecmd->supported = SUPPORTED_10000baseT_Full;
3107 ecmd->advertising = ADVERTISED_10000baseT_Full;
3108 } else {
3109 ecmd->supported = (SUPPORTED_10baseT_Half |
3110 SUPPORTED_10baseT_Full |
3111 SUPPORTED_100baseT_Half |
3112 SUPPORTED_100baseT_Full |
3113 SUPPORTED_1000baseT_Half |
3114 SUPPORTED_1000baseT_Full);
3115 ecmd->advertising = (ADVERTISED_100baseT_Half |
3116 ADVERTISED_100baseT_Full |
3117 ADVERTISED_1000baseT_Half |
3118 ADVERTISED_1000baseT_Full);
3119 }
3120
3121 switch (ahw->supported_type) {
3122 case PORT_FIBRE:
3123 ecmd->supported |= SUPPORTED_FIBRE;
3124 ecmd->advertising |= ADVERTISED_FIBRE;
3125 ecmd->port = PORT_FIBRE;
3126 ecmd->transceiver = XCVR_EXTERNAL;
3127 break;
3128 case PORT_TP:
3129 ecmd->supported |= SUPPORTED_TP;
3130 ecmd->advertising |= ADVERTISED_TP;
3131 ecmd->port = PORT_TP;
3132 ecmd->transceiver = XCVR_INTERNAL;
3133 break;
3134 default:
3135 ecmd->supported |= SUPPORTED_FIBRE;
3136 ecmd->advertising |= ADVERTISED_FIBRE;
3137 ecmd->port = PORT_OTHER;
3138 ecmd->transceiver = XCVR_EXTERNAL;
3139 break;
3140 }
3141 ecmd->phy_address = ahw->physical_port;
3142 return status;
3143 }
3144
3145 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3146 struct ethtool_cmd *ecmd)
3147 {
3148 int status = 0;
3149 u32 config = adapter->ahw->port_config;
3150
3151 if (ecmd->autoneg)
3152 adapter->ahw->port_config |= BIT_15;
3153
3154 switch (ethtool_cmd_speed(ecmd)) {
3155 case SPEED_10:
3156 adapter->ahw->port_config |= BIT_8;
3157 break;
3158 case SPEED_100:
3159 adapter->ahw->port_config |= BIT_9;
3160 break;
3161 case SPEED_1000:
3162 adapter->ahw->port_config |= BIT_10;
3163 break;
3164 case SPEED_10000:
3165 adapter->ahw->port_config |= BIT_11;
3166 break;
3167 default:
3168 return -EINVAL;
3169 }
3170
3171 status = qlcnic_83xx_set_port_config(adapter);
3172 if (status) {
3173 dev_info(&adapter->pdev->dev,
3174 "Failed to Set Link Speed and autoneg.\n");
3175 adapter->ahw->port_config = config;
3176 }
3177 return status;
3178 }
3179
3180 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3181 u64 *data, int index)
3182 {
3183 u32 low, hi;
3184 u64 val;
3185
3186 low = cmd->rsp.arg[index];
3187 hi = cmd->rsp.arg[index + 1];
3188 val = (((u64) low) | (((u64) hi) << 32));
3189 *data++ = val;
3190 return data;
3191 }
3192
3193 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3194 struct qlcnic_cmd_args *cmd, u64 *data,
3195 int type, int *ret)
3196 {
3197 int err, k, total_regs;
3198
3199 *ret = 0;
3200 err = qlcnic_issue_cmd(adapter, cmd);
3201 if (err != QLCNIC_RCODE_SUCCESS) {
3202 dev_info(&adapter->pdev->dev,
3203 "Error in get statistics mailbox command\n");
3204 *ret = -EIO;
3205 return data;
3206 }
3207 total_regs = cmd->rsp.num;
3208 switch (type) {
3209 case QLC_83XX_STAT_MAC:
3210 /* fill in MAC tx counters */
3211 for (k = 2; k < 28; k += 2)
3212 data = qlcnic_83xx_copy_stats(cmd, data, k);
3213 /* skip 24 bytes of reserved area */
3214 /* fill in MAC rx counters */
3215 for (k += 6; k < 60; k += 2)
3216 data = qlcnic_83xx_copy_stats(cmd, data, k);
3217 /* skip 24 bytes of reserved area */
3218 /* fill in MAC rx frame stats */
3219 for (k += 6; k < 80; k += 2)
3220 data = qlcnic_83xx_copy_stats(cmd, data, k);
3221 /* fill in eSwitch stats */
3222 for (; k < total_regs; k += 2)
3223 data = qlcnic_83xx_copy_stats(cmd, data, k);
3224 break;
3225 case QLC_83XX_STAT_RX:
3226 for (k = 2; k < 8; k += 2)
3227 data = qlcnic_83xx_copy_stats(cmd, data, k);
3228 /* skip 8 bytes of reserved data */
3229 for (k += 2; k < 24; k += 2)
3230 data = qlcnic_83xx_copy_stats(cmd, data, k);
3231 /* skip 8 bytes containing RE1FBQ error data */
3232 for (k += 2; k < total_regs; k += 2)
3233 data = qlcnic_83xx_copy_stats(cmd, data, k);
3234 break;
3235 case QLC_83XX_STAT_TX:
3236 for (k = 2; k < 10; k += 2)
3237 data = qlcnic_83xx_copy_stats(cmd, data, k);
3238 /* skip 8 bytes of reserved data */
3239 for (k += 2; k < total_regs; k += 2)
3240 data = qlcnic_83xx_copy_stats(cmd, data, k);
3241 break;
3242 default:
3243 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3244 *ret = -EIO;
3245 }
3246 return data;
3247 }
3248
3249 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3250 {
3251 struct qlcnic_cmd_args cmd;
3252 struct net_device *netdev = adapter->netdev;
3253 int ret = 0;
3254
3255 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3256 if (ret)
3257 return;
3258 /* Get Tx stats */
3259 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3260 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3261 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3262 QLC_83XX_STAT_TX, &ret);
3263 if (ret) {
3264 netdev_err(netdev, "Error getting Tx stats\n");
3265 goto out;
3266 }
3267 /* Get MAC stats */
3268 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3269 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3270 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3271 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3272 QLC_83XX_STAT_MAC, &ret);
3273 if (ret) {
3274 netdev_err(netdev, "Error getting MAC stats\n");
3275 goto out;
3276 }
3277 /* Get Rx stats */
3278 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3279 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3280 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3281 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3282 QLC_83XX_STAT_RX, &ret);
3283 if (ret)
3284 netdev_err(netdev, "Error getting Rx stats\n");
3285 out:
3286 qlcnic_free_mbx_args(&cmd);
3287 }
3288
3289 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3290 {
3291 u32 major, minor, sub;
3292
3293 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3294 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3295 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3296
3297 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3298 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3299 __func__);
3300 return 1;
3301 }
3302 return 0;
3303 }
3304
3305 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3306 {
3307 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3308 sizeof(*adapter->ahw->ext_reg_tbl)) +
3309 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3310 sizeof(*adapter->ahw->reg_tbl));
3311 }
3312
3313 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3314 {
3315 int i, j = 0;
3316
3317 for (i = QLCNIC_DEV_INFO_SIZE + 1;
3318 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3319 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3320
3321 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3322 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3323 return i;
3324 }
3325
3326 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3327 {
3328 struct qlcnic_adapter *adapter = netdev_priv(netdev);
3329 struct qlcnic_hardware_context *ahw = adapter->ahw;
3330 struct qlcnic_cmd_args cmd;
3331 u8 val, drv_sds_rings = adapter->drv_sds_rings;
3332 u8 drv_tx_rings = adapter->drv_tx_rings;
3333 u32 data;
3334 u16 intrpt_id, id;
3335 int ret;
3336
3337 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3338 netdev_info(netdev, "Device is resetting\n");
3339 return -EBUSY;
3340 }
3341
3342 if (qlcnic_get_diag_lock(adapter)) {
3343 netdev_info(netdev, "Device in diagnostics mode\n");
3344 return -EBUSY;
3345 }
3346
3347 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3348 drv_sds_rings);
3349 if (ret)
3350 goto fail_diag_irq;
3351
3352 ahw->diag_cnt = 0;
3353 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3354 if (ret)
3355 goto fail_diag_irq;
3356
3357 if (adapter->flags & QLCNIC_MSIX_ENABLED)
3358 intrpt_id = ahw->intr_tbl[0].id;
3359 else
3360 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3361
3362 cmd.req.arg[1] = 1;
3363 cmd.req.arg[2] = intrpt_id;
3364 cmd.req.arg[3] = BIT_0;
3365
3366 ret = qlcnic_issue_cmd(adapter, &cmd);
3367 data = cmd.rsp.arg[2];
3368 id = LSW(data);
3369 val = LSB(MSW(data));
3370 if (id != intrpt_id)
3371 dev_info(&adapter->pdev->dev,
3372 "Interrupt generated: 0x%x, requested:0x%x\n",
3373 id, intrpt_id);
3374 if (val)
3375 dev_err(&adapter->pdev->dev,
3376 "Interrupt test error: 0x%x\n", val);
3377 if (ret)
3378 goto done;
3379
3380 msleep(20);
3381 ret = !ahw->diag_cnt;
3382
3383 done:
3384 qlcnic_free_mbx_args(&cmd);
3385 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3386
3387 fail_diag_irq:
3388 adapter->drv_sds_rings = drv_sds_rings;
3389 adapter->drv_tx_rings = drv_tx_rings;
3390 qlcnic_release_diag_lock(adapter);
3391 return ret;
3392 }
3393
3394 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3395 struct ethtool_pauseparam *pause)
3396 {
3397 struct qlcnic_hardware_context *ahw = adapter->ahw;
3398 int status = 0;
3399 u32 config;
3400
3401 status = qlcnic_83xx_get_port_config(adapter);
3402 if (status) {
3403 dev_err(&adapter->pdev->dev,
3404 "%s: Get Pause Config failed\n", __func__);
3405 return;
3406 }
3407 config = ahw->port_config;
3408 if (config & QLC_83XX_CFG_STD_PAUSE) {
3409 switch (MSW(config)) {
3410 case QLC_83XX_TX_PAUSE:
3411 pause->tx_pause = 1;
3412 break;
3413 case QLC_83XX_RX_PAUSE:
3414 pause->rx_pause = 1;
3415 break;
3416 case QLC_83XX_TX_RX_PAUSE:
3417 default:
3418 /* Backward compatibility for existing
3419 * flash definitions
3420 */
3421 pause->tx_pause = 1;
3422 pause->rx_pause = 1;
3423 }
3424 }
3425
3426 if (QLC_83XX_AUTONEG(config))
3427 pause->autoneg = 1;
3428 }
3429
3430 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3431 struct ethtool_pauseparam *pause)
3432 {
3433 struct qlcnic_hardware_context *ahw = adapter->ahw;
3434 int status = 0;
3435 u32 config;
3436
3437 status = qlcnic_83xx_get_port_config(adapter);
3438 if (status) {
3439 dev_err(&adapter->pdev->dev,
3440 "%s: Get Pause Config failed.\n", __func__);
3441 return status;
3442 }
3443 config = ahw->port_config;
3444
3445 if (ahw->port_type == QLCNIC_GBE) {
3446 if (pause->autoneg)
3447 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3448 if (!pause->autoneg)
3449 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3450 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3451 return -EOPNOTSUPP;
3452 }
3453
3454 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3455 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3456
3457 if (pause->rx_pause && pause->tx_pause) {
3458 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3459 } else if (pause->rx_pause && !pause->tx_pause) {
3460 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3461 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3462 } else if (pause->tx_pause && !pause->rx_pause) {
3463 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3464 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3465 } else if (!pause->rx_pause && !pause->tx_pause) {
3466 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3467 QLC_83XX_CFG_STD_PAUSE);
3468 }
3469 status = qlcnic_83xx_set_port_config(adapter);
3470 if (status) {
3471 dev_err(&adapter->pdev->dev,
3472 "%s: Set Pause Config failed.\n", __func__);
3473 ahw->port_config = config;
3474 }
3475 return status;
3476 }
3477
3478 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3479 {
3480 int ret, err = 0;
3481 u32 temp;
3482
3483 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3484 QLC_83XX_FLASH_OEM_READ_SIG);
3485 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3486 QLC_83XX_FLASH_READ_CTRL);
3487 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3488 if (ret)
3489 return -EIO;
3490
3491 temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3492 if (err == -EIO)
3493 return err;
3494
3495 return temp & 0xFF;
3496 }
3497
3498 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3499 {
3500 int status;
3501
3502 status = qlcnic_83xx_read_flash_status_reg(adapter);
3503 if (status == -EIO) {
3504 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3505 __func__);
3506 return 1;
3507 }
3508 return 0;
3509 }
3510
3511 static int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3512 {
3513 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3514 struct net_device *netdev = adapter->netdev;
3515 int retval;
3516
3517 netif_device_detach(netdev);
3518 qlcnic_cancel_idc_work(adapter);
3519
3520 if (netif_running(netdev))
3521 qlcnic_down(adapter, netdev);
3522
3523 qlcnic_83xx_disable_mbx_intr(adapter);
3524 cancel_delayed_work_sync(&adapter->idc_aen_work);
3525
3526 retval = pci_save_state(pdev);
3527 if (retval)
3528 return retval;
3529
3530 return 0;
3531 }
3532
3533 static int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3534 {
3535 struct qlcnic_hardware_context *ahw = adapter->ahw;
3536 struct qlc_83xx_idc *idc = &ahw->idc;
3537 int err = 0;
3538
3539 err = qlcnic_83xx_idc_init(adapter);
3540 if (err)
3541 return err;
3542
3543 if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3544 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3545 qlcnic_83xx_set_vnic_opmode(adapter);
3546 } else {
3547 err = qlcnic_83xx_check_vnic_state(adapter);
3548 if (err)
3549 return err;
3550 }
3551 }
3552
3553 err = qlcnic_83xx_idc_reattach_driver(adapter);
3554 if (err)
3555 return err;
3556
3557 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3558 idc->delay);
3559 return err;
3560 }
3561
3562 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3563 {
3564 reinit_completion(&mbx->completion);
3565 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3566 }
3567
3568 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3569 {
3570 if (!mbx)
3571 return;
3572
3573 destroy_workqueue(mbx->work_q);
3574 kfree(mbx);
3575 }
3576
3577 static inline void
3578 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3579 struct qlcnic_cmd_args *cmd)
3580 {
3581 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3582
3583 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3584 qlcnic_free_mbx_args(cmd);
3585 kfree(cmd);
3586 return;
3587 }
3588 complete(&cmd->completion);
3589 }
3590
3591 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3592 {
3593 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3594 struct list_head *head = &mbx->cmd_q;
3595 struct qlcnic_cmd_args *cmd = NULL;
3596
3597 spin_lock(&mbx->queue_lock);
3598
3599 while (!list_empty(head)) {
3600 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3601 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3602 __func__, cmd->cmd_op);
3603 list_del(&cmd->list);
3604 mbx->num_cmds--;
3605 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3606 }
3607
3608 spin_unlock(&mbx->queue_lock);
3609 }
3610
3611 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3612 {
3613 struct qlcnic_hardware_context *ahw = adapter->ahw;
3614 struct qlcnic_mailbox *mbx = ahw->mailbox;
3615 u32 host_mbx_ctrl;
3616
3617 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3618 return -EBUSY;
3619
3620 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3621 if (host_mbx_ctrl) {
3622 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3623 ahw->idc.collect_dump = 1;
3624 return -EIO;
3625 }
3626
3627 return 0;
3628 }
3629
3630 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3631 u8 issue_cmd)
3632 {
3633 if (issue_cmd)
3634 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3635 else
3636 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3637 }
3638
3639 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3640 struct qlcnic_cmd_args *cmd)
3641 {
3642 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3643
3644 spin_lock(&mbx->queue_lock);
3645
3646 list_del(&cmd->list);
3647 mbx->num_cmds--;
3648
3649 spin_unlock(&mbx->queue_lock);
3650
3651 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3652 }
3653
3654 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3655 struct qlcnic_cmd_args *cmd)
3656 {
3657 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3658 struct qlcnic_hardware_context *ahw = adapter->ahw;
3659 int i, j;
3660
3661 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3662 mbx_cmd = cmd->req.arg[0];
3663 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3664 for (i = 1; i < cmd->req.num; i++)
3665 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3666 } else {
3667 fw_hal_version = ahw->fw_hal_version;
3668 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3669 total_size = cmd->pay_size + hdr_size;
3670 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3671 mbx_cmd = tmp | fw_hal_version << 29;
3672 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3673
3674 /* Back channel specific operations bits */
3675 mbx_cmd = 0x1 | 1 << 4;
3676
3677 if (qlcnic_sriov_pf_check(adapter))
3678 mbx_cmd |= cmd->func_num << 5;
3679
3680 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3681
3682 for (i = 2, j = 0; j < hdr_size; i++, j++)
3683 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3684 for (j = 0; j < cmd->pay_size; j++, i++)
3685 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3686 }
3687 }
3688
3689 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3690 {
3691 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3692
3693 if (!mbx)
3694 return;
3695
3696 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3697 complete(&mbx->completion);
3698 cancel_work_sync(&mbx->work);
3699 flush_workqueue(mbx->work_q);
3700 qlcnic_83xx_flush_mbx_queue(adapter);
3701 }
3702
3703 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3704 struct qlcnic_cmd_args *cmd,
3705 unsigned long *timeout)
3706 {
3707 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3708
3709 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3710 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3711 init_completion(&cmd->completion);
3712 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3713
3714 spin_lock(&mbx->queue_lock);
3715
3716 list_add_tail(&cmd->list, &mbx->cmd_q);
3717 mbx->num_cmds++;
3718 cmd->total_cmds = mbx->num_cmds;
3719 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3720 queue_work(mbx->work_q, &mbx->work);
3721
3722 spin_unlock(&mbx->queue_lock);
3723
3724 return 0;
3725 }
3726
3727 return -EBUSY;
3728 }
3729
3730 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3731 struct qlcnic_cmd_args *cmd)
3732 {
3733 u8 mac_cmd_rcode;
3734 u32 fw_data;
3735
3736 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3737 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3738 mac_cmd_rcode = (u8)fw_data;
3739 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3740 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3741 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3742 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3743 return QLCNIC_RCODE_SUCCESS;
3744 }
3745 }
3746
3747 return -EINVAL;
3748 }
3749
3750 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3751 struct qlcnic_cmd_args *cmd)
3752 {
3753 struct qlcnic_hardware_context *ahw = adapter->ahw;
3754 struct device *dev = &adapter->pdev->dev;
3755 u8 mbx_err_code;
3756 u32 fw_data;
3757
3758 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3759 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3760 qlcnic_83xx_get_mbx_data(adapter, cmd);
3761
3762 switch (mbx_err_code) {
3763 case QLCNIC_MBX_RSP_OK:
3764 case QLCNIC_MBX_PORT_RSP_OK:
3765 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3766 break;
3767 default:
3768 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3769 break;
3770
3771 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3772 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3773 ahw->op_mode, mbx_err_code);
3774 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3775 qlcnic_dump_mbx(adapter, cmd);
3776 }
3777
3778 return;
3779 }
3780
3781 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter)
3782 {
3783 struct qlcnic_hardware_context *ahw = adapter->ahw;
3784 u32 offset;
3785
3786 offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
3787 dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x",
3788 readl(ahw->pci_base0 + offset),
3789 QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL),
3790 QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL),
3791 QLCRDX(ahw, QLCNIC_FW_MBX_CTRL));
3792 }
3793
3794 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3795 {
3796 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3797 work);
3798 struct qlcnic_adapter *adapter = mbx->adapter;
3799 struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3800 struct device *dev = &adapter->pdev->dev;
3801 atomic_t *rsp_status = &mbx->rsp_status;
3802 struct list_head *head = &mbx->cmd_q;
3803 struct qlcnic_hardware_context *ahw;
3804 struct qlcnic_cmd_args *cmd = NULL;
3805
3806 ahw = adapter->ahw;
3807
3808 while (true) {
3809 if (qlcnic_83xx_check_mbx_status(adapter)) {
3810 qlcnic_83xx_flush_mbx_queue(adapter);
3811 return;
3812 }
3813
3814 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3815
3816 spin_lock(&mbx->queue_lock);
3817
3818 if (list_empty(head)) {
3819 spin_unlock(&mbx->queue_lock);
3820 return;
3821 }
3822 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3823
3824 spin_unlock(&mbx->queue_lock);
3825
3826 mbx_ops->encode_cmd(adapter, cmd);
3827 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3828
3829 if (wait_for_completion_timeout(&mbx->completion,
3830 QLC_83XX_MBX_TIMEOUT)) {
3831 mbx_ops->decode_resp(adapter, cmd);
3832 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3833 } else {
3834 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3835 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3836 ahw->op_mode);
3837 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3838 qlcnic_dump_mailbox_registers(adapter);
3839 qlcnic_83xx_get_mbx_data(adapter, cmd);
3840 qlcnic_dump_mbx(adapter, cmd);
3841 qlcnic_83xx_idc_request_reset(adapter,
3842 QLCNIC_FORCE_FW_DUMP_KEY);
3843 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3844 }
3845 mbx_ops->dequeue_cmd(adapter, cmd);
3846 }
3847 }
3848
3849 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3850 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd,
3851 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd,
3852 .decode_resp = qlcnic_83xx_decode_mbx_rsp,
3853 .encode_cmd = qlcnic_83xx_encode_mbx_cmd,
3854 .nofity_fw = qlcnic_83xx_signal_mbx_cmd,
3855 };
3856
3857 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3858 {
3859 struct qlcnic_hardware_context *ahw = adapter->ahw;
3860 struct qlcnic_mailbox *mbx;
3861
3862 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3863 if (!ahw->mailbox)
3864 return -ENOMEM;
3865
3866 mbx = ahw->mailbox;
3867 mbx->ops = &qlcnic_83xx_mbx_ops;
3868 mbx->adapter = adapter;
3869
3870 spin_lock_init(&mbx->queue_lock);
3871 spin_lock_init(&mbx->aen_lock);
3872 INIT_LIST_HEAD(&mbx->cmd_q);
3873 init_completion(&mbx->completion);
3874
3875 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
3876 if (mbx->work_q == NULL) {
3877 kfree(mbx);
3878 return -ENOMEM;
3879 }
3880
3881 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
3882 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3883 return 0;
3884 }
3885
3886 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
3887 pci_channel_state_t state)
3888 {
3889 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3890
3891 if (state == pci_channel_io_perm_failure)
3892 return PCI_ERS_RESULT_DISCONNECT;
3893
3894 if (state == pci_channel_io_normal)
3895 return PCI_ERS_RESULT_RECOVERED;
3896
3897 set_bit(__QLCNIC_AER, &adapter->state);
3898 set_bit(__QLCNIC_RESETTING, &adapter->state);
3899
3900 qlcnic_83xx_aer_stop_poll_work(adapter);
3901
3902 pci_save_state(pdev);
3903 pci_disable_device(pdev);
3904
3905 return PCI_ERS_RESULT_NEED_RESET;
3906 }
3907
3908 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
3909 {
3910 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3911 int err = 0;
3912
3913 pdev->error_state = pci_channel_io_normal;
3914 err = pci_enable_device(pdev);
3915 if (err)
3916 goto disconnect;
3917
3918 pci_set_power_state(pdev, PCI_D0);
3919 pci_set_master(pdev);
3920 pci_restore_state(pdev);
3921
3922 err = qlcnic_83xx_aer_reset(adapter);
3923 if (err == 0)
3924 return PCI_ERS_RESULT_RECOVERED;
3925 disconnect:
3926 clear_bit(__QLCNIC_AER, &adapter->state);
3927 clear_bit(__QLCNIC_RESETTING, &adapter->state);
3928 return PCI_ERS_RESULT_DISCONNECT;
3929 }
3930
3931 static void qlcnic_83xx_io_resume(struct pci_dev *pdev)
3932 {
3933 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3934
3935 pci_cleanup_aer_uncorrect_error_status(pdev);
3936 if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
3937 qlcnic_83xx_aer_start_poll_work(adapter);
3938 }
Linux kernel - Deliverables
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