2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
8 #include "qlcnic_sriov.h"
10 #include "qlcnic_hw.h"
12 /* Reset template definitions */
13 #define QLC_83XX_RESTART_TEMPLATE_SIZE 0x2000
14 #define QLC_83XX_RESET_TEMPLATE_ADDR 0x4F0000
15 #define QLC_83XX_RESET_SEQ_VERSION 0x0101
17 #define QLC_83XX_OPCODE_NOP 0x0000
18 #define QLC_83XX_OPCODE_WRITE_LIST 0x0001
19 #define QLC_83XX_OPCODE_READ_WRITE_LIST 0x0002
20 #define QLC_83XX_OPCODE_POLL_LIST 0x0004
21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST 0x0008
22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE 0x0010
23 #define QLC_83XX_OPCODE_SEQ_PAUSE 0x0020
24 #define QLC_83XX_OPCODE_SEQ_END 0x0040
25 #define QLC_83XX_OPCODE_TMPL_END 0x0080
26 #define QLC_83XX_OPCODE_POLL_READ_LIST 0x0100
28 /* EPORT control registers */
29 #define QLC_83XX_RESET_CONTROL 0x28084E50
30 #define QLC_83XX_RESET_REG 0x28084E60
31 #define QLC_83XX_RESET_PORT0 0x28084E70
32 #define QLC_83XX_RESET_PORT1 0x28084E80
33 #define QLC_83XX_RESET_PORT2 0x28084E90
34 #define QLC_83XX_RESET_PORT3 0x28084EA0
35 #define QLC_83XX_RESET_SRESHIM 0x28084EB0
36 #define QLC_83XX_RESET_EPGSHIM 0x28084EC0
37 #define QLC_83XX_RESET_ETHERPCS 0x28084ED0
39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter
*adapter
);
40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter
*p_dev
);
41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter
*adapter
);
42 static int qlcnic_83xx_check_hw_status(struct qlcnic_adapter
*p_dev
);
43 static int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter
*);
44 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter
*);
47 struct qlc_83xx_reset_hdr
{
48 #if defined(__LITTLE_ENDIAN)
57 #elif defined(__BIG_ENDIAN)
69 /* Command entry header. */
70 struct qlc_83xx_entry_hdr
{
71 #if defined(__LITTLE_ENDIAN)
76 #elif defined(__BIG_ENDIAN)
84 /* Generic poll command */
85 struct qlc_83xx_poll
{
90 /* Read modify write command */
95 #if defined(__LITTLE_ENDIAN)
100 #elif defined(__BIG_ENDIAN)
108 /* Generic command with 2 DWORD */
109 struct qlc_83xx_entry
{
114 /* Generic command with 4 DWORD */
115 struct qlc_83xx_quad_entry
{
121 static const char *const qlc_83xx_idc_states
[] = {
133 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter
*adapter
)
137 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
);
144 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter
*adapter
)
147 cur
= adapter
->ahw
->idc
.curr_state
;
148 prev
= adapter
->ahw
->idc
.prev_state
;
150 dev_info(&adapter
->pdev
->dev
,
151 "current state = %s, prev state = %s\n",
152 adapter
->ahw
->idc
.name
[cur
],
153 adapter
->ahw
->idc
.name
[prev
]);
156 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter
*adapter
,
163 if (qlcnic_83xx_lock_driver(adapter
))
167 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_AUDIT
);
168 val
|= (adapter
->portnum
& 0xf);
171 seconds
= jiffies
/ HZ
- adapter
->ahw
->idc
.sec_counter
;
173 seconds
= jiffies
/ HZ
;
176 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DRV_AUDIT
, val
);
177 adapter
->ahw
->idc
.sec_counter
= jiffies
/ HZ
;
180 qlcnic_83xx_unlock_driver(adapter
);
185 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter
*adapter
)
189 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_MIN_VERSION
);
190 val
= val
& ~(0x3 << (adapter
->portnum
* 2));
191 val
= val
| (QLC_83XX_IDC_MINOR_VERSION
<< (adapter
->portnum
* 2));
192 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_MIN_VERSION
, val
);
195 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter
*adapter
,
201 if (qlcnic_83xx_lock_driver(adapter
))
205 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_MAJ_VERSION
);
207 val
= val
| QLC_83XX_IDC_MAJOR_VERSION
;
208 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_MAJ_VERSION
, val
);
211 qlcnic_83xx_unlock_driver(adapter
);
217 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter
*adapter
,
218 int status
, int lock
)
223 if (qlcnic_83xx_lock_driver(adapter
))
227 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
);
230 val
= val
| (1 << adapter
->portnum
);
232 val
= val
& ~(1 << adapter
->portnum
);
234 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
, val
);
235 qlcnic_83xx_idc_update_minor_version(adapter
);
238 qlcnic_83xx_unlock_driver(adapter
);
243 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter
*adapter
)
248 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_MAJ_VERSION
);
249 version
= val
& 0xFF;
251 if (version
!= QLC_83XX_IDC_MAJOR_VERSION
) {
252 dev_info(&adapter
->pdev
->dev
,
253 "%s:mismatch. version 0x%x, expected version 0x%x\n",
254 __func__
, version
, QLC_83XX_IDC_MAJOR_VERSION
);
261 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter
*adapter
,
267 if (qlcnic_83xx_lock_driver(adapter
))
271 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DRV_ACK
, 0);
272 /* Clear graceful reset bit */
273 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
274 val
&= ~QLC_83XX_IDC_GRACEFULL_RESET
;
275 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_CTRL
, val
);
278 qlcnic_83xx_unlock_driver(adapter
);
283 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter
*adapter
,
289 if (qlcnic_83xx_lock_driver(adapter
))
293 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_ACK
);
295 val
= val
| (1 << adapter
->portnum
);
297 val
= val
& ~(1 << adapter
->portnum
);
298 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DRV_ACK
, val
);
301 qlcnic_83xx_unlock_driver(adapter
);
306 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter
*adapter
,
311 seconds
= jiffies
/ HZ
- adapter
->ahw
->idc
.sec_counter
;
312 if (seconds
<= time_limit
)
319 * qlcnic_83xx_idc_check_reset_ack_reg
321 * @adapter: adapter structure
323 * Check ACK wait limit and clear the functions which failed to ACK
325 * Return 0 if all functions have acknowledged the reset request.
327 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter
*adapter
)
330 u32 ack
, presence
, val
;
332 timeout
= QLC_83XX_IDC_RESET_TIMEOUT_SECS
;
333 ack
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_ACK
);
334 presence
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
);
335 dev_info(&adapter
->pdev
->dev
,
336 "%s: ack = 0x%x, presence = 0x%x\n", __func__
, ack
, presence
);
337 if (!((ack
& presence
) == presence
)) {
338 if (qlcnic_83xx_idc_check_timeout(adapter
, timeout
)) {
339 /* Clear functions which failed to ACK */
340 dev_info(&adapter
->pdev
->dev
,
341 "%s: ACK wait exceeds time limit\n", __func__
);
342 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
);
343 val
= val
& ~(ack
^ presence
);
344 if (qlcnic_83xx_lock_driver(adapter
))
346 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
, val
);
347 dev_info(&adapter
->pdev
->dev
,
348 "%s: updated drv presence reg = 0x%x\n",
350 qlcnic_83xx_unlock_driver(adapter
);
357 dev_info(&adapter
->pdev
->dev
,
358 "%s: Reset ACK received from all functions\n",
365 * qlcnic_83xx_idc_tx_soft_reset
367 * @adapter: adapter structure
369 * Handle context deletion and recreation request from transmit routine
371 * Returns -EBUSY or Success (0)
374 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter
*adapter
)
376 struct net_device
*netdev
= adapter
->netdev
;
378 if (test_and_set_bit(__QLCNIC_RESETTING
, &adapter
->state
))
381 netif_device_detach(netdev
);
382 qlcnic_down(adapter
, netdev
);
383 qlcnic_up(adapter
, netdev
);
384 netif_device_attach(netdev
);
385 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
386 netdev_info(adapter
->netdev
, "%s: soft reset complete.\n", __func__
);
392 * qlcnic_83xx_idc_detach_driver
394 * @adapter: adapter structure
395 * Detach net interface, stop TX and cleanup resources before the HW reset.
399 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter
*adapter
)
402 struct net_device
*netdev
= adapter
->netdev
;
404 netif_device_detach(netdev
);
405 qlcnic_83xx_detach_mailbox_work(adapter
);
407 /* Disable mailbox interrupt */
408 qlcnic_83xx_disable_mbx_intr(adapter
);
409 qlcnic_down(adapter
, netdev
);
410 for (i
= 0; i
< adapter
->ahw
->num_msix
; i
++) {
411 adapter
->ahw
->intr_tbl
[i
].id
= i
;
412 adapter
->ahw
->intr_tbl
[i
].enabled
= 0;
413 adapter
->ahw
->intr_tbl
[i
].src
= 0;
416 if (qlcnic_sriov_pf_check(adapter
))
417 qlcnic_sriov_pf_reset(adapter
);
421 * qlcnic_83xx_idc_attach_driver
423 * @adapter: adapter structure
425 * Re-attach and re-enable net interface
429 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter
*adapter
)
431 struct net_device
*netdev
= adapter
->netdev
;
433 if (netif_running(netdev
)) {
434 if (qlcnic_up(adapter
, netdev
))
436 qlcnic_restore_indev_addr(netdev
, NETDEV_UP
);
439 netif_device_attach(netdev
);
442 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter
*adapter
,
446 if (qlcnic_83xx_lock_driver(adapter
))
450 qlcnic_83xx_idc_clear_registers(adapter
, 0);
451 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
, QLC_83XX_IDC_DEV_FAILED
);
453 qlcnic_83xx_unlock_driver(adapter
);
455 qlcnic_83xx_idc_log_state_history(adapter
);
456 dev_info(&adapter
->pdev
->dev
, "Device will enter failed state\n");
461 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter
*adapter
,
465 if (qlcnic_83xx_lock_driver(adapter
))
469 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
, QLC_83XX_IDC_DEV_INIT
);
472 qlcnic_83xx_unlock_driver(adapter
);
477 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter
*adapter
,
481 if (qlcnic_83xx_lock_driver(adapter
))
485 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
,
486 QLC_83XX_IDC_DEV_NEED_QUISCENT
);
489 qlcnic_83xx_unlock_driver(adapter
);
495 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter
*adapter
, int lock
)
498 if (qlcnic_83xx_lock_driver(adapter
))
502 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
,
503 QLC_83XX_IDC_DEV_NEED_RESET
);
506 qlcnic_83xx_unlock_driver(adapter
);
511 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter
*adapter
,
515 if (qlcnic_83xx_lock_driver(adapter
))
519 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
, QLC_83XX_IDC_DEV_READY
);
521 qlcnic_83xx_unlock_driver(adapter
);
527 * qlcnic_83xx_idc_find_reset_owner_id
529 * @adapter: adapter structure
531 * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
532 * Within the same class, function with lowest PCI ID assumes ownership
534 * Returns: reset owner id or failure indication (-EIO)
537 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter
*adapter
)
539 u32 reg
, reg1
, reg2
, i
, j
, owner
, class;
541 reg1
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DEV_PARTITION_INFO_1
);
542 reg2
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DEV_PARTITION_INFO_2
);
543 owner
= QLCNIC_TYPE_NIC
;
549 class = (((reg
& (0xF << j
* 4)) >> j
* 4) & 0x3);
552 if (i
== (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO
- 1)) {
559 if (i
== (QLC_83XX_IDC_MAX_CNA_FUNCTIONS
- 1)) {
560 if (owner
== QLCNIC_TYPE_NIC
)
561 owner
= QLCNIC_TYPE_ISCSI
;
562 else if (owner
== QLCNIC_TYPE_ISCSI
)
563 owner
= QLCNIC_TYPE_FCOE
;
564 else if (owner
== QLCNIC_TYPE_FCOE
)
570 } while (i
++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS
);
575 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter
*adapter
, int lock
)
579 ret
= qlcnic_83xx_restart_hw(adapter
);
582 qlcnic_83xx_idc_enter_failed_state(adapter
, lock
);
584 qlcnic_83xx_idc_clear_registers(adapter
, lock
);
585 ret
= qlcnic_83xx_idc_enter_ready_state(adapter
, lock
);
591 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter
*adapter
)
595 status
= QLC_SHARED_REG_RD32(adapter
, QLCNIC_PEG_HALT_STATUS1
);
597 if (status
& QLCNIC_RCODE_FATAL_ERROR
) {
598 dev_err(&adapter
->pdev
->dev
,
599 "peg halt status1=0x%x\n", status
);
600 if (QLCNIC_FWERROR_CODE(status
) == QLCNIC_FWERROR_FAN_FAILURE
) {
601 dev_err(&adapter
->pdev
->dev
,
602 "On board active cooling fan failed. "
603 "Device has been halted.\n");
604 dev_err(&adapter
->pdev
->dev
,
605 "Replace the adapter.\n");
613 int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter
*adapter
)
617 qlcnic_83xx_reinit_mbx_work(adapter
->ahw
->mailbox
);
618 qlcnic_83xx_enable_mbx_interrupt(adapter
);
620 qlcnic_83xx_initialize_nic(adapter
, 1);
622 err
= qlcnic_sriov_pf_reinit(adapter
);
626 qlcnic_83xx_enable_mbx_interrupt(adapter
);
628 if (qlcnic_83xx_configure_opmode(adapter
)) {
629 qlcnic_83xx_idc_enter_failed_state(adapter
, 1);
633 if (adapter
->nic_ops
->init_driver(adapter
)) {
634 qlcnic_83xx_idc_enter_failed_state(adapter
, 1);
638 if (adapter
->portnum
== 0)
639 qlcnic_set_drv_version(adapter
);
641 qlcnic_dcb_get_info(adapter
->dcb
);
642 qlcnic_83xx_idc_attach_driver(adapter
);
647 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter
*adapter
)
649 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
651 qlcnic_83xx_idc_update_drv_presence_reg(adapter
, 1, 1);
652 qlcnic_83xx_idc_update_audit_reg(adapter
, 0, 1);
653 set_bit(QLC_83XX_MODULE_LOADED
, &adapter
->ahw
->idc
.status
);
655 ahw
->idc
.quiesce_req
= 0;
656 ahw
->idc
.delay
= QLC_83XX_IDC_FW_POLL_DELAY
;
657 ahw
->idc
.err_code
= 0;
658 ahw
->idc
.collect_dump
= 0;
659 ahw
->reset_context
= 0;
660 adapter
->tx_timeo_cnt
= 0;
661 ahw
->idc
.delay_reset
= 0;
663 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
667 * qlcnic_83xx_idc_ready_state_entry
669 * @adapter: adapter structure
671 * Perform ready state initialization, this routine will get invoked only
672 * once from READY state.
674 * Returns: Error code or Success(0)
677 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter
*adapter
)
679 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
681 if (ahw
->idc
.prev_state
!= QLC_83XX_IDC_DEV_READY
) {
682 qlcnic_83xx_idc_update_idc_params(adapter
);
683 /* Re-attach the device if required */
684 if ((ahw
->idc
.prev_state
== QLC_83XX_IDC_DEV_NEED_RESET
) ||
685 (ahw
->idc
.prev_state
== QLC_83XX_IDC_DEV_INIT
)) {
686 if (qlcnic_83xx_idc_reattach_driver(adapter
))
695 * qlcnic_83xx_idc_vnic_pf_entry
697 * @adapter: adapter structure
699 * Ensure vNIC mode privileged function starts only after vNIC mode is
700 * enabled by management function.
701 * If vNIC mode is ready, start initialization.
706 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter
*adapter
)
709 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
711 /* Privileged function waits till mgmt function enables VNIC mode */
712 state
= QLCRDX(adapter
->ahw
, QLC_83XX_VNIC_STATE
);
713 if (state
!= QLCNIC_DEV_NPAR_OPER
) {
714 if (!ahw
->idc
.vnic_wait_limit
--) {
715 qlcnic_83xx_idc_enter_failed_state(adapter
, 1);
718 dev_info(&adapter
->pdev
->dev
, "vNIC mode disabled\n");
722 /* Perform one time initialization from ready state */
723 if (ahw
->idc
.vnic_state
!= QLCNIC_DEV_NPAR_OPER
) {
724 qlcnic_83xx_idc_update_idc_params(adapter
);
726 /* If the previous state is UNKNOWN, device will be
727 already attached properly by Init routine*/
728 if (ahw
->idc
.prev_state
!= QLC_83XX_IDC_DEV_UNKNOWN
) {
729 if (qlcnic_83xx_idc_reattach_driver(adapter
))
732 adapter
->ahw
->idc
.vnic_state
= QLCNIC_DEV_NPAR_OPER
;
733 dev_info(&adapter
->pdev
->dev
, "vNIC mode enabled\n");
740 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter
*adapter
)
742 adapter
->ahw
->idc
.err_code
= -EIO
;
743 dev_err(&adapter
->pdev
->dev
,
744 "%s: Device in unknown state\n", __func__
);
745 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
750 * qlcnic_83xx_idc_cold_state
752 * @adapter: adapter structure
754 * If HW is up and running device will enter READY state.
755 * If firmware image from host needs to be loaded, device is
756 * forced to start with the file firmware image.
758 * Returns: Error code or Success(0)
761 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter
*adapter
)
763 qlcnic_83xx_idc_update_drv_presence_reg(adapter
, 1, 0);
764 qlcnic_83xx_idc_update_audit_reg(adapter
, 1, 0);
766 if (qlcnic_load_fw_file
) {
767 qlcnic_83xx_idc_restart_hw(adapter
, 0);
769 if (qlcnic_83xx_check_hw_status(adapter
)) {
770 qlcnic_83xx_idc_enter_failed_state(adapter
, 0);
773 qlcnic_83xx_idc_enter_ready_state(adapter
, 0);
780 * qlcnic_83xx_idc_init_state
782 * @adapter: adapter structure
784 * Reset owner will restart the device from this state.
785 * Device will enter failed state if it remains
786 * in this state for more than DEV_INIT time limit.
788 * Returns: Error code or Success(0)
791 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter
*adapter
)
793 int timeout
, ret
= 0;
796 timeout
= QLC_83XX_IDC_INIT_TIMEOUT_SECS
;
797 if (adapter
->ahw
->idc
.prev_state
== QLC_83XX_IDC_DEV_NEED_RESET
) {
798 owner
= qlcnic_83xx_idc_find_reset_owner_id(adapter
);
799 if (adapter
->ahw
->pci_func
== owner
)
800 ret
= qlcnic_83xx_idc_restart_hw(adapter
, 1);
802 ret
= qlcnic_83xx_idc_check_timeout(adapter
, timeout
);
809 * qlcnic_83xx_idc_ready_state
811 * @adapter: adapter structure
813 * Perform IDC protocol specicifed actions after monitoring device state and
816 * Returns: Error code or Success(0)
819 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter
*adapter
)
821 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
822 struct qlcnic_mailbox
*mbx
= ahw
->mailbox
;
826 /* Perform NIC configuration based ready state entry actions */
827 if (ahw
->idc
.state_entry(adapter
))
830 if (qlcnic_check_temp(adapter
)) {
831 if (ahw
->temp
== QLCNIC_TEMP_PANIC
) {
832 qlcnic_83xx_idc_check_fan_failure(adapter
);
833 dev_err(&adapter
->pdev
->dev
,
834 "Error: device temperature %d above limits\n",
836 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
837 set_bit(__QLCNIC_RESETTING
, &adapter
->state
);
838 qlcnic_83xx_idc_detach_driver(adapter
);
839 qlcnic_83xx_idc_enter_failed_state(adapter
, 1);
844 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
845 ret
= qlcnic_83xx_check_heartbeat(adapter
);
847 adapter
->flags
|= QLCNIC_FW_HANG
;
848 if (!(val
& QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY
)) {
849 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
850 set_bit(__QLCNIC_RESETTING
, &adapter
->state
);
851 qlcnic_83xx_idc_enter_need_reset_state(adapter
, 1);
853 netdev_info(adapter
->netdev
, "%s: Auto firmware recovery is disabled\n",
855 qlcnic_83xx_idc_enter_failed_state(adapter
, 1);
860 if ((val
& QLC_83XX_IDC_GRACEFULL_RESET
) || ahw
->idc
.collect_dump
) {
861 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
863 /* Move to need reset state and prepare for reset */
864 qlcnic_83xx_idc_enter_need_reset_state(adapter
, 1);
868 /* Check for soft reset request */
869 if (ahw
->reset_context
&&
870 !(val
& QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY
)) {
871 adapter
->ahw
->reset_context
= 0;
872 qlcnic_83xx_idc_tx_soft_reset(adapter
);
876 /* Move to need quiesce state if requested */
877 if (adapter
->ahw
->idc
.quiesce_req
) {
878 qlcnic_83xx_idc_enter_need_quiesce(adapter
, 1);
879 qlcnic_83xx_idc_update_audit_reg(adapter
, 0, 1);
887 * qlcnic_83xx_idc_need_reset_state
889 * @adapter: adapter structure
891 * Device will remain in this state until:
892 * Reset request ACK's are received from all the functions
893 * Wait time exceeds max time limit
895 * Returns: Error code or Success(0)
898 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter
*adapter
)
900 struct qlcnic_mailbox
*mbx
= adapter
->ahw
->mailbox
;
903 if (adapter
->ahw
->idc
.prev_state
!= QLC_83XX_IDC_DEV_NEED_RESET
) {
904 qlcnic_83xx_idc_update_audit_reg(adapter
, 0, 1);
905 set_bit(__QLCNIC_RESETTING
, &adapter
->state
);
906 clear_bit(QLC_83XX_MBX_READY
, &mbx
->status
);
907 if (adapter
->ahw
->nic_mode
== QLCNIC_VNIC_MODE
)
908 qlcnic_83xx_disable_vnic_mode(adapter
, 1);
910 if (qlcnic_check_diag_status(adapter
)) {
911 dev_info(&adapter
->pdev
->dev
,
912 "%s: Wait for diag completion\n", __func__
);
913 adapter
->ahw
->idc
.delay_reset
= 1;
916 qlcnic_83xx_idc_update_drv_ack_reg(adapter
, 1, 1);
917 qlcnic_83xx_idc_detach_driver(adapter
);
921 if (qlcnic_check_diag_status(adapter
)) {
922 dev_info(&adapter
->pdev
->dev
,
923 "%s: Wait for diag completion\n", __func__
);
926 if (adapter
->ahw
->idc
.delay_reset
) {
927 qlcnic_83xx_idc_update_drv_ack_reg(adapter
, 1, 1);
928 qlcnic_83xx_idc_detach_driver(adapter
);
929 adapter
->ahw
->idc
.delay_reset
= 0;
932 /* Check for ACK from other functions */
933 ret
= qlcnic_83xx_idc_check_reset_ack_reg(adapter
);
935 dev_info(&adapter
->pdev
->dev
,
936 "%s: Waiting for reset ACK\n", __func__
);
941 /* Transit to INIT state and restart the HW */
942 qlcnic_83xx_idc_enter_init_state(adapter
, 1);
947 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter
*adapter
)
949 dev_err(&adapter
->pdev
->dev
, "%s: TBD\n", __func__
);
953 static void qlcnic_83xx_idc_failed_state(struct qlcnic_adapter
*adapter
)
955 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
958 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
959 if (val
& QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY
) {
960 owner
= qlcnic_83xx_idc_find_reset_owner_id(adapter
);
961 if (ahw
->pci_func
== owner
) {
962 qlcnic_83xx_stop_hw(adapter
);
963 qlcnic_dump_fw(adapter
);
967 netdev_warn(adapter
->netdev
, "%s: Reboot will be required to recover the adapter!!\n",
969 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
970 ahw
->idc
.err_code
= -EIO
;
975 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter
*adapter
)
977 dev_info(&adapter
->pdev
->dev
, "%s: TBD\n", __func__
);
981 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter
*adapter
,
986 cur
= adapter
->ahw
->idc
.curr_state
;
987 prev
= adapter
->ahw
->idc
.prev_state
;
990 if ((next
< QLC_83XX_IDC_DEV_COLD
) ||
991 (next
> QLC_83XX_IDC_DEV_QUISCENT
)) {
992 dev_err(&adapter
->pdev
->dev
,
993 "%s: curr %d, prev %d, next state %d is invalid\n",
994 __func__
, cur
, prev
, state
);
998 if ((cur
== QLC_83XX_IDC_DEV_UNKNOWN
) &&
999 (prev
== QLC_83XX_IDC_DEV_UNKNOWN
)) {
1000 if ((next
!= QLC_83XX_IDC_DEV_COLD
) &&
1001 (next
!= QLC_83XX_IDC_DEV_READY
)) {
1002 dev_err(&adapter
->pdev
->dev
,
1003 "%s: failed, cur %d prev %d next %d\n",
1004 __func__
, cur
, prev
, next
);
1009 if (next
== QLC_83XX_IDC_DEV_INIT
) {
1010 if ((prev
!= QLC_83XX_IDC_DEV_INIT
) &&
1011 (prev
!= QLC_83XX_IDC_DEV_COLD
) &&
1012 (prev
!= QLC_83XX_IDC_DEV_NEED_RESET
)) {
1013 dev_err(&adapter
->pdev
->dev
,
1014 "%s: failed, cur %d prev %d next %d\n",
1015 __func__
, cur
, prev
, next
);
1023 #ifdef CONFIG_QLCNIC_VXLAN
1024 #define QLC_83XX_ENCAP_TYPE_VXLAN BIT_1
1025 #define QLC_83XX_MATCH_ENCAP_ID BIT_2
1026 #define QLC_83XX_SET_VXLAN_UDP_DPORT BIT_3
1027 #define QLC_83XX_VXLAN_UDP_DPORT(PORT) ((PORT & 0xffff) << 16)
1029 #define QLCNIC_ENABLE_INGRESS_ENCAP_PARSING 1
1030 #define QLCNIC_DISABLE_INGRESS_ENCAP_PARSING 0
1032 static int qlcnic_set_vxlan_port(struct qlcnic_adapter
*adapter
)
1034 u16 port
= adapter
->ahw
->vxlan_port
;
1035 struct qlcnic_cmd_args cmd
;
1038 memset(&cmd
, 0, sizeof(cmd
));
1040 ret
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1041 QLCNIC_CMD_INIT_NIC_FUNC
);
1045 cmd
.req
.arg
[1] = QLC_83XX_MULTI_TENANCY_INFO
;
1046 cmd
.req
.arg
[2] = QLC_83XX_ENCAP_TYPE_VXLAN
|
1047 QLC_83XX_SET_VXLAN_UDP_DPORT
|
1048 QLC_83XX_VXLAN_UDP_DPORT(port
);
1050 ret
= qlcnic_issue_cmd(adapter
, &cmd
);
1052 netdev_err(adapter
->netdev
,
1053 "Failed to set VXLAN port %d in adapter\n",
1056 qlcnic_free_mbx_args(&cmd
);
1061 static int qlcnic_set_vxlan_parsing(struct qlcnic_adapter
*adapter
,
1064 u16 vxlan_port
= adapter
->ahw
->vxlan_port
;
1065 struct qlcnic_cmd_args cmd
;
1068 memset(&cmd
, 0, sizeof(cmd
));
1070 ret
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
1071 QLCNIC_CMD_SET_INGRESS_ENCAP
);
1075 cmd
.req
.arg
[1] = state
? QLCNIC_ENABLE_INGRESS_ENCAP_PARSING
:
1076 QLCNIC_DISABLE_INGRESS_ENCAP_PARSING
;
1078 ret
= qlcnic_issue_cmd(adapter
, &cmd
);
1080 netdev_err(adapter
->netdev
,
1081 "Failed to %s VXLAN parsing for port %d\n",
1082 state
? "enable" : "disable", vxlan_port
);
1084 netdev_info(adapter
->netdev
,
1085 "%s VXLAN parsing for port %d\n",
1086 state
? "Enabled" : "Disabled", vxlan_port
);
1088 qlcnic_free_mbx_args(&cmd
);
1094 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter
*adapter
)
1096 if (adapter
->fhash
.fnum
)
1097 qlcnic_prune_lb_filters(adapter
);
1099 #ifdef CONFIG_QLCNIC_VXLAN
1100 if (adapter
->flags
& QLCNIC_ADD_VXLAN_PORT
) {
1101 if (qlcnic_set_vxlan_port(adapter
))
1104 if (qlcnic_set_vxlan_parsing(adapter
, true))
1107 adapter
->flags
&= ~QLCNIC_ADD_VXLAN_PORT
;
1108 } else if (adapter
->flags
& QLCNIC_DEL_VXLAN_PORT
) {
1109 if (qlcnic_set_vxlan_parsing(adapter
, false))
1112 adapter
->ahw
->vxlan_port
= 0;
1113 adapter
->flags
&= ~QLCNIC_DEL_VXLAN_PORT
;
1119 * qlcnic_83xx_idc_poll_dev_state
1121 * @work: kernel work queue structure used to schedule the function
1123 * Poll device state periodically and perform state specific
1124 * actions defined by Inter Driver Communication (IDC) protocol.
1129 void qlcnic_83xx_idc_poll_dev_state(struct work_struct
*work
)
1131 struct qlcnic_adapter
*adapter
;
1134 adapter
= container_of(work
, struct qlcnic_adapter
, fw_work
.work
);
1135 state
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
);
1137 if (qlcnic_83xx_idc_check_state_validity(adapter
, state
)) {
1138 qlcnic_83xx_idc_log_state_history(adapter
);
1139 adapter
->ahw
->idc
.curr_state
= QLC_83XX_IDC_DEV_UNKNOWN
;
1141 adapter
->ahw
->idc
.curr_state
= state
;
1144 switch (adapter
->ahw
->idc
.curr_state
) {
1145 case QLC_83XX_IDC_DEV_READY
:
1146 qlcnic_83xx_idc_ready_state(adapter
);
1148 case QLC_83XX_IDC_DEV_NEED_RESET
:
1149 qlcnic_83xx_idc_need_reset_state(adapter
);
1151 case QLC_83XX_IDC_DEV_NEED_QUISCENT
:
1152 qlcnic_83xx_idc_need_quiesce_state(adapter
);
1154 case QLC_83XX_IDC_DEV_FAILED
:
1155 qlcnic_83xx_idc_failed_state(adapter
);
1157 case QLC_83XX_IDC_DEV_INIT
:
1158 qlcnic_83xx_idc_init_state(adapter
);
1160 case QLC_83XX_IDC_DEV_QUISCENT
:
1161 qlcnic_83xx_idc_quiesce_state(adapter
);
1164 qlcnic_83xx_idc_unknown_state(adapter
);
1167 adapter
->ahw
->idc
.prev_state
= adapter
->ahw
->idc
.curr_state
;
1168 qlcnic_83xx_periodic_tasks(adapter
);
1170 /* Re-schedule the function */
1171 if (test_bit(QLC_83XX_MODULE_LOADED
, &adapter
->ahw
->idc
.status
))
1172 qlcnic_schedule_work(adapter
, qlcnic_83xx_idc_poll_dev_state
,
1173 adapter
->ahw
->idc
.delay
);
1176 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter
*adapter
)
1178 u32 idc_params
, val
;
1180 if (qlcnic_83xx_flash_read32(adapter
, QLC_83XX_IDC_FLASH_PARAM_ADDR
,
1181 (u8
*)&idc_params
, 1)) {
1182 dev_info(&adapter
->pdev
->dev
,
1183 "%s:failed to get IDC params from flash\n", __func__
);
1184 adapter
->dev_init_timeo
= QLC_83XX_IDC_INIT_TIMEOUT_SECS
;
1185 adapter
->reset_ack_timeo
= QLC_83XX_IDC_RESET_TIMEOUT_SECS
;
1187 adapter
->dev_init_timeo
= idc_params
& 0xFFFF;
1188 adapter
->reset_ack_timeo
= ((idc_params
>> 16) & 0xFFFF);
1191 adapter
->ahw
->idc
.curr_state
= QLC_83XX_IDC_DEV_UNKNOWN
;
1192 adapter
->ahw
->idc
.prev_state
= QLC_83XX_IDC_DEV_UNKNOWN
;
1193 adapter
->ahw
->idc
.delay
= QLC_83XX_IDC_FW_POLL_DELAY
;
1194 adapter
->ahw
->idc
.err_code
= 0;
1195 adapter
->ahw
->idc
.collect_dump
= 0;
1196 adapter
->ahw
->idc
.name
= (char **)qlc_83xx_idc_states
;
1198 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
1199 set_bit(QLC_83XX_MODULE_LOADED
, &adapter
->ahw
->idc
.status
);
1201 /* Check if reset recovery is disabled */
1202 if (!qlcnic_auto_fw_reset
) {
1203 /* Propagate do not reset request to other functions */
1204 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
1205 val
= val
| QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY
;
1206 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_CTRL
, val
);
1211 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter
*adapter
)
1215 if (qlcnic_83xx_lock_driver(adapter
))
1218 /* Clear driver lock register */
1219 QLCWRX(adapter
->ahw
, QLC_83XX_RECOVER_DRV_LOCK
, 0);
1220 if (qlcnic_83xx_idc_update_major_version(adapter
, 0)) {
1221 qlcnic_83xx_unlock_driver(adapter
);
1225 state
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
);
1226 if (qlcnic_83xx_idc_check_state_validity(adapter
, state
)) {
1227 qlcnic_83xx_unlock_driver(adapter
);
1231 if (state
!= QLC_83XX_IDC_DEV_COLD
&& qlcnic_load_fw_file
) {
1232 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DEV_STATE
,
1233 QLC_83XX_IDC_DEV_COLD
);
1234 state
= QLC_83XX_IDC_DEV_COLD
;
1237 adapter
->ahw
->idc
.curr_state
= state
;
1238 /* First to load function should cold boot the device */
1239 if (state
== QLC_83XX_IDC_DEV_COLD
)
1240 qlcnic_83xx_idc_cold_state_handler(adapter
);
1242 /* Check if reset recovery is enabled */
1243 if (qlcnic_auto_fw_reset
) {
1244 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
1245 val
= val
& ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY
;
1246 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_CTRL
, val
);
1249 qlcnic_83xx_unlock_driver(adapter
);
1254 int qlcnic_83xx_idc_init(struct qlcnic_adapter
*adapter
)
1258 qlcnic_83xx_setup_idc_parameters(adapter
);
1260 if (qlcnic_83xx_get_reset_instruction_template(adapter
))
1263 if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter
)) {
1264 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter
))
1267 if (qlcnic_83xx_idc_check_major_version(adapter
))
1271 qlcnic_83xx_idc_update_audit_reg(adapter
, 0, 1);
1276 void qlcnic_83xx_idc_exit(struct qlcnic_adapter
*adapter
)
1281 while (test_and_set_bit(__QLCNIC_RESETTING
, &adapter
->state
))
1282 usleep_range(10000, 11000);
1284 id
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
1287 if (id
== adapter
->portnum
) {
1288 dev_err(&adapter
->pdev
->dev
,
1289 "%s: wait for lock recovery.. %d\n", __func__
, id
);
1291 id
= QLCRDX(adapter
->ahw
, QLC_83XX_DRV_LOCK_ID
);
1295 /* Clear driver presence bit */
1296 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
);
1297 val
= val
& ~(1 << adapter
->portnum
);
1298 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
, val
);
1299 clear_bit(QLC_83XX_MODULE_LOADED
, &adapter
->ahw
->idc
.status
);
1300 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
1302 cancel_delayed_work_sync(&adapter
->fw_work
);
1305 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter
*adapter
, u32 key
)
1309 if (qlcnic_sriov_vf_check(adapter
))
1312 if (qlcnic_83xx_lock_driver(adapter
)) {
1313 dev_err(&adapter
->pdev
->dev
,
1314 "%s:failed, please retry\n", __func__
);
1318 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
1319 if (val
& QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY
) {
1320 netdev_info(adapter
->netdev
, "%s: Auto firmware recovery is disabled\n",
1322 qlcnic_83xx_idc_enter_failed_state(adapter
, 0);
1323 qlcnic_83xx_unlock_driver(adapter
);
1327 if (key
== QLCNIC_FORCE_FW_RESET
) {
1328 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
1329 val
= val
| QLC_83XX_IDC_GRACEFULL_RESET
;
1330 QLCWRX(adapter
->ahw
, QLC_83XX_IDC_CTRL
, val
);
1331 } else if (key
== QLCNIC_FORCE_FW_DUMP_KEY
) {
1332 adapter
->ahw
->idc
.collect_dump
= 1;
1335 qlcnic_83xx_unlock_driver(adapter
);
1339 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter
*adapter
)
1346 src
= QLC_83XX_BOOTLOADER_FLASH_ADDR
;
1347 dest
= QLCRDX(adapter
->ahw
, QLCNIC_BOOTLOADER_ADDR
);
1348 size
= QLCRDX(adapter
->ahw
, QLCNIC_BOOTLOADER_SIZE
);
1350 /* alignment check */
1352 size
= (size
+ 16) & ~0xF;
1354 p_cache
= vzalloc(size
);
1355 if (p_cache
== NULL
)
1358 ret
= qlcnic_83xx_lockless_flash_read32(adapter
, src
, p_cache
,
1359 size
/ sizeof(u32
));
1364 /* 16 byte write to MS memory */
1365 ret
= qlcnic_ms_mem_write128(adapter
, dest
, (u32
*)p_cache
,
1376 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter
*adapter
)
1378 struct qlc_83xx_fw_info
*fw_info
= adapter
->ahw
->fw_info
;
1379 const struct firmware
*fw
= fw_info
->fw
;
1380 u32 dest
, *p_cache
, *temp
;
1387 temp
= kzalloc(fw
->size
, GFP_KERNEL
);
1389 release_firmware(fw
);
1394 temp_le
= (__le32
*)fw
->data
;
1396 /* FW image in file is in little endian, swap the data to nullify
1397 * the effect of writel() operation on big endian platform.
1399 for (i
= 0; i
< fw
->size
/ sizeof(u32
); i
++)
1400 temp
[i
] = __le32_to_cpu(temp_le
[i
]);
1402 dest
= QLCRDX(adapter
->ahw
, QLCNIC_FW_IMAGE_ADDR
);
1403 size
= (fw
->size
& ~0xF);
1407 ret
= qlcnic_ms_mem_write128(adapter
, addr
,
1408 p_cache
, size
/ 16);
1410 dev_err(&adapter
->pdev
->dev
, "MS memory write failed\n");
1414 /* alignment check */
1415 if (fw
->size
& 0xF) {
1417 for (i
= 0; i
< (fw
->size
& 0xF); i
++)
1418 data
[i
] = ((u8
*)temp
)[size
+ i
];
1421 ret
= qlcnic_ms_mem_write128(adapter
, addr
,
1424 dev_err(&adapter
->pdev
->dev
,
1425 "MS memory write failed\n");
1431 release_firmware(fw
);
1438 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter
*adapter
)
1441 u32 val
= 0, val1
= 0, reg
= 0;
1444 val
= QLCRD32(adapter
, QLC_83XX_SRE_SHIM_REG
, &err
);
1447 dev_info(&adapter
->pdev
->dev
, "SRE-Shim Ctrl:0x%x\n", val
);
1449 for (j
= 0; j
< 2; j
++) {
1451 dev_info(&adapter
->pdev
->dev
,
1452 "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1453 reg
= QLC_83XX_PORT0_THRESHOLD
;
1454 } else if (j
== 1) {
1455 dev_info(&adapter
->pdev
->dev
,
1456 "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1457 reg
= QLC_83XX_PORT1_THRESHOLD
;
1459 for (i
= 0; i
< 8; i
++) {
1460 val
= QLCRD32(adapter
, reg
+ (i
* 0x4), &err
);
1463 dev_info(&adapter
->pdev
->dev
, "0x%x ", val
);
1465 dev_info(&adapter
->pdev
->dev
, "\n");
1468 for (j
= 0; j
< 2; j
++) {
1470 dev_info(&adapter
->pdev
->dev
,
1471 "Port 0 RxB TC Max Cell Registers[4..1]:");
1472 reg
= QLC_83XX_PORT0_TC_MC_REG
;
1473 } else if (j
== 1) {
1474 dev_info(&adapter
->pdev
->dev
,
1475 "Port 1 RxB TC Max Cell Registers[4..1]:");
1476 reg
= QLC_83XX_PORT1_TC_MC_REG
;
1478 for (i
= 0; i
< 4; i
++) {
1479 val
= QLCRD32(adapter
, reg
+ (i
* 0x4), &err
);
1482 dev_info(&adapter
->pdev
->dev
, "0x%x ", val
);
1484 dev_info(&adapter
->pdev
->dev
, "\n");
1487 for (j
= 0; j
< 2; j
++) {
1489 dev_info(&adapter
->pdev
->dev
,
1490 "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1491 reg
= QLC_83XX_PORT0_TC_STATS
;
1492 } else if (j
== 1) {
1493 dev_info(&adapter
->pdev
->dev
,
1494 "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1495 reg
= QLC_83XX_PORT1_TC_STATS
;
1497 for (i
= 7; i
>= 0; i
--) {
1498 val
= QLCRD32(adapter
, reg
, &err
);
1501 val
&= ~(0x7 << 29); /* Reset bits 29 to 31 */
1502 QLCWR32(adapter
, reg
, (val
| (i
<< 29)));
1503 val
= QLCRD32(adapter
, reg
, &err
);
1506 dev_info(&adapter
->pdev
->dev
, "0x%x ", val
);
1508 dev_info(&adapter
->pdev
->dev
, "\n");
1511 val
= QLCRD32(adapter
, QLC_83XX_PORT2_IFB_THRESHOLD
, &err
);
1514 val1
= QLCRD32(adapter
, QLC_83XX_PORT3_IFB_THRESHOLD
, &err
);
1517 dev_info(&adapter
->pdev
->dev
,
1518 "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1523 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter
*adapter
)
1527 if (qlcnic_83xx_lock_driver(adapter
)) {
1528 dev_err(&adapter
->pdev
->dev
,
1529 "%s:failed to acquire driver lock\n", __func__
);
1533 qlcnic_83xx_dump_pause_control_regs(adapter
);
1534 QLCWR32(adapter
, QLC_83XX_SRE_SHIM_REG
, 0x0);
1536 for (j
= 0; j
< 2; j
++) {
1538 reg
= QLC_83XX_PORT0_THRESHOLD
;
1540 reg
= QLC_83XX_PORT1_THRESHOLD
;
1542 for (i
= 0; i
< 8; i
++)
1543 QLCWR32(adapter
, reg
+ (i
* 0x4), 0x0);
1546 for (j
= 0; j
< 2; j
++) {
1548 reg
= QLC_83XX_PORT0_TC_MC_REG
;
1550 reg
= QLC_83XX_PORT1_TC_MC_REG
;
1552 for (i
= 0; i
< 4; i
++)
1553 QLCWR32(adapter
, reg
+ (i
* 0x4), 0x03FF03FF);
1556 QLCWR32(adapter
, QLC_83XX_PORT2_IFB_THRESHOLD
, 0);
1557 QLCWR32(adapter
, QLC_83XX_PORT3_IFB_THRESHOLD
, 0);
1558 dev_info(&adapter
->pdev
->dev
,
1559 "Disabled pause frames successfully on all ports\n");
1560 qlcnic_83xx_unlock_driver(adapter
);
1563 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter
*adapter
)
1565 QLCWR32(adapter
, QLC_83XX_RESET_REG
, 0);
1566 QLCWR32(adapter
, QLC_83XX_RESET_PORT0
, 0);
1567 QLCWR32(adapter
, QLC_83XX_RESET_PORT1
, 0);
1568 QLCWR32(adapter
, QLC_83XX_RESET_PORT2
, 0);
1569 QLCWR32(adapter
, QLC_83XX_RESET_PORT3
, 0);
1570 QLCWR32(adapter
, QLC_83XX_RESET_SRESHIM
, 0);
1571 QLCWR32(adapter
, QLC_83XX_RESET_EPGSHIM
, 0);
1572 QLCWR32(adapter
, QLC_83XX_RESET_ETHERPCS
, 0);
1573 QLCWR32(adapter
, QLC_83XX_RESET_CONTROL
, 1);
1576 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter
*p_dev
)
1578 u32 heartbeat
, peg_status
;
1579 int retries
, ret
= -EIO
, err
= 0;
1581 retries
= QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT
;
1582 p_dev
->heartbeat
= QLC_SHARED_REG_RD32(p_dev
,
1583 QLCNIC_PEG_ALIVE_COUNTER
);
1586 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS
);
1587 heartbeat
= QLC_SHARED_REG_RD32(p_dev
,
1588 QLCNIC_PEG_ALIVE_COUNTER
);
1589 if (heartbeat
!= p_dev
->heartbeat
) {
1590 ret
= QLCNIC_RCODE_SUCCESS
;
1593 } while (--retries
);
1596 dev_err(&p_dev
->pdev
->dev
, "firmware hang detected\n");
1597 qlcnic_83xx_take_eport_out_of_reset(p_dev
);
1598 qlcnic_83xx_disable_pause_frames(p_dev
);
1599 peg_status
= QLC_SHARED_REG_RD32(p_dev
,
1600 QLCNIC_PEG_HALT_STATUS1
);
1601 dev_info(&p_dev
->pdev
->dev
, "Dumping HW/FW registers\n"
1602 "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1603 "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1604 "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1605 "PEG_NET_4_PC: 0x%x\n", peg_status
,
1606 QLC_SHARED_REG_RD32(p_dev
, QLCNIC_PEG_HALT_STATUS2
),
1607 QLCRD32(p_dev
, QLC_83XX_CRB_PEG_NET_0
, &err
),
1608 QLCRD32(p_dev
, QLC_83XX_CRB_PEG_NET_1
, &err
),
1609 QLCRD32(p_dev
, QLC_83XX_CRB_PEG_NET_2
, &err
),
1610 QLCRD32(p_dev
, QLC_83XX_CRB_PEG_NET_3
, &err
),
1611 QLCRD32(p_dev
, QLC_83XX_CRB_PEG_NET_4
, &err
));
1613 if (QLCNIC_FWERROR_CODE(peg_status
) == 0x67)
1614 dev_err(&p_dev
->pdev
->dev
,
1615 "Device is being reset err code 0x00006700.\n");
1621 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter
*p_dev
)
1623 int retries
= QLCNIC_CMDPEG_CHECK_RETRY_COUNT
;
1627 val
= QLC_SHARED_REG_RD32(p_dev
, QLCNIC_CMDPEG_STATE
);
1628 if (val
== QLC_83XX_CMDPEG_COMPLETE
)
1630 msleep(QLCNIC_CMDPEG_CHECK_DELAY
);
1631 } while (--retries
);
1633 dev_err(&p_dev
->pdev
->dev
, "%s: failed, state = 0x%x\n", __func__
, val
);
1637 static int qlcnic_83xx_check_hw_status(struct qlcnic_adapter
*p_dev
)
1641 err
= qlcnic_83xx_check_cmd_peg_status(p_dev
);
1645 err
= qlcnic_83xx_check_heartbeat(p_dev
);
1652 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter
*p_dev
, u32 addr
,
1653 int duration
, u32 mask
, u32 status
)
1655 int timeout_error
, err
= 0;
1659 value
= QLCRD32(p_dev
, addr
, &err
);
1662 retries
= duration
/ 10;
1665 if ((value
& mask
) != status
) {
1667 msleep(duration
/ 10);
1668 value
= QLCRD32(p_dev
, addr
, &err
);
1675 } while (retries
--);
1677 if (timeout_error
) {
1678 p_dev
->ahw
->reset
.seq_error
++;
1679 dev_err(&p_dev
->pdev
->dev
,
1680 "%s: Timeout Err, entry_num = %d\n",
1681 __func__
, p_dev
->ahw
->reset
.seq_index
);
1682 dev_err(&p_dev
->pdev
->dev
,
1683 "0x%08x 0x%08x 0x%08x\n",
1684 value
, mask
, status
);
1687 return timeout_error
;
1690 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter
*p_dev
)
1693 u16
*buff
= (u16
*)p_dev
->ahw
->reset
.buff
;
1694 int count
= p_dev
->ahw
->reset
.hdr
->size
/ sizeof(u16
);
1700 sum
= (sum
& 0xFFFF) + (sum
>> 16);
1705 dev_err(&p_dev
->pdev
->dev
, "%s: failed\n", __func__
);
1710 static int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter
*p_dev
)
1712 struct qlcnic_hardware_context
*ahw
= p_dev
->ahw
;
1713 u32 addr
, count
, prev_ver
, curr_ver
;
1716 if (ahw
->reset
.buff
!= NULL
) {
1717 prev_ver
= p_dev
->fw_version
;
1718 curr_ver
= qlcnic_83xx_get_fw_version(p_dev
);
1719 if (curr_ver
> prev_ver
)
1720 kfree(ahw
->reset
.buff
);
1725 ahw
->reset
.seq_error
= 0;
1726 ahw
->reset
.buff
= kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE
, GFP_KERNEL
);
1727 if (p_dev
->ahw
->reset
.buff
== NULL
)
1730 p_buff
= p_dev
->ahw
->reset
.buff
;
1731 addr
= QLC_83XX_RESET_TEMPLATE_ADDR
;
1732 count
= sizeof(struct qlc_83xx_reset_hdr
) / sizeof(u32
);
1734 /* Copy template header from flash */
1735 if (qlcnic_83xx_flash_read32(p_dev
, addr
, p_buff
, count
)) {
1736 dev_err(&p_dev
->pdev
->dev
, "%s: flash read failed\n", __func__
);
1739 ahw
->reset
.hdr
= (struct qlc_83xx_reset_hdr
*)ahw
->reset
.buff
;
1740 addr
= QLC_83XX_RESET_TEMPLATE_ADDR
+ ahw
->reset
.hdr
->hdr_size
;
1741 p_buff
= ahw
->reset
.buff
+ ahw
->reset
.hdr
->hdr_size
;
1742 count
= (ahw
->reset
.hdr
->size
- ahw
->reset
.hdr
->hdr_size
) / sizeof(u32
);
1744 /* Copy rest of the template */
1745 if (qlcnic_83xx_flash_read32(p_dev
, addr
, p_buff
, count
)) {
1746 dev_err(&p_dev
->pdev
->dev
, "%s: flash read failed\n", __func__
);
1750 if (qlcnic_83xx_reset_template_checksum(p_dev
))
1752 /* Get Stop, Start and Init command offsets */
1753 ahw
->reset
.init_offset
= ahw
->reset
.buff
+ ahw
->reset
.hdr
->init_offset
;
1754 ahw
->reset
.start_offset
= ahw
->reset
.buff
+
1755 ahw
->reset
.hdr
->start_offset
;
1756 ahw
->reset
.stop_offset
= ahw
->reset
.buff
+ ahw
->reset
.hdr
->hdr_size
;
1760 /* Read Write HW register command */
1761 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter
*p_dev
,
1762 u32 raddr
, u32 waddr
)
1767 value
= QLCRD32(p_dev
, raddr
, &err
);
1770 qlcnic_83xx_wrt_reg_indirect(p_dev
, waddr
, value
);
1773 /* Read Modify Write HW register command */
1774 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter
*p_dev
,
1775 u32 raddr
, u32 waddr
,
1776 struct qlc_83xx_rmw
*p_rmw_hdr
)
1781 if (p_rmw_hdr
->index_a
) {
1782 value
= p_dev
->ahw
->reset
.array
[p_rmw_hdr
->index_a
];
1784 value
= QLCRD32(p_dev
, raddr
, &err
);
1789 value
&= p_rmw_hdr
->mask
;
1790 value
<<= p_rmw_hdr
->shl
;
1791 value
>>= p_rmw_hdr
->shr
;
1792 value
|= p_rmw_hdr
->or_value
;
1793 value
^= p_rmw_hdr
->xor_value
;
1794 qlcnic_83xx_wrt_reg_indirect(p_dev
, waddr
, value
);
1797 /* Write HW register command */
1798 static void qlcnic_83xx_write_list(struct qlcnic_adapter
*p_dev
,
1799 struct qlc_83xx_entry_hdr
*p_hdr
)
1802 struct qlc_83xx_entry
*entry
;
1804 entry
= (struct qlc_83xx_entry
*)((char *)p_hdr
+
1805 sizeof(struct qlc_83xx_entry_hdr
));
1807 for (i
= 0; i
< p_hdr
->count
; i
++, entry
++) {
1808 qlcnic_83xx_wrt_reg_indirect(p_dev
, entry
->arg1
,
1811 udelay((u32
)(p_hdr
->delay
));
1815 /* Read and Write instruction */
1816 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter
*p_dev
,
1817 struct qlc_83xx_entry_hdr
*p_hdr
)
1820 struct qlc_83xx_entry
*entry
;
1822 entry
= (struct qlc_83xx_entry
*)((char *)p_hdr
+
1823 sizeof(struct qlc_83xx_entry_hdr
));
1825 for (i
= 0; i
< p_hdr
->count
; i
++, entry
++) {
1826 qlcnic_83xx_read_write_crb_reg(p_dev
, entry
->arg1
,
1829 udelay((u32
)(p_hdr
->delay
));
1833 /* Poll HW register command */
1834 static void qlcnic_83xx_poll_list(struct qlcnic_adapter
*p_dev
,
1835 struct qlc_83xx_entry_hdr
*p_hdr
)
1838 struct qlc_83xx_entry
*entry
;
1839 struct qlc_83xx_poll
*poll
;
1841 unsigned long arg1
, arg2
;
1843 poll
= (struct qlc_83xx_poll
*)((char *)p_hdr
+
1844 sizeof(struct qlc_83xx_entry_hdr
));
1846 entry
= (struct qlc_83xx_entry
*)((char *)poll
+
1847 sizeof(struct qlc_83xx_poll
));
1848 delay
= (long)p_hdr
->delay
;
1851 for (i
= 0; i
< p_hdr
->count
; i
++, entry
++)
1852 qlcnic_83xx_poll_reg(p_dev
, entry
->arg1
,
1856 for (i
= 0; i
< p_hdr
->count
; i
++, entry
++) {
1860 if (qlcnic_83xx_poll_reg(p_dev
,
1864 QLCRD32(p_dev
, arg1
, &err
);
1867 QLCRD32(p_dev
, arg2
, &err
);
1876 /* Poll and write HW register command */
1877 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter
*p_dev
,
1878 struct qlc_83xx_entry_hdr
*p_hdr
)
1882 struct qlc_83xx_quad_entry
*entry
;
1883 struct qlc_83xx_poll
*poll
;
1885 poll
= (struct qlc_83xx_poll
*)((char *)p_hdr
+
1886 sizeof(struct qlc_83xx_entry_hdr
));
1887 entry
= (struct qlc_83xx_quad_entry
*)((char *)poll
+
1888 sizeof(struct qlc_83xx_poll
));
1889 delay
= (long)p_hdr
->delay
;
1891 for (i
= 0; i
< p_hdr
->count
; i
++, entry
++) {
1892 qlcnic_83xx_wrt_reg_indirect(p_dev
, entry
->dr_addr
,
1894 qlcnic_83xx_wrt_reg_indirect(p_dev
, entry
->ar_addr
,
1897 qlcnic_83xx_poll_reg(p_dev
, entry
->ar_addr
, delay
,
1898 poll
->mask
, poll
->status
);
1902 /* Read Modify Write register command */
1903 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter
*p_dev
,
1904 struct qlc_83xx_entry_hdr
*p_hdr
)
1907 struct qlc_83xx_entry
*entry
;
1908 struct qlc_83xx_rmw
*rmw_hdr
;
1910 rmw_hdr
= (struct qlc_83xx_rmw
*)((char *)p_hdr
+
1911 sizeof(struct qlc_83xx_entry_hdr
));
1913 entry
= (struct qlc_83xx_entry
*)((char *)rmw_hdr
+
1914 sizeof(struct qlc_83xx_rmw
));
1916 for (i
= 0; i
< p_hdr
->count
; i
++, entry
++) {
1917 qlcnic_83xx_rmw_crb_reg(p_dev
, entry
->arg1
,
1918 entry
->arg2
, rmw_hdr
);
1920 udelay((u32
)(p_hdr
->delay
));
1924 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr
*p_hdr
)
1927 mdelay((u32
)((long)p_hdr
->delay
));
1930 /* Read and poll register command */
1931 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter
*p_dev
,
1932 struct qlc_83xx_entry_hdr
*p_hdr
)
1935 int index
, i
, j
, err
;
1936 struct qlc_83xx_quad_entry
*entry
;
1937 struct qlc_83xx_poll
*poll
;
1940 poll
= (struct qlc_83xx_poll
*)((char *)p_hdr
+
1941 sizeof(struct qlc_83xx_entry_hdr
));
1943 entry
= (struct qlc_83xx_quad_entry
*)((char *)poll
+
1944 sizeof(struct qlc_83xx_poll
));
1945 delay
= (long)p_hdr
->delay
;
1947 for (i
= 0; i
< p_hdr
->count
; i
++, entry
++) {
1948 qlcnic_83xx_wrt_reg_indirect(p_dev
, entry
->ar_addr
,
1951 if (!qlcnic_83xx_poll_reg(p_dev
, entry
->ar_addr
, delay
,
1952 poll
->mask
, poll
->status
)){
1953 index
= p_dev
->ahw
->reset
.array_index
;
1954 addr
= entry
->dr_addr
;
1955 j
= QLCRD32(p_dev
, addr
, &err
);
1959 p_dev
->ahw
->reset
.array
[index
++] = j
;
1961 if (index
== QLC_83XX_MAX_RESET_SEQ_ENTRIES
)
1962 p_dev
->ahw
->reset
.array_index
= 1;
1968 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter
*p_dev
)
1970 p_dev
->ahw
->reset
.seq_end
= 1;
1973 static void qlcnic_83xx_template_end(struct qlcnic_adapter
*p_dev
)
1975 p_dev
->ahw
->reset
.template_end
= 1;
1976 if (p_dev
->ahw
->reset
.seq_error
== 0)
1977 dev_err(&p_dev
->pdev
->dev
,
1978 "HW restart process completed successfully.\n");
1980 dev_err(&p_dev
->pdev
->dev
,
1981 "HW restart completed with timeout errors.\n");
1985 * qlcnic_83xx_exec_template_cmd
1987 * @p_dev: adapter structure
1988 * @p_buff: Poiter to instruction template
1990 * Template provides instructions to stop, restart and initalize firmware.
1991 * These instructions are abstracted as a series of read, write and
1992 * poll operations on hardware registers. Register information and operation
1993 * specifics are not exposed to the driver. Driver reads the template from
1994 * flash and executes the instructions located at pre-defined offsets.
1998 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter
*p_dev
,
2002 struct qlc_83xx_entry_hdr
*p_hdr
;
2003 char *entry
= p_buff
;
2005 p_dev
->ahw
->reset
.seq_end
= 0;
2006 p_dev
->ahw
->reset
.template_end
= 0;
2007 entries
= p_dev
->ahw
->reset
.hdr
->entries
;
2008 index
= p_dev
->ahw
->reset
.seq_index
;
2010 for (; (!p_dev
->ahw
->reset
.seq_end
) && (index
< entries
); index
++) {
2011 p_hdr
= (struct qlc_83xx_entry_hdr
*)entry
;
2013 switch (p_hdr
->cmd
) {
2014 case QLC_83XX_OPCODE_NOP
:
2016 case QLC_83XX_OPCODE_WRITE_LIST
:
2017 qlcnic_83xx_write_list(p_dev
, p_hdr
);
2019 case QLC_83XX_OPCODE_READ_WRITE_LIST
:
2020 qlcnic_83xx_read_write_list(p_dev
, p_hdr
);
2022 case QLC_83XX_OPCODE_POLL_LIST
:
2023 qlcnic_83xx_poll_list(p_dev
, p_hdr
);
2025 case QLC_83XX_OPCODE_POLL_WRITE_LIST
:
2026 qlcnic_83xx_poll_write_list(p_dev
, p_hdr
);
2028 case QLC_83XX_OPCODE_READ_MODIFY_WRITE
:
2029 qlcnic_83xx_read_modify_write(p_dev
, p_hdr
);
2031 case QLC_83XX_OPCODE_SEQ_PAUSE
:
2032 qlcnic_83xx_pause(p_hdr
);
2034 case QLC_83XX_OPCODE_SEQ_END
:
2035 qlcnic_83xx_seq_end(p_dev
);
2037 case QLC_83XX_OPCODE_TMPL_END
:
2038 qlcnic_83xx_template_end(p_dev
);
2040 case QLC_83XX_OPCODE_POLL_READ_LIST
:
2041 qlcnic_83xx_poll_read_list(p_dev
, p_hdr
);
2044 dev_err(&p_dev
->pdev
->dev
,
2045 "%s: Unknown opcode 0x%04x in template %d\n",
2046 __func__
, p_hdr
->cmd
, index
);
2049 entry
+= p_hdr
->size
;
2051 p_dev
->ahw
->reset
.seq_index
= index
;
2054 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter
*p_dev
)
2056 p_dev
->ahw
->reset
.seq_index
= 0;
2058 qlcnic_83xx_exec_template_cmd(p_dev
, p_dev
->ahw
->reset
.stop_offset
);
2059 if (p_dev
->ahw
->reset
.seq_end
!= 1)
2060 dev_err(&p_dev
->pdev
->dev
, "%s: failed\n", __func__
);
2063 static void qlcnic_83xx_start_hw(struct qlcnic_adapter
*p_dev
)
2065 qlcnic_83xx_exec_template_cmd(p_dev
, p_dev
->ahw
->reset
.start_offset
);
2066 if (p_dev
->ahw
->reset
.template_end
!= 1)
2067 dev_err(&p_dev
->pdev
->dev
, "%s: failed\n", __func__
);
2070 static void qlcnic_83xx_init_hw(struct qlcnic_adapter
*p_dev
)
2072 qlcnic_83xx_exec_template_cmd(p_dev
, p_dev
->ahw
->reset
.init_offset
);
2073 if (p_dev
->ahw
->reset
.seq_end
!= 1)
2074 dev_err(&p_dev
->pdev
->dev
, "%s: failed\n", __func__
);
2077 /* POST FW related definations*/
2078 #define QLC_83XX_POST_SIGNATURE_REG 0x41602014
2079 #define QLC_83XX_POST_MODE_REG 0x41602018
2080 #define QLC_83XX_POST_FAST_MODE 0
2081 #define QLC_83XX_POST_MEDIUM_MODE 1
2082 #define QLC_83XX_POST_SLOW_MODE 2
2084 /* POST Timeout values in milliseconds */
2085 #define QLC_83XX_POST_FAST_MODE_TIMEOUT 690
2086 #define QLC_83XX_POST_MED_MODE_TIMEOUT 2930
2087 #define QLC_83XX_POST_SLOW_MODE_TIMEOUT 7500
2089 /* POST result values */
2090 #define QLC_83XX_POST_PASS 0xfffffff0
2091 #define QLC_83XX_POST_ASIC_STRESS_TEST_FAIL 0xffffffff
2092 #define QLC_83XX_POST_DDR_TEST_FAIL 0xfffffffe
2093 #define QLC_83XX_POST_ASIC_MEMORY_TEST_FAIL 0xfffffffc
2094 #define QLC_83XX_POST_FLASH_TEST_FAIL 0xfffffff8
2096 static int qlcnic_83xx_run_post(struct qlcnic_adapter
*adapter
)
2098 struct qlc_83xx_fw_info
*fw_info
= adapter
->ahw
->fw_info
;
2099 struct device
*dev
= &adapter
->pdev
->dev
;
2100 int timeout
, count
, ret
= 0;
2103 /* Set timeout values with extra 2 seconds of buffer */
2104 switch (adapter
->ahw
->post_mode
) {
2105 case QLC_83XX_POST_FAST_MODE
:
2106 timeout
= QLC_83XX_POST_FAST_MODE_TIMEOUT
+ 2000;
2108 case QLC_83XX_POST_MEDIUM_MODE
:
2109 timeout
= QLC_83XX_POST_MED_MODE_TIMEOUT
+ 2000;
2111 case QLC_83XX_POST_SLOW_MODE
:
2112 timeout
= QLC_83XX_POST_SLOW_MODE_TIMEOUT
+ 2000;
2118 strncpy(fw_info
->fw_file_name
, QLC_83XX_POST_FW_FILE_NAME
,
2119 QLC_FW_FILE_NAME_LEN
);
2121 ret
= request_firmware(&fw_info
->fw
, fw_info
->fw_file_name
, dev
);
2123 dev_err(dev
, "POST firmware can not be loaded, skipping POST\n");
2127 ret
= qlcnic_83xx_copy_fw_file(adapter
);
2131 /* clear QLC_83XX_POST_SIGNATURE_REG register */
2132 qlcnic_ind_wr(adapter
, QLC_83XX_POST_SIGNATURE_REG
, 0);
2135 qlcnic_ind_wr(adapter
, QLC_83XX_POST_MODE_REG
,
2136 adapter
->ahw
->post_mode
);
2138 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FW_IMG_VALID
,
2139 QLC_83XX_BOOT_FROM_FILE
);
2141 qlcnic_83xx_start_hw(adapter
);
2148 signature
= qlcnic_ind_rd(adapter
, QLC_83XX_POST_SIGNATURE_REG
);
2149 if (signature
== QLC_83XX_POST_PASS
)
2151 } while (timeout
> count
);
2153 if (timeout
<= count
) {
2154 dev_err(dev
, "POST timed out, signature = 0x%08x\n", signature
);
2158 switch (signature
) {
2159 case QLC_83XX_POST_PASS
:
2160 dev_info(dev
, "POST passed, Signature = 0x%08x\n", signature
);
2162 case QLC_83XX_POST_ASIC_STRESS_TEST_FAIL
:
2163 dev_err(dev
, "POST failed, Test case : ASIC STRESS TEST, Signature = 0x%08x\n",
2167 case QLC_83XX_POST_DDR_TEST_FAIL
:
2168 dev_err(dev
, "POST failed, Test case : DDT TEST, Signature = 0x%08x\n",
2172 case QLC_83XX_POST_ASIC_MEMORY_TEST_FAIL
:
2173 dev_err(dev
, "POST failed, Test case : ASIC MEMORY TEST, Signature = 0x%08x\n",
2177 case QLC_83XX_POST_FLASH_TEST_FAIL
:
2178 dev_err(dev
, "POST failed, Test case : FLASH TEST, Signature = 0x%08x\n",
2183 dev_err(dev
, "POST failed, Test case : INVALID, Signature = 0x%08x\n",
2192 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter
*adapter
)
2194 struct qlc_83xx_fw_info
*fw_info
= adapter
->ahw
->fw_info
;
2197 if (request_firmware(&fw_info
->fw
, fw_info
->fw_file_name
,
2198 &(adapter
->pdev
->dev
))) {
2199 dev_err(&adapter
->pdev
->dev
,
2200 "No file FW image, loading flash FW image.\n");
2201 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FW_IMG_VALID
,
2202 QLC_83XX_BOOT_FROM_FLASH
);
2204 if (qlcnic_83xx_copy_fw_file(adapter
))
2206 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FW_IMG_VALID
,
2207 QLC_83XX_BOOT_FROM_FILE
);
2213 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter
*adapter
)
2218 qlcnic_83xx_stop_hw(adapter
);
2220 /* Collect FW register dump if required */
2221 val
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_CTRL
);
2222 if (!(val
& QLC_83XX_IDC_GRACEFULL_RESET
))
2223 qlcnic_dump_fw(adapter
);
2225 if (val
& QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY
) {
2226 netdev_info(adapter
->netdev
, "%s: Auto firmware recovery is disabled\n",
2228 qlcnic_83xx_idc_enter_failed_state(adapter
, 1);
2232 qlcnic_83xx_init_hw(adapter
);
2234 if (qlcnic_83xx_copy_bootloader(adapter
))
2237 /* Check if POST needs to be run */
2238 if (adapter
->ahw
->run_post
) {
2239 err
= qlcnic_83xx_run_post(adapter
);
2243 /* No need to run POST in next reset sequence */
2244 adapter
->ahw
->run_post
= false;
2246 /* Again reset the adapter to load regular firmware */
2247 qlcnic_83xx_stop_hw(adapter
);
2248 qlcnic_83xx_init_hw(adapter
);
2250 err
= qlcnic_83xx_copy_bootloader(adapter
);
2255 /* Boot either flash image or firmware image from host file system */
2256 if (qlcnic_load_fw_file
== 1) {
2257 if (qlcnic_83xx_load_fw_image_from_host(adapter
))
2260 QLC_SHARED_REG_WR32(adapter
, QLCNIC_FW_IMG_VALID
,
2261 QLC_83XX_BOOT_FROM_FLASH
);
2264 qlcnic_83xx_start_hw(adapter
);
2265 if (qlcnic_83xx_check_hw_status(adapter
))
2271 static int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter
*adapter
)
2274 struct qlcnic_info nic_info
;
2275 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2277 memset(&nic_info
, 0, sizeof(struct qlcnic_info
));
2278 err
= qlcnic_get_nic_info(adapter
, &nic_info
, ahw
->pci_func
);
2282 ahw
->physical_port
= (u8
) nic_info
.phys_port
;
2283 ahw
->switch_mode
= nic_info
.switch_mode
;
2284 ahw
->max_tx_ques
= nic_info
.max_tx_ques
;
2285 ahw
->max_rx_ques
= nic_info
.max_rx_ques
;
2286 ahw
->capabilities
= nic_info
.capabilities
;
2287 ahw
->max_mac_filters
= nic_info
.max_mac_filters
;
2288 ahw
->max_mtu
= nic_info
.max_mtu
;
2290 /* eSwitch capability indicates vNIC mode.
2291 * vNIC and SRIOV are mutually exclusive operational modes.
2292 * If SR-IOV capability is detected, SR-IOV physical function
2293 * will get initialized in default mode.
2294 * SR-IOV virtual function initialization follows a
2295 * different code path and opmode.
2296 * SRIOV mode has precedence over vNIC mode.
2298 if (test_bit(__QLCNIC_SRIOV_CAPABLE
, &adapter
->state
))
2299 return QLC_83XX_DEFAULT_OPMODE
;
2301 if (ahw
->capabilities
& QLC_83XX_ESWITCH_CAPABILITY
)
2302 return QLCNIC_VNIC_MODE
;
2304 return QLC_83XX_DEFAULT_OPMODE
;
2307 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter
*adapter
)
2309 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2310 u16 max_sds_rings
, max_tx_rings
;
2313 ret
= qlcnic_83xx_get_nic_configuration(adapter
);
2317 if (ret
== QLCNIC_VNIC_MODE
) {
2318 ahw
->nic_mode
= QLCNIC_VNIC_MODE
;
2320 if (qlcnic_83xx_config_vnic_opmode(adapter
))
2323 max_sds_rings
= QLCNIC_MAX_VNIC_SDS_RINGS
;
2324 max_tx_rings
= QLCNIC_MAX_VNIC_TX_RINGS
;
2325 } else if (ret
== QLC_83XX_DEFAULT_OPMODE
) {
2326 ahw
->nic_mode
= QLCNIC_DEFAULT_MODE
;
2327 adapter
->nic_ops
->init_driver
= qlcnic_83xx_init_default_driver
;
2328 ahw
->idc
.state_entry
= qlcnic_83xx_idc_ready_state_entry
;
2329 max_sds_rings
= QLCNIC_MAX_SDS_RINGS
;
2330 max_tx_rings
= QLCNIC_MAX_TX_RINGS
;
2332 dev_err(&adapter
->pdev
->dev
, "%s: Invalid opmode %d\n",
2337 adapter
->max_sds_rings
= min(ahw
->max_rx_ques
, max_sds_rings
);
2338 adapter
->max_tx_rings
= min(ahw
->max_tx_ques
, max_tx_rings
);
2343 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter
*adapter
)
2345 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2347 if (ahw
->port_type
== QLCNIC_XGBE
) {
2348 adapter
->num_rxd
= DEFAULT_RCV_DESCRIPTORS_10G
;
2349 adapter
->max_rxd
= MAX_RCV_DESCRIPTORS_10G
;
2350 adapter
->num_jumbo_rxd
= MAX_JUMBO_RCV_DESCRIPTORS_10G
;
2351 adapter
->max_jumbo_rxd
= MAX_JUMBO_RCV_DESCRIPTORS_10G
;
2353 } else if (ahw
->port_type
== QLCNIC_GBE
) {
2354 adapter
->num_rxd
= DEFAULT_RCV_DESCRIPTORS_1G
;
2355 adapter
->num_jumbo_rxd
= MAX_JUMBO_RCV_DESCRIPTORS_1G
;
2356 adapter
->max_jumbo_rxd
= MAX_JUMBO_RCV_DESCRIPTORS_1G
;
2357 adapter
->max_rxd
= MAX_RCV_DESCRIPTORS_1G
;
2359 adapter
->num_txd
= MAX_CMD_DESCRIPTORS
;
2360 adapter
->max_rds_rings
= MAX_RDS_RINGS
;
2363 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter
*adapter
)
2367 qlcnic_83xx_get_minidump_template(adapter
);
2368 if (qlcnic_83xx_get_port_info(adapter
))
2371 qlcnic_83xx_config_buff_descriptors(adapter
);
2372 adapter
->ahw
->msix_supported
= !!qlcnic_use_msi_x
;
2373 adapter
->flags
|= QLCNIC_ADAPTER_INITIALIZED
;
2375 dev_info(&adapter
->pdev
->dev
, "HAL Version: %d\n",
2376 adapter
->ahw
->fw_hal_version
);
2381 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2382 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter
*adapter
)
2384 struct qlcnic_cmd_args cmd
;
2385 u32 presence_mask
, audit_mask
;
2388 presence_mask
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_PRESENCE
);
2389 audit_mask
= QLCRDX(adapter
->ahw
, QLC_83XX_IDC_DRV_AUDIT
);
2391 if (IS_QLC_83XX_USED(adapter
, presence_mask
, audit_mask
)) {
2392 status
= qlcnic_alloc_mbx_args(&cmd
, adapter
,
2393 QLCNIC_CMD_STOP_NIC_FUNC
);
2397 cmd
.req
.arg
[1] = BIT_31
;
2398 status
= qlcnic_issue_cmd(adapter
, &cmd
);
2400 dev_err(&adapter
->pdev
->dev
,
2401 "Failed to clean up the function resources\n");
2402 qlcnic_free_mbx_args(&cmd
);
2406 static int qlcnic_83xx_get_fw_info(struct qlcnic_adapter
*adapter
)
2408 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2409 struct pci_dev
*pdev
= adapter
->pdev
;
2410 struct qlc_83xx_fw_info
*fw_info
;
2413 ahw
->fw_info
= kzalloc(sizeof(*fw_info
), GFP_KERNEL
);
2414 if (!ahw
->fw_info
) {
2417 fw_info
= ahw
->fw_info
;
2418 switch (pdev
->device
) {
2419 case PCI_DEVICE_ID_QLOGIC_QLE834X
:
2420 case PCI_DEVICE_ID_QLOGIC_QLE8830
:
2421 strncpy(fw_info
->fw_file_name
, QLC_83XX_FW_FILE_NAME
,
2422 QLC_FW_FILE_NAME_LEN
);
2424 case PCI_DEVICE_ID_QLOGIC_QLE844X
:
2425 strncpy(fw_info
->fw_file_name
, QLC_84XX_FW_FILE_NAME
,
2426 QLC_FW_FILE_NAME_LEN
);
2429 dev_err(&pdev
->dev
, "%s: Invalid device id\n",
2439 static void qlcnic_83xx_init_rings(struct qlcnic_adapter
*adapter
)
2441 u8 rx_cnt
= QLCNIC_DEF_SDS_RINGS
;
2442 u8 tx_cnt
= QLCNIC_DEF_TX_RINGS
;
2444 adapter
->max_tx_rings
= QLCNIC_MAX_TX_RINGS
;
2445 adapter
->max_sds_rings
= QLCNIC_MAX_SDS_RINGS
;
2447 if (!adapter
->ahw
->msix_supported
) {
2448 rx_cnt
= QLCNIC_SINGLE_RING
;
2449 tx_cnt
= QLCNIC_SINGLE_RING
;
2452 /* compute and set drv sds rings */
2453 qlcnic_set_tx_ring_count(adapter
, tx_cnt
);
2454 qlcnic_set_sds_ring_count(adapter
, rx_cnt
);
2457 int qlcnic_83xx_init(struct qlcnic_adapter
*adapter
, int pci_using_dac
)
2459 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2462 adapter
->rx_mac_learn
= false;
2463 ahw
->msix_supported
= !!qlcnic_use_msi_x
;
2465 /* Check if POST needs to be run */
2466 switch (qlcnic_load_fw_file
) {
2468 ahw
->post_mode
= QLC_83XX_POST_FAST_MODE
;
2469 ahw
->run_post
= true;
2472 ahw
->post_mode
= QLC_83XX_POST_MEDIUM_MODE
;
2473 ahw
->run_post
= true;
2476 ahw
->post_mode
= QLC_83XX_POST_SLOW_MODE
;
2477 ahw
->run_post
= true;
2480 ahw
->run_post
= false;
2484 qlcnic_83xx_init_rings(adapter
);
2486 err
= qlcnic_83xx_init_mailbox_work(adapter
);
2490 if (qlcnic_sriov_vf_check(adapter
)) {
2491 err
= qlcnic_sriov_vf_init(adapter
, pci_using_dac
);
2498 if (qlcnic_83xx_read_flash_descriptor_table(adapter
) ||
2499 qlcnic_83xx_read_flash_mfg_id(adapter
)) {
2500 dev_err(&adapter
->pdev
->dev
, "Failed reading flash mfg id\n");
2501 err
= -ENOTRECOVERABLE
;
2505 err
= qlcnic_83xx_check_hw_status(adapter
);
2509 err
= qlcnic_83xx_get_fw_info(adapter
);
2513 err
= qlcnic_83xx_idc_init(adapter
);
2517 err
= qlcnic_setup_intr(adapter
);
2519 dev_err(&adapter
->pdev
->dev
, "Failed to setup interrupt\n");
2523 INIT_DELAYED_WORK(&adapter
->idc_aen_work
, qlcnic_83xx_idc_aen_work
);
2525 err
= qlcnic_83xx_setup_mbx_intr(adapter
);
2527 goto disable_mbx_intr
;
2529 qlcnic_83xx_clear_function_resources(adapter
);
2530 qlcnic_dcb_enable(adapter
->dcb
);
2531 qlcnic_83xx_initialize_nic(adapter
, 1);
2532 qlcnic_dcb_get_info(adapter
->dcb
);
2534 /* Configure default, SR-IOV or Virtual NIC mode of operation */
2535 err
= qlcnic_83xx_configure_opmode(adapter
);
2537 goto disable_mbx_intr
;
2540 /* Perform operating mode specific initialization */
2541 err
= adapter
->nic_ops
->init_driver(adapter
);
2543 goto disable_mbx_intr
;
2545 /* Periodically monitor device status */
2546 qlcnic_83xx_idc_poll_dev_state(&adapter
->fw_work
.work
);
2550 qlcnic_83xx_free_mbx_intr(adapter
);
2553 qlcnic_teardown_intr(adapter
);
2556 qlcnic_83xx_detach_mailbox_work(adapter
);
2557 qlcnic_83xx_free_mailbox(ahw
->mailbox
);
2558 ahw
->mailbox
= NULL
;
2563 void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter
*adapter
)
2565 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2566 struct qlc_83xx_idc
*idc
= &ahw
->idc
;
2568 clear_bit(QLC_83XX_MBX_READY
, &idc
->status
);
2569 cancel_delayed_work_sync(&adapter
->fw_work
);
2571 if (ahw
->nic_mode
== QLCNIC_VNIC_MODE
)
2572 qlcnic_83xx_disable_vnic_mode(adapter
, 1);
2574 qlcnic_83xx_idc_detach_driver(adapter
);
2575 qlcnic_83xx_initialize_nic(adapter
, 0);
2577 cancel_delayed_work_sync(&adapter
->idc_aen_work
);
2580 int qlcnic_83xx_aer_reset(struct qlcnic_adapter
*adapter
)
2582 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2583 struct qlc_83xx_idc
*idc
= &ahw
->idc
;
2587 /* Mark the previous IDC state as NEED_RESET so
2588 * that state_entry() will perform the reattachment
2589 * and bringup the device
2591 idc
->prev_state
= QLC_83XX_IDC_DEV_NEED_RESET
;
2592 owner
= qlcnic_83xx_idc_find_reset_owner_id(adapter
);
2593 if (ahw
->pci_func
== owner
) {
2594 ret
= qlcnic_83xx_restart_hw(adapter
);
2597 qlcnic_83xx_idc_clear_registers(adapter
, 0);
2600 ret
= idc
->state_entry(adapter
);
2604 void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter
*adapter
)
2606 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
2607 struct qlc_83xx_idc
*idc
= &ahw
->idc
;
2610 idc
->prev_state
= QLC_83XX_IDC_DEV_READY
;
2611 owner
= qlcnic_83xx_idc_find_reset_owner_id(adapter
);
2612 if (ahw
->pci_func
== owner
)
2613 qlcnic_83xx_idc_enter_ready_state(adapter
, 0);
2615 qlcnic_schedule_work(adapter
, qlcnic_83xx_idc_poll_dev_state
, 0);