2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
9 #include "qlcnic_hdr.h"
11 #include <linux/slab.h>
13 #include <linux/bitops.h>
15 #define MASK(n) ((1ULL<<(n))-1)
16 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
18 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
20 #define CRB_BLK(off) ((off >> 20) & 0x3f)
21 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
22 #define CRB_WINDOW_2M (0x130060)
23 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
24 #define CRB_INDIRECT_2M (0x1e0000UL)
26 struct qlcnic_ms_reg_ctrl
{
37 static inline u64
readq(void __iomem
*addr
)
39 return readl(addr
) | (((u64
) readl(addr
+ 4)) << 32LL);
44 static inline void writeq(u64 val
, void __iomem
*addr
)
46 writel(((u32
) (val
)), (addr
));
47 writel(((u32
) (val
>> 32)), (addr
+ 4));
51 static struct crb_128M_2M_block_map
52 crb_128M_2M_map
[64] __cacheline_aligned_in_smp
= {
53 {{{0, 0, 0, 0} } }, /* 0: PCI */
54 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
55 {1, 0x0110000, 0x0120000, 0x130000},
56 {1, 0x0120000, 0x0122000, 0x124000},
57 {1, 0x0130000, 0x0132000, 0x126000},
58 {1, 0x0140000, 0x0142000, 0x128000},
59 {1, 0x0150000, 0x0152000, 0x12a000},
60 {1, 0x0160000, 0x0170000, 0x110000},
61 {1, 0x0170000, 0x0172000, 0x12e000},
62 {0, 0x0000000, 0x0000000, 0x000000},
63 {0, 0x0000000, 0x0000000, 0x000000},
64 {0, 0x0000000, 0x0000000, 0x000000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {1, 0x01e0000, 0x01e0800, 0x122000},
69 {0, 0x0000000, 0x0000000, 0x000000} } },
70 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
71 {{{0, 0, 0, 0} } }, /* 3: */
72 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
73 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
74 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
75 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
76 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
77 {0, 0x0000000, 0x0000000, 0x000000},
78 {0, 0x0000000, 0x0000000, 0x000000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {1, 0x08f0000, 0x08f2000, 0x172000} } },
92 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {1, 0x09f0000, 0x09f2000, 0x176000} } },
108 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
124 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
140 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
141 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
142 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
143 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
144 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
145 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
146 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
147 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
148 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
149 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
150 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
151 {{{0, 0, 0, 0} } }, /* 23: */
152 {{{0, 0, 0, 0} } }, /* 24: */
153 {{{0, 0, 0, 0} } }, /* 25: */
154 {{{0, 0, 0, 0} } }, /* 26: */
155 {{{0, 0, 0, 0} } }, /* 27: */
156 {{{0, 0, 0, 0} } }, /* 28: */
157 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
158 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
159 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
160 {{{0} } }, /* 32: PCI */
161 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
162 {1, 0x2110000, 0x2120000, 0x130000},
163 {1, 0x2120000, 0x2122000, 0x124000},
164 {1, 0x2130000, 0x2132000, 0x126000},
165 {1, 0x2140000, 0x2142000, 0x128000},
166 {1, 0x2150000, 0x2152000, 0x12a000},
167 {1, 0x2160000, 0x2170000, 0x110000},
168 {1, 0x2170000, 0x2172000, 0x12e000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000} } },
177 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
183 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
184 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
185 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
186 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
187 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
188 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
189 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
190 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
191 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
192 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
193 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
194 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
196 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
197 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
198 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
199 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
200 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
201 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
202 {{{0} } }, /* 59: I2C0 */
203 {{{0} } }, /* 60: I2C1 */
204 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
205 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
206 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
210 * top 12 bits of crb internal address (hub, agent)
212 static const unsigned crb_hub_agt
[64] = {
214 QLCNIC_HW_CRB_HUB_AGT_ADR_PS
,
215 QLCNIC_HW_CRB_HUB_AGT_ADR_MN
,
216 QLCNIC_HW_CRB_HUB_AGT_ADR_MS
,
218 QLCNIC_HW_CRB_HUB_AGT_ADR_SRE
,
219 QLCNIC_HW_CRB_HUB_AGT_ADR_NIU
,
220 QLCNIC_HW_CRB_HUB_AGT_ADR_QMN
,
221 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0
,
222 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1
,
223 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2
,
224 QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3
,
225 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q
,
226 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR
,
227 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB
,
228 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4
,
229 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA
,
230 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0
,
231 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1
,
232 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2
,
233 QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3
,
234 QLCNIC_HW_CRB_HUB_AGT_ADR_PGND
,
235 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI
,
236 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0
,
237 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1
,
238 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2
,
239 QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3
,
241 QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI
,
242 QLCNIC_HW_CRB_HUB_AGT_ADR_SN
,
244 QLCNIC_HW_CRB_HUB_AGT_ADR_EG
,
246 QLCNIC_HW_CRB_HUB_AGT_ADR_PS
,
247 QLCNIC_HW_CRB_HUB_AGT_ADR_CAM
,
253 QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR
,
255 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1
,
256 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2
,
257 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3
,
258 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4
,
259 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5
,
260 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6
,
261 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7
,
262 QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA
,
263 QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q
,
264 QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB
,
266 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0
,
267 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8
,
268 QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9
,
269 QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0
,
271 QLCNIC_HW_CRB_HUB_AGT_ADR_SMB
,
272 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0
,
273 QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1
,
275 QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC
,
279 static const u32 msi_tgt_status
[8] = {
280 ISR_INT_TARGET_STATUS
, ISR_INT_TARGET_STATUS_F1
,
281 ISR_INT_TARGET_STATUS_F2
, ISR_INT_TARGET_STATUS_F3
,
282 ISR_INT_TARGET_STATUS_F4
, ISR_INT_TARGET_STATUS_F5
,
283 ISR_INT_TARGET_STATUS_F6
, ISR_INT_TARGET_STATUS_F7
286 /* PCI Windowing for DDR regions. */
288 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
290 static void qlcnic_read_window_reg(u32 addr
, void __iomem
*bar0
, u32
*data
)
295 dest
= addr
& 0xFFFF0000;
296 val
= bar0
+ QLCNIC_FW_DUMP_REG1
;
299 val
= bar0
+ QLCNIC_FW_DUMP_REG2
+ LSW(addr
);
303 static void qlcnic_write_window_reg(u32 addr
, void __iomem
*bar0
, u32 data
)
308 dest
= addr
& 0xFFFF0000;
309 val
= bar0
+ QLCNIC_FW_DUMP_REG1
;
312 val
= bar0
+ QLCNIC_FW_DUMP_REG2
+ LSW(addr
);
318 qlcnic_pcie_sem_lock(struct qlcnic_adapter
*adapter
, int sem
, u32 id_reg
)
320 int done
= 0, timeout
= 0;
323 done
= QLCRD32(adapter
, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem
)));
326 if (++timeout
>= QLCNIC_PCIE_SEM_TIMEOUT
) {
327 dev_err(&adapter
->pdev
->dev
,
328 "Failed to acquire sem=%d lock; holdby=%d\n",
329 sem
, id_reg
? QLCRD32(adapter
, id_reg
) : -1);
336 QLCWR32(adapter
, id_reg
, adapter
->portnum
);
342 qlcnic_pcie_sem_unlock(struct qlcnic_adapter
*adapter
, int sem
)
344 QLCRD32(adapter
, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem
)));
347 int qlcnic_ind_rd(struct qlcnic_adapter
*adapter
, u32 addr
)
351 if (qlcnic_82xx_check(adapter
))
352 qlcnic_read_window_reg(addr
, adapter
->ahw
->pci_base0
, &data
);
354 data
= qlcnic_83xx_rd_reg_indirect(adapter
, addr
);
361 void qlcnic_ind_wr(struct qlcnic_adapter
*adapter
, u32 addr
, u32 data
)
363 if (qlcnic_82xx_check(adapter
))
364 qlcnic_write_window_reg(addr
, adapter
->ahw
->pci_base0
, data
);
366 qlcnic_83xx_wrt_reg_indirect(adapter
, addr
, data
);
370 qlcnic_send_cmd_descs(struct qlcnic_adapter
*adapter
,
371 struct cmd_desc_type0
*cmd_desc_arr
, int nr_desc
)
374 struct qlcnic_cmd_buffer
*pbuf
;
375 struct cmd_desc_type0
*cmd_desc
;
376 struct qlcnic_host_tx_ring
*tx_ring
;
380 if (!test_bit(__QLCNIC_FW_ATTACHED
, &adapter
->state
))
383 tx_ring
= adapter
->tx_ring
;
384 __netif_tx_lock_bh(tx_ring
->txq
);
386 producer
= tx_ring
->producer
;
388 if (nr_desc
>= qlcnic_tx_avail(tx_ring
)) {
389 netif_tx_stop_queue(tx_ring
->txq
);
391 if (qlcnic_tx_avail(tx_ring
) > nr_desc
) {
392 if (qlcnic_tx_avail(tx_ring
) > TX_STOP_THRESH
)
393 netif_tx_wake_queue(tx_ring
->txq
);
395 adapter
->stats
.xmit_off
++;
396 __netif_tx_unlock_bh(tx_ring
->txq
);
402 cmd_desc
= &cmd_desc_arr
[i
];
404 pbuf
= &tx_ring
->cmd_buf_arr
[producer
];
406 pbuf
->frag_count
= 0;
408 memcpy(&tx_ring
->desc_head
[producer
],
409 cmd_desc
, sizeof(struct cmd_desc_type0
));
411 producer
= get_next_index(producer
, tx_ring
->num_desc
);
414 } while (i
!= nr_desc
);
416 tx_ring
->producer
= producer
;
418 qlcnic_update_cmd_producer(tx_ring
);
420 __netif_tx_unlock_bh(tx_ring
->txq
);
425 int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter
*adapter
, u8
*addr
,
428 struct qlcnic_nic_req req
;
429 struct qlcnic_mac_req
*mac_req
;
430 struct qlcnic_vlan_req
*vlan_req
;
433 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
434 req
.qhdr
= cpu_to_le64(QLCNIC_REQUEST
<< 23);
436 word
= QLCNIC_MAC_EVENT
| ((u64
)adapter
->portnum
<< 16);
437 req
.req_hdr
= cpu_to_le64(word
);
439 mac_req
= (struct qlcnic_mac_req
*)&req
.words
[0];
441 memcpy(mac_req
->mac_addr
, addr
, 6);
443 vlan_req
= (struct qlcnic_vlan_req
*)&req
.words
[1];
444 vlan_req
->vlan_id
= cpu_to_le16(vlan_id
);
446 return qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
449 int qlcnic_nic_del_mac(struct qlcnic_adapter
*adapter
, const u8
*addr
)
451 struct list_head
*head
;
452 struct qlcnic_mac_list_s
*cur
;
455 /* Delete MAC from the existing list */
456 list_for_each(head
, &adapter
->mac_list
) {
457 cur
= list_entry(head
, struct qlcnic_mac_list_s
, list
);
458 if (memcmp(addr
, cur
->mac_addr
, ETH_ALEN
) == 0) {
459 err
= qlcnic_sre_macaddr_change(adapter
, cur
->mac_addr
,
463 list_del(&cur
->list
);
471 int qlcnic_nic_add_mac(struct qlcnic_adapter
*adapter
, const u8
*addr
, u16 vlan
)
473 struct list_head
*head
;
474 struct qlcnic_mac_list_s
*cur
;
476 /* look up if already exists */
477 list_for_each(head
, &adapter
->mac_list
) {
478 cur
= list_entry(head
, struct qlcnic_mac_list_s
, list
);
479 if (memcmp(addr
, cur
->mac_addr
, ETH_ALEN
) == 0)
483 cur
= kzalloc(sizeof(struct qlcnic_mac_list_s
), GFP_ATOMIC
);
487 memcpy(cur
->mac_addr
, addr
, ETH_ALEN
);
489 if (qlcnic_sre_macaddr_change(adapter
,
490 cur
->mac_addr
, vlan
, QLCNIC_MAC_ADD
)) {
495 list_add_tail(&cur
->list
, &adapter
->mac_list
);
499 void __qlcnic_set_multi(struct net_device
*netdev
, u16 vlan
)
501 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
502 struct qlcnic_hardware_context
*ahw
= adapter
->ahw
;
503 struct netdev_hw_addr
*ha
;
504 static const u8 bcast_addr
[ETH_ALEN
] = {
505 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
507 u32 mode
= VPORT_MISS_MODE_DROP
;
509 if (!test_bit(__QLCNIC_FW_ATTACHED
, &adapter
->state
))
512 if (!qlcnic_sriov_vf_check(adapter
))
513 qlcnic_nic_add_mac(adapter
, adapter
->mac_addr
, vlan
);
514 qlcnic_nic_add_mac(adapter
, bcast_addr
, vlan
);
516 if (netdev
->flags
& IFF_PROMISC
) {
517 if (!(adapter
->flags
& QLCNIC_PROMISC_DISABLED
))
518 mode
= VPORT_MISS_MODE_ACCEPT_ALL
;
519 } else if ((netdev
->flags
& IFF_ALLMULTI
) ||
520 (netdev_mc_count(netdev
) > ahw
->max_mc_count
)) {
521 mode
= VPORT_MISS_MODE_ACCEPT_MULTI
;
522 } else if (!netdev_mc_empty(netdev
) &&
523 !qlcnic_sriov_vf_check(adapter
)) {
524 netdev_for_each_mc_addr(ha
, netdev
)
525 qlcnic_nic_add_mac(adapter
, ha
->addr
, vlan
);
528 if (qlcnic_sriov_vf_check(adapter
))
529 qlcnic_vf_add_mc_list(netdev
, vlan
);
531 /* configure unicast MAC address, if there is not sufficient space
532 * to store all the unicast addresses then enable promiscuous mode
534 if (netdev_uc_count(netdev
) > ahw
->max_uc_count
) {
535 mode
= VPORT_MISS_MODE_ACCEPT_ALL
;
536 } else if (!netdev_uc_empty(netdev
)) {
537 netdev_for_each_uc_addr(ha
, netdev
)
538 qlcnic_nic_add_mac(adapter
, ha
->addr
, vlan
);
541 if (!qlcnic_sriov_vf_check(adapter
)) {
542 if (mode
== VPORT_MISS_MODE_ACCEPT_ALL
&&
543 !adapter
->fdb_mac_learn
) {
544 qlcnic_alloc_lb_filters_mem(adapter
);
545 adapter
->drv_mac_learn
= true;
547 adapter
->drv_mac_learn
= false;
551 qlcnic_nic_set_promisc(adapter
, mode
);
554 void qlcnic_set_multi(struct net_device
*netdev
)
556 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
557 struct netdev_hw_addr
*ha
;
558 struct qlcnic_mac_list_s
*cur
;
560 if (!test_bit(__QLCNIC_FW_ATTACHED
, &adapter
->state
))
562 if (qlcnic_sriov_vf_check(adapter
)) {
563 if (!netdev_mc_empty(netdev
)) {
564 netdev_for_each_mc_addr(ha
, netdev
) {
565 cur
= kzalloc(sizeof(struct qlcnic_mac_list_s
),
569 memcpy(cur
->mac_addr
,
571 list_add_tail(&cur
->list
, &adapter
->vf_mc_list
);
574 qlcnic_sriov_vf_schedule_multi(adapter
->netdev
);
577 __qlcnic_set_multi(netdev
, 0);
580 int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter
*adapter
, u32 mode
)
582 struct qlcnic_nic_req req
;
585 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
587 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
589 word
= QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE
|
590 ((u64
)adapter
->portnum
<< 16);
591 req
.req_hdr
= cpu_to_le64(word
);
593 req
.words
[0] = cpu_to_le64(mode
);
595 return qlcnic_send_cmd_descs(adapter
,
596 (struct cmd_desc_type0
*)&req
, 1);
599 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter
*adapter
)
601 struct qlcnic_mac_list_s
*cur
;
602 struct list_head
*head
= &adapter
->mac_list
;
604 while (!list_empty(head
)) {
605 cur
= list_entry(head
->next
, struct qlcnic_mac_list_s
, list
);
606 qlcnic_sre_macaddr_change(adapter
,
607 cur
->mac_addr
, 0, QLCNIC_MAC_DEL
);
608 list_del(&cur
->list
);
613 void qlcnic_prune_lb_filters(struct qlcnic_adapter
*adapter
)
615 struct qlcnic_filter
*tmp_fil
;
616 struct hlist_node
*n
;
617 struct hlist_head
*head
;
622 for (i
= 0; i
< adapter
->fhash
.fbucket_size
; i
++) {
623 head
= &(adapter
->fhash
.fhead
[i
]);
624 hlist_for_each_entry_safe(tmp_fil
, n
, head
, fnode
) {
625 cmd
= tmp_fil
->vlan_id
? QLCNIC_MAC_VLAN_DEL
:
627 time
= tmp_fil
->ftime
;
628 if (jiffies
> (QLCNIC_FILTER_AGE
* HZ
+ time
)) {
629 qlcnic_sre_macaddr_change(adapter
,
633 spin_lock_bh(&adapter
->mac_learn_lock
);
634 adapter
->fhash
.fnum
--;
635 hlist_del(&tmp_fil
->fnode
);
636 spin_unlock_bh(&adapter
->mac_learn_lock
);
641 for (i
= 0; i
< adapter
->rx_fhash
.fbucket_size
; i
++) {
642 head
= &(adapter
->rx_fhash
.fhead
[i
]);
644 hlist_for_each_entry_safe(tmp_fil
, n
, head
, fnode
)
646 time
= tmp_fil
->ftime
;
647 if (jiffies
> (QLCNIC_FILTER_AGE
* HZ
+ time
)) {
648 spin_lock_bh(&adapter
->rx_mac_learn_lock
);
649 adapter
->rx_fhash
.fnum
--;
650 hlist_del(&tmp_fil
->fnode
);
651 spin_unlock_bh(&adapter
->rx_mac_learn_lock
);
658 void qlcnic_delete_lb_filters(struct qlcnic_adapter
*adapter
)
660 struct qlcnic_filter
*tmp_fil
;
661 struct hlist_node
*n
;
662 struct hlist_head
*head
;
666 for (i
= 0; i
< adapter
->fhash
.fbucket_size
; i
++) {
667 head
= &(adapter
->fhash
.fhead
[i
]);
668 hlist_for_each_entry_safe(tmp_fil
, n
, head
, fnode
) {
669 cmd
= tmp_fil
->vlan_id
? QLCNIC_MAC_VLAN_DEL
:
671 qlcnic_sre_macaddr_change(adapter
,
675 spin_lock_bh(&adapter
->mac_learn_lock
);
676 adapter
->fhash
.fnum
--;
677 hlist_del(&tmp_fil
->fnode
);
678 spin_unlock_bh(&adapter
->mac_learn_lock
);
684 static int qlcnic_set_fw_loopback(struct qlcnic_adapter
*adapter
, u8 flag
)
686 struct qlcnic_nic_req req
;
689 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
691 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
692 req
.req_hdr
= cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK
|
693 ((u64
) adapter
->portnum
<< 16) | ((u64
) 0x1 << 32));
695 req
.words
[0] = cpu_to_le64(flag
);
697 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
699 dev_err(&adapter
->pdev
->dev
, "%sting loopback mode failed\n",
700 flag
? "Set" : "Reset");
704 int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter
*adapter
, u8 mode
)
706 if (qlcnic_set_fw_loopback(adapter
, mode
))
709 if (qlcnic_nic_set_promisc(adapter
,
710 VPORT_MISS_MODE_ACCEPT_ALL
)) {
711 qlcnic_set_fw_loopback(adapter
, 0);
719 int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter
*adapter
, u8 mode
)
721 struct net_device
*netdev
= adapter
->netdev
;
723 mode
= VPORT_MISS_MODE_DROP
;
724 qlcnic_set_fw_loopback(adapter
, 0);
726 if (netdev
->flags
& IFF_PROMISC
)
727 mode
= VPORT_MISS_MODE_ACCEPT_ALL
;
728 else if (netdev
->flags
& IFF_ALLMULTI
)
729 mode
= VPORT_MISS_MODE_ACCEPT_MULTI
;
731 qlcnic_nic_set_promisc(adapter
, mode
);
737 * Send the interrupt coalescing parameter set by ethtool to the card.
739 void qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter
*adapter
)
741 struct qlcnic_nic_req req
;
744 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
746 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
748 req
.req_hdr
= cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE
|
749 ((u64
) adapter
->portnum
<< 16));
751 req
.words
[0] = cpu_to_le64(((u64
) adapter
->ahw
->coal
.flag
) << 32);
752 req
.words
[2] = cpu_to_le64(adapter
->ahw
->coal
.rx_packets
|
753 ((u64
) adapter
->ahw
->coal
.rx_time_us
) << 16);
754 req
.words
[5] = cpu_to_le64(adapter
->ahw
->coal
.timer_out
|
755 ((u64
) adapter
->ahw
->coal
.type
) << 32 |
756 ((u64
) adapter
->ahw
->coal
.sts_ring_mask
) << 40);
757 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
759 dev_err(&adapter
->netdev
->dev
,
760 "Could not send interrupt coalescing parameters\n");
763 #define QLCNIC_ENABLE_IPV4_LRO 1
764 #define QLCNIC_ENABLE_IPV6_LRO 2
765 #define QLCNIC_NO_DEST_IPV4_CHECK (1 << 8)
766 #define QLCNIC_NO_DEST_IPV6_CHECK (2 << 8)
768 int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter
*adapter
, int enable
)
770 struct qlcnic_nic_req req
;
774 if (!test_bit(__QLCNIC_FW_ATTACHED
, &adapter
->state
))
777 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
779 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
781 word
= QLCNIC_H2C_OPCODE_CONFIG_HW_LRO
| ((u64
)adapter
->portnum
<< 16);
782 req
.req_hdr
= cpu_to_le64(word
);
786 word
= QLCNIC_ENABLE_IPV4_LRO
| QLCNIC_NO_DEST_IPV4_CHECK
;
787 if (adapter
->ahw
->extra_capability
[0] &
788 QLCNIC_FW_CAP2_HW_LRO_IPV6
)
789 word
|= QLCNIC_ENABLE_IPV6_LRO
|
790 QLCNIC_NO_DEST_IPV6_CHECK
;
793 req
.words
[0] = cpu_to_le64(word
);
795 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
797 dev_err(&adapter
->netdev
->dev
,
798 "Could not send configure hw lro request\n");
803 int qlcnic_config_bridged_mode(struct qlcnic_adapter
*adapter
, u32 enable
)
805 struct qlcnic_nic_req req
;
809 if (!!(adapter
->flags
& QLCNIC_BRIDGE_ENABLED
) == enable
)
812 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
814 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
816 word
= QLCNIC_H2C_OPCODE_CONFIG_BRIDGING
|
817 ((u64
)adapter
->portnum
<< 16);
818 req
.req_hdr
= cpu_to_le64(word
);
820 req
.words
[0] = cpu_to_le64(enable
);
822 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
824 dev_err(&adapter
->netdev
->dev
,
825 "Could not send configure bridge mode request\n");
827 adapter
->flags
^= QLCNIC_BRIDGE_ENABLED
;
833 #define QLCNIC_RSS_HASHTYPE_IP_TCP 0x3
834 #define QLCNIC_ENABLE_TYPE_C_RSS BIT_10
835 #define QLCNIC_RSS_FEATURE_FLAG (1ULL << 63)
836 #define QLCNIC_RSS_IND_TABLE_MASK 0x7ULL
838 int qlcnic_82xx_config_rss(struct qlcnic_adapter
*adapter
, int enable
)
840 struct qlcnic_nic_req req
;
844 static const u64 key
[] = {
845 0xbeac01fa6a42b73bULL
, 0x8030f20c77cb2da3ULL
,
846 0xae7b30b4d0ca2bcbULL
, 0x43a38fb04167253dULL
,
847 0x255b0ec26d5a56daULL
850 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
851 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
853 word
= QLCNIC_H2C_OPCODE_CONFIG_RSS
| ((u64
)adapter
->portnum
<< 16);
854 req
.req_hdr
= cpu_to_le64(word
);
858 * bits 3-0: hash_method
859 * 5-4: hash_type_ipv4
860 * 7-6: hash_type_ipv6
862 * 9: use indirection table
866 * 62-48: indirection table mask
869 word
= ((u64
)(QLCNIC_RSS_HASHTYPE_IP_TCP
& 0x3) << 4) |
870 ((u64
)(QLCNIC_RSS_HASHTYPE_IP_TCP
& 0x3) << 6) |
871 ((u64
)(enable
& 0x1) << 8) |
872 ((u64
)QLCNIC_RSS_IND_TABLE_MASK
<< 48) |
873 (u64
)QLCNIC_ENABLE_TYPE_C_RSS
|
874 (u64
)QLCNIC_RSS_FEATURE_FLAG
;
876 req
.words
[0] = cpu_to_le64(word
);
877 for (i
= 0; i
< 5; i
++)
878 req
.words
[i
+1] = cpu_to_le64(key
[i
]);
880 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
882 dev_err(&adapter
->netdev
->dev
, "could not configure RSS\n");
887 void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter
*adapter
,
890 struct qlcnic_nic_req req
;
891 struct qlcnic_ipaddr
*ipa
;
895 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
896 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
898 word
= QLCNIC_H2C_OPCODE_CONFIG_IPADDR
| ((u64
)adapter
->portnum
<< 16);
899 req
.req_hdr
= cpu_to_le64(word
);
901 req
.words
[0] = cpu_to_le64(cmd
);
902 ipa
= (struct qlcnic_ipaddr
*)&req
.words
[1];
905 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
907 dev_err(&adapter
->netdev
->dev
,
908 "could not notify %s IP 0x%x reuqest\n",
909 (cmd
== QLCNIC_IP_UP
) ? "Add" : "Remove", ip
);
912 int qlcnic_82xx_linkevent_request(struct qlcnic_adapter
*adapter
, int enable
)
914 struct qlcnic_nic_req req
;
917 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
918 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
920 word
= QLCNIC_H2C_OPCODE_GET_LINKEVENT
| ((u64
)adapter
->portnum
<< 16);
921 req
.req_hdr
= cpu_to_le64(word
);
922 req
.words
[0] = cpu_to_le64(enable
| (enable
<< 8));
923 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
925 dev_err(&adapter
->netdev
->dev
,
926 "could not configure link notification\n");
931 int qlcnic_send_lro_cleanup(struct qlcnic_adapter
*adapter
)
933 struct qlcnic_nic_req req
;
937 if (!test_bit(__QLCNIC_FW_ATTACHED
, &adapter
->state
))
940 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
941 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
943 word
= QLCNIC_H2C_OPCODE_LRO_REQUEST
|
944 ((u64
)adapter
->portnum
<< 16) |
945 ((u64
)QLCNIC_LRO_REQUEST_CLEANUP
<< 56) ;
947 req
.req_hdr
= cpu_to_le64(word
);
949 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
951 dev_err(&adapter
->netdev
->dev
,
952 "could not cleanup lro flows\n");
958 * qlcnic_change_mtu - Change the Maximum Transfer Unit
959 * @returns 0 on success, negative on failure
962 int qlcnic_change_mtu(struct net_device
*netdev
, int mtu
)
964 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
967 if (mtu
< P3P_MIN_MTU
|| mtu
> P3P_MAX_MTU
) {
968 dev_err(&adapter
->netdev
->dev
, "%d bytes < mtu < %d bytes"
969 " not supported\n", P3P_MAX_MTU
, P3P_MIN_MTU
);
973 rc
= qlcnic_fw_cmd_set_mtu(adapter
, mtu
);
981 static netdev_features_t
qlcnic_process_flags(struct qlcnic_adapter
*adapter
,
982 netdev_features_t features
)
984 u32 offload_flags
= adapter
->offload_flags
;
986 if (offload_flags
& BIT_0
) {
987 features
|= NETIF_F_RXCSUM
| NETIF_F_IP_CSUM
|
989 adapter
->rx_csum
= 1;
990 if (QLCNIC_IS_TSO_CAPABLE(adapter
)) {
991 if (!(offload_flags
& BIT_1
))
992 features
&= ~NETIF_F_TSO
;
994 features
|= NETIF_F_TSO
;
996 if (!(offload_flags
& BIT_2
))
997 features
&= ~NETIF_F_TSO6
;
999 features
|= NETIF_F_TSO6
;
1002 features
&= ~(NETIF_F_RXCSUM
|
1006 if (QLCNIC_IS_TSO_CAPABLE(adapter
))
1007 features
&= ~(NETIF_F_TSO
| NETIF_F_TSO6
);
1008 adapter
->rx_csum
= 0;
1014 netdev_features_t
qlcnic_fix_features(struct net_device
*netdev
,
1015 netdev_features_t features
)
1017 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1018 netdev_features_t changed
;
1020 if (qlcnic_82xx_check(adapter
) &&
1021 (adapter
->flags
& QLCNIC_ESWITCH_ENABLED
)) {
1022 if (adapter
->flags
& QLCNIC_APP_CHANGED_FLAGS
) {
1023 features
= qlcnic_process_flags(adapter
, features
);
1025 changed
= features
^ netdev
->features
;
1026 features
^= changed
& (NETIF_F_RXCSUM
|
1034 if (!(features
& NETIF_F_RXCSUM
))
1035 features
&= ~NETIF_F_LRO
;
1041 int qlcnic_set_features(struct net_device
*netdev
, netdev_features_t features
)
1043 struct qlcnic_adapter
*adapter
= netdev_priv(netdev
);
1044 netdev_features_t changed
= netdev
->features
^ features
;
1045 int hw_lro
= (features
& NETIF_F_LRO
) ? QLCNIC_LRO_ENABLED
: 0;
1047 if (!(changed
& NETIF_F_LRO
))
1050 netdev
->features
^= NETIF_F_LRO
;
1052 if (qlcnic_config_hw_lro(adapter
, hw_lro
))
1055 if (!hw_lro
&& qlcnic_82xx_check(adapter
)) {
1056 if (qlcnic_send_lro_cleanup(adapter
))
1064 * Changes the CRB window to the specified window.
1066 /* Returns < 0 if off is not valid,
1067 * 1 if window access is needed. 'off' is set to offset from
1068 * CRB space in 128M pci map
1069 * 0 if no window access is needed. 'off' is set to 2M addr
1070 * In: 'off' is offset from base in 128M pci map
1072 static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context
*ahw
,
1073 ulong off
, void __iomem
**addr
)
1075 const struct crb_128M_2M_sub_block_map
*m
;
1077 if ((off
>= QLCNIC_CRB_MAX
) || (off
< QLCNIC_PCI_CRBSPACE
))
1080 off
-= QLCNIC_PCI_CRBSPACE
;
1085 m
= &crb_128M_2M_map
[CRB_BLK(off
)].sub_block
[CRB_SUBBLK(off
)];
1087 if (m
->valid
&& (m
->start_128M
<= off
) && (m
->end_128M
> off
)) {
1088 *addr
= ahw
->pci_base0
+ m
->start_2M
+
1089 (off
- m
->start_128M
);
1094 * Not in direct map, use crb window
1096 *addr
= ahw
->pci_base0
+ CRB_INDIRECT_2M
+ (off
& MASK(16));
1101 * In: 'off' is offset from CRB space in 128M pci map
1102 * Out: 'off' is 2M pci map addr
1103 * side effect: lock crb window
1106 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter
*adapter
, ulong off
)
1109 void __iomem
*addr
= adapter
->ahw
->pci_base0
+ CRB_WINDOW_2M
;
1111 off
-= QLCNIC_PCI_CRBSPACE
;
1113 window
= CRB_HI(off
);
1115 dev_err(&adapter
->pdev
->dev
, "Invalid offset 0x%lx\n", off
);
1119 writel(window
, addr
);
1120 if (readl(addr
) != window
) {
1121 if (printk_ratelimit())
1122 dev_warn(&adapter
->pdev
->dev
,
1123 "failed to set CRB window to %d off 0x%lx\n",
1130 int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter
*adapter
, ulong off
,
1133 unsigned long flags
;
1135 void __iomem
*addr
= NULL
;
1137 rv
= qlcnic_pci_get_crb_addr_2M(adapter
->ahw
, off
, &addr
);
1145 /* indirect access */
1146 write_lock_irqsave(&adapter
->ahw
->crb_lock
, flags
);
1147 crb_win_lock(adapter
);
1148 rv
= qlcnic_pci_set_crbwindow_2M(adapter
, off
);
1151 crb_win_unlock(adapter
);
1152 write_unlock_irqrestore(&adapter
->ahw
->crb_lock
, flags
);
1156 dev_err(&adapter
->pdev
->dev
,
1157 "%s: invalid offset: 0x%016lx\n", __func__
, off
);
1162 int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter
*adapter
, ulong off
)
1164 unsigned long flags
;
1167 void __iomem
*addr
= NULL
;
1169 rv
= qlcnic_pci_get_crb_addr_2M(adapter
->ahw
, off
, &addr
);
1175 /* indirect access */
1176 write_lock_irqsave(&adapter
->ahw
->crb_lock
, flags
);
1177 crb_win_lock(adapter
);
1178 if (!qlcnic_pci_set_crbwindow_2M(adapter
, off
))
1180 crb_win_unlock(adapter
);
1181 write_unlock_irqrestore(&adapter
->ahw
->crb_lock
, flags
);
1185 dev_err(&adapter
->pdev
->dev
,
1186 "%s: invalid offset: 0x%016lx\n", __func__
, off
);
1191 void __iomem
*qlcnic_get_ioaddr(struct qlcnic_hardware_context
*ahw
,
1194 void __iomem
*addr
= NULL
;
1196 WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw
, offset
, &addr
));
1201 static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter
*adapter
,
1202 u32 window
, u64 off
, u64
*data
, int op
)
1207 mutex_lock(&adapter
->ahw
->mem_lock
);
1209 writel(window
, adapter
->ahw
->ocm_win_crb
);
1210 /* read back to flush */
1211 readl(adapter
->ahw
->ocm_win_crb
);
1212 start
= QLCNIC_PCI_OCM0_2M
+ off
;
1214 addr
= adapter
->ahw
->pci_base0
+ start
;
1216 if (op
== 0) /* read */
1217 *data
= readq(addr
);
1219 writeq(*data
, addr
);
1221 /* Set window to 0 */
1222 writel(0, adapter
->ahw
->ocm_win_crb
);
1223 readl(adapter
->ahw
->ocm_win_crb
);
1225 mutex_unlock(&adapter
->ahw
->mem_lock
);
1230 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter
*adapter
, u64 off
, u64
*data
)
1232 void __iomem
*addr
= adapter
->ahw
->pci_base0
+
1233 QLCNIC_PCI_CAMQM_2M_BASE
+ (off
- QLCNIC_PCI_CAMQM
);
1235 mutex_lock(&adapter
->ahw
->mem_lock
);
1236 *data
= readq(addr
);
1237 mutex_unlock(&adapter
->ahw
->mem_lock
);
1241 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter
*adapter
, u64 off
, u64 data
)
1243 void __iomem
*addr
= adapter
->ahw
->pci_base0
+
1244 QLCNIC_PCI_CAMQM_2M_BASE
+ (off
- QLCNIC_PCI_CAMQM
);
1246 mutex_lock(&adapter
->ahw
->mem_lock
);
1248 mutex_unlock(&adapter
->ahw
->mem_lock
);
1253 /* Set MS memory control data for different adapters */
1254 static void qlcnic_set_ms_controls(struct qlcnic_adapter
*adapter
, u64 off
,
1255 struct qlcnic_ms_reg_ctrl
*ms
)
1257 ms
->control
= QLCNIC_MS_CTRL
;
1258 ms
->low
= QLCNIC_MS_ADDR_LO
;
1259 ms
->hi
= QLCNIC_MS_ADDR_HI
;
1261 ms
->wd
[0] = QLCNIC_MS_WRTDATA_LO
;
1262 ms
->rd
[0] = QLCNIC_MS_RDDATA_LO
;
1263 ms
->wd
[1] = QLCNIC_MS_WRTDATA_HI
;
1264 ms
->rd
[1] = QLCNIC_MS_RDDATA_HI
;
1265 ms
->wd
[2] = QLCNIC_MS_WRTDATA_ULO
;
1266 ms
->wd
[3] = QLCNIC_MS_WRTDATA_UHI
;
1267 ms
->rd
[2] = QLCNIC_MS_RDDATA_ULO
;
1268 ms
->rd
[3] = QLCNIC_MS_RDDATA_UHI
;
1270 ms
->wd
[0] = QLCNIC_MS_WRTDATA_ULO
;
1271 ms
->rd
[0] = QLCNIC_MS_RDDATA_ULO
;
1272 ms
->wd
[1] = QLCNIC_MS_WRTDATA_UHI
;
1273 ms
->rd
[1] = QLCNIC_MS_RDDATA_UHI
;
1274 ms
->wd
[2] = QLCNIC_MS_WRTDATA_LO
;
1275 ms
->wd
[3] = QLCNIC_MS_WRTDATA_HI
;
1276 ms
->rd
[2] = QLCNIC_MS_RDDATA_LO
;
1277 ms
->rd
[3] = QLCNIC_MS_RDDATA_HI
;
1280 ms
->ocm_window
= OCM_WIN_P3P(off
);
1281 ms
->off
= GET_MEM_OFFS_2M(off
);
1284 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter
*adapter
, u64 off
, u64 data
)
1288 struct qlcnic_ms_reg_ctrl ms
;
1290 /* Only 64-bit aligned access */
1294 memset(&ms
, 0, sizeof(struct qlcnic_ms_reg_ctrl
));
1295 if (!(ADDR_IN_RANGE(off
, QLCNIC_ADDR_QDR_NET
,
1296 QLCNIC_ADDR_QDR_NET_MAX
) ||
1297 ADDR_IN_RANGE(off
, QLCNIC_ADDR_DDR_NET
,
1298 QLCNIC_ADDR_DDR_NET_MAX
)))
1301 qlcnic_set_ms_controls(adapter
, off
, &ms
);
1303 if (ADDR_IN_RANGE(off
, QLCNIC_ADDR_OCM0
, QLCNIC_ADDR_OCM0_MAX
))
1304 return qlcnic_pci_mem_access_direct(adapter
, ms
.ocm_window
,
1309 mutex_lock(&adapter
->ahw
->mem_lock
);
1311 qlcnic_ind_wr(adapter
, ms
.low
, off8
);
1312 qlcnic_ind_wr(adapter
, ms
.hi
, 0);
1314 qlcnic_ind_wr(adapter
, ms
.control
, TA_CTL_ENABLE
);
1315 qlcnic_ind_wr(adapter
, ms
.control
, QLCNIC_TA_START_ENABLE
);
1317 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1318 temp
= qlcnic_ind_rd(adapter
, ms
.control
);
1319 if ((temp
& TA_CTL_BUSY
) == 0)
1323 if (j
>= MAX_CTL_CHECK
) {
1328 /* This is the modify part of read-modify-write */
1329 qlcnic_ind_wr(adapter
, ms
.wd
[0], qlcnic_ind_rd(adapter
, ms
.rd
[0]));
1330 qlcnic_ind_wr(adapter
, ms
.wd
[1], qlcnic_ind_rd(adapter
, ms
.rd
[1]));
1331 /* This is the write part of read-modify-write */
1332 qlcnic_ind_wr(adapter
, ms
.wd
[2], data
& 0xffffffff);
1333 qlcnic_ind_wr(adapter
, ms
.wd
[3], (data
>> 32) & 0xffffffff);
1335 qlcnic_ind_wr(adapter
, ms
.control
, QLCNIC_TA_WRITE_ENABLE
);
1336 qlcnic_ind_wr(adapter
, ms
.control
, QLCNIC_TA_WRITE_START
);
1338 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1339 temp
= qlcnic_ind_rd(adapter
, ms
.control
);
1340 if ((temp
& TA_CTL_BUSY
) == 0)
1344 if (j
>= MAX_CTL_CHECK
) {
1345 if (printk_ratelimit())
1346 dev_err(&adapter
->pdev
->dev
,
1347 "failed to write through agent\n");
1353 mutex_unlock(&adapter
->ahw
->mem_lock
);
1358 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter
*adapter
, u64 off
, u64
*data
)
1363 struct qlcnic_ms_reg_ctrl ms
;
1365 /* Only 64-bit aligned access */
1368 if (!(ADDR_IN_RANGE(off
, QLCNIC_ADDR_QDR_NET
,
1369 QLCNIC_ADDR_QDR_NET_MAX
) ||
1370 ADDR_IN_RANGE(off
, QLCNIC_ADDR_DDR_NET
,
1371 QLCNIC_ADDR_DDR_NET_MAX
)))
1374 memset(&ms
, 0, sizeof(struct qlcnic_ms_reg_ctrl
));
1375 qlcnic_set_ms_controls(adapter
, off
, &ms
);
1377 if (ADDR_IN_RANGE(off
, QLCNIC_ADDR_OCM0
, QLCNIC_ADDR_OCM0_MAX
))
1378 return qlcnic_pci_mem_access_direct(adapter
, ms
.ocm_window
,
1381 mutex_lock(&adapter
->ahw
->mem_lock
);
1385 qlcnic_ind_wr(adapter
, ms
.low
, off8
);
1386 qlcnic_ind_wr(adapter
, ms
.hi
, 0);
1388 qlcnic_ind_wr(adapter
, ms
.control
, TA_CTL_ENABLE
);
1389 qlcnic_ind_wr(adapter
, ms
.control
, QLCNIC_TA_START_ENABLE
);
1391 for (j
= 0; j
< MAX_CTL_CHECK
; j
++) {
1392 temp
= qlcnic_ind_rd(adapter
, ms
.control
);
1393 if ((temp
& TA_CTL_BUSY
) == 0)
1397 if (j
>= MAX_CTL_CHECK
) {
1398 if (printk_ratelimit())
1399 dev_err(&adapter
->pdev
->dev
,
1400 "failed to read through agent\n");
1404 temp
= qlcnic_ind_rd(adapter
, ms
.rd
[3]);
1405 val
= (u64
)temp
<< 32;
1406 val
|= qlcnic_ind_rd(adapter
, ms
.rd
[2]);
1411 mutex_unlock(&adapter
->ahw
->mem_lock
);
1416 int qlcnic_82xx_get_board_info(struct qlcnic_adapter
*adapter
)
1418 int offset
, board_type
, magic
;
1419 struct pci_dev
*pdev
= adapter
->pdev
;
1421 offset
= QLCNIC_FW_MAGIC_OFFSET
;
1422 if (qlcnic_rom_fast_read(adapter
, offset
, &magic
))
1425 if (magic
!= QLCNIC_BDINFO_MAGIC
) {
1426 dev_err(&pdev
->dev
, "invalid board config, magic=%08x\n",
1431 offset
= QLCNIC_BRDTYPE_OFFSET
;
1432 if (qlcnic_rom_fast_read(adapter
, offset
, &board_type
))
1435 adapter
->ahw
->board_type
= board_type
;
1437 if (board_type
== QLCNIC_BRDTYPE_P3P_4_GB_MM
) {
1438 u32 gpio
= QLCRD32(adapter
, QLCNIC_ROMUSB_GLB_PAD_GPIO_I
);
1439 if ((gpio
& 0x8000) == 0)
1440 board_type
= QLCNIC_BRDTYPE_P3P_10G_TP
;
1443 switch (board_type
) {
1444 case QLCNIC_BRDTYPE_P3P_HMEZ
:
1445 case QLCNIC_BRDTYPE_P3P_XG_LOM
:
1446 case QLCNIC_BRDTYPE_P3P_10G_CX4
:
1447 case QLCNIC_BRDTYPE_P3P_10G_CX4_LP
:
1448 case QLCNIC_BRDTYPE_P3P_IMEZ
:
1449 case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS
:
1450 case QLCNIC_BRDTYPE_P3P_10G_SFP_CT
:
1451 case QLCNIC_BRDTYPE_P3P_10G_SFP_QT
:
1452 case QLCNIC_BRDTYPE_P3P_10G_XFP
:
1453 case QLCNIC_BRDTYPE_P3P_10000_BASE_T
:
1454 adapter
->ahw
->port_type
= QLCNIC_XGBE
;
1456 case QLCNIC_BRDTYPE_P3P_REF_QG
:
1457 case QLCNIC_BRDTYPE_P3P_4_GB
:
1458 case QLCNIC_BRDTYPE_P3P_4_GB_MM
:
1459 adapter
->ahw
->port_type
= QLCNIC_GBE
;
1461 case QLCNIC_BRDTYPE_P3P_10G_TP
:
1462 adapter
->ahw
->port_type
= (adapter
->portnum
< 2) ?
1463 QLCNIC_XGBE
: QLCNIC_GBE
;
1466 dev_err(&pdev
->dev
, "unknown board type %x\n", board_type
);
1467 adapter
->ahw
->port_type
= QLCNIC_XGBE
;
1475 qlcnic_wol_supported(struct qlcnic_adapter
*adapter
)
1479 wol_cfg
= QLCRD32(adapter
, QLCNIC_WOL_CONFIG_NV
);
1480 if (wol_cfg
& (1UL << adapter
->portnum
)) {
1481 wol_cfg
= QLCRD32(adapter
, QLCNIC_WOL_CONFIG
);
1482 if (wol_cfg
& (1 << adapter
->portnum
))
1489 int qlcnic_82xx_config_led(struct qlcnic_adapter
*adapter
, u32 state
, u32 rate
)
1491 struct qlcnic_nic_req req
;
1495 memset(&req
, 0, sizeof(struct qlcnic_nic_req
));
1496 req
.qhdr
= cpu_to_le64(QLCNIC_HOST_REQUEST
<< 23);
1498 word
= QLCNIC_H2C_OPCODE_CONFIG_LED
| ((u64
)adapter
->portnum
<< 16);
1499 req
.req_hdr
= cpu_to_le64(word
);
1501 req
.words
[0] = cpu_to_le64(((u64
)rate
<< 32) | adapter
->portnum
);
1502 req
.words
[1] = cpu_to_le64(state
);
1504 rv
= qlcnic_send_cmd_descs(adapter
, (struct cmd_desc_type0
*)&req
, 1);
1506 dev_err(&adapter
->pdev
->dev
, "LED configuration failed.\n");
1511 int qlcnic_get_beacon_state(struct qlcnic_adapter
*adapter
, u8
*h_state
)
1513 struct qlcnic_cmd_args cmd
;
1516 err
= qlcnic_alloc_mbx_args(&cmd
, adapter
, QLCNIC_CMD_GET_LED_STATUS
);
1518 err
= qlcnic_issue_cmd(adapter
, &cmd
);
1520 *h_state
= cmd
.rsp
.arg
[1];
1522 qlcnic_free_mbx_args(&cmd
);
1526 void qlcnic_82xx_get_func_no(struct qlcnic_adapter
*adapter
)
1528 void __iomem
*msix_base_addr
;
1532 pci_read_config_dword(adapter
->pdev
, QLCNIC_MSIX_TABLE_OFFSET
, &func
);
1533 msix_base_addr
= adapter
->ahw
->pci_base0
+ QLCNIC_MSIX_BASE
;
1534 msix_base
= readl(msix_base_addr
);
1535 func
= (func
- msix_base
) / QLCNIC_MSIX_TBL_PGSIZE
;
1536 adapter
->ahw
->pci_func
= func
;
1539 void qlcnic_82xx_read_crb(struct qlcnic_adapter
*adapter
, char *buf
,
1540 loff_t offset
, size_t size
)
1545 if (ADDR_IN_RANGE(offset
, QLCNIC_PCI_CAMQM
, QLCNIC_PCI_CAMQM_END
)) {
1546 qlcnic_pci_camqm_read_2M(adapter
, offset
, &qmdata
);
1547 memcpy(buf
, &qmdata
, size
);
1549 data
= QLCRD32(adapter
, offset
);
1550 memcpy(buf
, &data
, size
);
1554 void qlcnic_82xx_write_crb(struct qlcnic_adapter
*adapter
, char *buf
,
1555 loff_t offset
, size_t size
)
1560 if (ADDR_IN_RANGE(offset
, QLCNIC_PCI_CAMQM
, QLCNIC_PCI_CAMQM_END
)) {
1561 memcpy(&qmdata
, buf
, size
);
1562 qlcnic_pci_camqm_write_2M(adapter
, offset
, qmdata
);
1564 memcpy(&data
, buf
, size
);
1565 QLCWR32(adapter
, offset
, data
);
1569 int qlcnic_82xx_api_lock(struct qlcnic_adapter
*adapter
)
1571 return qlcnic_pcie_sem_lock(adapter
, 5, 0);
1574 void qlcnic_82xx_api_unlock(struct qlcnic_adapter
*adapter
)
1576 qlcnic_pcie_sem_unlock(adapter
, 5);
1579 int qlcnic_82xx_shutdown(struct pci_dev
*pdev
)
1581 struct qlcnic_adapter
*adapter
= pci_get_drvdata(pdev
);
1582 struct net_device
*netdev
= adapter
->netdev
;
1585 netif_device_detach(netdev
);
1587 qlcnic_cancel_idc_work(adapter
);
1589 if (netif_running(netdev
))
1590 qlcnic_down(adapter
, netdev
);
1592 qlcnic_clr_all_drv_state(adapter
, 0);
1594 clear_bit(__QLCNIC_RESETTING
, &adapter
->state
);
1596 retval
= pci_save_state(pdev
);
1600 if (qlcnic_wol_supported(adapter
)) {
1601 pci_enable_wake(pdev
, PCI_D3cold
, 1);
1602 pci_enable_wake(pdev
, PCI_D3hot
, 1);
1608 int qlcnic_82xx_resume(struct qlcnic_adapter
*adapter
)
1610 struct net_device
*netdev
= adapter
->netdev
;
1613 err
= qlcnic_start_firmware(adapter
);
1615 dev_err(&adapter
->pdev
->dev
, "failed to start firmware\n");
1619 if (netif_running(netdev
)) {
1620 err
= qlcnic_up(adapter
, netdev
);
1622 qlcnic_restore_indev_addr(netdev
, NETDEV_UP
);
1625 netif_device_attach(netdev
);
1626 qlcnic_schedule_work(adapter
, qlcnic_fw_poll_work
, FW_POLL_DELAY
);