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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next
[deliverable/linux.git] / drivers / net / ethernet / realtek / 8139cp.c
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
51 #define DRV_NAME "8139cp"
52 #define DRV_VERSION "1.3"
53 #define DRV_RELDATE "Mar 22, 2004"
54
55
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/interrupt.h>
64 #include <linux/pci.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/delay.h>
67 #include <linux/ethtool.h>
68 #include <linux/gfp.h>
69 #include <linux/mii.h>
70 #include <linux/if_vlan.h>
71 #include <linux/crc32.h>
72 #include <linux/in.h>
73 #include <linux/ip.h>
74 #include <linux/tcp.h>
75 #include <linux/udp.h>
76 #include <linux/cache.h>
77 #include <asm/io.h>
78 #include <asm/irq.h>
79 #include <asm/uaccess.h>
80
81 /* These identify the driver base version and may not be removed. */
82 static char version[] =
83 DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
84
85 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
86 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
87 MODULE_VERSION(DRV_VERSION);
88 MODULE_LICENSE("GPL");
89
90 static int debug = -1;
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
93
94 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
95 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
96 static int multicast_filter_limit = 32;
97 module_param(multicast_filter_limit, int, 0);
98 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
99
100 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
101 NETIF_MSG_PROBE | \
102 NETIF_MSG_LINK)
103 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
104 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
105 #define CP_REGS_SIZE (0xff + 1)
106 #define CP_REGS_VER 1 /* version 1 */
107 #define CP_RX_RING_SIZE 64
108 #define CP_TX_RING_SIZE 64
109 #define CP_RING_BYTES \
110 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
111 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
112 CP_STATS_SIZE)
113 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
114 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
115 #define TX_BUFFS_AVAIL(CP) \
116 (((CP)->tx_tail <= (CP)->tx_head) ? \
117 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
118 (CP)->tx_tail - (CP)->tx_head - 1)
119
120 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
121 #define CP_INTERNAL_PHY 32
122
123 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
124 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
125 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
126 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
128
129 /* Time in jiffies before concluding the transmitter is hung. */
130 #define TX_TIMEOUT (6*HZ)
131
132 /* hardware minimum and maximum for a single frame's data payload */
133 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
134 #define CP_MAX_MTU 4096
135
136 enum {
137 /* NIC register offsets */
138 MAC0 = 0x00, /* Ethernet hardware address. */
139 MAR0 = 0x08, /* Multicast filter. */
140 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
141 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
142 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
143 Cmd = 0x37, /* Command register */
144 IntrMask = 0x3C, /* Interrupt mask */
145 IntrStatus = 0x3E, /* Interrupt status */
146 TxConfig = 0x40, /* Tx configuration */
147 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
148 RxConfig = 0x44, /* Rx configuration */
149 RxMissed = 0x4C, /* 24 bits valid, write clears */
150 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
151 Config1 = 0x52, /* Config1 */
152 Config3 = 0x59, /* Config3 */
153 Config4 = 0x5A, /* Config4 */
154 MultiIntr = 0x5C, /* Multiple interrupt select */
155 BasicModeCtrl = 0x62, /* MII BMCR */
156 BasicModeStatus = 0x64, /* MII BMSR */
157 NWayAdvert = 0x66, /* MII ADVERTISE */
158 NWayLPAR = 0x68, /* MII LPA */
159 NWayExpansion = 0x6A, /* MII Expansion */
160 Config5 = 0xD8, /* Config5 */
161 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
162 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
163 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
164 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
165 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
166 TxThresh = 0xEC, /* Early Tx threshold */
167 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
168 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
169
170 /* Tx and Rx status descriptors */
171 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
172 RingEnd = (1 << 30), /* End of descriptor ring */
173 FirstFrag = (1 << 29), /* First segment of a packet */
174 LastFrag = (1 << 28), /* Final segment of a packet */
175 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
176 MSSShift = 16, /* MSS value position */
177 MSSMask = 0xfff, /* MSS value: 11 bits */
178 TxError = (1 << 23), /* Tx error summary */
179 RxError = (1 << 20), /* Rx error summary */
180 IPCS = (1 << 18), /* Calculate IP checksum */
181 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
182 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
183 TxVlanTag = (1 << 17), /* Add VLAN tag */
184 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
185 IPFail = (1 << 15), /* IP checksum failed */
186 UDPFail = (1 << 14), /* UDP/IP checksum failed */
187 TCPFail = (1 << 13), /* TCP/IP checksum failed */
188 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
189 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
190 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
191 RxProtoTCP = 1,
192 RxProtoUDP = 2,
193 RxProtoIP = 3,
194 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
195 TxOWC = (1 << 22), /* Tx Out-of-window collision */
196 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
197 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
198 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
199 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
200 RxErrFrame = (1 << 27), /* Rx frame alignment error */
201 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
202 RxErrCRC = (1 << 18), /* Rx CRC error */
203 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
204 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
205 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
206
207 /* StatsAddr register */
208 DumpStats = (1 << 3), /* Begin stats dump */
209
210 /* RxConfig register */
211 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
212 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
213 AcceptErr = 0x20, /* Accept packets with CRC errors */
214 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
215 AcceptBroadcast = 0x08, /* Accept broadcast packets */
216 AcceptMulticast = 0x04, /* Accept multicast packets */
217 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
218 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
219
220 /* IntrMask / IntrStatus registers */
221 PciErr = (1 << 15), /* System error on the PCI bus */
222 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
223 LenChg = (1 << 13), /* Cable length change */
224 SWInt = (1 << 8), /* Software-requested interrupt */
225 TxEmpty = (1 << 7), /* No Tx descriptors available */
226 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
227 LinkChg = (1 << 5), /* Packet underrun, or link change */
228 RxEmpty = (1 << 4), /* No Rx descriptors available */
229 TxErr = (1 << 3), /* Tx error */
230 TxOK = (1 << 2), /* Tx packet sent */
231 RxErr = (1 << 1), /* Rx error */
232 RxOK = (1 << 0), /* Rx packet received */
233 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
234 but hardware likes to raise it */
235
236 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
237 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
238 RxErr | RxOK | IntrResvd,
239
240 /* C mode command register */
241 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
242 RxOn = (1 << 3), /* Rx mode enable */
243 TxOn = (1 << 2), /* Tx mode enable */
244
245 /* C+ mode command register */
246 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
247 RxChkSum = (1 << 5), /* Rx checksum offload enable */
248 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
249 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
250 CpRxOn = (1 << 1), /* Rx mode enable */
251 CpTxOn = (1 << 0), /* Tx mode enable */
252
253 /* Cfg9436 EEPROM control register */
254 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
255 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
256
257 /* TxConfig register */
258 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
259 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
260
261 /* Early Tx Threshold register */
262 TxThreshMask = 0x3f, /* Mask bits 5-0 */
263 TxThreshMax = 2048, /* Max early Tx threshold */
264
265 /* Config1 register */
266 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
267 LWACT = (1 << 4), /* LWAKE active mode */
268 PMEnable = (1 << 0), /* Enable various PM features of chip */
269
270 /* Config3 register */
271 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
272 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
273 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
274
275 /* Config4 register */
276 LWPTN = (1 << 1), /* LWAKE Pattern */
277 LWPME = (1 << 4), /* LANWAKE vs PMEB */
278
279 /* Config5 register */
280 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
281 MWF = (1 << 5), /* Accept Multicast wakeup frame */
282 UWF = (1 << 4), /* Accept Unicast wakeup frame */
283 LANWake = (1 << 1), /* Enable LANWake signal */
284 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
285
286 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
287 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
288 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
289 };
290
291 static const unsigned int cp_rx_config =
292 (RX_FIFO_THRESH << RxCfgFIFOShift) |
293 (RX_DMA_BURST << RxCfgDMAShift);
294
295 struct cp_desc {
296 __le32 opts1;
297 __le32 opts2;
298 __le64 addr;
299 };
300
301 struct cp_dma_stats {
302 __le64 tx_ok;
303 __le64 rx_ok;
304 __le64 tx_err;
305 __le32 rx_err;
306 __le16 rx_fifo;
307 __le16 frame_align;
308 __le32 tx_ok_1col;
309 __le32 tx_ok_mcol;
310 __le64 rx_ok_phys;
311 __le64 rx_ok_bcast;
312 __le32 rx_ok_mcast;
313 __le16 tx_abort;
314 __le16 tx_underrun;
315 } __packed;
316
317 struct cp_extra_stats {
318 unsigned long rx_frags;
319 };
320
321 struct cp_private {
322 void __iomem *regs;
323 struct net_device *dev;
324 spinlock_t lock;
325 u32 msg_enable;
326
327 struct napi_struct napi;
328
329 struct pci_dev *pdev;
330 u32 rx_config;
331 u16 cpcmd;
332
333 struct cp_extra_stats cp_stats;
334
335 unsigned rx_head ____cacheline_aligned;
336 unsigned rx_tail;
337 struct cp_desc *rx_ring;
338 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
339
340 unsigned tx_head ____cacheline_aligned;
341 unsigned tx_tail;
342 struct cp_desc *tx_ring;
343 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
344
345 unsigned rx_buf_sz;
346 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
347
348 dma_addr_t ring_dma;
349
350 struct mii_if_info mii_if;
351 };
352
353 #define cpr8(reg) readb(cp->regs + (reg))
354 #define cpr16(reg) readw(cp->regs + (reg))
355 #define cpr32(reg) readl(cp->regs + (reg))
356 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
357 #define cpw16(reg,val) writew((val), cp->regs + (reg))
358 #define cpw32(reg,val) writel((val), cp->regs + (reg))
359 #define cpw8_f(reg,val) do { \
360 writeb((val), cp->regs + (reg)); \
361 readb(cp->regs + (reg)); \
362 } while (0)
363 #define cpw16_f(reg,val) do { \
364 writew((val), cp->regs + (reg)); \
365 readw(cp->regs + (reg)); \
366 } while (0)
367 #define cpw32_f(reg,val) do { \
368 writel((val), cp->regs + (reg)); \
369 readl(cp->regs + (reg)); \
370 } while (0)
371
372
373 static void __cp_set_rx_mode (struct net_device *dev);
374 static void cp_tx (struct cp_private *cp);
375 static void cp_clean_rings (struct cp_private *cp);
376 #ifdef CONFIG_NET_POLL_CONTROLLER
377 static void cp_poll_controller(struct net_device *dev);
378 #endif
379 static int cp_get_eeprom_len(struct net_device *dev);
380 static int cp_get_eeprom(struct net_device *dev,
381 struct ethtool_eeprom *eeprom, u8 *data);
382 static int cp_set_eeprom(struct net_device *dev,
383 struct ethtool_eeprom *eeprom, u8 *data);
384
385 static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
386 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
387 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
388 { },
389 };
390 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
391
392 static struct {
393 const char str[ETH_GSTRING_LEN];
394 } ethtool_stats_keys[] = {
395 { "tx_ok" },
396 { "rx_ok" },
397 { "tx_err" },
398 { "rx_err" },
399 { "rx_fifo" },
400 { "frame_align" },
401 { "tx_ok_1col" },
402 { "tx_ok_mcol" },
403 { "rx_ok_phys" },
404 { "rx_ok_bcast" },
405 { "rx_ok_mcast" },
406 { "tx_abort" },
407 { "tx_underrun" },
408 { "rx_frags" },
409 };
410
411
412 static inline void cp_set_rxbufsize (struct cp_private *cp)
413 {
414 unsigned int mtu = cp->dev->mtu;
415
416 if (mtu > ETH_DATA_LEN)
417 /* MTU + ethernet header + FCS + optional VLAN tag */
418 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
419 else
420 cp->rx_buf_sz = PKT_BUF_SZ;
421 }
422
423 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
424 struct cp_desc *desc)
425 {
426 u32 opts2 = le32_to_cpu(desc->opts2);
427
428 skb->protocol = eth_type_trans (skb, cp->dev);
429
430 cp->dev->stats.rx_packets++;
431 cp->dev->stats.rx_bytes += skb->len;
432
433 if (opts2 & RxVlanTagged)
434 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
435
436 napi_gro_receive(&cp->napi, skb);
437 }
438
439 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
440 u32 status, u32 len)
441 {
442 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
443 rx_tail, status, len);
444 cp->dev->stats.rx_errors++;
445 if (status & RxErrFrame)
446 cp->dev->stats.rx_frame_errors++;
447 if (status & RxErrCRC)
448 cp->dev->stats.rx_crc_errors++;
449 if ((status & RxErrRunt) || (status & RxErrLong))
450 cp->dev->stats.rx_length_errors++;
451 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
452 cp->dev->stats.rx_length_errors++;
453 if (status & RxErrFIFO)
454 cp->dev->stats.rx_fifo_errors++;
455 }
456
457 static inline unsigned int cp_rx_csum_ok (u32 status)
458 {
459 unsigned int protocol = (status >> 16) & 0x3;
460
461 if (((protocol == RxProtoTCP) && !(status & TCPFail)) ||
462 ((protocol == RxProtoUDP) && !(status & UDPFail)))
463 return 1;
464 else
465 return 0;
466 }
467
468 static int cp_rx_poll(struct napi_struct *napi, int budget)
469 {
470 struct cp_private *cp = container_of(napi, struct cp_private, napi);
471 struct net_device *dev = cp->dev;
472 unsigned int rx_tail = cp->rx_tail;
473 int rx;
474
475 rx_status_loop:
476 rx = 0;
477 cpw16(IntrStatus, cp_rx_intr_mask);
478
479 while (1) {
480 u32 status, len;
481 dma_addr_t mapping;
482 struct sk_buff *skb, *new_skb;
483 struct cp_desc *desc;
484 const unsigned buflen = cp->rx_buf_sz;
485
486 skb = cp->rx_skb[rx_tail];
487 BUG_ON(!skb);
488
489 desc = &cp->rx_ring[rx_tail];
490 status = le32_to_cpu(desc->opts1);
491 if (status & DescOwn)
492 break;
493
494 len = (status & 0x1fff) - 4;
495 mapping = le64_to_cpu(desc->addr);
496
497 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
498 /* we don't support incoming fragmented frames.
499 * instead, we attempt to ensure that the
500 * pre-allocated RX skbs are properly sized such
501 * that RX fragments are never encountered
502 */
503 cp_rx_err_acct(cp, rx_tail, status, len);
504 dev->stats.rx_dropped++;
505 cp->cp_stats.rx_frags++;
506 goto rx_next;
507 }
508
509 if (status & (RxError | RxErrFIFO)) {
510 cp_rx_err_acct(cp, rx_tail, status, len);
511 goto rx_next;
512 }
513
514 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
515 rx_tail, status, len);
516
517 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
518 if (!new_skb) {
519 dev->stats.rx_dropped++;
520 goto rx_next;
521 }
522
523 dma_unmap_single(&cp->pdev->dev, mapping,
524 buflen, PCI_DMA_FROMDEVICE);
525
526 /* Handle checksum offloading for incoming packets. */
527 if (cp_rx_csum_ok(status))
528 skb->ip_summed = CHECKSUM_UNNECESSARY;
529 else
530 skb_checksum_none_assert(skb);
531
532 skb_put(skb, len);
533
534 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
535 PCI_DMA_FROMDEVICE);
536 cp->rx_skb[rx_tail] = new_skb;
537
538 cp_rx_skb(cp, skb, desc);
539 rx++;
540
541 rx_next:
542 cp->rx_ring[rx_tail].opts2 = 0;
543 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
544 if (rx_tail == (CP_RX_RING_SIZE - 1))
545 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
546 cp->rx_buf_sz);
547 else
548 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
549 rx_tail = NEXT_RX(rx_tail);
550
551 if (rx >= budget)
552 break;
553 }
554
555 cp->rx_tail = rx_tail;
556
557 /* if we did not reach work limit, then we're done with
558 * this round of polling
559 */
560 if (rx < budget) {
561 unsigned long flags;
562
563 if (cpr16(IntrStatus) & cp_rx_intr_mask)
564 goto rx_status_loop;
565
566 napi_gro_flush(napi, false);
567 spin_lock_irqsave(&cp->lock, flags);
568 __napi_complete(napi);
569 cpw16_f(IntrMask, cp_intr_mask);
570 spin_unlock_irqrestore(&cp->lock, flags);
571 }
572
573 return rx;
574 }
575
576 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
577 {
578 struct net_device *dev = dev_instance;
579 struct cp_private *cp;
580 u16 status;
581
582 if (unlikely(dev == NULL))
583 return IRQ_NONE;
584 cp = netdev_priv(dev);
585
586 status = cpr16(IntrStatus);
587 if (!status || (status == 0xFFFF))
588 return IRQ_NONE;
589
590 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
591 status, cpr8(Cmd), cpr16(CpCmd));
592
593 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
594
595 spin_lock(&cp->lock);
596
597 /* close possible race's with dev_close */
598 if (unlikely(!netif_running(dev))) {
599 cpw16(IntrMask, 0);
600 spin_unlock(&cp->lock);
601 return IRQ_HANDLED;
602 }
603
604 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
605 if (napi_schedule_prep(&cp->napi)) {
606 cpw16_f(IntrMask, cp_norx_intr_mask);
607 __napi_schedule(&cp->napi);
608 }
609
610 if (status & (TxOK | TxErr | TxEmpty | SWInt))
611 cp_tx(cp);
612 if (status & LinkChg)
613 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
614
615 spin_unlock(&cp->lock);
616
617 if (status & PciErr) {
618 u16 pci_status;
619
620 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
621 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
622 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
623 status, pci_status);
624
625 /* TODO: reset hardware */
626 }
627
628 return IRQ_HANDLED;
629 }
630
631 #ifdef CONFIG_NET_POLL_CONTROLLER
632 /*
633 * Polling receive - used by netconsole and other diagnostic tools
634 * to allow network i/o with interrupts disabled.
635 */
636 static void cp_poll_controller(struct net_device *dev)
637 {
638 struct cp_private *cp = netdev_priv(dev);
639 const int irq = cp->pdev->irq;
640
641 disable_irq(irq);
642 cp_interrupt(irq, dev);
643 enable_irq(irq);
644 }
645 #endif
646
647 static void cp_tx (struct cp_private *cp)
648 {
649 unsigned tx_head = cp->tx_head;
650 unsigned tx_tail = cp->tx_tail;
651 unsigned bytes_compl = 0, pkts_compl = 0;
652
653 while (tx_tail != tx_head) {
654 struct cp_desc *txd = cp->tx_ring + tx_tail;
655 struct sk_buff *skb;
656 u32 status;
657
658 rmb();
659 status = le32_to_cpu(txd->opts1);
660 if (status & DescOwn)
661 break;
662
663 skb = cp->tx_skb[tx_tail];
664 BUG_ON(!skb);
665
666 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
667 le32_to_cpu(txd->opts1) & 0xffff,
668 PCI_DMA_TODEVICE);
669
670 bytes_compl += skb->len;
671 pkts_compl++;
672
673 if (status & LastFrag) {
674 if (status & (TxError | TxFIFOUnder)) {
675 netif_dbg(cp, tx_err, cp->dev,
676 "tx err, status 0x%x\n", status);
677 cp->dev->stats.tx_errors++;
678 if (status & TxOWC)
679 cp->dev->stats.tx_window_errors++;
680 if (status & TxMaxCol)
681 cp->dev->stats.tx_aborted_errors++;
682 if (status & TxLinkFail)
683 cp->dev->stats.tx_carrier_errors++;
684 if (status & TxFIFOUnder)
685 cp->dev->stats.tx_fifo_errors++;
686 } else {
687 cp->dev->stats.collisions +=
688 ((status >> TxColCntShift) & TxColCntMask);
689 cp->dev->stats.tx_packets++;
690 cp->dev->stats.tx_bytes += skb->len;
691 netif_dbg(cp, tx_done, cp->dev,
692 "tx done, slot %d\n", tx_tail);
693 }
694 dev_kfree_skb_irq(skb);
695 }
696
697 cp->tx_skb[tx_tail] = NULL;
698
699 tx_tail = NEXT_TX(tx_tail);
700 }
701
702 cp->tx_tail = tx_tail;
703
704 netdev_completed_queue(cp->dev, pkts_compl, bytes_compl);
705 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
706 netif_wake_queue(cp->dev);
707 }
708
709 static inline u32 cp_tx_vlan_tag(struct sk_buff *skb)
710 {
711 return vlan_tx_tag_present(skb) ?
712 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
713 }
714
715 static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
716 struct net_device *dev)
717 {
718 struct cp_private *cp = netdev_priv(dev);
719 unsigned entry;
720 u32 eor, flags;
721 unsigned long intr_flags;
722 __le32 opts2;
723 int mss = 0;
724
725 spin_lock_irqsave(&cp->lock, intr_flags);
726
727 /* This is a hard error, log it. */
728 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
729 netif_stop_queue(dev);
730 spin_unlock_irqrestore(&cp->lock, intr_flags);
731 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
732 return NETDEV_TX_BUSY;
733 }
734
735 entry = cp->tx_head;
736 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
737 mss = skb_shinfo(skb)->gso_size;
738
739 opts2 = cpu_to_le32(cp_tx_vlan_tag(skb));
740
741 if (skb_shinfo(skb)->nr_frags == 0) {
742 struct cp_desc *txd = &cp->tx_ring[entry];
743 u32 len;
744 dma_addr_t mapping;
745
746 len = skb->len;
747 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
748 txd->opts2 = opts2;
749 txd->addr = cpu_to_le64(mapping);
750 wmb();
751
752 flags = eor | len | DescOwn | FirstFrag | LastFrag;
753
754 if (mss)
755 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
756 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
757 const struct iphdr *ip = ip_hdr(skb);
758 if (ip->protocol == IPPROTO_TCP)
759 flags |= IPCS | TCPCS;
760 else if (ip->protocol == IPPROTO_UDP)
761 flags |= IPCS | UDPCS;
762 else
763 WARN_ON(1); /* we need a WARN() */
764 }
765
766 txd->opts1 = cpu_to_le32(flags);
767 wmb();
768
769 cp->tx_skb[entry] = skb;
770 entry = NEXT_TX(entry);
771 } else {
772 struct cp_desc *txd;
773 u32 first_len, first_eor;
774 dma_addr_t first_mapping;
775 int frag, first_entry = entry;
776 const struct iphdr *ip = ip_hdr(skb);
777
778 /* We must give this initial chunk to the device last.
779 * Otherwise we could race with the device.
780 */
781 first_eor = eor;
782 first_len = skb_headlen(skb);
783 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
784 first_len, PCI_DMA_TODEVICE);
785 cp->tx_skb[entry] = skb;
786 entry = NEXT_TX(entry);
787
788 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
789 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
790 u32 len;
791 u32 ctrl;
792 dma_addr_t mapping;
793
794 len = skb_frag_size(this_frag);
795 mapping = dma_map_single(&cp->pdev->dev,
796 skb_frag_address(this_frag),
797 len, PCI_DMA_TODEVICE);
798 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
799
800 ctrl = eor | len | DescOwn;
801
802 if (mss)
803 ctrl |= LargeSend |
804 ((mss & MSSMask) << MSSShift);
805 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
806 if (ip->protocol == IPPROTO_TCP)
807 ctrl |= IPCS | TCPCS;
808 else if (ip->protocol == IPPROTO_UDP)
809 ctrl |= IPCS | UDPCS;
810 else
811 BUG();
812 }
813
814 if (frag == skb_shinfo(skb)->nr_frags - 1)
815 ctrl |= LastFrag;
816
817 txd = &cp->tx_ring[entry];
818 txd->opts2 = opts2;
819 txd->addr = cpu_to_le64(mapping);
820 wmb();
821
822 txd->opts1 = cpu_to_le32(ctrl);
823 wmb();
824
825 cp->tx_skb[entry] = skb;
826 entry = NEXT_TX(entry);
827 }
828
829 txd = &cp->tx_ring[first_entry];
830 txd->opts2 = opts2;
831 txd->addr = cpu_to_le64(first_mapping);
832 wmb();
833
834 if (skb->ip_summed == CHECKSUM_PARTIAL) {
835 if (ip->protocol == IPPROTO_TCP)
836 txd->opts1 = cpu_to_le32(first_eor | first_len |
837 FirstFrag | DescOwn |
838 IPCS | TCPCS);
839 else if (ip->protocol == IPPROTO_UDP)
840 txd->opts1 = cpu_to_le32(first_eor | first_len |
841 FirstFrag | DescOwn |
842 IPCS | UDPCS);
843 else
844 BUG();
845 } else
846 txd->opts1 = cpu_to_le32(first_eor | first_len |
847 FirstFrag | DescOwn);
848 wmb();
849 }
850 cp->tx_head = entry;
851
852 netdev_sent_queue(dev, skb->len);
853 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
854 entry, skb->len);
855 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
856 netif_stop_queue(dev);
857
858 spin_unlock_irqrestore(&cp->lock, intr_flags);
859
860 cpw8(TxPoll, NormalTxPoll);
861
862 return NETDEV_TX_OK;
863 }
864
865 /* Set or clear the multicast filter for this adaptor.
866 This routine is not state sensitive and need not be SMP locked. */
867
868 static void __cp_set_rx_mode (struct net_device *dev)
869 {
870 struct cp_private *cp = netdev_priv(dev);
871 u32 mc_filter[2]; /* Multicast hash filter */
872 int rx_mode;
873
874 /* Note: do not reorder, GCC is clever about common statements. */
875 if (dev->flags & IFF_PROMISC) {
876 /* Unconditionally log net taps. */
877 rx_mode =
878 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
879 AcceptAllPhys;
880 mc_filter[1] = mc_filter[0] = 0xffffffff;
881 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
882 (dev->flags & IFF_ALLMULTI)) {
883 /* Too many to filter perfectly -- accept all multicasts. */
884 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
885 mc_filter[1] = mc_filter[0] = 0xffffffff;
886 } else {
887 struct netdev_hw_addr *ha;
888 rx_mode = AcceptBroadcast | AcceptMyPhys;
889 mc_filter[1] = mc_filter[0] = 0;
890 netdev_for_each_mc_addr(ha, dev) {
891 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
892
893 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
894 rx_mode |= AcceptMulticast;
895 }
896 }
897
898 /* We can safely update without stopping the chip. */
899 cp->rx_config = cp_rx_config | rx_mode;
900 cpw32_f(RxConfig, cp->rx_config);
901
902 cpw32_f (MAR0 + 0, mc_filter[0]);
903 cpw32_f (MAR0 + 4, mc_filter[1]);
904 }
905
906 static void cp_set_rx_mode (struct net_device *dev)
907 {
908 unsigned long flags;
909 struct cp_private *cp = netdev_priv(dev);
910
911 spin_lock_irqsave (&cp->lock, flags);
912 __cp_set_rx_mode(dev);
913 spin_unlock_irqrestore (&cp->lock, flags);
914 }
915
916 static void __cp_get_stats(struct cp_private *cp)
917 {
918 /* only lower 24 bits valid; write any value to clear */
919 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
920 cpw32 (RxMissed, 0);
921 }
922
923 static struct net_device_stats *cp_get_stats(struct net_device *dev)
924 {
925 struct cp_private *cp = netdev_priv(dev);
926 unsigned long flags;
927
928 /* The chip only need report frame silently dropped. */
929 spin_lock_irqsave(&cp->lock, flags);
930 if (netif_running(dev) && netif_device_present(dev))
931 __cp_get_stats(cp);
932 spin_unlock_irqrestore(&cp->lock, flags);
933
934 return &dev->stats;
935 }
936
937 static void cp_stop_hw (struct cp_private *cp)
938 {
939 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
940 cpw16_f(IntrMask, 0);
941 cpw8(Cmd, 0);
942 cpw16_f(CpCmd, 0);
943 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
944
945 cp->rx_tail = 0;
946 cp->tx_head = cp->tx_tail = 0;
947
948 netdev_reset_queue(cp->dev);
949 }
950
951 static void cp_reset_hw (struct cp_private *cp)
952 {
953 unsigned work = 1000;
954
955 cpw8(Cmd, CmdReset);
956
957 while (work--) {
958 if (!(cpr8(Cmd) & CmdReset))
959 return;
960
961 schedule_timeout_uninterruptible(10);
962 }
963
964 netdev_err(cp->dev, "hardware reset timeout\n");
965 }
966
967 static inline void cp_start_hw (struct cp_private *cp)
968 {
969 dma_addr_t ring_dma;
970
971 cpw16(CpCmd, cp->cpcmd);
972
973 /*
974 * These (at least TxRingAddr) need to be configured after the
975 * corresponding bits in CpCmd are enabled. Datasheet v1.6 §6.33
976 * (C+ Command Register) recommends that these and more be configured
977 * *after* the [RT]xEnable bits in CpCmd are set. And on some hardware
978 * it's been observed that the TxRingAddr is actually reset to garbage
979 * when C+ mode Tx is enabled in CpCmd.
980 */
981 cpw32_f(HiTxRingAddr, 0);
982 cpw32_f(HiTxRingAddr + 4, 0);
983
984 ring_dma = cp->ring_dma;
985 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
986 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
987
988 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
989 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
990 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
991
992 /*
993 * Strictly speaking, the datasheet says this should be enabled
994 * *before* setting the descriptor addresses. But what, then, would
995 * prevent it from doing DMA to random unconfigured addresses?
996 * This variant appears to work fine.
997 */
998 cpw8(Cmd, RxOn | TxOn);
999
1000 netdev_reset_queue(cp->dev);
1001 }
1002
1003 static void cp_enable_irq(struct cp_private *cp)
1004 {
1005 cpw16_f(IntrMask, cp_intr_mask);
1006 }
1007
1008 static void cp_init_hw (struct cp_private *cp)
1009 {
1010 struct net_device *dev = cp->dev;
1011
1012 cp_reset_hw(cp);
1013
1014 cpw8_f (Cfg9346, Cfg9346_Unlock);
1015
1016 /* Restore our idea of the MAC address. */
1017 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1018 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1019
1020 cp_start_hw(cp);
1021 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1022
1023 __cp_set_rx_mode(dev);
1024 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1025
1026 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1027 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1028 cpw8(Config3, PARMEnable);
1029 cp->wol_enabled = 0;
1030
1031 cpw8(Config5, cpr8(Config5) & PMEStatus);
1032
1033 cpw16(MultiIntr, 0);
1034
1035 cpw8_f(Cfg9346, Cfg9346_Lock);
1036 }
1037
1038 static int cp_refill_rx(struct cp_private *cp)
1039 {
1040 struct net_device *dev = cp->dev;
1041 unsigned i;
1042
1043 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1044 struct sk_buff *skb;
1045 dma_addr_t mapping;
1046
1047 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1048 if (!skb)
1049 goto err_out;
1050
1051 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1052 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1053 cp->rx_skb[i] = skb;
1054
1055 cp->rx_ring[i].opts2 = 0;
1056 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1057 if (i == (CP_RX_RING_SIZE - 1))
1058 cp->rx_ring[i].opts1 =
1059 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1060 else
1061 cp->rx_ring[i].opts1 =
1062 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1063 }
1064
1065 return 0;
1066
1067 err_out:
1068 cp_clean_rings(cp);
1069 return -ENOMEM;
1070 }
1071
1072 static void cp_init_rings_index (struct cp_private *cp)
1073 {
1074 cp->rx_tail = 0;
1075 cp->tx_head = cp->tx_tail = 0;
1076 }
1077
1078 static int cp_init_rings (struct cp_private *cp)
1079 {
1080 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1081 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1082
1083 cp_init_rings_index(cp);
1084
1085 return cp_refill_rx (cp);
1086 }
1087
1088 static int cp_alloc_rings (struct cp_private *cp)
1089 {
1090 struct device *d = &cp->pdev->dev;
1091 void *mem;
1092 int rc;
1093
1094 mem = dma_alloc_coherent(d, CP_RING_BYTES, &cp->ring_dma, GFP_KERNEL);
1095 if (!mem)
1096 return -ENOMEM;
1097
1098 cp->rx_ring = mem;
1099 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1100
1101 rc = cp_init_rings(cp);
1102 if (rc < 0)
1103 dma_free_coherent(d, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1104
1105 return rc;
1106 }
1107
1108 static void cp_clean_rings (struct cp_private *cp)
1109 {
1110 struct cp_desc *desc;
1111 unsigned i;
1112
1113 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1114 if (cp->rx_skb[i]) {
1115 desc = cp->rx_ring + i;
1116 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1117 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1118 dev_kfree_skb(cp->rx_skb[i]);
1119 }
1120 }
1121
1122 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1123 if (cp->tx_skb[i]) {
1124 struct sk_buff *skb = cp->tx_skb[i];
1125
1126 desc = cp->tx_ring + i;
1127 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1128 le32_to_cpu(desc->opts1) & 0xffff,
1129 PCI_DMA_TODEVICE);
1130 if (le32_to_cpu(desc->opts1) & LastFrag)
1131 dev_kfree_skb(skb);
1132 cp->dev->stats.tx_dropped++;
1133 }
1134 }
1135
1136 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1137 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1138
1139 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1140 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1141 }
1142
1143 static void cp_free_rings (struct cp_private *cp)
1144 {
1145 cp_clean_rings(cp);
1146 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1147 cp->ring_dma);
1148 cp->rx_ring = NULL;
1149 cp->tx_ring = NULL;
1150 }
1151
1152 static int cp_open (struct net_device *dev)
1153 {
1154 struct cp_private *cp = netdev_priv(dev);
1155 const int irq = cp->pdev->irq;
1156 int rc;
1157
1158 netif_dbg(cp, ifup, dev, "enabling interface\n");
1159
1160 rc = cp_alloc_rings(cp);
1161 if (rc)
1162 return rc;
1163
1164 napi_enable(&cp->napi);
1165
1166 cp_init_hw(cp);
1167
1168 rc = request_irq(irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1169 if (rc)
1170 goto err_out_hw;
1171
1172 cp_enable_irq(cp);
1173
1174 netif_carrier_off(dev);
1175 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1176 netif_start_queue(dev);
1177
1178 return 0;
1179
1180 err_out_hw:
1181 napi_disable(&cp->napi);
1182 cp_stop_hw(cp);
1183 cp_free_rings(cp);
1184 return rc;
1185 }
1186
1187 static int cp_close (struct net_device *dev)
1188 {
1189 struct cp_private *cp = netdev_priv(dev);
1190 unsigned long flags;
1191
1192 napi_disable(&cp->napi);
1193
1194 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1195
1196 spin_lock_irqsave(&cp->lock, flags);
1197
1198 netif_stop_queue(dev);
1199 netif_carrier_off(dev);
1200
1201 cp_stop_hw(cp);
1202
1203 spin_unlock_irqrestore(&cp->lock, flags);
1204
1205 free_irq(cp->pdev->irq, dev);
1206
1207 cp_free_rings(cp);
1208 return 0;
1209 }
1210
1211 static void cp_tx_timeout(struct net_device *dev)
1212 {
1213 struct cp_private *cp = netdev_priv(dev);
1214 unsigned long flags;
1215 int rc;
1216
1217 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1218 cpr8(Cmd), cpr16(CpCmd),
1219 cpr16(IntrStatus), cpr16(IntrMask));
1220
1221 spin_lock_irqsave(&cp->lock, flags);
1222
1223 cp_stop_hw(cp);
1224 cp_clean_rings(cp);
1225 rc = cp_init_rings(cp);
1226 cp_start_hw(cp);
1227 cp_enable_irq(cp);
1228
1229 netif_wake_queue(dev);
1230
1231 spin_unlock_irqrestore(&cp->lock, flags);
1232 }
1233
1234 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1235 {
1236 struct cp_private *cp = netdev_priv(dev);
1237
1238 /* check for invalid MTU, according to hardware limits */
1239 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1240 return -EINVAL;
1241
1242 /* if network interface not up, no need for complexity */
1243 if (!netif_running(dev)) {
1244 dev->mtu = new_mtu;
1245 cp_set_rxbufsize(cp); /* set new rx buf size */
1246 return 0;
1247 }
1248
1249 /* network IS up, close it, reset MTU, and come up again. */
1250 cp_close(dev);
1251 dev->mtu = new_mtu;
1252 cp_set_rxbufsize(cp);
1253 return cp_open(dev);
1254 }
1255
1256 static const char mii_2_8139_map[8] = {
1257 BasicModeCtrl,
1258 BasicModeStatus,
1259 0,
1260 0,
1261 NWayAdvert,
1262 NWayLPAR,
1263 NWayExpansion,
1264 0
1265 };
1266
1267 static int mdio_read(struct net_device *dev, int phy_id, int location)
1268 {
1269 struct cp_private *cp = netdev_priv(dev);
1270
1271 return location < 8 && mii_2_8139_map[location] ?
1272 readw(cp->regs + mii_2_8139_map[location]) : 0;
1273 }
1274
1275
1276 static void mdio_write(struct net_device *dev, int phy_id, int location,
1277 int value)
1278 {
1279 struct cp_private *cp = netdev_priv(dev);
1280
1281 if (location == 0) {
1282 cpw8(Cfg9346, Cfg9346_Unlock);
1283 cpw16(BasicModeCtrl, value);
1284 cpw8(Cfg9346, Cfg9346_Lock);
1285 } else if (location < 8 && mii_2_8139_map[location])
1286 cpw16(mii_2_8139_map[location], value);
1287 }
1288
1289 /* Set the ethtool Wake-on-LAN settings */
1290 static int netdev_set_wol (struct cp_private *cp,
1291 const struct ethtool_wolinfo *wol)
1292 {
1293 u8 options;
1294
1295 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1296 /* If WOL is being disabled, no need for complexity */
1297 if (wol->wolopts) {
1298 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1299 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1300 }
1301
1302 cpw8 (Cfg9346, Cfg9346_Unlock);
1303 cpw8 (Config3, options);
1304 cpw8 (Cfg9346, Cfg9346_Lock);
1305
1306 options = 0; /* Paranoia setting */
1307 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1308 /* If WOL is being disabled, no need for complexity */
1309 if (wol->wolopts) {
1310 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1311 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1312 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1313 }
1314
1315 cpw8 (Config5, options);
1316
1317 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1318
1319 return 0;
1320 }
1321
1322 /* Get the ethtool Wake-on-LAN settings */
1323 static void netdev_get_wol (struct cp_private *cp,
1324 struct ethtool_wolinfo *wol)
1325 {
1326 u8 options;
1327
1328 wol->wolopts = 0; /* Start from scratch */
1329 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1330 WAKE_MCAST | WAKE_UCAST;
1331 /* We don't need to go on if WOL is disabled */
1332 if (!cp->wol_enabled) return;
1333
1334 options = cpr8 (Config3);
1335 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1336 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1337
1338 options = 0; /* Paranoia setting */
1339 options = cpr8 (Config5);
1340 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1341 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1342 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1343 }
1344
1345 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1346 {
1347 struct cp_private *cp = netdev_priv(dev);
1348
1349 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1350 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1351 strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
1352 }
1353
1354 static void cp_get_ringparam(struct net_device *dev,
1355 struct ethtool_ringparam *ring)
1356 {
1357 ring->rx_max_pending = CP_RX_RING_SIZE;
1358 ring->tx_max_pending = CP_TX_RING_SIZE;
1359 ring->rx_pending = CP_RX_RING_SIZE;
1360 ring->tx_pending = CP_TX_RING_SIZE;
1361 }
1362
1363 static int cp_get_regs_len(struct net_device *dev)
1364 {
1365 return CP_REGS_SIZE;
1366 }
1367
1368 static int cp_get_sset_count (struct net_device *dev, int sset)
1369 {
1370 switch (sset) {
1371 case ETH_SS_STATS:
1372 return CP_NUM_STATS;
1373 default:
1374 return -EOPNOTSUPP;
1375 }
1376 }
1377
1378 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1379 {
1380 struct cp_private *cp = netdev_priv(dev);
1381 int rc;
1382 unsigned long flags;
1383
1384 spin_lock_irqsave(&cp->lock, flags);
1385 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1386 spin_unlock_irqrestore(&cp->lock, flags);
1387
1388 return rc;
1389 }
1390
1391 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1392 {
1393 struct cp_private *cp = netdev_priv(dev);
1394 int rc;
1395 unsigned long flags;
1396
1397 spin_lock_irqsave(&cp->lock, flags);
1398 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1399 spin_unlock_irqrestore(&cp->lock, flags);
1400
1401 return rc;
1402 }
1403
1404 static int cp_nway_reset(struct net_device *dev)
1405 {
1406 struct cp_private *cp = netdev_priv(dev);
1407 return mii_nway_restart(&cp->mii_if);
1408 }
1409
1410 static u32 cp_get_msglevel(struct net_device *dev)
1411 {
1412 struct cp_private *cp = netdev_priv(dev);
1413 return cp->msg_enable;
1414 }
1415
1416 static void cp_set_msglevel(struct net_device *dev, u32 value)
1417 {
1418 struct cp_private *cp = netdev_priv(dev);
1419 cp->msg_enable = value;
1420 }
1421
1422 static int cp_set_features(struct net_device *dev, netdev_features_t features)
1423 {
1424 struct cp_private *cp = netdev_priv(dev);
1425 unsigned long flags;
1426
1427 if (!((dev->features ^ features) & NETIF_F_RXCSUM))
1428 return 0;
1429
1430 spin_lock_irqsave(&cp->lock, flags);
1431
1432 if (features & NETIF_F_RXCSUM)
1433 cp->cpcmd |= RxChkSum;
1434 else
1435 cp->cpcmd &= ~RxChkSum;
1436
1437 if (features & NETIF_F_HW_VLAN_RX)
1438 cp->cpcmd |= RxVlanOn;
1439 else
1440 cp->cpcmd &= ~RxVlanOn;
1441
1442 cpw16_f(CpCmd, cp->cpcmd);
1443 spin_unlock_irqrestore(&cp->lock, flags);
1444
1445 return 0;
1446 }
1447
1448 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1449 void *p)
1450 {
1451 struct cp_private *cp = netdev_priv(dev);
1452 unsigned long flags;
1453
1454 if (regs->len < CP_REGS_SIZE)
1455 return /* -EINVAL */;
1456
1457 regs->version = CP_REGS_VER;
1458
1459 spin_lock_irqsave(&cp->lock, flags);
1460 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1461 spin_unlock_irqrestore(&cp->lock, flags);
1462 }
1463
1464 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1465 {
1466 struct cp_private *cp = netdev_priv(dev);
1467 unsigned long flags;
1468
1469 spin_lock_irqsave (&cp->lock, flags);
1470 netdev_get_wol (cp, wol);
1471 spin_unlock_irqrestore (&cp->lock, flags);
1472 }
1473
1474 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1475 {
1476 struct cp_private *cp = netdev_priv(dev);
1477 unsigned long flags;
1478 int rc;
1479
1480 spin_lock_irqsave (&cp->lock, flags);
1481 rc = netdev_set_wol (cp, wol);
1482 spin_unlock_irqrestore (&cp->lock, flags);
1483
1484 return rc;
1485 }
1486
1487 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1488 {
1489 switch (stringset) {
1490 case ETH_SS_STATS:
1491 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1492 break;
1493 default:
1494 BUG();
1495 break;
1496 }
1497 }
1498
1499 static void cp_get_ethtool_stats (struct net_device *dev,
1500 struct ethtool_stats *estats, u64 *tmp_stats)
1501 {
1502 struct cp_private *cp = netdev_priv(dev);
1503 struct cp_dma_stats *nic_stats;
1504 dma_addr_t dma;
1505 int i;
1506
1507 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1508 &dma, GFP_KERNEL);
1509 if (!nic_stats)
1510 return;
1511
1512 /* begin NIC statistics dump */
1513 cpw32(StatsAddr + 4, (u64)dma >> 32);
1514 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1515 cpr32(StatsAddr);
1516
1517 for (i = 0; i < 1000; i++) {
1518 if ((cpr32(StatsAddr) & DumpStats) == 0)
1519 break;
1520 udelay(10);
1521 }
1522 cpw32(StatsAddr, 0);
1523 cpw32(StatsAddr + 4, 0);
1524 cpr32(StatsAddr);
1525
1526 i = 0;
1527 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1528 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1529 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1530 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1531 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1532 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1533 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1534 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1535 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1536 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1537 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1538 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1539 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1540 tmp_stats[i++] = cp->cp_stats.rx_frags;
1541 BUG_ON(i != CP_NUM_STATS);
1542
1543 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1544 }
1545
1546 static const struct ethtool_ops cp_ethtool_ops = {
1547 .get_drvinfo = cp_get_drvinfo,
1548 .get_regs_len = cp_get_regs_len,
1549 .get_sset_count = cp_get_sset_count,
1550 .get_settings = cp_get_settings,
1551 .set_settings = cp_set_settings,
1552 .nway_reset = cp_nway_reset,
1553 .get_link = ethtool_op_get_link,
1554 .get_msglevel = cp_get_msglevel,
1555 .set_msglevel = cp_set_msglevel,
1556 .get_regs = cp_get_regs,
1557 .get_wol = cp_get_wol,
1558 .set_wol = cp_set_wol,
1559 .get_strings = cp_get_strings,
1560 .get_ethtool_stats = cp_get_ethtool_stats,
1561 .get_eeprom_len = cp_get_eeprom_len,
1562 .get_eeprom = cp_get_eeprom,
1563 .set_eeprom = cp_set_eeprom,
1564 .get_ringparam = cp_get_ringparam,
1565 };
1566
1567 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1568 {
1569 struct cp_private *cp = netdev_priv(dev);
1570 int rc;
1571 unsigned long flags;
1572
1573 if (!netif_running(dev))
1574 return -EINVAL;
1575
1576 spin_lock_irqsave(&cp->lock, flags);
1577 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1578 spin_unlock_irqrestore(&cp->lock, flags);
1579 return rc;
1580 }
1581
1582 static int cp_set_mac_address(struct net_device *dev, void *p)
1583 {
1584 struct cp_private *cp = netdev_priv(dev);
1585 struct sockaddr *addr = p;
1586
1587 if (!is_valid_ether_addr(addr->sa_data))
1588 return -EADDRNOTAVAIL;
1589
1590 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1591
1592 spin_lock_irq(&cp->lock);
1593
1594 cpw8_f(Cfg9346, Cfg9346_Unlock);
1595 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1596 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1597 cpw8_f(Cfg9346, Cfg9346_Lock);
1598
1599 spin_unlock_irq(&cp->lock);
1600
1601 return 0;
1602 }
1603
1604 /* Serial EEPROM section. */
1605
1606 /* EEPROM_Ctrl bits. */
1607 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1608 #define EE_CS 0x08 /* EEPROM chip select. */
1609 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1610 #define EE_WRITE_0 0x00
1611 #define EE_WRITE_1 0x02
1612 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1613 #define EE_ENB (0x80 | EE_CS)
1614
1615 /* Delay between EEPROM clock transitions.
1616 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1617 */
1618
1619 #define eeprom_delay() readb(ee_addr)
1620
1621 /* The EEPROM commands include the alway-set leading bit. */
1622 #define EE_EXTEND_CMD (4)
1623 #define EE_WRITE_CMD (5)
1624 #define EE_READ_CMD (6)
1625 #define EE_ERASE_CMD (7)
1626
1627 #define EE_EWDS_ADDR (0)
1628 #define EE_WRAL_ADDR (1)
1629 #define EE_ERAL_ADDR (2)
1630 #define EE_EWEN_ADDR (3)
1631
1632 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1633
1634 static void eeprom_cmd_start(void __iomem *ee_addr)
1635 {
1636 writeb (EE_ENB & ~EE_CS, ee_addr);
1637 writeb (EE_ENB, ee_addr);
1638 eeprom_delay ();
1639 }
1640
1641 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1642 {
1643 int i;
1644
1645 /* Shift the command bits out. */
1646 for (i = cmd_len - 1; i >= 0; i--) {
1647 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1648 writeb (EE_ENB | dataval, ee_addr);
1649 eeprom_delay ();
1650 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1651 eeprom_delay ();
1652 }
1653 writeb (EE_ENB, ee_addr);
1654 eeprom_delay ();
1655 }
1656
1657 static void eeprom_cmd_end(void __iomem *ee_addr)
1658 {
1659 writeb(0, ee_addr);
1660 eeprom_delay ();
1661 }
1662
1663 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1664 int addr_len)
1665 {
1666 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1667
1668 eeprom_cmd_start(ee_addr);
1669 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1670 eeprom_cmd_end(ee_addr);
1671 }
1672
1673 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1674 {
1675 int i;
1676 u16 retval = 0;
1677 void __iomem *ee_addr = ioaddr + Cfg9346;
1678 int read_cmd = location | (EE_READ_CMD << addr_len);
1679
1680 eeprom_cmd_start(ee_addr);
1681 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1682
1683 for (i = 16; i > 0; i--) {
1684 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1685 eeprom_delay ();
1686 retval =
1687 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1688 0);
1689 writeb (EE_ENB, ee_addr);
1690 eeprom_delay ();
1691 }
1692
1693 eeprom_cmd_end(ee_addr);
1694
1695 return retval;
1696 }
1697
1698 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1699 int addr_len)
1700 {
1701 int i;
1702 void __iomem *ee_addr = ioaddr + Cfg9346;
1703 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1704
1705 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1706
1707 eeprom_cmd_start(ee_addr);
1708 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1709 eeprom_cmd(ee_addr, val, 16);
1710 eeprom_cmd_end(ee_addr);
1711
1712 eeprom_cmd_start(ee_addr);
1713 for (i = 0; i < 20000; i++)
1714 if (readb(ee_addr) & EE_DATA_READ)
1715 break;
1716 eeprom_cmd_end(ee_addr);
1717
1718 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1719 }
1720
1721 static int cp_get_eeprom_len(struct net_device *dev)
1722 {
1723 struct cp_private *cp = netdev_priv(dev);
1724 int size;
1725
1726 spin_lock_irq(&cp->lock);
1727 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1728 spin_unlock_irq(&cp->lock);
1729
1730 return size;
1731 }
1732
1733 static int cp_get_eeprom(struct net_device *dev,
1734 struct ethtool_eeprom *eeprom, u8 *data)
1735 {
1736 struct cp_private *cp = netdev_priv(dev);
1737 unsigned int addr_len;
1738 u16 val;
1739 u32 offset = eeprom->offset >> 1;
1740 u32 len = eeprom->len;
1741 u32 i = 0;
1742
1743 eeprom->magic = CP_EEPROM_MAGIC;
1744
1745 spin_lock_irq(&cp->lock);
1746
1747 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1748
1749 if (eeprom->offset & 1) {
1750 val = read_eeprom(cp->regs, offset, addr_len);
1751 data[i++] = (u8)(val >> 8);
1752 offset++;
1753 }
1754
1755 while (i < len - 1) {
1756 val = read_eeprom(cp->regs, offset, addr_len);
1757 data[i++] = (u8)val;
1758 data[i++] = (u8)(val >> 8);
1759 offset++;
1760 }
1761
1762 if (i < len) {
1763 val = read_eeprom(cp->regs, offset, addr_len);
1764 data[i] = (u8)val;
1765 }
1766
1767 spin_unlock_irq(&cp->lock);
1768 return 0;
1769 }
1770
1771 static int cp_set_eeprom(struct net_device *dev,
1772 struct ethtool_eeprom *eeprom, u8 *data)
1773 {
1774 struct cp_private *cp = netdev_priv(dev);
1775 unsigned int addr_len;
1776 u16 val;
1777 u32 offset = eeprom->offset >> 1;
1778 u32 len = eeprom->len;
1779 u32 i = 0;
1780
1781 if (eeprom->magic != CP_EEPROM_MAGIC)
1782 return -EINVAL;
1783
1784 spin_lock_irq(&cp->lock);
1785
1786 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1787
1788 if (eeprom->offset & 1) {
1789 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1790 val |= (u16)data[i++] << 8;
1791 write_eeprom(cp->regs, offset, val, addr_len);
1792 offset++;
1793 }
1794
1795 while (i < len - 1) {
1796 val = (u16)data[i++];
1797 val |= (u16)data[i++] << 8;
1798 write_eeprom(cp->regs, offset, val, addr_len);
1799 offset++;
1800 }
1801
1802 if (i < len) {
1803 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1804 val |= (u16)data[i];
1805 write_eeprom(cp->regs, offset, val, addr_len);
1806 }
1807
1808 spin_unlock_irq(&cp->lock);
1809 return 0;
1810 }
1811
1812 /* Put the board into D3cold state and wait for WakeUp signal */
1813 static void cp_set_d3_state (struct cp_private *cp)
1814 {
1815 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1816 pci_set_power_state (cp->pdev, PCI_D3hot);
1817 }
1818
1819 static const struct net_device_ops cp_netdev_ops = {
1820 .ndo_open = cp_open,
1821 .ndo_stop = cp_close,
1822 .ndo_validate_addr = eth_validate_addr,
1823 .ndo_set_mac_address = cp_set_mac_address,
1824 .ndo_set_rx_mode = cp_set_rx_mode,
1825 .ndo_get_stats = cp_get_stats,
1826 .ndo_do_ioctl = cp_ioctl,
1827 .ndo_start_xmit = cp_start_xmit,
1828 .ndo_tx_timeout = cp_tx_timeout,
1829 .ndo_set_features = cp_set_features,
1830 .ndo_change_mtu = cp_change_mtu,
1831
1832 #ifdef CONFIG_NET_POLL_CONTROLLER
1833 .ndo_poll_controller = cp_poll_controller,
1834 #endif
1835 };
1836
1837 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1838 {
1839 struct net_device *dev;
1840 struct cp_private *cp;
1841 int rc;
1842 void __iomem *regs;
1843 resource_size_t pciaddr;
1844 unsigned int addr_len, i, pci_using_dac;
1845
1846 #ifndef MODULE
1847 static int version_printed;
1848 if (version_printed++ == 0)
1849 pr_info("%s", version);
1850 #endif
1851
1852 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1853 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1854 dev_info(&pdev->dev,
1855 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1856 pdev->vendor, pdev->device, pdev->revision);
1857 return -ENODEV;
1858 }
1859
1860 dev = alloc_etherdev(sizeof(struct cp_private));
1861 if (!dev)
1862 return -ENOMEM;
1863 SET_NETDEV_DEV(dev, &pdev->dev);
1864
1865 cp = netdev_priv(dev);
1866 cp->pdev = pdev;
1867 cp->dev = dev;
1868 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1869 spin_lock_init (&cp->lock);
1870 cp->mii_if.dev = dev;
1871 cp->mii_if.mdio_read = mdio_read;
1872 cp->mii_if.mdio_write = mdio_write;
1873 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1874 cp->mii_if.phy_id_mask = 0x1f;
1875 cp->mii_if.reg_num_mask = 0x1f;
1876 cp_set_rxbufsize(cp);
1877
1878 rc = pci_enable_device(pdev);
1879 if (rc)
1880 goto err_out_free;
1881
1882 rc = pci_set_mwi(pdev);
1883 if (rc)
1884 goto err_out_disable;
1885
1886 rc = pci_request_regions(pdev, DRV_NAME);
1887 if (rc)
1888 goto err_out_mwi;
1889
1890 pciaddr = pci_resource_start(pdev, 1);
1891 if (!pciaddr) {
1892 rc = -EIO;
1893 dev_err(&pdev->dev, "no MMIO resource\n");
1894 goto err_out_res;
1895 }
1896 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1897 rc = -EIO;
1898 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1899 (unsigned long long)pci_resource_len(pdev, 1));
1900 goto err_out_res;
1901 }
1902
1903 /* Configure DMA attributes. */
1904 if ((sizeof(dma_addr_t) > 4) &&
1905 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1906 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1907 pci_using_dac = 1;
1908 } else {
1909 pci_using_dac = 0;
1910
1911 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1912 if (rc) {
1913 dev_err(&pdev->dev,
1914 "No usable DMA configuration, aborting\n");
1915 goto err_out_res;
1916 }
1917 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1918 if (rc) {
1919 dev_err(&pdev->dev,
1920 "No usable consistent DMA configuration, aborting\n");
1921 goto err_out_res;
1922 }
1923 }
1924
1925 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1926 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1927
1928 dev->features |= NETIF_F_RXCSUM;
1929 dev->hw_features |= NETIF_F_RXCSUM;
1930
1931 regs = ioremap(pciaddr, CP_REGS_SIZE);
1932 if (!regs) {
1933 rc = -EIO;
1934 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1935 (unsigned long long)pci_resource_len(pdev, 1),
1936 (unsigned long long)pciaddr);
1937 goto err_out_res;
1938 }
1939 cp->regs = regs;
1940
1941 cp_stop_hw(cp);
1942
1943 /* read MAC address from EEPROM */
1944 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1945 for (i = 0; i < 3; i++)
1946 ((__le16 *) (dev->dev_addr))[i] =
1947 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1948 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1949
1950 dev->netdev_ops = &cp_netdev_ops;
1951 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1952 dev->ethtool_ops = &cp_ethtool_ops;
1953 dev->watchdog_timeo = TX_TIMEOUT;
1954
1955 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1956
1957 if (pci_using_dac)
1958 dev->features |= NETIF_F_HIGHDMA;
1959
1960 /* disabled by default until verified */
1961 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1962 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1963 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1964 NETIF_F_HIGHDMA;
1965
1966 rc = register_netdev(dev);
1967 if (rc)
1968 goto err_out_iomap;
1969
1970 netdev_info(dev, "RTL-8139C+ at 0x%p, %pM, IRQ %d\n",
1971 regs, dev->dev_addr, pdev->irq);
1972
1973 pci_set_drvdata(pdev, dev);
1974
1975 /* enable busmastering and memory-write-invalidate */
1976 pci_set_master(pdev);
1977
1978 if (cp->wol_enabled)
1979 cp_set_d3_state (cp);
1980
1981 return 0;
1982
1983 err_out_iomap:
1984 iounmap(regs);
1985 err_out_res:
1986 pci_release_regions(pdev);
1987 err_out_mwi:
1988 pci_clear_mwi(pdev);
1989 err_out_disable:
1990 pci_disable_device(pdev);
1991 err_out_free:
1992 free_netdev(dev);
1993 return rc;
1994 }
1995
1996 static void cp_remove_one (struct pci_dev *pdev)
1997 {
1998 struct net_device *dev = pci_get_drvdata(pdev);
1999 struct cp_private *cp = netdev_priv(dev);
2000
2001 unregister_netdev(dev);
2002 iounmap(cp->regs);
2003 if (cp->wol_enabled)
2004 pci_set_power_state (pdev, PCI_D0);
2005 pci_release_regions(pdev);
2006 pci_clear_mwi(pdev);
2007 pci_disable_device(pdev);
2008 pci_set_drvdata(pdev, NULL);
2009 free_netdev(dev);
2010 }
2011
2012 #ifdef CONFIG_PM
2013 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2014 {
2015 struct net_device *dev = pci_get_drvdata(pdev);
2016 struct cp_private *cp = netdev_priv(dev);
2017 unsigned long flags;
2018
2019 if (!netif_running(dev))
2020 return 0;
2021
2022 netif_device_detach (dev);
2023 netif_stop_queue (dev);
2024
2025 spin_lock_irqsave (&cp->lock, flags);
2026
2027 /* Disable Rx and Tx */
2028 cpw16 (IntrMask, 0);
2029 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2030
2031 spin_unlock_irqrestore (&cp->lock, flags);
2032
2033 pci_save_state(pdev);
2034 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2035 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2036
2037 return 0;
2038 }
2039
2040 static int cp_resume (struct pci_dev *pdev)
2041 {
2042 struct net_device *dev = pci_get_drvdata (pdev);
2043 struct cp_private *cp = netdev_priv(dev);
2044 unsigned long flags;
2045
2046 if (!netif_running(dev))
2047 return 0;
2048
2049 netif_device_attach (dev);
2050
2051 pci_set_power_state(pdev, PCI_D0);
2052 pci_restore_state(pdev);
2053 pci_enable_wake(pdev, PCI_D0, 0);
2054
2055 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2056 cp_init_rings_index (cp);
2057 cp_init_hw (cp);
2058 cp_enable_irq(cp);
2059 netif_start_queue (dev);
2060
2061 spin_lock_irqsave (&cp->lock, flags);
2062
2063 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2064
2065 spin_unlock_irqrestore (&cp->lock, flags);
2066
2067 return 0;
2068 }
2069 #endif /* CONFIG_PM */
2070
2071 static struct pci_driver cp_driver = {
2072 .name = DRV_NAME,
2073 .id_table = cp_pci_tbl,
2074 .probe = cp_init_one,
2075 .remove = cp_remove_one,
2076 #ifdef CONFIG_PM
2077 .resume = cp_resume,
2078 .suspend = cp_suspend,
2079 #endif
2080 };
2081
2082 static int __init cp_init (void)
2083 {
2084 #ifdef MODULE
2085 pr_info("%s", version);
2086 #endif
2087 return pci_register_driver(&cp_driver);
2088 }
2089
2090 static void __exit cp_exit (void)
2091 {
2092 pci_unregister_driver (&cp_driver);
2093 }
2094
2095 module_init(cp_init);
2096 module_exit(cp_exit);
Linux kernel - Deliverables
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