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Merge branch 'for-3.11-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj...
[deliverable/linux.git] / drivers / net / ethernet / realtek / 8139cp.c
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
51 #define DRV_NAME "8139cp"
52 #define DRV_VERSION "1.3"
53 #define DRV_RELDATE "Mar 22, 2004"
54
55
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/interrupt.h>
64 #include <linux/pci.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/delay.h>
67 #include <linux/ethtool.h>
68 #include <linux/gfp.h>
69 #include <linux/mii.h>
70 #include <linux/if_vlan.h>
71 #include <linux/crc32.h>
72 #include <linux/in.h>
73 #include <linux/ip.h>
74 #include <linux/tcp.h>
75 #include <linux/udp.h>
76 #include <linux/cache.h>
77 #include <asm/io.h>
78 #include <asm/irq.h>
79 #include <asm/uaccess.h>
80
81 /* These identify the driver base version and may not be removed. */
82 static char version[] =
83 DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
84
85 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
86 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
87 MODULE_VERSION(DRV_VERSION);
88 MODULE_LICENSE("GPL");
89
90 static int debug = -1;
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
93
94 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
95 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
96 static int multicast_filter_limit = 32;
97 module_param(multicast_filter_limit, int, 0);
98 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
99
100 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
101 NETIF_MSG_PROBE | \
102 NETIF_MSG_LINK)
103 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
104 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
105 #define CP_REGS_SIZE (0xff + 1)
106 #define CP_REGS_VER 1 /* version 1 */
107 #define CP_RX_RING_SIZE 64
108 #define CP_TX_RING_SIZE 64
109 #define CP_RING_BYTES \
110 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
111 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
112 CP_STATS_SIZE)
113 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
114 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
115 #define TX_BUFFS_AVAIL(CP) \
116 (((CP)->tx_tail <= (CP)->tx_head) ? \
117 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
118 (CP)->tx_tail - (CP)->tx_head - 1)
119
120 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
121 #define CP_INTERNAL_PHY 32
122
123 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
124 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
125 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
126 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
128
129 /* Time in jiffies before concluding the transmitter is hung. */
130 #define TX_TIMEOUT (6*HZ)
131
132 /* hardware minimum and maximum for a single frame's data payload */
133 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
134 #define CP_MAX_MTU 4096
135
136 enum {
137 /* NIC register offsets */
138 MAC0 = 0x00, /* Ethernet hardware address. */
139 MAR0 = 0x08, /* Multicast filter. */
140 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
141 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
142 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
143 Cmd = 0x37, /* Command register */
144 IntrMask = 0x3C, /* Interrupt mask */
145 IntrStatus = 0x3E, /* Interrupt status */
146 TxConfig = 0x40, /* Tx configuration */
147 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
148 RxConfig = 0x44, /* Rx configuration */
149 RxMissed = 0x4C, /* 24 bits valid, write clears */
150 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
151 Config1 = 0x52, /* Config1 */
152 Config3 = 0x59, /* Config3 */
153 Config4 = 0x5A, /* Config4 */
154 MultiIntr = 0x5C, /* Multiple interrupt select */
155 BasicModeCtrl = 0x62, /* MII BMCR */
156 BasicModeStatus = 0x64, /* MII BMSR */
157 NWayAdvert = 0x66, /* MII ADVERTISE */
158 NWayLPAR = 0x68, /* MII LPA */
159 NWayExpansion = 0x6A, /* MII Expansion */
160 Config5 = 0xD8, /* Config5 */
161 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
162 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
163 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
164 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
165 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
166 TxThresh = 0xEC, /* Early Tx threshold */
167 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
168 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
169
170 /* Tx and Rx status descriptors */
171 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
172 RingEnd = (1 << 30), /* End of descriptor ring */
173 FirstFrag = (1 << 29), /* First segment of a packet */
174 LastFrag = (1 << 28), /* Final segment of a packet */
175 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
176 MSSShift = 16, /* MSS value position */
177 MSSMask = 0xfff, /* MSS value: 11 bits */
178 TxError = (1 << 23), /* Tx error summary */
179 RxError = (1 << 20), /* Rx error summary */
180 IPCS = (1 << 18), /* Calculate IP checksum */
181 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
182 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
183 TxVlanTag = (1 << 17), /* Add VLAN tag */
184 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
185 IPFail = (1 << 15), /* IP checksum failed */
186 UDPFail = (1 << 14), /* UDP/IP checksum failed */
187 TCPFail = (1 << 13), /* TCP/IP checksum failed */
188 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
189 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
190 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
191 RxProtoTCP = 1,
192 RxProtoUDP = 2,
193 RxProtoIP = 3,
194 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
195 TxOWC = (1 << 22), /* Tx Out-of-window collision */
196 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
197 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
198 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
199 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
200 RxErrFrame = (1 << 27), /* Rx frame alignment error */
201 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
202 RxErrCRC = (1 << 18), /* Rx CRC error */
203 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
204 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
205 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
206
207 /* StatsAddr register */
208 DumpStats = (1 << 3), /* Begin stats dump */
209
210 /* RxConfig register */
211 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
212 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
213 AcceptErr = 0x20, /* Accept packets with CRC errors */
214 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
215 AcceptBroadcast = 0x08, /* Accept broadcast packets */
216 AcceptMulticast = 0x04, /* Accept multicast packets */
217 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
218 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
219
220 /* IntrMask / IntrStatus registers */
221 PciErr = (1 << 15), /* System error on the PCI bus */
222 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
223 LenChg = (1 << 13), /* Cable length change */
224 SWInt = (1 << 8), /* Software-requested interrupt */
225 TxEmpty = (1 << 7), /* No Tx descriptors available */
226 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
227 LinkChg = (1 << 5), /* Packet underrun, or link change */
228 RxEmpty = (1 << 4), /* No Rx descriptors available */
229 TxErr = (1 << 3), /* Tx error */
230 TxOK = (1 << 2), /* Tx packet sent */
231 RxErr = (1 << 1), /* Rx error */
232 RxOK = (1 << 0), /* Rx packet received */
233 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
234 but hardware likes to raise it */
235
236 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
237 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
238 RxErr | RxOK | IntrResvd,
239
240 /* C mode command register */
241 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
242 RxOn = (1 << 3), /* Rx mode enable */
243 TxOn = (1 << 2), /* Tx mode enable */
244
245 /* C+ mode command register */
246 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
247 RxChkSum = (1 << 5), /* Rx checksum offload enable */
248 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
249 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
250 CpRxOn = (1 << 1), /* Rx mode enable */
251 CpTxOn = (1 << 0), /* Tx mode enable */
252
253 /* Cfg9436 EEPROM control register */
254 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
255 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
256
257 /* TxConfig register */
258 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
259 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
260
261 /* Early Tx Threshold register */
262 TxThreshMask = 0x3f, /* Mask bits 5-0 */
263 TxThreshMax = 2048, /* Max early Tx threshold */
264
265 /* Config1 register */
266 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
267 LWACT = (1 << 4), /* LWAKE active mode */
268 PMEnable = (1 << 0), /* Enable various PM features of chip */
269
270 /* Config3 register */
271 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
272 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
273 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
274
275 /* Config4 register */
276 LWPTN = (1 << 1), /* LWAKE Pattern */
277 LWPME = (1 << 4), /* LANWAKE vs PMEB */
278
279 /* Config5 register */
280 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
281 MWF = (1 << 5), /* Accept Multicast wakeup frame */
282 UWF = (1 << 4), /* Accept Unicast wakeup frame */
283 LANWake = (1 << 1), /* Enable LANWake signal */
284 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
285
286 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
287 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
288 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
289 };
290
291 static const unsigned int cp_rx_config =
292 (RX_FIFO_THRESH << RxCfgFIFOShift) |
293 (RX_DMA_BURST << RxCfgDMAShift);
294
295 struct cp_desc {
296 __le32 opts1;
297 __le32 opts2;
298 __le64 addr;
299 };
300
301 struct cp_dma_stats {
302 __le64 tx_ok;
303 __le64 rx_ok;
304 __le64 tx_err;
305 __le32 rx_err;
306 __le16 rx_fifo;
307 __le16 frame_align;
308 __le32 tx_ok_1col;
309 __le32 tx_ok_mcol;
310 __le64 rx_ok_phys;
311 __le64 rx_ok_bcast;
312 __le32 rx_ok_mcast;
313 __le16 tx_abort;
314 __le16 tx_underrun;
315 } __packed;
316
317 struct cp_extra_stats {
318 unsigned long rx_frags;
319 };
320
321 struct cp_private {
322 void __iomem *regs;
323 struct net_device *dev;
324 spinlock_t lock;
325 u32 msg_enable;
326
327 struct napi_struct napi;
328
329 struct pci_dev *pdev;
330 u32 rx_config;
331 u16 cpcmd;
332
333 struct cp_extra_stats cp_stats;
334
335 unsigned rx_head ____cacheline_aligned;
336 unsigned rx_tail;
337 struct cp_desc *rx_ring;
338 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
339
340 unsigned tx_head ____cacheline_aligned;
341 unsigned tx_tail;
342 struct cp_desc *tx_ring;
343 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
344
345 unsigned rx_buf_sz;
346 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
347
348 dma_addr_t ring_dma;
349
350 struct mii_if_info mii_if;
351 };
352
353 #define cpr8(reg) readb(cp->regs + (reg))
354 #define cpr16(reg) readw(cp->regs + (reg))
355 #define cpr32(reg) readl(cp->regs + (reg))
356 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
357 #define cpw16(reg,val) writew((val), cp->regs + (reg))
358 #define cpw32(reg,val) writel((val), cp->regs + (reg))
359 #define cpw8_f(reg,val) do { \
360 writeb((val), cp->regs + (reg)); \
361 readb(cp->regs + (reg)); \
362 } while (0)
363 #define cpw16_f(reg,val) do { \
364 writew((val), cp->regs + (reg)); \
365 readw(cp->regs + (reg)); \
366 } while (0)
367 #define cpw32_f(reg,val) do { \
368 writel((val), cp->regs + (reg)); \
369 readl(cp->regs + (reg)); \
370 } while (0)
371
372
373 static void __cp_set_rx_mode (struct net_device *dev);
374 static void cp_tx (struct cp_private *cp);
375 static void cp_clean_rings (struct cp_private *cp);
376 #ifdef CONFIG_NET_POLL_CONTROLLER
377 static void cp_poll_controller(struct net_device *dev);
378 #endif
379 static int cp_get_eeprom_len(struct net_device *dev);
380 static int cp_get_eeprom(struct net_device *dev,
381 struct ethtool_eeprom *eeprom, u8 *data);
382 static int cp_set_eeprom(struct net_device *dev,
383 struct ethtool_eeprom *eeprom, u8 *data);
384
385 static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
386 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
387 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
388 { },
389 };
390 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
391
392 static struct {
393 const char str[ETH_GSTRING_LEN];
394 } ethtool_stats_keys[] = {
395 { "tx_ok" },
396 { "rx_ok" },
397 { "tx_err" },
398 { "rx_err" },
399 { "rx_fifo" },
400 { "frame_align" },
401 { "tx_ok_1col" },
402 { "tx_ok_mcol" },
403 { "rx_ok_phys" },
404 { "rx_ok_bcast" },
405 { "rx_ok_mcast" },
406 { "tx_abort" },
407 { "tx_underrun" },
408 { "rx_frags" },
409 };
410
411
412 static inline void cp_set_rxbufsize (struct cp_private *cp)
413 {
414 unsigned int mtu = cp->dev->mtu;
415
416 if (mtu > ETH_DATA_LEN)
417 /* MTU + ethernet header + FCS + optional VLAN tag */
418 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
419 else
420 cp->rx_buf_sz = PKT_BUF_SZ;
421 }
422
423 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
424 struct cp_desc *desc)
425 {
426 u32 opts2 = le32_to_cpu(desc->opts2);
427
428 skb->protocol = eth_type_trans (skb, cp->dev);
429
430 cp->dev->stats.rx_packets++;
431 cp->dev->stats.rx_bytes += skb->len;
432
433 if (opts2 & RxVlanTagged)
434 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
435
436 napi_gro_receive(&cp->napi, skb);
437 }
438
439 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
440 u32 status, u32 len)
441 {
442 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
443 rx_tail, status, len);
444 cp->dev->stats.rx_errors++;
445 if (status & RxErrFrame)
446 cp->dev->stats.rx_frame_errors++;
447 if (status & RxErrCRC)
448 cp->dev->stats.rx_crc_errors++;
449 if ((status & RxErrRunt) || (status & RxErrLong))
450 cp->dev->stats.rx_length_errors++;
451 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
452 cp->dev->stats.rx_length_errors++;
453 if (status & RxErrFIFO)
454 cp->dev->stats.rx_fifo_errors++;
455 }
456
457 static inline unsigned int cp_rx_csum_ok (u32 status)
458 {
459 unsigned int protocol = (status >> 16) & 0x3;
460
461 if (((protocol == RxProtoTCP) && !(status & TCPFail)) ||
462 ((protocol == RxProtoUDP) && !(status & UDPFail)))
463 return 1;
464 else
465 return 0;
466 }
467
468 static int cp_rx_poll(struct napi_struct *napi, int budget)
469 {
470 struct cp_private *cp = container_of(napi, struct cp_private, napi);
471 struct net_device *dev = cp->dev;
472 unsigned int rx_tail = cp->rx_tail;
473 int rx;
474
475 rx_status_loop:
476 rx = 0;
477 cpw16(IntrStatus, cp_rx_intr_mask);
478
479 while (1) {
480 u32 status, len;
481 dma_addr_t mapping, new_mapping;
482 struct sk_buff *skb, *new_skb;
483 struct cp_desc *desc;
484 const unsigned buflen = cp->rx_buf_sz;
485
486 skb = cp->rx_skb[rx_tail];
487 BUG_ON(!skb);
488
489 desc = &cp->rx_ring[rx_tail];
490 status = le32_to_cpu(desc->opts1);
491 if (status & DescOwn)
492 break;
493
494 len = (status & 0x1fff) - 4;
495 mapping = le64_to_cpu(desc->addr);
496
497 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
498 /* we don't support incoming fragmented frames.
499 * instead, we attempt to ensure that the
500 * pre-allocated RX skbs are properly sized such
501 * that RX fragments are never encountered
502 */
503 cp_rx_err_acct(cp, rx_tail, status, len);
504 dev->stats.rx_dropped++;
505 cp->cp_stats.rx_frags++;
506 goto rx_next;
507 }
508
509 if (status & (RxError | RxErrFIFO)) {
510 cp_rx_err_acct(cp, rx_tail, status, len);
511 goto rx_next;
512 }
513
514 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
515 rx_tail, status, len);
516
517 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
518 if (!new_skb) {
519 dev->stats.rx_dropped++;
520 goto rx_next;
521 }
522
523 new_mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
524 PCI_DMA_FROMDEVICE);
525 if (dma_mapping_error(&cp->pdev->dev, new_mapping)) {
526 dev->stats.rx_dropped++;
527 kfree_skb(new_skb);
528 goto rx_next;
529 }
530
531 dma_unmap_single(&cp->pdev->dev, mapping,
532 buflen, PCI_DMA_FROMDEVICE);
533
534 /* Handle checksum offloading for incoming packets. */
535 if (cp_rx_csum_ok(status))
536 skb->ip_summed = CHECKSUM_UNNECESSARY;
537 else
538 skb_checksum_none_assert(skb);
539
540 skb_put(skb, len);
541
542 cp->rx_skb[rx_tail] = new_skb;
543
544 cp_rx_skb(cp, skb, desc);
545 rx++;
546 mapping = new_mapping;
547
548 rx_next:
549 cp->rx_ring[rx_tail].opts2 = 0;
550 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
551 if (rx_tail == (CP_RX_RING_SIZE - 1))
552 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
553 cp->rx_buf_sz);
554 else
555 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
556 rx_tail = NEXT_RX(rx_tail);
557
558 if (rx >= budget)
559 break;
560 }
561
562 cp->rx_tail = rx_tail;
563
564 /* if we did not reach work limit, then we're done with
565 * this round of polling
566 */
567 if (rx < budget) {
568 unsigned long flags;
569
570 if (cpr16(IntrStatus) & cp_rx_intr_mask)
571 goto rx_status_loop;
572
573 napi_gro_flush(napi, false);
574 spin_lock_irqsave(&cp->lock, flags);
575 __napi_complete(napi);
576 cpw16_f(IntrMask, cp_intr_mask);
577 spin_unlock_irqrestore(&cp->lock, flags);
578 }
579
580 return rx;
581 }
582
583 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
584 {
585 struct net_device *dev = dev_instance;
586 struct cp_private *cp;
587 int handled = 0;
588 u16 status;
589
590 if (unlikely(dev == NULL))
591 return IRQ_NONE;
592 cp = netdev_priv(dev);
593
594 spin_lock(&cp->lock);
595
596 status = cpr16(IntrStatus);
597 if (!status || (status == 0xFFFF))
598 goto out_unlock;
599
600 handled = 1;
601
602 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
603 status, cpr8(Cmd), cpr16(CpCmd));
604
605 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
606
607 /* close possible race's with dev_close */
608 if (unlikely(!netif_running(dev))) {
609 cpw16(IntrMask, 0);
610 goto out_unlock;
611 }
612
613 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
614 if (napi_schedule_prep(&cp->napi)) {
615 cpw16_f(IntrMask, cp_norx_intr_mask);
616 __napi_schedule(&cp->napi);
617 }
618
619 if (status & (TxOK | TxErr | TxEmpty | SWInt))
620 cp_tx(cp);
621 if (status & LinkChg)
622 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
623
624
625 if (status & PciErr) {
626 u16 pci_status;
627
628 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
629 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
630 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
631 status, pci_status);
632
633 /* TODO: reset hardware */
634 }
635
636 out_unlock:
637 spin_unlock(&cp->lock);
638
639 return IRQ_RETVAL(handled);
640 }
641
642 #ifdef CONFIG_NET_POLL_CONTROLLER
643 /*
644 * Polling receive - used by netconsole and other diagnostic tools
645 * to allow network i/o with interrupts disabled.
646 */
647 static void cp_poll_controller(struct net_device *dev)
648 {
649 struct cp_private *cp = netdev_priv(dev);
650 const int irq = cp->pdev->irq;
651
652 disable_irq(irq);
653 cp_interrupt(irq, dev);
654 enable_irq(irq);
655 }
656 #endif
657
658 static void cp_tx (struct cp_private *cp)
659 {
660 unsigned tx_head = cp->tx_head;
661 unsigned tx_tail = cp->tx_tail;
662 unsigned bytes_compl = 0, pkts_compl = 0;
663
664 while (tx_tail != tx_head) {
665 struct cp_desc *txd = cp->tx_ring + tx_tail;
666 struct sk_buff *skb;
667 u32 status;
668
669 rmb();
670 status = le32_to_cpu(txd->opts1);
671 if (status & DescOwn)
672 break;
673
674 skb = cp->tx_skb[tx_tail];
675 BUG_ON(!skb);
676
677 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
678 le32_to_cpu(txd->opts1) & 0xffff,
679 PCI_DMA_TODEVICE);
680
681 bytes_compl += skb->len;
682 pkts_compl++;
683
684 if (status & LastFrag) {
685 if (status & (TxError | TxFIFOUnder)) {
686 netif_dbg(cp, tx_err, cp->dev,
687 "tx err, status 0x%x\n", status);
688 cp->dev->stats.tx_errors++;
689 if (status & TxOWC)
690 cp->dev->stats.tx_window_errors++;
691 if (status & TxMaxCol)
692 cp->dev->stats.tx_aborted_errors++;
693 if (status & TxLinkFail)
694 cp->dev->stats.tx_carrier_errors++;
695 if (status & TxFIFOUnder)
696 cp->dev->stats.tx_fifo_errors++;
697 } else {
698 cp->dev->stats.collisions +=
699 ((status >> TxColCntShift) & TxColCntMask);
700 cp->dev->stats.tx_packets++;
701 cp->dev->stats.tx_bytes += skb->len;
702 netif_dbg(cp, tx_done, cp->dev,
703 "tx done, slot %d\n", tx_tail);
704 }
705 dev_kfree_skb_irq(skb);
706 }
707
708 cp->tx_skb[tx_tail] = NULL;
709
710 tx_tail = NEXT_TX(tx_tail);
711 }
712
713 cp->tx_tail = tx_tail;
714
715 netdev_completed_queue(cp->dev, pkts_compl, bytes_compl);
716 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
717 netif_wake_queue(cp->dev);
718 }
719
720 static inline u32 cp_tx_vlan_tag(struct sk_buff *skb)
721 {
722 return vlan_tx_tag_present(skb) ?
723 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
724 }
725
726 static void unwind_tx_frag_mapping(struct cp_private *cp, struct sk_buff *skb,
727 int first, int entry_last)
728 {
729 int frag, index;
730 struct cp_desc *txd;
731 skb_frag_t *this_frag;
732 for (frag = 0; frag+first < entry_last; frag++) {
733 index = first+frag;
734 cp->tx_skb[index] = NULL;
735 txd = &cp->tx_ring[index];
736 this_frag = &skb_shinfo(skb)->frags[frag];
737 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
738 skb_frag_size(this_frag), PCI_DMA_TODEVICE);
739 }
740 }
741
742 static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
743 struct net_device *dev)
744 {
745 struct cp_private *cp = netdev_priv(dev);
746 unsigned entry;
747 u32 eor, flags;
748 unsigned long intr_flags;
749 __le32 opts2;
750 int mss = 0;
751
752 spin_lock_irqsave(&cp->lock, intr_flags);
753
754 /* This is a hard error, log it. */
755 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
756 netif_stop_queue(dev);
757 spin_unlock_irqrestore(&cp->lock, intr_flags);
758 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
759 return NETDEV_TX_BUSY;
760 }
761
762 entry = cp->tx_head;
763 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
764 mss = skb_shinfo(skb)->gso_size;
765
766 opts2 = cpu_to_le32(cp_tx_vlan_tag(skb));
767
768 if (skb_shinfo(skb)->nr_frags == 0) {
769 struct cp_desc *txd = &cp->tx_ring[entry];
770 u32 len;
771 dma_addr_t mapping;
772
773 len = skb->len;
774 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
775 if (dma_mapping_error(&cp->pdev->dev, mapping))
776 goto out_dma_error;
777
778 txd->opts2 = opts2;
779 txd->addr = cpu_to_le64(mapping);
780 wmb();
781
782 flags = eor | len | DescOwn | FirstFrag | LastFrag;
783
784 if (mss)
785 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
786 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
787 const struct iphdr *ip = ip_hdr(skb);
788 if (ip->protocol == IPPROTO_TCP)
789 flags |= IPCS | TCPCS;
790 else if (ip->protocol == IPPROTO_UDP)
791 flags |= IPCS | UDPCS;
792 else
793 WARN_ON(1); /* we need a WARN() */
794 }
795
796 txd->opts1 = cpu_to_le32(flags);
797 wmb();
798
799 cp->tx_skb[entry] = skb;
800 entry = NEXT_TX(entry);
801 } else {
802 struct cp_desc *txd;
803 u32 first_len, first_eor;
804 dma_addr_t first_mapping;
805 int frag, first_entry = entry;
806 const struct iphdr *ip = ip_hdr(skb);
807
808 /* We must give this initial chunk to the device last.
809 * Otherwise we could race with the device.
810 */
811 first_eor = eor;
812 first_len = skb_headlen(skb);
813 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
814 first_len, PCI_DMA_TODEVICE);
815 if (dma_mapping_error(&cp->pdev->dev, first_mapping))
816 goto out_dma_error;
817
818 cp->tx_skb[entry] = skb;
819 entry = NEXT_TX(entry);
820
821 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
822 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
823 u32 len;
824 u32 ctrl;
825 dma_addr_t mapping;
826
827 len = skb_frag_size(this_frag);
828 mapping = dma_map_single(&cp->pdev->dev,
829 skb_frag_address(this_frag),
830 len, PCI_DMA_TODEVICE);
831 if (dma_mapping_error(&cp->pdev->dev, mapping)) {
832 unwind_tx_frag_mapping(cp, skb, first_entry, entry);
833 goto out_dma_error;
834 }
835
836 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
837
838 ctrl = eor | len | DescOwn;
839
840 if (mss)
841 ctrl |= LargeSend |
842 ((mss & MSSMask) << MSSShift);
843 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
844 if (ip->protocol == IPPROTO_TCP)
845 ctrl |= IPCS | TCPCS;
846 else if (ip->protocol == IPPROTO_UDP)
847 ctrl |= IPCS | UDPCS;
848 else
849 BUG();
850 }
851
852 if (frag == skb_shinfo(skb)->nr_frags - 1)
853 ctrl |= LastFrag;
854
855 txd = &cp->tx_ring[entry];
856 txd->opts2 = opts2;
857 txd->addr = cpu_to_le64(mapping);
858 wmb();
859
860 txd->opts1 = cpu_to_le32(ctrl);
861 wmb();
862
863 cp->tx_skb[entry] = skb;
864 entry = NEXT_TX(entry);
865 }
866
867 txd = &cp->tx_ring[first_entry];
868 txd->opts2 = opts2;
869 txd->addr = cpu_to_le64(first_mapping);
870 wmb();
871
872 if (skb->ip_summed == CHECKSUM_PARTIAL) {
873 if (ip->protocol == IPPROTO_TCP)
874 txd->opts1 = cpu_to_le32(first_eor | first_len |
875 FirstFrag | DescOwn |
876 IPCS | TCPCS);
877 else if (ip->protocol == IPPROTO_UDP)
878 txd->opts1 = cpu_to_le32(first_eor | first_len |
879 FirstFrag | DescOwn |
880 IPCS | UDPCS);
881 else
882 BUG();
883 } else
884 txd->opts1 = cpu_to_le32(first_eor | first_len |
885 FirstFrag | DescOwn);
886 wmb();
887 }
888 cp->tx_head = entry;
889
890 netdev_sent_queue(dev, skb->len);
891 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
892 entry, skb->len);
893 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
894 netif_stop_queue(dev);
895
896 out_unlock:
897 spin_unlock_irqrestore(&cp->lock, intr_flags);
898
899 cpw8(TxPoll, NormalTxPoll);
900
901 return NETDEV_TX_OK;
902 out_dma_error:
903 kfree_skb(skb);
904 cp->dev->stats.tx_dropped++;
905 goto out_unlock;
906 }
907
908 /* Set or clear the multicast filter for this adaptor.
909 This routine is not state sensitive and need not be SMP locked. */
910
911 static void __cp_set_rx_mode (struct net_device *dev)
912 {
913 struct cp_private *cp = netdev_priv(dev);
914 u32 mc_filter[2]; /* Multicast hash filter */
915 int rx_mode;
916
917 /* Note: do not reorder, GCC is clever about common statements. */
918 if (dev->flags & IFF_PROMISC) {
919 /* Unconditionally log net taps. */
920 rx_mode =
921 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
922 AcceptAllPhys;
923 mc_filter[1] = mc_filter[0] = 0xffffffff;
924 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
925 (dev->flags & IFF_ALLMULTI)) {
926 /* Too many to filter perfectly -- accept all multicasts. */
927 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
928 mc_filter[1] = mc_filter[0] = 0xffffffff;
929 } else {
930 struct netdev_hw_addr *ha;
931 rx_mode = AcceptBroadcast | AcceptMyPhys;
932 mc_filter[1] = mc_filter[0] = 0;
933 netdev_for_each_mc_addr(ha, dev) {
934 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
935
936 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
937 rx_mode |= AcceptMulticast;
938 }
939 }
940
941 /* We can safely update without stopping the chip. */
942 cp->rx_config = cp_rx_config | rx_mode;
943 cpw32_f(RxConfig, cp->rx_config);
944
945 cpw32_f (MAR0 + 0, mc_filter[0]);
946 cpw32_f (MAR0 + 4, mc_filter[1]);
947 }
948
949 static void cp_set_rx_mode (struct net_device *dev)
950 {
951 unsigned long flags;
952 struct cp_private *cp = netdev_priv(dev);
953
954 spin_lock_irqsave (&cp->lock, flags);
955 __cp_set_rx_mode(dev);
956 spin_unlock_irqrestore (&cp->lock, flags);
957 }
958
959 static void __cp_get_stats(struct cp_private *cp)
960 {
961 /* only lower 24 bits valid; write any value to clear */
962 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
963 cpw32 (RxMissed, 0);
964 }
965
966 static struct net_device_stats *cp_get_stats(struct net_device *dev)
967 {
968 struct cp_private *cp = netdev_priv(dev);
969 unsigned long flags;
970
971 /* The chip only need report frame silently dropped. */
972 spin_lock_irqsave(&cp->lock, flags);
973 if (netif_running(dev) && netif_device_present(dev))
974 __cp_get_stats(cp);
975 spin_unlock_irqrestore(&cp->lock, flags);
976
977 return &dev->stats;
978 }
979
980 static void cp_stop_hw (struct cp_private *cp)
981 {
982 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
983 cpw16_f(IntrMask, 0);
984 cpw8(Cmd, 0);
985 cpw16_f(CpCmd, 0);
986 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
987
988 cp->rx_tail = 0;
989 cp->tx_head = cp->tx_tail = 0;
990
991 netdev_reset_queue(cp->dev);
992 }
993
994 static void cp_reset_hw (struct cp_private *cp)
995 {
996 unsigned work = 1000;
997
998 cpw8(Cmd, CmdReset);
999
1000 while (work--) {
1001 if (!(cpr8(Cmd) & CmdReset))
1002 return;
1003
1004 schedule_timeout_uninterruptible(10);
1005 }
1006
1007 netdev_err(cp->dev, "hardware reset timeout\n");
1008 }
1009
1010 static inline void cp_start_hw (struct cp_private *cp)
1011 {
1012 dma_addr_t ring_dma;
1013
1014 cpw16(CpCmd, cp->cpcmd);
1015
1016 /*
1017 * These (at least TxRingAddr) need to be configured after the
1018 * corresponding bits in CpCmd are enabled. Datasheet v1.6 §6.33
1019 * (C+ Command Register) recommends that these and more be configured
1020 * *after* the [RT]xEnable bits in CpCmd are set. And on some hardware
1021 * it's been observed that the TxRingAddr is actually reset to garbage
1022 * when C+ mode Tx is enabled in CpCmd.
1023 */
1024 cpw32_f(HiTxRingAddr, 0);
1025 cpw32_f(HiTxRingAddr + 4, 0);
1026
1027 ring_dma = cp->ring_dma;
1028 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1029 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1030
1031 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1032 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1033 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1034
1035 /*
1036 * Strictly speaking, the datasheet says this should be enabled
1037 * *before* setting the descriptor addresses. But what, then, would
1038 * prevent it from doing DMA to random unconfigured addresses?
1039 * This variant appears to work fine.
1040 */
1041 cpw8(Cmd, RxOn | TxOn);
1042
1043 netdev_reset_queue(cp->dev);
1044 }
1045
1046 static void cp_enable_irq(struct cp_private *cp)
1047 {
1048 cpw16_f(IntrMask, cp_intr_mask);
1049 }
1050
1051 static void cp_init_hw (struct cp_private *cp)
1052 {
1053 struct net_device *dev = cp->dev;
1054
1055 cp_reset_hw(cp);
1056
1057 cpw8_f (Cfg9346, Cfg9346_Unlock);
1058
1059 /* Restore our idea of the MAC address. */
1060 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1061 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1062
1063 cp_start_hw(cp);
1064 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1065
1066 __cp_set_rx_mode(dev);
1067 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1068
1069 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1070 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1071 cpw8(Config3, PARMEnable);
1072 cp->wol_enabled = 0;
1073
1074 cpw8(Config5, cpr8(Config5) & PMEStatus);
1075
1076 cpw16(MultiIntr, 0);
1077
1078 cpw8_f(Cfg9346, Cfg9346_Lock);
1079 }
1080
1081 static int cp_refill_rx(struct cp_private *cp)
1082 {
1083 struct net_device *dev = cp->dev;
1084 unsigned i;
1085
1086 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1087 struct sk_buff *skb;
1088 dma_addr_t mapping;
1089
1090 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1091 if (!skb)
1092 goto err_out;
1093
1094 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1095 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1096 if (dma_mapping_error(&cp->pdev->dev, mapping)) {
1097 kfree_skb(skb);
1098 goto err_out;
1099 }
1100 cp->rx_skb[i] = skb;
1101
1102 cp->rx_ring[i].opts2 = 0;
1103 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1104 if (i == (CP_RX_RING_SIZE - 1))
1105 cp->rx_ring[i].opts1 =
1106 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1107 else
1108 cp->rx_ring[i].opts1 =
1109 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1110 }
1111
1112 return 0;
1113
1114 err_out:
1115 cp_clean_rings(cp);
1116 return -ENOMEM;
1117 }
1118
1119 static void cp_init_rings_index (struct cp_private *cp)
1120 {
1121 cp->rx_tail = 0;
1122 cp->tx_head = cp->tx_tail = 0;
1123 }
1124
1125 static int cp_init_rings (struct cp_private *cp)
1126 {
1127 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1128 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1129
1130 cp_init_rings_index(cp);
1131
1132 return cp_refill_rx (cp);
1133 }
1134
1135 static int cp_alloc_rings (struct cp_private *cp)
1136 {
1137 struct device *d = &cp->pdev->dev;
1138 void *mem;
1139 int rc;
1140
1141 mem = dma_alloc_coherent(d, CP_RING_BYTES, &cp->ring_dma, GFP_KERNEL);
1142 if (!mem)
1143 return -ENOMEM;
1144
1145 cp->rx_ring = mem;
1146 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1147
1148 rc = cp_init_rings(cp);
1149 if (rc < 0)
1150 dma_free_coherent(d, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1151
1152 return rc;
1153 }
1154
1155 static void cp_clean_rings (struct cp_private *cp)
1156 {
1157 struct cp_desc *desc;
1158 unsigned i;
1159
1160 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1161 if (cp->rx_skb[i]) {
1162 desc = cp->rx_ring + i;
1163 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1164 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1165 dev_kfree_skb(cp->rx_skb[i]);
1166 }
1167 }
1168
1169 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1170 if (cp->tx_skb[i]) {
1171 struct sk_buff *skb = cp->tx_skb[i];
1172
1173 desc = cp->tx_ring + i;
1174 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1175 le32_to_cpu(desc->opts1) & 0xffff,
1176 PCI_DMA_TODEVICE);
1177 if (le32_to_cpu(desc->opts1) & LastFrag)
1178 dev_kfree_skb(skb);
1179 cp->dev->stats.tx_dropped++;
1180 }
1181 }
1182 netdev_reset_queue(cp->dev);
1183
1184 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1185 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1186
1187 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1188 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1189 }
1190
1191 static void cp_free_rings (struct cp_private *cp)
1192 {
1193 cp_clean_rings(cp);
1194 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1195 cp->ring_dma);
1196 cp->rx_ring = NULL;
1197 cp->tx_ring = NULL;
1198 }
1199
1200 static int cp_open (struct net_device *dev)
1201 {
1202 struct cp_private *cp = netdev_priv(dev);
1203 const int irq = cp->pdev->irq;
1204 int rc;
1205
1206 netif_dbg(cp, ifup, dev, "enabling interface\n");
1207
1208 rc = cp_alloc_rings(cp);
1209 if (rc)
1210 return rc;
1211
1212 napi_enable(&cp->napi);
1213
1214 cp_init_hw(cp);
1215
1216 rc = request_irq(irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1217 if (rc)
1218 goto err_out_hw;
1219
1220 cp_enable_irq(cp);
1221
1222 netif_carrier_off(dev);
1223 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1224 netif_start_queue(dev);
1225
1226 return 0;
1227
1228 err_out_hw:
1229 napi_disable(&cp->napi);
1230 cp_stop_hw(cp);
1231 cp_free_rings(cp);
1232 return rc;
1233 }
1234
1235 static int cp_close (struct net_device *dev)
1236 {
1237 struct cp_private *cp = netdev_priv(dev);
1238 unsigned long flags;
1239
1240 napi_disable(&cp->napi);
1241
1242 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1243
1244 spin_lock_irqsave(&cp->lock, flags);
1245
1246 netif_stop_queue(dev);
1247 netif_carrier_off(dev);
1248
1249 cp_stop_hw(cp);
1250
1251 spin_unlock_irqrestore(&cp->lock, flags);
1252
1253 free_irq(cp->pdev->irq, dev);
1254
1255 cp_free_rings(cp);
1256 return 0;
1257 }
1258
1259 static void cp_tx_timeout(struct net_device *dev)
1260 {
1261 struct cp_private *cp = netdev_priv(dev);
1262 unsigned long flags;
1263 int rc;
1264
1265 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1266 cpr8(Cmd), cpr16(CpCmd),
1267 cpr16(IntrStatus), cpr16(IntrMask));
1268
1269 spin_lock_irqsave(&cp->lock, flags);
1270
1271 cp_stop_hw(cp);
1272 cp_clean_rings(cp);
1273 rc = cp_init_rings(cp);
1274 cp_start_hw(cp);
1275 cp_enable_irq(cp);
1276
1277 netif_wake_queue(dev);
1278
1279 spin_unlock_irqrestore(&cp->lock, flags);
1280 }
1281
1282 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1283 {
1284 struct cp_private *cp = netdev_priv(dev);
1285
1286 /* check for invalid MTU, according to hardware limits */
1287 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1288 return -EINVAL;
1289
1290 /* if network interface not up, no need for complexity */
1291 if (!netif_running(dev)) {
1292 dev->mtu = new_mtu;
1293 cp_set_rxbufsize(cp); /* set new rx buf size */
1294 return 0;
1295 }
1296
1297 /* network IS up, close it, reset MTU, and come up again. */
1298 cp_close(dev);
1299 dev->mtu = new_mtu;
1300 cp_set_rxbufsize(cp);
1301 return cp_open(dev);
1302 }
1303
1304 static const char mii_2_8139_map[8] = {
1305 BasicModeCtrl,
1306 BasicModeStatus,
1307 0,
1308 0,
1309 NWayAdvert,
1310 NWayLPAR,
1311 NWayExpansion,
1312 0
1313 };
1314
1315 static int mdio_read(struct net_device *dev, int phy_id, int location)
1316 {
1317 struct cp_private *cp = netdev_priv(dev);
1318
1319 return location < 8 && mii_2_8139_map[location] ?
1320 readw(cp->regs + mii_2_8139_map[location]) : 0;
1321 }
1322
1323
1324 static void mdio_write(struct net_device *dev, int phy_id, int location,
1325 int value)
1326 {
1327 struct cp_private *cp = netdev_priv(dev);
1328
1329 if (location == 0) {
1330 cpw8(Cfg9346, Cfg9346_Unlock);
1331 cpw16(BasicModeCtrl, value);
1332 cpw8(Cfg9346, Cfg9346_Lock);
1333 } else if (location < 8 && mii_2_8139_map[location])
1334 cpw16(mii_2_8139_map[location], value);
1335 }
1336
1337 /* Set the ethtool Wake-on-LAN settings */
1338 static int netdev_set_wol (struct cp_private *cp,
1339 const struct ethtool_wolinfo *wol)
1340 {
1341 u8 options;
1342
1343 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1344 /* If WOL is being disabled, no need for complexity */
1345 if (wol->wolopts) {
1346 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1347 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1348 }
1349
1350 cpw8 (Cfg9346, Cfg9346_Unlock);
1351 cpw8 (Config3, options);
1352 cpw8 (Cfg9346, Cfg9346_Lock);
1353
1354 options = 0; /* Paranoia setting */
1355 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1356 /* If WOL is being disabled, no need for complexity */
1357 if (wol->wolopts) {
1358 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1359 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1360 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1361 }
1362
1363 cpw8 (Config5, options);
1364
1365 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1366
1367 return 0;
1368 }
1369
1370 /* Get the ethtool Wake-on-LAN settings */
1371 static void netdev_get_wol (struct cp_private *cp,
1372 struct ethtool_wolinfo *wol)
1373 {
1374 u8 options;
1375
1376 wol->wolopts = 0; /* Start from scratch */
1377 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1378 WAKE_MCAST | WAKE_UCAST;
1379 /* We don't need to go on if WOL is disabled */
1380 if (!cp->wol_enabled) return;
1381
1382 options = cpr8 (Config3);
1383 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1384 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1385
1386 options = 0; /* Paranoia setting */
1387 options = cpr8 (Config5);
1388 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1389 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1390 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1391 }
1392
1393 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1394 {
1395 struct cp_private *cp = netdev_priv(dev);
1396
1397 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1398 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1399 strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
1400 }
1401
1402 static void cp_get_ringparam(struct net_device *dev,
1403 struct ethtool_ringparam *ring)
1404 {
1405 ring->rx_max_pending = CP_RX_RING_SIZE;
1406 ring->tx_max_pending = CP_TX_RING_SIZE;
1407 ring->rx_pending = CP_RX_RING_SIZE;
1408 ring->tx_pending = CP_TX_RING_SIZE;
1409 }
1410
1411 static int cp_get_regs_len(struct net_device *dev)
1412 {
1413 return CP_REGS_SIZE;
1414 }
1415
1416 static int cp_get_sset_count (struct net_device *dev, int sset)
1417 {
1418 switch (sset) {
1419 case ETH_SS_STATS:
1420 return CP_NUM_STATS;
1421 default:
1422 return -EOPNOTSUPP;
1423 }
1424 }
1425
1426 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1427 {
1428 struct cp_private *cp = netdev_priv(dev);
1429 int rc;
1430 unsigned long flags;
1431
1432 spin_lock_irqsave(&cp->lock, flags);
1433 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1434 spin_unlock_irqrestore(&cp->lock, flags);
1435
1436 return rc;
1437 }
1438
1439 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1440 {
1441 struct cp_private *cp = netdev_priv(dev);
1442 int rc;
1443 unsigned long flags;
1444
1445 spin_lock_irqsave(&cp->lock, flags);
1446 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1447 spin_unlock_irqrestore(&cp->lock, flags);
1448
1449 return rc;
1450 }
1451
1452 static int cp_nway_reset(struct net_device *dev)
1453 {
1454 struct cp_private *cp = netdev_priv(dev);
1455 return mii_nway_restart(&cp->mii_if);
1456 }
1457
1458 static u32 cp_get_msglevel(struct net_device *dev)
1459 {
1460 struct cp_private *cp = netdev_priv(dev);
1461 return cp->msg_enable;
1462 }
1463
1464 static void cp_set_msglevel(struct net_device *dev, u32 value)
1465 {
1466 struct cp_private *cp = netdev_priv(dev);
1467 cp->msg_enable = value;
1468 }
1469
1470 static int cp_set_features(struct net_device *dev, netdev_features_t features)
1471 {
1472 struct cp_private *cp = netdev_priv(dev);
1473 unsigned long flags;
1474
1475 if (!((dev->features ^ features) & NETIF_F_RXCSUM))
1476 return 0;
1477
1478 spin_lock_irqsave(&cp->lock, flags);
1479
1480 if (features & NETIF_F_RXCSUM)
1481 cp->cpcmd |= RxChkSum;
1482 else
1483 cp->cpcmd &= ~RxChkSum;
1484
1485 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1486 cp->cpcmd |= RxVlanOn;
1487 else
1488 cp->cpcmd &= ~RxVlanOn;
1489
1490 cpw16_f(CpCmd, cp->cpcmd);
1491 spin_unlock_irqrestore(&cp->lock, flags);
1492
1493 return 0;
1494 }
1495
1496 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1497 void *p)
1498 {
1499 struct cp_private *cp = netdev_priv(dev);
1500 unsigned long flags;
1501
1502 if (regs->len < CP_REGS_SIZE)
1503 return /* -EINVAL */;
1504
1505 regs->version = CP_REGS_VER;
1506
1507 spin_lock_irqsave(&cp->lock, flags);
1508 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1509 spin_unlock_irqrestore(&cp->lock, flags);
1510 }
1511
1512 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1513 {
1514 struct cp_private *cp = netdev_priv(dev);
1515 unsigned long flags;
1516
1517 spin_lock_irqsave (&cp->lock, flags);
1518 netdev_get_wol (cp, wol);
1519 spin_unlock_irqrestore (&cp->lock, flags);
1520 }
1521
1522 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1523 {
1524 struct cp_private *cp = netdev_priv(dev);
1525 unsigned long flags;
1526 int rc;
1527
1528 spin_lock_irqsave (&cp->lock, flags);
1529 rc = netdev_set_wol (cp, wol);
1530 spin_unlock_irqrestore (&cp->lock, flags);
1531
1532 return rc;
1533 }
1534
1535 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1536 {
1537 switch (stringset) {
1538 case ETH_SS_STATS:
1539 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1540 break;
1541 default:
1542 BUG();
1543 break;
1544 }
1545 }
1546
1547 static void cp_get_ethtool_stats (struct net_device *dev,
1548 struct ethtool_stats *estats, u64 *tmp_stats)
1549 {
1550 struct cp_private *cp = netdev_priv(dev);
1551 struct cp_dma_stats *nic_stats;
1552 dma_addr_t dma;
1553 int i;
1554
1555 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1556 &dma, GFP_KERNEL);
1557 if (!nic_stats)
1558 return;
1559
1560 /* begin NIC statistics dump */
1561 cpw32(StatsAddr + 4, (u64)dma >> 32);
1562 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1563 cpr32(StatsAddr);
1564
1565 for (i = 0; i < 1000; i++) {
1566 if ((cpr32(StatsAddr) & DumpStats) == 0)
1567 break;
1568 udelay(10);
1569 }
1570 cpw32(StatsAddr, 0);
1571 cpw32(StatsAddr + 4, 0);
1572 cpr32(StatsAddr);
1573
1574 i = 0;
1575 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1576 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1577 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1578 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1579 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1580 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1581 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1582 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1583 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1584 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1585 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1586 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1587 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1588 tmp_stats[i++] = cp->cp_stats.rx_frags;
1589 BUG_ON(i != CP_NUM_STATS);
1590
1591 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1592 }
1593
1594 static const struct ethtool_ops cp_ethtool_ops = {
1595 .get_drvinfo = cp_get_drvinfo,
1596 .get_regs_len = cp_get_regs_len,
1597 .get_sset_count = cp_get_sset_count,
1598 .get_settings = cp_get_settings,
1599 .set_settings = cp_set_settings,
1600 .nway_reset = cp_nway_reset,
1601 .get_link = ethtool_op_get_link,
1602 .get_msglevel = cp_get_msglevel,
1603 .set_msglevel = cp_set_msglevel,
1604 .get_regs = cp_get_regs,
1605 .get_wol = cp_get_wol,
1606 .set_wol = cp_set_wol,
1607 .get_strings = cp_get_strings,
1608 .get_ethtool_stats = cp_get_ethtool_stats,
1609 .get_eeprom_len = cp_get_eeprom_len,
1610 .get_eeprom = cp_get_eeprom,
1611 .set_eeprom = cp_set_eeprom,
1612 .get_ringparam = cp_get_ringparam,
1613 };
1614
1615 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1616 {
1617 struct cp_private *cp = netdev_priv(dev);
1618 int rc;
1619 unsigned long flags;
1620
1621 if (!netif_running(dev))
1622 return -EINVAL;
1623
1624 spin_lock_irqsave(&cp->lock, flags);
1625 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1626 spin_unlock_irqrestore(&cp->lock, flags);
1627 return rc;
1628 }
1629
1630 static int cp_set_mac_address(struct net_device *dev, void *p)
1631 {
1632 struct cp_private *cp = netdev_priv(dev);
1633 struct sockaddr *addr = p;
1634
1635 if (!is_valid_ether_addr(addr->sa_data))
1636 return -EADDRNOTAVAIL;
1637
1638 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1639
1640 spin_lock_irq(&cp->lock);
1641
1642 cpw8_f(Cfg9346, Cfg9346_Unlock);
1643 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1644 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1645 cpw8_f(Cfg9346, Cfg9346_Lock);
1646
1647 spin_unlock_irq(&cp->lock);
1648
1649 return 0;
1650 }
1651
1652 /* Serial EEPROM section. */
1653
1654 /* EEPROM_Ctrl bits. */
1655 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1656 #define EE_CS 0x08 /* EEPROM chip select. */
1657 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1658 #define EE_WRITE_0 0x00
1659 #define EE_WRITE_1 0x02
1660 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1661 #define EE_ENB (0x80 | EE_CS)
1662
1663 /* Delay between EEPROM clock transitions.
1664 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1665 */
1666
1667 #define eeprom_delay() readb(ee_addr)
1668
1669 /* The EEPROM commands include the alway-set leading bit. */
1670 #define EE_EXTEND_CMD (4)
1671 #define EE_WRITE_CMD (5)
1672 #define EE_READ_CMD (6)
1673 #define EE_ERASE_CMD (7)
1674
1675 #define EE_EWDS_ADDR (0)
1676 #define EE_WRAL_ADDR (1)
1677 #define EE_ERAL_ADDR (2)
1678 #define EE_EWEN_ADDR (3)
1679
1680 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1681
1682 static void eeprom_cmd_start(void __iomem *ee_addr)
1683 {
1684 writeb (EE_ENB & ~EE_CS, ee_addr);
1685 writeb (EE_ENB, ee_addr);
1686 eeprom_delay ();
1687 }
1688
1689 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1690 {
1691 int i;
1692
1693 /* Shift the command bits out. */
1694 for (i = cmd_len - 1; i >= 0; i--) {
1695 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1696 writeb (EE_ENB | dataval, ee_addr);
1697 eeprom_delay ();
1698 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1699 eeprom_delay ();
1700 }
1701 writeb (EE_ENB, ee_addr);
1702 eeprom_delay ();
1703 }
1704
1705 static void eeprom_cmd_end(void __iomem *ee_addr)
1706 {
1707 writeb(0, ee_addr);
1708 eeprom_delay ();
1709 }
1710
1711 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1712 int addr_len)
1713 {
1714 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1715
1716 eeprom_cmd_start(ee_addr);
1717 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1718 eeprom_cmd_end(ee_addr);
1719 }
1720
1721 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1722 {
1723 int i;
1724 u16 retval = 0;
1725 void __iomem *ee_addr = ioaddr + Cfg9346;
1726 int read_cmd = location | (EE_READ_CMD << addr_len);
1727
1728 eeprom_cmd_start(ee_addr);
1729 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1730
1731 for (i = 16; i > 0; i--) {
1732 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1733 eeprom_delay ();
1734 retval =
1735 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1736 0);
1737 writeb (EE_ENB, ee_addr);
1738 eeprom_delay ();
1739 }
1740
1741 eeprom_cmd_end(ee_addr);
1742
1743 return retval;
1744 }
1745
1746 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1747 int addr_len)
1748 {
1749 int i;
1750 void __iomem *ee_addr = ioaddr + Cfg9346;
1751 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1752
1753 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1754
1755 eeprom_cmd_start(ee_addr);
1756 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1757 eeprom_cmd(ee_addr, val, 16);
1758 eeprom_cmd_end(ee_addr);
1759
1760 eeprom_cmd_start(ee_addr);
1761 for (i = 0; i < 20000; i++)
1762 if (readb(ee_addr) & EE_DATA_READ)
1763 break;
1764 eeprom_cmd_end(ee_addr);
1765
1766 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1767 }
1768
1769 static int cp_get_eeprom_len(struct net_device *dev)
1770 {
1771 struct cp_private *cp = netdev_priv(dev);
1772 int size;
1773
1774 spin_lock_irq(&cp->lock);
1775 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1776 spin_unlock_irq(&cp->lock);
1777
1778 return size;
1779 }
1780
1781 static int cp_get_eeprom(struct net_device *dev,
1782 struct ethtool_eeprom *eeprom, u8 *data)
1783 {
1784 struct cp_private *cp = netdev_priv(dev);
1785 unsigned int addr_len;
1786 u16 val;
1787 u32 offset = eeprom->offset >> 1;
1788 u32 len = eeprom->len;
1789 u32 i = 0;
1790
1791 eeprom->magic = CP_EEPROM_MAGIC;
1792
1793 spin_lock_irq(&cp->lock);
1794
1795 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1796
1797 if (eeprom->offset & 1) {
1798 val = read_eeprom(cp->regs, offset, addr_len);
1799 data[i++] = (u8)(val >> 8);
1800 offset++;
1801 }
1802
1803 while (i < len - 1) {
1804 val = read_eeprom(cp->regs, offset, addr_len);
1805 data[i++] = (u8)val;
1806 data[i++] = (u8)(val >> 8);
1807 offset++;
1808 }
1809
1810 if (i < len) {
1811 val = read_eeprom(cp->regs, offset, addr_len);
1812 data[i] = (u8)val;
1813 }
1814
1815 spin_unlock_irq(&cp->lock);
1816 return 0;
1817 }
1818
1819 static int cp_set_eeprom(struct net_device *dev,
1820 struct ethtool_eeprom *eeprom, u8 *data)
1821 {
1822 struct cp_private *cp = netdev_priv(dev);
1823 unsigned int addr_len;
1824 u16 val;
1825 u32 offset = eeprom->offset >> 1;
1826 u32 len = eeprom->len;
1827 u32 i = 0;
1828
1829 if (eeprom->magic != CP_EEPROM_MAGIC)
1830 return -EINVAL;
1831
1832 spin_lock_irq(&cp->lock);
1833
1834 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1835
1836 if (eeprom->offset & 1) {
1837 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1838 val |= (u16)data[i++] << 8;
1839 write_eeprom(cp->regs, offset, val, addr_len);
1840 offset++;
1841 }
1842
1843 while (i < len - 1) {
1844 val = (u16)data[i++];
1845 val |= (u16)data[i++] << 8;
1846 write_eeprom(cp->regs, offset, val, addr_len);
1847 offset++;
1848 }
1849
1850 if (i < len) {
1851 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1852 val |= (u16)data[i];
1853 write_eeprom(cp->regs, offset, val, addr_len);
1854 }
1855
1856 spin_unlock_irq(&cp->lock);
1857 return 0;
1858 }
1859
1860 /* Put the board into D3cold state and wait for WakeUp signal */
1861 static void cp_set_d3_state (struct cp_private *cp)
1862 {
1863 pci_enable_wake(cp->pdev, PCI_D0, 1); /* Enable PME# generation */
1864 pci_set_power_state (cp->pdev, PCI_D3hot);
1865 }
1866
1867 static const struct net_device_ops cp_netdev_ops = {
1868 .ndo_open = cp_open,
1869 .ndo_stop = cp_close,
1870 .ndo_validate_addr = eth_validate_addr,
1871 .ndo_set_mac_address = cp_set_mac_address,
1872 .ndo_set_rx_mode = cp_set_rx_mode,
1873 .ndo_get_stats = cp_get_stats,
1874 .ndo_do_ioctl = cp_ioctl,
1875 .ndo_start_xmit = cp_start_xmit,
1876 .ndo_tx_timeout = cp_tx_timeout,
1877 .ndo_set_features = cp_set_features,
1878 .ndo_change_mtu = cp_change_mtu,
1879
1880 #ifdef CONFIG_NET_POLL_CONTROLLER
1881 .ndo_poll_controller = cp_poll_controller,
1882 #endif
1883 };
1884
1885 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1886 {
1887 struct net_device *dev;
1888 struct cp_private *cp;
1889 int rc;
1890 void __iomem *regs;
1891 resource_size_t pciaddr;
1892 unsigned int addr_len, i, pci_using_dac;
1893
1894 #ifndef MODULE
1895 static int version_printed;
1896 if (version_printed++ == 0)
1897 pr_info("%s", version);
1898 #endif
1899
1900 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1901 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1902 dev_info(&pdev->dev,
1903 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1904 pdev->vendor, pdev->device, pdev->revision);
1905 return -ENODEV;
1906 }
1907
1908 dev = alloc_etherdev(sizeof(struct cp_private));
1909 if (!dev)
1910 return -ENOMEM;
1911 SET_NETDEV_DEV(dev, &pdev->dev);
1912
1913 cp = netdev_priv(dev);
1914 cp->pdev = pdev;
1915 cp->dev = dev;
1916 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1917 spin_lock_init (&cp->lock);
1918 cp->mii_if.dev = dev;
1919 cp->mii_if.mdio_read = mdio_read;
1920 cp->mii_if.mdio_write = mdio_write;
1921 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1922 cp->mii_if.phy_id_mask = 0x1f;
1923 cp->mii_if.reg_num_mask = 0x1f;
1924 cp_set_rxbufsize(cp);
1925
1926 rc = pci_enable_device(pdev);
1927 if (rc)
1928 goto err_out_free;
1929
1930 rc = pci_set_mwi(pdev);
1931 if (rc)
1932 goto err_out_disable;
1933
1934 rc = pci_request_regions(pdev, DRV_NAME);
1935 if (rc)
1936 goto err_out_mwi;
1937
1938 pciaddr = pci_resource_start(pdev, 1);
1939 if (!pciaddr) {
1940 rc = -EIO;
1941 dev_err(&pdev->dev, "no MMIO resource\n");
1942 goto err_out_res;
1943 }
1944 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1945 rc = -EIO;
1946 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1947 (unsigned long long)pci_resource_len(pdev, 1));
1948 goto err_out_res;
1949 }
1950
1951 /* Configure DMA attributes. */
1952 if ((sizeof(dma_addr_t) > 4) &&
1953 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1954 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1955 pci_using_dac = 1;
1956 } else {
1957 pci_using_dac = 0;
1958
1959 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1960 if (rc) {
1961 dev_err(&pdev->dev,
1962 "No usable DMA configuration, aborting\n");
1963 goto err_out_res;
1964 }
1965 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1966 if (rc) {
1967 dev_err(&pdev->dev,
1968 "No usable consistent DMA configuration, aborting\n");
1969 goto err_out_res;
1970 }
1971 }
1972
1973 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1974 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1975
1976 dev->features |= NETIF_F_RXCSUM;
1977 dev->hw_features |= NETIF_F_RXCSUM;
1978
1979 regs = ioremap(pciaddr, CP_REGS_SIZE);
1980 if (!regs) {
1981 rc = -EIO;
1982 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1983 (unsigned long long)pci_resource_len(pdev, 1),
1984 (unsigned long long)pciaddr);
1985 goto err_out_res;
1986 }
1987 cp->regs = regs;
1988
1989 cp_stop_hw(cp);
1990
1991 /* read MAC address from EEPROM */
1992 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1993 for (i = 0; i < 3; i++)
1994 ((__le16 *) (dev->dev_addr))[i] =
1995 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1996
1997 dev->netdev_ops = &cp_netdev_ops;
1998 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1999 dev->ethtool_ops = &cp_ethtool_ops;
2000 dev->watchdog_timeo = TX_TIMEOUT;
2001
2002 dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
2003
2004 if (pci_using_dac)
2005 dev->features |= NETIF_F_HIGHDMA;
2006
2007 /* disabled by default until verified */
2008 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
2009 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
2010 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
2011 NETIF_F_HIGHDMA;
2012
2013 rc = register_netdev(dev);
2014 if (rc)
2015 goto err_out_iomap;
2016
2017 netdev_info(dev, "RTL-8139C+ at 0x%p, %pM, IRQ %d\n",
2018 regs, dev->dev_addr, pdev->irq);
2019
2020 pci_set_drvdata(pdev, dev);
2021
2022 /* enable busmastering and memory-write-invalidate */
2023 pci_set_master(pdev);
2024
2025 if (cp->wol_enabled)
2026 cp_set_d3_state (cp);
2027
2028 return 0;
2029
2030 err_out_iomap:
2031 iounmap(regs);
2032 err_out_res:
2033 pci_release_regions(pdev);
2034 err_out_mwi:
2035 pci_clear_mwi(pdev);
2036 err_out_disable:
2037 pci_disable_device(pdev);
2038 err_out_free:
2039 free_netdev(dev);
2040 return rc;
2041 }
2042
2043 static void cp_remove_one (struct pci_dev *pdev)
2044 {
2045 struct net_device *dev = pci_get_drvdata(pdev);
2046 struct cp_private *cp = netdev_priv(dev);
2047
2048 unregister_netdev(dev);
2049 iounmap(cp->regs);
2050 if (cp->wol_enabled)
2051 pci_set_power_state (pdev, PCI_D0);
2052 pci_release_regions(pdev);
2053 pci_clear_mwi(pdev);
2054 pci_disable_device(pdev);
2055 pci_set_drvdata(pdev, NULL);
2056 free_netdev(dev);
2057 }
2058
2059 #ifdef CONFIG_PM
2060 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2061 {
2062 struct net_device *dev = pci_get_drvdata(pdev);
2063 struct cp_private *cp = netdev_priv(dev);
2064 unsigned long flags;
2065
2066 if (!netif_running(dev))
2067 return 0;
2068
2069 netif_device_detach (dev);
2070 netif_stop_queue (dev);
2071
2072 spin_lock_irqsave (&cp->lock, flags);
2073
2074 /* Disable Rx and Tx */
2075 cpw16 (IntrMask, 0);
2076 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2077
2078 spin_unlock_irqrestore (&cp->lock, flags);
2079
2080 pci_save_state(pdev);
2081 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2082 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2083
2084 return 0;
2085 }
2086
2087 static int cp_resume (struct pci_dev *pdev)
2088 {
2089 struct net_device *dev = pci_get_drvdata (pdev);
2090 struct cp_private *cp = netdev_priv(dev);
2091 unsigned long flags;
2092
2093 if (!netif_running(dev))
2094 return 0;
2095
2096 netif_device_attach (dev);
2097
2098 pci_set_power_state(pdev, PCI_D0);
2099 pci_restore_state(pdev);
2100 pci_enable_wake(pdev, PCI_D0, 0);
2101
2102 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2103 cp_init_rings_index (cp);
2104 cp_init_hw (cp);
2105 cp_enable_irq(cp);
2106 netif_start_queue (dev);
2107
2108 spin_lock_irqsave (&cp->lock, flags);
2109
2110 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2111
2112 spin_unlock_irqrestore (&cp->lock, flags);
2113
2114 return 0;
2115 }
2116 #endif /* CONFIG_PM */
2117
2118 static struct pci_driver cp_driver = {
2119 .name = DRV_NAME,
2120 .id_table = cp_pci_tbl,
2121 .probe = cp_init_one,
2122 .remove = cp_remove_one,
2123 #ifdef CONFIG_PM
2124 .resume = cp_resume,
2125 .suspend = cp_suspend,
2126 #endif
2127 };
2128
2129 static int __init cp_init (void)
2130 {
2131 #ifdef MODULE
2132 pr_info("%s", version);
2133 #endif
2134 return pci_register_driver(&cp_driver);
2135 }
2136
2137 static void __exit cp_exit (void)
2138 {
2139 pci_unregister_driver (&cp_driver);
2140 }
2141
2142 module_init(cp_init);
2143 module_exit(cp_exit);
Linux kernel - Deliverables
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