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Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dma
[deliverable/linux.git] / drivers / net / ethernet / realtek / 8139cp.c
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
51 #define DRV_NAME "8139cp"
52 #define DRV_VERSION "1.3"
53 #define DRV_RELDATE "Mar 22, 2004"
54
55
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/interrupt.h>
64 #include <linux/pci.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/delay.h>
67 #include <linux/ethtool.h>
68 #include <linux/gfp.h>
69 #include <linux/mii.h>
70 #include <linux/if_vlan.h>
71 #include <linux/crc32.h>
72 #include <linux/in.h>
73 #include <linux/ip.h>
74 #include <linux/tcp.h>
75 #include <linux/udp.h>
76 #include <linux/cache.h>
77 #include <asm/io.h>
78 #include <asm/irq.h>
79 #include <asm/uaccess.h>
80
81 /* These identify the driver base version and may not be removed. */
82 static char version[] =
83 DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
84
85 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
86 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
87 MODULE_VERSION(DRV_VERSION);
88 MODULE_LICENSE("GPL");
89
90 static int debug = -1;
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
93
94 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
95 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
96 static int multicast_filter_limit = 32;
97 module_param(multicast_filter_limit, int, 0);
98 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
99
100 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
101 NETIF_MSG_PROBE | \
102 NETIF_MSG_LINK)
103 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
104 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
105 #define CP_REGS_SIZE (0xff + 1)
106 #define CP_REGS_VER 1 /* version 1 */
107 #define CP_RX_RING_SIZE 64
108 #define CP_TX_RING_SIZE 64
109 #define CP_RING_BYTES \
110 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
111 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
112 CP_STATS_SIZE)
113 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
114 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
115 #define TX_BUFFS_AVAIL(CP) \
116 (((CP)->tx_tail <= (CP)->tx_head) ? \
117 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
118 (CP)->tx_tail - (CP)->tx_head - 1)
119
120 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
121 #define CP_INTERNAL_PHY 32
122
123 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
124 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
125 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
126 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
128
129 /* Time in jiffies before concluding the transmitter is hung. */
130 #define TX_TIMEOUT (6*HZ)
131
132 /* hardware minimum and maximum for a single frame's data payload */
133 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
134 #define CP_MAX_MTU 4096
135
136 enum {
137 /* NIC register offsets */
138 MAC0 = 0x00, /* Ethernet hardware address. */
139 MAR0 = 0x08, /* Multicast filter. */
140 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
141 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
142 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
143 Cmd = 0x37, /* Command register */
144 IntrMask = 0x3C, /* Interrupt mask */
145 IntrStatus = 0x3E, /* Interrupt status */
146 TxConfig = 0x40, /* Tx configuration */
147 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
148 RxConfig = 0x44, /* Rx configuration */
149 RxMissed = 0x4C, /* 24 bits valid, write clears */
150 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
151 Config1 = 0x52, /* Config1 */
152 Config3 = 0x59, /* Config3 */
153 Config4 = 0x5A, /* Config4 */
154 MultiIntr = 0x5C, /* Multiple interrupt select */
155 BasicModeCtrl = 0x62, /* MII BMCR */
156 BasicModeStatus = 0x64, /* MII BMSR */
157 NWayAdvert = 0x66, /* MII ADVERTISE */
158 NWayLPAR = 0x68, /* MII LPA */
159 NWayExpansion = 0x6A, /* MII Expansion */
160 Config5 = 0xD8, /* Config5 */
161 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
162 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
163 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
164 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
165 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
166 TxThresh = 0xEC, /* Early Tx threshold */
167 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
168 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
169
170 /* Tx and Rx status descriptors */
171 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
172 RingEnd = (1 << 30), /* End of descriptor ring */
173 FirstFrag = (1 << 29), /* First segment of a packet */
174 LastFrag = (1 << 28), /* Final segment of a packet */
175 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
176 MSSShift = 16, /* MSS value position */
177 MSSMask = 0xfff, /* MSS value: 11 bits */
178 TxError = (1 << 23), /* Tx error summary */
179 RxError = (1 << 20), /* Rx error summary */
180 IPCS = (1 << 18), /* Calculate IP checksum */
181 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
182 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
183 TxVlanTag = (1 << 17), /* Add VLAN tag */
184 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
185 IPFail = (1 << 15), /* IP checksum failed */
186 UDPFail = (1 << 14), /* UDP/IP checksum failed */
187 TCPFail = (1 << 13), /* TCP/IP checksum failed */
188 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
189 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
190 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
191 RxProtoTCP = 1,
192 RxProtoUDP = 2,
193 RxProtoIP = 3,
194 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
195 TxOWC = (1 << 22), /* Tx Out-of-window collision */
196 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
197 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
198 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
199 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
200 RxErrFrame = (1 << 27), /* Rx frame alignment error */
201 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
202 RxErrCRC = (1 << 18), /* Rx CRC error */
203 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
204 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
205 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
206
207 /* StatsAddr register */
208 DumpStats = (1 << 3), /* Begin stats dump */
209
210 /* RxConfig register */
211 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
212 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
213 AcceptErr = 0x20, /* Accept packets with CRC errors */
214 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
215 AcceptBroadcast = 0x08, /* Accept broadcast packets */
216 AcceptMulticast = 0x04, /* Accept multicast packets */
217 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
218 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
219
220 /* IntrMask / IntrStatus registers */
221 PciErr = (1 << 15), /* System error on the PCI bus */
222 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
223 LenChg = (1 << 13), /* Cable length change */
224 SWInt = (1 << 8), /* Software-requested interrupt */
225 TxEmpty = (1 << 7), /* No Tx descriptors available */
226 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
227 LinkChg = (1 << 5), /* Packet underrun, or link change */
228 RxEmpty = (1 << 4), /* No Rx descriptors available */
229 TxErr = (1 << 3), /* Tx error */
230 TxOK = (1 << 2), /* Tx packet sent */
231 RxErr = (1 << 1), /* Rx error */
232 RxOK = (1 << 0), /* Rx packet received */
233 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
234 but hardware likes to raise it */
235
236 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
237 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
238 RxErr | RxOK | IntrResvd,
239
240 /* C mode command register */
241 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
242 RxOn = (1 << 3), /* Rx mode enable */
243 TxOn = (1 << 2), /* Tx mode enable */
244
245 /* C+ mode command register */
246 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
247 RxChkSum = (1 << 5), /* Rx checksum offload enable */
248 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
249 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
250 CpRxOn = (1 << 1), /* Rx mode enable */
251 CpTxOn = (1 << 0), /* Tx mode enable */
252
253 /* Cfg9436 EEPROM control register */
254 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
255 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
256
257 /* TxConfig register */
258 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
259 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
260
261 /* Early Tx Threshold register */
262 TxThreshMask = 0x3f, /* Mask bits 5-0 */
263 TxThreshMax = 2048, /* Max early Tx threshold */
264
265 /* Config1 register */
266 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
267 LWACT = (1 << 4), /* LWAKE active mode */
268 PMEnable = (1 << 0), /* Enable various PM features of chip */
269
270 /* Config3 register */
271 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
272 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
273 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
274
275 /* Config4 register */
276 LWPTN = (1 << 1), /* LWAKE Pattern */
277 LWPME = (1 << 4), /* LANWAKE vs PMEB */
278
279 /* Config5 register */
280 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
281 MWF = (1 << 5), /* Accept Multicast wakeup frame */
282 UWF = (1 << 4), /* Accept Unicast wakeup frame */
283 LANWake = (1 << 1), /* Enable LANWake signal */
284 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
285
286 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
287 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
288 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
289 };
290
291 static const unsigned int cp_rx_config =
292 (RX_FIFO_THRESH << RxCfgFIFOShift) |
293 (RX_DMA_BURST << RxCfgDMAShift);
294
295 struct cp_desc {
296 __le32 opts1;
297 __le32 opts2;
298 __le64 addr;
299 };
300
301 struct cp_dma_stats {
302 __le64 tx_ok;
303 __le64 rx_ok;
304 __le64 tx_err;
305 __le32 rx_err;
306 __le16 rx_fifo;
307 __le16 frame_align;
308 __le32 tx_ok_1col;
309 __le32 tx_ok_mcol;
310 __le64 rx_ok_phys;
311 __le64 rx_ok_bcast;
312 __le32 rx_ok_mcast;
313 __le16 tx_abort;
314 __le16 tx_underrun;
315 } __packed;
316
317 struct cp_extra_stats {
318 unsigned long rx_frags;
319 };
320
321 struct cp_private {
322 void __iomem *regs;
323 struct net_device *dev;
324 spinlock_t lock;
325 u32 msg_enable;
326
327 struct napi_struct napi;
328
329 struct pci_dev *pdev;
330 u32 rx_config;
331 u16 cpcmd;
332
333 struct cp_extra_stats cp_stats;
334
335 unsigned rx_head ____cacheline_aligned;
336 unsigned rx_tail;
337 struct cp_desc *rx_ring;
338 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
339
340 unsigned tx_head ____cacheline_aligned;
341 unsigned tx_tail;
342 struct cp_desc *tx_ring;
343 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
344
345 unsigned rx_buf_sz;
346 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
347
348 dma_addr_t ring_dma;
349
350 struct mii_if_info mii_if;
351 };
352
353 #define cpr8(reg) readb(cp->regs + (reg))
354 #define cpr16(reg) readw(cp->regs + (reg))
355 #define cpr32(reg) readl(cp->regs + (reg))
356 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
357 #define cpw16(reg,val) writew((val), cp->regs + (reg))
358 #define cpw32(reg,val) writel((val), cp->regs + (reg))
359 #define cpw8_f(reg,val) do { \
360 writeb((val), cp->regs + (reg)); \
361 readb(cp->regs + (reg)); \
362 } while (0)
363 #define cpw16_f(reg,val) do { \
364 writew((val), cp->regs + (reg)); \
365 readw(cp->regs + (reg)); \
366 } while (0)
367 #define cpw32_f(reg,val) do { \
368 writel((val), cp->regs + (reg)); \
369 readl(cp->regs + (reg)); \
370 } while (0)
371
372
373 static void __cp_set_rx_mode (struct net_device *dev);
374 static void cp_tx (struct cp_private *cp);
375 static void cp_clean_rings (struct cp_private *cp);
376 #ifdef CONFIG_NET_POLL_CONTROLLER
377 static void cp_poll_controller(struct net_device *dev);
378 #endif
379 static int cp_get_eeprom_len(struct net_device *dev);
380 static int cp_get_eeprom(struct net_device *dev,
381 struct ethtool_eeprom *eeprom, u8 *data);
382 static int cp_set_eeprom(struct net_device *dev,
383 struct ethtool_eeprom *eeprom, u8 *data);
384
385 static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
386 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
387 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
388 { },
389 };
390 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
391
392 static struct {
393 const char str[ETH_GSTRING_LEN];
394 } ethtool_stats_keys[] = {
395 { "tx_ok" },
396 { "rx_ok" },
397 { "tx_err" },
398 { "rx_err" },
399 { "rx_fifo" },
400 { "frame_align" },
401 { "tx_ok_1col" },
402 { "tx_ok_mcol" },
403 { "rx_ok_phys" },
404 { "rx_ok_bcast" },
405 { "rx_ok_mcast" },
406 { "tx_abort" },
407 { "tx_underrun" },
408 { "rx_frags" },
409 };
410
411
412 static inline void cp_set_rxbufsize (struct cp_private *cp)
413 {
414 unsigned int mtu = cp->dev->mtu;
415
416 if (mtu > ETH_DATA_LEN)
417 /* MTU + ethernet header + FCS + optional VLAN tag */
418 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
419 else
420 cp->rx_buf_sz = PKT_BUF_SZ;
421 }
422
423 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
424 struct cp_desc *desc)
425 {
426 u32 opts2 = le32_to_cpu(desc->opts2);
427
428 skb->protocol = eth_type_trans (skb, cp->dev);
429
430 cp->dev->stats.rx_packets++;
431 cp->dev->stats.rx_bytes += skb->len;
432
433 if (opts2 & RxVlanTagged)
434 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
435
436 napi_gro_receive(&cp->napi, skb);
437 }
438
439 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
440 u32 status, u32 len)
441 {
442 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
443 rx_tail, status, len);
444 cp->dev->stats.rx_errors++;
445 if (status & RxErrFrame)
446 cp->dev->stats.rx_frame_errors++;
447 if (status & RxErrCRC)
448 cp->dev->stats.rx_crc_errors++;
449 if ((status & RxErrRunt) || (status & RxErrLong))
450 cp->dev->stats.rx_length_errors++;
451 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
452 cp->dev->stats.rx_length_errors++;
453 if (status & RxErrFIFO)
454 cp->dev->stats.rx_fifo_errors++;
455 }
456
457 static inline unsigned int cp_rx_csum_ok (u32 status)
458 {
459 unsigned int protocol = (status >> 16) & 0x3;
460
461 if (((protocol == RxProtoTCP) && !(status & TCPFail)) ||
462 ((protocol == RxProtoUDP) && !(status & UDPFail)))
463 return 1;
464 else
465 return 0;
466 }
467
468 static int cp_rx_poll(struct napi_struct *napi, int budget)
469 {
470 struct cp_private *cp = container_of(napi, struct cp_private, napi);
471 struct net_device *dev = cp->dev;
472 unsigned int rx_tail = cp->rx_tail;
473 int rx;
474
475 rx_status_loop:
476 rx = 0;
477 cpw16(IntrStatus, cp_rx_intr_mask);
478
479 while (1) {
480 u32 status, len;
481 dma_addr_t mapping, new_mapping;
482 struct sk_buff *skb, *new_skb;
483 struct cp_desc *desc;
484 const unsigned buflen = cp->rx_buf_sz;
485
486 skb = cp->rx_skb[rx_tail];
487 BUG_ON(!skb);
488
489 desc = &cp->rx_ring[rx_tail];
490 status = le32_to_cpu(desc->opts1);
491 if (status & DescOwn)
492 break;
493
494 len = (status & 0x1fff) - 4;
495 mapping = le64_to_cpu(desc->addr);
496
497 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
498 /* we don't support incoming fragmented frames.
499 * instead, we attempt to ensure that the
500 * pre-allocated RX skbs are properly sized such
501 * that RX fragments are never encountered
502 */
503 cp_rx_err_acct(cp, rx_tail, status, len);
504 dev->stats.rx_dropped++;
505 cp->cp_stats.rx_frags++;
506 goto rx_next;
507 }
508
509 if (status & (RxError | RxErrFIFO)) {
510 cp_rx_err_acct(cp, rx_tail, status, len);
511 goto rx_next;
512 }
513
514 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
515 rx_tail, status, len);
516
517 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
518 if (!new_skb) {
519 dev->stats.rx_dropped++;
520 goto rx_next;
521 }
522
523 new_mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
524 PCI_DMA_FROMDEVICE);
525 if (dma_mapping_error(&cp->pdev->dev, new_mapping)) {
526 dev->stats.rx_dropped++;
527 goto rx_next;
528 }
529
530 dma_unmap_single(&cp->pdev->dev, mapping,
531 buflen, PCI_DMA_FROMDEVICE);
532
533 /* Handle checksum offloading for incoming packets. */
534 if (cp_rx_csum_ok(status))
535 skb->ip_summed = CHECKSUM_UNNECESSARY;
536 else
537 skb_checksum_none_assert(skb);
538
539 skb_put(skb, len);
540
541 cp->rx_skb[rx_tail] = new_skb;
542
543 cp_rx_skb(cp, skb, desc);
544 rx++;
545 mapping = new_mapping;
546
547 rx_next:
548 cp->rx_ring[rx_tail].opts2 = 0;
549 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
550 if (rx_tail == (CP_RX_RING_SIZE - 1))
551 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
552 cp->rx_buf_sz);
553 else
554 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
555 rx_tail = NEXT_RX(rx_tail);
556
557 if (rx >= budget)
558 break;
559 }
560
561 cp->rx_tail = rx_tail;
562
563 /* if we did not reach work limit, then we're done with
564 * this round of polling
565 */
566 if (rx < budget) {
567 unsigned long flags;
568
569 if (cpr16(IntrStatus) & cp_rx_intr_mask)
570 goto rx_status_loop;
571
572 napi_gro_flush(napi, false);
573 spin_lock_irqsave(&cp->lock, flags);
574 __napi_complete(napi);
575 cpw16_f(IntrMask, cp_intr_mask);
576 spin_unlock_irqrestore(&cp->lock, flags);
577 }
578
579 return rx;
580 }
581
582 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
583 {
584 struct net_device *dev = dev_instance;
585 struct cp_private *cp;
586 int handled = 0;
587 u16 status;
588
589 if (unlikely(dev == NULL))
590 return IRQ_NONE;
591 cp = netdev_priv(dev);
592
593 spin_lock(&cp->lock);
594
595 status = cpr16(IntrStatus);
596 if (!status || (status == 0xFFFF))
597 goto out_unlock;
598
599 handled = 1;
600
601 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
602 status, cpr8(Cmd), cpr16(CpCmd));
603
604 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
605
606 /* close possible race's with dev_close */
607 if (unlikely(!netif_running(dev))) {
608 cpw16(IntrMask, 0);
609 goto out_unlock;
610 }
611
612 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
613 if (napi_schedule_prep(&cp->napi)) {
614 cpw16_f(IntrMask, cp_norx_intr_mask);
615 __napi_schedule(&cp->napi);
616 }
617
618 if (status & (TxOK | TxErr | TxEmpty | SWInt))
619 cp_tx(cp);
620 if (status & LinkChg)
621 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
622
623
624 if (status & PciErr) {
625 u16 pci_status;
626
627 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
628 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
629 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
630 status, pci_status);
631
632 /* TODO: reset hardware */
633 }
634
635 out_unlock:
636 spin_unlock(&cp->lock);
637
638 return IRQ_RETVAL(handled);
639 }
640
641 #ifdef CONFIG_NET_POLL_CONTROLLER
642 /*
643 * Polling receive - used by netconsole and other diagnostic tools
644 * to allow network i/o with interrupts disabled.
645 */
646 static void cp_poll_controller(struct net_device *dev)
647 {
648 struct cp_private *cp = netdev_priv(dev);
649 const int irq = cp->pdev->irq;
650
651 disable_irq(irq);
652 cp_interrupt(irq, dev);
653 enable_irq(irq);
654 }
655 #endif
656
657 static void cp_tx (struct cp_private *cp)
658 {
659 unsigned tx_head = cp->tx_head;
660 unsigned tx_tail = cp->tx_tail;
661 unsigned bytes_compl = 0, pkts_compl = 0;
662
663 while (tx_tail != tx_head) {
664 struct cp_desc *txd = cp->tx_ring + tx_tail;
665 struct sk_buff *skb;
666 u32 status;
667
668 rmb();
669 status = le32_to_cpu(txd->opts1);
670 if (status & DescOwn)
671 break;
672
673 skb = cp->tx_skb[tx_tail];
674 BUG_ON(!skb);
675
676 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
677 le32_to_cpu(txd->opts1) & 0xffff,
678 PCI_DMA_TODEVICE);
679
680 bytes_compl += skb->len;
681 pkts_compl++;
682
683 if (status & LastFrag) {
684 if (status & (TxError | TxFIFOUnder)) {
685 netif_dbg(cp, tx_err, cp->dev,
686 "tx err, status 0x%x\n", status);
687 cp->dev->stats.tx_errors++;
688 if (status & TxOWC)
689 cp->dev->stats.tx_window_errors++;
690 if (status & TxMaxCol)
691 cp->dev->stats.tx_aborted_errors++;
692 if (status & TxLinkFail)
693 cp->dev->stats.tx_carrier_errors++;
694 if (status & TxFIFOUnder)
695 cp->dev->stats.tx_fifo_errors++;
696 } else {
697 cp->dev->stats.collisions +=
698 ((status >> TxColCntShift) & TxColCntMask);
699 cp->dev->stats.tx_packets++;
700 cp->dev->stats.tx_bytes += skb->len;
701 netif_dbg(cp, tx_done, cp->dev,
702 "tx done, slot %d\n", tx_tail);
703 }
704 dev_kfree_skb_irq(skb);
705 }
706
707 cp->tx_skb[tx_tail] = NULL;
708
709 tx_tail = NEXT_TX(tx_tail);
710 }
711
712 cp->tx_tail = tx_tail;
713
714 netdev_completed_queue(cp->dev, pkts_compl, bytes_compl);
715 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
716 netif_wake_queue(cp->dev);
717 }
718
719 static inline u32 cp_tx_vlan_tag(struct sk_buff *skb)
720 {
721 return vlan_tx_tag_present(skb) ?
722 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
723 }
724
725 static void unwind_tx_frag_mapping(struct cp_private *cp, struct sk_buff *skb,
726 int first, int entry_last)
727 {
728 int frag, index;
729 struct cp_desc *txd;
730 skb_frag_t *this_frag;
731 for (frag = 0; frag+first < entry_last; frag++) {
732 index = first+frag;
733 cp->tx_skb[index] = NULL;
734 txd = &cp->tx_ring[index];
735 this_frag = &skb_shinfo(skb)->frags[frag];
736 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
737 skb_frag_size(this_frag), PCI_DMA_TODEVICE);
738 }
739 }
740
741 static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
742 struct net_device *dev)
743 {
744 struct cp_private *cp = netdev_priv(dev);
745 unsigned entry;
746 u32 eor, flags;
747 unsigned long intr_flags;
748 __le32 opts2;
749 int mss = 0;
750
751 spin_lock_irqsave(&cp->lock, intr_flags);
752
753 /* This is a hard error, log it. */
754 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
755 netif_stop_queue(dev);
756 spin_unlock_irqrestore(&cp->lock, intr_flags);
757 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
758 return NETDEV_TX_BUSY;
759 }
760
761 entry = cp->tx_head;
762 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
763 mss = skb_shinfo(skb)->gso_size;
764
765 opts2 = cpu_to_le32(cp_tx_vlan_tag(skb));
766
767 if (skb_shinfo(skb)->nr_frags == 0) {
768 struct cp_desc *txd = &cp->tx_ring[entry];
769 u32 len;
770 dma_addr_t mapping;
771
772 len = skb->len;
773 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
774 if (dma_mapping_error(&cp->pdev->dev, mapping))
775 goto out_dma_error;
776
777 txd->opts2 = opts2;
778 txd->addr = cpu_to_le64(mapping);
779 wmb();
780
781 flags = eor | len | DescOwn | FirstFrag | LastFrag;
782
783 if (mss)
784 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
785 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
786 const struct iphdr *ip = ip_hdr(skb);
787 if (ip->protocol == IPPROTO_TCP)
788 flags |= IPCS | TCPCS;
789 else if (ip->protocol == IPPROTO_UDP)
790 flags |= IPCS | UDPCS;
791 else
792 WARN_ON(1); /* we need a WARN() */
793 }
794
795 txd->opts1 = cpu_to_le32(flags);
796 wmb();
797
798 cp->tx_skb[entry] = skb;
799 entry = NEXT_TX(entry);
800 } else {
801 struct cp_desc *txd;
802 u32 first_len, first_eor;
803 dma_addr_t first_mapping;
804 int frag, first_entry = entry;
805 const struct iphdr *ip = ip_hdr(skb);
806
807 /* We must give this initial chunk to the device last.
808 * Otherwise we could race with the device.
809 */
810 first_eor = eor;
811 first_len = skb_headlen(skb);
812 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
813 first_len, PCI_DMA_TODEVICE);
814 if (dma_mapping_error(&cp->pdev->dev, first_mapping))
815 goto out_dma_error;
816
817 cp->tx_skb[entry] = skb;
818 entry = NEXT_TX(entry);
819
820 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
821 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
822 u32 len;
823 u32 ctrl;
824 dma_addr_t mapping;
825
826 len = skb_frag_size(this_frag);
827 mapping = dma_map_single(&cp->pdev->dev,
828 skb_frag_address(this_frag),
829 len, PCI_DMA_TODEVICE);
830 if (dma_mapping_error(&cp->pdev->dev, mapping)) {
831 unwind_tx_frag_mapping(cp, skb, first_entry, entry);
832 goto out_dma_error;
833 }
834
835 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
836
837 ctrl = eor | len | DescOwn;
838
839 if (mss)
840 ctrl |= LargeSend |
841 ((mss & MSSMask) << MSSShift);
842 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
843 if (ip->protocol == IPPROTO_TCP)
844 ctrl |= IPCS | TCPCS;
845 else if (ip->protocol == IPPROTO_UDP)
846 ctrl |= IPCS | UDPCS;
847 else
848 BUG();
849 }
850
851 if (frag == skb_shinfo(skb)->nr_frags - 1)
852 ctrl |= LastFrag;
853
854 txd = &cp->tx_ring[entry];
855 txd->opts2 = opts2;
856 txd->addr = cpu_to_le64(mapping);
857 wmb();
858
859 txd->opts1 = cpu_to_le32(ctrl);
860 wmb();
861
862 cp->tx_skb[entry] = skb;
863 entry = NEXT_TX(entry);
864 }
865
866 txd = &cp->tx_ring[first_entry];
867 txd->opts2 = opts2;
868 txd->addr = cpu_to_le64(first_mapping);
869 wmb();
870
871 if (skb->ip_summed == CHECKSUM_PARTIAL) {
872 if (ip->protocol == IPPROTO_TCP)
873 txd->opts1 = cpu_to_le32(first_eor | first_len |
874 FirstFrag | DescOwn |
875 IPCS | TCPCS);
876 else if (ip->protocol == IPPROTO_UDP)
877 txd->opts1 = cpu_to_le32(first_eor | first_len |
878 FirstFrag | DescOwn |
879 IPCS | UDPCS);
880 else
881 BUG();
882 } else
883 txd->opts1 = cpu_to_le32(first_eor | first_len |
884 FirstFrag | DescOwn);
885 wmb();
886 }
887 cp->tx_head = entry;
888
889 netdev_sent_queue(dev, skb->len);
890 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
891 entry, skb->len);
892 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
893 netif_stop_queue(dev);
894
895 out_unlock:
896 spin_unlock_irqrestore(&cp->lock, intr_flags);
897
898 cpw8(TxPoll, NormalTxPoll);
899
900 return NETDEV_TX_OK;
901 out_dma_error:
902 kfree_skb(skb);
903 cp->dev->stats.tx_dropped++;
904 goto out_unlock;
905 }
906
907 /* Set or clear the multicast filter for this adaptor.
908 This routine is not state sensitive and need not be SMP locked. */
909
910 static void __cp_set_rx_mode (struct net_device *dev)
911 {
912 struct cp_private *cp = netdev_priv(dev);
913 u32 mc_filter[2]; /* Multicast hash filter */
914 int rx_mode;
915
916 /* Note: do not reorder, GCC is clever about common statements. */
917 if (dev->flags & IFF_PROMISC) {
918 /* Unconditionally log net taps. */
919 rx_mode =
920 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
921 AcceptAllPhys;
922 mc_filter[1] = mc_filter[0] = 0xffffffff;
923 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
924 (dev->flags & IFF_ALLMULTI)) {
925 /* Too many to filter perfectly -- accept all multicasts. */
926 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
927 mc_filter[1] = mc_filter[0] = 0xffffffff;
928 } else {
929 struct netdev_hw_addr *ha;
930 rx_mode = AcceptBroadcast | AcceptMyPhys;
931 mc_filter[1] = mc_filter[0] = 0;
932 netdev_for_each_mc_addr(ha, dev) {
933 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
934
935 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
936 rx_mode |= AcceptMulticast;
937 }
938 }
939
940 /* We can safely update without stopping the chip. */
941 cp->rx_config = cp_rx_config | rx_mode;
942 cpw32_f(RxConfig, cp->rx_config);
943
944 cpw32_f (MAR0 + 0, mc_filter[0]);
945 cpw32_f (MAR0 + 4, mc_filter[1]);
946 }
947
948 static void cp_set_rx_mode (struct net_device *dev)
949 {
950 unsigned long flags;
951 struct cp_private *cp = netdev_priv(dev);
952
953 spin_lock_irqsave (&cp->lock, flags);
954 __cp_set_rx_mode(dev);
955 spin_unlock_irqrestore (&cp->lock, flags);
956 }
957
958 static void __cp_get_stats(struct cp_private *cp)
959 {
960 /* only lower 24 bits valid; write any value to clear */
961 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
962 cpw32 (RxMissed, 0);
963 }
964
965 static struct net_device_stats *cp_get_stats(struct net_device *dev)
966 {
967 struct cp_private *cp = netdev_priv(dev);
968 unsigned long flags;
969
970 /* The chip only need report frame silently dropped. */
971 spin_lock_irqsave(&cp->lock, flags);
972 if (netif_running(dev) && netif_device_present(dev))
973 __cp_get_stats(cp);
974 spin_unlock_irqrestore(&cp->lock, flags);
975
976 return &dev->stats;
977 }
978
979 static void cp_stop_hw (struct cp_private *cp)
980 {
981 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
982 cpw16_f(IntrMask, 0);
983 cpw8(Cmd, 0);
984 cpw16_f(CpCmd, 0);
985 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
986
987 cp->rx_tail = 0;
988 cp->tx_head = cp->tx_tail = 0;
989
990 netdev_reset_queue(cp->dev);
991 }
992
993 static void cp_reset_hw (struct cp_private *cp)
994 {
995 unsigned work = 1000;
996
997 cpw8(Cmd, CmdReset);
998
999 while (work--) {
1000 if (!(cpr8(Cmd) & CmdReset))
1001 return;
1002
1003 schedule_timeout_uninterruptible(10);
1004 }
1005
1006 netdev_err(cp->dev, "hardware reset timeout\n");
1007 }
1008
1009 static inline void cp_start_hw (struct cp_private *cp)
1010 {
1011 dma_addr_t ring_dma;
1012
1013 cpw16(CpCmd, cp->cpcmd);
1014
1015 /*
1016 * These (at least TxRingAddr) need to be configured after the
1017 * corresponding bits in CpCmd are enabled. Datasheet v1.6 §6.33
1018 * (C+ Command Register) recommends that these and more be configured
1019 * *after* the [RT]xEnable bits in CpCmd are set. And on some hardware
1020 * it's been observed that the TxRingAddr is actually reset to garbage
1021 * when C+ mode Tx is enabled in CpCmd.
1022 */
1023 cpw32_f(HiTxRingAddr, 0);
1024 cpw32_f(HiTxRingAddr + 4, 0);
1025
1026 ring_dma = cp->ring_dma;
1027 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1028 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1029
1030 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1031 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1032 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1033
1034 /*
1035 * Strictly speaking, the datasheet says this should be enabled
1036 * *before* setting the descriptor addresses. But what, then, would
1037 * prevent it from doing DMA to random unconfigured addresses?
1038 * This variant appears to work fine.
1039 */
1040 cpw8(Cmd, RxOn | TxOn);
1041
1042 netdev_reset_queue(cp->dev);
1043 }
1044
1045 static void cp_enable_irq(struct cp_private *cp)
1046 {
1047 cpw16_f(IntrMask, cp_intr_mask);
1048 }
1049
1050 static void cp_init_hw (struct cp_private *cp)
1051 {
1052 struct net_device *dev = cp->dev;
1053
1054 cp_reset_hw(cp);
1055
1056 cpw8_f (Cfg9346, Cfg9346_Unlock);
1057
1058 /* Restore our idea of the MAC address. */
1059 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1060 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1061
1062 cp_start_hw(cp);
1063 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1064
1065 __cp_set_rx_mode(dev);
1066 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1067
1068 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1069 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1070 cpw8(Config3, PARMEnable);
1071 cp->wol_enabled = 0;
1072
1073 cpw8(Config5, cpr8(Config5) & PMEStatus);
1074
1075 cpw16(MultiIntr, 0);
1076
1077 cpw8_f(Cfg9346, Cfg9346_Lock);
1078 }
1079
1080 static int cp_refill_rx(struct cp_private *cp)
1081 {
1082 struct net_device *dev = cp->dev;
1083 unsigned i;
1084
1085 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1086 struct sk_buff *skb;
1087 dma_addr_t mapping;
1088
1089 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1090 if (!skb)
1091 goto err_out;
1092
1093 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1094 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1095 if (dma_mapping_error(&cp->pdev->dev, mapping)) {
1096 kfree_skb(skb);
1097 goto err_out;
1098 }
1099 cp->rx_skb[i] = skb;
1100
1101 cp->rx_ring[i].opts2 = 0;
1102 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1103 if (i == (CP_RX_RING_SIZE - 1))
1104 cp->rx_ring[i].opts1 =
1105 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1106 else
1107 cp->rx_ring[i].opts1 =
1108 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1109 }
1110
1111 return 0;
1112
1113 err_out:
1114 cp_clean_rings(cp);
1115 return -ENOMEM;
1116 }
1117
1118 static void cp_init_rings_index (struct cp_private *cp)
1119 {
1120 cp->rx_tail = 0;
1121 cp->tx_head = cp->tx_tail = 0;
1122 }
1123
1124 static int cp_init_rings (struct cp_private *cp)
1125 {
1126 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1127 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1128
1129 cp_init_rings_index(cp);
1130
1131 return cp_refill_rx (cp);
1132 }
1133
1134 static int cp_alloc_rings (struct cp_private *cp)
1135 {
1136 struct device *d = &cp->pdev->dev;
1137 void *mem;
1138 int rc;
1139
1140 mem = dma_alloc_coherent(d, CP_RING_BYTES, &cp->ring_dma, GFP_KERNEL);
1141 if (!mem)
1142 return -ENOMEM;
1143
1144 cp->rx_ring = mem;
1145 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1146
1147 rc = cp_init_rings(cp);
1148 if (rc < 0)
1149 dma_free_coherent(d, CP_RING_BYTES, cp->rx_ring, cp->ring_dma);
1150
1151 return rc;
1152 }
1153
1154 static void cp_clean_rings (struct cp_private *cp)
1155 {
1156 struct cp_desc *desc;
1157 unsigned i;
1158
1159 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1160 if (cp->rx_skb[i]) {
1161 desc = cp->rx_ring + i;
1162 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1163 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1164 dev_kfree_skb(cp->rx_skb[i]);
1165 }
1166 }
1167
1168 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1169 if (cp->tx_skb[i]) {
1170 struct sk_buff *skb = cp->tx_skb[i];
1171
1172 desc = cp->tx_ring + i;
1173 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1174 le32_to_cpu(desc->opts1) & 0xffff,
1175 PCI_DMA_TODEVICE);
1176 if (le32_to_cpu(desc->opts1) & LastFrag)
1177 dev_kfree_skb(skb);
1178 cp->dev->stats.tx_dropped++;
1179 }
1180 }
1181 netdev_reset_queue(cp->dev);
1182
1183 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1184 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1185
1186 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1187 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1188 }
1189
1190 static void cp_free_rings (struct cp_private *cp)
1191 {
1192 cp_clean_rings(cp);
1193 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1194 cp->ring_dma);
1195 cp->rx_ring = NULL;
1196 cp->tx_ring = NULL;
1197 }
1198
1199 static int cp_open (struct net_device *dev)
1200 {
1201 struct cp_private *cp = netdev_priv(dev);
1202 const int irq = cp->pdev->irq;
1203 int rc;
1204
1205 netif_dbg(cp, ifup, dev, "enabling interface\n");
1206
1207 rc = cp_alloc_rings(cp);
1208 if (rc)
1209 return rc;
1210
1211 napi_enable(&cp->napi);
1212
1213 cp_init_hw(cp);
1214
1215 rc = request_irq(irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1216 if (rc)
1217 goto err_out_hw;
1218
1219 cp_enable_irq(cp);
1220
1221 netif_carrier_off(dev);
1222 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1223 netif_start_queue(dev);
1224
1225 return 0;
1226
1227 err_out_hw:
1228 napi_disable(&cp->napi);
1229 cp_stop_hw(cp);
1230 cp_free_rings(cp);
1231 return rc;
1232 }
1233
1234 static int cp_close (struct net_device *dev)
1235 {
1236 struct cp_private *cp = netdev_priv(dev);
1237 unsigned long flags;
1238
1239 napi_disable(&cp->napi);
1240
1241 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1242
1243 spin_lock_irqsave(&cp->lock, flags);
1244
1245 netif_stop_queue(dev);
1246 netif_carrier_off(dev);
1247
1248 cp_stop_hw(cp);
1249
1250 spin_unlock_irqrestore(&cp->lock, flags);
1251
1252 free_irq(cp->pdev->irq, dev);
1253
1254 cp_free_rings(cp);
1255 return 0;
1256 }
1257
1258 static void cp_tx_timeout(struct net_device *dev)
1259 {
1260 struct cp_private *cp = netdev_priv(dev);
1261 unsigned long flags;
1262 int rc;
1263
1264 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1265 cpr8(Cmd), cpr16(CpCmd),
1266 cpr16(IntrStatus), cpr16(IntrMask));
1267
1268 spin_lock_irqsave(&cp->lock, flags);
1269
1270 cp_stop_hw(cp);
1271 cp_clean_rings(cp);
1272 rc = cp_init_rings(cp);
1273 cp_start_hw(cp);
1274 cp_enable_irq(cp);
1275
1276 netif_wake_queue(dev);
1277
1278 spin_unlock_irqrestore(&cp->lock, flags);
1279 }
1280
1281 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1282 {
1283 struct cp_private *cp = netdev_priv(dev);
1284
1285 /* check for invalid MTU, according to hardware limits */
1286 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1287 return -EINVAL;
1288
1289 /* if network interface not up, no need for complexity */
1290 if (!netif_running(dev)) {
1291 dev->mtu = new_mtu;
1292 cp_set_rxbufsize(cp); /* set new rx buf size */
1293 return 0;
1294 }
1295
1296 /* network IS up, close it, reset MTU, and come up again. */
1297 cp_close(dev);
1298 dev->mtu = new_mtu;
1299 cp_set_rxbufsize(cp);
1300 return cp_open(dev);
1301 }
1302
1303 static const char mii_2_8139_map[8] = {
1304 BasicModeCtrl,
1305 BasicModeStatus,
1306 0,
1307 0,
1308 NWayAdvert,
1309 NWayLPAR,
1310 NWayExpansion,
1311 0
1312 };
1313
1314 static int mdio_read(struct net_device *dev, int phy_id, int location)
1315 {
1316 struct cp_private *cp = netdev_priv(dev);
1317
1318 return location < 8 && mii_2_8139_map[location] ?
1319 readw(cp->regs + mii_2_8139_map[location]) : 0;
1320 }
1321
1322
1323 static void mdio_write(struct net_device *dev, int phy_id, int location,
1324 int value)
1325 {
1326 struct cp_private *cp = netdev_priv(dev);
1327
1328 if (location == 0) {
1329 cpw8(Cfg9346, Cfg9346_Unlock);
1330 cpw16(BasicModeCtrl, value);
1331 cpw8(Cfg9346, Cfg9346_Lock);
1332 } else if (location < 8 && mii_2_8139_map[location])
1333 cpw16(mii_2_8139_map[location], value);
1334 }
1335
1336 /* Set the ethtool Wake-on-LAN settings */
1337 static int netdev_set_wol (struct cp_private *cp,
1338 const struct ethtool_wolinfo *wol)
1339 {
1340 u8 options;
1341
1342 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1343 /* If WOL is being disabled, no need for complexity */
1344 if (wol->wolopts) {
1345 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1346 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1347 }
1348
1349 cpw8 (Cfg9346, Cfg9346_Unlock);
1350 cpw8 (Config3, options);
1351 cpw8 (Cfg9346, Cfg9346_Lock);
1352
1353 options = 0; /* Paranoia setting */
1354 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1355 /* If WOL is being disabled, no need for complexity */
1356 if (wol->wolopts) {
1357 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1358 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1359 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1360 }
1361
1362 cpw8 (Config5, options);
1363
1364 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1365
1366 return 0;
1367 }
1368
1369 /* Get the ethtool Wake-on-LAN settings */
1370 static void netdev_get_wol (struct cp_private *cp,
1371 struct ethtool_wolinfo *wol)
1372 {
1373 u8 options;
1374
1375 wol->wolopts = 0; /* Start from scratch */
1376 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1377 WAKE_MCAST | WAKE_UCAST;
1378 /* We don't need to go on if WOL is disabled */
1379 if (!cp->wol_enabled) return;
1380
1381 options = cpr8 (Config3);
1382 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1383 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1384
1385 options = 0; /* Paranoia setting */
1386 options = cpr8 (Config5);
1387 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1388 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1389 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1390 }
1391
1392 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1393 {
1394 struct cp_private *cp = netdev_priv(dev);
1395
1396 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1397 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1398 strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info));
1399 }
1400
1401 static void cp_get_ringparam(struct net_device *dev,
1402 struct ethtool_ringparam *ring)
1403 {
1404 ring->rx_max_pending = CP_RX_RING_SIZE;
1405 ring->tx_max_pending = CP_TX_RING_SIZE;
1406 ring->rx_pending = CP_RX_RING_SIZE;
1407 ring->tx_pending = CP_TX_RING_SIZE;
1408 }
1409
1410 static int cp_get_regs_len(struct net_device *dev)
1411 {
1412 return CP_REGS_SIZE;
1413 }
1414
1415 static int cp_get_sset_count (struct net_device *dev, int sset)
1416 {
1417 switch (sset) {
1418 case ETH_SS_STATS:
1419 return CP_NUM_STATS;
1420 default:
1421 return -EOPNOTSUPP;
1422 }
1423 }
1424
1425 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1426 {
1427 struct cp_private *cp = netdev_priv(dev);
1428 int rc;
1429 unsigned long flags;
1430
1431 spin_lock_irqsave(&cp->lock, flags);
1432 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1433 spin_unlock_irqrestore(&cp->lock, flags);
1434
1435 return rc;
1436 }
1437
1438 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1439 {
1440 struct cp_private *cp = netdev_priv(dev);
1441 int rc;
1442 unsigned long flags;
1443
1444 spin_lock_irqsave(&cp->lock, flags);
1445 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1446 spin_unlock_irqrestore(&cp->lock, flags);
1447
1448 return rc;
1449 }
1450
1451 static int cp_nway_reset(struct net_device *dev)
1452 {
1453 struct cp_private *cp = netdev_priv(dev);
1454 return mii_nway_restart(&cp->mii_if);
1455 }
1456
1457 static u32 cp_get_msglevel(struct net_device *dev)
1458 {
1459 struct cp_private *cp = netdev_priv(dev);
1460 return cp->msg_enable;
1461 }
1462
1463 static void cp_set_msglevel(struct net_device *dev, u32 value)
1464 {
1465 struct cp_private *cp = netdev_priv(dev);
1466 cp->msg_enable = value;
1467 }
1468
1469 static int cp_set_features(struct net_device *dev, netdev_features_t features)
1470 {
1471 struct cp_private *cp = netdev_priv(dev);
1472 unsigned long flags;
1473
1474 if (!((dev->features ^ features) & NETIF_F_RXCSUM))
1475 return 0;
1476
1477 spin_lock_irqsave(&cp->lock, flags);
1478
1479 if (features & NETIF_F_RXCSUM)
1480 cp->cpcmd |= RxChkSum;
1481 else
1482 cp->cpcmd &= ~RxChkSum;
1483
1484 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1485 cp->cpcmd |= RxVlanOn;
1486 else
1487 cp->cpcmd &= ~RxVlanOn;
1488
1489 cpw16_f(CpCmd, cp->cpcmd);
1490 spin_unlock_irqrestore(&cp->lock, flags);
1491
1492 return 0;
1493 }
1494
1495 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1496 void *p)
1497 {
1498 struct cp_private *cp = netdev_priv(dev);
1499 unsigned long flags;
1500
1501 if (regs->len < CP_REGS_SIZE)
1502 return /* -EINVAL */;
1503
1504 regs->version = CP_REGS_VER;
1505
1506 spin_lock_irqsave(&cp->lock, flags);
1507 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1508 spin_unlock_irqrestore(&cp->lock, flags);
1509 }
1510
1511 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1512 {
1513 struct cp_private *cp = netdev_priv(dev);
1514 unsigned long flags;
1515
1516 spin_lock_irqsave (&cp->lock, flags);
1517 netdev_get_wol (cp, wol);
1518 spin_unlock_irqrestore (&cp->lock, flags);
1519 }
1520
1521 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1522 {
1523 struct cp_private *cp = netdev_priv(dev);
1524 unsigned long flags;
1525 int rc;
1526
1527 spin_lock_irqsave (&cp->lock, flags);
1528 rc = netdev_set_wol (cp, wol);
1529 spin_unlock_irqrestore (&cp->lock, flags);
1530
1531 return rc;
1532 }
1533
1534 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1535 {
1536 switch (stringset) {
1537 case ETH_SS_STATS:
1538 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1539 break;
1540 default:
1541 BUG();
1542 break;
1543 }
1544 }
1545
1546 static void cp_get_ethtool_stats (struct net_device *dev,
1547 struct ethtool_stats *estats, u64 *tmp_stats)
1548 {
1549 struct cp_private *cp = netdev_priv(dev);
1550 struct cp_dma_stats *nic_stats;
1551 dma_addr_t dma;
1552 int i;
1553
1554 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1555 &dma, GFP_KERNEL);
1556 if (!nic_stats)
1557 return;
1558
1559 /* begin NIC statistics dump */
1560 cpw32(StatsAddr + 4, (u64)dma >> 32);
1561 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1562 cpr32(StatsAddr);
1563
1564 for (i = 0; i < 1000; i++) {
1565 if ((cpr32(StatsAddr) & DumpStats) == 0)
1566 break;
1567 udelay(10);
1568 }
1569 cpw32(StatsAddr, 0);
1570 cpw32(StatsAddr + 4, 0);
1571 cpr32(StatsAddr);
1572
1573 i = 0;
1574 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1575 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1576 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1577 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1578 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1579 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1580 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1581 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1582 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1583 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1584 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1585 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1586 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1587 tmp_stats[i++] = cp->cp_stats.rx_frags;
1588 BUG_ON(i != CP_NUM_STATS);
1589
1590 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1591 }
1592
1593 static const struct ethtool_ops cp_ethtool_ops = {
1594 .get_drvinfo = cp_get_drvinfo,
1595 .get_regs_len = cp_get_regs_len,
1596 .get_sset_count = cp_get_sset_count,
1597 .get_settings = cp_get_settings,
1598 .set_settings = cp_set_settings,
1599 .nway_reset = cp_nway_reset,
1600 .get_link = ethtool_op_get_link,
1601 .get_msglevel = cp_get_msglevel,
1602 .set_msglevel = cp_set_msglevel,
1603 .get_regs = cp_get_regs,
1604 .get_wol = cp_get_wol,
1605 .set_wol = cp_set_wol,
1606 .get_strings = cp_get_strings,
1607 .get_ethtool_stats = cp_get_ethtool_stats,
1608 .get_eeprom_len = cp_get_eeprom_len,
1609 .get_eeprom = cp_get_eeprom,
1610 .set_eeprom = cp_set_eeprom,
1611 .get_ringparam = cp_get_ringparam,
1612 };
1613
1614 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1615 {
1616 struct cp_private *cp = netdev_priv(dev);
1617 int rc;
1618 unsigned long flags;
1619
1620 if (!netif_running(dev))
1621 return -EINVAL;
1622
1623 spin_lock_irqsave(&cp->lock, flags);
1624 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1625 spin_unlock_irqrestore(&cp->lock, flags);
1626 return rc;
1627 }
1628
1629 static int cp_set_mac_address(struct net_device *dev, void *p)
1630 {
1631 struct cp_private *cp = netdev_priv(dev);
1632 struct sockaddr *addr = p;
1633
1634 if (!is_valid_ether_addr(addr->sa_data))
1635 return -EADDRNOTAVAIL;
1636
1637 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1638
1639 spin_lock_irq(&cp->lock);
1640
1641 cpw8_f(Cfg9346, Cfg9346_Unlock);
1642 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1643 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1644 cpw8_f(Cfg9346, Cfg9346_Lock);
1645
1646 spin_unlock_irq(&cp->lock);
1647
1648 return 0;
1649 }
1650
1651 /* Serial EEPROM section. */
1652
1653 /* EEPROM_Ctrl bits. */
1654 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1655 #define EE_CS 0x08 /* EEPROM chip select. */
1656 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1657 #define EE_WRITE_0 0x00
1658 #define EE_WRITE_1 0x02
1659 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1660 #define EE_ENB (0x80 | EE_CS)
1661
1662 /* Delay between EEPROM clock transitions.
1663 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1664 */
1665
1666 #define eeprom_delay() readb(ee_addr)
1667
1668 /* The EEPROM commands include the alway-set leading bit. */
1669 #define EE_EXTEND_CMD (4)
1670 #define EE_WRITE_CMD (5)
1671 #define EE_READ_CMD (6)
1672 #define EE_ERASE_CMD (7)
1673
1674 #define EE_EWDS_ADDR (0)
1675 #define EE_WRAL_ADDR (1)
1676 #define EE_ERAL_ADDR (2)
1677 #define EE_EWEN_ADDR (3)
1678
1679 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1680
1681 static void eeprom_cmd_start(void __iomem *ee_addr)
1682 {
1683 writeb (EE_ENB & ~EE_CS, ee_addr);
1684 writeb (EE_ENB, ee_addr);
1685 eeprom_delay ();
1686 }
1687
1688 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1689 {
1690 int i;
1691
1692 /* Shift the command bits out. */
1693 for (i = cmd_len - 1; i >= 0; i--) {
1694 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1695 writeb (EE_ENB | dataval, ee_addr);
1696 eeprom_delay ();
1697 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1698 eeprom_delay ();
1699 }
1700 writeb (EE_ENB, ee_addr);
1701 eeprom_delay ();
1702 }
1703
1704 static void eeprom_cmd_end(void __iomem *ee_addr)
1705 {
1706 writeb(0, ee_addr);
1707 eeprom_delay ();
1708 }
1709
1710 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1711 int addr_len)
1712 {
1713 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1714
1715 eeprom_cmd_start(ee_addr);
1716 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1717 eeprom_cmd_end(ee_addr);
1718 }
1719
1720 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1721 {
1722 int i;
1723 u16 retval = 0;
1724 void __iomem *ee_addr = ioaddr + Cfg9346;
1725 int read_cmd = location | (EE_READ_CMD << addr_len);
1726
1727 eeprom_cmd_start(ee_addr);
1728 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1729
1730 for (i = 16; i > 0; i--) {
1731 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1732 eeprom_delay ();
1733 retval =
1734 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1735 0);
1736 writeb (EE_ENB, ee_addr);
1737 eeprom_delay ();
1738 }
1739
1740 eeprom_cmd_end(ee_addr);
1741
1742 return retval;
1743 }
1744
1745 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1746 int addr_len)
1747 {
1748 int i;
1749 void __iomem *ee_addr = ioaddr + Cfg9346;
1750 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1751
1752 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1753
1754 eeprom_cmd_start(ee_addr);
1755 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1756 eeprom_cmd(ee_addr, val, 16);
1757 eeprom_cmd_end(ee_addr);
1758
1759 eeprom_cmd_start(ee_addr);
1760 for (i = 0; i < 20000; i++)
1761 if (readb(ee_addr) & EE_DATA_READ)
1762 break;
1763 eeprom_cmd_end(ee_addr);
1764
1765 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1766 }
1767
1768 static int cp_get_eeprom_len(struct net_device *dev)
1769 {
1770 struct cp_private *cp = netdev_priv(dev);
1771 int size;
1772
1773 spin_lock_irq(&cp->lock);
1774 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1775 spin_unlock_irq(&cp->lock);
1776
1777 return size;
1778 }
1779
1780 static int cp_get_eeprom(struct net_device *dev,
1781 struct ethtool_eeprom *eeprom, u8 *data)
1782 {
1783 struct cp_private *cp = netdev_priv(dev);
1784 unsigned int addr_len;
1785 u16 val;
1786 u32 offset = eeprom->offset >> 1;
1787 u32 len = eeprom->len;
1788 u32 i = 0;
1789
1790 eeprom->magic = CP_EEPROM_MAGIC;
1791
1792 spin_lock_irq(&cp->lock);
1793
1794 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1795
1796 if (eeprom->offset & 1) {
1797 val = read_eeprom(cp->regs, offset, addr_len);
1798 data[i++] = (u8)(val >> 8);
1799 offset++;
1800 }
1801
1802 while (i < len - 1) {
1803 val = read_eeprom(cp->regs, offset, addr_len);
1804 data[i++] = (u8)val;
1805 data[i++] = (u8)(val >> 8);
1806 offset++;
1807 }
1808
1809 if (i < len) {
1810 val = read_eeprom(cp->regs, offset, addr_len);
1811 data[i] = (u8)val;
1812 }
1813
1814 spin_unlock_irq(&cp->lock);
1815 return 0;
1816 }
1817
1818 static int cp_set_eeprom(struct net_device *dev,
1819 struct ethtool_eeprom *eeprom, u8 *data)
1820 {
1821 struct cp_private *cp = netdev_priv(dev);
1822 unsigned int addr_len;
1823 u16 val;
1824 u32 offset = eeprom->offset >> 1;
1825 u32 len = eeprom->len;
1826 u32 i = 0;
1827
1828 if (eeprom->magic != CP_EEPROM_MAGIC)
1829 return -EINVAL;
1830
1831 spin_lock_irq(&cp->lock);
1832
1833 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1834
1835 if (eeprom->offset & 1) {
1836 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1837 val |= (u16)data[i++] << 8;
1838 write_eeprom(cp->regs, offset, val, addr_len);
1839 offset++;
1840 }
1841
1842 while (i < len - 1) {
1843 val = (u16)data[i++];
1844 val |= (u16)data[i++] << 8;
1845 write_eeprom(cp->regs, offset, val, addr_len);
1846 offset++;
1847 }
1848
1849 if (i < len) {
1850 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1851 val |= (u16)data[i];
1852 write_eeprom(cp->regs, offset, val, addr_len);
1853 }
1854
1855 spin_unlock_irq(&cp->lock);
1856 return 0;
1857 }
1858
1859 /* Put the board into D3cold state and wait for WakeUp signal */
1860 static void cp_set_d3_state (struct cp_private *cp)
1861 {
1862 pci_enable_wake(cp->pdev, PCI_D0, 1); /* Enable PME# generation */
1863 pci_set_power_state (cp->pdev, PCI_D3hot);
1864 }
1865
1866 static const struct net_device_ops cp_netdev_ops = {
1867 .ndo_open = cp_open,
1868 .ndo_stop = cp_close,
1869 .ndo_validate_addr = eth_validate_addr,
1870 .ndo_set_mac_address = cp_set_mac_address,
1871 .ndo_set_rx_mode = cp_set_rx_mode,
1872 .ndo_get_stats = cp_get_stats,
1873 .ndo_do_ioctl = cp_ioctl,
1874 .ndo_start_xmit = cp_start_xmit,
1875 .ndo_tx_timeout = cp_tx_timeout,
1876 .ndo_set_features = cp_set_features,
1877 .ndo_change_mtu = cp_change_mtu,
1878
1879 #ifdef CONFIG_NET_POLL_CONTROLLER
1880 .ndo_poll_controller = cp_poll_controller,
1881 #endif
1882 };
1883
1884 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1885 {
1886 struct net_device *dev;
1887 struct cp_private *cp;
1888 int rc;
1889 void __iomem *regs;
1890 resource_size_t pciaddr;
1891 unsigned int addr_len, i, pci_using_dac;
1892
1893 #ifndef MODULE
1894 static int version_printed;
1895 if (version_printed++ == 0)
1896 pr_info("%s", version);
1897 #endif
1898
1899 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1900 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1901 dev_info(&pdev->dev,
1902 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1903 pdev->vendor, pdev->device, pdev->revision);
1904 return -ENODEV;
1905 }
1906
1907 dev = alloc_etherdev(sizeof(struct cp_private));
1908 if (!dev)
1909 return -ENOMEM;
1910 SET_NETDEV_DEV(dev, &pdev->dev);
1911
1912 cp = netdev_priv(dev);
1913 cp->pdev = pdev;
1914 cp->dev = dev;
1915 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1916 spin_lock_init (&cp->lock);
1917 cp->mii_if.dev = dev;
1918 cp->mii_if.mdio_read = mdio_read;
1919 cp->mii_if.mdio_write = mdio_write;
1920 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1921 cp->mii_if.phy_id_mask = 0x1f;
1922 cp->mii_if.reg_num_mask = 0x1f;
1923 cp_set_rxbufsize(cp);
1924
1925 rc = pci_enable_device(pdev);
1926 if (rc)
1927 goto err_out_free;
1928
1929 rc = pci_set_mwi(pdev);
1930 if (rc)
1931 goto err_out_disable;
1932
1933 rc = pci_request_regions(pdev, DRV_NAME);
1934 if (rc)
1935 goto err_out_mwi;
1936
1937 pciaddr = pci_resource_start(pdev, 1);
1938 if (!pciaddr) {
1939 rc = -EIO;
1940 dev_err(&pdev->dev, "no MMIO resource\n");
1941 goto err_out_res;
1942 }
1943 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1944 rc = -EIO;
1945 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1946 (unsigned long long)pci_resource_len(pdev, 1));
1947 goto err_out_res;
1948 }
1949
1950 /* Configure DMA attributes. */
1951 if ((sizeof(dma_addr_t) > 4) &&
1952 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1953 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1954 pci_using_dac = 1;
1955 } else {
1956 pci_using_dac = 0;
1957
1958 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1959 if (rc) {
1960 dev_err(&pdev->dev,
1961 "No usable DMA configuration, aborting\n");
1962 goto err_out_res;
1963 }
1964 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1965 if (rc) {
1966 dev_err(&pdev->dev,
1967 "No usable consistent DMA configuration, aborting\n");
1968 goto err_out_res;
1969 }
1970 }
1971
1972 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1973 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1974
1975 dev->features |= NETIF_F_RXCSUM;
1976 dev->hw_features |= NETIF_F_RXCSUM;
1977
1978 regs = ioremap(pciaddr, CP_REGS_SIZE);
1979 if (!regs) {
1980 rc = -EIO;
1981 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1982 (unsigned long long)pci_resource_len(pdev, 1),
1983 (unsigned long long)pciaddr);
1984 goto err_out_res;
1985 }
1986 cp->regs = regs;
1987
1988 cp_stop_hw(cp);
1989
1990 /* read MAC address from EEPROM */
1991 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1992 for (i = 0; i < 3; i++)
1993 ((__le16 *) (dev->dev_addr))[i] =
1994 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1995
1996 dev->netdev_ops = &cp_netdev_ops;
1997 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1998 dev->ethtool_ops = &cp_ethtool_ops;
1999 dev->watchdog_timeo = TX_TIMEOUT;
2000
2001 dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
2002
2003 if (pci_using_dac)
2004 dev->features |= NETIF_F_HIGHDMA;
2005
2006 /* disabled by default until verified */
2007 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
2008 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
2009 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
2010 NETIF_F_HIGHDMA;
2011
2012 rc = register_netdev(dev);
2013 if (rc)
2014 goto err_out_iomap;
2015
2016 netdev_info(dev, "RTL-8139C+ at 0x%p, %pM, IRQ %d\n",
2017 regs, dev->dev_addr, pdev->irq);
2018
2019 pci_set_drvdata(pdev, dev);
2020
2021 /* enable busmastering and memory-write-invalidate */
2022 pci_set_master(pdev);
2023
2024 if (cp->wol_enabled)
2025 cp_set_d3_state (cp);
2026
2027 return 0;
2028
2029 err_out_iomap:
2030 iounmap(regs);
2031 err_out_res:
2032 pci_release_regions(pdev);
2033 err_out_mwi:
2034 pci_clear_mwi(pdev);
2035 err_out_disable:
2036 pci_disable_device(pdev);
2037 err_out_free:
2038 free_netdev(dev);
2039 return rc;
2040 }
2041
2042 static void cp_remove_one (struct pci_dev *pdev)
2043 {
2044 struct net_device *dev = pci_get_drvdata(pdev);
2045 struct cp_private *cp = netdev_priv(dev);
2046
2047 unregister_netdev(dev);
2048 iounmap(cp->regs);
2049 if (cp->wol_enabled)
2050 pci_set_power_state (pdev, PCI_D0);
2051 pci_release_regions(pdev);
2052 pci_clear_mwi(pdev);
2053 pci_disable_device(pdev);
2054 pci_set_drvdata(pdev, NULL);
2055 free_netdev(dev);
2056 }
2057
2058 #ifdef CONFIG_PM
2059 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2060 {
2061 struct net_device *dev = pci_get_drvdata(pdev);
2062 struct cp_private *cp = netdev_priv(dev);
2063 unsigned long flags;
2064
2065 if (!netif_running(dev))
2066 return 0;
2067
2068 netif_device_detach (dev);
2069 netif_stop_queue (dev);
2070
2071 spin_lock_irqsave (&cp->lock, flags);
2072
2073 /* Disable Rx and Tx */
2074 cpw16 (IntrMask, 0);
2075 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2076
2077 spin_unlock_irqrestore (&cp->lock, flags);
2078
2079 pci_save_state(pdev);
2080 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2081 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2082
2083 return 0;
2084 }
2085
2086 static int cp_resume (struct pci_dev *pdev)
2087 {
2088 struct net_device *dev = pci_get_drvdata (pdev);
2089 struct cp_private *cp = netdev_priv(dev);
2090 unsigned long flags;
2091
2092 if (!netif_running(dev))
2093 return 0;
2094
2095 netif_device_attach (dev);
2096
2097 pci_set_power_state(pdev, PCI_D0);
2098 pci_restore_state(pdev);
2099 pci_enable_wake(pdev, PCI_D0, 0);
2100
2101 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2102 cp_init_rings_index (cp);
2103 cp_init_hw (cp);
2104 cp_enable_irq(cp);
2105 netif_start_queue (dev);
2106
2107 spin_lock_irqsave (&cp->lock, flags);
2108
2109 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2110
2111 spin_unlock_irqrestore (&cp->lock, flags);
2112
2113 return 0;
2114 }
2115 #endif /* CONFIG_PM */
2116
2117 static struct pci_driver cp_driver = {
2118 .name = DRV_NAME,
2119 .id_table = cp_pci_tbl,
2120 .probe = cp_init_one,
2121 .remove = cp_remove_one,
2122 #ifdef CONFIG_PM
2123 .resume = cp_resume,
2124 .suspend = cp_suspend,
2125 #endif
2126 };
2127
2128 static int __init cp_init (void)
2129 {
2130 #ifdef MODULE
2131 pr_info("%s", version);
2132 #endif
2133 return pci_register_driver(&cp_driver);
2134 }
2135
2136 static void __exit cp_exit (void)
2137 {
2138 pci_unregister_driver (&cp_driver);
2139 }
2140
2141 module_init(cp_init);
2142 module_exit(cp_exit);
Linux kernel - Deliverables
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