2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
35 #define RTL8169_VERSION "2.3LK-NAPI"
36 #define MODULENAME "r8169"
37 #define PFX MODULENAME ": "
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
49 #define assert(expr) \
51 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
52 #expr,__FILE__,__func__,__LINE__); \
54 #define dprintk(fmt, args...) \
55 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
57 #define assert(expr) do {} while (0)
58 #define dprintk(fmt, args...) do {} while (0)
59 #endif /* RTL8169_DEBUG */
61 #define R8169_MSG_DEFAULT \
62 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
64 #define TX_BUFFS_AVAIL(tp) \
65 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
67 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
68 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
69 static const int multicast_filter_limit
= 32;
71 #define MAX_READ_REQUEST_SHIFT 12
72 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
73 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
74 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76 #define R8169_REGS_SIZE 256
77 #define R8169_NAPI_WEIGHT 64
78 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
79 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
80 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
81 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
82 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84 #define RTL8169_TX_TIMEOUT (6*HZ)
85 #define RTL8169_PHY_TIMEOUT (10*HZ)
87 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
88 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
89 #define RTL_EEPROM_SIG_ADDR 0x0000
91 /* write/read MMIO register */
92 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
93 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
94 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
95 #define RTL_R8(reg) readb (ioaddr + (reg))
96 #define RTL_R16(reg) readw (ioaddr + (reg))
97 #define RTL_R32(reg) readl (ioaddr + (reg))
100 RTL_GIGA_MAC_VER_01
= 0,
136 RTL_GIGA_MAC_NONE
= 0xff,
139 enum rtl_tx_desc_version
{
144 #define JUMBO_1K ETH_DATA_LEN
145 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
146 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
147 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
148 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150 #define _R(NAME,TD,FW,SZ,B) { \
158 static const struct {
160 enum rtl_tx_desc_version txd_version
;
164 } rtl_chip_infos
[] = {
166 [RTL_GIGA_MAC_VER_01
] =
167 _R("RTL8169", RTL_TD_0
, NULL
, JUMBO_7K
, true),
168 [RTL_GIGA_MAC_VER_02
] =
169 _R("RTL8169s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
170 [RTL_GIGA_MAC_VER_03
] =
171 _R("RTL8110s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
172 [RTL_GIGA_MAC_VER_04
] =
173 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
, JUMBO_7K
, true),
174 [RTL_GIGA_MAC_VER_05
] =
175 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
176 [RTL_GIGA_MAC_VER_06
] =
177 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
179 [RTL_GIGA_MAC_VER_07
] =
180 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
181 [RTL_GIGA_MAC_VER_08
] =
182 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
183 [RTL_GIGA_MAC_VER_09
] =
184 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
185 [RTL_GIGA_MAC_VER_10
] =
186 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
187 [RTL_GIGA_MAC_VER_11
] =
188 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
189 [RTL_GIGA_MAC_VER_12
] =
190 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
191 [RTL_GIGA_MAC_VER_13
] =
192 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
193 [RTL_GIGA_MAC_VER_14
] =
194 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
195 [RTL_GIGA_MAC_VER_15
] =
196 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
197 [RTL_GIGA_MAC_VER_16
] =
198 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
199 [RTL_GIGA_MAC_VER_17
] =
200 _R("RTL8168b/8111b", RTL_TD_1
, NULL
, JUMBO_4K
, false),
201 [RTL_GIGA_MAC_VER_18
] =
202 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
203 [RTL_GIGA_MAC_VER_19
] =
204 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
205 [RTL_GIGA_MAC_VER_20
] =
206 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
207 [RTL_GIGA_MAC_VER_21
] =
208 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
209 [RTL_GIGA_MAC_VER_22
] =
210 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
211 [RTL_GIGA_MAC_VER_23
] =
212 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
213 [RTL_GIGA_MAC_VER_24
] =
214 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
215 [RTL_GIGA_MAC_VER_25
] =
216 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
,
218 [RTL_GIGA_MAC_VER_26
] =
219 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
,
221 [RTL_GIGA_MAC_VER_27
] =
222 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
223 [RTL_GIGA_MAC_VER_28
] =
224 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
225 [RTL_GIGA_MAC_VER_29
] =
226 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
228 [RTL_GIGA_MAC_VER_30
] =
229 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
231 [RTL_GIGA_MAC_VER_31
] =
232 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
233 [RTL_GIGA_MAC_VER_32
] =
234 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
,
236 [RTL_GIGA_MAC_VER_33
] =
237 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
,
239 [RTL_GIGA_MAC_VER_34
] =
240 _R("RTL8168evl/8111evl",RTL_TD_1
, FIRMWARE_8168E_3
,
242 [RTL_GIGA_MAC_VER_35
] =
243 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_1
,
245 [RTL_GIGA_MAC_VER_36
] =
246 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_2
,
257 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl
) = {
258 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
259 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
260 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
261 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
262 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
263 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
264 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4302), 0, 0, RTL_CFG_0
},
265 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
266 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
267 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
268 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
270 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
274 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
276 static int rx_buf_sz
= 16383;
283 MAC0
= 0, /* Ethernet hardware address. */
285 MAR0
= 8, /* Multicast filter. */
286 CounterAddrLow
= 0x10,
287 CounterAddrHigh
= 0x14,
288 TxDescStartAddrLow
= 0x20,
289 TxDescStartAddrHigh
= 0x24,
290 TxHDescStartAddrLow
= 0x28,
291 TxHDescStartAddrHigh
= 0x2c,
300 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
301 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
304 #define RX128_INT_EN (1 << 15) /* 8111c and later */
305 #define RX_MULTI_EN (1 << 14) /* 8111c only */
306 #define RXCFG_FIFO_SHIFT 13
307 /* No threshold before first PCI xfer */
308 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
309 #define RXCFG_DMA_SHIFT 8
310 /* Unlimited maximum PCI burst. */
311 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
318 #define PME_SIGNAL (1 << 5) /* 8168c and later */
329 RxDescAddrLow
= 0xe4,
330 RxDescAddrHigh
= 0xe8,
331 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
333 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
335 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
337 #define TxPacketMax (8064 >> 7)
338 #define EarlySize 0x27
341 FuncEventMask
= 0xf4,
342 FuncPresetState
= 0xf8,
343 FuncForceEvent
= 0xfc,
346 enum rtl8110_registers
{
352 enum rtl8168_8101_registers
{
355 #define CSIAR_FLAG 0x80000000
356 #define CSIAR_WRITE_CMD 0x80000000
357 #define CSIAR_BYTE_ENABLE 0x0f
358 #define CSIAR_BYTE_ENABLE_SHIFT 12
359 #define CSIAR_ADDR_MASK 0x0fff
362 #define EPHYAR_FLAG 0x80000000
363 #define EPHYAR_WRITE_CMD 0x80000000
364 #define EPHYAR_REG_MASK 0x1f
365 #define EPHYAR_REG_SHIFT 16
366 #define EPHYAR_DATA_MASK 0xffff
368 #define PFM_EN (1 << 6)
370 #define FIX_NAK_1 (1 << 4)
371 #define FIX_NAK_2 (1 << 3)
374 #define NOW_IS_OOB (1 << 7)
375 #define EN_NDP (1 << 3)
376 #define EN_OOB_RESET (1 << 2)
378 #define EFUSEAR_FLAG 0x80000000
379 #define EFUSEAR_WRITE_CMD 0x80000000
380 #define EFUSEAR_READ_CMD 0x00000000
381 #define EFUSEAR_REG_MASK 0x03ff
382 #define EFUSEAR_REG_SHIFT 8
383 #define EFUSEAR_DATA_MASK 0xff
386 enum rtl8168_registers
{
391 #define ERIAR_FLAG 0x80000000
392 #define ERIAR_WRITE_CMD 0x80000000
393 #define ERIAR_READ_CMD 0x00000000
394 #define ERIAR_ADDR_BYTE_ALIGN 4
395 #define ERIAR_TYPE_SHIFT 16
396 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
397 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
398 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
399 #define ERIAR_MASK_SHIFT 12
400 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
401 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
402 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
403 EPHY_RXER_NUM
= 0x7c,
404 OCPDR
= 0xb0, /* OCP GPHY access */
405 #define OCPDR_WRITE_CMD 0x80000000
406 #define OCPDR_READ_CMD 0x00000000
407 #define OCPDR_REG_MASK 0x7f
408 #define OCPDR_GPHY_REG_SHIFT 16
409 #define OCPDR_DATA_MASK 0xffff
411 #define OCPAR_FLAG 0x80000000
412 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
413 #define OCPAR_GPHY_READ_CMD 0x0000f060
414 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
415 MISC
= 0xf0, /* 8168e only. */
416 #define TXPLA_RST (1 << 29)
417 #define PWM_EN (1 << 22)
420 enum rtl_register_content
{
421 /* InterruptStatusBits */
425 TxDescUnavail
= 0x0080,
449 /* TXPoll register p.5 */
450 HPQ
= 0x80, /* Poll cmd on the high prio queue */
451 NPQ
= 0x40, /* Poll cmd on the low prio queue */
452 FSWInt
= 0x01, /* Forced software interrupt */
456 Cfg9346_Unlock
= 0xc0,
461 AcceptBroadcast
= 0x08,
462 AcceptMulticast
= 0x04,
464 AcceptAllPhys
= 0x01,
465 #define RX_CONFIG_ACCEPT_MASK 0x3f
468 TxInterFrameGapShift
= 24,
469 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
471 /* Config1 register p.24 */
474 Speed_down
= (1 << 4),
478 PMEnable
= (1 << 0), /* Power Management Enable */
480 /* Config2 register p. 25 */
481 MSIEnable
= (1 << 5), /* 8169 only. Reserved in the 8168. */
482 PCI_Clock_66MHz
= 0x01,
483 PCI_Clock_33MHz
= 0x00,
485 /* Config3 register p.25 */
486 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
487 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
488 Jumbo_En0
= (1 << 2), /* 8168 only. Reserved in the 8168b */
489 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
491 /* Config4 register */
492 Jumbo_En1
= (1 << 1), /* 8168 only. Reserved in the 8168b */
494 /* Config5 register p.27 */
495 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
496 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
497 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
499 LanWake
= (1 << 1), /* LanWake enable/disable */
500 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
503 TBIReset
= 0x80000000,
504 TBILoopback
= 0x40000000,
505 TBINwEnable
= 0x20000000,
506 TBINwRestart
= 0x10000000,
507 TBILinkOk
= 0x02000000,
508 TBINwComplete
= 0x01000000,
511 EnableBist
= (1 << 15), // 8168 8101
512 Mac_dbgo_oe
= (1 << 14), // 8168 8101
513 Normal_mode
= (1 << 13), // unused
514 Force_half_dup
= (1 << 12), // 8168 8101
515 Force_rxflow_en
= (1 << 11), // 8168 8101
516 Force_txflow_en
= (1 << 10), // 8168 8101
517 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
518 ASF
= (1 << 8), // 8168 8101
519 PktCntrDisable
= (1 << 7), // 8168 8101
520 Mac_dbgo_sel
= 0x001c, // 8168
525 INTT_0
= 0x0000, // 8168
526 INTT_1
= 0x0001, // 8168
527 INTT_2
= 0x0002, // 8168
528 INTT_3
= 0x0003, // 8168
530 /* rtl8169_PHYstatus */
541 TBILinkOK
= 0x02000000,
543 /* DumpCounterCommand */
548 /* First doubleword. */
549 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
550 RingEnd
= (1 << 30), /* End of descriptor ring */
551 FirstFrag
= (1 << 29), /* First segment of a packet */
552 LastFrag
= (1 << 28), /* Final segment of a packet */
556 enum rtl_tx_desc_bit
{
557 /* First doubleword. */
558 TD_LSO
= (1 << 27), /* Large Send Offload */
559 #define TD_MSS_MAX 0x07ffu /* MSS value */
561 /* Second doubleword. */
562 TxVlanTag
= (1 << 17), /* Add VLAN tag */
565 /* 8169, 8168b and 810x except 8102e. */
566 enum rtl_tx_desc_bit_0
{
567 /* First doubleword. */
568 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
569 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
570 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
571 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
574 /* 8102e, 8168c and beyond. */
575 enum rtl_tx_desc_bit_1
{
576 /* Second doubleword. */
577 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
578 TD1_IP_CS
= (1 << 29), /* Calculate IP checksum */
579 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
580 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
583 static const struct rtl_tx_desc_info
{
590 } tx_desc_info
[] = {
593 .udp
= TD0_IP_CS
| TD0_UDP_CS
,
594 .tcp
= TD0_IP_CS
| TD0_TCP_CS
596 .mss_shift
= TD0_MSS_SHIFT
,
601 .udp
= TD1_IP_CS
| TD1_UDP_CS
,
602 .tcp
= TD1_IP_CS
| TD1_TCP_CS
604 .mss_shift
= TD1_MSS_SHIFT
,
609 enum rtl_rx_desc_bit
{
611 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
612 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
614 #define RxProtoUDP (PID1)
615 #define RxProtoTCP (PID0)
616 #define RxProtoIP (PID1 | PID0)
617 #define RxProtoMask RxProtoIP
619 IPFail
= (1 << 16), /* IP checksum failed */
620 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
621 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
622 RxVlanTag
= (1 << 16), /* VLAN tag available */
625 #define RsvdMask 0x3fffc000
642 u8 __pad
[sizeof(void *) - sizeof(u32
)];
646 RTL_FEATURE_WOL
= (1 << 0),
647 RTL_FEATURE_MSI
= (1 << 1),
648 RTL_FEATURE_GMII
= (1 << 2),
651 struct rtl8169_counters
{
658 __le32 tx_one_collision
;
659 __le32 tx_multi_collision
;
668 RTL_FLAG_TASK_ENABLED
,
669 RTL_FLAG_TASK_SLOW_PENDING
,
670 RTL_FLAG_TASK_RESET_PENDING
,
671 RTL_FLAG_TASK_PHY_PENDING
,
675 struct rtl8169_stats
{
678 struct u64_stats_sync syncp
;
681 struct rtl8169_private
{
682 void __iomem
*mmio_addr
; /* memory map physical address */
683 struct pci_dev
*pci_dev
;
684 struct net_device
*dev
;
685 struct napi_struct napi
;
689 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
690 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
693 struct rtl8169_stats rx_stats
;
694 struct rtl8169_stats tx_stats
;
695 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
696 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
697 dma_addr_t TxPhyAddr
;
698 dma_addr_t RxPhyAddr
;
699 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
700 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
701 struct timer_list timer
;
707 void (*write
)(void __iomem
*, int, int);
708 int (*read
)(void __iomem
*, int);
711 struct pll_power_ops
{
712 void (*down
)(struct rtl8169_private
*);
713 void (*up
)(struct rtl8169_private
*);
717 void (*enable
)(struct rtl8169_private
*);
718 void (*disable
)(struct rtl8169_private
*);
722 void (*write
)(void __iomem
*, int, int);
723 u32 (*read
)(void __iomem
*, int);
726 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
727 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
728 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
729 void (*hw_start
)(struct net_device
*);
730 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
731 unsigned int (*link_ok
)(void __iomem
*);
732 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
735 DECLARE_BITMAP(flags
, RTL_FLAG_MAX
);
737 struct work_struct work
;
742 struct mii_if_info mii
;
743 struct rtl8169_counters counters
;
748 const struct firmware
*fw
;
750 #define RTL_VER_SIZE 32
752 char version
[RTL_VER_SIZE
];
754 struct rtl_fw_phy_action
{
759 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
762 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
763 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
764 module_param(use_dac
, int, 0);
765 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
766 module_param_named(debug
, debug
.msg_enable
, int, 0);
767 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
768 MODULE_LICENSE("GPL");
769 MODULE_VERSION(RTL8169_VERSION
);
770 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
771 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
772 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
773 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
774 MODULE_FIRMWARE(FIRMWARE_8168E_3
);
775 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
776 MODULE_FIRMWARE(FIRMWARE_8168F_1
);
777 MODULE_FIRMWARE(FIRMWARE_8168F_2
);
779 static void rtl_lock_work(struct rtl8169_private
*tp
)
781 mutex_lock(&tp
->wk
.mutex
);
784 static void rtl_unlock_work(struct rtl8169_private
*tp
)
786 mutex_unlock(&tp
->wk
.mutex
);
789 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
791 int cap
= pci_pcie_cap(pdev
);
796 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
797 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
798 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
802 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
804 void __iomem
*ioaddr
= tp
->mmio_addr
;
807 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
808 for (i
= 0; i
< 20; i
++) {
810 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
813 return RTL_R32(OCPDR
);
816 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
818 void __iomem
*ioaddr
= tp
->mmio_addr
;
821 RTL_W32(OCPDR
, data
);
822 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
823 for (i
= 0; i
< 20; i
++) {
825 if ((RTL_R32(OCPAR
) & OCPAR_FLAG
) == 0)
830 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
832 void __iomem
*ioaddr
= tp
->mmio_addr
;
836 RTL_W32(ERIAR
, 0x800010e8);
838 for (i
= 0; i
< 5; i
++) {
840 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
844 ocp_write(tp
, 0x1, 0x30, 0x00000001);
847 #define OOB_CMD_RESET 0x00
848 #define OOB_CMD_DRIVER_START 0x05
849 #define OOB_CMD_DRIVER_STOP 0x06
851 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
853 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
856 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
861 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
863 reg
= rtl8168_get_ocp_reg(tp
);
865 for (i
= 0; i
< 10; i
++) {
867 if (ocp_read(tp
, 0x0f, reg
) & 0x00000800)
872 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
877 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
879 reg
= rtl8168_get_ocp_reg(tp
);
881 for (i
= 0; i
< 10; i
++) {
883 if ((ocp_read(tp
, 0x0f, reg
) & 0x00000800) == 0)
888 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
890 u16 reg
= rtl8168_get_ocp_reg(tp
);
892 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
895 static void r8169_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
899 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
901 for (i
= 20; i
> 0; i
--) {
903 * Check if the RTL8169 has completed writing to the specified
906 if (!(RTL_R32(PHYAR
) & 0x80000000))
911 * According to hardware specs a 20us delay is required after write
912 * complete indication, but before sending next command.
917 static int r8169_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
921 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
923 for (i
= 20; i
> 0; i
--) {
925 * Check if the RTL8169 has completed retrieving data from
926 * the specified MII register.
928 if (RTL_R32(PHYAR
) & 0x80000000) {
929 value
= RTL_R32(PHYAR
) & 0xffff;
935 * According to hardware specs a 20us delay is required after read
936 * complete indication, but before sending next command.
943 static void r8168dp_1_mdio_access(void __iomem
*ioaddr
, int reg_addr
, u32 data
)
947 RTL_W32(OCPDR
, data
|
948 ((reg_addr
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
949 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
950 RTL_W32(EPHY_RXER_NUM
, 0);
952 for (i
= 0; i
< 100; i
++) {
954 if (!(RTL_R32(OCPAR
) & OCPAR_FLAG
))
959 static void r8168dp_1_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
961 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_WRITE_CMD
|
962 (value
& OCPDR_DATA_MASK
));
965 static int r8168dp_1_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
969 r8168dp_1_mdio_access(ioaddr
, reg_addr
, OCPDR_READ_CMD
);
972 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
973 RTL_W32(EPHY_RXER_NUM
, 0);
975 for (i
= 0; i
< 100; i
++) {
977 if (RTL_R32(OCPAR
) & OCPAR_FLAG
)
981 return RTL_R32(OCPDR
) & OCPDR_DATA_MASK
;
984 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
986 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
988 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
991 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
993 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
996 static void r8168dp_2_mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
998 r8168dp_2_mdio_start(ioaddr
);
1000 r8169_mdio_write(ioaddr
, reg_addr
, value
);
1002 r8168dp_2_mdio_stop(ioaddr
);
1005 static int r8168dp_2_mdio_read(void __iomem
*ioaddr
, int reg_addr
)
1009 r8168dp_2_mdio_start(ioaddr
);
1011 value
= r8169_mdio_read(ioaddr
, reg_addr
);
1013 r8168dp_2_mdio_stop(ioaddr
);
1018 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
1020 tp
->mdio_ops
.write(tp
->mmio_addr
, location
, val
);
1023 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
1025 return tp
->mdio_ops
.read(tp
->mmio_addr
, location
);
1028 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1030 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
1033 static void rtl_w1w0_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
1037 val
= rtl_readphy(tp
, reg_addr
);
1038 rtl_writephy(tp
, reg_addr
, (val
| p
) & ~m
);
1041 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
1044 struct rtl8169_private
*tp
= netdev_priv(dev
);
1046 rtl_writephy(tp
, location
, val
);
1049 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
1051 struct rtl8169_private
*tp
= netdev_priv(dev
);
1053 return rtl_readphy(tp
, location
);
1056 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
1060 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
1061 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1063 for (i
= 0; i
< 100; i
++) {
1064 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
1070 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
1075 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1077 for (i
= 0; i
< 100; i
++) {
1078 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
1079 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
1089 void rtl_eri_write(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 val
, int type
)
1093 BUG_ON((addr
& 3) || (mask
== 0));
1094 RTL_W32(ERIDR
, val
);
1095 RTL_W32(ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1097 for (i
= 0; i
< 100; i
++) {
1098 if (!(RTL_R32(ERIAR
) & ERIAR_FLAG
))
1104 static u32
rtl_eri_read(void __iomem
*ioaddr
, int addr
, int type
)
1109 RTL_W32(ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1111 for (i
= 0; i
< 100; i
++) {
1112 if (RTL_R32(ERIAR
) & ERIAR_FLAG
) {
1113 value
= RTL_R32(ERIDR
);
1123 rtl_w1w0_eri(void __iomem
*ioaddr
, int addr
, u32 mask
, u32 p
, u32 m
, int type
)
1127 val
= rtl_eri_read(ioaddr
, addr
, type
);
1128 rtl_eri_write(ioaddr
, addr
, mask
, (val
& ~m
) | p
, type
);
1137 static void rtl_write_exgmac_batch(void __iomem
*ioaddr
,
1138 const struct exgmac_reg
*r
, int len
)
1141 rtl_eri_write(ioaddr
, r
->addr
, r
->mask
, r
->val
, ERIAR_EXGMAC
);
1146 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
1151 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1153 for (i
= 0; i
< 300; i
++) {
1154 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
1155 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
1164 static u16
rtl_get_events(struct rtl8169_private
*tp
)
1166 void __iomem
*ioaddr
= tp
->mmio_addr
;
1168 return RTL_R16(IntrStatus
);
1171 static void rtl_ack_events(struct rtl8169_private
*tp
, u16 bits
)
1173 void __iomem
*ioaddr
= tp
->mmio_addr
;
1175 RTL_W16(IntrStatus
, bits
);
1179 static void rtl_irq_disable(struct rtl8169_private
*tp
)
1181 void __iomem
*ioaddr
= tp
->mmio_addr
;
1183 RTL_W16(IntrMask
, 0);
1187 static void rtl_irq_enable(struct rtl8169_private
*tp
, u16 bits
)
1189 void __iomem
*ioaddr
= tp
->mmio_addr
;
1191 RTL_W16(IntrMask
, bits
);
1194 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1195 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1196 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1198 static void rtl_irq_enable_all(struct rtl8169_private
*tp
)
1200 rtl_irq_enable(tp
, RTL_EVENT_NAPI
| tp
->event_slow
);
1203 static void rtl8169_irq_mask_and_ack(struct rtl8169_private
*tp
)
1205 void __iomem
*ioaddr
= tp
->mmio_addr
;
1207 rtl_irq_disable(tp
);
1208 rtl_ack_events(tp
, RTL_EVENT_NAPI
| tp
->event_slow
);
1212 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1214 void __iomem
*ioaddr
= tp
->mmio_addr
;
1216 return RTL_R32(TBICSR
) & TBIReset
;
1219 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1221 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1224 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1226 return RTL_R32(TBICSR
) & TBILinkOk
;
1229 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1231 return RTL_R8(PHYstatus
) & LinkStatus
;
1234 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1236 void __iomem
*ioaddr
= tp
->mmio_addr
;
1238 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1241 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1245 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1246 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1249 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1251 void __iomem
*ioaddr
= tp
->mmio_addr
;
1252 struct net_device
*dev
= tp
->dev
;
1254 if (!netif_running(dev
))
1257 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
1258 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1259 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1260 0x00000011, ERIAR_EXGMAC
);
1261 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1262 0x00000005, ERIAR_EXGMAC
);
1263 } else if (RTL_R8(PHYstatus
) & _100bps
) {
1264 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1265 0x0000001f, ERIAR_EXGMAC
);
1266 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1267 0x00000005, ERIAR_EXGMAC
);
1269 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1270 0x0000001f, ERIAR_EXGMAC
);
1271 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1272 0x0000003f, ERIAR_EXGMAC
);
1274 /* Reset packet filter */
1275 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01,
1277 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00,
1279 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
1280 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
1281 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1282 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1283 0x00000011, ERIAR_EXGMAC
);
1284 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1285 0x00000005, ERIAR_EXGMAC
);
1287 rtl_eri_write(ioaddr
, 0x1bc, ERIAR_MASK_1111
,
1288 0x0000001f, ERIAR_EXGMAC
);
1289 rtl_eri_write(ioaddr
, 0x1dc, ERIAR_MASK_1111
,
1290 0x0000003f, ERIAR_EXGMAC
);
1295 static void __rtl8169_check_link_status(struct net_device
*dev
,
1296 struct rtl8169_private
*tp
,
1297 void __iomem
*ioaddr
, bool pm
)
1299 if (tp
->link_ok(ioaddr
)) {
1300 rtl_link_chg_patch(tp
);
1301 /* This is to cancel a scheduled suspend if there's one. */
1303 pm_request_resume(&tp
->pci_dev
->dev
);
1304 netif_carrier_on(dev
);
1305 if (net_ratelimit())
1306 netif_info(tp
, ifup
, dev
, "link up\n");
1308 netif_carrier_off(dev
);
1309 netif_info(tp
, ifdown
, dev
, "link down\n");
1311 pm_schedule_suspend(&tp
->pci_dev
->dev
, 5000);
1315 static void rtl8169_check_link_status(struct net_device
*dev
,
1316 struct rtl8169_private
*tp
,
1317 void __iomem
*ioaddr
)
1319 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1322 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1324 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1326 void __iomem
*ioaddr
= tp
->mmio_addr
;
1330 options
= RTL_R8(Config1
);
1331 if (!(options
& PMEnable
))
1334 options
= RTL_R8(Config3
);
1335 if (options
& LinkUp
)
1336 wolopts
|= WAKE_PHY
;
1337 if (options
& MagicPacket
)
1338 wolopts
|= WAKE_MAGIC
;
1340 options
= RTL_R8(Config5
);
1342 wolopts
|= WAKE_UCAST
;
1344 wolopts
|= WAKE_BCAST
;
1346 wolopts
|= WAKE_MCAST
;
1351 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1353 struct rtl8169_private
*tp
= netdev_priv(dev
);
1357 wol
->supported
= WAKE_ANY
;
1358 wol
->wolopts
= __rtl8169_get_wol(tp
);
1360 rtl_unlock_work(tp
);
1363 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1365 void __iomem
*ioaddr
= tp
->mmio_addr
;
1367 static const struct {
1372 { WAKE_PHY
, Config3
, LinkUp
},
1373 { WAKE_MAGIC
, Config3
, MagicPacket
},
1374 { WAKE_UCAST
, Config5
, UWF
},
1375 { WAKE_BCAST
, Config5
, BWF
},
1376 { WAKE_MCAST
, Config5
, MWF
},
1377 { WAKE_ANY
, Config5
, LanWake
}
1381 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1383 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
1384 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1385 if (wolopts
& cfg
[i
].opt
)
1386 options
|= cfg
[i
].mask
;
1387 RTL_W8(cfg
[i
].reg
, options
);
1390 switch (tp
->mac_version
) {
1391 case RTL_GIGA_MAC_VER_01
... RTL_GIGA_MAC_VER_17
:
1392 options
= RTL_R8(Config1
) & ~PMEnable
;
1394 options
|= PMEnable
;
1395 RTL_W8(Config1
, options
);
1398 options
= RTL_R8(Config2
) & ~PME_SIGNAL
;
1400 options
|= PME_SIGNAL
;
1401 RTL_W8(Config2
, options
);
1405 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1408 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1410 struct rtl8169_private
*tp
= netdev_priv(dev
);
1415 tp
->features
|= RTL_FEATURE_WOL
;
1417 tp
->features
&= ~RTL_FEATURE_WOL
;
1418 __rtl8169_set_wol(tp
, wol
->wolopts
);
1420 rtl_unlock_work(tp
);
1422 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1427 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1429 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1432 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1433 struct ethtool_drvinfo
*info
)
1435 struct rtl8169_private
*tp
= netdev_priv(dev
);
1436 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1438 strlcpy(info
->driver
, MODULENAME
, sizeof(info
->driver
));
1439 strlcpy(info
->version
, RTL8169_VERSION
, sizeof(info
->version
));
1440 strlcpy(info
->bus_info
, pci_name(tp
->pci_dev
), sizeof(info
->bus_info
));
1441 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1442 if (!IS_ERR_OR_NULL(rtl_fw
))
1443 strlcpy(info
->fw_version
, rtl_fw
->version
,
1444 sizeof(info
->fw_version
));
1447 static int rtl8169_get_regs_len(struct net_device
*dev
)
1449 return R8169_REGS_SIZE
;
1452 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1453 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1455 struct rtl8169_private
*tp
= netdev_priv(dev
);
1456 void __iomem
*ioaddr
= tp
->mmio_addr
;
1460 reg
= RTL_R32(TBICSR
);
1461 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1462 (duplex
== DUPLEX_FULL
)) {
1463 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1464 } else if (autoneg
== AUTONEG_ENABLE
)
1465 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1467 netif_warn(tp
, link
, dev
,
1468 "incorrect speed setting refused in TBI mode\n");
1475 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1476 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1478 struct rtl8169_private
*tp
= netdev_priv(dev
);
1479 int giga_ctrl
, bmcr
;
1482 rtl_writephy(tp
, 0x1f, 0x0000);
1484 if (autoneg
== AUTONEG_ENABLE
) {
1487 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1488 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1489 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1491 if (adv
& ADVERTISED_10baseT_Half
)
1492 auto_nego
|= ADVERTISE_10HALF
;
1493 if (adv
& ADVERTISED_10baseT_Full
)
1494 auto_nego
|= ADVERTISE_10FULL
;
1495 if (adv
& ADVERTISED_100baseT_Half
)
1496 auto_nego
|= ADVERTISE_100HALF
;
1497 if (adv
& ADVERTISED_100baseT_Full
)
1498 auto_nego
|= ADVERTISE_100FULL
;
1500 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1502 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1503 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1505 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1506 if (tp
->mii
.supports_gmii
) {
1507 if (adv
& ADVERTISED_1000baseT_Half
)
1508 giga_ctrl
|= ADVERTISE_1000HALF
;
1509 if (adv
& ADVERTISED_1000baseT_Full
)
1510 giga_ctrl
|= ADVERTISE_1000FULL
;
1511 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1512 ADVERTISED_1000baseT_Full
)) {
1513 netif_info(tp
, link
, dev
,
1514 "PHY does not support 1000Mbps\n");
1518 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1520 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1521 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1525 if (speed
== SPEED_10
)
1527 else if (speed
== SPEED_100
)
1528 bmcr
= BMCR_SPEED100
;
1532 if (duplex
== DUPLEX_FULL
)
1533 bmcr
|= BMCR_FULLDPLX
;
1536 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1538 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1539 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
1540 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1541 rtl_writephy(tp
, 0x17, 0x2138);
1542 rtl_writephy(tp
, 0x0e, 0x0260);
1544 rtl_writephy(tp
, 0x17, 0x2108);
1545 rtl_writephy(tp
, 0x0e, 0x0000);
1554 static int rtl8169_set_speed(struct net_device
*dev
,
1555 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
1557 struct rtl8169_private
*tp
= netdev_priv(dev
);
1560 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
1564 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
1565 (advertising
& ADVERTISED_1000baseT_Full
)) {
1566 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1572 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1574 struct rtl8169_private
*tp
= netdev_priv(dev
);
1577 del_timer_sync(&tp
->timer
);
1580 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, ethtool_cmd_speed(cmd
),
1581 cmd
->duplex
, cmd
->advertising
);
1582 rtl_unlock_work(tp
);
1587 static netdev_features_t
rtl8169_fix_features(struct net_device
*dev
,
1588 netdev_features_t features
)
1590 struct rtl8169_private
*tp
= netdev_priv(dev
);
1592 if (dev
->mtu
> TD_MSS_MAX
)
1593 features
&= ~NETIF_F_ALL_TSO
;
1595 if (dev
->mtu
> JUMBO_1K
&&
1596 !rtl_chip_infos
[tp
->mac_version
].jumbo_tx_csum
)
1597 features
&= ~NETIF_F_IP_CSUM
;
1602 static void __rtl8169_set_features(struct net_device
*dev
,
1603 netdev_features_t features
)
1605 struct rtl8169_private
*tp
= netdev_priv(dev
);
1606 netdev_features_t changed
= features
^ dev
->features
;
1607 void __iomem
*ioaddr
= tp
->mmio_addr
;
1609 if (!(changed
& (NETIF_F_RXALL
| NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_RX
)))
1612 if (changed
& (NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_RX
)) {
1613 if (features
& NETIF_F_RXCSUM
)
1614 tp
->cp_cmd
|= RxChkSum
;
1616 tp
->cp_cmd
&= ~RxChkSum
;
1618 if (dev
->features
& NETIF_F_HW_VLAN_RX
)
1619 tp
->cp_cmd
|= RxVlan
;
1621 tp
->cp_cmd
&= ~RxVlan
;
1623 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1626 if (changed
& NETIF_F_RXALL
) {
1627 int tmp
= (RTL_R32(RxConfig
) & ~(AcceptErr
| AcceptRunt
));
1628 if (features
& NETIF_F_RXALL
)
1629 tmp
|= (AcceptErr
| AcceptRunt
);
1630 RTL_W32(RxConfig
, tmp
);
1634 static int rtl8169_set_features(struct net_device
*dev
,
1635 netdev_features_t features
)
1637 struct rtl8169_private
*tp
= netdev_priv(dev
);
1640 __rtl8169_set_features(dev
, features
);
1641 rtl_unlock_work(tp
);
1647 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1648 struct sk_buff
*skb
)
1650 return (vlan_tx_tag_present(skb
)) ?
1651 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1654 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1656 u32 opts2
= le32_to_cpu(desc
->opts2
);
1658 if (opts2
& RxVlanTag
)
1659 __vlan_hwaccel_put_tag(skb
, swab16(opts2
& 0xffff));
1664 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1666 struct rtl8169_private
*tp
= netdev_priv(dev
);
1667 void __iomem
*ioaddr
= tp
->mmio_addr
;
1671 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1672 cmd
->port
= PORT_FIBRE
;
1673 cmd
->transceiver
= XCVR_INTERNAL
;
1675 status
= RTL_R32(TBICSR
);
1676 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1677 cmd
->autoneg
= !!(status
& TBINwEnable
);
1679 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1680 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1685 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1687 struct rtl8169_private
*tp
= netdev_priv(dev
);
1689 return mii_ethtool_gset(&tp
->mii
, cmd
);
1692 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1694 struct rtl8169_private
*tp
= netdev_priv(dev
);
1698 rc
= tp
->get_settings(dev
, cmd
);
1699 rtl_unlock_work(tp
);
1704 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1707 struct rtl8169_private
*tp
= netdev_priv(dev
);
1709 if (regs
->len
> R8169_REGS_SIZE
)
1710 regs
->len
= R8169_REGS_SIZE
;
1713 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1714 rtl_unlock_work(tp
);
1717 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1719 struct rtl8169_private
*tp
= netdev_priv(dev
);
1721 return tp
->msg_enable
;
1724 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1726 struct rtl8169_private
*tp
= netdev_priv(dev
);
1728 tp
->msg_enable
= value
;
1731 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1738 "tx_single_collisions",
1739 "tx_multi_collisions",
1747 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1751 return ARRAY_SIZE(rtl8169_gstrings
);
1757 static void rtl8169_update_counters(struct net_device
*dev
)
1759 struct rtl8169_private
*tp
= netdev_priv(dev
);
1760 void __iomem
*ioaddr
= tp
->mmio_addr
;
1761 struct device
*d
= &tp
->pci_dev
->dev
;
1762 struct rtl8169_counters
*counters
;
1768 * Some chips are unable to dump tally counters when the receiver
1771 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1774 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
1778 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1779 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1780 RTL_W32(CounterAddrLow
, cmd
);
1781 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1784 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1785 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1791 RTL_W32(CounterAddrLow
, 0);
1792 RTL_W32(CounterAddrHigh
, 0);
1794 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
1797 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1798 struct ethtool_stats
*stats
, u64
*data
)
1800 struct rtl8169_private
*tp
= netdev_priv(dev
);
1804 rtl8169_update_counters(dev
);
1806 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1807 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1808 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1809 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1810 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1811 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1812 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1813 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1814 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1815 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1816 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1817 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1818 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1821 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1825 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1830 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1831 .get_drvinfo
= rtl8169_get_drvinfo
,
1832 .get_regs_len
= rtl8169_get_regs_len
,
1833 .get_link
= ethtool_op_get_link
,
1834 .get_settings
= rtl8169_get_settings
,
1835 .set_settings
= rtl8169_set_settings
,
1836 .get_msglevel
= rtl8169_get_msglevel
,
1837 .set_msglevel
= rtl8169_set_msglevel
,
1838 .get_regs
= rtl8169_get_regs
,
1839 .get_wol
= rtl8169_get_wol
,
1840 .set_wol
= rtl8169_set_wol
,
1841 .get_strings
= rtl8169_get_strings
,
1842 .get_sset_count
= rtl8169_get_sset_count
,
1843 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1844 .get_ts_info
= ethtool_op_get_ts_info
,
1847 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1848 struct net_device
*dev
, u8 default_version
)
1850 void __iomem
*ioaddr
= tp
->mmio_addr
;
1852 * The driver currently handles the 8168Bf and the 8168Be identically
1853 * but they can be identified more specifically through the test below
1856 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1858 * Same thing for the 8101Eb and the 8101Ec:
1860 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1862 static const struct rtl_mac_info
{
1868 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36
},
1869 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35
},
1872 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34
},
1873 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
1874 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
1875 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
1878 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1879 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1880 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1882 /* 8168DP family. */
1883 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1884 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
1885 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
1888 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
1889 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1890 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1891 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1892 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1893 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1894 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1895 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1896 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1899 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1900 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1901 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1902 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1905 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
1906 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
1907 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
1908 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
1909 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1910 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1911 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1912 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1913 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1914 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1915 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1916 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1917 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1918 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1919 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1920 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1921 /* FIXME: where did these entries come from ? -- FR */
1922 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1923 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1926 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1927 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1928 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1929 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1930 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1931 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1934 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1936 const struct rtl_mac_info
*p
= mac_info
;
1939 reg
= RTL_R32(TxConfig
);
1940 while ((reg
& p
->mask
) != p
->val
)
1942 tp
->mac_version
= p
->mac_version
;
1944 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
1945 netif_notice(tp
, probe
, dev
,
1946 "unknown MAC, using family default\n");
1947 tp
->mac_version
= default_version
;
1951 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1953 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1961 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
1962 const struct phy_reg
*regs
, int len
)
1965 rtl_writephy(tp
, regs
->reg
, regs
->val
);
1970 #define PHY_READ 0x00000000
1971 #define PHY_DATA_OR 0x10000000
1972 #define PHY_DATA_AND 0x20000000
1973 #define PHY_BJMPN 0x30000000
1974 #define PHY_READ_EFUSE 0x40000000
1975 #define PHY_READ_MAC_BYTE 0x50000000
1976 #define PHY_WRITE_MAC_BYTE 0x60000000
1977 #define PHY_CLEAR_READCOUNT 0x70000000
1978 #define PHY_WRITE 0x80000000
1979 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1980 #define PHY_COMP_EQ_SKIPN 0xa0000000
1981 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1982 #define PHY_WRITE_PREVIOUS 0xc0000000
1983 #define PHY_SKIPN 0xd0000000
1984 #define PHY_DELAY_MS 0xe0000000
1985 #define PHY_WRITE_ERI_WORD 0xf0000000
1989 char version
[RTL_VER_SIZE
];
1995 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1997 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
1999 const struct firmware
*fw
= rtl_fw
->fw
;
2000 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
2001 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2002 char *version
= rtl_fw
->version
;
2005 if (fw
->size
< FW_OPCODE_SIZE
)
2008 if (!fw_info
->magic
) {
2009 size_t i
, size
, start
;
2012 if (fw
->size
< sizeof(*fw_info
))
2015 for (i
= 0; i
< fw
->size
; i
++)
2016 checksum
+= fw
->data
[i
];
2020 start
= le32_to_cpu(fw_info
->fw_start
);
2021 if (start
> fw
->size
)
2024 size
= le32_to_cpu(fw_info
->fw_len
);
2025 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
2028 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
2030 pa
->code
= (__le32
*)(fw
->data
+ start
);
2033 if (fw
->size
% FW_OPCODE_SIZE
)
2036 strlcpy(version
, rtl_lookup_firmware_name(tp
), RTL_VER_SIZE
);
2038 pa
->code
= (__le32
*)fw
->data
;
2039 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
2041 version
[RTL_VER_SIZE
- 1] = 0;
2048 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
2049 struct rtl_fw_phy_action
*pa
)
2054 for (index
= 0; index
< pa
->size
; index
++) {
2055 u32 action
= le32_to_cpu(pa
->code
[index
]);
2056 u32 regno
= (action
& 0x0fff0000) >> 16;
2058 switch(action
& 0xf0000000) {
2062 case PHY_READ_EFUSE
:
2063 case PHY_CLEAR_READCOUNT
:
2065 case PHY_WRITE_PREVIOUS
:
2070 if (regno
> index
) {
2071 netif_err(tp
, ifup
, tp
->dev
,
2072 "Out of range of firmware\n");
2076 case PHY_READCOUNT_EQ_SKIP
:
2077 if (index
+ 2 >= pa
->size
) {
2078 netif_err(tp
, ifup
, tp
->dev
,
2079 "Out of range of firmware\n");
2083 case PHY_COMP_EQ_SKIPN
:
2084 case PHY_COMP_NEQ_SKIPN
:
2086 if (index
+ 1 + regno
>= pa
->size
) {
2087 netif_err(tp
, ifup
, tp
->dev
,
2088 "Out of range of firmware\n");
2093 case PHY_READ_MAC_BYTE
:
2094 case PHY_WRITE_MAC_BYTE
:
2095 case PHY_WRITE_ERI_WORD
:
2097 netif_err(tp
, ifup
, tp
->dev
,
2098 "Invalid action 0x%08x\n", action
);
2107 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2109 struct net_device
*dev
= tp
->dev
;
2112 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
2113 netif_err(tp
, ifup
, dev
, "invalid firwmare\n");
2117 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
2123 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2125 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2129 predata
= count
= 0;
2131 for (index
= 0; index
< pa
->size
; ) {
2132 u32 action
= le32_to_cpu(pa
->code
[index
]);
2133 u32 data
= action
& 0x0000ffff;
2134 u32 regno
= (action
& 0x0fff0000) >> 16;
2139 switch(action
& 0xf0000000) {
2141 predata
= rtl_readphy(tp
, regno
);
2156 case PHY_READ_EFUSE
:
2157 predata
= rtl8168d_efuse_read(tp
->mmio_addr
, regno
);
2160 case PHY_CLEAR_READCOUNT
:
2165 rtl_writephy(tp
, regno
, data
);
2168 case PHY_READCOUNT_EQ_SKIP
:
2169 index
+= (count
== data
) ? 2 : 1;
2171 case PHY_COMP_EQ_SKIPN
:
2172 if (predata
== data
)
2176 case PHY_COMP_NEQ_SKIPN
:
2177 if (predata
!= data
)
2181 case PHY_WRITE_PREVIOUS
:
2182 rtl_writephy(tp
, regno
, predata
);
2193 case PHY_READ_MAC_BYTE
:
2194 case PHY_WRITE_MAC_BYTE
:
2195 case PHY_WRITE_ERI_WORD
:
2202 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2204 if (!IS_ERR_OR_NULL(tp
->rtl_fw
)) {
2205 release_firmware(tp
->rtl_fw
->fw
);
2208 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
2211 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
2213 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
2215 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2216 if (!IS_ERR_OR_NULL(rtl_fw
))
2217 rtl_phy_write_fw(tp
, rtl_fw
);
2220 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
2222 if (rtl_readphy(tp
, reg
) != val
)
2223 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
2225 rtl_apply_firmware(tp
);
2228 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2230 static const struct phy_reg phy_reg_init
[] = {
2292 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2295 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2297 static const struct phy_reg phy_reg_init
[] = {
2303 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2306 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2308 struct pci_dev
*pdev
= tp
->pci_dev
;
2310 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
2311 (pdev
->subsystem_device
!= 0xe000))
2314 rtl_writephy(tp
, 0x1f, 0x0001);
2315 rtl_writephy(tp
, 0x10, 0xf01b);
2316 rtl_writephy(tp
, 0x1f, 0x0000);
2319 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2321 static const struct phy_reg phy_reg_init
[] = {
2361 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2363 rtl8169scd_hw_phy_config_quirk(tp
);
2366 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2368 static const struct phy_reg phy_reg_init
[] = {
2416 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2419 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2421 static const struct phy_reg phy_reg_init
[] = {
2426 rtl_writephy(tp
, 0x1f, 0x0001);
2427 rtl_patchphy(tp
, 0x16, 1 << 0);
2429 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2432 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2434 static const struct phy_reg phy_reg_init
[] = {
2440 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2443 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2445 static const struct phy_reg phy_reg_init
[] = {
2453 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2456 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2458 static const struct phy_reg phy_reg_init
[] = {
2464 rtl_writephy(tp
, 0x1f, 0x0000);
2465 rtl_patchphy(tp
, 0x14, 1 << 5);
2466 rtl_patchphy(tp
, 0x0d, 1 << 5);
2468 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2471 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2473 static const struct phy_reg phy_reg_init
[] = {
2493 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2495 rtl_patchphy(tp
, 0x14, 1 << 5);
2496 rtl_patchphy(tp
, 0x0d, 1 << 5);
2497 rtl_writephy(tp
, 0x1f, 0x0000);
2500 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2502 static const struct phy_reg phy_reg_init
[] = {
2520 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2522 rtl_patchphy(tp
, 0x16, 1 << 0);
2523 rtl_patchphy(tp
, 0x14, 1 << 5);
2524 rtl_patchphy(tp
, 0x0d, 1 << 5);
2525 rtl_writephy(tp
, 0x1f, 0x0000);
2528 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2530 static const struct phy_reg phy_reg_init
[] = {
2542 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2544 rtl_patchphy(tp
, 0x16, 1 << 0);
2545 rtl_patchphy(tp
, 0x14, 1 << 5);
2546 rtl_patchphy(tp
, 0x0d, 1 << 5);
2547 rtl_writephy(tp
, 0x1f, 0x0000);
2550 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2552 rtl8168c_3_hw_phy_config(tp
);
2555 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2557 static const struct phy_reg phy_reg_init_0
[] = {
2558 /* Channel Estimation */
2579 * Enhance line driver power
2588 * Can not link to 1Gbps with bad cable
2589 * Decrease SNR threshold form 21.07dB to 19.04dB
2597 void __iomem
*ioaddr
= tp
->mmio_addr
;
2599 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2603 * Fine Tune Switching regulator parameter
2605 rtl_writephy(tp
, 0x1f, 0x0002);
2606 rtl_w1w0_phy(tp
, 0x0b, 0x0010, 0x00ef);
2607 rtl_w1w0_phy(tp
, 0x0c, 0xa200, 0x5d00);
2609 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2610 static const struct phy_reg phy_reg_init
[] = {
2620 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2622 val
= rtl_readphy(tp
, 0x0d);
2624 if ((val
& 0x00ff) != 0x006c) {
2625 static const u32 set
[] = {
2626 0x0065, 0x0066, 0x0067, 0x0068,
2627 0x0069, 0x006a, 0x006b, 0x006c
2631 rtl_writephy(tp
, 0x1f, 0x0002);
2634 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2635 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2638 static const struct phy_reg phy_reg_init
[] = {
2646 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2649 /* RSET couple improve */
2650 rtl_writephy(tp
, 0x1f, 0x0002);
2651 rtl_patchphy(tp
, 0x0d, 0x0300);
2652 rtl_patchphy(tp
, 0x0f, 0x0010);
2654 /* Fine tune PLL performance */
2655 rtl_writephy(tp
, 0x1f, 0x0002);
2656 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2657 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2659 rtl_writephy(tp
, 0x1f, 0x0005);
2660 rtl_writephy(tp
, 0x05, 0x001b);
2662 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
2664 rtl_writephy(tp
, 0x1f, 0x0000);
2667 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2669 static const struct phy_reg phy_reg_init_0
[] = {
2670 /* Channel Estimation */
2691 * Enhance line driver power
2700 * Can not link to 1Gbps with bad cable
2701 * Decrease SNR threshold form 21.07dB to 19.04dB
2709 void __iomem
*ioaddr
= tp
->mmio_addr
;
2711 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2713 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2714 static const struct phy_reg phy_reg_init
[] = {
2725 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2727 val
= rtl_readphy(tp
, 0x0d);
2728 if ((val
& 0x00ff) != 0x006c) {
2729 static const u32 set
[] = {
2730 0x0065, 0x0066, 0x0067, 0x0068,
2731 0x0069, 0x006a, 0x006b, 0x006c
2735 rtl_writephy(tp
, 0x1f, 0x0002);
2738 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2739 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2742 static const struct phy_reg phy_reg_init
[] = {
2750 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2753 /* Fine tune PLL performance */
2754 rtl_writephy(tp
, 0x1f, 0x0002);
2755 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2756 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2758 /* Switching regulator Slew rate */
2759 rtl_writephy(tp
, 0x1f, 0x0002);
2760 rtl_patchphy(tp
, 0x0f, 0x0017);
2762 rtl_writephy(tp
, 0x1f, 0x0005);
2763 rtl_writephy(tp
, 0x05, 0x001b);
2765 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
2767 rtl_writephy(tp
, 0x1f, 0x0000);
2770 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
2772 static const struct phy_reg phy_reg_init
[] = {
2828 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2831 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
2833 static const struct phy_reg phy_reg_init
[] = {
2843 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2844 rtl_patchphy(tp
, 0x0d, 1 << 5);
2847 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
2849 static const struct phy_reg phy_reg_init
[] = {
2850 /* Enable Delay cap */
2856 /* Channel estimation fine tune */
2865 /* Update PFM & 10M TX idle timer */
2877 rtl_apply_firmware(tp
);
2879 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2881 /* DCO enable for 10M IDLE Power */
2882 rtl_writephy(tp
, 0x1f, 0x0007);
2883 rtl_writephy(tp
, 0x1e, 0x0023);
2884 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2885 rtl_writephy(tp
, 0x1f, 0x0000);
2887 /* For impedance matching */
2888 rtl_writephy(tp
, 0x1f, 0x0002);
2889 rtl_w1w0_phy(tp
, 0x08, 0x8000, 0x7f00);
2890 rtl_writephy(tp
, 0x1f, 0x0000);
2892 /* PHY auto speed down */
2893 rtl_writephy(tp
, 0x1f, 0x0007);
2894 rtl_writephy(tp
, 0x1e, 0x002d);
2895 rtl_w1w0_phy(tp
, 0x18, 0x0050, 0x0000);
2896 rtl_writephy(tp
, 0x1f, 0x0000);
2897 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2899 rtl_writephy(tp
, 0x1f, 0x0005);
2900 rtl_writephy(tp
, 0x05, 0x8b86);
2901 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2902 rtl_writephy(tp
, 0x1f, 0x0000);
2904 rtl_writephy(tp
, 0x1f, 0x0005);
2905 rtl_writephy(tp
, 0x05, 0x8b85);
2906 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2907 rtl_writephy(tp
, 0x1f, 0x0007);
2908 rtl_writephy(tp
, 0x1e, 0x0020);
2909 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x1100);
2910 rtl_writephy(tp
, 0x1f, 0x0006);
2911 rtl_writephy(tp
, 0x00, 0x5a00);
2912 rtl_writephy(tp
, 0x1f, 0x0000);
2913 rtl_writephy(tp
, 0x0d, 0x0007);
2914 rtl_writephy(tp
, 0x0e, 0x003c);
2915 rtl_writephy(tp
, 0x0d, 0x4007);
2916 rtl_writephy(tp
, 0x0e, 0x0000);
2917 rtl_writephy(tp
, 0x0d, 0x0000);
2920 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
2922 static const struct phy_reg phy_reg_init
[] = {
2923 /* Enable Delay cap */
2932 /* Channel estimation fine tune */
2949 rtl_apply_firmware(tp
);
2951 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2953 /* For 4-corner performance improve */
2954 rtl_writephy(tp
, 0x1f, 0x0005);
2955 rtl_writephy(tp
, 0x05, 0x8b80);
2956 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
2957 rtl_writephy(tp
, 0x1f, 0x0000);
2959 /* PHY auto speed down */
2960 rtl_writephy(tp
, 0x1f, 0x0004);
2961 rtl_writephy(tp
, 0x1f, 0x0007);
2962 rtl_writephy(tp
, 0x1e, 0x002d);
2963 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
2964 rtl_writephy(tp
, 0x1f, 0x0002);
2965 rtl_writephy(tp
, 0x1f, 0x0000);
2966 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
2968 /* improve 10M EEE waveform */
2969 rtl_writephy(tp
, 0x1f, 0x0005);
2970 rtl_writephy(tp
, 0x05, 0x8b86);
2971 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
2972 rtl_writephy(tp
, 0x1f, 0x0000);
2974 /* Improve 2-pair detection performance */
2975 rtl_writephy(tp
, 0x1f, 0x0005);
2976 rtl_writephy(tp
, 0x05, 0x8b85);
2977 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
2978 rtl_writephy(tp
, 0x1f, 0x0000);
2981 rtl_w1w0_eri(tp
->mmio_addr
, 0x1b0, ERIAR_MASK_1111
, 0x0000, 0x0003,
2983 rtl_writephy(tp
, 0x1f, 0x0005);
2984 rtl_writephy(tp
, 0x05, 0x8b85);
2985 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
2986 rtl_writephy(tp
, 0x1f, 0x0004);
2987 rtl_writephy(tp
, 0x1f, 0x0007);
2988 rtl_writephy(tp
, 0x1e, 0x0020);
2989 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x0100);
2990 rtl_writephy(tp
, 0x1f, 0x0002);
2991 rtl_writephy(tp
, 0x1f, 0x0000);
2992 rtl_writephy(tp
, 0x0d, 0x0007);
2993 rtl_writephy(tp
, 0x0e, 0x003c);
2994 rtl_writephy(tp
, 0x0d, 0x4007);
2995 rtl_writephy(tp
, 0x0e, 0x0000);
2996 rtl_writephy(tp
, 0x0d, 0x0000);
2999 rtl_writephy(tp
, 0x1f, 0x0003);
3000 rtl_w1w0_phy(tp
, 0x19, 0x0000, 0x0001);
3001 rtl_w1w0_phy(tp
, 0x10, 0x0000, 0x0400);
3002 rtl_writephy(tp
, 0x1f, 0x0000);
3005 static void rtl8168f_1_hw_phy_config(struct rtl8169_private
*tp
)
3007 static const struct phy_reg phy_reg_init
[] = {
3008 /* Channel estimation fine tune */
3013 /* Modify green table for giga & fnet */
3030 /* Modify green table for 10M */
3036 /* Disable hiimpedance detection (RTCT) */
3042 rtl_apply_firmware(tp
);
3044 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3046 /* For 4-corner performance improve */
3047 rtl_writephy(tp
, 0x1f, 0x0005);
3048 rtl_writephy(tp
, 0x05, 0x8b80);
3049 rtl_w1w0_phy(tp
, 0x06, 0x0006, 0x0000);
3050 rtl_writephy(tp
, 0x1f, 0x0000);
3052 /* PHY auto speed down */
3053 rtl_writephy(tp
, 0x1f, 0x0007);
3054 rtl_writephy(tp
, 0x1e, 0x002d);
3055 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
3056 rtl_writephy(tp
, 0x1f, 0x0000);
3057 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
3059 /* Improve 10M EEE waveform */
3060 rtl_writephy(tp
, 0x1f, 0x0005);
3061 rtl_writephy(tp
, 0x05, 0x8b86);
3062 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
3063 rtl_writephy(tp
, 0x1f, 0x0000);
3065 /* Improve 2-pair detection performance */
3066 rtl_writephy(tp
, 0x1f, 0x0005);
3067 rtl_writephy(tp
, 0x05, 0x8b85);
3068 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
3069 rtl_writephy(tp
, 0x1f, 0x0000);
3072 static void rtl8168f_2_hw_phy_config(struct rtl8169_private
*tp
)
3074 rtl_apply_firmware(tp
);
3076 /* For 4-corner performance improve */
3077 rtl_writephy(tp
, 0x1f, 0x0005);
3078 rtl_writephy(tp
, 0x05, 0x8b80);
3079 rtl_w1w0_phy(tp
, 0x06, 0x0006, 0x0000);
3080 rtl_writephy(tp
, 0x1f, 0x0000);
3082 /* PHY auto speed down */
3083 rtl_writephy(tp
, 0x1f, 0x0007);
3084 rtl_writephy(tp
, 0x1e, 0x002d);
3085 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
3086 rtl_writephy(tp
, 0x1f, 0x0000);
3087 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
3089 /* Improve 10M EEE waveform */
3090 rtl_writephy(tp
, 0x1f, 0x0005);
3091 rtl_writephy(tp
, 0x05, 0x8b86);
3092 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
3093 rtl_writephy(tp
, 0x1f, 0x0000);
3096 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
3098 static const struct phy_reg phy_reg_init
[] = {
3105 rtl_writephy(tp
, 0x1f, 0x0000);
3106 rtl_patchphy(tp
, 0x11, 1 << 12);
3107 rtl_patchphy(tp
, 0x19, 1 << 13);
3108 rtl_patchphy(tp
, 0x10, 1 << 15);
3110 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3113 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
3115 static const struct phy_reg phy_reg_init
[] = {
3129 /* Disable ALDPS before ram code */
3130 rtl_writephy(tp
, 0x1f, 0x0000);
3131 rtl_writephy(tp
, 0x18, 0x0310);
3134 rtl_apply_firmware(tp
);
3136 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3139 static void rtl_hw_phy_config(struct net_device
*dev
)
3141 struct rtl8169_private
*tp
= netdev_priv(dev
);
3143 rtl8169_print_mac_version(tp
);
3145 switch (tp
->mac_version
) {
3146 case RTL_GIGA_MAC_VER_01
:
3148 case RTL_GIGA_MAC_VER_02
:
3149 case RTL_GIGA_MAC_VER_03
:
3150 rtl8169s_hw_phy_config(tp
);
3152 case RTL_GIGA_MAC_VER_04
:
3153 rtl8169sb_hw_phy_config(tp
);
3155 case RTL_GIGA_MAC_VER_05
:
3156 rtl8169scd_hw_phy_config(tp
);
3158 case RTL_GIGA_MAC_VER_06
:
3159 rtl8169sce_hw_phy_config(tp
);
3161 case RTL_GIGA_MAC_VER_07
:
3162 case RTL_GIGA_MAC_VER_08
:
3163 case RTL_GIGA_MAC_VER_09
:
3164 rtl8102e_hw_phy_config(tp
);
3166 case RTL_GIGA_MAC_VER_11
:
3167 rtl8168bb_hw_phy_config(tp
);
3169 case RTL_GIGA_MAC_VER_12
:
3170 rtl8168bef_hw_phy_config(tp
);
3172 case RTL_GIGA_MAC_VER_17
:
3173 rtl8168bef_hw_phy_config(tp
);
3175 case RTL_GIGA_MAC_VER_18
:
3176 rtl8168cp_1_hw_phy_config(tp
);
3178 case RTL_GIGA_MAC_VER_19
:
3179 rtl8168c_1_hw_phy_config(tp
);
3181 case RTL_GIGA_MAC_VER_20
:
3182 rtl8168c_2_hw_phy_config(tp
);
3184 case RTL_GIGA_MAC_VER_21
:
3185 rtl8168c_3_hw_phy_config(tp
);
3187 case RTL_GIGA_MAC_VER_22
:
3188 rtl8168c_4_hw_phy_config(tp
);
3190 case RTL_GIGA_MAC_VER_23
:
3191 case RTL_GIGA_MAC_VER_24
:
3192 rtl8168cp_2_hw_phy_config(tp
);
3194 case RTL_GIGA_MAC_VER_25
:
3195 rtl8168d_1_hw_phy_config(tp
);
3197 case RTL_GIGA_MAC_VER_26
:
3198 rtl8168d_2_hw_phy_config(tp
);
3200 case RTL_GIGA_MAC_VER_27
:
3201 rtl8168d_3_hw_phy_config(tp
);
3203 case RTL_GIGA_MAC_VER_28
:
3204 rtl8168d_4_hw_phy_config(tp
);
3206 case RTL_GIGA_MAC_VER_29
:
3207 case RTL_GIGA_MAC_VER_30
:
3208 rtl8105e_hw_phy_config(tp
);
3210 case RTL_GIGA_MAC_VER_31
:
3213 case RTL_GIGA_MAC_VER_32
:
3214 case RTL_GIGA_MAC_VER_33
:
3215 rtl8168e_1_hw_phy_config(tp
);
3217 case RTL_GIGA_MAC_VER_34
:
3218 rtl8168e_2_hw_phy_config(tp
);
3220 case RTL_GIGA_MAC_VER_35
:
3221 rtl8168f_1_hw_phy_config(tp
);
3223 case RTL_GIGA_MAC_VER_36
:
3224 rtl8168f_2_hw_phy_config(tp
);
3232 static void rtl_phy_work(struct rtl8169_private
*tp
)
3234 struct timer_list
*timer
= &tp
->timer
;
3235 void __iomem
*ioaddr
= tp
->mmio_addr
;
3236 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
3238 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
3240 if (tp
->phy_reset_pending(tp
)) {
3242 * A busy loop could burn quite a few cycles on nowadays CPU.
3243 * Let's delay the execution of the timer for a few ticks.
3249 if (tp
->link_ok(ioaddr
))
3252 netif_warn(tp
, link
, tp
->dev
, "PHY reset until link up\n");
3254 tp
->phy_reset_enable(tp
);
3257 mod_timer(timer
, jiffies
+ timeout
);
3260 static void rtl_schedule_task(struct rtl8169_private
*tp
, enum rtl_flag flag
)
3262 if (!test_and_set_bit(flag
, tp
->wk
.flags
))
3263 schedule_work(&tp
->wk
.work
);
3266 static void rtl8169_phy_timer(unsigned long __opaque
)
3268 struct net_device
*dev
= (struct net_device
*)__opaque
;
3269 struct rtl8169_private
*tp
= netdev_priv(dev
);
3271 rtl_schedule_task(tp
, RTL_FLAG_TASK_PHY_PENDING
);
3274 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
3275 void __iomem
*ioaddr
)
3278 pci_release_regions(pdev
);
3279 pci_clear_mwi(pdev
);
3280 pci_disable_device(pdev
);
3284 static void rtl8169_phy_reset(struct net_device
*dev
,
3285 struct rtl8169_private
*tp
)
3289 tp
->phy_reset_enable(tp
);
3290 for (i
= 0; i
< 100; i
++) {
3291 if (!tp
->phy_reset_pending(tp
))
3295 netif_err(tp
, link
, dev
, "PHY reset failed\n");
3298 static bool rtl_tbi_enabled(struct rtl8169_private
*tp
)
3300 void __iomem
*ioaddr
= tp
->mmio_addr
;
3302 return (tp
->mac_version
== RTL_GIGA_MAC_VER_01
) &&
3303 (RTL_R8(PHYstatus
) & TBI_Enable
);
3306 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
3308 void __iomem
*ioaddr
= tp
->mmio_addr
;
3310 rtl_hw_phy_config(dev
);
3312 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
3313 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3317 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
3319 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
3320 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
3322 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
3323 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3325 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3326 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
3329 rtl8169_phy_reset(dev
, tp
);
3331 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
3332 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
3333 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
3334 (tp
->mii
.supports_gmii
?
3335 ADVERTISED_1000baseT_Half
|
3336 ADVERTISED_1000baseT_Full
: 0));
3338 if (rtl_tbi_enabled(tp
))
3339 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
3342 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
3344 void __iomem
*ioaddr
= tp
->mmio_addr
;
3348 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
3349 high
= addr
[4] | (addr
[5] << 8);
3353 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3355 RTL_W32(MAC4
, high
);
3361 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
) {
3362 const struct exgmac_reg e
[] = {
3363 { .addr
= 0xe0, ERIAR_MASK_1111
, .val
= low
},
3364 { .addr
= 0xe4, ERIAR_MASK_1111
, .val
= high
},
3365 { .addr
= 0xf0, ERIAR_MASK_1111
, .val
= low
<< 16 },
3366 { .addr
= 0xf4, ERIAR_MASK_1111
, .val
= high
<< 16 |
3370 rtl_write_exgmac_batch(ioaddr
, e
, ARRAY_SIZE(e
));
3373 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3375 rtl_unlock_work(tp
);
3378 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
3380 struct rtl8169_private
*tp
= netdev_priv(dev
);
3381 struct sockaddr
*addr
= p
;
3383 if (!is_valid_ether_addr(addr
->sa_data
))
3384 return -EADDRNOTAVAIL
;
3386 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
3388 rtl_rar_set(tp
, dev
->dev_addr
);
3393 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3395 struct rtl8169_private
*tp
= netdev_priv(dev
);
3396 struct mii_ioctl_data
*data
= if_mii(ifr
);
3398 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
3401 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
3402 struct mii_ioctl_data
*data
, int cmd
)
3406 data
->phy_id
= 32; /* Internal PHY */
3410 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
3414 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
3420 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
3425 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
3427 if (tp
->features
& RTL_FEATURE_MSI
) {
3428 pci_disable_msi(pdev
);
3429 tp
->features
&= ~RTL_FEATURE_MSI
;
3433 static void __devinit
rtl_init_mdio_ops(struct rtl8169_private
*tp
)
3435 struct mdio_ops
*ops
= &tp
->mdio_ops
;
3437 switch (tp
->mac_version
) {
3438 case RTL_GIGA_MAC_VER_27
:
3439 ops
->write
= r8168dp_1_mdio_write
;
3440 ops
->read
= r8168dp_1_mdio_read
;
3442 case RTL_GIGA_MAC_VER_28
:
3443 case RTL_GIGA_MAC_VER_31
:
3444 ops
->write
= r8168dp_2_mdio_write
;
3445 ops
->read
= r8168dp_2_mdio_read
;
3448 ops
->write
= r8169_mdio_write
;
3449 ops
->read
= r8169_mdio_read
;
3454 static void rtl_wol_suspend_quirk(struct rtl8169_private
*tp
)
3456 void __iomem
*ioaddr
= tp
->mmio_addr
;
3458 switch (tp
->mac_version
) {
3459 case RTL_GIGA_MAC_VER_29
:
3460 case RTL_GIGA_MAC_VER_30
:
3461 case RTL_GIGA_MAC_VER_32
:
3462 case RTL_GIGA_MAC_VER_33
:
3463 case RTL_GIGA_MAC_VER_34
:
3464 RTL_W32(RxConfig
, RTL_R32(RxConfig
) |
3465 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
3472 static bool rtl_wol_pll_power_down(struct rtl8169_private
*tp
)
3474 if (!(__rtl8169_get_wol(tp
) & WAKE_ANY
))
3477 rtl_writephy(tp
, 0x1f, 0x0000);
3478 rtl_writephy(tp
, MII_BMCR
, 0x0000);
3480 rtl_wol_suspend_quirk(tp
);
3485 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
3487 rtl_writephy(tp
, 0x1f, 0x0000);
3488 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3491 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
3493 rtl_writephy(tp
, 0x1f, 0x0000);
3494 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3497 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
3499 void __iomem
*ioaddr
= tp
->mmio_addr
;
3501 if (rtl_wol_pll_power_down(tp
))
3504 r810x_phy_power_down(tp
);
3506 switch (tp
->mac_version
) {
3507 case RTL_GIGA_MAC_VER_07
:
3508 case RTL_GIGA_MAC_VER_08
:
3509 case RTL_GIGA_MAC_VER_09
:
3510 case RTL_GIGA_MAC_VER_10
:
3511 case RTL_GIGA_MAC_VER_13
:
3512 case RTL_GIGA_MAC_VER_16
:
3515 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
3520 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
3522 void __iomem
*ioaddr
= tp
->mmio_addr
;
3524 r810x_phy_power_up(tp
);
3526 switch (tp
->mac_version
) {
3527 case RTL_GIGA_MAC_VER_07
:
3528 case RTL_GIGA_MAC_VER_08
:
3529 case RTL_GIGA_MAC_VER_09
:
3530 case RTL_GIGA_MAC_VER_10
:
3531 case RTL_GIGA_MAC_VER_13
:
3532 case RTL_GIGA_MAC_VER_16
:
3535 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
3540 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
3542 rtl_writephy(tp
, 0x1f, 0x0000);
3543 switch (tp
->mac_version
) {
3544 case RTL_GIGA_MAC_VER_11
:
3545 case RTL_GIGA_MAC_VER_12
:
3546 case RTL_GIGA_MAC_VER_17
:
3547 case RTL_GIGA_MAC_VER_18
:
3548 case RTL_GIGA_MAC_VER_19
:
3549 case RTL_GIGA_MAC_VER_20
:
3550 case RTL_GIGA_MAC_VER_21
:
3551 case RTL_GIGA_MAC_VER_22
:
3552 case RTL_GIGA_MAC_VER_23
:
3553 case RTL_GIGA_MAC_VER_24
:
3554 case RTL_GIGA_MAC_VER_25
:
3555 case RTL_GIGA_MAC_VER_26
:
3556 case RTL_GIGA_MAC_VER_27
:
3557 case RTL_GIGA_MAC_VER_28
:
3558 case RTL_GIGA_MAC_VER_31
:
3559 rtl_writephy(tp
, 0x0e, 0x0000);
3564 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3567 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
3569 rtl_writephy(tp
, 0x1f, 0x0000);
3570 switch (tp
->mac_version
) {
3571 case RTL_GIGA_MAC_VER_32
:
3572 case RTL_GIGA_MAC_VER_33
:
3573 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
3576 case RTL_GIGA_MAC_VER_11
:
3577 case RTL_GIGA_MAC_VER_12
:
3578 case RTL_GIGA_MAC_VER_17
:
3579 case RTL_GIGA_MAC_VER_18
:
3580 case RTL_GIGA_MAC_VER_19
:
3581 case RTL_GIGA_MAC_VER_20
:
3582 case RTL_GIGA_MAC_VER_21
:
3583 case RTL_GIGA_MAC_VER_22
:
3584 case RTL_GIGA_MAC_VER_23
:
3585 case RTL_GIGA_MAC_VER_24
:
3586 case RTL_GIGA_MAC_VER_25
:
3587 case RTL_GIGA_MAC_VER_26
:
3588 case RTL_GIGA_MAC_VER_27
:
3589 case RTL_GIGA_MAC_VER_28
:
3590 case RTL_GIGA_MAC_VER_31
:
3591 rtl_writephy(tp
, 0x0e, 0x0200);
3593 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3598 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
3600 void __iomem
*ioaddr
= tp
->mmio_addr
;
3602 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3603 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3604 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
3605 r8168dp_check_dash(tp
)) {
3609 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
3610 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
3611 (RTL_R16(CPlusCmd
) & ASF
)) {
3615 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
3616 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
3617 rtl_ephy_write(ioaddr
, 0x19, 0xff64);
3619 if (rtl_wol_pll_power_down(tp
))
3622 r8168_phy_power_down(tp
);
3624 switch (tp
->mac_version
) {
3625 case RTL_GIGA_MAC_VER_25
:
3626 case RTL_GIGA_MAC_VER_26
:
3627 case RTL_GIGA_MAC_VER_27
:
3628 case RTL_GIGA_MAC_VER_28
:
3629 case RTL_GIGA_MAC_VER_31
:
3630 case RTL_GIGA_MAC_VER_32
:
3631 case RTL_GIGA_MAC_VER_33
:
3632 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
3637 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
3639 void __iomem
*ioaddr
= tp
->mmio_addr
;
3641 switch (tp
->mac_version
) {
3642 case RTL_GIGA_MAC_VER_25
:
3643 case RTL_GIGA_MAC_VER_26
:
3644 case RTL_GIGA_MAC_VER_27
:
3645 case RTL_GIGA_MAC_VER_28
:
3646 case RTL_GIGA_MAC_VER_31
:
3647 case RTL_GIGA_MAC_VER_32
:
3648 case RTL_GIGA_MAC_VER_33
:
3649 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
3653 r8168_phy_power_up(tp
);
3656 static void rtl_generic_op(struct rtl8169_private
*tp
,
3657 void (*op
)(struct rtl8169_private
*))
3663 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
3665 rtl_generic_op(tp
, tp
->pll_power_ops
.down
);
3668 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
3670 rtl_generic_op(tp
, tp
->pll_power_ops
.up
);
3673 static void __devinit
rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
3675 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
3677 switch (tp
->mac_version
) {
3678 case RTL_GIGA_MAC_VER_07
:
3679 case RTL_GIGA_MAC_VER_08
:
3680 case RTL_GIGA_MAC_VER_09
:
3681 case RTL_GIGA_MAC_VER_10
:
3682 case RTL_GIGA_MAC_VER_16
:
3683 case RTL_GIGA_MAC_VER_29
:
3684 case RTL_GIGA_MAC_VER_30
:
3685 ops
->down
= r810x_pll_power_down
;
3686 ops
->up
= r810x_pll_power_up
;
3689 case RTL_GIGA_MAC_VER_11
:
3690 case RTL_GIGA_MAC_VER_12
:
3691 case RTL_GIGA_MAC_VER_17
:
3692 case RTL_GIGA_MAC_VER_18
:
3693 case RTL_GIGA_MAC_VER_19
:
3694 case RTL_GIGA_MAC_VER_20
:
3695 case RTL_GIGA_MAC_VER_21
:
3696 case RTL_GIGA_MAC_VER_22
:
3697 case RTL_GIGA_MAC_VER_23
:
3698 case RTL_GIGA_MAC_VER_24
:
3699 case RTL_GIGA_MAC_VER_25
:
3700 case RTL_GIGA_MAC_VER_26
:
3701 case RTL_GIGA_MAC_VER_27
:
3702 case RTL_GIGA_MAC_VER_28
:
3703 case RTL_GIGA_MAC_VER_31
:
3704 case RTL_GIGA_MAC_VER_32
:
3705 case RTL_GIGA_MAC_VER_33
:
3706 case RTL_GIGA_MAC_VER_34
:
3707 case RTL_GIGA_MAC_VER_35
:
3708 case RTL_GIGA_MAC_VER_36
:
3709 ops
->down
= r8168_pll_power_down
;
3710 ops
->up
= r8168_pll_power_up
;
3720 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
3722 void __iomem
*ioaddr
= tp
->mmio_addr
;
3724 switch (tp
->mac_version
) {
3725 case RTL_GIGA_MAC_VER_01
:
3726 case RTL_GIGA_MAC_VER_02
:
3727 case RTL_GIGA_MAC_VER_03
:
3728 case RTL_GIGA_MAC_VER_04
:
3729 case RTL_GIGA_MAC_VER_05
:
3730 case RTL_GIGA_MAC_VER_06
:
3731 case RTL_GIGA_MAC_VER_10
:
3732 case RTL_GIGA_MAC_VER_11
:
3733 case RTL_GIGA_MAC_VER_12
:
3734 case RTL_GIGA_MAC_VER_13
:
3735 case RTL_GIGA_MAC_VER_14
:
3736 case RTL_GIGA_MAC_VER_15
:
3737 case RTL_GIGA_MAC_VER_16
:
3738 case RTL_GIGA_MAC_VER_17
:
3739 RTL_W32(RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
3741 case RTL_GIGA_MAC_VER_18
:
3742 case RTL_GIGA_MAC_VER_19
:
3743 case RTL_GIGA_MAC_VER_20
:
3744 case RTL_GIGA_MAC_VER_21
:
3745 case RTL_GIGA_MAC_VER_22
:
3746 case RTL_GIGA_MAC_VER_23
:
3747 case RTL_GIGA_MAC_VER_24
:
3748 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
3751 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
3756 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
3758 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
3761 static void rtl_hw_jumbo_enable(struct rtl8169_private
*tp
)
3763 void __iomem
*ioaddr
= tp
->mmio_addr
;
3765 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3766 rtl_generic_op(tp
, tp
->jumbo_ops
.enable
);
3767 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3770 static void rtl_hw_jumbo_disable(struct rtl8169_private
*tp
)
3772 void __iomem
*ioaddr
= tp
->mmio_addr
;
3774 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3775 rtl_generic_op(tp
, tp
->jumbo_ops
.disable
);
3776 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3779 static void r8168c_hw_jumbo_enable(struct rtl8169_private
*tp
)
3781 void __iomem
*ioaddr
= tp
->mmio_addr
;
3783 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
3784 RTL_W8(Config4
, RTL_R8(Config4
) | Jumbo_En1
);
3785 rtl_tx_performance_tweak(tp
->pci_dev
, 0x2 << MAX_READ_REQUEST_SHIFT
);
3788 static void r8168c_hw_jumbo_disable(struct rtl8169_private
*tp
)
3790 void __iomem
*ioaddr
= tp
->mmio_addr
;
3792 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
3793 RTL_W8(Config4
, RTL_R8(Config4
) & ~Jumbo_En1
);
3794 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3797 static void r8168dp_hw_jumbo_enable(struct rtl8169_private
*tp
)
3799 void __iomem
*ioaddr
= tp
->mmio_addr
;
3801 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
3804 static void r8168dp_hw_jumbo_disable(struct rtl8169_private
*tp
)
3806 void __iomem
*ioaddr
= tp
->mmio_addr
;
3808 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
3811 static void r8168e_hw_jumbo_enable(struct rtl8169_private
*tp
)
3813 void __iomem
*ioaddr
= tp
->mmio_addr
;
3815 RTL_W8(MaxTxPacketSize
, 0x3f);
3816 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
3817 RTL_W8(Config4
, RTL_R8(Config4
) | 0x01);
3818 rtl_tx_performance_tweak(tp
->pci_dev
, 0x2 << MAX_READ_REQUEST_SHIFT
);
3821 static void r8168e_hw_jumbo_disable(struct rtl8169_private
*tp
)
3823 void __iomem
*ioaddr
= tp
->mmio_addr
;
3825 RTL_W8(MaxTxPacketSize
, 0x0c);
3826 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
3827 RTL_W8(Config4
, RTL_R8(Config4
) & ~0x01);
3828 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3831 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private
*tp
)
3833 rtl_tx_performance_tweak(tp
->pci_dev
,
3834 (0x2 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3837 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private
*tp
)
3839 rtl_tx_performance_tweak(tp
->pci_dev
,
3840 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3843 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private
*tp
)
3845 void __iomem
*ioaddr
= tp
->mmio_addr
;
3847 r8168b_0_hw_jumbo_enable(tp
);
3849 RTL_W8(Config4
, RTL_R8(Config4
) | (1 << 0));
3852 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private
*tp
)
3854 void __iomem
*ioaddr
= tp
->mmio_addr
;
3856 r8168b_0_hw_jumbo_disable(tp
);
3858 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
3861 static void __devinit
rtl_init_jumbo_ops(struct rtl8169_private
*tp
)
3863 struct jumbo_ops
*ops
= &tp
->jumbo_ops
;
3865 switch (tp
->mac_version
) {
3866 case RTL_GIGA_MAC_VER_11
:
3867 ops
->disable
= r8168b_0_hw_jumbo_disable
;
3868 ops
->enable
= r8168b_0_hw_jumbo_enable
;
3870 case RTL_GIGA_MAC_VER_12
:
3871 case RTL_GIGA_MAC_VER_17
:
3872 ops
->disable
= r8168b_1_hw_jumbo_disable
;
3873 ops
->enable
= r8168b_1_hw_jumbo_enable
;
3875 case RTL_GIGA_MAC_VER_18
: /* Wild guess. Needs info from Realtek. */
3876 case RTL_GIGA_MAC_VER_19
:
3877 case RTL_GIGA_MAC_VER_20
:
3878 case RTL_GIGA_MAC_VER_21
: /* Wild guess. Needs info from Realtek. */
3879 case RTL_GIGA_MAC_VER_22
:
3880 case RTL_GIGA_MAC_VER_23
:
3881 case RTL_GIGA_MAC_VER_24
:
3882 case RTL_GIGA_MAC_VER_25
:
3883 case RTL_GIGA_MAC_VER_26
:
3884 ops
->disable
= r8168c_hw_jumbo_disable
;
3885 ops
->enable
= r8168c_hw_jumbo_enable
;
3887 case RTL_GIGA_MAC_VER_27
:
3888 case RTL_GIGA_MAC_VER_28
:
3889 ops
->disable
= r8168dp_hw_jumbo_disable
;
3890 ops
->enable
= r8168dp_hw_jumbo_enable
;
3892 case RTL_GIGA_MAC_VER_31
: /* Wild guess. Needs info from Realtek. */
3893 case RTL_GIGA_MAC_VER_32
:
3894 case RTL_GIGA_MAC_VER_33
:
3895 case RTL_GIGA_MAC_VER_34
:
3896 ops
->disable
= r8168e_hw_jumbo_disable
;
3897 ops
->enable
= r8168e_hw_jumbo_enable
;
3901 * No action needed for jumbo frames with 8169.
3902 * No jumbo for 810x at all.
3905 ops
->disable
= NULL
;
3911 static void rtl_hw_reset(struct rtl8169_private
*tp
)
3913 void __iomem
*ioaddr
= tp
->mmio_addr
;
3916 /* Soft reset the chip. */
3917 RTL_W8(ChipCmd
, CmdReset
);
3919 /* Check that the chip has finished the reset. */
3920 for (i
= 0; i
< 100; i
++) {
3921 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3927 static void rtl_request_uncached_firmware(struct rtl8169_private
*tp
)
3929 struct rtl_fw
*rtl_fw
;
3933 name
= rtl_lookup_firmware_name(tp
);
3935 goto out_no_firmware
;
3937 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
3941 rc
= request_firmware(&rtl_fw
->fw
, name
, &tp
->pci_dev
->dev
);
3945 rc
= rtl_check_firmware(tp
, rtl_fw
);
3947 goto err_release_firmware
;
3949 tp
->rtl_fw
= rtl_fw
;
3953 err_release_firmware
:
3954 release_firmware(rtl_fw
->fw
);
3958 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
3965 static void rtl_request_firmware(struct rtl8169_private
*tp
)
3967 if (IS_ERR(tp
->rtl_fw
))
3968 rtl_request_uncached_firmware(tp
);
3971 static void rtl_rx_close(struct rtl8169_private
*tp
)
3973 void __iomem
*ioaddr
= tp
->mmio_addr
;
3975 RTL_W32(RxConfig
, RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
3978 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
3980 void __iomem
*ioaddr
= tp
->mmio_addr
;
3982 /* Disable interrupts */
3983 rtl8169_irq_mask_and_ack(tp
);
3987 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
3988 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
3989 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
3990 while (RTL_R8(TxPoll
) & NPQ
)
3992 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
3993 tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
3994 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
3995 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
3996 while (!(RTL_R32(TxConfig
) & TXCFG_EMPTY
))
3999 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4006 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
4008 void __iomem
*ioaddr
= tp
->mmio_addr
;
4010 /* Set DMA burst size and Interframe Gap Time */
4011 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4012 (InterFrameGap
<< TxInterFrameGapShift
));
4015 static void rtl_hw_start(struct net_device
*dev
)
4017 struct rtl8169_private
*tp
= netdev_priv(dev
);
4021 rtl_irq_enable_all(tp
);
4024 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
4025 void __iomem
*ioaddr
)
4028 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4029 * register to be written before TxDescAddrLow to work.
4030 * Switching from MMIO to I/O access fixes the issue as well.
4032 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
4033 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
4034 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
4035 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
4038 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
4042 cmd
= RTL_R16(CPlusCmd
);
4043 RTL_W16(CPlusCmd
, cmd
);
4047 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
4049 /* Low hurts. Let's disable the filtering. */
4050 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
4053 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
4055 static const struct rtl_cfg2_info
{
4060 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
4061 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
4062 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
4063 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
4065 const struct rtl_cfg2_info
*p
= cfg2_info
;
4069 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
4070 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
4071 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
4072 RTL_W32(0x7c, p
->val
);
4078 static void rtl_set_rx_mode(struct net_device
*dev
)
4080 struct rtl8169_private
*tp
= netdev_priv(dev
);
4081 void __iomem
*ioaddr
= tp
->mmio_addr
;
4082 u32 mc_filter
[2]; /* Multicast hash filter */
4086 if (dev
->flags
& IFF_PROMISC
) {
4087 /* Unconditionally log net taps. */
4088 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
4090 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
4092 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4093 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
4094 (dev
->flags
& IFF_ALLMULTI
)) {
4095 /* Too many to filter perfectly -- accept all multicasts. */
4096 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
4097 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4099 struct netdev_hw_addr
*ha
;
4101 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
4102 mc_filter
[1] = mc_filter
[0] = 0;
4103 netdev_for_each_mc_addr(ha
, dev
) {
4104 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
4105 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
4106 rx_mode
|= AcceptMulticast
;
4110 if (dev
->features
& NETIF_F_RXALL
)
4111 rx_mode
|= (AcceptErr
| AcceptRunt
);
4113 tmp
= (RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
;
4115 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
4116 u32 data
= mc_filter
[0];
4118 mc_filter
[0] = swab32(mc_filter
[1]);
4119 mc_filter
[1] = swab32(data
);
4122 RTL_W32(MAR0
+ 4, mc_filter
[1]);
4123 RTL_W32(MAR0
+ 0, mc_filter
[0]);
4125 RTL_W32(RxConfig
, tmp
);
4128 static void rtl_hw_start_8169(struct net_device
*dev
)
4130 struct rtl8169_private
*tp
= netdev_priv(dev
);
4131 void __iomem
*ioaddr
= tp
->mmio_addr
;
4132 struct pci_dev
*pdev
= tp
->pci_dev
;
4134 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
4135 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
4136 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
4139 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4140 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4141 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4142 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4143 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4144 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4148 RTL_W8(EarlyTxThres
, NoEarlyTx
);
4150 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4152 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4153 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4154 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4155 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4156 rtl_set_rx_tx_config_registers(tp
);
4158 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
4160 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4161 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
4162 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4163 "Bit-3 and bit-14 MUST be 1\n");
4164 tp
->cp_cmd
|= (1 << 14);
4167 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4169 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
4172 * Undocumented corner. Supposedly:
4173 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4175 RTL_W16(IntrMitigate
, 0x0000);
4177 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4179 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
4180 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
4181 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
4182 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
4183 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4184 rtl_set_rx_tx_config_registers(tp
);
4187 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4189 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4192 RTL_W32(RxMissed
, 0);
4194 rtl_set_rx_mode(dev
);
4196 /* no early-rx interrupts */
4197 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4200 static void rtl_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
4202 if (tp
->csi_ops
.write
)
4203 tp
->csi_ops
.write(tp
->mmio_addr
, addr
, value
);
4206 static u32
rtl_csi_read(struct rtl8169_private
*tp
, int addr
)
4208 if (tp
->csi_ops
.read
)
4209 return tp
->csi_ops
.read(tp
->mmio_addr
, addr
);
4214 static void rtl_csi_access_enable(struct rtl8169_private
*tp
, u32 bits
)
4218 csi
= rtl_csi_read(tp
, 0x070c) & 0x00ffffff;
4219 rtl_csi_write(tp
, 0x070c, csi
| bits
);
4222 static void rtl_csi_access_enable_1(struct rtl8169_private
*tp
)
4224 rtl_csi_access_enable(tp
, 0x17000000);
4227 static void rtl_csi_access_enable_2(struct rtl8169_private
*tp
)
4229 rtl_csi_access_enable(tp
, 0x27000000);
4232 static void r8169_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
4236 RTL_W32(CSIDR
, value
);
4237 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
4238 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
4240 for (i
= 0; i
< 100; i
++) {
4241 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
4247 static u32
r8169_csi_read(void __iomem
*ioaddr
, int addr
)
4252 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
4253 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
4255 for (i
= 0; i
< 100; i
++) {
4256 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
4257 value
= RTL_R32(CSIDR
);
4266 static void __devinit
rtl_init_csi_ops(struct rtl8169_private
*tp
)
4268 struct csi_ops
*ops
= &tp
->csi_ops
;
4270 switch (tp
->mac_version
) {
4271 case RTL_GIGA_MAC_VER_01
:
4272 case RTL_GIGA_MAC_VER_02
:
4273 case RTL_GIGA_MAC_VER_03
:
4274 case RTL_GIGA_MAC_VER_04
:
4275 case RTL_GIGA_MAC_VER_05
:
4276 case RTL_GIGA_MAC_VER_06
:
4277 case RTL_GIGA_MAC_VER_10
:
4278 case RTL_GIGA_MAC_VER_11
:
4279 case RTL_GIGA_MAC_VER_12
:
4280 case RTL_GIGA_MAC_VER_13
:
4281 case RTL_GIGA_MAC_VER_14
:
4282 case RTL_GIGA_MAC_VER_15
:
4283 case RTL_GIGA_MAC_VER_16
:
4284 case RTL_GIGA_MAC_VER_17
:
4290 ops
->write
= r8169_csi_write
;
4291 ops
->read
= r8169_csi_read
;
4297 unsigned int offset
;
4302 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
4307 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
4308 rtl_ephy_write(ioaddr
, e
->offset
, w
);
4313 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
4315 int cap
= pci_pcie_cap(pdev
);
4320 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4321 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
4322 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4326 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
4328 int cap
= pci_pcie_cap(pdev
);
4333 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
4334 ctl
|= PCI_EXP_LNKCTL_CLKREQ_EN
;
4335 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
4339 #define R8168_CPCMD_QUIRK_MASK (\
4350 static void rtl_hw_start_8168bb(struct rtl8169_private
*tp
)
4352 void __iomem
*ioaddr
= tp
->mmio_addr
;
4353 struct pci_dev
*pdev
= tp
->pci_dev
;
4355 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4357 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4359 rtl_tx_performance_tweak(pdev
,
4360 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
4363 static void rtl_hw_start_8168bef(struct rtl8169_private
*tp
)
4365 void __iomem
*ioaddr
= tp
->mmio_addr
;
4367 rtl_hw_start_8168bb(tp
);
4369 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4371 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
4374 static void __rtl_hw_start_8168cp(struct rtl8169_private
*tp
)
4376 void __iomem
*ioaddr
= tp
->mmio_addr
;
4377 struct pci_dev
*pdev
= tp
->pci_dev
;
4379 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
4381 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4383 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4385 rtl_disable_clock_request(pdev
);
4387 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4390 static void rtl_hw_start_8168cp_1(struct rtl8169_private
*tp
)
4392 void __iomem
*ioaddr
= tp
->mmio_addr
;
4393 static const struct ephy_info e_info_8168cp
[] = {
4394 { 0x01, 0, 0x0001 },
4395 { 0x02, 0x0800, 0x1000 },
4396 { 0x03, 0, 0x0042 },
4397 { 0x06, 0x0080, 0x0000 },
4401 rtl_csi_access_enable_2(tp
);
4403 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
4405 __rtl_hw_start_8168cp(tp
);
4408 static void rtl_hw_start_8168cp_2(struct rtl8169_private
*tp
)
4410 void __iomem
*ioaddr
= tp
->mmio_addr
;
4411 struct pci_dev
*pdev
= tp
->pci_dev
;
4413 rtl_csi_access_enable_2(tp
);
4415 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4417 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4419 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4422 static void rtl_hw_start_8168cp_3(struct rtl8169_private
*tp
)
4424 void __iomem
*ioaddr
= tp
->mmio_addr
;
4425 struct pci_dev
*pdev
= tp
->pci_dev
;
4427 rtl_csi_access_enable_2(tp
);
4429 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4432 RTL_W8(DBG_REG
, 0x20);
4434 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4436 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4438 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4441 static void rtl_hw_start_8168c_1(struct rtl8169_private
*tp
)
4443 void __iomem
*ioaddr
= tp
->mmio_addr
;
4444 static const struct ephy_info e_info_8168c_1
[] = {
4445 { 0x02, 0x0800, 0x1000 },
4446 { 0x03, 0, 0x0002 },
4447 { 0x06, 0x0080, 0x0000 }
4450 rtl_csi_access_enable_2(tp
);
4452 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
4454 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
4456 __rtl_hw_start_8168cp(tp
);
4459 static void rtl_hw_start_8168c_2(struct rtl8169_private
*tp
)
4461 void __iomem
*ioaddr
= tp
->mmio_addr
;
4462 static const struct ephy_info e_info_8168c_2
[] = {
4463 { 0x01, 0, 0x0001 },
4464 { 0x03, 0x0400, 0x0220 }
4467 rtl_csi_access_enable_2(tp
);
4469 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
4471 __rtl_hw_start_8168cp(tp
);
4474 static void rtl_hw_start_8168c_3(struct rtl8169_private
*tp
)
4476 rtl_hw_start_8168c_2(tp
);
4479 static void rtl_hw_start_8168c_4(struct rtl8169_private
*tp
)
4481 rtl_csi_access_enable_2(tp
);
4483 __rtl_hw_start_8168cp(tp
);
4486 static void rtl_hw_start_8168d(struct rtl8169_private
*tp
)
4488 void __iomem
*ioaddr
= tp
->mmio_addr
;
4489 struct pci_dev
*pdev
= tp
->pci_dev
;
4491 rtl_csi_access_enable_2(tp
);
4493 rtl_disable_clock_request(pdev
);
4495 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4497 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4499 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4502 static void rtl_hw_start_8168dp(struct rtl8169_private
*tp
)
4504 void __iomem
*ioaddr
= tp
->mmio_addr
;
4505 struct pci_dev
*pdev
= tp
->pci_dev
;
4507 rtl_csi_access_enable_1(tp
);
4509 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4511 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4513 rtl_disable_clock_request(pdev
);
4516 static void rtl_hw_start_8168d_4(struct rtl8169_private
*tp
)
4518 void __iomem
*ioaddr
= tp
->mmio_addr
;
4519 struct pci_dev
*pdev
= tp
->pci_dev
;
4520 static const struct ephy_info e_info_8168d_4
[] = {
4522 { 0x19, 0x20, 0x50 },
4527 rtl_csi_access_enable_1(tp
);
4529 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4531 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4533 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
4534 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
4537 w
= rtl_ephy_read(ioaddr
, e
->offset
);
4538 rtl_ephy_write(ioaddr
, 0x03, (w
& e
->mask
) | e
->bits
);
4541 rtl_enable_clock_request(pdev
);
4544 static void rtl_hw_start_8168e_1(struct rtl8169_private
*tp
)
4546 void __iomem
*ioaddr
= tp
->mmio_addr
;
4547 struct pci_dev
*pdev
= tp
->pci_dev
;
4548 static const struct ephy_info e_info_8168e_1
[] = {
4549 { 0x00, 0x0200, 0x0100 },
4550 { 0x00, 0x0000, 0x0004 },
4551 { 0x06, 0x0002, 0x0001 },
4552 { 0x06, 0x0000, 0x0030 },
4553 { 0x07, 0x0000, 0x2000 },
4554 { 0x00, 0x0000, 0x0020 },
4555 { 0x03, 0x5800, 0x2000 },
4556 { 0x03, 0x0000, 0x0001 },
4557 { 0x01, 0x0800, 0x1000 },
4558 { 0x07, 0x0000, 0x4000 },
4559 { 0x1e, 0x0000, 0x2000 },
4560 { 0x19, 0xffff, 0xfe6c },
4561 { 0x0a, 0x0000, 0x0040 }
4564 rtl_csi_access_enable_2(tp
);
4566 rtl_ephy_init(ioaddr
, e_info_8168e_1
, ARRAY_SIZE(e_info_8168e_1
));
4568 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4570 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4572 rtl_disable_clock_request(pdev
);
4574 /* Reset tx FIFO pointer */
4575 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
4576 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
4578 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4581 static void rtl_hw_start_8168e_2(struct rtl8169_private
*tp
)
4583 void __iomem
*ioaddr
= tp
->mmio_addr
;
4584 struct pci_dev
*pdev
= tp
->pci_dev
;
4585 static const struct ephy_info e_info_8168e_2
[] = {
4586 { 0x09, 0x0000, 0x0080 },
4587 { 0x19, 0x0000, 0x0224 }
4590 rtl_csi_access_enable_1(tp
);
4592 rtl_ephy_init(ioaddr
, e_info_8168e_2
, ARRAY_SIZE(e_info_8168e_2
));
4594 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4596 rtl_eri_write(ioaddr
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4597 rtl_eri_write(ioaddr
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4598 rtl_eri_write(ioaddr
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
4599 rtl_eri_write(ioaddr
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
4600 rtl_eri_write(ioaddr
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
4601 rtl_eri_write(ioaddr
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060, ERIAR_EXGMAC
);
4602 rtl_w1w0_eri(ioaddr
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4603 rtl_w1w0_eri(ioaddr
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00,
4606 RTL_W8(MaxTxPacketSize
, EarlySize
);
4608 rtl_disable_clock_request(pdev
);
4610 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
4611 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
4613 /* Adjust EEE LED frequency */
4614 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
4616 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4617 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
4618 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4621 static void rtl_hw_start_8168f_1(struct rtl8169_private
*tp
)
4623 void __iomem
*ioaddr
= tp
->mmio_addr
;
4624 struct pci_dev
*pdev
= tp
->pci_dev
;
4625 static const struct ephy_info e_info_8168f_1
[] = {
4626 { 0x06, 0x00c0, 0x0020 },
4627 { 0x08, 0x0001, 0x0002 },
4628 { 0x09, 0x0000, 0x0080 },
4629 { 0x19, 0x0000, 0x0224 }
4632 rtl_csi_access_enable_1(tp
);
4634 rtl_ephy_init(ioaddr
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
4636 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4638 rtl_eri_write(ioaddr
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4639 rtl_eri_write(ioaddr
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
4640 rtl_eri_write(ioaddr
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
4641 rtl_eri_write(ioaddr
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
4642 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
4643 rtl_w1w0_eri(ioaddr
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
4644 rtl_w1w0_eri(ioaddr
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4645 rtl_w1w0_eri(ioaddr
, 0x1d0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
4646 rtl_eri_write(ioaddr
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
4647 rtl_eri_write(ioaddr
, 0xd0, ERIAR_MASK_1111
, 0x00000060, ERIAR_EXGMAC
);
4648 rtl_w1w0_eri(ioaddr
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00,
4651 RTL_W8(MaxTxPacketSize
, EarlySize
);
4653 rtl_disable_clock_request(pdev
);
4655 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
4656 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
4658 /* Adjust EEE LED frequency */
4659 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
4661 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4662 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
4663 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
4666 static void rtl_hw_start_8168(struct net_device
*dev
)
4668 struct rtl8169_private
*tp
= netdev_priv(dev
);
4669 void __iomem
*ioaddr
= tp
->mmio_addr
;
4671 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4673 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4675 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4677 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
4679 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4681 RTL_W16(IntrMitigate
, 0x5151);
4683 /* Work around for RxFIFO overflow. */
4684 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
4685 tp
->event_slow
|= RxFIFOOver
| PCSTimeout
;
4686 tp
->event_slow
&= ~RxOverflow
;
4689 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4691 rtl_set_rx_mode(dev
);
4693 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4694 (InterFrameGap
<< TxInterFrameGapShift
));
4698 switch (tp
->mac_version
) {
4699 case RTL_GIGA_MAC_VER_11
:
4700 rtl_hw_start_8168bb(tp
);
4703 case RTL_GIGA_MAC_VER_12
:
4704 case RTL_GIGA_MAC_VER_17
:
4705 rtl_hw_start_8168bef(tp
);
4708 case RTL_GIGA_MAC_VER_18
:
4709 rtl_hw_start_8168cp_1(tp
);
4712 case RTL_GIGA_MAC_VER_19
:
4713 rtl_hw_start_8168c_1(tp
);
4716 case RTL_GIGA_MAC_VER_20
:
4717 rtl_hw_start_8168c_2(tp
);
4720 case RTL_GIGA_MAC_VER_21
:
4721 rtl_hw_start_8168c_3(tp
);
4724 case RTL_GIGA_MAC_VER_22
:
4725 rtl_hw_start_8168c_4(tp
);
4728 case RTL_GIGA_MAC_VER_23
:
4729 rtl_hw_start_8168cp_2(tp
);
4732 case RTL_GIGA_MAC_VER_24
:
4733 rtl_hw_start_8168cp_3(tp
);
4736 case RTL_GIGA_MAC_VER_25
:
4737 case RTL_GIGA_MAC_VER_26
:
4738 case RTL_GIGA_MAC_VER_27
:
4739 rtl_hw_start_8168d(tp
);
4742 case RTL_GIGA_MAC_VER_28
:
4743 rtl_hw_start_8168d_4(tp
);
4746 case RTL_GIGA_MAC_VER_31
:
4747 rtl_hw_start_8168dp(tp
);
4750 case RTL_GIGA_MAC_VER_32
:
4751 case RTL_GIGA_MAC_VER_33
:
4752 rtl_hw_start_8168e_1(tp
);
4754 case RTL_GIGA_MAC_VER_34
:
4755 rtl_hw_start_8168e_2(tp
);
4758 case RTL_GIGA_MAC_VER_35
:
4759 case RTL_GIGA_MAC_VER_36
:
4760 rtl_hw_start_8168f_1(tp
);
4764 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
4765 dev
->name
, tp
->mac_version
);
4769 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4771 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4773 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4776 #define R810X_CPCMD_QUIRK_MASK (\
4787 static void rtl_hw_start_8102e_1(struct rtl8169_private
*tp
)
4789 void __iomem
*ioaddr
= tp
->mmio_addr
;
4790 struct pci_dev
*pdev
= tp
->pci_dev
;
4791 static const struct ephy_info e_info_8102e_1
[] = {
4792 { 0x01, 0, 0x6e65 },
4793 { 0x02, 0, 0x091f },
4794 { 0x03, 0, 0xc2f9 },
4795 { 0x06, 0, 0xafb5 },
4796 { 0x07, 0, 0x0e00 },
4797 { 0x19, 0, 0xec80 },
4798 { 0x01, 0, 0x2e65 },
4803 rtl_csi_access_enable_2(tp
);
4805 RTL_W8(DBG_REG
, FIX_NAK_1
);
4807 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4810 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
4811 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4813 cfg1
= RTL_R8(Config1
);
4814 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
4815 RTL_W8(Config1
, cfg1
& ~LEDS0
);
4817 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
4820 static void rtl_hw_start_8102e_2(struct rtl8169_private
*tp
)
4822 void __iomem
*ioaddr
= tp
->mmio_addr
;
4823 struct pci_dev
*pdev
= tp
->pci_dev
;
4825 rtl_csi_access_enable_2(tp
);
4827 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4829 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
4830 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4833 static void rtl_hw_start_8102e_3(struct rtl8169_private
*tp
)
4835 rtl_hw_start_8102e_2(tp
);
4837 rtl_ephy_write(tp
->mmio_addr
, 0x03, 0xc2f9);
4840 static void rtl_hw_start_8105e_1(struct rtl8169_private
*tp
)
4842 void __iomem
*ioaddr
= tp
->mmio_addr
;
4843 static const struct ephy_info e_info_8105e_1
[] = {
4844 { 0x07, 0, 0x4000 },
4845 { 0x19, 0, 0x0200 },
4846 { 0x19, 0, 0x0020 },
4847 { 0x1e, 0, 0x2000 },
4848 { 0x03, 0, 0x0001 },
4849 { 0x19, 0, 0x0100 },
4850 { 0x19, 0, 0x0004 },
4854 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4855 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
4857 /* Disable Early Tally Counter */
4858 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
4860 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
4861 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
4863 rtl_ephy_init(ioaddr
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
4866 static void rtl_hw_start_8105e_2(struct rtl8169_private
*tp
)
4868 void __iomem
*ioaddr
= tp
->mmio_addr
;
4870 rtl_hw_start_8105e_1(tp
);
4871 rtl_ephy_write(ioaddr
, 0x1e, rtl_ephy_read(ioaddr
, 0x1e) | 0x8000);
4874 static void rtl_hw_start_8101(struct net_device
*dev
)
4876 struct rtl8169_private
*tp
= netdev_priv(dev
);
4877 void __iomem
*ioaddr
= tp
->mmio_addr
;
4878 struct pci_dev
*pdev
= tp
->pci_dev
;
4880 if (tp
->mac_version
>= RTL_GIGA_MAC_VER_30
)
4881 tp
->event_slow
&= ~RxFIFOOver
;
4883 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
4884 tp
->mac_version
== RTL_GIGA_MAC_VER_16
) {
4885 int cap
= pci_pcie_cap(pdev
);
4888 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
4889 PCI_EXP_DEVCTL_NOSNOOP_EN
);
4893 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4895 switch (tp
->mac_version
) {
4896 case RTL_GIGA_MAC_VER_07
:
4897 rtl_hw_start_8102e_1(tp
);
4900 case RTL_GIGA_MAC_VER_08
:
4901 rtl_hw_start_8102e_3(tp
);
4904 case RTL_GIGA_MAC_VER_09
:
4905 rtl_hw_start_8102e_2(tp
);
4908 case RTL_GIGA_MAC_VER_29
:
4909 rtl_hw_start_8105e_1(tp
);
4911 case RTL_GIGA_MAC_VER_30
:
4912 rtl_hw_start_8105e_2(tp
);
4916 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4918 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4920 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4922 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
4923 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4925 RTL_W16(IntrMitigate
, 0x0000);
4927 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4929 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4930 rtl_set_rx_tx_config_registers(tp
);
4934 rtl_set_rx_mode(dev
);
4936 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
4939 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
4941 struct rtl8169_private
*tp
= netdev_priv(dev
);
4943 if (new_mtu
< ETH_ZLEN
||
4944 new_mtu
> rtl_chip_infos
[tp
->mac_version
].jumbo_max
)
4947 if (new_mtu
> ETH_DATA_LEN
)
4948 rtl_hw_jumbo_enable(tp
);
4950 rtl_hw_jumbo_disable(tp
);
4953 netdev_update_features(dev
);
4958 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
4960 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
4961 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
4964 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
4965 void **data_buff
, struct RxDesc
*desc
)
4967 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
4972 rtl8169_make_unusable_by_asic(desc
);
4975 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
4977 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
4979 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
4982 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
4985 desc
->addr
= cpu_to_le64(mapping
);
4987 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
4990 static inline void *rtl8169_align(void *data
)
4992 return (void *)ALIGN((long)data
, 16);
4995 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
4996 struct RxDesc
*desc
)
5000 struct device
*d
= &tp
->pci_dev
->dev
;
5001 struct net_device
*dev
= tp
->dev
;
5002 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
5004 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
5008 if (rtl8169_align(data
) != data
) {
5010 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
5015 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
5017 if (unlikely(dma_mapping_error(d
, mapping
))) {
5018 if (net_ratelimit())
5019 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
5023 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
5031 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
5035 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5036 if (tp
->Rx_databuff
[i
]) {
5037 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
5038 tp
->RxDescArray
+ i
);
5043 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
5045 desc
->opts1
|= cpu_to_le32(RingEnd
);
5048 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
5052 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5055 if (tp
->Rx_databuff
[i
])
5058 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
5060 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
5063 tp
->Rx_databuff
[i
] = data
;
5066 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
5070 rtl8169_rx_clear(tp
);
5074 static int rtl8169_init_ring(struct net_device
*dev
)
5076 struct rtl8169_private
*tp
= netdev_priv(dev
);
5078 rtl8169_init_ring_indexes(tp
);
5080 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
5081 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
5083 return rtl8169_rx_fill(tp
);
5086 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
5087 struct TxDesc
*desc
)
5089 unsigned int len
= tx_skb
->len
;
5091 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
5099 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
5104 for (i
= 0; i
< n
; i
++) {
5105 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
5106 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5107 unsigned int len
= tx_skb
->len
;
5110 struct sk_buff
*skb
= tx_skb
->skb
;
5112 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
5113 tp
->TxDescArray
+ entry
);
5115 tp
->dev
->stats
.tx_dropped
++;
5123 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
5125 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
5126 tp
->cur_tx
= tp
->dirty_tx
= 0;
5127 netdev_reset_queue(tp
->dev
);
5130 static void rtl_reset_work(struct rtl8169_private
*tp
)
5132 struct net_device
*dev
= tp
->dev
;
5135 napi_disable(&tp
->napi
);
5136 netif_stop_queue(dev
);
5137 synchronize_sched();
5139 rtl8169_hw_reset(tp
);
5141 for (i
= 0; i
< NUM_RX_DESC
; i
++)
5142 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
5144 rtl8169_tx_clear(tp
);
5145 rtl8169_init_ring_indexes(tp
);
5147 napi_enable(&tp
->napi
);
5149 netif_wake_queue(dev
);
5150 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
5153 static void rtl8169_tx_timeout(struct net_device
*dev
)
5155 struct rtl8169_private
*tp
= netdev_priv(dev
);
5157 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
5160 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
5163 struct skb_shared_info
*info
= skb_shinfo(skb
);
5164 unsigned int cur_frag
, entry
;
5165 struct TxDesc
* uninitialized_var(txd
);
5166 struct device
*d
= &tp
->pci_dev
->dev
;
5169 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
5170 const skb_frag_t
*frag
= info
->frags
+ cur_frag
;
5175 entry
= (entry
+ 1) % NUM_TX_DESC
;
5177 txd
= tp
->TxDescArray
+ entry
;
5178 len
= skb_frag_size(frag
);
5179 addr
= skb_frag_address(frag
);
5180 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
5181 if (unlikely(dma_mapping_error(d
, mapping
))) {
5182 if (net_ratelimit())
5183 netif_err(tp
, drv
, tp
->dev
,
5184 "Failed to map TX fragments DMA!\n");
5188 /* Anti gcc 2.95.3 bugware (sic) */
5189 status
= opts
[0] | len
|
5190 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5192 txd
->opts1
= cpu_to_le32(status
);
5193 txd
->opts2
= cpu_to_le32(opts
[1]);
5194 txd
->addr
= cpu_to_le64(mapping
);
5196 tp
->tx_skb
[entry
].len
= len
;
5200 tp
->tx_skb
[entry
].skb
= skb
;
5201 txd
->opts1
|= cpu_to_le32(LastFrag
);
5207 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
5211 static inline void rtl8169_tso_csum(struct rtl8169_private
*tp
,
5212 struct sk_buff
*skb
, u32
*opts
)
5214 const struct rtl_tx_desc_info
*info
= tx_desc_info
+ tp
->txd_version
;
5215 u32 mss
= skb_shinfo(skb
)->gso_size
;
5216 int offset
= info
->opts_offset
;
5220 opts
[offset
] |= min(mss
, TD_MSS_MAX
) << info
->mss_shift
;
5221 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5222 const struct iphdr
*ip
= ip_hdr(skb
);
5224 if (ip
->protocol
== IPPROTO_TCP
)
5225 opts
[offset
] |= info
->checksum
.tcp
;
5226 else if (ip
->protocol
== IPPROTO_UDP
)
5227 opts
[offset
] |= info
->checksum
.udp
;
5233 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
5234 struct net_device
*dev
)
5236 struct rtl8169_private
*tp
= netdev_priv(dev
);
5237 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
5238 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
5239 void __iomem
*ioaddr
= tp
->mmio_addr
;
5240 struct device
*d
= &tp
->pci_dev
->dev
;
5246 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
5247 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
5251 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
5254 len
= skb_headlen(skb
);
5255 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
5256 if (unlikely(dma_mapping_error(d
, mapping
))) {
5257 if (net_ratelimit())
5258 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
5262 tp
->tx_skb
[entry
].len
= len
;
5263 txd
->addr
= cpu_to_le64(mapping
);
5265 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
5268 rtl8169_tso_csum(tp
, skb
, opts
);
5270 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
5274 opts
[0] |= FirstFrag
;
5276 opts
[0] |= FirstFrag
| LastFrag
;
5277 tp
->tx_skb
[entry
].skb
= skb
;
5280 txd
->opts2
= cpu_to_le32(opts
[1]);
5282 netdev_sent_queue(dev
, skb
->len
);
5284 skb_tx_timestamp(skb
);
5288 /* Anti gcc 2.95.3 bugware (sic) */
5289 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5290 txd
->opts1
= cpu_to_le32(status
);
5292 tp
->cur_tx
+= frags
+ 1;
5296 RTL_W8(TxPoll
, NPQ
);
5300 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
5301 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
5302 * not miss a ring update when it notices a stopped queue.
5305 netif_stop_queue(dev
);
5306 /* Sync with rtl_tx:
5307 * - publish queue status and cur_tx ring index (write barrier)
5308 * - refresh dirty_tx ring index (read barrier).
5309 * May the current thread have a pessimistic view of the ring
5310 * status and forget to wake up queue, a racing rtl_tx thread
5314 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
5315 netif_wake_queue(dev
);
5318 return NETDEV_TX_OK
;
5321 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
5324 dev
->stats
.tx_dropped
++;
5325 return NETDEV_TX_OK
;
5328 netif_stop_queue(dev
);
5329 dev
->stats
.tx_dropped
++;
5330 return NETDEV_TX_BUSY
;
5333 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
5335 struct rtl8169_private
*tp
= netdev_priv(dev
);
5336 struct pci_dev
*pdev
= tp
->pci_dev
;
5337 u16 pci_status
, pci_cmd
;
5339 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
5340 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
5342 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5343 pci_cmd
, pci_status
);
5346 * The recovery sequence below admits a very elaborated explanation:
5347 * - it seems to work;
5348 * - I did not see what else could be done;
5349 * - it makes iop3xx happy.
5351 * Feel free to adjust to your needs.
5353 if (pdev
->broken_parity_status
)
5354 pci_cmd
&= ~PCI_COMMAND_PARITY
;
5356 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
5358 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
5360 pci_write_config_word(pdev
, PCI_STATUS
,
5361 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
5362 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
5363 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
5365 /* The infamous DAC f*ckup only happens at boot time */
5366 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
5367 void __iomem
*ioaddr
= tp
->mmio_addr
;
5369 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
5370 tp
->cp_cmd
&= ~PCIDAC
;
5371 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5372 dev
->features
&= ~NETIF_F_HIGHDMA
;
5375 rtl8169_hw_reset(tp
);
5377 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
5385 static void rtl_tx(struct net_device
*dev
, struct rtl8169_private
*tp
)
5387 struct rtl8169_stats
*tx_stats
= &tp
->tx_stats
;
5388 unsigned int dirty_tx
, tx_left
;
5389 struct rtl_txc txc
= { 0, 0 };
5391 dirty_tx
= tp
->dirty_tx
;
5393 tx_left
= tp
->cur_tx
- dirty_tx
;
5395 while (tx_left
> 0) {
5396 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
5397 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5401 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
5402 if (status
& DescOwn
)
5405 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
5406 tp
->TxDescArray
+ entry
);
5407 if (status
& LastFrag
) {
5408 struct sk_buff
*skb
= tx_skb
->skb
;
5411 txc
.bytes
+= skb
->len
;
5419 u64_stats_update_begin(&tx_stats
->syncp
);
5420 tx_stats
->packets
+= txc
.packets
;
5421 tx_stats
->bytes
+= txc
.bytes
;
5422 u64_stats_update_end(&tx_stats
->syncp
);
5424 netdev_completed_queue(dev
, txc
.packets
, txc
.bytes
);
5426 if (tp
->dirty_tx
!= dirty_tx
) {
5427 tp
->dirty_tx
= dirty_tx
;
5428 /* Sync with rtl8169_start_xmit:
5429 * - publish dirty_tx ring index (write barrier)
5430 * - refresh cur_tx ring index and queue status (read barrier)
5431 * May the current thread miss the stopped queue condition,
5432 * a racing xmit thread can only have a right view of the
5436 if (netif_queue_stopped(dev
) &&
5437 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
5438 netif_wake_queue(dev
);
5441 * 8168 hack: TxPoll requests are lost when the Tx packets are
5442 * too close. Let's kick an extra TxPoll request when a burst
5443 * of start_xmit activity is detected (if it is not detected,
5444 * it is slow enough). -- FR
5446 if (tp
->cur_tx
!= dirty_tx
) {
5447 void __iomem
*ioaddr
= tp
->mmio_addr
;
5449 RTL_W8(TxPoll
, NPQ
);
5454 static inline int rtl8169_fragmented_frame(u32 status
)
5456 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
5459 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
5461 u32 status
= opts1
& RxProtoMask
;
5463 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
5464 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
5465 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
5467 skb_checksum_none_assert(skb
);
5470 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
5471 struct rtl8169_private
*tp
,
5475 struct sk_buff
*skb
;
5476 struct device
*d
= &tp
->pci_dev
->dev
;
5478 data
= rtl8169_align(data
);
5479 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5481 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
5483 memcpy(skb
->data
, data
, pkt_size
);
5484 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
5489 static int rtl_rx(struct net_device
*dev
, struct rtl8169_private
*tp
, u32 budget
)
5491 unsigned int cur_rx
, rx_left
;
5494 cur_rx
= tp
->cur_rx
;
5495 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
5496 rx_left
= min(rx_left
, budget
);
5498 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
5499 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
5500 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
5504 status
= le32_to_cpu(desc
->opts1
) & tp
->opts1_mask
;
5506 if (status
& DescOwn
)
5508 if (unlikely(status
& RxRES
)) {
5509 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
5511 dev
->stats
.rx_errors
++;
5512 if (status
& (RxRWT
| RxRUNT
))
5513 dev
->stats
.rx_length_errors
++;
5515 dev
->stats
.rx_crc_errors
++;
5516 if (status
& RxFOVF
) {
5517 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
5518 dev
->stats
.rx_fifo_errors
++;
5520 if ((status
& (RxRUNT
| RxCRC
)) &&
5521 !(status
& (RxRWT
| RxFOVF
)) &&
5522 (dev
->features
& NETIF_F_RXALL
))
5525 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5527 struct sk_buff
*skb
;
5532 addr
= le64_to_cpu(desc
->addr
);
5533 if (likely(!(dev
->features
& NETIF_F_RXFCS
)))
5534 pkt_size
= (status
& 0x00003fff) - 4;
5536 pkt_size
= status
& 0x00003fff;
5539 * The driver does not support incoming fragmented
5540 * frames. They are seen as a symptom of over-mtu
5543 if (unlikely(rtl8169_fragmented_frame(status
))) {
5544 dev
->stats
.rx_dropped
++;
5545 dev
->stats
.rx_length_errors
++;
5546 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5550 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
5551 tp
, pkt_size
, addr
);
5552 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5554 dev
->stats
.rx_dropped
++;
5558 rtl8169_rx_csum(skb
, status
);
5559 skb_put(skb
, pkt_size
);
5560 skb
->protocol
= eth_type_trans(skb
, dev
);
5562 rtl8169_rx_vlan_tag(desc
, skb
);
5564 napi_gro_receive(&tp
->napi
, skb
);
5566 u64_stats_update_begin(&tp
->rx_stats
.syncp
);
5567 tp
->rx_stats
.packets
++;
5568 tp
->rx_stats
.bytes
+= pkt_size
;
5569 u64_stats_update_end(&tp
->rx_stats
.syncp
);
5572 /* Work around for AMD plateform. */
5573 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
5574 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
5580 count
= cur_rx
- tp
->cur_rx
;
5581 tp
->cur_rx
= cur_rx
;
5583 tp
->dirty_rx
+= count
;
5588 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
5590 struct net_device
*dev
= dev_instance
;
5591 struct rtl8169_private
*tp
= netdev_priv(dev
);
5595 status
= rtl_get_events(tp
);
5596 if (status
&& status
!= 0xffff) {
5597 status
&= RTL_EVENT_NAPI
| tp
->event_slow
;
5601 rtl_irq_disable(tp
);
5602 napi_schedule(&tp
->napi
);
5605 return IRQ_RETVAL(handled
);
5609 * Workqueue context.
5611 static void rtl_slow_event_work(struct rtl8169_private
*tp
)
5613 struct net_device
*dev
= tp
->dev
;
5616 status
= rtl_get_events(tp
) & tp
->event_slow
;
5617 rtl_ack_events(tp
, status
);
5619 if (unlikely(status
& RxFIFOOver
)) {
5620 switch (tp
->mac_version
) {
5621 /* Work around for rx fifo overflow */
5622 case RTL_GIGA_MAC_VER_11
:
5623 netif_stop_queue(dev
);
5624 /* XXX - Hack alert. See rtl_task(). */
5625 set_bit(RTL_FLAG_TASK_RESET_PENDING
, tp
->wk
.flags
);
5631 if (unlikely(status
& SYSErr
))
5632 rtl8169_pcierr_interrupt(dev
);
5634 if (status
& LinkChg
)
5635 __rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
, true);
5637 napi_disable(&tp
->napi
);
5638 rtl_irq_disable(tp
);
5640 napi_enable(&tp
->napi
);
5641 napi_schedule(&tp
->napi
);
5644 static void rtl_task(struct work_struct
*work
)
5646 static const struct {
5648 void (*action
)(struct rtl8169_private
*);
5650 /* XXX - keep rtl_slow_event_work() as first element. */
5651 { RTL_FLAG_TASK_SLOW_PENDING
, rtl_slow_event_work
},
5652 { RTL_FLAG_TASK_RESET_PENDING
, rtl_reset_work
},
5653 { RTL_FLAG_TASK_PHY_PENDING
, rtl_phy_work
}
5655 struct rtl8169_private
*tp
=
5656 container_of(work
, struct rtl8169_private
, wk
.work
);
5657 struct net_device
*dev
= tp
->dev
;
5662 if (!netif_running(dev
) ||
5663 !test_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
))
5666 for (i
= 0; i
< ARRAY_SIZE(rtl_work
); i
++) {
5669 pending
= test_and_clear_bit(rtl_work
[i
].bitnr
, tp
->wk
.flags
);
5671 rtl_work
[i
].action(tp
);
5675 rtl_unlock_work(tp
);
5678 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
5680 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
5681 struct net_device
*dev
= tp
->dev
;
5682 u16 enable_mask
= RTL_EVENT_NAPI
| tp
->event_slow
;
5686 status
= rtl_get_events(tp
);
5687 rtl_ack_events(tp
, status
& ~tp
->event_slow
);
5689 if (status
& RTL_EVENT_NAPI_RX
)
5690 work_done
= rtl_rx(dev
, tp
, (u32
) budget
);
5692 if (status
& RTL_EVENT_NAPI_TX
)
5695 if (status
& tp
->event_slow
) {
5696 enable_mask
&= ~tp
->event_slow
;
5698 rtl_schedule_task(tp
, RTL_FLAG_TASK_SLOW_PENDING
);
5701 if (work_done
< budget
) {
5702 napi_complete(napi
);
5704 rtl_irq_enable(tp
, enable_mask
);
5711 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
5713 struct rtl8169_private
*tp
= netdev_priv(dev
);
5715 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
5718 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
5719 RTL_W32(RxMissed
, 0);
5722 static void rtl8169_down(struct net_device
*dev
)
5724 struct rtl8169_private
*tp
= netdev_priv(dev
);
5725 void __iomem
*ioaddr
= tp
->mmio_addr
;
5727 del_timer_sync(&tp
->timer
);
5729 napi_disable(&tp
->napi
);
5730 netif_stop_queue(dev
);
5732 rtl8169_hw_reset(tp
);
5734 * At this point device interrupts can not be enabled in any function,
5735 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
5736 * and napi is disabled (rtl8169_poll).
5738 rtl8169_rx_missed(dev
, ioaddr
);
5740 /* Give a racing hard_start_xmit a few cycles to complete. */
5741 synchronize_sched();
5743 rtl8169_tx_clear(tp
);
5745 rtl8169_rx_clear(tp
);
5747 rtl_pll_power_down(tp
);
5750 static int rtl8169_close(struct net_device
*dev
)
5752 struct rtl8169_private
*tp
= netdev_priv(dev
);
5753 struct pci_dev
*pdev
= tp
->pci_dev
;
5755 pm_runtime_get_sync(&pdev
->dev
);
5757 /* Update counters before going down */
5758 rtl8169_update_counters(dev
);
5761 clear_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
5764 rtl_unlock_work(tp
);
5766 free_irq(pdev
->irq
, dev
);
5768 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
5770 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
5772 tp
->TxDescArray
= NULL
;
5773 tp
->RxDescArray
= NULL
;
5775 pm_runtime_put_sync(&pdev
->dev
);
5780 #ifdef CONFIG_NET_POLL_CONTROLLER
5781 static void rtl8169_netpoll(struct net_device
*dev
)
5783 struct rtl8169_private
*tp
= netdev_priv(dev
);
5785 rtl8169_interrupt(tp
->pci_dev
->irq
, dev
);
5789 static int rtl_open(struct net_device
*dev
)
5791 struct rtl8169_private
*tp
= netdev_priv(dev
);
5792 void __iomem
*ioaddr
= tp
->mmio_addr
;
5793 struct pci_dev
*pdev
= tp
->pci_dev
;
5794 int retval
= -ENOMEM
;
5796 pm_runtime_get_sync(&pdev
->dev
);
5799 * Rx and Tx desscriptors needs 256 bytes alignment.
5800 * dma_alloc_coherent provides more.
5802 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
5803 &tp
->TxPhyAddr
, GFP_KERNEL
);
5804 if (!tp
->TxDescArray
)
5805 goto err_pm_runtime_put
;
5807 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
5808 &tp
->RxPhyAddr
, GFP_KERNEL
);
5809 if (!tp
->RxDescArray
)
5812 retval
= rtl8169_init_ring(dev
);
5816 INIT_WORK(&tp
->wk
.work
, rtl_task
);
5820 rtl_request_firmware(tp
);
5822 retval
= request_irq(pdev
->irq
, rtl8169_interrupt
,
5823 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
5826 goto err_release_fw_2
;
5830 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
5832 napi_enable(&tp
->napi
);
5834 rtl8169_init_phy(dev
, tp
);
5836 __rtl8169_set_features(dev
, dev
->features
);
5838 rtl_pll_power_up(tp
);
5842 netif_start_queue(dev
);
5844 rtl_unlock_work(tp
);
5846 tp
->saved_wolopts
= 0;
5847 pm_runtime_put_noidle(&pdev
->dev
);
5849 rtl8169_check_link_status(dev
, tp
, ioaddr
);
5854 rtl_release_firmware(tp
);
5855 rtl8169_rx_clear(tp
);
5857 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
5859 tp
->RxDescArray
= NULL
;
5861 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
5863 tp
->TxDescArray
= NULL
;
5865 pm_runtime_put_noidle(&pdev
->dev
);
5869 static struct rtnl_link_stats64
*
5870 rtl8169_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
5872 struct rtl8169_private
*tp
= netdev_priv(dev
);
5873 void __iomem
*ioaddr
= tp
->mmio_addr
;
5876 if (netif_running(dev
))
5877 rtl8169_rx_missed(dev
, ioaddr
);
5880 start
= u64_stats_fetch_begin_bh(&tp
->rx_stats
.syncp
);
5881 stats
->rx_packets
= tp
->rx_stats
.packets
;
5882 stats
->rx_bytes
= tp
->rx_stats
.bytes
;
5883 } while (u64_stats_fetch_retry_bh(&tp
->rx_stats
.syncp
, start
));
5887 start
= u64_stats_fetch_begin_bh(&tp
->tx_stats
.syncp
);
5888 stats
->tx_packets
= tp
->tx_stats
.packets
;
5889 stats
->tx_bytes
= tp
->tx_stats
.bytes
;
5890 } while (u64_stats_fetch_retry_bh(&tp
->tx_stats
.syncp
, start
));
5892 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
5893 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
5894 stats
->rx_length_errors
= dev
->stats
.rx_length_errors
;
5895 stats
->rx_errors
= dev
->stats
.rx_errors
;
5896 stats
->rx_crc_errors
= dev
->stats
.rx_crc_errors
;
5897 stats
->rx_fifo_errors
= dev
->stats
.rx_fifo_errors
;
5898 stats
->rx_missed_errors
= dev
->stats
.rx_missed_errors
;
5903 static void rtl8169_net_suspend(struct net_device
*dev
)
5905 struct rtl8169_private
*tp
= netdev_priv(dev
);
5907 if (!netif_running(dev
))
5910 netif_device_detach(dev
);
5911 netif_stop_queue(dev
);
5914 napi_disable(&tp
->napi
);
5915 clear_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
5916 rtl_unlock_work(tp
);
5918 rtl_pll_power_down(tp
);
5923 static int rtl8169_suspend(struct device
*device
)
5925 struct pci_dev
*pdev
= to_pci_dev(device
);
5926 struct net_device
*dev
= pci_get_drvdata(pdev
);
5928 rtl8169_net_suspend(dev
);
5933 static void __rtl8169_resume(struct net_device
*dev
)
5935 struct rtl8169_private
*tp
= netdev_priv(dev
);
5937 netif_device_attach(dev
);
5939 rtl_pll_power_up(tp
);
5942 napi_enable(&tp
->napi
);
5943 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
5944 rtl_unlock_work(tp
);
5946 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
5949 static int rtl8169_resume(struct device
*device
)
5951 struct pci_dev
*pdev
= to_pci_dev(device
);
5952 struct net_device
*dev
= pci_get_drvdata(pdev
);
5953 struct rtl8169_private
*tp
= netdev_priv(dev
);
5955 rtl8169_init_phy(dev
, tp
);
5957 if (netif_running(dev
))
5958 __rtl8169_resume(dev
);
5963 static int rtl8169_runtime_suspend(struct device
*device
)
5965 struct pci_dev
*pdev
= to_pci_dev(device
);
5966 struct net_device
*dev
= pci_get_drvdata(pdev
);
5967 struct rtl8169_private
*tp
= netdev_priv(dev
);
5969 if (!tp
->TxDescArray
)
5973 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
5974 __rtl8169_set_wol(tp
, WAKE_ANY
);
5975 rtl_unlock_work(tp
);
5977 rtl8169_net_suspend(dev
);
5982 static int rtl8169_runtime_resume(struct device
*device
)
5984 struct pci_dev
*pdev
= to_pci_dev(device
);
5985 struct net_device
*dev
= pci_get_drvdata(pdev
);
5986 struct rtl8169_private
*tp
= netdev_priv(dev
);
5988 if (!tp
->TxDescArray
)
5992 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
5993 tp
->saved_wolopts
= 0;
5994 rtl_unlock_work(tp
);
5996 rtl8169_init_phy(dev
, tp
);
5998 __rtl8169_resume(dev
);
6003 static int rtl8169_runtime_idle(struct device
*device
)
6005 struct pci_dev
*pdev
= to_pci_dev(device
);
6006 struct net_device
*dev
= pci_get_drvdata(pdev
);
6007 struct rtl8169_private
*tp
= netdev_priv(dev
);
6009 return tp
->TxDescArray
? -EBUSY
: 0;
6012 static const struct dev_pm_ops rtl8169_pm_ops
= {
6013 .suspend
= rtl8169_suspend
,
6014 .resume
= rtl8169_resume
,
6015 .freeze
= rtl8169_suspend
,
6016 .thaw
= rtl8169_resume
,
6017 .poweroff
= rtl8169_suspend
,
6018 .restore
= rtl8169_resume
,
6019 .runtime_suspend
= rtl8169_runtime_suspend
,
6020 .runtime_resume
= rtl8169_runtime_resume
,
6021 .runtime_idle
= rtl8169_runtime_idle
,
6024 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6026 #else /* !CONFIG_PM */
6028 #define RTL8169_PM_OPS NULL
6030 #endif /* !CONFIG_PM */
6032 static void rtl_wol_shutdown_quirk(struct rtl8169_private
*tp
)
6034 void __iomem
*ioaddr
= tp
->mmio_addr
;
6036 /* WoL fails with 8168b when the receiver is disabled. */
6037 switch (tp
->mac_version
) {
6038 case RTL_GIGA_MAC_VER_11
:
6039 case RTL_GIGA_MAC_VER_12
:
6040 case RTL_GIGA_MAC_VER_17
:
6041 pci_clear_master(tp
->pci_dev
);
6043 RTL_W8(ChipCmd
, CmdRxEnb
);
6052 static void rtl_shutdown(struct pci_dev
*pdev
)
6054 struct net_device
*dev
= pci_get_drvdata(pdev
);
6055 struct rtl8169_private
*tp
= netdev_priv(dev
);
6056 struct device
*d
= &pdev
->dev
;
6058 pm_runtime_get_sync(d
);
6060 rtl8169_net_suspend(dev
);
6062 /* Restore original MAC address */
6063 rtl_rar_set(tp
, dev
->perm_addr
);
6065 rtl8169_hw_reset(tp
);
6067 if (system_state
== SYSTEM_POWER_OFF
) {
6068 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
6069 rtl_wol_suspend_quirk(tp
);
6070 rtl_wol_shutdown_quirk(tp
);
6073 pci_wake_from_d3(pdev
, true);
6074 pci_set_power_state(pdev
, PCI_D3hot
);
6077 pm_runtime_put_noidle(d
);
6080 static void __devexit
rtl_remove_one(struct pci_dev
*pdev
)
6082 struct net_device
*dev
= pci_get_drvdata(pdev
);
6083 struct rtl8169_private
*tp
= netdev_priv(dev
);
6085 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
6086 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
6087 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
6088 rtl8168_driver_stop(tp
);
6091 cancel_work_sync(&tp
->wk
.work
);
6093 unregister_netdev(dev
);
6095 rtl_release_firmware(tp
);
6097 if (pci_dev_run_wake(pdev
))
6098 pm_runtime_get_noresume(&pdev
->dev
);
6100 /* restore original MAC address */
6101 rtl_rar_set(tp
, dev
->perm_addr
);
6103 rtl_disable_msi(pdev
, tp
);
6104 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
6105 pci_set_drvdata(pdev
, NULL
);
6108 static const struct net_device_ops rtl_netdev_ops
= {
6109 .ndo_open
= rtl_open
,
6110 .ndo_stop
= rtl8169_close
,
6111 .ndo_get_stats64
= rtl8169_get_stats64
,
6112 .ndo_start_xmit
= rtl8169_start_xmit
,
6113 .ndo_tx_timeout
= rtl8169_tx_timeout
,
6114 .ndo_validate_addr
= eth_validate_addr
,
6115 .ndo_change_mtu
= rtl8169_change_mtu
,
6116 .ndo_fix_features
= rtl8169_fix_features
,
6117 .ndo_set_features
= rtl8169_set_features
,
6118 .ndo_set_mac_address
= rtl_set_mac_address
,
6119 .ndo_do_ioctl
= rtl8169_ioctl
,
6120 .ndo_set_rx_mode
= rtl_set_rx_mode
,
6121 #ifdef CONFIG_NET_POLL_CONTROLLER
6122 .ndo_poll_controller
= rtl8169_netpoll
,
6127 static const struct rtl_cfg_info
{
6128 void (*hw_start
)(struct net_device
*);
6129 unsigned int region
;
6134 } rtl_cfg_infos
[] = {
6136 .hw_start
= rtl_hw_start_8169
,
6139 .event_slow
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
,
6140 .features
= RTL_FEATURE_GMII
,
6141 .default_ver
= RTL_GIGA_MAC_VER_01
,
6144 .hw_start
= rtl_hw_start_8168
,
6147 .event_slow
= SYSErr
| LinkChg
| RxOverflow
,
6148 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
6149 .default_ver
= RTL_GIGA_MAC_VER_11
,
6152 .hw_start
= rtl_hw_start_8101
,
6155 .event_slow
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
|
6157 .features
= RTL_FEATURE_MSI
,
6158 .default_ver
= RTL_GIGA_MAC_VER_13
,
6162 /* Cfg9346_Unlock assumed. */
6163 static unsigned rtl_try_msi(struct rtl8169_private
*tp
,
6164 const struct rtl_cfg_info
*cfg
)
6166 void __iomem
*ioaddr
= tp
->mmio_addr
;
6170 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
6171 if (cfg
->features
& RTL_FEATURE_MSI
) {
6172 if (pci_enable_msi(tp
->pci_dev
)) {
6173 netif_info(tp
, hw
, tp
->dev
, "no MSI. Back to INTx.\n");
6176 msi
= RTL_FEATURE_MSI
;
6179 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
6180 RTL_W8(Config2
, cfg2
);
6184 static int __devinit
6185 rtl_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
6187 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
6188 const unsigned int region
= cfg
->region
;
6189 struct rtl8169_private
*tp
;
6190 struct mii_if_info
*mii
;
6191 struct net_device
*dev
;
6192 void __iomem
*ioaddr
;
6196 if (netif_msg_drv(&debug
)) {
6197 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
6198 MODULENAME
, RTL8169_VERSION
);
6201 dev
= alloc_etherdev(sizeof (*tp
));
6207 SET_NETDEV_DEV(dev
, &pdev
->dev
);
6208 dev
->netdev_ops
= &rtl_netdev_ops
;
6209 tp
= netdev_priv(dev
);
6212 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
6216 mii
->mdio_read
= rtl_mdio_read
;
6217 mii
->mdio_write
= rtl_mdio_write
;
6218 mii
->phy_id_mask
= 0x1f;
6219 mii
->reg_num_mask
= 0x1f;
6220 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
6222 /* disable ASPM completely as that cause random device stop working
6223 * problems as well as full system hangs for some PCIe devices users */
6224 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
6225 PCIE_LINK_STATE_CLKPM
);
6227 /* enable device (incl. PCI PM wakeup and hotplug setup) */
6228 rc
= pci_enable_device(pdev
);
6230 netif_err(tp
, probe
, dev
, "enable failure\n");
6231 goto err_out_free_dev_1
;
6234 if (pci_set_mwi(pdev
) < 0)
6235 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
6237 /* make sure PCI base addr 1 is MMIO */
6238 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
6239 netif_err(tp
, probe
, dev
,
6240 "region #%d not an MMIO resource, aborting\n",
6246 /* check for weird/broken PCI region reporting */
6247 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
6248 netif_err(tp
, probe
, dev
,
6249 "Invalid PCI region size(s), aborting\n");
6254 rc
= pci_request_regions(pdev
, MODULENAME
);
6256 netif_err(tp
, probe
, dev
, "could not request regions\n");
6260 tp
->cp_cmd
= RxChkSum
;
6262 if ((sizeof(dma_addr_t
) > 4) &&
6263 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
6264 tp
->cp_cmd
|= PCIDAC
;
6265 dev
->features
|= NETIF_F_HIGHDMA
;
6267 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
6269 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
6270 goto err_out_free_res_3
;
6274 /* ioremap MMIO region */
6275 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
6277 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
6279 goto err_out_free_res_3
;
6281 tp
->mmio_addr
= ioaddr
;
6283 if (!pci_is_pcie(pdev
))
6284 netif_info(tp
, probe
, dev
, "not PCI Express\n");
6286 /* Identify chip attached to board */
6287 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
6291 rtl_irq_disable(tp
);
6295 rtl_ack_events(tp
, 0xffff);
6297 pci_set_master(pdev
);
6300 * Pretend we are using VLANs; This bypasses a nasty bug where
6301 * Interrupts stop flowing on high load on 8110SCd controllers.
6303 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
6304 tp
->cp_cmd
|= RxVlan
;
6306 rtl_init_mdio_ops(tp
);
6307 rtl_init_pll_power_ops(tp
);
6308 rtl_init_jumbo_ops(tp
);
6309 rtl_init_csi_ops(tp
);
6311 rtl8169_print_mac_version(tp
);
6313 chipset
= tp
->mac_version
;
6314 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
6316 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
6317 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
6318 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
6319 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
6320 tp
->features
|= RTL_FEATURE_WOL
;
6321 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
6322 tp
->features
|= RTL_FEATURE_WOL
;
6323 tp
->features
|= rtl_try_msi(tp
, cfg
);
6324 RTL_W8(Cfg9346
, Cfg9346_Lock
);
6326 if (rtl_tbi_enabled(tp
)) {
6327 tp
->set_speed
= rtl8169_set_speed_tbi
;
6328 tp
->get_settings
= rtl8169_gset_tbi
;
6329 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
6330 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
6331 tp
->link_ok
= rtl8169_tbi_link_ok
;
6332 tp
->do_ioctl
= rtl_tbi_ioctl
;
6334 tp
->set_speed
= rtl8169_set_speed_xmii
;
6335 tp
->get_settings
= rtl8169_gset_xmii
;
6336 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
6337 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
6338 tp
->link_ok
= rtl8169_xmii_link_ok
;
6339 tp
->do_ioctl
= rtl_xmii_ioctl
;
6342 mutex_init(&tp
->wk
.mutex
);
6344 /* Get MAC address */
6345 for (i
= 0; i
< ETH_ALEN
; i
++)
6346 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
6347 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
6349 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
6350 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
6352 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
6354 /* don't enable SG, IP_CSUM and TSO by default - it might not work
6355 * properly for all devices */
6356 dev
->features
|= NETIF_F_RXCSUM
|
6357 NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
6359 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
6360 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
6361 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
6364 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
6365 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
6366 dev
->hw_features
&= ~NETIF_F_HW_VLAN_RX
;
6368 dev
->hw_features
|= NETIF_F_RXALL
;
6369 dev
->hw_features
|= NETIF_F_RXFCS
;
6371 tp
->hw_start
= cfg
->hw_start
;
6372 tp
->event_slow
= cfg
->event_slow
;
6374 tp
->opts1_mask
= (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) ?
6375 ~(RxBOVF
| RxFOVF
) : ~0;
6377 init_timer(&tp
->timer
);
6378 tp
->timer
.data
= (unsigned long) dev
;
6379 tp
->timer
.function
= rtl8169_phy_timer
;
6381 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
6383 rc
= register_netdev(dev
);
6387 pci_set_drvdata(pdev
, dev
);
6389 netif_info(tp
, probe
, dev
, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
6390 rtl_chip_infos
[chipset
].name
, ioaddr
, dev
->dev_addr
,
6391 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), pdev
->irq
);
6392 if (rtl_chip_infos
[chipset
].jumbo_max
!= JUMBO_1K
) {
6393 netif_info(tp
, probe
, dev
, "jumbo features [frames: %d bytes, "
6394 "tx checksumming: %s]\n",
6395 rtl_chip_infos
[chipset
].jumbo_max
,
6396 rtl_chip_infos
[chipset
].jumbo_tx_csum
? "ok" : "ko");
6399 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
6400 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
6401 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
6402 rtl8168_driver_start(tp
);
6405 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
6407 if (pci_dev_run_wake(pdev
))
6408 pm_runtime_put_noidle(&pdev
->dev
);
6410 netif_carrier_off(dev
);
6416 rtl_disable_msi(pdev
, tp
);
6419 pci_release_regions(pdev
);
6421 pci_clear_mwi(pdev
);
6422 pci_disable_device(pdev
);
6428 static struct pci_driver rtl8169_pci_driver
= {
6430 .id_table
= rtl8169_pci_tbl
,
6431 .probe
= rtl_init_one
,
6432 .remove
= __devexit_p(rtl_remove_one
),
6433 .shutdown
= rtl_shutdown
,
6434 .driver
.pm
= RTL8169_PM_OPS
,
6437 static int __init
rtl8169_init_module(void)
6439 return pci_register_driver(&rtl8169_pci_driver
);
6442 static void __exit
rtl8169_cleanup_module(void)
6444 pci_unregister_driver(&rtl8169_pci_driver
);
6447 module_init(rtl8169_init_module
);
6448 module_exit(rtl8169_cleanup_module
);