2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
57 #define assert(expr) \
59 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
60 #expr,__FILE__,__func__,__LINE__); \
62 #define dprintk(fmt, args...) \
63 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
65 #define assert(expr) do {} while (0)
66 #define dprintk(fmt, args...) do {} while (0)
67 #endif /* RTL8169_DEBUG */
69 #define R8169_MSG_DEFAULT \
70 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
72 #define TX_SLOTS_AVAIL(tp) \
73 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
75 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
76 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
77 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
79 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
80 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
81 static const int multicast_filter_limit
= 32;
83 #define MAX_READ_REQUEST_SHIFT 12
84 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
85 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
87 #define R8169_REGS_SIZE 256
88 #define R8169_NAPI_WEIGHT 64
89 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
90 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
91 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
92 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
94 #define RTL8169_TX_TIMEOUT (6*HZ)
95 #define RTL8169_PHY_TIMEOUT (10*HZ)
97 /* write/read MMIO register */
98 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
99 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
100 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
101 #define RTL_R8(reg) readb (ioaddr + (reg))
102 #define RTL_R16(reg) readw (ioaddr + (reg))
103 #define RTL_R32(reg) readl (ioaddr + (reg))
106 RTL_GIGA_MAC_VER_01
= 0,
150 RTL_GIGA_MAC_NONE
= 0xff,
153 enum rtl_tx_desc_version
{
158 #define JUMBO_1K ETH_DATA_LEN
159 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
160 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
161 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
162 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
164 #define _R(NAME,TD,FW,SZ,B) { \
172 static const struct {
174 enum rtl_tx_desc_version txd_version
;
178 } rtl_chip_infos
[] = {
180 [RTL_GIGA_MAC_VER_01
] =
181 _R("RTL8169", RTL_TD_0
, NULL
, JUMBO_7K
, true),
182 [RTL_GIGA_MAC_VER_02
] =
183 _R("RTL8169s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
184 [RTL_GIGA_MAC_VER_03
] =
185 _R("RTL8110s", RTL_TD_0
, NULL
, JUMBO_7K
, true),
186 [RTL_GIGA_MAC_VER_04
] =
187 _R("RTL8169sb/8110sb", RTL_TD_0
, NULL
, JUMBO_7K
, true),
188 [RTL_GIGA_MAC_VER_05
] =
189 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
190 [RTL_GIGA_MAC_VER_06
] =
191 _R("RTL8169sc/8110sc", RTL_TD_0
, NULL
, JUMBO_7K
, true),
193 [RTL_GIGA_MAC_VER_07
] =
194 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
195 [RTL_GIGA_MAC_VER_08
] =
196 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
197 [RTL_GIGA_MAC_VER_09
] =
198 _R("RTL8102e", RTL_TD_1
, NULL
, JUMBO_1K
, true),
199 [RTL_GIGA_MAC_VER_10
] =
200 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
201 [RTL_GIGA_MAC_VER_11
] =
202 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
203 [RTL_GIGA_MAC_VER_12
] =
204 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
205 [RTL_GIGA_MAC_VER_13
] =
206 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
207 [RTL_GIGA_MAC_VER_14
] =
208 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
209 [RTL_GIGA_MAC_VER_15
] =
210 _R("RTL8100e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
211 [RTL_GIGA_MAC_VER_16
] =
212 _R("RTL8101e", RTL_TD_0
, NULL
, JUMBO_1K
, true),
213 [RTL_GIGA_MAC_VER_17
] =
214 _R("RTL8168b/8111b", RTL_TD_0
, NULL
, JUMBO_4K
, false),
215 [RTL_GIGA_MAC_VER_18
] =
216 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
217 [RTL_GIGA_MAC_VER_19
] =
218 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
219 [RTL_GIGA_MAC_VER_20
] =
220 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
221 [RTL_GIGA_MAC_VER_21
] =
222 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
223 [RTL_GIGA_MAC_VER_22
] =
224 _R("RTL8168c/8111c", RTL_TD_1
, NULL
, JUMBO_6K
, false),
225 [RTL_GIGA_MAC_VER_23
] =
226 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
227 [RTL_GIGA_MAC_VER_24
] =
228 _R("RTL8168cp/8111cp", RTL_TD_1
, NULL
, JUMBO_6K
, false),
229 [RTL_GIGA_MAC_VER_25
] =
230 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_1
,
232 [RTL_GIGA_MAC_VER_26
] =
233 _R("RTL8168d/8111d", RTL_TD_1
, FIRMWARE_8168D_2
,
235 [RTL_GIGA_MAC_VER_27
] =
236 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
237 [RTL_GIGA_MAC_VER_28
] =
238 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
239 [RTL_GIGA_MAC_VER_29
] =
240 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
242 [RTL_GIGA_MAC_VER_30
] =
243 _R("RTL8105e", RTL_TD_1
, FIRMWARE_8105E_1
,
245 [RTL_GIGA_MAC_VER_31
] =
246 _R("RTL8168dp/8111dp", RTL_TD_1
, NULL
, JUMBO_9K
, false),
247 [RTL_GIGA_MAC_VER_32
] =
248 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_1
,
250 [RTL_GIGA_MAC_VER_33
] =
251 _R("RTL8168e/8111e", RTL_TD_1
, FIRMWARE_8168E_2
,
253 [RTL_GIGA_MAC_VER_34
] =
254 _R("RTL8168evl/8111evl",RTL_TD_1
, FIRMWARE_8168E_3
,
256 [RTL_GIGA_MAC_VER_35
] =
257 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_1
,
259 [RTL_GIGA_MAC_VER_36
] =
260 _R("RTL8168f/8111f", RTL_TD_1
, FIRMWARE_8168F_2
,
262 [RTL_GIGA_MAC_VER_37
] =
263 _R("RTL8402", RTL_TD_1
, FIRMWARE_8402_1
,
265 [RTL_GIGA_MAC_VER_38
] =
266 _R("RTL8411", RTL_TD_1
, FIRMWARE_8411_1
,
268 [RTL_GIGA_MAC_VER_39
] =
269 _R("RTL8106e", RTL_TD_1
, FIRMWARE_8106E_1
,
271 [RTL_GIGA_MAC_VER_40
] =
272 _R("RTL8168g/8111g", RTL_TD_1
, FIRMWARE_8168G_2
,
274 [RTL_GIGA_MAC_VER_41
] =
275 _R("RTL8168g/8111g", RTL_TD_1
, NULL
, JUMBO_9K
, false),
276 [RTL_GIGA_MAC_VER_42
] =
277 _R("RTL8168g/8111g", RTL_TD_1
, FIRMWARE_8168G_3
,
279 [RTL_GIGA_MAC_VER_43
] =
280 _R("RTL8106e", RTL_TD_1
, FIRMWARE_8106E_2
,
282 [RTL_GIGA_MAC_VER_44
] =
283 _R("RTL8411", RTL_TD_1
, FIRMWARE_8411_2
,
294 static const struct pci_device_id rtl8169_pci_tbl
[] = {
295 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
296 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
297 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
298 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
299 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
300 { PCI_VENDOR_ID_DLINK
, 0x4300,
301 PCI_VENDOR_ID_DLINK
, 0x4b10, 0, 0, RTL_CFG_1
},
302 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
303 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4302), 0, 0, RTL_CFG_0
},
304 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
305 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
306 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
307 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
309 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
313 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
315 static int rx_buf_sz
= 16383;
322 MAC0
= 0, /* Ethernet hardware address. */
324 MAR0
= 8, /* Multicast filter. */
325 CounterAddrLow
= 0x10,
326 CounterAddrHigh
= 0x14,
327 TxDescStartAddrLow
= 0x20,
328 TxDescStartAddrHigh
= 0x24,
329 TxHDescStartAddrLow
= 0x28,
330 TxHDescStartAddrHigh
= 0x2c,
339 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
340 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
343 #define RX128_INT_EN (1 << 15) /* 8111c and later */
344 #define RX_MULTI_EN (1 << 14) /* 8111c only */
345 #define RXCFG_FIFO_SHIFT 13
346 /* No threshold before first PCI xfer */
347 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
348 #define RX_EARLY_OFF (1 << 11)
349 #define RXCFG_DMA_SHIFT 8
350 /* Unlimited maximum PCI burst. */
351 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
358 #define PME_SIGNAL (1 << 5) /* 8168c and later */
369 RxDescAddrLow
= 0xe4,
370 RxDescAddrHigh
= 0xe8,
371 EarlyTxThres
= 0xec, /* 8169. Unit of 32 bytes. */
373 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
375 MaxTxPacketSize
= 0xec, /* 8101/8168. Unit of 128 bytes. */
377 #define TxPacketMax (8064 >> 7)
378 #define EarlySize 0x27
381 FuncEventMask
= 0xf4,
382 FuncPresetState
= 0xf8,
383 FuncForceEvent
= 0xfc,
386 enum rtl8110_registers
{
392 enum rtl8168_8101_registers
{
395 #define CSIAR_FLAG 0x80000000
396 #define CSIAR_WRITE_CMD 0x80000000
397 #define CSIAR_BYTE_ENABLE 0x0f
398 #define CSIAR_BYTE_ENABLE_SHIFT 12
399 #define CSIAR_ADDR_MASK 0x0fff
400 #define CSIAR_FUNC_CARD 0x00000000
401 #define CSIAR_FUNC_SDIO 0x00010000
402 #define CSIAR_FUNC_NIC 0x00020000
403 #define CSIAR_FUNC_NIC2 0x00010000
406 #define EPHYAR_FLAG 0x80000000
407 #define EPHYAR_WRITE_CMD 0x80000000
408 #define EPHYAR_REG_MASK 0x1f
409 #define EPHYAR_REG_SHIFT 16
410 #define EPHYAR_DATA_MASK 0xffff
412 #define PFM_EN (1 << 6)
414 #define FIX_NAK_1 (1 << 4)
415 #define FIX_NAK_2 (1 << 3)
418 #define NOW_IS_OOB (1 << 7)
419 #define TX_EMPTY (1 << 5)
420 #define RX_EMPTY (1 << 4)
421 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
422 #define EN_NDP (1 << 3)
423 #define EN_OOB_RESET (1 << 2)
424 #define LINK_LIST_RDY (1 << 1)
426 #define EFUSEAR_FLAG 0x80000000
427 #define EFUSEAR_WRITE_CMD 0x80000000
428 #define EFUSEAR_READ_CMD 0x00000000
429 #define EFUSEAR_REG_MASK 0x03ff
430 #define EFUSEAR_REG_SHIFT 8
431 #define EFUSEAR_DATA_MASK 0xff
434 enum rtl8168_registers
{
439 #define ERIAR_FLAG 0x80000000
440 #define ERIAR_WRITE_CMD 0x80000000
441 #define ERIAR_READ_CMD 0x00000000
442 #define ERIAR_ADDR_BYTE_ALIGN 4
443 #define ERIAR_TYPE_SHIFT 16
444 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
445 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
446 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
447 #define ERIAR_MASK_SHIFT 12
448 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
449 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
450 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
451 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
452 EPHY_RXER_NUM
= 0x7c,
453 OCPDR
= 0xb0, /* OCP GPHY access */
454 #define OCPDR_WRITE_CMD 0x80000000
455 #define OCPDR_READ_CMD 0x00000000
456 #define OCPDR_REG_MASK 0x7f
457 #define OCPDR_GPHY_REG_SHIFT 16
458 #define OCPDR_DATA_MASK 0xffff
460 #define OCPAR_FLAG 0x80000000
461 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
462 #define OCPAR_GPHY_READ_CMD 0x0000f060
464 RDSAR1
= 0xd0, /* 8168c only. Undocumented on 8168dp */
465 MISC
= 0xf0, /* 8168e only. */
466 #define TXPLA_RST (1 << 29)
467 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
468 #define PWM_EN (1 << 22)
469 #define RXDV_GATED_EN (1 << 19)
470 #define EARLY_TALLY_EN (1 << 16)
473 enum rtl_register_content
{
474 /* InterruptStatusBits */
478 TxDescUnavail
= 0x0080,
502 /* TXPoll register p.5 */
503 HPQ
= 0x80, /* Poll cmd on the high prio queue */
504 NPQ
= 0x40, /* Poll cmd on the low prio queue */
505 FSWInt
= 0x01, /* Forced software interrupt */
509 Cfg9346_Unlock
= 0xc0,
514 AcceptBroadcast
= 0x08,
515 AcceptMulticast
= 0x04,
517 AcceptAllPhys
= 0x01,
518 #define RX_CONFIG_ACCEPT_MASK 0x3f
521 TxInterFrameGapShift
= 24,
522 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
524 /* Config1 register p.24 */
527 Speed_down
= (1 << 4),
531 PMEnable
= (1 << 0), /* Power Management Enable */
533 /* Config2 register p. 25 */
534 ClkReqEn
= (1 << 7), /* Clock Request Enable */
535 MSIEnable
= (1 << 5), /* 8169 only. Reserved in the 8168. */
536 PCI_Clock_66MHz
= 0x01,
537 PCI_Clock_33MHz
= 0x00,
539 /* Config3 register p.25 */
540 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
541 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
542 Jumbo_En0
= (1 << 2), /* 8168 only. Reserved in the 8168b */
543 Rdy_to_L23
= (1 << 1), /* L23 Enable */
544 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
546 /* Config4 register */
547 Jumbo_En1
= (1 << 1), /* 8168 only. Reserved in the 8168b */
549 /* Config5 register p.27 */
550 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
551 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
552 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
554 LanWake
= (1 << 1), /* LanWake enable/disable */
555 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
556 ASPM_en
= (1 << 0), /* ASPM enable */
559 TBIReset
= 0x80000000,
560 TBILoopback
= 0x40000000,
561 TBINwEnable
= 0x20000000,
562 TBINwRestart
= 0x10000000,
563 TBILinkOk
= 0x02000000,
564 TBINwComplete
= 0x01000000,
567 EnableBist
= (1 << 15), // 8168 8101
568 Mac_dbgo_oe
= (1 << 14), // 8168 8101
569 Normal_mode
= (1 << 13), // unused
570 Force_half_dup
= (1 << 12), // 8168 8101
571 Force_rxflow_en
= (1 << 11), // 8168 8101
572 Force_txflow_en
= (1 << 10), // 8168 8101
573 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
574 ASF
= (1 << 8), // 8168 8101
575 PktCntrDisable
= (1 << 7), // 8168 8101
576 Mac_dbgo_sel
= 0x001c, // 8168
581 INTT_0
= 0x0000, // 8168
582 INTT_1
= 0x0001, // 8168
583 INTT_2
= 0x0002, // 8168
584 INTT_3
= 0x0003, // 8168
586 /* rtl8169_PHYstatus */
597 TBILinkOK
= 0x02000000,
599 /* DumpCounterCommand */
604 /* First doubleword. */
605 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
606 RingEnd
= (1 << 30), /* End of descriptor ring */
607 FirstFrag
= (1 << 29), /* First segment of a packet */
608 LastFrag
= (1 << 28), /* Final segment of a packet */
612 enum rtl_tx_desc_bit
{
613 /* First doubleword. */
614 TD_LSO
= (1 << 27), /* Large Send Offload */
615 #define TD_MSS_MAX 0x07ffu /* MSS value */
617 /* Second doubleword. */
618 TxVlanTag
= (1 << 17), /* Add VLAN tag */
621 /* 8169, 8168b and 810x except 8102e. */
622 enum rtl_tx_desc_bit_0
{
623 /* First doubleword. */
624 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
625 TD0_TCP_CS
= (1 << 16), /* Calculate TCP/IP checksum */
626 TD0_UDP_CS
= (1 << 17), /* Calculate UDP/IP checksum */
627 TD0_IP_CS
= (1 << 18), /* Calculate IP checksum */
630 /* 8102e, 8168c and beyond. */
631 enum rtl_tx_desc_bit_1
{
632 /* First doubleword. */
633 TD1_GTSENV4
= (1 << 26), /* Giant Send for IPv4 */
634 TD1_GTSENV6
= (1 << 25), /* Giant Send for IPv6 */
635 #define GTTCPHO_SHIFT 18
636 #define GTTCPHO_MAX 0x7fU
638 /* Second doubleword. */
639 #define TCPHO_SHIFT 18
640 #define TCPHO_MAX 0x3ffU
641 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
642 TD1_IPv6_CS
= (1 << 28), /* Calculate IPv6 checksum */
643 TD1_IPv4_CS
= (1 << 29), /* Calculate IPv4 checksum */
644 TD1_TCP_CS
= (1 << 30), /* Calculate TCP/IP checksum */
645 TD1_UDP_CS
= (1 << 31), /* Calculate UDP/IP checksum */
648 enum rtl_rx_desc_bit
{
650 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
651 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
653 #define RxProtoUDP (PID1)
654 #define RxProtoTCP (PID0)
655 #define RxProtoIP (PID1 | PID0)
656 #define RxProtoMask RxProtoIP
658 IPFail
= (1 << 16), /* IP checksum failed */
659 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
660 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
661 RxVlanTag
= (1 << 16), /* VLAN tag available */
664 #define RsvdMask 0x3fffc000
681 u8 __pad
[sizeof(void *) - sizeof(u32
)];
685 RTL_FEATURE_WOL
= (1 << 0),
686 RTL_FEATURE_MSI
= (1 << 1),
687 RTL_FEATURE_GMII
= (1 << 2),
690 struct rtl8169_counters
{
697 __le32 tx_one_collision
;
698 __le32 tx_multi_collision
;
707 RTL_FLAG_TASK_ENABLED
,
708 RTL_FLAG_TASK_SLOW_PENDING
,
709 RTL_FLAG_TASK_RESET_PENDING
,
710 RTL_FLAG_TASK_PHY_PENDING
,
714 struct rtl8169_stats
{
717 struct u64_stats_sync syncp
;
720 struct rtl8169_private
{
721 void __iomem
*mmio_addr
; /* memory map physical address */
722 struct pci_dev
*pci_dev
;
723 struct net_device
*dev
;
724 struct napi_struct napi
;
728 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
729 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
731 struct rtl8169_stats rx_stats
;
732 struct rtl8169_stats tx_stats
;
733 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
734 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
735 dma_addr_t TxPhyAddr
;
736 dma_addr_t RxPhyAddr
;
737 void *Rx_databuff
[NUM_RX_DESC
]; /* Rx data buffers */
738 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
739 struct timer_list timer
;
745 void (*write
)(struct rtl8169_private
*, int, int);
746 int (*read
)(struct rtl8169_private
*, int);
749 struct pll_power_ops
{
750 void (*down
)(struct rtl8169_private
*);
751 void (*up
)(struct rtl8169_private
*);
755 void (*enable
)(struct rtl8169_private
*);
756 void (*disable
)(struct rtl8169_private
*);
760 void (*write
)(struct rtl8169_private
*, int, int);
761 u32 (*read
)(struct rtl8169_private
*, int);
764 int (*set_speed
)(struct net_device
*, u8 aneg
, u16 sp
, u8 dpx
, u32 adv
);
765 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
766 void (*phy_reset_enable
)(struct rtl8169_private
*tp
);
767 void (*hw_start
)(struct net_device
*);
768 unsigned int (*phy_reset_pending
)(struct rtl8169_private
*tp
);
769 unsigned int (*link_ok
)(void __iomem
*);
770 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
771 bool (*tso_csum
)(struct rtl8169_private
*, struct sk_buff
*, u32
*);
774 DECLARE_BITMAP(flags
, RTL_FLAG_MAX
);
776 struct work_struct work
;
781 struct mii_if_info mii
;
782 struct rtl8169_counters counters
;
787 const struct firmware
*fw
;
789 #define RTL_VER_SIZE 32
791 char version
[RTL_VER_SIZE
];
793 struct rtl_fw_phy_action
{
798 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
803 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
804 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
805 module_param(use_dac
, int, 0);
806 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
807 module_param_named(debug
, debug
.msg_enable
, int, 0);
808 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
809 MODULE_LICENSE("GPL");
810 MODULE_VERSION(RTL8169_VERSION
);
811 MODULE_FIRMWARE(FIRMWARE_8168D_1
);
812 MODULE_FIRMWARE(FIRMWARE_8168D_2
);
813 MODULE_FIRMWARE(FIRMWARE_8168E_1
);
814 MODULE_FIRMWARE(FIRMWARE_8168E_2
);
815 MODULE_FIRMWARE(FIRMWARE_8168E_3
);
816 MODULE_FIRMWARE(FIRMWARE_8105E_1
);
817 MODULE_FIRMWARE(FIRMWARE_8168F_1
);
818 MODULE_FIRMWARE(FIRMWARE_8168F_2
);
819 MODULE_FIRMWARE(FIRMWARE_8402_1
);
820 MODULE_FIRMWARE(FIRMWARE_8411_1
);
821 MODULE_FIRMWARE(FIRMWARE_8411_2
);
822 MODULE_FIRMWARE(FIRMWARE_8106E_1
);
823 MODULE_FIRMWARE(FIRMWARE_8106E_2
);
824 MODULE_FIRMWARE(FIRMWARE_8168G_2
);
825 MODULE_FIRMWARE(FIRMWARE_8168G_3
);
827 static void rtl_lock_work(struct rtl8169_private
*tp
)
829 mutex_lock(&tp
->wk
.mutex
);
832 static void rtl_unlock_work(struct rtl8169_private
*tp
)
834 mutex_unlock(&tp
->wk
.mutex
);
837 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
839 pcie_capability_clear_and_set_word(pdev
, PCI_EXP_DEVCTL
,
840 PCI_EXP_DEVCTL_READRQ
, force
);
844 bool (*check
)(struct rtl8169_private
*);
848 static void rtl_udelay(unsigned int d
)
853 static bool rtl_loop_wait(struct rtl8169_private
*tp
, const struct rtl_cond
*c
,
854 void (*delay
)(unsigned int), unsigned int d
, int n
,
859 for (i
= 0; i
< n
; i
++) {
861 if (c
->check(tp
) == high
)
864 netif_err(tp
, drv
, tp
->dev
, "%s == %d (loop: %d, delay: %d).\n",
865 c
->msg
, !high
, n
, d
);
869 static bool rtl_udelay_loop_wait_high(struct rtl8169_private
*tp
,
870 const struct rtl_cond
*c
,
871 unsigned int d
, int n
)
873 return rtl_loop_wait(tp
, c
, rtl_udelay
, d
, n
, true);
876 static bool rtl_udelay_loop_wait_low(struct rtl8169_private
*tp
,
877 const struct rtl_cond
*c
,
878 unsigned int d
, int n
)
880 return rtl_loop_wait(tp
, c
, rtl_udelay
, d
, n
, false);
883 static bool rtl_msleep_loop_wait_high(struct rtl8169_private
*tp
,
884 const struct rtl_cond
*c
,
885 unsigned int d
, int n
)
887 return rtl_loop_wait(tp
, c
, msleep
, d
, n
, true);
890 static bool rtl_msleep_loop_wait_low(struct rtl8169_private
*tp
,
891 const struct rtl_cond
*c
,
892 unsigned int d
, int n
)
894 return rtl_loop_wait(tp
, c
, msleep
, d
, n
, false);
897 #define DECLARE_RTL_COND(name) \
898 static bool name ## _check(struct rtl8169_private *); \
900 static const struct rtl_cond name = { \
901 .check = name ## _check, \
905 static bool name ## _check(struct rtl8169_private *tp)
907 DECLARE_RTL_COND(rtl_ocpar_cond
)
909 void __iomem
*ioaddr
= tp
->mmio_addr
;
911 return RTL_R32(OCPAR
) & OCPAR_FLAG
;
914 static u32
ocp_read(struct rtl8169_private
*tp
, u8 mask
, u16 reg
)
916 void __iomem
*ioaddr
= tp
->mmio_addr
;
918 RTL_W32(OCPAR
, ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
920 return rtl_udelay_loop_wait_high(tp
, &rtl_ocpar_cond
, 100, 20) ?
924 static void ocp_write(struct rtl8169_private
*tp
, u8 mask
, u16 reg
, u32 data
)
926 void __iomem
*ioaddr
= tp
->mmio_addr
;
928 RTL_W32(OCPDR
, data
);
929 RTL_W32(OCPAR
, OCPAR_FLAG
| ((u32
)mask
& 0x0f) << 12 | (reg
& 0x0fff));
931 rtl_udelay_loop_wait_low(tp
, &rtl_ocpar_cond
, 100, 20);
934 DECLARE_RTL_COND(rtl_eriar_cond
)
936 void __iomem
*ioaddr
= tp
->mmio_addr
;
938 return RTL_R32(ERIAR
) & ERIAR_FLAG
;
941 static void rtl8168_oob_notify(struct rtl8169_private
*tp
, u8 cmd
)
943 void __iomem
*ioaddr
= tp
->mmio_addr
;
946 RTL_W32(ERIAR
, 0x800010e8);
949 if (!rtl_udelay_loop_wait_low(tp
, &rtl_eriar_cond
, 100, 5))
952 ocp_write(tp
, 0x1, 0x30, 0x00000001);
955 #define OOB_CMD_RESET 0x00
956 #define OOB_CMD_DRIVER_START 0x05
957 #define OOB_CMD_DRIVER_STOP 0x06
959 static u16
rtl8168_get_ocp_reg(struct rtl8169_private
*tp
)
961 return (tp
->mac_version
== RTL_GIGA_MAC_VER_31
) ? 0xb8 : 0x10;
964 DECLARE_RTL_COND(rtl_ocp_read_cond
)
968 reg
= rtl8168_get_ocp_reg(tp
);
970 return ocp_read(tp
, 0x0f, reg
) & 0x00000800;
973 static void rtl8168_driver_start(struct rtl8169_private
*tp
)
975 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_START
);
977 rtl_msleep_loop_wait_high(tp
, &rtl_ocp_read_cond
, 10, 10);
980 static void rtl8168_driver_stop(struct rtl8169_private
*tp
)
982 rtl8168_oob_notify(tp
, OOB_CMD_DRIVER_STOP
);
984 rtl_msleep_loop_wait_low(tp
, &rtl_ocp_read_cond
, 10, 10);
987 static int r8168dp_check_dash(struct rtl8169_private
*tp
)
989 u16 reg
= rtl8168_get_ocp_reg(tp
);
991 return (ocp_read(tp
, 0x0f, reg
) & 0x00008000) ? 1 : 0;
994 static bool rtl_ocp_reg_failure(struct rtl8169_private
*tp
, u32 reg
)
996 if (reg
& 0xffff0001) {
997 netif_err(tp
, drv
, tp
->dev
, "Invalid ocp reg %x!\n", reg
);
1003 DECLARE_RTL_COND(rtl_ocp_gphy_cond
)
1005 void __iomem
*ioaddr
= tp
->mmio_addr
;
1007 return RTL_R32(GPHY_OCP
) & OCPAR_FLAG
;
1010 static void r8168_phy_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
1012 void __iomem
*ioaddr
= tp
->mmio_addr
;
1014 if (rtl_ocp_reg_failure(tp
, reg
))
1017 RTL_W32(GPHY_OCP
, OCPAR_FLAG
| (reg
<< 15) | data
);
1019 rtl_udelay_loop_wait_low(tp
, &rtl_ocp_gphy_cond
, 25, 10);
1022 static u16
r8168_phy_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
1024 void __iomem
*ioaddr
= tp
->mmio_addr
;
1026 if (rtl_ocp_reg_failure(tp
, reg
))
1029 RTL_W32(GPHY_OCP
, reg
<< 15);
1031 return rtl_udelay_loop_wait_high(tp
, &rtl_ocp_gphy_cond
, 25, 10) ?
1032 (RTL_R32(GPHY_OCP
) & 0xffff) : ~0;
1035 static void r8168_mac_ocp_write(struct rtl8169_private
*tp
, u32 reg
, u32 data
)
1037 void __iomem
*ioaddr
= tp
->mmio_addr
;
1039 if (rtl_ocp_reg_failure(tp
, reg
))
1042 RTL_W32(OCPDR
, OCPAR_FLAG
| (reg
<< 15) | data
);
1045 static u16
r8168_mac_ocp_read(struct rtl8169_private
*tp
, u32 reg
)
1047 void __iomem
*ioaddr
= tp
->mmio_addr
;
1049 if (rtl_ocp_reg_failure(tp
, reg
))
1052 RTL_W32(OCPDR
, reg
<< 15);
1054 return RTL_R32(OCPDR
);
1057 #define OCP_STD_PHY_BASE 0xa400
1059 static void r8168g_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1062 tp
->ocp_base
= value
? value
<< 4 : OCP_STD_PHY_BASE
;
1066 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
1069 r8168_phy_ocp_write(tp
, tp
->ocp_base
+ reg
* 2, value
);
1072 static int r8168g_mdio_read(struct rtl8169_private
*tp
, int reg
)
1074 if (tp
->ocp_base
!= OCP_STD_PHY_BASE
)
1077 return r8168_phy_ocp_read(tp
, tp
->ocp_base
+ reg
* 2);
1080 static void mac_mcu_write(struct rtl8169_private
*tp
, int reg
, int value
)
1083 tp
->ocp_base
= value
<< 4;
1087 r8168_mac_ocp_write(tp
, tp
->ocp_base
+ reg
, value
);
1090 static int mac_mcu_read(struct rtl8169_private
*tp
, int reg
)
1092 return r8168_mac_ocp_read(tp
, tp
->ocp_base
+ reg
);
1095 DECLARE_RTL_COND(rtl_phyar_cond
)
1097 void __iomem
*ioaddr
= tp
->mmio_addr
;
1099 return RTL_R32(PHYAR
) & 0x80000000;
1102 static void r8169_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1104 void __iomem
*ioaddr
= tp
->mmio_addr
;
1106 RTL_W32(PHYAR
, 0x80000000 | (reg
& 0x1f) << 16 | (value
& 0xffff));
1108 rtl_udelay_loop_wait_low(tp
, &rtl_phyar_cond
, 25, 20);
1110 * According to hardware specs a 20us delay is required after write
1111 * complete indication, but before sending next command.
1116 static int r8169_mdio_read(struct rtl8169_private
*tp
, int reg
)
1118 void __iomem
*ioaddr
= tp
->mmio_addr
;
1121 RTL_W32(PHYAR
, 0x0 | (reg
& 0x1f) << 16);
1123 value
= rtl_udelay_loop_wait_high(tp
, &rtl_phyar_cond
, 25, 20) ?
1124 RTL_R32(PHYAR
) & 0xffff : ~0;
1127 * According to hardware specs a 20us delay is required after read
1128 * complete indication, but before sending next command.
1135 static void r8168dp_1_mdio_access(struct rtl8169_private
*tp
, int reg
, u32 data
)
1137 void __iomem
*ioaddr
= tp
->mmio_addr
;
1139 RTL_W32(OCPDR
, data
| ((reg
& OCPDR_REG_MASK
) << OCPDR_GPHY_REG_SHIFT
));
1140 RTL_W32(OCPAR
, OCPAR_GPHY_WRITE_CMD
);
1141 RTL_W32(EPHY_RXER_NUM
, 0);
1143 rtl_udelay_loop_wait_low(tp
, &rtl_ocpar_cond
, 1000, 100);
1146 static void r8168dp_1_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1148 r8168dp_1_mdio_access(tp
, reg
,
1149 OCPDR_WRITE_CMD
| (value
& OCPDR_DATA_MASK
));
1152 static int r8168dp_1_mdio_read(struct rtl8169_private
*tp
, int reg
)
1154 void __iomem
*ioaddr
= tp
->mmio_addr
;
1156 r8168dp_1_mdio_access(tp
, reg
, OCPDR_READ_CMD
);
1159 RTL_W32(OCPAR
, OCPAR_GPHY_READ_CMD
);
1160 RTL_W32(EPHY_RXER_NUM
, 0);
1162 return rtl_udelay_loop_wait_high(tp
, &rtl_ocpar_cond
, 1000, 100) ?
1163 RTL_R32(OCPDR
) & OCPDR_DATA_MASK
: ~0;
1166 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1168 static void r8168dp_2_mdio_start(void __iomem
*ioaddr
)
1170 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT
);
1173 static void r8168dp_2_mdio_stop(void __iomem
*ioaddr
)
1175 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT
);
1178 static void r8168dp_2_mdio_write(struct rtl8169_private
*tp
, int reg
, int value
)
1180 void __iomem
*ioaddr
= tp
->mmio_addr
;
1182 r8168dp_2_mdio_start(ioaddr
);
1184 r8169_mdio_write(tp
, reg
, value
);
1186 r8168dp_2_mdio_stop(ioaddr
);
1189 static int r8168dp_2_mdio_read(struct rtl8169_private
*tp
, int reg
)
1191 void __iomem
*ioaddr
= tp
->mmio_addr
;
1194 r8168dp_2_mdio_start(ioaddr
);
1196 value
= r8169_mdio_read(tp
, reg
);
1198 r8168dp_2_mdio_stop(ioaddr
);
1203 static void rtl_writephy(struct rtl8169_private
*tp
, int location
, u32 val
)
1205 tp
->mdio_ops
.write(tp
, location
, val
);
1208 static int rtl_readphy(struct rtl8169_private
*tp
, int location
)
1210 return tp
->mdio_ops
.read(tp
, location
);
1213 static void rtl_patchphy(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1215 rtl_writephy(tp
, reg_addr
, rtl_readphy(tp
, reg_addr
) | value
);
1218 static void rtl_w1w0_phy(struct rtl8169_private
*tp
, int reg_addr
, int p
, int m
)
1222 val
= rtl_readphy(tp
, reg_addr
);
1223 rtl_writephy(tp
, reg_addr
, (val
| p
) & ~m
);
1226 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
1229 struct rtl8169_private
*tp
= netdev_priv(dev
);
1231 rtl_writephy(tp
, location
, val
);
1234 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
1236 struct rtl8169_private
*tp
= netdev_priv(dev
);
1238 return rtl_readphy(tp
, location
);
1241 DECLARE_RTL_COND(rtl_ephyar_cond
)
1243 void __iomem
*ioaddr
= tp
->mmio_addr
;
1245 return RTL_R32(EPHYAR
) & EPHYAR_FLAG
;
1248 static void rtl_ephy_write(struct rtl8169_private
*tp
, int reg_addr
, int value
)
1250 void __iomem
*ioaddr
= tp
->mmio_addr
;
1252 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
1253 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1255 rtl_udelay_loop_wait_low(tp
, &rtl_ephyar_cond
, 10, 100);
1260 static u16
rtl_ephy_read(struct rtl8169_private
*tp
, int reg_addr
)
1262 void __iomem
*ioaddr
= tp
->mmio_addr
;
1264 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
1266 return rtl_udelay_loop_wait_high(tp
, &rtl_ephyar_cond
, 10, 100) ?
1267 RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
: ~0;
1270 static void rtl_eri_write(struct rtl8169_private
*tp
, int addr
, u32 mask
,
1273 void __iomem
*ioaddr
= tp
->mmio_addr
;
1275 BUG_ON((addr
& 3) || (mask
== 0));
1276 RTL_W32(ERIDR
, val
);
1277 RTL_W32(ERIAR
, ERIAR_WRITE_CMD
| type
| mask
| addr
);
1279 rtl_udelay_loop_wait_low(tp
, &rtl_eriar_cond
, 100, 100);
1282 static u32
rtl_eri_read(struct rtl8169_private
*tp
, int addr
, int type
)
1284 void __iomem
*ioaddr
= tp
->mmio_addr
;
1286 RTL_W32(ERIAR
, ERIAR_READ_CMD
| type
| ERIAR_MASK_1111
| addr
);
1288 return rtl_udelay_loop_wait_high(tp
, &rtl_eriar_cond
, 100, 100) ?
1289 RTL_R32(ERIDR
) : ~0;
1292 static void rtl_w1w0_eri(struct rtl8169_private
*tp
, int addr
, u32 mask
, u32 p
,
1297 val
= rtl_eri_read(tp
, addr
, type
);
1298 rtl_eri_write(tp
, addr
, mask
, (val
& ~m
) | p
, type
);
1307 static void rtl_write_exgmac_batch(struct rtl8169_private
*tp
,
1308 const struct exgmac_reg
*r
, int len
)
1311 rtl_eri_write(tp
, r
->addr
, r
->mask
, r
->val
, ERIAR_EXGMAC
);
1316 DECLARE_RTL_COND(rtl_efusear_cond
)
1318 void __iomem
*ioaddr
= tp
->mmio_addr
;
1320 return RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
;
1323 static u8
rtl8168d_efuse_read(struct rtl8169_private
*tp
, int reg_addr
)
1325 void __iomem
*ioaddr
= tp
->mmio_addr
;
1327 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
1329 return rtl_udelay_loop_wait_high(tp
, &rtl_efusear_cond
, 100, 300) ?
1330 RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
: ~0;
1333 static u16
rtl_get_events(struct rtl8169_private
*tp
)
1335 void __iomem
*ioaddr
= tp
->mmio_addr
;
1337 return RTL_R16(IntrStatus
);
1340 static void rtl_ack_events(struct rtl8169_private
*tp
, u16 bits
)
1342 void __iomem
*ioaddr
= tp
->mmio_addr
;
1344 RTL_W16(IntrStatus
, bits
);
1348 static void rtl_irq_disable(struct rtl8169_private
*tp
)
1350 void __iomem
*ioaddr
= tp
->mmio_addr
;
1352 RTL_W16(IntrMask
, 0);
1356 static void rtl_irq_enable(struct rtl8169_private
*tp
, u16 bits
)
1358 void __iomem
*ioaddr
= tp
->mmio_addr
;
1360 RTL_W16(IntrMask
, bits
);
1363 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1364 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1365 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1367 static void rtl_irq_enable_all(struct rtl8169_private
*tp
)
1369 rtl_irq_enable(tp
, RTL_EVENT_NAPI
| tp
->event_slow
);
1372 static void rtl8169_irq_mask_and_ack(struct rtl8169_private
*tp
)
1374 void __iomem
*ioaddr
= tp
->mmio_addr
;
1376 rtl_irq_disable(tp
);
1377 rtl_ack_events(tp
, RTL_EVENT_NAPI
| tp
->event_slow
);
1381 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private
*tp
)
1383 void __iomem
*ioaddr
= tp
->mmio_addr
;
1385 return RTL_R32(TBICSR
) & TBIReset
;
1388 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private
*tp
)
1390 return rtl_readphy(tp
, MII_BMCR
) & BMCR_RESET
;
1393 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
1395 return RTL_R32(TBICSR
) & TBILinkOk
;
1398 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
1400 return RTL_R8(PHYstatus
) & LinkStatus
;
1403 static void rtl8169_tbi_reset_enable(struct rtl8169_private
*tp
)
1405 void __iomem
*ioaddr
= tp
->mmio_addr
;
1407 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
1410 static void rtl8169_xmii_reset_enable(struct rtl8169_private
*tp
)
1414 val
= rtl_readphy(tp
, MII_BMCR
) | BMCR_RESET
;
1415 rtl_writephy(tp
, MII_BMCR
, val
& 0xffff);
1418 static void rtl_link_chg_patch(struct rtl8169_private
*tp
)
1420 void __iomem
*ioaddr
= tp
->mmio_addr
;
1421 struct net_device
*dev
= tp
->dev
;
1423 if (!netif_running(dev
))
1426 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
1427 tp
->mac_version
== RTL_GIGA_MAC_VER_38
) {
1428 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1429 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011,
1431 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1433 } else if (RTL_R8(PHYstatus
) & _100bps
) {
1434 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1436 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1439 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1441 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f,
1444 /* Reset packet filter */
1445 rtl_w1w0_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01,
1447 rtl_w1w0_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00,
1449 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
1450 tp
->mac_version
== RTL_GIGA_MAC_VER_36
) {
1451 if (RTL_R8(PHYstatus
) & _1000bpsF
) {
1452 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x00000011,
1454 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x00000005,
1457 rtl_eri_write(tp
, 0x1bc, ERIAR_MASK_1111
, 0x0000001f,
1459 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_1111
, 0x0000003f,
1462 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_37
) {
1463 if (RTL_R8(PHYstatus
) & _10bps
) {
1464 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x4d02,
1466 rtl_eri_write(tp
, 0x1dc, ERIAR_MASK_0011
, 0x0060,
1469 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000,
1475 static void __rtl8169_check_link_status(struct net_device
*dev
,
1476 struct rtl8169_private
*tp
,
1477 void __iomem
*ioaddr
, bool pm
)
1479 if (tp
->link_ok(ioaddr
)) {
1480 rtl_link_chg_patch(tp
);
1481 /* This is to cancel a scheduled suspend if there's one. */
1483 pm_request_resume(&tp
->pci_dev
->dev
);
1484 netif_carrier_on(dev
);
1485 if (net_ratelimit())
1486 netif_info(tp
, ifup
, dev
, "link up\n");
1488 netif_carrier_off(dev
);
1489 netif_info(tp
, ifdown
, dev
, "link down\n");
1491 pm_schedule_suspend(&tp
->pci_dev
->dev
, 5000);
1495 static void rtl8169_check_link_status(struct net_device
*dev
,
1496 struct rtl8169_private
*tp
,
1497 void __iomem
*ioaddr
)
1499 __rtl8169_check_link_status(dev
, tp
, ioaddr
, false);
1502 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1504 static u32
__rtl8169_get_wol(struct rtl8169_private
*tp
)
1506 void __iomem
*ioaddr
= tp
->mmio_addr
;
1510 options
= RTL_R8(Config1
);
1511 if (!(options
& PMEnable
))
1514 options
= RTL_R8(Config3
);
1515 if (options
& LinkUp
)
1516 wolopts
|= WAKE_PHY
;
1517 if (options
& MagicPacket
)
1518 wolopts
|= WAKE_MAGIC
;
1520 options
= RTL_R8(Config5
);
1522 wolopts
|= WAKE_UCAST
;
1524 wolopts
|= WAKE_BCAST
;
1526 wolopts
|= WAKE_MCAST
;
1531 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1533 struct rtl8169_private
*tp
= netdev_priv(dev
);
1537 wol
->supported
= WAKE_ANY
;
1538 wol
->wolopts
= __rtl8169_get_wol(tp
);
1540 rtl_unlock_work(tp
);
1543 static void __rtl8169_set_wol(struct rtl8169_private
*tp
, u32 wolopts
)
1545 void __iomem
*ioaddr
= tp
->mmio_addr
;
1547 static const struct {
1552 { WAKE_PHY
, Config3
, LinkUp
},
1553 { WAKE_MAGIC
, Config3
, MagicPacket
},
1554 { WAKE_UCAST
, Config5
, UWF
},
1555 { WAKE_BCAST
, Config5
, BWF
},
1556 { WAKE_MCAST
, Config5
, MWF
},
1557 { WAKE_ANY
, Config5
, LanWake
}
1561 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1563 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
1564 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
1565 if (wolopts
& cfg
[i
].opt
)
1566 options
|= cfg
[i
].mask
;
1567 RTL_W8(cfg
[i
].reg
, options
);
1570 switch (tp
->mac_version
) {
1571 case RTL_GIGA_MAC_VER_01
... RTL_GIGA_MAC_VER_17
:
1572 options
= RTL_R8(Config1
) & ~PMEnable
;
1574 options
|= PMEnable
;
1575 RTL_W8(Config1
, options
);
1578 options
= RTL_R8(Config2
) & ~PME_SIGNAL
;
1580 options
|= PME_SIGNAL
;
1581 RTL_W8(Config2
, options
);
1585 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1588 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
1590 struct rtl8169_private
*tp
= netdev_priv(dev
);
1595 tp
->features
|= RTL_FEATURE_WOL
;
1597 tp
->features
&= ~RTL_FEATURE_WOL
;
1598 __rtl8169_set_wol(tp
, wol
->wolopts
);
1600 rtl_unlock_work(tp
);
1602 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
1607 static const char *rtl_lookup_firmware_name(struct rtl8169_private
*tp
)
1609 return rtl_chip_infos
[tp
->mac_version
].fw_name
;
1612 static void rtl8169_get_drvinfo(struct net_device
*dev
,
1613 struct ethtool_drvinfo
*info
)
1615 struct rtl8169_private
*tp
= netdev_priv(dev
);
1616 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
1618 strlcpy(info
->driver
, MODULENAME
, sizeof(info
->driver
));
1619 strlcpy(info
->version
, RTL8169_VERSION
, sizeof(info
->version
));
1620 strlcpy(info
->bus_info
, pci_name(tp
->pci_dev
), sizeof(info
->bus_info
));
1621 BUILD_BUG_ON(sizeof(info
->fw_version
) < sizeof(rtl_fw
->version
));
1622 if (!IS_ERR_OR_NULL(rtl_fw
))
1623 strlcpy(info
->fw_version
, rtl_fw
->version
,
1624 sizeof(info
->fw_version
));
1627 static int rtl8169_get_regs_len(struct net_device
*dev
)
1629 return R8169_REGS_SIZE
;
1632 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
1633 u8 autoneg
, u16 speed
, u8 duplex
, u32 ignored
)
1635 struct rtl8169_private
*tp
= netdev_priv(dev
);
1636 void __iomem
*ioaddr
= tp
->mmio_addr
;
1640 reg
= RTL_R32(TBICSR
);
1641 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
1642 (duplex
== DUPLEX_FULL
)) {
1643 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
1644 } else if (autoneg
== AUTONEG_ENABLE
)
1645 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
1647 netif_warn(tp
, link
, dev
,
1648 "incorrect speed setting refused in TBI mode\n");
1655 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
1656 u8 autoneg
, u16 speed
, u8 duplex
, u32 adv
)
1658 struct rtl8169_private
*tp
= netdev_priv(dev
);
1659 int giga_ctrl
, bmcr
;
1662 rtl_writephy(tp
, 0x1f, 0x0000);
1664 if (autoneg
== AUTONEG_ENABLE
) {
1667 auto_nego
= rtl_readphy(tp
, MII_ADVERTISE
);
1668 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
1669 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
1671 if (adv
& ADVERTISED_10baseT_Half
)
1672 auto_nego
|= ADVERTISE_10HALF
;
1673 if (adv
& ADVERTISED_10baseT_Full
)
1674 auto_nego
|= ADVERTISE_10FULL
;
1675 if (adv
& ADVERTISED_100baseT_Half
)
1676 auto_nego
|= ADVERTISE_100HALF
;
1677 if (adv
& ADVERTISED_100baseT_Full
)
1678 auto_nego
|= ADVERTISE_100FULL
;
1680 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
1682 giga_ctrl
= rtl_readphy(tp
, MII_CTRL1000
);
1683 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
1685 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1686 if (tp
->mii
.supports_gmii
) {
1687 if (adv
& ADVERTISED_1000baseT_Half
)
1688 giga_ctrl
|= ADVERTISE_1000HALF
;
1689 if (adv
& ADVERTISED_1000baseT_Full
)
1690 giga_ctrl
|= ADVERTISE_1000FULL
;
1691 } else if (adv
& (ADVERTISED_1000baseT_Half
|
1692 ADVERTISED_1000baseT_Full
)) {
1693 netif_info(tp
, link
, dev
,
1694 "PHY does not support 1000Mbps\n");
1698 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
1700 rtl_writephy(tp
, MII_ADVERTISE
, auto_nego
);
1701 rtl_writephy(tp
, MII_CTRL1000
, giga_ctrl
);
1705 if (speed
== SPEED_10
)
1707 else if (speed
== SPEED_100
)
1708 bmcr
= BMCR_SPEED100
;
1712 if (duplex
== DUPLEX_FULL
)
1713 bmcr
|= BMCR_FULLDPLX
;
1716 rtl_writephy(tp
, MII_BMCR
, bmcr
);
1718 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
1719 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
1720 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
1721 rtl_writephy(tp
, 0x17, 0x2138);
1722 rtl_writephy(tp
, 0x0e, 0x0260);
1724 rtl_writephy(tp
, 0x17, 0x2108);
1725 rtl_writephy(tp
, 0x0e, 0x0000);
1734 static int rtl8169_set_speed(struct net_device
*dev
,
1735 u8 autoneg
, u16 speed
, u8 duplex
, u32 advertising
)
1737 struct rtl8169_private
*tp
= netdev_priv(dev
);
1740 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
, advertising
);
1744 if (netif_running(dev
) && (autoneg
== AUTONEG_ENABLE
) &&
1745 (advertising
& ADVERTISED_1000baseT_Full
)) {
1746 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1752 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1754 struct rtl8169_private
*tp
= netdev_priv(dev
);
1757 del_timer_sync(&tp
->timer
);
1760 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, ethtool_cmd_speed(cmd
),
1761 cmd
->duplex
, cmd
->advertising
);
1762 rtl_unlock_work(tp
);
1767 static netdev_features_t
rtl8169_fix_features(struct net_device
*dev
,
1768 netdev_features_t features
)
1770 struct rtl8169_private
*tp
= netdev_priv(dev
);
1772 if (dev
->mtu
> TD_MSS_MAX
)
1773 features
&= ~NETIF_F_ALL_TSO
;
1775 if (dev
->mtu
> JUMBO_1K
&&
1776 !rtl_chip_infos
[tp
->mac_version
].jumbo_tx_csum
)
1777 features
&= ~NETIF_F_IP_CSUM
;
1782 static void __rtl8169_set_features(struct net_device
*dev
,
1783 netdev_features_t features
)
1785 struct rtl8169_private
*tp
= netdev_priv(dev
);
1786 netdev_features_t changed
= features
^ dev
->features
;
1787 void __iomem
*ioaddr
= tp
->mmio_addr
;
1789 if (!(changed
& (NETIF_F_RXALL
| NETIF_F_RXCSUM
|
1790 NETIF_F_HW_VLAN_CTAG_RX
)))
1793 if (changed
& (NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_RX
)) {
1794 if (features
& NETIF_F_RXCSUM
)
1795 tp
->cp_cmd
|= RxChkSum
;
1797 tp
->cp_cmd
&= ~RxChkSum
;
1799 if (dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
)
1800 tp
->cp_cmd
|= RxVlan
;
1802 tp
->cp_cmd
&= ~RxVlan
;
1804 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1807 if (changed
& NETIF_F_RXALL
) {
1808 int tmp
= (RTL_R32(RxConfig
) & ~(AcceptErr
| AcceptRunt
));
1809 if (features
& NETIF_F_RXALL
)
1810 tmp
|= (AcceptErr
| AcceptRunt
);
1811 RTL_W32(RxConfig
, tmp
);
1815 static int rtl8169_set_features(struct net_device
*dev
,
1816 netdev_features_t features
)
1818 struct rtl8169_private
*tp
= netdev_priv(dev
);
1821 __rtl8169_set_features(dev
, features
);
1822 rtl_unlock_work(tp
);
1828 static inline u32
rtl8169_tx_vlan_tag(struct sk_buff
*skb
)
1830 return (vlan_tx_tag_present(skb
)) ?
1831 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1834 static void rtl8169_rx_vlan_tag(struct RxDesc
*desc
, struct sk_buff
*skb
)
1836 u32 opts2
= le32_to_cpu(desc
->opts2
);
1838 if (opts2
& RxVlanTag
)
1839 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), swab16(opts2
& 0xffff));
1842 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1844 struct rtl8169_private
*tp
= netdev_priv(dev
);
1845 void __iomem
*ioaddr
= tp
->mmio_addr
;
1849 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1850 cmd
->port
= PORT_FIBRE
;
1851 cmd
->transceiver
= XCVR_INTERNAL
;
1853 status
= RTL_R32(TBICSR
);
1854 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1855 cmd
->autoneg
= !!(status
& TBINwEnable
);
1857 ethtool_cmd_speed_set(cmd
, SPEED_1000
);
1858 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1863 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1865 struct rtl8169_private
*tp
= netdev_priv(dev
);
1867 return mii_ethtool_gset(&tp
->mii
, cmd
);
1870 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1872 struct rtl8169_private
*tp
= netdev_priv(dev
);
1876 rc
= tp
->get_settings(dev
, cmd
);
1877 rtl_unlock_work(tp
);
1882 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1885 struct rtl8169_private
*tp
= netdev_priv(dev
);
1886 u32 __iomem
*data
= tp
->mmio_addr
;
1891 for (i
= 0; i
< R8169_REGS_SIZE
; i
+= 4)
1892 memcpy_fromio(dw
++, data
++, 4);
1893 rtl_unlock_work(tp
);
1896 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1898 struct rtl8169_private
*tp
= netdev_priv(dev
);
1900 return tp
->msg_enable
;
1903 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1905 struct rtl8169_private
*tp
= netdev_priv(dev
);
1907 tp
->msg_enable
= value
;
1910 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1917 "tx_single_collisions",
1918 "tx_multi_collisions",
1926 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1930 return ARRAY_SIZE(rtl8169_gstrings
);
1936 DECLARE_RTL_COND(rtl_counters_cond
)
1938 void __iomem
*ioaddr
= tp
->mmio_addr
;
1940 return RTL_R32(CounterAddrLow
) & CounterDump
;
1943 static void rtl8169_update_counters(struct net_device
*dev
)
1945 struct rtl8169_private
*tp
= netdev_priv(dev
);
1946 void __iomem
*ioaddr
= tp
->mmio_addr
;
1947 struct device
*d
= &tp
->pci_dev
->dev
;
1948 struct rtl8169_counters
*counters
;
1953 * Some chips are unable to dump tally counters when the receiver
1956 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1959 counters
= dma_alloc_coherent(d
, sizeof(*counters
), &paddr
, GFP_KERNEL
);
1963 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1964 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1965 RTL_W32(CounterAddrLow
, cmd
);
1966 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1968 if (rtl_udelay_loop_wait_low(tp
, &rtl_counters_cond
, 10, 1000))
1969 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1971 RTL_W32(CounterAddrLow
, 0);
1972 RTL_W32(CounterAddrHigh
, 0);
1974 dma_free_coherent(d
, sizeof(*counters
), counters
, paddr
);
1977 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1978 struct ethtool_stats
*stats
, u64
*data
)
1980 struct rtl8169_private
*tp
= netdev_priv(dev
);
1984 rtl8169_update_counters(dev
);
1986 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1987 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1988 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1989 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1990 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1991 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1992 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1993 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1994 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1995 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1996 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1997 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1998 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
2001 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
2005 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
2010 static const struct ethtool_ops rtl8169_ethtool_ops
= {
2011 .get_drvinfo
= rtl8169_get_drvinfo
,
2012 .get_regs_len
= rtl8169_get_regs_len
,
2013 .get_link
= ethtool_op_get_link
,
2014 .get_settings
= rtl8169_get_settings
,
2015 .set_settings
= rtl8169_set_settings
,
2016 .get_msglevel
= rtl8169_get_msglevel
,
2017 .set_msglevel
= rtl8169_set_msglevel
,
2018 .get_regs
= rtl8169_get_regs
,
2019 .get_wol
= rtl8169_get_wol
,
2020 .set_wol
= rtl8169_set_wol
,
2021 .get_strings
= rtl8169_get_strings
,
2022 .get_sset_count
= rtl8169_get_sset_count
,
2023 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
2024 .get_ts_info
= ethtool_op_get_ts_info
,
2027 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
2028 struct net_device
*dev
, u8 default_version
)
2030 void __iomem
*ioaddr
= tp
->mmio_addr
;
2032 * The driver currently handles the 8168Bf and the 8168Be identically
2033 * but they can be identified more specifically through the test below
2036 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2038 * Same thing for the 8101Eb and the 8101Ec:
2040 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2042 static const struct rtl_mac_info
{
2048 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44
},
2049 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42
},
2050 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41
},
2051 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40
},
2054 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38
},
2055 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36
},
2056 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35
},
2059 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34
},
2060 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33
},
2061 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32
},
2062 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33
},
2065 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
2066 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
2067 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
2069 /* 8168DP family. */
2070 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27
},
2071 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28
},
2072 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31
},
2075 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24
},
2076 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
2077 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
2078 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
2079 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
2080 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
2081 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
2082 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
2083 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
2086 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
2087 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
2088 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
2089 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
2092 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39
},
2093 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39
},
2094 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37
},
2095 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30
},
2096 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30
},
2097 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29
},
2098 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30
},
2099 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
2100 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
2101 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
2102 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
2103 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
2104 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
2105 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
2106 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
2107 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
2108 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
2109 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
2110 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
2111 /* FIXME: where did these entries come from ? -- FR */
2112 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
2113 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
2116 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
2117 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
2118 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
2119 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
2120 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
2121 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
2124 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
2126 const struct rtl_mac_info
*p
= mac_info
;
2129 reg
= RTL_R32(TxConfig
);
2130 while ((reg
& p
->mask
) != p
->val
)
2132 tp
->mac_version
= p
->mac_version
;
2134 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
2135 netif_notice(tp
, probe
, dev
,
2136 "unknown MAC, using family default\n");
2137 tp
->mac_version
= default_version
;
2138 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_42
) {
2139 tp
->mac_version
= tp
->mii
.supports_gmii
?
2140 RTL_GIGA_MAC_VER_42
:
2141 RTL_GIGA_MAC_VER_43
;
2145 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
2147 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
2155 static void rtl_writephy_batch(struct rtl8169_private
*tp
,
2156 const struct phy_reg
*regs
, int len
)
2159 rtl_writephy(tp
, regs
->reg
, regs
->val
);
2164 #define PHY_READ 0x00000000
2165 #define PHY_DATA_OR 0x10000000
2166 #define PHY_DATA_AND 0x20000000
2167 #define PHY_BJMPN 0x30000000
2168 #define PHY_MDIO_CHG 0x40000000
2169 #define PHY_CLEAR_READCOUNT 0x70000000
2170 #define PHY_WRITE 0x80000000
2171 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2172 #define PHY_COMP_EQ_SKIPN 0xa0000000
2173 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2174 #define PHY_WRITE_PREVIOUS 0xc0000000
2175 #define PHY_SKIPN 0xd0000000
2176 #define PHY_DELAY_MS 0xe0000000
2180 char version
[RTL_VER_SIZE
];
2186 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2188 static bool rtl_fw_format_ok(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2190 const struct firmware
*fw
= rtl_fw
->fw
;
2191 struct fw_info
*fw_info
= (struct fw_info
*)fw
->data
;
2192 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2193 char *version
= rtl_fw
->version
;
2196 if (fw
->size
< FW_OPCODE_SIZE
)
2199 if (!fw_info
->magic
) {
2200 size_t i
, size
, start
;
2203 if (fw
->size
< sizeof(*fw_info
))
2206 for (i
= 0; i
< fw
->size
; i
++)
2207 checksum
+= fw
->data
[i
];
2211 start
= le32_to_cpu(fw_info
->fw_start
);
2212 if (start
> fw
->size
)
2215 size
= le32_to_cpu(fw_info
->fw_len
);
2216 if (size
> (fw
->size
- start
) / FW_OPCODE_SIZE
)
2219 memcpy(version
, fw_info
->version
, RTL_VER_SIZE
);
2221 pa
->code
= (__le32
*)(fw
->data
+ start
);
2224 if (fw
->size
% FW_OPCODE_SIZE
)
2227 strlcpy(version
, rtl_lookup_firmware_name(tp
), RTL_VER_SIZE
);
2229 pa
->code
= (__le32
*)fw
->data
;
2230 pa
->size
= fw
->size
/ FW_OPCODE_SIZE
;
2232 version
[RTL_VER_SIZE
- 1] = 0;
2239 static bool rtl_fw_data_ok(struct rtl8169_private
*tp
, struct net_device
*dev
,
2240 struct rtl_fw_phy_action
*pa
)
2245 for (index
= 0; index
< pa
->size
; index
++) {
2246 u32 action
= le32_to_cpu(pa
->code
[index
]);
2247 u32 regno
= (action
& 0x0fff0000) >> 16;
2249 switch(action
& 0xf0000000) {
2254 case PHY_CLEAR_READCOUNT
:
2256 case PHY_WRITE_PREVIOUS
:
2261 if (regno
> index
) {
2262 netif_err(tp
, ifup
, tp
->dev
,
2263 "Out of range of firmware\n");
2267 case PHY_READCOUNT_EQ_SKIP
:
2268 if (index
+ 2 >= pa
->size
) {
2269 netif_err(tp
, ifup
, tp
->dev
,
2270 "Out of range of firmware\n");
2274 case PHY_COMP_EQ_SKIPN
:
2275 case PHY_COMP_NEQ_SKIPN
:
2277 if (index
+ 1 + regno
>= pa
->size
) {
2278 netif_err(tp
, ifup
, tp
->dev
,
2279 "Out of range of firmware\n");
2285 netif_err(tp
, ifup
, tp
->dev
,
2286 "Invalid action 0x%08x\n", action
);
2295 static int rtl_check_firmware(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2297 struct net_device
*dev
= tp
->dev
;
2300 if (!rtl_fw_format_ok(tp
, rtl_fw
)) {
2301 netif_err(tp
, ifup
, dev
, "invalid firwmare\n");
2305 if (rtl_fw_data_ok(tp
, dev
, &rtl_fw
->phy_action
))
2311 static void rtl_phy_write_fw(struct rtl8169_private
*tp
, struct rtl_fw
*rtl_fw
)
2313 struct rtl_fw_phy_action
*pa
= &rtl_fw
->phy_action
;
2314 struct mdio_ops org
, *ops
= &tp
->mdio_ops
;
2318 predata
= count
= 0;
2319 org
.write
= ops
->write
;
2320 org
.read
= ops
->read
;
2322 for (index
= 0; index
< pa
->size
; ) {
2323 u32 action
= le32_to_cpu(pa
->code
[index
]);
2324 u32 data
= action
& 0x0000ffff;
2325 u32 regno
= (action
& 0x0fff0000) >> 16;
2330 switch(action
& 0xf0000000) {
2332 predata
= rtl_readphy(tp
, regno
);
2349 ops
->write
= org
.write
;
2350 ops
->read
= org
.read
;
2351 } else if (data
== 1) {
2352 ops
->write
= mac_mcu_write
;
2353 ops
->read
= mac_mcu_read
;
2358 case PHY_CLEAR_READCOUNT
:
2363 rtl_writephy(tp
, regno
, data
);
2366 case PHY_READCOUNT_EQ_SKIP
:
2367 index
+= (count
== data
) ? 2 : 1;
2369 case PHY_COMP_EQ_SKIPN
:
2370 if (predata
== data
)
2374 case PHY_COMP_NEQ_SKIPN
:
2375 if (predata
!= data
)
2379 case PHY_WRITE_PREVIOUS
:
2380 rtl_writephy(tp
, regno
, predata
);
2396 ops
->write
= org
.write
;
2397 ops
->read
= org
.read
;
2400 static void rtl_release_firmware(struct rtl8169_private
*tp
)
2402 if (!IS_ERR_OR_NULL(tp
->rtl_fw
)) {
2403 release_firmware(tp
->rtl_fw
->fw
);
2406 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
2409 static void rtl_apply_firmware(struct rtl8169_private
*tp
)
2411 struct rtl_fw
*rtl_fw
= tp
->rtl_fw
;
2413 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2414 if (!IS_ERR_OR_NULL(rtl_fw
))
2415 rtl_phy_write_fw(tp
, rtl_fw
);
2418 static void rtl_apply_firmware_cond(struct rtl8169_private
*tp
, u8 reg
, u16 val
)
2420 if (rtl_readphy(tp
, reg
) != val
)
2421 netif_warn(tp
, hw
, tp
->dev
, "chipset not ready for firmware\n");
2423 rtl_apply_firmware(tp
);
2426 static void rtl8169s_hw_phy_config(struct rtl8169_private
*tp
)
2428 static const struct phy_reg phy_reg_init
[] = {
2490 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2493 static void rtl8169sb_hw_phy_config(struct rtl8169_private
*tp
)
2495 static const struct phy_reg phy_reg_init
[] = {
2501 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2504 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
)
2506 struct pci_dev
*pdev
= tp
->pci_dev
;
2508 if ((pdev
->subsystem_vendor
!= PCI_VENDOR_ID_GIGABYTE
) ||
2509 (pdev
->subsystem_device
!= 0xe000))
2512 rtl_writephy(tp
, 0x1f, 0x0001);
2513 rtl_writephy(tp
, 0x10, 0xf01b);
2514 rtl_writephy(tp
, 0x1f, 0x0000);
2517 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
)
2519 static const struct phy_reg phy_reg_init
[] = {
2559 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2561 rtl8169scd_hw_phy_config_quirk(tp
);
2564 static void rtl8169sce_hw_phy_config(struct rtl8169_private
*tp
)
2566 static const struct phy_reg phy_reg_init
[] = {
2614 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2617 static void rtl8168bb_hw_phy_config(struct rtl8169_private
*tp
)
2619 static const struct phy_reg phy_reg_init
[] = {
2624 rtl_writephy(tp
, 0x1f, 0x0001);
2625 rtl_patchphy(tp
, 0x16, 1 << 0);
2627 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2630 static void rtl8168bef_hw_phy_config(struct rtl8169_private
*tp
)
2632 static const struct phy_reg phy_reg_init
[] = {
2638 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2641 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private
*tp
)
2643 static const struct phy_reg phy_reg_init
[] = {
2651 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2654 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private
*tp
)
2656 static const struct phy_reg phy_reg_init
[] = {
2662 rtl_writephy(tp
, 0x1f, 0x0000);
2663 rtl_patchphy(tp
, 0x14, 1 << 5);
2664 rtl_patchphy(tp
, 0x0d, 1 << 5);
2666 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2669 static void rtl8168c_1_hw_phy_config(struct rtl8169_private
*tp
)
2671 static const struct phy_reg phy_reg_init
[] = {
2691 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2693 rtl_patchphy(tp
, 0x14, 1 << 5);
2694 rtl_patchphy(tp
, 0x0d, 1 << 5);
2695 rtl_writephy(tp
, 0x1f, 0x0000);
2698 static void rtl8168c_2_hw_phy_config(struct rtl8169_private
*tp
)
2700 static const struct phy_reg phy_reg_init
[] = {
2718 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2720 rtl_patchphy(tp
, 0x16, 1 << 0);
2721 rtl_patchphy(tp
, 0x14, 1 << 5);
2722 rtl_patchphy(tp
, 0x0d, 1 << 5);
2723 rtl_writephy(tp
, 0x1f, 0x0000);
2726 static void rtl8168c_3_hw_phy_config(struct rtl8169_private
*tp
)
2728 static const struct phy_reg phy_reg_init
[] = {
2740 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2742 rtl_patchphy(tp
, 0x16, 1 << 0);
2743 rtl_patchphy(tp
, 0x14, 1 << 5);
2744 rtl_patchphy(tp
, 0x0d, 1 << 5);
2745 rtl_writephy(tp
, 0x1f, 0x0000);
2748 static void rtl8168c_4_hw_phy_config(struct rtl8169_private
*tp
)
2750 rtl8168c_3_hw_phy_config(tp
);
2753 static void rtl8168d_1_hw_phy_config(struct rtl8169_private
*tp
)
2755 static const struct phy_reg phy_reg_init_0
[] = {
2756 /* Channel Estimation */
2777 * Enhance line driver power
2786 * Can not link to 1Gbps with bad cable
2787 * Decrease SNR threshold form 21.07dB to 19.04dB
2796 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2800 * Fine Tune Switching regulator parameter
2802 rtl_writephy(tp
, 0x1f, 0x0002);
2803 rtl_w1w0_phy(tp
, 0x0b, 0x0010, 0x00ef);
2804 rtl_w1w0_phy(tp
, 0x0c, 0xa200, 0x5d00);
2806 if (rtl8168d_efuse_read(tp
, 0x01) == 0xb1) {
2807 static const struct phy_reg phy_reg_init
[] = {
2817 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2819 val
= rtl_readphy(tp
, 0x0d);
2821 if ((val
& 0x00ff) != 0x006c) {
2822 static const u32 set
[] = {
2823 0x0065, 0x0066, 0x0067, 0x0068,
2824 0x0069, 0x006a, 0x006b, 0x006c
2828 rtl_writephy(tp
, 0x1f, 0x0002);
2831 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2832 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2835 static const struct phy_reg phy_reg_init
[] = {
2843 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2846 /* RSET couple improve */
2847 rtl_writephy(tp
, 0x1f, 0x0002);
2848 rtl_patchphy(tp
, 0x0d, 0x0300);
2849 rtl_patchphy(tp
, 0x0f, 0x0010);
2851 /* Fine tune PLL performance */
2852 rtl_writephy(tp
, 0x1f, 0x0002);
2853 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2854 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2856 rtl_writephy(tp
, 0x1f, 0x0005);
2857 rtl_writephy(tp
, 0x05, 0x001b);
2859 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xbf00);
2861 rtl_writephy(tp
, 0x1f, 0x0000);
2864 static void rtl8168d_2_hw_phy_config(struct rtl8169_private
*tp
)
2866 static const struct phy_reg phy_reg_init_0
[] = {
2867 /* Channel Estimation */
2888 * Enhance line driver power
2897 * Can not link to 1Gbps with bad cable
2898 * Decrease SNR threshold form 21.07dB to 19.04dB
2907 rtl_writephy_batch(tp
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2909 if (rtl8168d_efuse_read(tp
, 0x01) == 0xb1) {
2910 static const struct phy_reg phy_reg_init
[] = {
2921 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2923 val
= rtl_readphy(tp
, 0x0d);
2924 if ((val
& 0x00ff) != 0x006c) {
2925 static const u32 set
[] = {
2926 0x0065, 0x0066, 0x0067, 0x0068,
2927 0x0069, 0x006a, 0x006b, 0x006c
2931 rtl_writephy(tp
, 0x1f, 0x0002);
2934 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2935 rtl_writephy(tp
, 0x0d, val
| set
[i
]);
2938 static const struct phy_reg phy_reg_init
[] = {
2946 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2949 /* Fine tune PLL performance */
2950 rtl_writephy(tp
, 0x1f, 0x0002);
2951 rtl_w1w0_phy(tp
, 0x02, 0x0100, 0x0600);
2952 rtl_w1w0_phy(tp
, 0x03, 0x0000, 0xe000);
2954 /* Switching regulator Slew rate */
2955 rtl_writephy(tp
, 0x1f, 0x0002);
2956 rtl_patchphy(tp
, 0x0f, 0x0017);
2958 rtl_writephy(tp
, 0x1f, 0x0005);
2959 rtl_writephy(tp
, 0x05, 0x001b);
2961 rtl_apply_firmware_cond(tp
, MII_EXPANSION
, 0xb300);
2963 rtl_writephy(tp
, 0x1f, 0x0000);
2966 static void rtl8168d_3_hw_phy_config(struct rtl8169_private
*tp
)
2968 static const struct phy_reg phy_reg_init
[] = {
3024 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3027 static void rtl8168d_4_hw_phy_config(struct rtl8169_private
*tp
)
3029 static const struct phy_reg phy_reg_init
[] = {
3039 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3040 rtl_patchphy(tp
, 0x0d, 1 << 5);
3043 static void rtl8168e_1_hw_phy_config(struct rtl8169_private
*tp
)
3045 static const struct phy_reg phy_reg_init
[] = {
3046 /* Enable Delay cap */
3052 /* Channel estimation fine tune */
3061 /* Update PFM & 10M TX idle timer */
3073 rtl_apply_firmware(tp
);
3075 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3077 /* DCO enable for 10M IDLE Power */
3078 rtl_writephy(tp
, 0x1f, 0x0007);
3079 rtl_writephy(tp
, 0x1e, 0x0023);
3080 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
3081 rtl_writephy(tp
, 0x1f, 0x0000);
3083 /* For impedance matching */
3084 rtl_writephy(tp
, 0x1f, 0x0002);
3085 rtl_w1w0_phy(tp
, 0x08, 0x8000, 0x7f00);
3086 rtl_writephy(tp
, 0x1f, 0x0000);
3088 /* PHY auto speed down */
3089 rtl_writephy(tp
, 0x1f, 0x0007);
3090 rtl_writephy(tp
, 0x1e, 0x002d);
3091 rtl_w1w0_phy(tp
, 0x18, 0x0050, 0x0000);
3092 rtl_writephy(tp
, 0x1f, 0x0000);
3093 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
3095 rtl_writephy(tp
, 0x1f, 0x0005);
3096 rtl_writephy(tp
, 0x05, 0x8b86);
3097 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
3098 rtl_writephy(tp
, 0x1f, 0x0000);
3100 rtl_writephy(tp
, 0x1f, 0x0005);
3101 rtl_writephy(tp
, 0x05, 0x8b85);
3102 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
3103 rtl_writephy(tp
, 0x1f, 0x0007);
3104 rtl_writephy(tp
, 0x1e, 0x0020);
3105 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x1100);
3106 rtl_writephy(tp
, 0x1f, 0x0006);
3107 rtl_writephy(tp
, 0x00, 0x5a00);
3108 rtl_writephy(tp
, 0x1f, 0x0000);
3109 rtl_writephy(tp
, 0x0d, 0x0007);
3110 rtl_writephy(tp
, 0x0e, 0x003c);
3111 rtl_writephy(tp
, 0x0d, 0x4007);
3112 rtl_writephy(tp
, 0x0e, 0x0000);
3113 rtl_writephy(tp
, 0x0d, 0x0000);
3116 static void rtl_rar_exgmac_set(struct rtl8169_private
*tp
, u8
*addr
)
3119 addr
[0] | (addr
[1] << 8),
3120 addr
[2] | (addr
[3] << 8),
3121 addr
[4] | (addr
[5] << 8)
3123 const struct exgmac_reg e
[] = {
3124 { .addr
= 0xe0, ERIAR_MASK_1111
, .val
= w
[0] | (w
[1] << 16) },
3125 { .addr
= 0xe4, ERIAR_MASK_1111
, .val
= w
[2] },
3126 { .addr
= 0xf0, ERIAR_MASK_1111
, .val
= w
[0] << 16 },
3127 { .addr
= 0xf4, ERIAR_MASK_1111
, .val
= w
[1] | (w
[2] << 16) }
3130 rtl_write_exgmac_batch(tp
, e
, ARRAY_SIZE(e
));
3133 static void rtl8168e_2_hw_phy_config(struct rtl8169_private
*tp
)
3135 static const struct phy_reg phy_reg_init
[] = {
3136 /* Enable Delay cap */
3145 /* Channel estimation fine tune */
3162 rtl_apply_firmware(tp
);
3164 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3166 /* For 4-corner performance improve */
3167 rtl_writephy(tp
, 0x1f, 0x0005);
3168 rtl_writephy(tp
, 0x05, 0x8b80);
3169 rtl_w1w0_phy(tp
, 0x17, 0x0006, 0x0000);
3170 rtl_writephy(tp
, 0x1f, 0x0000);
3172 /* PHY auto speed down */
3173 rtl_writephy(tp
, 0x1f, 0x0004);
3174 rtl_writephy(tp
, 0x1f, 0x0007);
3175 rtl_writephy(tp
, 0x1e, 0x002d);
3176 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
3177 rtl_writephy(tp
, 0x1f, 0x0002);
3178 rtl_writephy(tp
, 0x1f, 0x0000);
3179 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
3181 /* improve 10M EEE waveform */
3182 rtl_writephy(tp
, 0x1f, 0x0005);
3183 rtl_writephy(tp
, 0x05, 0x8b86);
3184 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
3185 rtl_writephy(tp
, 0x1f, 0x0000);
3187 /* Improve 2-pair detection performance */
3188 rtl_writephy(tp
, 0x1f, 0x0005);
3189 rtl_writephy(tp
, 0x05, 0x8b85);
3190 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
3191 rtl_writephy(tp
, 0x1f, 0x0000);
3194 rtl_w1w0_eri(tp
, 0x1b0, ERIAR_MASK_1111
, 0x0000, 0x0003, ERIAR_EXGMAC
);
3195 rtl_writephy(tp
, 0x1f, 0x0005);
3196 rtl_writephy(tp
, 0x05, 0x8b85);
3197 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
3198 rtl_writephy(tp
, 0x1f, 0x0004);
3199 rtl_writephy(tp
, 0x1f, 0x0007);
3200 rtl_writephy(tp
, 0x1e, 0x0020);
3201 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x0100);
3202 rtl_writephy(tp
, 0x1f, 0x0002);
3203 rtl_writephy(tp
, 0x1f, 0x0000);
3204 rtl_writephy(tp
, 0x0d, 0x0007);
3205 rtl_writephy(tp
, 0x0e, 0x003c);
3206 rtl_writephy(tp
, 0x0d, 0x4007);
3207 rtl_writephy(tp
, 0x0e, 0x0000);
3208 rtl_writephy(tp
, 0x0d, 0x0000);
3211 rtl_writephy(tp
, 0x1f, 0x0003);
3212 rtl_w1w0_phy(tp
, 0x19, 0x0000, 0x0001);
3213 rtl_w1w0_phy(tp
, 0x10, 0x0000, 0x0400);
3214 rtl_writephy(tp
, 0x1f, 0x0000);
3216 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3217 rtl_rar_exgmac_set(tp
, tp
->dev
->dev_addr
);
3220 static void rtl8168f_hw_phy_config(struct rtl8169_private
*tp
)
3222 /* For 4-corner performance improve */
3223 rtl_writephy(tp
, 0x1f, 0x0005);
3224 rtl_writephy(tp
, 0x05, 0x8b80);
3225 rtl_w1w0_phy(tp
, 0x06, 0x0006, 0x0000);
3226 rtl_writephy(tp
, 0x1f, 0x0000);
3228 /* PHY auto speed down */
3229 rtl_writephy(tp
, 0x1f, 0x0007);
3230 rtl_writephy(tp
, 0x1e, 0x002d);
3231 rtl_w1w0_phy(tp
, 0x18, 0x0010, 0x0000);
3232 rtl_writephy(tp
, 0x1f, 0x0000);
3233 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
3235 /* Improve 10M EEE waveform */
3236 rtl_writephy(tp
, 0x1f, 0x0005);
3237 rtl_writephy(tp
, 0x05, 0x8b86);
3238 rtl_w1w0_phy(tp
, 0x06, 0x0001, 0x0000);
3239 rtl_writephy(tp
, 0x1f, 0x0000);
3242 static void rtl8168f_1_hw_phy_config(struct rtl8169_private
*tp
)
3244 static const struct phy_reg phy_reg_init
[] = {
3245 /* Channel estimation fine tune */
3250 /* Modify green table for giga & fnet */
3267 /* Modify green table for 10M */
3273 /* Disable hiimpedance detection (RTCT) */
3279 rtl_apply_firmware(tp
);
3281 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3283 rtl8168f_hw_phy_config(tp
);
3285 /* Improve 2-pair detection performance */
3286 rtl_writephy(tp
, 0x1f, 0x0005);
3287 rtl_writephy(tp
, 0x05, 0x8b85);
3288 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
3289 rtl_writephy(tp
, 0x1f, 0x0000);
3292 static void rtl8168f_2_hw_phy_config(struct rtl8169_private
*tp
)
3294 rtl_apply_firmware(tp
);
3296 rtl8168f_hw_phy_config(tp
);
3299 static void rtl8411_hw_phy_config(struct rtl8169_private
*tp
)
3301 static const struct phy_reg phy_reg_init
[] = {
3302 /* Channel estimation fine tune */
3307 /* Modify green table for giga & fnet */
3324 /* Modify green table for 10M */
3330 /* Disable hiimpedance detection (RTCT) */
3337 rtl_apply_firmware(tp
);
3339 rtl8168f_hw_phy_config(tp
);
3341 /* Improve 2-pair detection performance */
3342 rtl_writephy(tp
, 0x1f, 0x0005);
3343 rtl_writephy(tp
, 0x05, 0x8b85);
3344 rtl_w1w0_phy(tp
, 0x06, 0x4000, 0x0000);
3345 rtl_writephy(tp
, 0x1f, 0x0000);
3347 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3349 /* Modify green table for giga */
3350 rtl_writephy(tp
, 0x1f, 0x0005);
3351 rtl_writephy(tp
, 0x05, 0x8b54);
3352 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x0800);
3353 rtl_writephy(tp
, 0x05, 0x8b5d);
3354 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x0800);
3355 rtl_writephy(tp
, 0x05, 0x8a7c);
3356 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x0100);
3357 rtl_writephy(tp
, 0x05, 0x8a7f);
3358 rtl_w1w0_phy(tp
, 0x06, 0x0100, 0x0000);
3359 rtl_writephy(tp
, 0x05, 0x8a82);
3360 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x0100);
3361 rtl_writephy(tp
, 0x05, 0x8a85);
3362 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x0100);
3363 rtl_writephy(tp
, 0x05, 0x8a88);
3364 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x0100);
3365 rtl_writephy(tp
, 0x1f, 0x0000);
3367 /* uc same-seed solution */
3368 rtl_writephy(tp
, 0x1f, 0x0005);
3369 rtl_writephy(tp
, 0x05, 0x8b85);
3370 rtl_w1w0_phy(tp
, 0x06, 0x8000, 0x0000);
3371 rtl_writephy(tp
, 0x1f, 0x0000);
3374 rtl_w1w0_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x00, 0x03, ERIAR_EXGMAC
);
3375 rtl_writephy(tp
, 0x1f, 0x0005);
3376 rtl_writephy(tp
, 0x05, 0x8b85);
3377 rtl_w1w0_phy(tp
, 0x06, 0x0000, 0x2000);
3378 rtl_writephy(tp
, 0x1f, 0x0004);
3379 rtl_writephy(tp
, 0x1f, 0x0007);
3380 rtl_writephy(tp
, 0x1e, 0x0020);
3381 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x0100);
3382 rtl_writephy(tp
, 0x1f, 0x0000);
3383 rtl_writephy(tp
, 0x0d, 0x0007);
3384 rtl_writephy(tp
, 0x0e, 0x003c);
3385 rtl_writephy(tp
, 0x0d, 0x4007);
3386 rtl_writephy(tp
, 0x0e, 0x0000);
3387 rtl_writephy(tp
, 0x0d, 0x0000);
3390 rtl_writephy(tp
, 0x1f, 0x0003);
3391 rtl_w1w0_phy(tp
, 0x19, 0x0000, 0x0001);
3392 rtl_w1w0_phy(tp
, 0x10, 0x0000, 0x0400);
3393 rtl_writephy(tp
, 0x1f, 0x0000);
3396 static void rtl8168g_1_hw_phy_config(struct rtl8169_private
*tp
)
3398 rtl_apply_firmware(tp
);
3400 rtl_writephy(tp
, 0x1f, 0x0a46);
3401 if (rtl_readphy(tp
, 0x10) & 0x0100) {
3402 rtl_writephy(tp
, 0x1f, 0x0bcc);
3403 rtl_w1w0_phy(tp
, 0x12, 0x0000, 0x8000);
3405 rtl_writephy(tp
, 0x1f, 0x0bcc);
3406 rtl_w1w0_phy(tp
, 0x12, 0x8000, 0x0000);
3409 rtl_writephy(tp
, 0x1f, 0x0a46);
3410 if (rtl_readphy(tp
, 0x13) & 0x0100) {
3411 rtl_writephy(tp
, 0x1f, 0x0c41);
3412 rtl_w1w0_phy(tp
, 0x15, 0x0002, 0x0000);
3414 rtl_writephy(tp
, 0x1f, 0x0c41);
3415 rtl_w1w0_phy(tp
, 0x15, 0x0000, 0x0002);
3418 /* Enable PHY auto speed down */
3419 rtl_writephy(tp
, 0x1f, 0x0a44);
3420 rtl_w1w0_phy(tp
, 0x11, 0x000c, 0x0000);
3422 rtl_writephy(tp
, 0x1f, 0x0bcc);
3423 rtl_w1w0_phy(tp
, 0x14, 0x0100, 0x0000);
3424 rtl_writephy(tp
, 0x1f, 0x0a44);
3425 rtl_w1w0_phy(tp
, 0x11, 0x00c0, 0x0000);
3426 rtl_writephy(tp
, 0x1f, 0x0a43);
3427 rtl_writephy(tp
, 0x13, 0x8084);
3428 rtl_w1w0_phy(tp
, 0x14, 0x0000, 0x6000);
3429 rtl_w1w0_phy(tp
, 0x10, 0x1003, 0x0000);
3431 /* EEE auto-fallback function */
3432 rtl_writephy(tp
, 0x1f, 0x0a4b);
3433 rtl_w1w0_phy(tp
, 0x11, 0x0004, 0x0000);
3435 /* Enable UC LPF tune function */
3436 rtl_writephy(tp
, 0x1f, 0x0a43);
3437 rtl_writephy(tp
, 0x13, 0x8012);
3438 rtl_w1w0_phy(tp
, 0x14, 0x8000, 0x0000);
3440 rtl_writephy(tp
, 0x1f, 0x0c42);
3441 rtl_w1w0_phy(tp
, 0x11, 0x4000, 0x2000);
3443 /* Improve SWR Efficiency */
3444 rtl_writephy(tp
, 0x1f, 0x0bcd);
3445 rtl_writephy(tp
, 0x14, 0x5065);
3446 rtl_writephy(tp
, 0x14, 0xd065);
3447 rtl_writephy(tp
, 0x1f, 0x0bc8);
3448 rtl_writephy(tp
, 0x11, 0x5655);
3449 rtl_writephy(tp
, 0x1f, 0x0bcd);
3450 rtl_writephy(tp
, 0x14, 0x1065);
3451 rtl_writephy(tp
, 0x14, 0x9065);
3452 rtl_writephy(tp
, 0x14, 0x1065);
3454 /* Check ALDPS bit, disable it if enabled */
3455 rtl_writephy(tp
, 0x1f, 0x0a43);
3456 if (rtl_readphy(tp
, 0x10) & 0x0004)
3457 rtl_w1w0_phy(tp
, 0x10, 0x0000, 0x0004);
3459 rtl_writephy(tp
, 0x1f, 0x0000);
3462 static void rtl8168g_2_hw_phy_config(struct rtl8169_private
*tp
)
3464 rtl_apply_firmware(tp
);
3467 static void rtl8102e_hw_phy_config(struct rtl8169_private
*tp
)
3469 static const struct phy_reg phy_reg_init
[] = {
3476 rtl_writephy(tp
, 0x1f, 0x0000);
3477 rtl_patchphy(tp
, 0x11, 1 << 12);
3478 rtl_patchphy(tp
, 0x19, 1 << 13);
3479 rtl_patchphy(tp
, 0x10, 1 << 15);
3481 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3484 static void rtl8105e_hw_phy_config(struct rtl8169_private
*tp
)
3486 static const struct phy_reg phy_reg_init
[] = {
3500 /* Disable ALDPS before ram code */
3501 rtl_writephy(tp
, 0x1f, 0x0000);
3502 rtl_writephy(tp
, 0x18, 0x0310);
3505 rtl_apply_firmware(tp
);
3507 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3510 static void rtl8402_hw_phy_config(struct rtl8169_private
*tp
)
3512 /* Disable ALDPS before setting firmware */
3513 rtl_writephy(tp
, 0x1f, 0x0000);
3514 rtl_writephy(tp
, 0x18, 0x0310);
3517 rtl_apply_firmware(tp
);
3520 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
3521 rtl_writephy(tp
, 0x1f, 0x0004);
3522 rtl_writephy(tp
, 0x10, 0x401f);
3523 rtl_writephy(tp
, 0x19, 0x7030);
3524 rtl_writephy(tp
, 0x1f, 0x0000);
3527 static void rtl8106e_hw_phy_config(struct rtl8169_private
*tp
)
3529 static const struct phy_reg phy_reg_init
[] = {
3536 /* Disable ALDPS before ram code */
3537 rtl_writephy(tp
, 0x1f, 0x0000);
3538 rtl_writephy(tp
, 0x18, 0x0310);
3541 rtl_apply_firmware(tp
);
3543 rtl_eri_write(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
3544 rtl_writephy_batch(tp
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
3546 rtl_eri_write(tp
, 0x1d0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
3549 static void rtl_hw_phy_config(struct net_device
*dev
)
3551 struct rtl8169_private
*tp
= netdev_priv(dev
);
3553 rtl8169_print_mac_version(tp
);
3555 switch (tp
->mac_version
) {
3556 case RTL_GIGA_MAC_VER_01
:
3558 case RTL_GIGA_MAC_VER_02
:
3559 case RTL_GIGA_MAC_VER_03
:
3560 rtl8169s_hw_phy_config(tp
);
3562 case RTL_GIGA_MAC_VER_04
:
3563 rtl8169sb_hw_phy_config(tp
);
3565 case RTL_GIGA_MAC_VER_05
:
3566 rtl8169scd_hw_phy_config(tp
);
3568 case RTL_GIGA_MAC_VER_06
:
3569 rtl8169sce_hw_phy_config(tp
);
3571 case RTL_GIGA_MAC_VER_07
:
3572 case RTL_GIGA_MAC_VER_08
:
3573 case RTL_GIGA_MAC_VER_09
:
3574 rtl8102e_hw_phy_config(tp
);
3576 case RTL_GIGA_MAC_VER_11
:
3577 rtl8168bb_hw_phy_config(tp
);
3579 case RTL_GIGA_MAC_VER_12
:
3580 rtl8168bef_hw_phy_config(tp
);
3582 case RTL_GIGA_MAC_VER_17
:
3583 rtl8168bef_hw_phy_config(tp
);
3585 case RTL_GIGA_MAC_VER_18
:
3586 rtl8168cp_1_hw_phy_config(tp
);
3588 case RTL_GIGA_MAC_VER_19
:
3589 rtl8168c_1_hw_phy_config(tp
);
3591 case RTL_GIGA_MAC_VER_20
:
3592 rtl8168c_2_hw_phy_config(tp
);
3594 case RTL_GIGA_MAC_VER_21
:
3595 rtl8168c_3_hw_phy_config(tp
);
3597 case RTL_GIGA_MAC_VER_22
:
3598 rtl8168c_4_hw_phy_config(tp
);
3600 case RTL_GIGA_MAC_VER_23
:
3601 case RTL_GIGA_MAC_VER_24
:
3602 rtl8168cp_2_hw_phy_config(tp
);
3604 case RTL_GIGA_MAC_VER_25
:
3605 rtl8168d_1_hw_phy_config(tp
);
3607 case RTL_GIGA_MAC_VER_26
:
3608 rtl8168d_2_hw_phy_config(tp
);
3610 case RTL_GIGA_MAC_VER_27
:
3611 rtl8168d_3_hw_phy_config(tp
);
3613 case RTL_GIGA_MAC_VER_28
:
3614 rtl8168d_4_hw_phy_config(tp
);
3616 case RTL_GIGA_MAC_VER_29
:
3617 case RTL_GIGA_MAC_VER_30
:
3618 rtl8105e_hw_phy_config(tp
);
3620 case RTL_GIGA_MAC_VER_31
:
3623 case RTL_GIGA_MAC_VER_32
:
3624 case RTL_GIGA_MAC_VER_33
:
3625 rtl8168e_1_hw_phy_config(tp
);
3627 case RTL_GIGA_MAC_VER_34
:
3628 rtl8168e_2_hw_phy_config(tp
);
3630 case RTL_GIGA_MAC_VER_35
:
3631 rtl8168f_1_hw_phy_config(tp
);
3633 case RTL_GIGA_MAC_VER_36
:
3634 rtl8168f_2_hw_phy_config(tp
);
3637 case RTL_GIGA_MAC_VER_37
:
3638 rtl8402_hw_phy_config(tp
);
3641 case RTL_GIGA_MAC_VER_38
:
3642 rtl8411_hw_phy_config(tp
);
3645 case RTL_GIGA_MAC_VER_39
:
3646 rtl8106e_hw_phy_config(tp
);
3649 case RTL_GIGA_MAC_VER_40
:
3650 rtl8168g_1_hw_phy_config(tp
);
3652 case RTL_GIGA_MAC_VER_42
:
3653 case RTL_GIGA_MAC_VER_43
:
3654 case RTL_GIGA_MAC_VER_44
:
3655 rtl8168g_2_hw_phy_config(tp
);
3658 case RTL_GIGA_MAC_VER_41
:
3664 static void rtl_phy_work(struct rtl8169_private
*tp
)
3666 struct timer_list
*timer
= &tp
->timer
;
3667 void __iomem
*ioaddr
= tp
->mmio_addr
;
3668 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
3670 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
3672 if (tp
->phy_reset_pending(tp
)) {
3674 * A busy loop could burn quite a few cycles on nowadays CPU.
3675 * Let's delay the execution of the timer for a few ticks.
3681 if (tp
->link_ok(ioaddr
))
3684 netif_dbg(tp
, link
, tp
->dev
, "PHY reset until link up\n");
3686 tp
->phy_reset_enable(tp
);
3689 mod_timer(timer
, jiffies
+ timeout
);
3692 static void rtl_schedule_task(struct rtl8169_private
*tp
, enum rtl_flag flag
)
3694 if (!test_and_set_bit(flag
, tp
->wk
.flags
))
3695 schedule_work(&tp
->wk
.work
);
3698 static void rtl8169_phy_timer(unsigned long __opaque
)
3700 struct net_device
*dev
= (struct net_device
*)__opaque
;
3701 struct rtl8169_private
*tp
= netdev_priv(dev
);
3703 rtl_schedule_task(tp
, RTL_FLAG_TASK_PHY_PENDING
);
3706 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
3707 void __iomem
*ioaddr
)
3710 pci_release_regions(pdev
);
3711 pci_clear_mwi(pdev
);
3712 pci_disable_device(pdev
);
3716 DECLARE_RTL_COND(rtl_phy_reset_cond
)
3718 return tp
->phy_reset_pending(tp
);
3721 static void rtl8169_phy_reset(struct net_device
*dev
,
3722 struct rtl8169_private
*tp
)
3724 tp
->phy_reset_enable(tp
);
3725 rtl_msleep_loop_wait_low(tp
, &rtl_phy_reset_cond
, 1, 100);
3728 static bool rtl_tbi_enabled(struct rtl8169_private
*tp
)
3730 void __iomem
*ioaddr
= tp
->mmio_addr
;
3732 return (tp
->mac_version
== RTL_GIGA_MAC_VER_01
) &&
3733 (RTL_R8(PHYstatus
) & TBI_Enable
);
3736 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
3738 void __iomem
*ioaddr
= tp
->mmio_addr
;
3740 rtl_hw_phy_config(dev
);
3742 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
3743 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3747 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
3749 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
3750 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
3752 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
3753 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3755 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3756 rtl_writephy(tp
, 0x0b, 0x0000); //w 0x0b 15 0 0
3759 rtl8169_phy_reset(dev
, tp
);
3761 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
3762 ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
3763 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
3764 (tp
->mii
.supports_gmii
?
3765 ADVERTISED_1000baseT_Half
|
3766 ADVERTISED_1000baseT_Full
: 0));
3768 if (rtl_tbi_enabled(tp
))
3769 netif_info(tp
, link
, dev
, "TBI auto-negotiating\n");
3772 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
3774 void __iomem
*ioaddr
= tp
->mmio_addr
;
3778 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3780 RTL_W32(MAC4
, addr
[4] | addr
[5] << 8);
3783 RTL_W32(MAC0
, addr
[0] | addr
[1] << 8 | addr
[2] << 16 | addr
[3] << 24);
3786 if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
)
3787 rtl_rar_exgmac_set(tp
, addr
);
3789 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3791 rtl_unlock_work(tp
);
3794 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
3796 struct rtl8169_private
*tp
= netdev_priv(dev
);
3797 struct sockaddr
*addr
= p
;
3799 if (!is_valid_ether_addr(addr
->sa_data
))
3800 return -EADDRNOTAVAIL
;
3802 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
3804 rtl_rar_set(tp
, dev
->dev_addr
);
3809 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3811 struct rtl8169_private
*tp
= netdev_priv(dev
);
3812 struct mii_ioctl_data
*data
= if_mii(ifr
);
3814 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
3817 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
,
3818 struct mii_ioctl_data
*data
, int cmd
)
3822 data
->phy_id
= 32; /* Internal PHY */
3826 data
->val_out
= rtl_readphy(tp
, data
->reg_num
& 0x1f);
3830 rtl_writephy(tp
, data
->reg_num
& 0x1f, data
->val_in
);
3836 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
3841 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
3843 if (tp
->features
& RTL_FEATURE_MSI
) {
3844 pci_disable_msi(pdev
);
3845 tp
->features
&= ~RTL_FEATURE_MSI
;
3849 static void rtl_init_mdio_ops(struct rtl8169_private
*tp
)
3851 struct mdio_ops
*ops
= &tp
->mdio_ops
;
3853 switch (tp
->mac_version
) {
3854 case RTL_GIGA_MAC_VER_27
:
3855 ops
->write
= r8168dp_1_mdio_write
;
3856 ops
->read
= r8168dp_1_mdio_read
;
3858 case RTL_GIGA_MAC_VER_28
:
3859 case RTL_GIGA_MAC_VER_31
:
3860 ops
->write
= r8168dp_2_mdio_write
;
3861 ops
->read
= r8168dp_2_mdio_read
;
3863 case RTL_GIGA_MAC_VER_40
:
3864 case RTL_GIGA_MAC_VER_41
:
3865 case RTL_GIGA_MAC_VER_42
:
3866 case RTL_GIGA_MAC_VER_43
:
3867 case RTL_GIGA_MAC_VER_44
:
3868 ops
->write
= r8168g_mdio_write
;
3869 ops
->read
= r8168g_mdio_read
;
3872 ops
->write
= r8169_mdio_write
;
3873 ops
->read
= r8169_mdio_read
;
3878 static void rtl_speed_down(struct rtl8169_private
*tp
)
3883 rtl_writephy(tp
, 0x1f, 0x0000);
3884 lpa
= rtl_readphy(tp
, MII_LPA
);
3886 if (lpa
& (LPA_10HALF
| LPA_10FULL
))
3887 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
;
3888 else if (lpa
& (LPA_100HALF
| LPA_100FULL
))
3889 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
3890 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
3892 adv
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
3893 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
|
3894 (tp
->mii
.supports_gmii
?
3895 ADVERTISED_1000baseT_Half
|
3896 ADVERTISED_1000baseT_Full
: 0);
3898 rtl8169_set_speed(tp
->dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
,
3902 static void rtl_wol_suspend_quirk(struct rtl8169_private
*tp
)
3904 void __iomem
*ioaddr
= tp
->mmio_addr
;
3906 switch (tp
->mac_version
) {
3907 case RTL_GIGA_MAC_VER_25
:
3908 case RTL_GIGA_MAC_VER_26
:
3909 case RTL_GIGA_MAC_VER_29
:
3910 case RTL_GIGA_MAC_VER_30
:
3911 case RTL_GIGA_MAC_VER_32
:
3912 case RTL_GIGA_MAC_VER_33
:
3913 case RTL_GIGA_MAC_VER_34
:
3914 case RTL_GIGA_MAC_VER_37
:
3915 case RTL_GIGA_MAC_VER_38
:
3916 case RTL_GIGA_MAC_VER_39
:
3917 case RTL_GIGA_MAC_VER_40
:
3918 case RTL_GIGA_MAC_VER_41
:
3919 case RTL_GIGA_MAC_VER_42
:
3920 case RTL_GIGA_MAC_VER_43
:
3921 case RTL_GIGA_MAC_VER_44
:
3922 RTL_W32(RxConfig
, RTL_R32(RxConfig
) |
3923 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
);
3930 static bool rtl_wol_pll_power_down(struct rtl8169_private
*tp
)
3932 if (!(__rtl8169_get_wol(tp
) & WAKE_ANY
))
3936 rtl_wol_suspend_quirk(tp
);
3941 static void r810x_phy_power_down(struct rtl8169_private
*tp
)
3943 rtl_writephy(tp
, 0x1f, 0x0000);
3944 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3947 static void r810x_phy_power_up(struct rtl8169_private
*tp
)
3949 rtl_writephy(tp
, 0x1f, 0x0000);
3950 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
3953 static void r810x_pll_power_down(struct rtl8169_private
*tp
)
3955 void __iomem
*ioaddr
= tp
->mmio_addr
;
3957 if (rtl_wol_pll_power_down(tp
))
3960 r810x_phy_power_down(tp
);
3962 switch (tp
->mac_version
) {
3963 case RTL_GIGA_MAC_VER_07
:
3964 case RTL_GIGA_MAC_VER_08
:
3965 case RTL_GIGA_MAC_VER_09
:
3966 case RTL_GIGA_MAC_VER_10
:
3967 case RTL_GIGA_MAC_VER_13
:
3968 case RTL_GIGA_MAC_VER_16
:
3971 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
3976 static void r810x_pll_power_up(struct rtl8169_private
*tp
)
3978 void __iomem
*ioaddr
= tp
->mmio_addr
;
3980 r810x_phy_power_up(tp
);
3982 switch (tp
->mac_version
) {
3983 case RTL_GIGA_MAC_VER_07
:
3984 case RTL_GIGA_MAC_VER_08
:
3985 case RTL_GIGA_MAC_VER_09
:
3986 case RTL_GIGA_MAC_VER_10
:
3987 case RTL_GIGA_MAC_VER_13
:
3988 case RTL_GIGA_MAC_VER_16
:
3991 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
3996 static void r8168_phy_power_up(struct rtl8169_private
*tp
)
3998 rtl_writephy(tp
, 0x1f, 0x0000);
3999 switch (tp
->mac_version
) {
4000 case RTL_GIGA_MAC_VER_11
:
4001 case RTL_GIGA_MAC_VER_12
:
4002 case RTL_GIGA_MAC_VER_17
:
4003 case RTL_GIGA_MAC_VER_18
:
4004 case RTL_GIGA_MAC_VER_19
:
4005 case RTL_GIGA_MAC_VER_20
:
4006 case RTL_GIGA_MAC_VER_21
:
4007 case RTL_GIGA_MAC_VER_22
:
4008 case RTL_GIGA_MAC_VER_23
:
4009 case RTL_GIGA_MAC_VER_24
:
4010 case RTL_GIGA_MAC_VER_25
:
4011 case RTL_GIGA_MAC_VER_26
:
4012 case RTL_GIGA_MAC_VER_27
:
4013 case RTL_GIGA_MAC_VER_28
:
4014 case RTL_GIGA_MAC_VER_31
:
4015 rtl_writephy(tp
, 0x0e, 0x0000);
4020 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
);
4023 static void r8168_phy_power_down(struct rtl8169_private
*tp
)
4025 rtl_writephy(tp
, 0x1f, 0x0000);
4026 switch (tp
->mac_version
) {
4027 case RTL_GIGA_MAC_VER_32
:
4028 case RTL_GIGA_MAC_VER_33
:
4029 case RTL_GIGA_MAC_VER_40
:
4030 case RTL_GIGA_MAC_VER_41
:
4031 rtl_writephy(tp
, MII_BMCR
, BMCR_ANENABLE
| BMCR_PDOWN
);
4034 case RTL_GIGA_MAC_VER_11
:
4035 case RTL_GIGA_MAC_VER_12
:
4036 case RTL_GIGA_MAC_VER_17
:
4037 case RTL_GIGA_MAC_VER_18
:
4038 case RTL_GIGA_MAC_VER_19
:
4039 case RTL_GIGA_MAC_VER_20
:
4040 case RTL_GIGA_MAC_VER_21
:
4041 case RTL_GIGA_MAC_VER_22
:
4042 case RTL_GIGA_MAC_VER_23
:
4043 case RTL_GIGA_MAC_VER_24
:
4044 case RTL_GIGA_MAC_VER_25
:
4045 case RTL_GIGA_MAC_VER_26
:
4046 case RTL_GIGA_MAC_VER_27
:
4047 case RTL_GIGA_MAC_VER_28
:
4048 case RTL_GIGA_MAC_VER_31
:
4049 rtl_writephy(tp
, 0x0e, 0x0200);
4051 rtl_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
4056 static void r8168_pll_power_down(struct rtl8169_private
*tp
)
4058 void __iomem
*ioaddr
= tp
->mmio_addr
;
4060 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4061 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4062 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) &&
4063 r8168dp_check_dash(tp
)) {
4067 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_23
||
4068 tp
->mac_version
== RTL_GIGA_MAC_VER_24
) &&
4069 (RTL_R16(CPlusCmd
) & ASF
)) {
4073 if (tp
->mac_version
== RTL_GIGA_MAC_VER_32
||
4074 tp
->mac_version
== RTL_GIGA_MAC_VER_33
)
4075 rtl_ephy_write(tp
, 0x19, 0xff64);
4077 if (rtl_wol_pll_power_down(tp
))
4080 r8168_phy_power_down(tp
);
4082 switch (tp
->mac_version
) {
4083 case RTL_GIGA_MAC_VER_25
:
4084 case RTL_GIGA_MAC_VER_26
:
4085 case RTL_GIGA_MAC_VER_27
:
4086 case RTL_GIGA_MAC_VER_28
:
4087 case RTL_GIGA_MAC_VER_31
:
4088 case RTL_GIGA_MAC_VER_32
:
4089 case RTL_GIGA_MAC_VER_33
:
4090 RTL_W8(PMCH
, RTL_R8(PMCH
) & ~0x80);
4092 case RTL_GIGA_MAC_VER_40
:
4093 case RTL_GIGA_MAC_VER_41
:
4094 rtl_w1w0_eri(tp
, 0x1a8, ERIAR_MASK_1111
, 0x00000000,
4095 0xfc000000, ERIAR_EXGMAC
);
4100 static void r8168_pll_power_up(struct rtl8169_private
*tp
)
4102 void __iomem
*ioaddr
= tp
->mmio_addr
;
4104 switch (tp
->mac_version
) {
4105 case RTL_GIGA_MAC_VER_25
:
4106 case RTL_GIGA_MAC_VER_26
:
4107 case RTL_GIGA_MAC_VER_27
:
4108 case RTL_GIGA_MAC_VER_28
:
4109 case RTL_GIGA_MAC_VER_31
:
4110 case RTL_GIGA_MAC_VER_32
:
4111 case RTL_GIGA_MAC_VER_33
:
4112 RTL_W8(PMCH
, RTL_R8(PMCH
) | 0x80);
4114 case RTL_GIGA_MAC_VER_40
:
4115 case RTL_GIGA_MAC_VER_41
:
4116 rtl_w1w0_eri(tp
, 0x1a8, ERIAR_MASK_1111
, 0xfc000000,
4117 0x00000000, ERIAR_EXGMAC
);
4121 r8168_phy_power_up(tp
);
4124 static void rtl_generic_op(struct rtl8169_private
*tp
,
4125 void (*op
)(struct rtl8169_private
*))
4131 static void rtl_pll_power_down(struct rtl8169_private
*tp
)
4133 rtl_generic_op(tp
, tp
->pll_power_ops
.down
);
4136 static void rtl_pll_power_up(struct rtl8169_private
*tp
)
4138 rtl_generic_op(tp
, tp
->pll_power_ops
.up
);
4141 static void rtl_init_pll_power_ops(struct rtl8169_private
*tp
)
4143 struct pll_power_ops
*ops
= &tp
->pll_power_ops
;
4145 switch (tp
->mac_version
) {
4146 case RTL_GIGA_MAC_VER_07
:
4147 case RTL_GIGA_MAC_VER_08
:
4148 case RTL_GIGA_MAC_VER_09
:
4149 case RTL_GIGA_MAC_VER_10
:
4150 case RTL_GIGA_MAC_VER_16
:
4151 case RTL_GIGA_MAC_VER_29
:
4152 case RTL_GIGA_MAC_VER_30
:
4153 case RTL_GIGA_MAC_VER_37
:
4154 case RTL_GIGA_MAC_VER_39
:
4155 case RTL_GIGA_MAC_VER_43
:
4156 ops
->down
= r810x_pll_power_down
;
4157 ops
->up
= r810x_pll_power_up
;
4160 case RTL_GIGA_MAC_VER_11
:
4161 case RTL_GIGA_MAC_VER_12
:
4162 case RTL_GIGA_MAC_VER_17
:
4163 case RTL_GIGA_MAC_VER_18
:
4164 case RTL_GIGA_MAC_VER_19
:
4165 case RTL_GIGA_MAC_VER_20
:
4166 case RTL_GIGA_MAC_VER_21
:
4167 case RTL_GIGA_MAC_VER_22
:
4168 case RTL_GIGA_MAC_VER_23
:
4169 case RTL_GIGA_MAC_VER_24
:
4170 case RTL_GIGA_MAC_VER_25
:
4171 case RTL_GIGA_MAC_VER_26
:
4172 case RTL_GIGA_MAC_VER_27
:
4173 case RTL_GIGA_MAC_VER_28
:
4174 case RTL_GIGA_MAC_VER_31
:
4175 case RTL_GIGA_MAC_VER_32
:
4176 case RTL_GIGA_MAC_VER_33
:
4177 case RTL_GIGA_MAC_VER_34
:
4178 case RTL_GIGA_MAC_VER_35
:
4179 case RTL_GIGA_MAC_VER_36
:
4180 case RTL_GIGA_MAC_VER_38
:
4181 case RTL_GIGA_MAC_VER_40
:
4182 case RTL_GIGA_MAC_VER_41
:
4183 case RTL_GIGA_MAC_VER_42
:
4184 case RTL_GIGA_MAC_VER_44
:
4185 ops
->down
= r8168_pll_power_down
;
4186 ops
->up
= r8168_pll_power_up
;
4196 static void rtl_init_rxcfg(struct rtl8169_private
*tp
)
4198 void __iomem
*ioaddr
= tp
->mmio_addr
;
4200 switch (tp
->mac_version
) {
4201 case RTL_GIGA_MAC_VER_01
:
4202 case RTL_GIGA_MAC_VER_02
:
4203 case RTL_GIGA_MAC_VER_03
:
4204 case RTL_GIGA_MAC_VER_04
:
4205 case RTL_GIGA_MAC_VER_05
:
4206 case RTL_GIGA_MAC_VER_06
:
4207 case RTL_GIGA_MAC_VER_10
:
4208 case RTL_GIGA_MAC_VER_11
:
4209 case RTL_GIGA_MAC_VER_12
:
4210 case RTL_GIGA_MAC_VER_13
:
4211 case RTL_GIGA_MAC_VER_14
:
4212 case RTL_GIGA_MAC_VER_15
:
4213 case RTL_GIGA_MAC_VER_16
:
4214 case RTL_GIGA_MAC_VER_17
:
4215 RTL_W32(RxConfig
, RX_FIFO_THRESH
| RX_DMA_BURST
);
4217 case RTL_GIGA_MAC_VER_18
:
4218 case RTL_GIGA_MAC_VER_19
:
4219 case RTL_GIGA_MAC_VER_20
:
4220 case RTL_GIGA_MAC_VER_21
:
4221 case RTL_GIGA_MAC_VER_22
:
4222 case RTL_GIGA_MAC_VER_23
:
4223 case RTL_GIGA_MAC_VER_24
:
4224 case RTL_GIGA_MAC_VER_34
:
4225 case RTL_GIGA_MAC_VER_35
:
4226 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
);
4228 case RTL_GIGA_MAC_VER_40
:
4229 RTL_W32(RxConfig
, RX128_INT_EN
| RX_MULTI_EN
| RX_DMA_BURST
| RX_EARLY_OFF
);
4231 case RTL_GIGA_MAC_VER_41
:
4232 case RTL_GIGA_MAC_VER_42
:
4233 case RTL_GIGA_MAC_VER_43
:
4234 case RTL_GIGA_MAC_VER_44
:
4235 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
| RX_EARLY_OFF
);
4238 RTL_W32(RxConfig
, RX128_INT_EN
| RX_DMA_BURST
);
4243 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
4245 tp
->dirty_tx
= tp
->cur_tx
= tp
->cur_rx
= 0;
4248 static void rtl_hw_jumbo_enable(struct rtl8169_private
*tp
)
4250 void __iomem
*ioaddr
= tp
->mmio_addr
;
4252 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4253 rtl_generic_op(tp
, tp
->jumbo_ops
.enable
);
4254 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4257 static void rtl_hw_jumbo_disable(struct rtl8169_private
*tp
)
4259 void __iomem
*ioaddr
= tp
->mmio_addr
;
4261 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4262 rtl_generic_op(tp
, tp
->jumbo_ops
.disable
);
4263 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4266 static void r8168c_hw_jumbo_enable(struct rtl8169_private
*tp
)
4268 void __iomem
*ioaddr
= tp
->mmio_addr
;
4270 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
4271 RTL_W8(Config4
, RTL_R8(Config4
) | Jumbo_En1
);
4272 rtl_tx_performance_tweak(tp
->pci_dev
, 0x2 << MAX_READ_REQUEST_SHIFT
);
4275 static void r8168c_hw_jumbo_disable(struct rtl8169_private
*tp
)
4277 void __iomem
*ioaddr
= tp
->mmio_addr
;
4279 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
4280 RTL_W8(Config4
, RTL_R8(Config4
) & ~Jumbo_En1
);
4281 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4284 static void r8168dp_hw_jumbo_enable(struct rtl8169_private
*tp
)
4286 void __iomem
*ioaddr
= tp
->mmio_addr
;
4288 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
4291 static void r8168dp_hw_jumbo_disable(struct rtl8169_private
*tp
)
4293 void __iomem
*ioaddr
= tp
->mmio_addr
;
4295 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
4298 static void r8168e_hw_jumbo_enable(struct rtl8169_private
*tp
)
4300 void __iomem
*ioaddr
= tp
->mmio_addr
;
4302 RTL_W8(MaxTxPacketSize
, 0x3f);
4303 RTL_W8(Config3
, RTL_R8(Config3
) | Jumbo_En0
);
4304 RTL_W8(Config4
, RTL_R8(Config4
) | 0x01);
4305 rtl_tx_performance_tweak(tp
->pci_dev
, 0x2 << MAX_READ_REQUEST_SHIFT
);
4308 static void r8168e_hw_jumbo_disable(struct rtl8169_private
*tp
)
4310 void __iomem
*ioaddr
= tp
->mmio_addr
;
4312 RTL_W8(MaxTxPacketSize
, 0x0c);
4313 RTL_W8(Config3
, RTL_R8(Config3
) & ~Jumbo_En0
);
4314 RTL_W8(Config4
, RTL_R8(Config4
) & ~0x01);
4315 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4318 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private
*tp
)
4320 rtl_tx_performance_tweak(tp
->pci_dev
,
4321 (0x2 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
4324 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private
*tp
)
4326 rtl_tx_performance_tweak(tp
->pci_dev
,
4327 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
4330 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private
*tp
)
4332 void __iomem
*ioaddr
= tp
->mmio_addr
;
4334 r8168b_0_hw_jumbo_enable(tp
);
4336 RTL_W8(Config4
, RTL_R8(Config4
) | (1 << 0));
4339 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private
*tp
)
4341 void __iomem
*ioaddr
= tp
->mmio_addr
;
4343 r8168b_0_hw_jumbo_disable(tp
);
4345 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
4348 static void rtl_init_jumbo_ops(struct rtl8169_private
*tp
)
4350 struct jumbo_ops
*ops
= &tp
->jumbo_ops
;
4352 switch (tp
->mac_version
) {
4353 case RTL_GIGA_MAC_VER_11
:
4354 ops
->disable
= r8168b_0_hw_jumbo_disable
;
4355 ops
->enable
= r8168b_0_hw_jumbo_enable
;
4357 case RTL_GIGA_MAC_VER_12
:
4358 case RTL_GIGA_MAC_VER_17
:
4359 ops
->disable
= r8168b_1_hw_jumbo_disable
;
4360 ops
->enable
= r8168b_1_hw_jumbo_enable
;
4362 case RTL_GIGA_MAC_VER_18
: /* Wild guess. Needs info from Realtek. */
4363 case RTL_GIGA_MAC_VER_19
:
4364 case RTL_GIGA_MAC_VER_20
:
4365 case RTL_GIGA_MAC_VER_21
: /* Wild guess. Needs info from Realtek. */
4366 case RTL_GIGA_MAC_VER_22
:
4367 case RTL_GIGA_MAC_VER_23
:
4368 case RTL_GIGA_MAC_VER_24
:
4369 case RTL_GIGA_MAC_VER_25
:
4370 case RTL_GIGA_MAC_VER_26
:
4371 ops
->disable
= r8168c_hw_jumbo_disable
;
4372 ops
->enable
= r8168c_hw_jumbo_enable
;
4374 case RTL_GIGA_MAC_VER_27
:
4375 case RTL_GIGA_MAC_VER_28
:
4376 ops
->disable
= r8168dp_hw_jumbo_disable
;
4377 ops
->enable
= r8168dp_hw_jumbo_enable
;
4379 case RTL_GIGA_MAC_VER_31
: /* Wild guess. Needs info from Realtek. */
4380 case RTL_GIGA_MAC_VER_32
:
4381 case RTL_GIGA_MAC_VER_33
:
4382 case RTL_GIGA_MAC_VER_34
:
4383 ops
->disable
= r8168e_hw_jumbo_disable
;
4384 ops
->enable
= r8168e_hw_jumbo_enable
;
4388 * No action needed for jumbo frames with 8169.
4389 * No jumbo for 810x at all.
4391 case RTL_GIGA_MAC_VER_40
:
4392 case RTL_GIGA_MAC_VER_41
:
4393 case RTL_GIGA_MAC_VER_42
:
4394 case RTL_GIGA_MAC_VER_43
:
4395 case RTL_GIGA_MAC_VER_44
:
4397 ops
->disable
= NULL
;
4403 DECLARE_RTL_COND(rtl_chipcmd_cond
)
4405 void __iomem
*ioaddr
= tp
->mmio_addr
;
4407 return RTL_R8(ChipCmd
) & CmdReset
;
4410 static void rtl_hw_reset(struct rtl8169_private
*tp
)
4412 void __iomem
*ioaddr
= tp
->mmio_addr
;
4414 RTL_W8(ChipCmd
, CmdReset
);
4416 rtl_udelay_loop_wait_low(tp
, &rtl_chipcmd_cond
, 100, 100);
4419 static void rtl_request_uncached_firmware(struct rtl8169_private
*tp
)
4421 struct rtl_fw
*rtl_fw
;
4425 name
= rtl_lookup_firmware_name(tp
);
4427 goto out_no_firmware
;
4429 rtl_fw
= kzalloc(sizeof(*rtl_fw
), GFP_KERNEL
);
4433 rc
= request_firmware(&rtl_fw
->fw
, name
, &tp
->pci_dev
->dev
);
4437 rc
= rtl_check_firmware(tp
, rtl_fw
);
4439 goto err_release_firmware
;
4441 tp
->rtl_fw
= rtl_fw
;
4445 err_release_firmware
:
4446 release_firmware(rtl_fw
->fw
);
4450 netif_warn(tp
, ifup
, tp
->dev
, "unable to load firmware patch %s (%d)\n",
4457 static void rtl_request_firmware(struct rtl8169_private
*tp
)
4459 if (IS_ERR(tp
->rtl_fw
))
4460 rtl_request_uncached_firmware(tp
);
4463 static void rtl_rx_close(struct rtl8169_private
*tp
)
4465 void __iomem
*ioaddr
= tp
->mmio_addr
;
4467 RTL_W32(RxConfig
, RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
);
4470 DECLARE_RTL_COND(rtl_npq_cond
)
4472 void __iomem
*ioaddr
= tp
->mmio_addr
;
4474 return RTL_R8(TxPoll
) & NPQ
;
4477 DECLARE_RTL_COND(rtl_txcfg_empty_cond
)
4479 void __iomem
*ioaddr
= tp
->mmio_addr
;
4481 return RTL_R32(TxConfig
) & TXCFG_EMPTY
;
4484 static void rtl8169_hw_reset(struct rtl8169_private
*tp
)
4486 void __iomem
*ioaddr
= tp
->mmio_addr
;
4488 /* Disable interrupts */
4489 rtl8169_irq_mask_and_ack(tp
);
4493 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
4494 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
4495 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
4496 rtl_udelay_loop_wait_low(tp
, &rtl_npq_cond
, 20, 42*42);
4497 } else if (tp
->mac_version
== RTL_GIGA_MAC_VER_34
||
4498 tp
->mac_version
== RTL_GIGA_MAC_VER_35
||
4499 tp
->mac_version
== RTL_GIGA_MAC_VER_36
||
4500 tp
->mac_version
== RTL_GIGA_MAC_VER_37
||
4501 tp
->mac_version
== RTL_GIGA_MAC_VER_40
||
4502 tp
->mac_version
== RTL_GIGA_MAC_VER_41
||
4503 tp
->mac_version
== RTL_GIGA_MAC_VER_42
||
4504 tp
->mac_version
== RTL_GIGA_MAC_VER_43
||
4505 tp
->mac_version
== RTL_GIGA_MAC_VER_44
||
4506 tp
->mac_version
== RTL_GIGA_MAC_VER_38
) {
4507 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4508 rtl_udelay_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 666);
4510 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) | StopReq
);
4517 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
4519 void __iomem
*ioaddr
= tp
->mmio_addr
;
4521 /* Set DMA burst size and Interframe Gap Time */
4522 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
4523 (InterFrameGap
<< TxInterFrameGapShift
));
4526 static void rtl_hw_start(struct net_device
*dev
)
4528 struct rtl8169_private
*tp
= netdev_priv(dev
);
4532 rtl_irq_enable_all(tp
);
4535 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
4536 void __iomem
*ioaddr
)
4539 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4540 * register to be written before TxDescAddrLow to work.
4541 * Switching from MMIO to I/O access fixes the issue as well.
4543 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
4544 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
4545 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
4546 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
4549 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
4553 cmd
= RTL_R16(CPlusCmd
);
4554 RTL_W16(CPlusCmd
, cmd
);
4558 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
4560 /* Low hurts. Let's disable the filtering. */
4561 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
4564 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
4566 static const struct rtl_cfg2_info
{
4571 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
4572 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
4573 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
4574 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
4576 const struct rtl_cfg2_info
*p
= cfg2_info
;
4580 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
4581 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
4582 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
4583 RTL_W32(0x7c, p
->val
);
4589 static void rtl_set_rx_mode(struct net_device
*dev
)
4591 struct rtl8169_private
*tp
= netdev_priv(dev
);
4592 void __iomem
*ioaddr
= tp
->mmio_addr
;
4593 u32 mc_filter
[2]; /* Multicast hash filter */
4597 if (dev
->flags
& IFF_PROMISC
) {
4598 /* Unconditionally log net taps. */
4599 netif_notice(tp
, link
, dev
, "Promiscuous mode enabled\n");
4601 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
4603 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4604 } else if ((netdev_mc_count(dev
) > multicast_filter_limit
) ||
4605 (dev
->flags
& IFF_ALLMULTI
)) {
4606 /* Too many to filter perfectly -- accept all multicasts. */
4607 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
4608 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4610 struct netdev_hw_addr
*ha
;
4612 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
4613 mc_filter
[1] = mc_filter
[0] = 0;
4614 netdev_for_each_mc_addr(ha
, dev
) {
4615 int bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) >> 26;
4616 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
4617 rx_mode
|= AcceptMulticast
;
4621 if (dev
->features
& NETIF_F_RXALL
)
4622 rx_mode
|= (AcceptErr
| AcceptRunt
);
4624 tmp
= (RTL_R32(RxConfig
) & ~RX_CONFIG_ACCEPT_MASK
) | rx_mode
;
4626 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
4627 u32 data
= mc_filter
[0];
4629 mc_filter
[0] = swab32(mc_filter
[1]);
4630 mc_filter
[1] = swab32(data
);
4633 if (tp
->mac_version
== RTL_GIGA_MAC_VER_35
)
4634 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4636 RTL_W32(MAR0
+ 4, mc_filter
[1]);
4637 RTL_W32(MAR0
+ 0, mc_filter
[0]);
4639 RTL_W32(RxConfig
, tmp
);
4642 static void rtl_hw_start_8169(struct net_device
*dev
)
4644 struct rtl8169_private
*tp
= netdev_priv(dev
);
4645 void __iomem
*ioaddr
= tp
->mmio_addr
;
4646 struct pci_dev
*pdev
= tp
->pci_dev
;
4648 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
4649 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
4650 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
4653 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
4654 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4655 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4656 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4657 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4658 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4662 RTL_W8(EarlyTxThres
, NoEarlyTx
);
4664 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
4666 if (tp
->mac_version
== RTL_GIGA_MAC_VER_01
||
4667 tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4668 tp
->mac_version
== RTL_GIGA_MAC_VER_03
||
4669 tp
->mac_version
== RTL_GIGA_MAC_VER_04
)
4670 rtl_set_rx_tx_config_registers(tp
);
4672 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
4674 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
||
4675 tp
->mac_version
== RTL_GIGA_MAC_VER_03
) {
4676 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4677 "Bit-3 and bit-14 MUST be 1\n");
4678 tp
->cp_cmd
|= (1 << 14);
4681 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4683 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
4686 * Undocumented corner. Supposedly:
4687 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4689 RTL_W16(IntrMitigate
, 0x0000);
4691 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
4693 if (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
&&
4694 tp
->mac_version
!= RTL_GIGA_MAC_VER_02
&&
4695 tp
->mac_version
!= RTL_GIGA_MAC_VER_03
&&
4696 tp
->mac_version
!= RTL_GIGA_MAC_VER_04
) {
4697 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
4698 rtl_set_rx_tx_config_registers(tp
);
4701 RTL_W8(Cfg9346
, Cfg9346_Lock
);
4703 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4706 RTL_W32(RxMissed
, 0);
4708 rtl_set_rx_mode(dev
);
4710 /* no early-rx interrupts */
4711 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
4714 static void rtl_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
4716 if (tp
->csi_ops
.write
)
4717 tp
->csi_ops
.write(tp
, addr
, value
);
4720 static u32
rtl_csi_read(struct rtl8169_private
*tp
, int addr
)
4722 return tp
->csi_ops
.read
? tp
->csi_ops
.read(tp
, addr
) : ~0;
4725 static void rtl_csi_access_enable(struct rtl8169_private
*tp
, u32 bits
)
4729 csi
= rtl_csi_read(tp
, 0x070c) & 0x00ffffff;
4730 rtl_csi_write(tp
, 0x070c, csi
| bits
);
4733 static void rtl_csi_access_enable_1(struct rtl8169_private
*tp
)
4735 rtl_csi_access_enable(tp
, 0x17000000);
4738 static void rtl_csi_access_enable_2(struct rtl8169_private
*tp
)
4740 rtl_csi_access_enable(tp
, 0x27000000);
4743 DECLARE_RTL_COND(rtl_csiar_cond
)
4745 void __iomem
*ioaddr
= tp
->mmio_addr
;
4747 return RTL_R32(CSIAR
) & CSIAR_FLAG
;
4750 static void r8169_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
4752 void __iomem
*ioaddr
= tp
->mmio_addr
;
4754 RTL_W32(CSIDR
, value
);
4755 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
4756 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
4758 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
4761 static u32
r8169_csi_read(struct rtl8169_private
*tp
, int addr
)
4763 void __iomem
*ioaddr
= tp
->mmio_addr
;
4765 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
4766 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
4768 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
4769 RTL_R32(CSIDR
) : ~0;
4772 static void r8402_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
4774 void __iomem
*ioaddr
= tp
->mmio_addr
;
4776 RTL_W32(CSIDR
, value
);
4777 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
4778 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
|
4781 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
4784 static u32
r8402_csi_read(struct rtl8169_private
*tp
, int addr
)
4786 void __iomem
*ioaddr
= tp
->mmio_addr
;
4788 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) | CSIAR_FUNC_NIC
|
4789 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
4791 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
4792 RTL_R32(CSIDR
) : ~0;
4795 static void r8411_csi_write(struct rtl8169_private
*tp
, int addr
, int value
)
4797 void __iomem
*ioaddr
= tp
->mmio_addr
;
4799 RTL_W32(CSIDR
, value
);
4800 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
4801 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
|
4804 rtl_udelay_loop_wait_low(tp
, &rtl_csiar_cond
, 10, 100);
4807 static u32
r8411_csi_read(struct rtl8169_private
*tp
, int addr
)
4809 void __iomem
*ioaddr
= tp
->mmio_addr
;
4811 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) | CSIAR_FUNC_NIC2
|
4812 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
4814 return rtl_udelay_loop_wait_high(tp
, &rtl_csiar_cond
, 10, 100) ?
4815 RTL_R32(CSIDR
) : ~0;
4818 static void rtl_init_csi_ops(struct rtl8169_private
*tp
)
4820 struct csi_ops
*ops
= &tp
->csi_ops
;
4822 switch (tp
->mac_version
) {
4823 case RTL_GIGA_MAC_VER_01
:
4824 case RTL_GIGA_MAC_VER_02
:
4825 case RTL_GIGA_MAC_VER_03
:
4826 case RTL_GIGA_MAC_VER_04
:
4827 case RTL_GIGA_MAC_VER_05
:
4828 case RTL_GIGA_MAC_VER_06
:
4829 case RTL_GIGA_MAC_VER_10
:
4830 case RTL_GIGA_MAC_VER_11
:
4831 case RTL_GIGA_MAC_VER_12
:
4832 case RTL_GIGA_MAC_VER_13
:
4833 case RTL_GIGA_MAC_VER_14
:
4834 case RTL_GIGA_MAC_VER_15
:
4835 case RTL_GIGA_MAC_VER_16
:
4836 case RTL_GIGA_MAC_VER_17
:
4841 case RTL_GIGA_MAC_VER_37
:
4842 case RTL_GIGA_MAC_VER_38
:
4843 ops
->write
= r8402_csi_write
;
4844 ops
->read
= r8402_csi_read
;
4847 case RTL_GIGA_MAC_VER_44
:
4848 ops
->write
= r8411_csi_write
;
4849 ops
->read
= r8411_csi_read
;
4853 ops
->write
= r8169_csi_write
;
4854 ops
->read
= r8169_csi_read
;
4860 unsigned int offset
;
4865 static void rtl_ephy_init(struct rtl8169_private
*tp
, const struct ephy_info
*e
,
4871 w
= (rtl_ephy_read(tp
, e
->offset
) & ~e
->mask
) | e
->bits
;
4872 rtl_ephy_write(tp
, e
->offset
, w
);
4877 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
4879 pcie_capability_clear_word(pdev
, PCI_EXP_LNKCTL
,
4880 PCI_EXP_LNKCTL_CLKREQ_EN
);
4883 static void rtl_enable_clock_request(struct pci_dev
*pdev
)
4885 pcie_capability_set_word(pdev
, PCI_EXP_LNKCTL
,
4886 PCI_EXP_LNKCTL_CLKREQ_EN
);
4889 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private
*tp
, bool enable
)
4891 void __iomem
*ioaddr
= tp
->mmio_addr
;
4894 data
= RTL_R8(Config3
);
4899 data
&= ~Rdy_to_L23
;
4901 RTL_W8(Config3
, data
);
4904 #define R8168_CPCMD_QUIRK_MASK (\
4915 static void rtl_hw_start_8168bb(struct rtl8169_private
*tp
)
4917 void __iomem
*ioaddr
= tp
->mmio_addr
;
4918 struct pci_dev
*pdev
= tp
->pci_dev
;
4920 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4922 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4924 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
4925 rtl_tx_performance_tweak(pdev
, (0x5 << MAX_READ_REQUEST_SHIFT
) |
4926 PCI_EXP_DEVCTL_NOSNOOP_EN
);
4930 static void rtl_hw_start_8168bef(struct rtl8169_private
*tp
)
4932 void __iomem
*ioaddr
= tp
->mmio_addr
;
4934 rtl_hw_start_8168bb(tp
);
4936 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
4938 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
4941 static void __rtl_hw_start_8168cp(struct rtl8169_private
*tp
)
4943 void __iomem
*ioaddr
= tp
->mmio_addr
;
4944 struct pci_dev
*pdev
= tp
->pci_dev
;
4946 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
4948 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4950 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4951 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4953 rtl_disable_clock_request(pdev
);
4955 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4958 static void rtl_hw_start_8168cp_1(struct rtl8169_private
*tp
)
4960 static const struct ephy_info e_info_8168cp
[] = {
4961 { 0x01, 0, 0x0001 },
4962 { 0x02, 0x0800, 0x1000 },
4963 { 0x03, 0, 0x0042 },
4964 { 0x06, 0x0080, 0x0000 },
4968 rtl_csi_access_enable_2(tp
);
4970 rtl_ephy_init(tp
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
4972 __rtl_hw_start_8168cp(tp
);
4975 static void rtl_hw_start_8168cp_2(struct rtl8169_private
*tp
)
4977 void __iomem
*ioaddr
= tp
->mmio_addr
;
4978 struct pci_dev
*pdev
= tp
->pci_dev
;
4980 rtl_csi_access_enable_2(tp
);
4982 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
4984 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
4985 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
4987 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
4990 static void rtl_hw_start_8168cp_3(struct rtl8169_private
*tp
)
4992 void __iomem
*ioaddr
= tp
->mmio_addr
;
4993 struct pci_dev
*pdev
= tp
->pci_dev
;
4995 rtl_csi_access_enable_2(tp
);
4997 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5000 RTL_W8(DBG_REG
, 0x20);
5002 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5004 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5005 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5007 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5010 static void rtl_hw_start_8168c_1(struct rtl8169_private
*tp
)
5012 void __iomem
*ioaddr
= tp
->mmio_addr
;
5013 static const struct ephy_info e_info_8168c_1
[] = {
5014 { 0x02, 0x0800, 0x1000 },
5015 { 0x03, 0, 0x0002 },
5016 { 0x06, 0x0080, 0x0000 }
5019 rtl_csi_access_enable_2(tp
);
5021 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
5023 rtl_ephy_init(tp
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
5025 __rtl_hw_start_8168cp(tp
);
5028 static void rtl_hw_start_8168c_2(struct rtl8169_private
*tp
)
5030 static const struct ephy_info e_info_8168c_2
[] = {
5031 { 0x01, 0, 0x0001 },
5032 { 0x03, 0x0400, 0x0220 }
5035 rtl_csi_access_enable_2(tp
);
5037 rtl_ephy_init(tp
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
5039 __rtl_hw_start_8168cp(tp
);
5042 static void rtl_hw_start_8168c_3(struct rtl8169_private
*tp
)
5044 rtl_hw_start_8168c_2(tp
);
5047 static void rtl_hw_start_8168c_4(struct rtl8169_private
*tp
)
5049 rtl_csi_access_enable_2(tp
);
5051 __rtl_hw_start_8168cp(tp
);
5054 static void rtl_hw_start_8168d(struct rtl8169_private
*tp
)
5056 void __iomem
*ioaddr
= tp
->mmio_addr
;
5057 struct pci_dev
*pdev
= tp
->pci_dev
;
5059 rtl_csi_access_enable_2(tp
);
5061 rtl_disable_clock_request(pdev
);
5063 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5065 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5066 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5068 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
5071 static void rtl_hw_start_8168dp(struct rtl8169_private
*tp
)
5073 void __iomem
*ioaddr
= tp
->mmio_addr
;
5074 struct pci_dev
*pdev
= tp
->pci_dev
;
5076 rtl_csi_access_enable_1(tp
);
5078 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5079 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5081 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5083 rtl_disable_clock_request(pdev
);
5086 static void rtl_hw_start_8168d_4(struct rtl8169_private
*tp
)
5088 void __iomem
*ioaddr
= tp
->mmio_addr
;
5089 struct pci_dev
*pdev
= tp
->pci_dev
;
5090 static const struct ephy_info e_info_8168d_4
[] = {
5092 { 0x19, 0x20, 0x50 },
5097 rtl_csi_access_enable_1(tp
);
5099 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5101 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5103 for (i
= 0; i
< ARRAY_SIZE(e_info_8168d_4
); i
++) {
5104 const struct ephy_info
*e
= e_info_8168d_4
+ i
;
5107 w
= rtl_ephy_read(tp
, e
->offset
);
5108 rtl_ephy_write(tp
, 0x03, (w
& e
->mask
) | e
->bits
);
5111 rtl_enable_clock_request(pdev
);
5114 static void rtl_hw_start_8168e_1(struct rtl8169_private
*tp
)
5116 void __iomem
*ioaddr
= tp
->mmio_addr
;
5117 struct pci_dev
*pdev
= tp
->pci_dev
;
5118 static const struct ephy_info e_info_8168e_1
[] = {
5119 { 0x00, 0x0200, 0x0100 },
5120 { 0x00, 0x0000, 0x0004 },
5121 { 0x06, 0x0002, 0x0001 },
5122 { 0x06, 0x0000, 0x0030 },
5123 { 0x07, 0x0000, 0x2000 },
5124 { 0x00, 0x0000, 0x0020 },
5125 { 0x03, 0x5800, 0x2000 },
5126 { 0x03, 0x0000, 0x0001 },
5127 { 0x01, 0x0800, 0x1000 },
5128 { 0x07, 0x0000, 0x4000 },
5129 { 0x1e, 0x0000, 0x2000 },
5130 { 0x19, 0xffff, 0xfe6c },
5131 { 0x0a, 0x0000, 0x0040 }
5134 rtl_csi_access_enable_2(tp
);
5136 rtl_ephy_init(tp
, e_info_8168e_1
, ARRAY_SIZE(e_info_8168e_1
));
5138 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5139 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5141 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5143 rtl_disable_clock_request(pdev
);
5145 /* Reset tx FIFO pointer */
5146 RTL_W32(MISC
, RTL_R32(MISC
) | TXPLA_RST
);
5147 RTL_W32(MISC
, RTL_R32(MISC
) & ~TXPLA_RST
);
5149 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
5152 static void rtl_hw_start_8168e_2(struct rtl8169_private
*tp
)
5154 void __iomem
*ioaddr
= tp
->mmio_addr
;
5155 struct pci_dev
*pdev
= tp
->pci_dev
;
5156 static const struct ephy_info e_info_8168e_2
[] = {
5157 { 0x09, 0x0000, 0x0080 },
5158 { 0x19, 0x0000, 0x0224 }
5161 rtl_csi_access_enable_1(tp
);
5163 rtl_ephy_init(tp
, e_info_8168e_2
, ARRAY_SIZE(e_info_8168e_2
));
5165 if (tp
->dev
->mtu
<= ETH_DATA_LEN
)
5166 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5168 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5169 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5170 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
5171 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
5172 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
5173 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x07ff0060, ERIAR_EXGMAC
);
5174 rtl_w1w0_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
5175 rtl_w1w0_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00, ERIAR_EXGMAC
);
5177 RTL_W8(MaxTxPacketSize
, EarlySize
);
5179 rtl_disable_clock_request(pdev
);
5181 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
5182 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
5184 /* Adjust EEE LED frequency */
5185 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
5187 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
5188 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
5189 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
5192 static void rtl_hw_start_8168f(struct rtl8169_private
*tp
)
5194 void __iomem
*ioaddr
= tp
->mmio_addr
;
5195 struct pci_dev
*pdev
= tp
->pci_dev
;
5197 rtl_csi_access_enable_2(tp
);
5199 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5201 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5202 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5203 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00100002, ERIAR_EXGMAC
);
5204 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
5205 rtl_w1w0_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
5206 rtl_w1w0_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
5207 rtl_w1w0_eri(tp
, 0x1b0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
5208 rtl_w1w0_eri(tp
, 0x1d0, ERIAR_MASK_0001
, 0x10, 0x00, ERIAR_EXGMAC
);
5209 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_1111
, 0x00000050, ERIAR_EXGMAC
);
5210 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_1111
, 0x00000060, ERIAR_EXGMAC
);
5212 RTL_W8(MaxTxPacketSize
, EarlySize
);
5214 rtl_disable_clock_request(pdev
);
5216 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
5217 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
5218 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
5219 RTL_W32(MISC
, RTL_R32(MISC
) | PWM_EN
);
5220 RTL_W8(Config5
, RTL_R8(Config5
) & ~Spi_en
);
5223 static void rtl_hw_start_8168f_1(struct rtl8169_private
*tp
)
5225 void __iomem
*ioaddr
= tp
->mmio_addr
;
5226 static const struct ephy_info e_info_8168f_1
[] = {
5227 { 0x06, 0x00c0, 0x0020 },
5228 { 0x08, 0x0001, 0x0002 },
5229 { 0x09, 0x0000, 0x0080 },
5230 { 0x19, 0x0000, 0x0224 }
5233 rtl_hw_start_8168f(tp
);
5235 rtl_ephy_init(tp
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
5237 rtl_w1w0_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0xff00, ERIAR_EXGMAC
);
5239 /* Adjust EEE LED frequency */
5240 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
5243 static void rtl_hw_start_8411(struct rtl8169_private
*tp
)
5245 static const struct ephy_info e_info_8168f_1
[] = {
5246 { 0x06, 0x00c0, 0x0020 },
5247 { 0x0f, 0xffff, 0x5200 },
5248 { 0x1e, 0x0000, 0x4000 },
5249 { 0x19, 0x0000, 0x0224 }
5252 rtl_hw_start_8168f(tp
);
5253 rtl_pcie_state_l2l3_enable(tp
, false);
5255 rtl_ephy_init(tp
, e_info_8168f_1
, ARRAY_SIZE(e_info_8168f_1
));
5257 rtl_w1w0_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0c00, 0x0000, ERIAR_EXGMAC
);
5260 static void rtl_hw_start_8168g_1(struct rtl8169_private
*tp
)
5262 void __iomem
*ioaddr
= tp
->mmio_addr
;
5263 struct pci_dev
*pdev
= tp
->pci_dev
;
5265 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
5267 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_0101
, 0x080002, ERIAR_EXGMAC
);
5268 rtl_eri_write(tp
, 0xcc, ERIAR_MASK_0001
, 0x38, ERIAR_EXGMAC
);
5269 rtl_eri_write(tp
, 0xd0, ERIAR_MASK_0001
, 0x48, ERIAR_EXGMAC
);
5270 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00100006, ERIAR_EXGMAC
);
5272 rtl_csi_access_enable_1(tp
);
5274 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5276 rtl_w1w0_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
5277 rtl_w1w0_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
5278 rtl_eri_write(tp
, 0x2f8, ERIAR_MASK_0011
, 0x1d8f, ERIAR_EXGMAC
);
5280 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5281 RTL_W32(MISC
, RTL_R32(MISC
) & ~RXDV_GATED_EN
);
5282 RTL_W8(MaxTxPacketSize
, EarlySize
);
5284 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5285 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5287 /* Adjust EEE LED frequency */
5288 RTL_W8(EEE_LED
, RTL_R8(EEE_LED
) & ~0x07);
5290 rtl_w1w0_eri(tp
, 0x2fc, ERIAR_MASK_0001
, 0x01, 0x06, ERIAR_EXGMAC
);
5291 rtl_w1w0_eri(tp
, 0x1b0, ERIAR_MASK_0011
, 0x0000, 0x1000, ERIAR_EXGMAC
);
5293 rtl_pcie_state_l2l3_enable(tp
, false);
5296 static void rtl_hw_start_8168g_2(struct rtl8169_private
*tp
)
5298 void __iomem
*ioaddr
= tp
->mmio_addr
;
5299 static const struct ephy_info e_info_8168g_2
[] = {
5300 { 0x00, 0x0000, 0x0008 },
5301 { 0x0c, 0x3df0, 0x0200 },
5302 { 0x19, 0xffff, 0xfc00 },
5303 { 0x1e, 0xffff, 0x20eb }
5306 rtl_hw_start_8168g_1(tp
);
5308 /* disable aspm and clock request before access ephy */
5309 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
5310 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
5311 rtl_ephy_init(tp
, e_info_8168g_2
, ARRAY_SIZE(e_info_8168g_2
));
5314 static void rtl_hw_start_8411_2(struct rtl8169_private
*tp
)
5316 void __iomem
*ioaddr
= tp
->mmio_addr
;
5317 static const struct ephy_info e_info_8411_2
[] = {
5318 { 0x00, 0x0000, 0x0008 },
5319 { 0x0c, 0x3df0, 0x0200 },
5320 { 0x0f, 0xffff, 0x5200 },
5321 { 0x19, 0x0020, 0x0000 },
5322 { 0x1e, 0x0000, 0x2000 }
5325 rtl_hw_start_8168g_1(tp
);
5327 /* disable aspm and clock request before access ephy */
5328 RTL_W8(Config2
, RTL_R8(Config2
) & ~ClkReqEn
);
5329 RTL_W8(Config5
, RTL_R8(Config5
) & ~ASPM_en
);
5330 rtl_ephy_init(tp
, e_info_8411_2
, ARRAY_SIZE(e_info_8411_2
));
5333 static void rtl_hw_start_8168(struct net_device
*dev
)
5335 struct rtl8169_private
*tp
= netdev_priv(dev
);
5336 void __iomem
*ioaddr
= tp
->mmio_addr
;
5338 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
5340 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5342 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
5344 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
5346 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5348 RTL_W16(IntrMitigate
, 0x5151);
5350 /* Work around for RxFIFO overflow. */
5351 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
5352 tp
->event_slow
|= RxFIFOOver
| PCSTimeout
;
5353 tp
->event_slow
&= ~RxOverflow
;
5356 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
5358 rtl_set_rx_tx_config_registers(tp
);
5362 switch (tp
->mac_version
) {
5363 case RTL_GIGA_MAC_VER_11
:
5364 rtl_hw_start_8168bb(tp
);
5367 case RTL_GIGA_MAC_VER_12
:
5368 case RTL_GIGA_MAC_VER_17
:
5369 rtl_hw_start_8168bef(tp
);
5372 case RTL_GIGA_MAC_VER_18
:
5373 rtl_hw_start_8168cp_1(tp
);
5376 case RTL_GIGA_MAC_VER_19
:
5377 rtl_hw_start_8168c_1(tp
);
5380 case RTL_GIGA_MAC_VER_20
:
5381 rtl_hw_start_8168c_2(tp
);
5384 case RTL_GIGA_MAC_VER_21
:
5385 rtl_hw_start_8168c_3(tp
);
5388 case RTL_GIGA_MAC_VER_22
:
5389 rtl_hw_start_8168c_4(tp
);
5392 case RTL_GIGA_MAC_VER_23
:
5393 rtl_hw_start_8168cp_2(tp
);
5396 case RTL_GIGA_MAC_VER_24
:
5397 rtl_hw_start_8168cp_3(tp
);
5400 case RTL_GIGA_MAC_VER_25
:
5401 case RTL_GIGA_MAC_VER_26
:
5402 case RTL_GIGA_MAC_VER_27
:
5403 rtl_hw_start_8168d(tp
);
5406 case RTL_GIGA_MAC_VER_28
:
5407 rtl_hw_start_8168d_4(tp
);
5410 case RTL_GIGA_MAC_VER_31
:
5411 rtl_hw_start_8168dp(tp
);
5414 case RTL_GIGA_MAC_VER_32
:
5415 case RTL_GIGA_MAC_VER_33
:
5416 rtl_hw_start_8168e_1(tp
);
5418 case RTL_GIGA_MAC_VER_34
:
5419 rtl_hw_start_8168e_2(tp
);
5422 case RTL_GIGA_MAC_VER_35
:
5423 case RTL_GIGA_MAC_VER_36
:
5424 rtl_hw_start_8168f_1(tp
);
5427 case RTL_GIGA_MAC_VER_38
:
5428 rtl_hw_start_8411(tp
);
5431 case RTL_GIGA_MAC_VER_40
:
5432 case RTL_GIGA_MAC_VER_41
:
5433 rtl_hw_start_8168g_1(tp
);
5435 case RTL_GIGA_MAC_VER_42
:
5436 rtl_hw_start_8168g_2(tp
);
5439 case RTL_GIGA_MAC_VER_44
:
5440 rtl_hw_start_8411_2(tp
);
5444 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
5445 dev
->name
, tp
->mac_version
);
5449 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5451 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5453 rtl_set_rx_mode(dev
);
5455 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
5458 #define R810X_CPCMD_QUIRK_MASK (\
5469 static void rtl_hw_start_8102e_1(struct rtl8169_private
*tp
)
5471 void __iomem
*ioaddr
= tp
->mmio_addr
;
5472 struct pci_dev
*pdev
= tp
->pci_dev
;
5473 static const struct ephy_info e_info_8102e_1
[] = {
5474 { 0x01, 0, 0x6e65 },
5475 { 0x02, 0, 0x091f },
5476 { 0x03, 0, 0xc2f9 },
5477 { 0x06, 0, 0xafb5 },
5478 { 0x07, 0, 0x0e00 },
5479 { 0x19, 0, 0xec80 },
5480 { 0x01, 0, 0x2e65 },
5485 rtl_csi_access_enable_2(tp
);
5487 RTL_W8(DBG_REG
, FIX_NAK_1
);
5489 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5492 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
5493 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5495 cfg1
= RTL_R8(Config1
);
5496 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
5497 RTL_W8(Config1
, cfg1
& ~LEDS0
);
5499 rtl_ephy_init(tp
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
5502 static void rtl_hw_start_8102e_2(struct rtl8169_private
*tp
)
5504 void __iomem
*ioaddr
= tp
->mmio_addr
;
5505 struct pci_dev
*pdev
= tp
->pci_dev
;
5507 rtl_csi_access_enable_2(tp
);
5509 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5511 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
5512 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
5515 static void rtl_hw_start_8102e_3(struct rtl8169_private
*tp
)
5517 rtl_hw_start_8102e_2(tp
);
5519 rtl_ephy_write(tp
, 0x03, 0xc2f9);
5522 static void rtl_hw_start_8105e_1(struct rtl8169_private
*tp
)
5524 void __iomem
*ioaddr
= tp
->mmio_addr
;
5525 static const struct ephy_info e_info_8105e_1
[] = {
5526 { 0x07, 0, 0x4000 },
5527 { 0x19, 0, 0x0200 },
5528 { 0x19, 0, 0x0020 },
5529 { 0x1e, 0, 0x2000 },
5530 { 0x03, 0, 0x0001 },
5531 { 0x19, 0, 0x0100 },
5532 { 0x19, 0, 0x0004 },
5536 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5537 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
5539 /* Disable Early Tally Counter */
5540 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) & ~0x010000);
5542 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
5543 RTL_W8(DLLPR
, RTL_R8(DLLPR
) | PFM_EN
);
5545 rtl_ephy_init(tp
, e_info_8105e_1
, ARRAY_SIZE(e_info_8105e_1
));
5547 rtl_pcie_state_l2l3_enable(tp
, false);
5550 static void rtl_hw_start_8105e_2(struct rtl8169_private
*tp
)
5552 rtl_hw_start_8105e_1(tp
);
5553 rtl_ephy_write(tp
, 0x1e, rtl_ephy_read(tp
, 0x1e) | 0x8000);
5556 static void rtl_hw_start_8402(struct rtl8169_private
*tp
)
5558 void __iomem
*ioaddr
= tp
->mmio_addr
;
5559 static const struct ephy_info e_info_8402
[] = {
5560 { 0x19, 0xffff, 0xff64 },
5564 rtl_csi_access_enable_2(tp
);
5566 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5567 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
5569 RTL_W32(TxConfig
, RTL_R32(TxConfig
) | TXCFG_AUTO_FIFO
);
5570 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
5572 rtl_ephy_init(tp
, e_info_8402
, ARRAY_SIZE(e_info_8402
));
5574 rtl_tx_performance_tweak(tp
->pci_dev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
5576 rtl_eri_write(tp
, 0xc8, ERIAR_MASK_1111
, 0x00000002, ERIAR_EXGMAC
);
5577 rtl_eri_write(tp
, 0xe8, ERIAR_MASK_1111
, 0x00000006, ERIAR_EXGMAC
);
5578 rtl_w1w0_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x00, 0x01, ERIAR_EXGMAC
);
5579 rtl_w1w0_eri(tp
, 0xdc, ERIAR_MASK_0001
, 0x01, 0x00, ERIAR_EXGMAC
);
5580 rtl_eri_write(tp
, 0xc0, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5581 rtl_eri_write(tp
, 0xb8, ERIAR_MASK_0011
, 0x0000, ERIAR_EXGMAC
);
5582 rtl_w1w0_eri(tp
, 0x0d4, ERIAR_MASK_0011
, 0x0e00, 0xff00, ERIAR_EXGMAC
);
5584 rtl_pcie_state_l2l3_enable(tp
, false);
5587 static void rtl_hw_start_8106(struct rtl8169_private
*tp
)
5589 void __iomem
*ioaddr
= tp
->mmio_addr
;
5591 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5592 RTL_W32(FuncEvent
, RTL_R32(FuncEvent
) | 0x002800);
5594 RTL_W32(MISC
, (RTL_R32(MISC
) | DISABLE_LAN_EN
) & ~EARLY_TALLY_EN
);
5595 RTL_W8(MCU
, RTL_R8(MCU
) | EN_NDP
| EN_OOB_RESET
);
5596 RTL_W8(DLLPR
, RTL_R8(DLLPR
) & ~PFM_EN
);
5598 rtl_pcie_state_l2l3_enable(tp
, false);
5601 static void rtl_hw_start_8101(struct net_device
*dev
)
5603 struct rtl8169_private
*tp
= netdev_priv(dev
);
5604 void __iomem
*ioaddr
= tp
->mmio_addr
;
5605 struct pci_dev
*pdev
= tp
->pci_dev
;
5607 if (tp
->mac_version
>= RTL_GIGA_MAC_VER_30
)
5608 tp
->event_slow
&= ~RxFIFOOver
;
5610 if (tp
->mac_version
== RTL_GIGA_MAC_VER_13
||
5611 tp
->mac_version
== RTL_GIGA_MAC_VER_16
)
5612 pcie_capability_set_word(pdev
, PCI_EXP_DEVCTL
,
5613 PCI_EXP_DEVCTL_NOSNOOP_EN
);
5615 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
5617 RTL_W8(MaxTxPacketSize
, TxPacketMax
);
5619 rtl_set_rx_max_size(ioaddr
, rx_buf_sz
);
5621 tp
->cp_cmd
&= ~R810X_CPCMD_QUIRK_MASK
;
5622 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
5624 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
5626 rtl_set_rx_tx_config_registers(tp
);
5628 switch (tp
->mac_version
) {
5629 case RTL_GIGA_MAC_VER_07
:
5630 rtl_hw_start_8102e_1(tp
);
5633 case RTL_GIGA_MAC_VER_08
:
5634 rtl_hw_start_8102e_3(tp
);
5637 case RTL_GIGA_MAC_VER_09
:
5638 rtl_hw_start_8102e_2(tp
);
5641 case RTL_GIGA_MAC_VER_29
:
5642 rtl_hw_start_8105e_1(tp
);
5644 case RTL_GIGA_MAC_VER_30
:
5645 rtl_hw_start_8105e_2(tp
);
5648 case RTL_GIGA_MAC_VER_37
:
5649 rtl_hw_start_8402(tp
);
5652 case RTL_GIGA_MAC_VER_39
:
5653 rtl_hw_start_8106(tp
);
5655 case RTL_GIGA_MAC_VER_43
:
5656 rtl_hw_start_8168g_2(tp
);
5660 RTL_W8(Cfg9346
, Cfg9346_Lock
);
5662 RTL_W16(IntrMitigate
, 0x0000);
5664 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
5666 rtl_set_rx_mode(dev
);
5670 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
5673 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
5675 struct rtl8169_private
*tp
= netdev_priv(dev
);
5677 if (new_mtu
< ETH_ZLEN
||
5678 new_mtu
> rtl_chip_infos
[tp
->mac_version
].jumbo_max
)
5681 if (new_mtu
> ETH_DATA_LEN
)
5682 rtl_hw_jumbo_enable(tp
);
5684 rtl_hw_jumbo_disable(tp
);
5687 netdev_update_features(dev
);
5692 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
5694 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
5695 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
5698 static void rtl8169_free_rx_databuff(struct rtl8169_private
*tp
,
5699 void **data_buff
, struct RxDesc
*desc
)
5701 dma_unmap_single(&tp
->pci_dev
->dev
, le64_to_cpu(desc
->addr
), rx_buf_sz
,
5706 rtl8169_make_unusable_by_asic(desc
);
5709 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
5711 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
5713 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
5716 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
5719 desc
->addr
= cpu_to_le64(mapping
);
5721 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
5724 static inline void *rtl8169_align(void *data
)
5726 return (void *)ALIGN((long)data
, 16);
5729 static struct sk_buff
*rtl8169_alloc_rx_data(struct rtl8169_private
*tp
,
5730 struct RxDesc
*desc
)
5734 struct device
*d
= &tp
->pci_dev
->dev
;
5735 struct net_device
*dev
= tp
->dev
;
5736 int node
= dev
->dev
.parent
? dev_to_node(dev
->dev
.parent
) : -1;
5738 data
= kmalloc_node(rx_buf_sz
, GFP_KERNEL
, node
);
5742 if (rtl8169_align(data
) != data
) {
5744 data
= kmalloc_node(rx_buf_sz
+ 15, GFP_KERNEL
, node
);
5749 mapping
= dma_map_single(d
, rtl8169_align(data
), rx_buf_sz
,
5751 if (unlikely(dma_mapping_error(d
, mapping
))) {
5752 if (net_ratelimit())
5753 netif_err(tp
, drv
, tp
->dev
, "Failed to map RX DMA!\n");
5757 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
5765 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
5769 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5770 if (tp
->Rx_databuff
[i
]) {
5771 rtl8169_free_rx_databuff(tp
, tp
->Rx_databuff
+ i
,
5772 tp
->RxDescArray
+ i
);
5777 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
5779 desc
->opts1
|= cpu_to_le32(RingEnd
);
5782 static int rtl8169_rx_fill(struct rtl8169_private
*tp
)
5786 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
5789 if (tp
->Rx_databuff
[i
])
5792 data
= rtl8169_alloc_rx_data(tp
, tp
->RxDescArray
+ i
);
5794 rtl8169_make_unusable_by_asic(tp
->RxDescArray
+ i
);
5797 tp
->Rx_databuff
[i
] = data
;
5800 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
5804 rtl8169_rx_clear(tp
);
5808 static int rtl8169_init_ring(struct net_device
*dev
)
5810 struct rtl8169_private
*tp
= netdev_priv(dev
);
5812 rtl8169_init_ring_indexes(tp
);
5814 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
5815 memset(tp
->Rx_databuff
, 0x0, NUM_RX_DESC
* sizeof(void *));
5817 return rtl8169_rx_fill(tp
);
5820 static void rtl8169_unmap_tx_skb(struct device
*d
, struct ring_info
*tx_skb
,
5821 struct TxDesc
*desc
)
5823 unsigned int len
= tx_skb
->len
;
5825 dma_unmap_single(d
, le64_to_cpu(desc
->addr
), len
, DMA_TO_DEVICE
);
5833 static void rtl8169_tx_clear_range(struct rtl8169_private
*tp
, u32 start
,
5838 for (i
= 0; i
< n
; i
++) {
5839 unsigned int entry
= (start
+ i
) % NUM_TX_DESC
;
5840 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
5841 unsigned int len
= tx_skb
->len
;
5844 struct sk_buff
*skb
= tx_skb
->skb
;
5846 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
5847 tp
->TxDescArray
+ entry
);
5849 tp
->dev
->stats
.tx_dropped
++;
5850 dev_kfree_skb_any(skb
);
5857 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
5859 rtl8169_tx_clear_range(tp
, tp
->dirty_tx
, NUM_TX_DESC
);
5860 tp
->cur_tx
= tp
->dirty_tx
= 0;
5863 static void rtl_reset_work(struct rtl8169_private
*tp
)
5865 struct net_device
*dev
= tp
->dev
;
5868 napi_disable(&tp
->napi
);
5869 netif_stop_queue(dev
);
5870 synchronize_sched();
5872 rtl8169_hw_reset(tp
);
5874 for (i
= 0; i
< NUM_RX_DESC
; i
++)
5875 rtl8169_mark_to_asic(tp
->RxDescArray
+ i
, rx_buf_sz
);
5877 rtl8169_tx_clear(tp
);
5878 rtl8169_init_ring_indexes(tp
);
5880 napi_enable(&tp
->napi
);
5882 netif_wake_queue(dev
);
5883 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
5886 static void rtl8169_tx_timeout(struct net_device
*dev
)
5888 struct rtl8169_private
*tp
= netdev_priv(dev
);
5890 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
5893 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
5896 struct skb_shared_info
*info
= skb_shinfo(skb
);
5897 unsigned int cur_frag
, entry
;
5898 struct TxDesc
* uninitialized_var(txd
);
5899 struct device
*d
= &tp
->pci_dev
->dev
;
5902 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
5903 const skb_frag_t
*frag
= info
->frags
+ cur_frag
;
5908 entry
= (entry
+ 1) % NUM_TX_DESC
;
5910 txd
= tp
->TxDescArray
+ entry
;
5911 len
= skb_frag_size(frag
);
5912 addr
= skb_frag_address(frag
);
5913 mapping
= dma_map_single(d
, addr
, len
, DMA_TO_DEVICE
);
5914 if (unlikely(dma_mapping_error(d
, mapping
))) {
5915 if (net_ratelimit())
5916 netif_err(tp
, drv
, tp
->dev
,
5917 "Failed to map TX fragments DMA!\n");
5921 /* Anti gcc 2.95.3 bugware (sic) */
5922 status
= opts
[0] | len
|
5923 (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
5925 txd
->opts1
= cpu_to_le32(status
);
5926 txd
->opts2
= cpu_to_le32(opts
[1]);
5927 txd
->addr
= cpu_to_le64(mapping
);
5929 tp
->tx_skb
[entry
].len
= len
;
5933 tp
->tx_skb
[entry
].skb
= skb
;
5934 txd
->opts1
|= cpu_to_le32(LastFrag
);
5940 rtl8169_tx_clear_range(tp
, tp
->cur_tx
+ 1, cur_frag
);
5944 static bool rtl_skb_pad(struct sk_buff
*skb
)
5946 if (skb_padto(skb
, ETH_ZLEN
))
5948 skb_put(skb
, ETH_ZLEN
- skb
->len
);
5952 static bool rtl_test_hw_pad_bug(struct rtl8169_private
*tp
, struct sk_buff
*skb
)
5954 return skb
->len
< ETH_ZLEN
&& tp
->mac_version
== RTL_GIGA_MAC_VER_34
;
5957 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
5958 struct net_device
*dev
);
5959 /* r8169_csum_workaround()
5960 * The hw limites the value the transport offset. When the offset is out of the
5961 * range, calculate the checksum by sw.
5963 static void r8169_csum_workaround(struct rtl8169_private
*tp
,
5964 struct sk_buff
*skb
)
5966 if (skb_shinfo(skb
)->gso_size
) {
5967 netdev_features_t features
= tp
->dev
->features
;
5968 struct sk_buff
*segs
, *nskb
;
5970 features
&= ~(NETIF_F_SG
| NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
);
5971 segs
= skb_gso_segment(skb
, features
);
5972 if (IS_ERR(segs
) || !segs
)
5979 rtl8169_start_xmit(nskb
, tp
->dev
);
5983 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5984 if (skb_checksum_help(skb
) < 0)
5987 rtl8169_start_xmit(skb
, tp
->dev
);
5989 struct net_device_stats
*stats
;
5992 stats
= &tp
->dev
->stats
;
5993 stats
->tx_dropped
++;
5998 /* msdn_giant_send_check()
5999 * According to the document of microsoft, the TCP Pseudo Header excludes the
6000 * packet length for IPv6 TCP large packets.
6002 static int msdn_giant_send_check(struct sk_buff
*skb
)
6004 const struct ipv6hdr
*ipv6h
;
6008 ret
= skb_cow_head(skb
, 0);
6012 ipv6h
= ipv6_hdr(skb
);
6016 th
->check
= ~tcp_v6_check(0, &ipv6h
->saddr
, &ipv6h
->daddr
, 0);
6021 static inline __be16
get_protocol(struct sk_buff
*skb
)
6025 if (skb
->protocol
== htons(ETH_P_8021Q
))
6026 protocol
= vlan_eth_hdr(skb
)->h_vlan_encapsulated_proto
;
6028 protocol
= skb
->protocol
;
6033 static bool rtl8169_tso_csum_v1(struct rtl8169_private
*tp
,
6034 struct sk_buff
*skb
, u32
*opts
)
6036 u32 mss
= skb_shinfo(skb
)->gso_size
;
6040 opts
[0] |= min(mss
, TD_MSS_MAX
) << TD0_MSS_SHIFT
;
6041 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6042 const struct iphdr
*ip
= ip_hdr(skb
);
6044 if (ip
->protocol
== IPPROTO_TCP
)
6045 opts
[0] |= TD0_IP_CS
| TD0_TCP_CS
;
6046 else if (ip
->protocol
== IPPROTO_UDP
)
6047 opts
[0] |= TD0_IP_CS
| TD0_UDP_CS
;
6055 static bool rtl8169_tso_csum_v2(struct rtl8169_private
*tp
,
6056 struct sk_buff
*skb
, u32
*opts
)
6058 u32 transport_offset
= (u32
)skb_transport_offset(skb
);
6059 u32 mss
= skb_shinfo(skb
)->gso_size
;
6062 if (transport_offset
> GTTCPHO_MAX
) {
6063 netif_warn(tp
, tx_err
, tp
->dev
,
6064 "Invalid transport offset 0x%x for TSO\n",
6069 switch (get_protocol(skb
)) {
6070 case htons(ETH_P_IP
):
6071 opts
[0] |= TD1_GTSENV4
;
6074 case htons(ETH_P_IPV6
):
6075 if (msdn_giant_send_check(skb
))
6078 opts
[0] |= TD1_GTSENV6
;
6086 opts
[0] |= transport_offset
<< GTTCPHO_SHIFT
;
6087 opts
[1] |= min(mss
, TD_MSS_MAX
) << TD1_MSS_SHIFT
;
6088 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6091 if (unlikely(rtl_test_hw_pad_bug(tp
, skb
)))
6092 return skb_checksum_help(skb
) == 0 && rtl_skb_pad(skb
);
6094 if (transport_offset
> TCPHO_MAX
) {
6095 netif_warn(tp
, tx_err
, tp
->dev
,
6096 "Invalid transport offset 0x%x\n",
6101 switch (get_protocol(skb
)) {
6102 case htons(ETH_P_IP
):
6103 opts
[1] |= TD1_IPv4_CS
;
6104 ip_protocol
= ip_hdr(skb
)->protocol
;
6107 case htons(ETH_P_IPV6
):
6108 opts
[1] |= TD1_IPv6_CS
;
6109 ip_protocol
= ipv6_hdr(skb
)->nexthdr
;
6113 ip_protocol
= IPPROTO_RAW
;
6117 if (ip_protocol
== IPPROTO_TCP
)
6118 opts
[1] |= TD1_TCP_CS
;
6119 else if (ip_protocol
== IPPROTO_UDP
)
6120 opts
[1] |= TD1_UDP_CS
;
6124 opts
[1] |= transport_offset
<< TCPHO_SHIFT
;
6126 if (unlikely(rtl_test_hw_pad_bug(tp
, skb
)))
6127 return rtl_skb_pad(skb
);
6133 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
6134 struct net_device
*dev
)
6136 struct rtl8169_private
*tp
= netdev_priv(dev
);
6137 unsigned int entry
= tp
->cur_tx
% NUM_TX_DESC
;
6138 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
6139 void __iomem
*ioaddr
= tp
->mmio_addr
;
6140 struct device
*d
= &tp
->pci_dev
->dev
;
6146 if (unlikely(!TX_FRAGS_READY_FOR(tp
, skb_shinfo(skb
)->nr_frags
))) {
6147 netif_err(tp
, drv
, dev
, "BUG! Tx Ring full when queue awake!\n");
6151 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
6154 opts
[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb
));
6157 if (!tp
->tso_csum(tp
, skb
, opts
)) {
6158 r8169_csum_workaround(tp
, skb
);
6159 return NETDEV_TX_OK
;
6162 len
= skb_headlen(skb
);
6163 mapping
= dma_map_single(d
, skb
->data
, len
, DMA_TO_DEVICE
);
6164 if (unlikely(dma_mapping_error(d
, mapping
))) {
6165 if (net_ratelimit())
6166 netif_err(tp
, drv
, dev
, "Failed to map TX DMA!\n");
6170 tp
->tx_skb
[entry
].len
= len
;
6171 txd
->addr
= cpu_to_le64(mapping
);
6173 frags
= rtl8169_xmit_frags(tp
, skb
, opts
);
6177 opts
[0] |= FirstFrag
;
6179 opts
[0] |= FirstFrag
| LastFrag
;
6180 tp
->tx_skb
[entry
].skb
= skb
;
6183 txd
->opts2
= cpu_to_le32(opts
[1]);
6185 skb_tx_timestamp(skb
);
6189 /* Anti gcc 2.95.3 bugware (sic) */
6190 status
= opts
[0] | len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
6191 txd
->opts1
= cpu_to_le32(status
);
6193 tp
->cur_tx
+= frags
+ 1;
6197 RTL_W8(TxPoll
, NPQ
);
6201 if (!TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
)) {
6202 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6203 * not miss a ring update when it notices a stopped queue.
6206 netif_stop_queue(dev
);
6207 /* Sync with rtl_tx:
6208 * - publish queue status and cur_tx ring index (write barrier)
6209 * - refresh dirty_tx ring index (read barrier).
6210 * May the current thread have a pessimistic view of the ring
6211 * status and forget to wake up queue, a racing rtl_tx thread
6215 if (TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
))
6216 netif_wake_queue(dev
);
6219 return NETDEV_TX_OK
;
6222 rtl8169_unmap_tx_skb(d
, tp
->tx_skb
+ entry
, txd
);
6224 dev_kfree_skb_any(skb
);
6225 dev
->stats
.tx_dropped
++;
6226 return NETDEV_TX_OK
;
6229 netif_stop_queue(dev
);
6230 dev
->stats
.tx_dropped
++;
6231 return NETDEV_TX_BUSY
;
6234 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
6236 struct rtl8169_private
*tp
= netdev_priv(dev
);
6237 struct pci_dev
*pdev
= tp
->pci_dev
;
6238 u16 pci_status
, pci_cmd
;
6240 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
6241 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
6243 netif_err(tp
, intr
, dev
, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6244 pci_cmd
, pci_status
);
6247 * The recovery sequence below admits a very elaborated explanation:
6248 * - it seems to work;
6249 * - I did not see what else could be done;
6250 * - it makes iop3xx happy.
6252 * Feel free to adjust to your needs.
6254 if (pdev
->broken_parity_status
)
6255 pci_cmd
&= ~PCI_COMMAND_PARITY
;
6257 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
6259 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
6261 pci_write_config_word(pdev
, PCI_STATUS
,
6262 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
6263 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
6264 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
6266 /* The infamous DAC f*ckup only happens at boot time */
6267 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->cur_rx
) {
6268 void __iomem
*ioaddr
= tp
->mmio_addr
;
6270 netif_info(tp
, intr
, dev
, "disabling PCI DAC\n");
6271 tp
->cp_cmd
&= ~PCIDAC
;
6272 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
6273 dev
->features
&= ~NETIF_F_HIGHDMA
;
6276 rtl8169_hw_reset(tp
);
6278 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
6281 static void rtl_tx(struct net_device
*dev
, struct rtl8169_private
*tp
)
6283 unsigned int dirty_tx
, tx_left
;
6285 dirty_tx
= tp
->dirty_tx
;
6287 tx_left
= tp
->cur_tx
- dirty_tx
;
6289 while (tx_left
> 0) {
6290 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
6291 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
6295 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
6296 if (status
& DescOwn
)
6299 rtl8169_unmap_tx_skb(&tp
->pci_dev
->dev
, tx_skb
,
6300 tp
->TxDescArray
+ entry
);
6301 if (status
& LastFrag
) {
6302 u64_stats_update_begin(&tp
->tx_stats
.syncp
);
6303 tp
->tx_stats
.packets
++;
6304 tp
->tx_stats
.bytes
+= tx_skb
->skb
->len
;
6305 u64_stats_update_end(&tp
->tx_stats
.syncp
);
6306 dev_kfree_skb_any(tx_skb
->skb
);
6313 if (tp
->dirty_tx
!= dirty_tx
) {
6314 tp
->dirty_tx
= dirty_tx
;
6315 /* Sync with rtl8169_start_xmit:
6316 * - publish dirty_tx ring index (write barrier)
6317 * - refresh cur_tx ring index and queue status (read barrier)
6318 * May the current thread miss the stopped queue condition,
6319 * a racing xmit thread can only have a right view of the
6323 if (netif_queue_stopped(dev
) &&
6324 TX_FRAGS_READY_FOR(tp
, MAX_SKB_FRAGS
)) {
6325 netif_wake_queue(dev
);
6328 * 8168 hack: TxPoll requests are lost when the Tx packets are
6329 * too close. Let's kick an extra TxPoll request when a burst
6330 * of start_xmit activity is detected (if it is not detected,
6331 * it is slow enough). -- FR
6333 if (tp
->cur_tx
!= dirty_tx
) {
6334 void __iomem
*ioaddr
= tp
->mmio_addr
;
6336 RTL_W8(TxPoll
, NPQ
);
6341 static inline int rtl8169_fragmented_frame(u32 status
)
6343 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
6346 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, u32 opts1
)
6348 u32 status
= opts1
& RxProtoMask
;
6350 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
6351 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)))
6352 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
6354 skb_checksum_none_assert(skb
);
6357 static struct sk_buff
*rtl8169_try_rx_copy(void *data
,
6358 struct rtl8169_private
*tp
,
6362 struct sk_buff
*skb
;
6363 struct device
*d
= &tp
->pci_dev
->dev
;
6365 data
= rtl8169_align(data
);
6366 dma_sync_single_for_cpu(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
6368 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
6370 memcpy(skb
->data
, data
, pkt_size
);
6371 dma_sync_single_for_device(d
, addr
, pkt_size
, DMA_FROM_DEVICE
);
6376 static int rtl_rx(struct net_device
*dev
, struct rtl8169_private
*tp
, u32 budget
)
6378 unsigned int cur_rx
, rx_left
;
6381 cur_rx
= tp
->cur_rx
;
6383 for (rx_left
= min(budget
, NUM_RX_DESC
); rx_left
> 0; rx_left
--, cur_rx
++) {
6384 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
6385 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
6389 status
= le32_to_cpu(desc
->opts1
) & tp
->opts1_mask
;
6391 if (status
& DescOwn
)
6393 if (unlikely(status
& RxRES
)) {
6394 netif_info(tp
, rx_err
, dev
, "Rx ERROR. status = %08x\n",
6396 dev
->stats
.rx_errors
++;
6397 if (status
& (RxRWT
| RxRUNT
))
6398 dev
->stats
.rx_length_errors
++;
6400 dev
->stats
.rx_crc_errors
++;
6401 if (status
& RxFOVF
) {
6402 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
6403 dev
->stats
.rx_fifo_errors
++;
6405 if ((status
& (RxRUNT
| RxCRC
)) &&
6406 !(status
& (RxRWT
| RxFOVF
)) &&
6407 (dev
->features
& NETIF_F_RXALL
))
6410 struct sk_buff
*skb
;
6415 addr
= le64_to_cpu(desc
->addr
);
6416 if (likely(!(dev
->features
& NETIF_F_RXFCS
)))
6417 pkt_size
= (status
& 0x00003fff) - 4;
6419 pkt_size
= status
& 0x00003fff;
6422 * The driver does not support incoming fragmented
6423 * frames. They are seen as a symptom of over-mtu
6426 if (unlikely(rtl8169_fragmented_frame(status
))) {
6427 dev
->stats
.rx_dropped
++;
6428 dev
->stats
.rx_length_errors
++;
6429 goto release_descriptor
;
6432 skb
= rtl8169_try_rx_copy(tp
->Rx_databuff
[entry
],
6433 tp
, pkt_size
, addr
);
6435 dev
->stats
.rx_dropped
++;
6436 goto release_descriptor
;
6439 rtl8169_rx_csum(skb
, status
);
6440 skb_put(skb
, pkt_size
);
6441 skb
->protocol
= eth_type_trans(skb
, dev
);
6443 rtl8169_rx_vlan_tag(desc
, skb
);
6445 napi_gro_receive(&tp
->napi
, skb
);
6447 u64_stats_update_begin(&tp
->rx_stats
.syncp
);
6448 tp
->rx_stats
.packets
++;
6449 tp
->rx_stats
.bytes
+= pkt_size
;
6450 u64_stats_update_end(&tp
->rx_stats
.syncp
);
6455 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
6458 count
= cur_rx
- tp
->cur_rx
;
6459 tp
->cur_rx
= cur_rx
;
6464 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
6466 struct net_device
*dev
= dev_instance
;
6467 struct rtl8169_private
*tp
= netdev_priv(dev
);
6471 status
= rtl_get_events(tp
);
6472 if (status
&& status
!= 0xffff) {
6473 status
&= RTL_EVENT_NAPI
| tp
->event_slow
;
6477 rtl_irq_disable(tp
);
6478 napi_schedule(&tp
->napi
);
6481 return IRQ_RETVAL(handled
);
6485 * Workqueue context.
6487 static void rtl_slow_event_work(struct rtl8169_private
*tp
)
6489 struct net_device
*dev
= tp
->dev
;
6492 status
= rtl_get_events(tp
) & tp
->event_slow
;
6493 rtl_ack_events(tp
, status
);
6495 if (unlikely(status
& RxFIFOOver
)) {
6496 switch (tp
->mac_version
) {
6497 /* Work around for rx fifo overflow */
6498 case RTL_GIGA_MAC_VER_11
:
6499 netif_stop_queue(dev
);
6500 /* XXX - Hack alert. See rtl_task(). */
6501 set_bit(RTL_FLAG_TASK_RESET_PENDING
, tp
->wk
.flags
);
6507 if (unlikely(status
& SYSErr
))
6508 rtl8169_pcierr_interrupt(dev
);
6510 if (status
& LinkChg
)
6511 __rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
, true);
6513 rtl_irq_enable_all(tp
);
6516 static void rtl_task(struct work_struct
*work
)
6518 static const struct {
6520 void (*action
)(struct rtl8169_private
*);
6522 /* XXX - keep rtl_slow_event_work() as first element. */
6523 { RTL_FLAG_TASK_SLOW_PENDING
, rtl_slow_event_work
},
6524 { RTL_FLAG_TASK_RESET_PENDING
, rtl_reset_work
},
6525 { RTL_FLAG_TASK_PHY_PENDING
, rtl_phy_work
}
6527 struct rtl8169_private
*tp
=
6528 container_of(work
, struct rtl8169_private
, wk
.work
);
6529 struct net_device
*dev
= tp
->dev
;
6534 if (!netif_running(dev
) ||
6535 !test_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
))
6538 for (i
= 0; i
< ARRAY_SIZE(rtl_work
); i
++) {
6541 pending
= test_and_clear_bit(rtl_work
[i
].bitnr
, tp
->wk
.flags
);
6543 rtl_work
[i
].action(tp
);
6547 rtl_unlock_work(tp
);
6550 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
6552 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
6553 struct net_device
*dev
= tp
->dev
;
6554 u16 enable_mask
= RTL_EVENT_NAPI
| tp
->event_slow
;
6558 status
= rtl_get_events(tp
);
6559 rtl_ack_events(tp
, status
& ~tp
->event_slow
);
6561 if (status
& RTL_EVENT_NAPI_RX
)
6562 work_done
= rtl_rx(dev
, tp
, (u32
) budget
);
6564 if (status
& RTL_EVENT_NAPI_TX
)
6567 if (status
& tp
->event_slow
) {
6568 enable_mask
&= ~tp
->event_slow
;
6570 rtl_schedule_task(tp
, RTL_FLAG_TASK_SLOW_PENDING
);
6573 if (work_done
< budget
) {
6574 napi_complete(napi
);
6576 rtl_irq_enable(tp
, enable_mask
);
6583 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
6585 struct rtl8169_private
*tp
= netdev_priv(dev
);
6587 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
6590 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
6591 RTL_W32(RxMissed
, 0);
6594 static void rtl8169_down(struct net_device
*dev
)
6596 struct rtl8169_private
*tp
= netdev_priv(dev
);
6597 void __iomem
*ioaddr
= tp
->mmio_addr
;
6599 del_timer_sync(&tp
->timer
);
6601 napi_disable(&tp
->napi
);
6602 netif_stop_queue(dev
);
6604 rtl8169_hw_reset(tp
);
6606 * At this point device interrupts can not be enabled in any function,
6607 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6608 * and napi is disabled (rtl8169_poll).
6610 rtl8169_rx_missed(dev
, ioaddr
);
6612 /* Give a racing hard_start_xmit a few cycles to complete. */
6613 synchronize_sched();
6615 rtl8169_tx_clear(tp
);
6617 rtl8169_rx_clear(tp
);
6619 rtl_pll_power_down(tp
);
6622 static int rtl8169_close(struct net_device
*dev
)
6624 struct rtl8169_private
*tp
= netdev_priv(dev
);
6625 struct pci_dev
*pdev
= tp
->pci_dev
;
6627 pm_runtime_get_sync(&pdev
->dev
);
6629 /* Update counters before going down */
6630 rtl8169_update_counters(dev
);
6633 clear_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
6636 rtl_unlock_work(tp
);
6638 cancel_work_sync(&tp
->wk
.work
);
6640 free_irq(pdev
->irq
, dev
);
6642 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
6644 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
6646 tp
->TxDescArray
= NULL
;
6647 tp
->RxDescArray
= NULL
;
6649 pm_runtime_put_sync(&pdev
->dev
);
6654 #ifdef CONFIG_NET_POLL_CONTROLLER
6655 static void rtl8169_netpoll(struct net_device
*dev
)
6657 struct rtl8169_private
*tp
= netdev_priv(dev
);
6659 rtl8169_interrupt(tp
->pci_dev
->irq
, dev
);
6663 static int rtl_open(struct net_device
*dev
)
6665 struct rtl8169_private
*tp
= netdev_priv(dev
);
6666 void __iomem
*ioaddr
= tp
->mmio_addr
;
6667 struct pci_dev
*pdev
= tp
->pci_dev
;
6668 int retval
= -ENOMEM
;
6670 pm_runtime_get_sync(&pdev
->dev
);
6673 * Rx and Tx descriptors needs 256 bytes alignment.
6674 * dma_alloc_coherent provides more.
6676 tp
->TxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
,
6677 &tp
->TxPhyAddr
, GFP_KERNEL
);
6678 if (!tp
->TxDescArray
)
6679 goto err_pm_runtime_put
;
6681 tp
->RxDescArray
= dma_alloc_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
,
6682 &tp
->RxPhyAddr
, GFP_KERNEL
);
6683 if (!tp
->RxDescArray
)
6686 retval
= rtl8169_init_ring(dev
);
6690 INIT_WORK(&tp
->wk
.work
, rtl_task
);
6694 rtl_request_firmware(tp
);
6696 retval
= request_irq(pdev
->irq
, rtl8169_interrupt
,
6697 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
6700 goto err_release_fw_2
;
6704 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
6706 napi_enable(&tp
->napi
);
6708 rtl8169_init_phy(dev
, tp
);
6710 __rtl8169_set_features(dev
, dev
->features
);
6712 rtl_pll_power_up(tp
);
6716 netif_start_queue(dev
);
6718 rtl_unlock_work(tp
);
6720 tp
->saved_wolopts
= 0;
6721 pm_runtime_put_noidle(&pdev
->dev
);
6723 rtl8169_check_link_status(dev
, tp
, ioaddr
);
6728 rtl_release_firmware(tp
);
6729 rtl8169_rx_clear(tp
);
6731 dma_free_coherent(&pdev
->dev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
6733 tp
->RxDescArray
= NULL
;
6735 dma_free_coherent(&pdev
->dev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
6737 tp
->TxDescArray
= NULL
;
6739 pm_runtime_put_noidle(&pdev
->dev
);
6743 static struct rtnl_link_stats64
*
6744 rtl8169_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
6746 struct rtl8169_private
*tp
= netdev_priv(dev
);
6747 void __iomem
*ioaddr
= tp
->mmio_addr
;
6750 if (netif_running(dev
))
6751 rtl8169_rx_missed(dev
, ioaddr
);
6754 start
= u64_stats_fetch_begin_irq(&tp
->rx_stats
.syncp
);
6755 stats
->rx_packets
= tp
->rx_stats
.packets
;
6756 stats
->rx_bytes
= tp
->rx_stats
.bytes
;
6757 } while (u64_stats_fetch_retry_irq(&tp
->rx_stats
.syncp
, start
));
6761 start
= u64_stats_fetch_begin_irq(&tp
->tx_stats
.syncp
);
6762 stats
->tx_packets
= tp
->tx_stats
.packets
;
6763 stats
->tx_bytes
= tp
->tx_stats
.bytes
;
6764 } while (u64_stats_fetch_retry_irq(&tp
->tx_stats
.syncp
, start
));
6766 stats
->rx_dropped
= dev
->stats
.rx_dropped
;
6767 stats
->tx_dropped
= dev
->stats
.tx_dropped
;
6768 stats
->rx_length_errors
= dev
->stats
.rx_length_errors
;
6769 stats
->rx_errors
= dev
->stats
.rx_errors
;
6770 stats
->rx_crc_errors
= dev
->stats
.rx_crc_errors
;
6771 stats
->rx_fifo_errors
= dev
->stats
.rx_fifo_errors
;
6772 stats
->rx_missed_errors
= dev
->stats
.rx_missed_errors
;
6777 static void rtl8169_net_suspend(struct net_device
*dev
)
6779 struct rtl8169_private
*tp
= netdev_priv(dev
);
6781 if (!netif_running(dev
))
6784 netif_device_detach(dev
);
6785 netif_stop_queue(dev
);
6788 napi_disable(&tp
->napi
);
6789 clear_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
6790 rtl_unlock_work(tp
);
6792 rtl_pll_power_down(tp
);
6797 static int rtl8169_suspend(struct device
*device
)
6799 struct pci_dev
*pdev
= to_pci_dev(device
);
6800 struct net_device
*dev
= pci_get_drvdata(pdev
);
6802 rtl8169_net_suspend(dev
);
6807 static void __rtl8169_resume(struct net_device
*dev
)
6809 struct rtl8169_private
*tp
= netdev_priv(dev
);
6811 netif_device_attach(dev
);
6813 rtl_pll_power_up(tp
);
6816 napi_enable(&tp
->napi
);
6817 set_bit(RTL_FLAG_TASK_ENABLED
, tp
->wk
.flags
);
6818 rtl_unlock_work(tp
);
6820 rtl_schedule_task(tp
, RTL_FLAG_TASK_RESET_PENDING
);
6823 static int rtl8169_resume(struct device
*device
)
6825 struct pci_dev
*pdev
= to_pci_dev(device
);
6826 struct net_device
*dev
= pci_get_drvdata(pdev
);
6827 struct rtl8169_private
*tp
= netdev_priv(dev
);
6829 rtl8169_init_phy(dev
, tp
);
6831 if (netif_running(dev
))
6832 __rtl8169_resume(dev
);
6837 static int rtl8169_runtime_suspend(struct device
*device
)
6839 struct pci_dev
*pdev
= to_pci_dev(device
);
6840 struct net_device
*dev
= pci_get_drvdata(pdev
);
6841 struct rtl8169_private
*tp
= netdev_priv(dev
);
6843 if (!tp
->TxDescArray
)
6847 tp
->saved_wolopts
= __rtl8169_get_wol(tp
);
6848 __rtl8169_set_wol(tp
, WAKE_ANY
);
6849 rtl_unlock_work(tp
);
6851 rtl8169_net_suspend(dev
);
6856 static int rtl8169_runtime_resume(struct device
*device
)
6858 struct pci_dev
*pdev
= to_pci_dev(device
);
6859 struct net_device
*dev
= pci_get_drvdata(pdev
);
6860 struct rtl8169_private
*tp
= netdev_priv(dev
);
6862 if (!tp
->TxDescArray
)
6866 __rtl8169_set_wol(tp
, tp
->saved_wolopts
);
6867 tp
->saved_wolopts
= 0;
6868 rtl_unlock_work(tp
);
6870 rtl8169_init_phy(dev
, tp
);
6872 __rtl8169_resume(dev
);
6877 static int rtl8169_runtime_idle(struct device
*device
)
6879 struct pci_dev
*pdev
= to_pci_dev(device
);
6880 struct net_device
*dev
= pci_get_drvdata(pdev
);
6881 struct rtl8169_private
*tp
= netdev_priv(dev
);
6883 return tp
->TxDescArray
? -EBUSY
: 0;
6886 static const struct dev_pm_ops rtl8169_pm_ops
= {
6887 .suspend
= rtl8169_suspend
,
6888 .resume
= rtl8169_resume
,
6889 .freeze
= rtl8169_suspend
,
6890 .thaw
= rtl8169_resume
,
6891 .poweroff
= rtl8169_suspend
,
6892 .restore
= rtl8169_resume
,
6893 .runtime_suspend
= rtl8169_runtime_suspend
,
6894 .runtime_resume
= rtl8169_runtime_resume
,
6895 .runtime_idle
= rtl8169_runtime_idle
,
6898 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
6900 #else /* !CONFIG_PM */
6902 #define RTL8169_PM_OPS NULL
6904 #endif /* !CONFIG_PM */
6906 static void rtl_wol_shutdown_quirk(struct rtl8169_private
*tp
)
6908 void __iomem
*ioaddr
= tp
->mmio_addr
;
6910 /* WoL fails with 8168b when the receiver is disabled. */
6911 switch (tp
->mac_version
) {
6912 case RTL_GIGA_MAC_VER_11
:
6913 case RTL_GIGA_MAC_VER_12
:
6914 case RTL_GIGA_MAC_VER_17
:
6915 pci_clear_master(tp
->pci_dev
);
6917 RTL_W8(ChipCmd
, CmdRxEnb
);
6926 static void rtl_shutdown(struct pci_dev
*pdev
)
6928 struct net_device
*dev
= pci_get_drvdata(pdev
);
6929 struct rtl8169_private
*tp
= netdev_priv(dev
);
6930 struct device
*d
= &pdev
->dev
;
6932 pm_runtime_get_sync(d
);
6934 rtl8169_net_suspend(dev
);
6936 /* Restore original MAC address */
6937 rtl_rar_set(tp
, dev
->perm_addr
);
6939 rtl8169_hw_reset(tp
);
6941 if (system_state
== SYSTEM_POWER_OFF
) {
6942 if (__rtl8169_get_wol(tp
) & WAKE_ANY
) {
6943 rtl_wol_suspend_quirk(tp
);
6944 rtl_wol_shutdown_quirk(tp
);
6947 pci_wake_from_d3(pdev
, true);
6948 pci_set_power_state(pdev
, PCI_D3hot
);
6951 pm_runtime_put_noidle(d
);
6954 static void rtl_remove_one(struct pci_dev
*pdev
)
6956 struct net_device
*dev
= pci_get_drvdata(pdev
);
6957 struct rtl8169_private
*tp
= netdev_priv(dev
);
6959 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
6960 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
6961 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
6962 rtl8168_driver_stop(tp
);
6965 netif_napi_del(&tp
->napi
);
6967 unregister_netdev(dev
);
6969 rtl_release_firmware(tp
);
6971 if (pci_dev_run_wake(pdev
))
6972 pm_runtime_get_noresume(&pdev
->dev
);
6974 /* restore original MAC address */
6975 rtl_rar_set(tp
, dev
->perm_addr
);
6977 rtl_disable_msi(pdev
, tp
);
6978 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
6981 static const struct net_device_ops rtl_netdev_ops
= {
6982 .ndo_open
= rtl_open
,
6983 .ndo_stop
= rtl8169_close
,
6984 .ndo_get_stats64
= rtl8169_get_stats64
,
6985 .ndo_start_xmit
= rtl8169_start_xmit
,
6986 .ndo_tx_timeout
= rtl8169_tx_timeout
,
6987 .ndo_validate_addr
= eth_validate_addr
,
6988 .ndo_change_mtu
= rtl8169_change_mtu
,
6989 .ndo_fix_features
= rtl8169_fix_features
,
6990 .ndo_set_features
= rtl8169_set_features
,
6991 .ndo_set_mac_address
= rtl_set_mac_address
,
6992 .ndo_do_ioctl
= rtl8169_ioctl
,
6993 .ndo_set_rx_mode
= rtl_set_rx_mode
,
6994 #ifdef CONFIG_NET_POLL_CONTROLLER
6995 .ndo_poll_controller
= rtl8169_netpoll
,
7000 static const struct rtl_cfg_info
{
7001 void (*hw_start
)(struct net_device
*);
7002 unsigned int region
;
7007 } rtl_cfg_infos
[] = {
7009 .hw_start
= rtl_hw_start_8169
,
7012 .event_slow
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
,
7013 .features
= RTL_FEATURE_GMII
,
7014 .default_ver
= RTL_GIGA_MAC_VER_01
,
7017 .hw_start
= rtl_hw_start_8168
,
7020 .event_slow
= SYSErr
| LinkChg
| RxOverflow
,
7021 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
7022 .default_ver
= RTL_GIGA_MAC_VER_11
,
7025 .hw_start
= rtl_hw_start_8101
,
7028 .event_slow
= SYSErr
| LinkChg
| RxOverflow
| RxFIFOOver
|
7030 .features
= RTL_FEATURE_MSI
,
7031 .default_ver
= RTL_GIGA_MAC_VER_13
,
7035 /* Cfg9346_Unlock assumed. */
7036 static unsigned rtl_try_msi(struct rtl8169_private
*tp
,
7037 const struct rtl_cfg_info
*cfg
)
7039 void __iomem
*ioaddr
= tp
->mmio_addr
;
7043 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
7044 if (cfg
->features
& RTL_FEATURE_MSI
) {
7045 if (pci_enable_msi(tp
->pci_dev
)) {
7046 netif_info(tp
, hw
, tp
->dev
, "no MSI. Back to INTx.\n");
7049 msi
= RTL_FEATURE_MSI
;
7052 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
7053 RTL_W8(Config2
, cfg2
);
7057 DECLARE_RTL_COND(rtl_link_list_ready_cond
)
7059 void __iomem
*ioaddr
= tp
->mmio_addr
;
7061 return RTL_R8(MCU
) & LINK_LIST_RDY
;
7064 DECLARE_RTL_COND(rtl_rxtx_empty_cond
)
7066 void __iomem
*ioaddr
= tp
->mmio_addr
;
7068 return (RTL_R8(MCU
) & RXTX_EMPTY
) == RXTX_EMPTY
;
7071 static void rtl_hw_init_8168g(struct rtl8169_private
*tp
)
7073 void __iomem
*ioaddr
= tp
->mmio_addr
;
7076 tp
->ocp_base
= OCP_STD_PHY_BASE
;
7078 RTL_W32(MISC
, RTL_R32(MISC
) | RXDV_GATED_EN
);
7080 if (!rtl_udelay_loop_wait_high(tp
, &rtl_txcfg_empty_cond
, 100, 42))
7083 if (!rtl_udelay_loop_wait_high(tp
, &rtl_rxtx_empty_cond
, 100, 42))
7086 RTL_W8(ChipCmd
, RTL_R8(ChipCmd
) & ~(CmdTxEnb
| CmdRxEnb
));
7088 RTL_W8(MCU
, RTL_R8(MCU
) & ~NOW_IS_OOB
);
7090 data
= r8168_mac_ocp_read(tp
, 0xe8de);
7092 r8168_mac_ocp_write(tp
, 0xe8de, data
);
7094 if (!rtl_udelay_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42))
7097 data
= r8168_mac_ocp_read(tp
, 0xe8de);
7099 r8168_mac_ocp_write(tp
, 0xe8de, data
);
7101 if (!rtl_udelay_loop_wait_high(tp
, &rtl_link_list_ready_cond
, 100, 42))
7105 static void rtl_hw_initialize(struct rtl8169_private
*tp
)
7107 switch (tp
->mac_version
) {
7108 case RTL_GIGA_MAC_VER_40
:
7109 case RTL_GIGA_MAC_VER_41
:
7110 case RTL_GIGA_MAC_VER_42
:
7111 case RTL_GIGA_MAC_VER_43
:
7112 case RTL_GIGA_MAC_VER_44
:
7113 rtl_hw_init_8168g(tp
);
7122 rtl_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
7124 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
7125 const unsigned int region
= cfg
->region
;
7126 struct rtl8169_private
*tp
;
7127 struct mii_if_info
*mii
;
7128 struct net_device
*dev
;
7129 void __iomem
*ioaddr
;
7133 if (netif_msg_drv(&debug
)) {
7134 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
7135 MODULENAME
, RTL8169_VERSION
);
7138 dev
= alloc_etherdev(sizeof (*tp
));
7144 SET_NETDEV_DEV(dev
, &pdev
->dev
);
7145 dev
->netdev_ops
= &rtl_netdev_ops
;
7146 tp
= netdev_priv(dev
);
7149 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
7153 mii
->mdio_read
= rtl_mdio_read
;
7154 mii
->mdio_write
= rtl_mdio_write
;
7155 mii
->phy_id_mask
= 0x1f;
7156 mii
->reg_num_mask
= 0x1f;
7157 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
7159 /* disable ASPM completely as that cause random device stop working
7160 * problems as well as full system hangs for some PCIe devices users */
7161 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
7162 PCIE_LINK_STATE_CLKPM
);
7164 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7165 rc
= pci_enable_device(pdev
);
7167 netif_err(tp
, probe
, dev
, "enable failure\n");
7168 goto err_out_free_dev_1
;
7171 if (pci_set_mwi(pdev
) < 0)
7172 netif_info(tp
, probe
, dev
, "Mem-Wr-Inval unavailable\n");
7174 /* make sure PCI base addr 1 is MMIO */
7175 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
7176 netif_err(tp
, probe
, dev
,
7177 "region #%d not an MMIO resource, aborting\n",
7183 /* check for weird/broken PCI region reporting */
7184 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
7185 netif_err(tp
, probe
, dev
,
7186 "Invalid PCI region size(s), aborting\n");
7191 rc
= pci_request_regions(pdev
, MODULENAME
);
7193 netif_err(tp
, probe
, dev
, "could not request regions\n");
7197 tp
->cp_cmd
= RxChkSum
;
7199 if ((sizeof(dma_addr_t
) > 4) &&
7200 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
7201 tp
->cp_cmd
|= PCIDAC
;
7202 dev
->features
|= NETIF_F_HIGHDMA
;
7204 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
7206 netif_err(tp
, probe
, dev
, "DMA configuration failed\n");
7207 goto err_out_free_res_3
;
7211 /* ioremap MMIO region */
7212 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
7214 netif_err(tp
, probe
, dev
, "cannot remap MMIO, aborting\n");
7216 goto err_out_free_res_3
;
7218 tp
->mmio_addr
= ioaddr
;
7220 if (!pci_is_pcie(pdev
))
7221 netif_info(tp
, probe
, dev
, "not PCI Express\n");
7223 /* Identify chip attached to board */
7224 rtl8169_get_mac_version(tp
, dev
, cfg
->default_ver
);
7228 rtl_irq_disable(tp
);
7230 rtl_hw_initialize(tp
);
7234 rtl_ack_events(tp
, 0xffff);
7236 pci_set_master(pdev
);
7239 * Pretend we are using VLANs; This bypasses a nasty bug where
7240 * Interrupts stop flowing on high load on 8110SCd controllers.
7242 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
7243 tp
->cp_cmd
|= RxVlan
;
7245 rtl_init_mdio_ops(tp
);
7246 rtl_init_pll_power_ops(tp
);
7247 rtl_init_jumbo_ops(tp
);
7248 rtl_init_csi_ops(tp
);
7250 rtl8169_print_mac_version(tp
);
7252 chipset
= tp
->mac_version
;
7253 tp
->txd_version
= rtl_chip_infos
[chipset
].txd_version
;
7255 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
7256 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
7257 RTL_W8(Config5
, RTL_R8(Config5
) & (BWF
| MWF
| UWF
| LanWake
| PMEStatus
));
7258 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
7259 tp
->features
|= RTL_FEATURE_WOL
;
7260 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
7261 tp
->features
|= RTL_FEATURE_WOL
;
7262 tp
->features
|= rtl_try_msi(tp
, cfg
);
7263 RTL_W8(Cfg9346
, Cfg9346_Lock
);
7265 if (rtl_tbi_enabled(tp
)) {
7266 tp
->set_speed
= rtl8169_set_speed_tbi
;
7267 tp
->get_settings
= rtl8169_gset_tbi
;
7268 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
7269 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
7270 tp
->link_ok
= rtl8169_tbi_link_ok
;
7271 tp
->do_ioctl
= rtl_tbi_ioctl
;
7273 tp
->set_speed
= rtl8169_set_speed_xmii
;
7274 tp
->get_settings
= rtl8169_gset_xmii
;
7275 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
7276 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
7277 tp
->link_ok
= rtl8169_xmii_link_ok
;
7278 tp
->do_ioctl
= rtl_xmii_ioctl
;
7281 mutex_init(&tp
->wk
.mutex
);
7282 u64_stats_init(&tp
->rx_stats
.syncp
);
7283 u64_stats_init(&tp
->tx_stats
.syncp
);
7285 /* Get MAC address */
7286 for (i
= 0; i
< ETH_ALEN
; i
++)
7287 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
7289 dev
->ethtool_ops
= &rtl8169_ethtool_ops
;
7290 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
7292 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
7294 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7295 * properly for all devices */
7296 dev
->features
|= NETIF_F_RXCSUM
|
7297 NETIF_F_HW_VLAN_CTAG_TX
| NETIF_F_HW_VLAN_CTAG_RX
;
7299 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
7300 NETIF_F_RXCSUM
| NETIF_F_HW_VLAN_CTAG_TX
|
7301 NETIF_F_HW_VLAN_CTAG_RX
;
7302 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_TSO
|
7305 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
7306 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
7307 dev
->hw_features
&= ~NETIF_F_HW_VLAN_CTAG_RX
;
7309 if (tp
->txd_version
== RTL_TD_0
)
7310 tp
->tso_csum
= rtl8169_tso_csum_v1
;
7311 else if (tp
->txd_version
== RTL_TD_1
) {
7312 tp
->tso_csum
= rtl8169_tso_csum_v2
;
7313 dev
->hw_features
|= NETIF_F_IPV6_CSUM
| NETIF_F_TSO6
;
7317 dev
->hw_features
|= NETIF_F_RXALL
;
7318 dev
->hw_features
|= NETIF_F_RXFCS
;
7320 tp
->hw_start
= cfg
->hw_start
;
7321 tp
->event_slow
= cfg
->event_slow
;
7323 tp
->opts1_mask
= (tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) ?
7324 ~(RxBOVF
| RxFOVF
) : ~0;
7326 init_timer(&tp
->timer
);
7327 tp
->timer
.data
= (unsigned long) dev
;
7328 tp
->timer
.function
= rtl8169_phy_timer
;
7330 tp
->rtl_fw
= RTL_FIRMWARE_UNKNOWN
;
7332 rc
= register_netdev(dev
);
7336 pci_set_drvdata(pdev
, dev
);
7338 netif_info(tp
, probe
, dev
, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
7339 rtl_chip_infos
[chipset
].name
, ioaddr
, dev
->dev_addr
,
7340 (u32
)(RTL_R32(TxConfig
) & 0x9cf0f8ff), pdev
->irq
);
7341 if (rtl_chip_infos
[chipset
].jumbo_max
!= JUMBO_1K
) {
7342 netif_info(tp
, probe
, dev
, "jumbo features [frames: %d bytes, "
7343 "tx checksumming: %s]\n",
7344 rtl_chip_infos
[chipset
].jumbo_max
,
7345 rtl_chip_infos
[chipset
].jumbo_tx_csum
? "ok" : "ko");
7348 if (tp
->mac_version
== RTL_GIGA_MAC_VER_27
||
7349 tp
->mac_version
== RTL_GIGA_MAC_VER_28
||
7350 tp
->mac_version
== RTL_GIGA_MAC_VER_31
) {
7351 rtl8168_driver_start(tp
);
7354 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
7356 if (pci_dev_run_wake(pdev
))
7357 pm_runtime_put_noidle(&pdev
->dev
);
7359 netif_carrier_off(dev
);
7365 netif_napi_del(&tp
->napi
);
7366 rtl_disable_msi(pdev
, tp
);
7369 pci_release_regions(pdev
);
7371 pci_clear_mwi(pdev
);
7372 pci_disable_device(pdev
);
7378 static struct pci_driver rtl8169_pci_driver
= {
7380 .id_table
= rtl8169_pci_tbl
,
7381 .probe
= rtl_init_one
,
7382 .remove
= rtl_remove_one
,
7383 .shutdown
= rtl_shutdown
,
7384 .driver
.pm
= RTL8169_PM_OPS
,
7387 module_pci_driver(rtl8169_pci_driver
);