1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include "net_driver.h"
11 #include "ef10_regs.h"
14 #include "mcdi_pcol.h"
16 #include "workarounds.h"
18 #include "ef10_sriov.h"
20 #include <linux/jhash.h>
21 #include <linux/wait.h>
22 #include <linux/workqueue.h>
24 /* Hardware control for EF10 architecture including 'Huntington'. */
26 #define EFX_EF10_DRVGEN_EV 7
32 /* The reserved RSS context value */
33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
34 /* The maximum size of a shared RSS context */
35 /* TODO: this should really be from the mcdi protocol export */
36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
38 /* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
50 #define HUNT_FILTER_TBL_ROWS 8192
52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
54 #define EFX_EF10_FILTER_DEV_UC_MAX 32
55 #define EFX_EF10_FILTER_DEV_MC_MAX 256
58 struct efx_ef10_vlan
{
59 struct list_head list
;
63 /* Per-VLAN filters information */
64 struct efx_ef10_filter_vlan
{
65 struct list_head list
;
67 u16 uc
[EFX_EF10_FILTER_DEV_UC_MAX
];
68 u16 mc
[EFX_EF10_FILTER_DEV_MC_MAX
];
74 struct efx_ef10_dev_addr
{
78 struct efx_ef10_filter_table
{
79 /* The MCDI match masks supported by this fw & hw, in order of priority */
80 u32 rx_match_mcdi_flags
[
81 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM
];
82 unsigned int rx_match_count
;
85 unsigned long spec
; /* pointer to spec plus flag bits */
86 /* BUSY flag indicates that an update is in progress. AUTO_OLD is
87 * used to mark and sweep MAC filters for the device address lists.
89 #define EFX_EF10_FILTER_FLAG_BUSY 1UL
90 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
91 #define EFX_EF10_FILTER_FLAGS 3UL
92 u64 handle
; /* firmware handle */
94 wait_queue_head_t waitq
;
95 /* Shadow of net_device address lists, guarded by mac_lock */
96 struct efx_ef10_dev_addr dev_uc_list
[EFX_EF10_FILTER_DEV_UC_MAX
];
97 struct efx_ef10_dev_addr dev_mc_list
[EFX_EF10_FILTER_DEV_MC_MAX
];
102 /* Whether in multicast promiscuous mode when last changed */
103 bool mc_promisc_last
;
105 struct list_head vlan_list
;
108 /* An arbitrary search limit for the software hash table */
109 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
111 static void efx_ef10_rx_free_indir_table(struct efx_nic
*efx
);
112 static void efx_ef10_filter_table_remove(struct efx_nic
*efx
);
113 static int efx_ef10_filter_add_vlan(struct efx_nic
*efx
, u16 vid
);
114 static void efx_ef10_filter_del_vlan_internal(struct efx_nic
*efx
,
115 struct efx_ef10_filter_vlan
*vlan
);
116 static void efx_ef10_filter_del_vlan(struct efx_nic
*efx
, u16 vid
);
118 static int efx_ef10_get_warm_boot_count(struct efx_nic
*efx
)
122 efx_readd(efx
, ®
, ER_DZ_BIU_MC_SFT_STATUS
);
123 return EFX_DWORD_FIELD(reg
, EFX_WORD_1
) == 0xb007 ?
124 EFX_DWORD_FIELD(reg
, EFX_WORD_0
) : -EIO
;
127 static unsigned int efx_ef10_mem_map_size(struct efx_nic
*efx
)
131 bar
= efx
->type
->mem_bar
;
132 return resource_size(&efx
->pci_dev
->resource
[bar
]);
135 static bool efx_ef10_is_vf(struct efx_nic
*efx
)
137 return efx
->type
->is_vf
;
140 static int efx_ef10_get_pf_index(struct efx_nic
*efx
)
142 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_FUNCTION_INFO_OUT_LEN
);
143 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
147 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_FUNCTION_INFO
, NULL
, 0, outbuf
,
148 sizeof(outbuf
), &outlen
);
151 if (outlen
< sizeof(outbuf
))
154 nic_data
->pf_index
= MCDI_DWORD(outbuf
, GET_FUNCTION_INFO_OUT_PF
);
158 #ifdef CONFIG_SFC_SRIOV
159 static int efx_ef10_get_vf_index(struct efx_nic
*efx
)
161 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_FUNCTION_INFO_OUT_LEN
);
162 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
166 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_FUNCTION_INFO
, NULL
, 0, outbuf
,
167 sizeof(outbuf
), &outlen
);
170 if (outlen
< sizeof(outbuf
))
173 nic_data
->vf_index
= MCDI_DWORD(outbuf
, GET_FUNCTION_INFO_OUT_VF
);
178 static int efx_ef10_init_datapath_caps(struct efx_nic
*efx
)
180 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_CAPABILITIES_V2_OUT_LEN
);
181 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
185 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN
!= 0);
187 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_CAPABILITIES
, NULL
, 0,
188 outbuf
, sizeof(outbuf
), &outlen
);
191 if (outlen
< MC_CMD_GET_CAPABILITIES_OUT_LEN
) {
192 netif_err(efx
, drv
, efx
->net_dev
,
193 "unable to read datapath firmware capabilities\n");
197 nic_data
->datapath_caps
=
198 MCDI_DWORD(outbuf
, GET_CAPABILITIES_OUT_FLAGS1
);
200 if (outlen
>= MC_CMD_GET_CAPABILITIES_V2_OUT_LEN
)
201 nic_data
->datapath_caps2
= MCDI_DWORD(outbuf
,
202 GET_CAPABILITIES_V2_OUT_FLAGS2
);
204 nic_data
->datapath_caps2
= 0;
206 /* record the DPCPU firmware IDs to determine VEB vswitching support.
208 nic_data
->rx_dpcpu_fw_id
=
209 MCDI_WORD(outbuf
, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID
);
210 nic_data
->tx_dpcpu_fw_id
=
211 MCDI_WORD(outbuf
, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID
);
213 if (!(nic_data
->datapath_caps
&
214 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN
))) {
215 netif_err(efx
, probe
, efx
->net_dev
,
216 "current firmware does not support an RX prefix\n");
223 static int efx_ef10_get_sysclk_freq(struct efx_nic
*efx
)
225 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_CLOCK_OUT_LEN
);
228 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_CLOCK
, NULL
, 0,
229 outbuf
, sizeof(outbuf
), NULL
);
232 rc
= MCDI_DWORD(outbuf
, GET_CLOCK_OUT_SYS_FREQ
);
233 return rc
> 0 ? rc
: -ERANGE
;
236 static int efx_ef10_get_timer_workarounds(struct efx_nic
*efx
)
238 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
239 unsigned int implemented
;
240 unsigned int enabled
;
243 nic_data
->workaround_35388
= false;
244 nic_data
->workaround_61265
= false;
246 rc
= efx_mcdi_get_workarounds(efx
, &implemented
, &enabled
);
249 /* Firmware without GET_WORKAROUNDS - not a problem. */
251 } else if (rc
== 0) {
252 /* Bug61265 workaround is always enabled if implemented. */
253 if (enabled
& MC_CMD_GET_WORKAROUNDS_OUT_BUG61265
)
254 nic_data
->workaround_61265
= true;
256 if (enabled
& MC_CMD_GET_WORKAROUNDS_OUT_BUG35388
) {
257 nic_data
->workaround_35388
= true;
258 } else if (implemented
& MC_CMD_GET_WORKAROUNDS_OUT_BUG35388
) {
259 /* Workaround is implemented but not enabled.
262 rc
= efx_mcdi_set_workaround(efx
,
263 MC_CMD_WORKAROUND_BUG35388
,
266 nic_data
->workaround_35388
= true;
267 /* If we failed to set the workaround just carry on. */
272 netif_dbg(efx
, probe
, efx
->net_dev
,
273 "workaround for bug 35388 is %sabled\n",
274 nic_data
->workaround_35388
? "en" : "dis");
275 netif_dbg(efx
, probe
, efx
->net_dev
,
276 "workaround for bug 61265 is %sabled\n",
277 nic_data
->workaround_61265
? "en" : "dis");
282 static void efx_ef10_process_timer_config(struct efx_nic
*efx
,
283 const efx_dword_t
*data
)
285 unsigned int max_count
;
287 if (EFX_EF10_WORKAROUND_61265(efx
)) {
288 efx
->timer_quantum_ns
= MCDI_DWORD(data
,
289 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS
);
290 efx
->timer_max_ns
= MCDI_DWORD(data
,
291 GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS
);
292 } else if (EFX_EF10_WORKAROUND_35388(efx
)) {
293 efx
->timer_quantum_ns
= MCDI_DWORD(data
,
294 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT
);
295 max_count
= MCDI_DWORD(data
,
296 GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT
);
297 efx
->timer_max_ns
= max_count
* efx
->timer_quantum_ns
;
299 efx
->timer_quantum_ns
= MCDI_DWORD(data
,
300 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT
);
301 max_count
= MCDI_DWORD(data
,
302 GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT
);
303 efx
->timer_max_ns
= max_count
* efx
->timer_quantum_ns
;
306 netif_dbg(efx
, probe
, efx
->net_dev
,
307 "got timer properties from MC: quantum %u ns; max %u ns\n",
308 efx
->timer_quantum_ns
, efx
->timer_max_ns
);
311 static int efx_ef10_get_timer_config(struct efx_nic
*efx
)
313 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN
);
316 rc
= efx_ef10_get_timer_workarounds(efx
);
320 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_GET_EVQ_TMR_PROPERTIES
, NULL
, 0,
321 outbuf
, sizeof(outbuf
), NULL
);
324 efx_ef10_process_timer_config(efx
, outbuf
);
325 } else if (rc
== -ENOSYS
|| rc
== -EPERM
) {
326 /* Not available - fall back to Huntington defaults. */
327 unsigned int quantum
;
329 rc
= efx_ef10_get_sysclk_freq(efx
);
333 quantum
= 1536000 / rc
; /* 1536 cycles */
334 efx
->timer_quantum_ns
= quantum
;
335 efx
->timer_max_ns
= efx
->type
->timer_period_max
* quantum
;
338 efx_mcdi_display_error(efx
, MC_CMD_GET_EVQ_TMR_PROPERTIES
,
339 MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_LEN
,
346 static int efx_ef10_get_mac_address_pf(struct efx_nic
*efx
, u8
*mac_address
)
348 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN
);
352 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN
!= 0);
354 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_MAC_ADDRESSES
, NULL
, 0,
355 outbuf
, sizeof(outbuf
), &outlen
);
358 if (outlen
< MC_CMD_GET_MAC_ADDRESSES_OUT_LEN
)
361 ether_addr_copy(mac_address
,
362 MCDI_PTR(outbuf
, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE
));
366 static int efx_ef10_get_mac_address_vf(struct efx_nic
*efx
, u8
*mac_address
)
368 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN
);
369 MCDI_DECLARE_BUF(outbuf
, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX
);
373 MCDI_SET_DWORD(inbuf
, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID
,
374 EVB_PORT_ID_ASSIGNED
);
375 rc
= efx_mcdi_rpc(efx
, MC_CMD_VPORT_GET_MAC_ADDRESSES
, inbuf
,
376 sizeof(inbuf
), outbuf
, sizeof(outbuf
), &outlen
);
380 if (outlen
< MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN
)
383 num_addrs
= MCDI_DWORD(outbuf
,
384 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT
);
386 WARN_ON(num_addrs
!= 1);
388 ether_addr_copy(mac_address
,
389 MCDI_PTR(outbuf
, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR
));
394 static ssize_t
efx_ef10_show_link_control_flag(struct device
*dev
,
395 struct device_attribute
*attr
,
398 struct efx_nic
*efx
= pci_get_drvdata(to_pci_dev(dev
));
400 return sprintf(buf
, "%d\n",
401 ((efx
->mcdi
->fn_flags
) &
402 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL
))
406 static ssize_t
efx_ef10_show_primary_flag(struct device
*dev
,
407 struct device_attribute
*attr
,
410 struct efx_nic
*efx
= pci_get_drvdata(to_pci_dev(dev
));
412 return sprintf(buf
, "%d\n",
413 ((efx
->mcdi
->fn_flags
) &
414 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY
))
418 static struct efx_ef10_vlan
*efx_ef10_find_vlan(struct efx_nic
*efx
, u16 vid
)
420 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
421 struct efx_ef10_vlan
*vlan
;
423 WARN_ON(!mutex_is_locked(&nic_data
->vlan_lock
));
425 list_for_each_entry(vlan
, &nic_data
->vlan_list
, list
) {
426 if (vlan
->vid
== vid
)
433 static int efx_ef10_add_vlan(struct efx_nic
*efx
, u16 vid
)
435 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
436 struct efx_ef10_vlan
*vlan
;
439 mutex_lock(&nic_data
->vlan_lock
);
441 vlan
= efx_ef10_find_vlan(efx
, vid
);
443 /* We add VID 0 on init. 8021q adds it on module init
444 * for all interfaces with VLAN filtring feature.
448 netif_warn(efx
, drv
, efx
->net_dev
,
449 "VLAN %u already added\n", vid
);
455 vlan
= kzalloc(sizeof(*vlan
), GFP_KERNEL
);
461 list_add_tail(&vlan
->list
, &nic_data
->vlan_list
);
463 if (efx
->filter_state
) {
464 mutex_lock(&efx
->mac_lock
);
465 down_write(&efx
->filter_sem
);
466 rc
= efx_ef10_filter_add_vlan(efx
, vlan
->vid
);
467 up_write(&efx
->filter_sem
);
468 mutex_unlock(&efx
->mac_lock
);
470 goto fail_filter_add_vlan
;
474 mutex_unlock(&nic_data
->vlan_lock
);
477 fail_filter_add_vlan
:
478 list_del(&vlan
->list
);
482 mutex_unlock(&nic_data
->vlan_lock
);
486 static void efx_ef10_del_vlan_internal(struct efx_nic
*efx
,
487 struct efx_ef10_vlan
*vlan
)
489 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
491 WARN_ON(!mutex_is_locked(&nic_data
->vlan_lock
));
493 if (efx
->filter_state
) {
494 down_write(&efx
->filter_sem
);
495 efx_ef10_filter_del_vlan(efx
, vlan
->vid
);
496 up_write(&efx
->filter_sem
);
499 list_del(&vlan
->list
);
503 static int efx_ef10_del_vlan(struct efx_nic
*efx
, u16 vid
)
505 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
506 struct efx_ef10_vlan
*vlan
;
509 /* 8021q removes VID 0 on module unload for all interfaces
510 * with VLAN filtering feature. We need to keep it to receive
516 mutex_lock(&nic_data
->vlan_lock
);
518 vlan
= efx_ef10_find_vlan(efx
, vid
);
520 netif_err(efx
, drv
, efx
->net_dev
,
521 "VLAN %u to be deleted not found\n", vid
);
524 efx_ef10_del_vlan_internal(efx
, vlan
);
527 mutex_unlock(&nic_data
->vlan_lock
);
532 static void efx_ef10_cleanup_vlans(struct efx_nic
*efx
)
534 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
535 struct efx_ef10_vlan
*vlan
, *next_vlan
;
537 mutex_lock(&nic_data
->vlan_lock
);
538 list_for_each_entry_safe(vlan
, next_vlan
, &nic_data
->vlan_list
, list
)
539 efx_ef10_del_vlan_internal(efx
, vlan
);
540 mutex_unlock(&nic_data
->vlan_lock
);
543 static DEVICE_ATTR(link_control_flag
, 0444, efx_ef10_show_link_control_flag
,
545 static DEVICE_ATTR(primary_flag
, 0444, efx_ef10_show_primary_flag
, NULL
);
547 static int efx_ef10_probe(struct efx_nic
*efx
)
549 struct efx_ef10_nic_data
*nic_data
;
550 struct net_device
*net_dev
= efx
->net_dev
;
553 /* We can have one VI for each 8K region. However, until we
554 * use TX option descriptors we need two TX queues per channel.
556 efx
->max_channels
= min_t(unsigned int,
558 efx_ef10_mem_map_size(efx
) /
559 (EFX_VI_PAGE_SIZE
* EFX_TXQ_TYPES
));
560 efx
->max_tx_channels
= efx
->max_channels
;
561 if (WARN_ON(efx
->max_channels
== 0))
564 nic_data
= kzalloc(sizeof(*nic_data
), GFP_KERNEL
);
567 efx
->nic_data
= nic_data
;
569 /* we assume later that we can copy from this buffer in dwords */
570 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2
% 4);
572 rc
= efx_nic_alloc_buffer(efx
, &nic_data
->mcdi_buf
,
573 8 + MCDI_CTL_SDU_LEN_MAX_V2
, GFP_KERNEL
);
577 /* Get the MC's warm boot count. In case it's rebooting right
578 * now, be prepared to retry.
582 rc
= efx_ef10_get_warm_boot_count(efx
);
589 nic_data
->warm_boot_count
= rc
;
591 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
593 nic_data
->vport_id
= EVB_PORT_ID_ASSIGNED
;
595 /* In case we're recovering from a crash (kexec), we want to
596 * cancel any outstanding request by the previous user of this
597 * function. We send a special message using the least
598 * significant bits of the 'high' (doorbell) register.
600 _efx_writed(efx
, cpu_to_le32(1), ER_DZ_MC_DB_HWRD
);
602 rc
= efx_mcdi_init(efx
);
606 /* Reset (most) configuration for this function */
607 rc
= efx_mcdi_reset(efx
, RESET_TYPE_ALL
);
611 /* Enable event logging */
612 rc
= efx_mcdi_log_ctrl(efx
, true, false, 0);
616 rc
= device_create_file(&efx
->pci_dev
->dev
,
617 &dev_attr_link_control_flag
);
621 rc
= device_create_file(&efx
->pci_dev
->dev
, &dev_attr_primary_flag
);
625 rc
= efx_ef10_get_pf_index(efx
);
629 rc
= efx_ef10_init_datapath_caps(efx
);
633 efx
->rx_packet_len_offset
=
634 ES_DZ_RX_PREFIX_PKTLEN_OFST
- ES_DZ_RX_PREFIX_SIZE
;
636 rc
= efx_mcdi_port_get_number(efx
);
640 net_dev
->dev_port
= rc
;
642 rc
= efx
->type
->get_mac_address(efx
, efx
->net_dev
->perm_addr
);
646 rc
= efx_ef10_get_timer_config(efx
);
650 rc
= efx_mcdi_mon_probe(efx
);
651 if (rc
&& rc
!= -EPERM
)
654 efx_ptp_probe(efx
, NULL
);
656 #ifdef CONFIG_SFC_SRIOV
657 if ((efx
->pci_dev
->physfn
) && (!efx
->pci_dev
->is_physfn
)) {
658 struct pci_dev
*pci_dev_pf
= efx
->pci_dev
->physfn
;
659 struct efx_nic
*efx_pf
= pci_get_drvdata(pci_dev_pf
);
661 efx_pf
->type
->get_mac_address(efx_pf
, nic_data
->port_id
);
664 ether_addr_copy(nic_data
->port_id
, efx
->net_dev
->perm_addr
);
666 INIT_LIST_HEAD(&nic_data
->vlan_list
);
667 mutex_init(&nic_data
->vlan_lock
);
669 /* Add unspecified VID to support VLAN filtering being disabled */
670 rc
= efx_ef10_add_vlan(efx
, EFX_FILTER_VID_UNSPEC
);
672 goto fail_add_vid_unspec
;
674 /* If VLAN filtering is enabled, we need VID 0 to get untagged
675 * traffic. It is added automatically if 8021q module is loaded,
676 * but we can't rely on it since module may be not loaded.
678 rc
= efx_ef10_add_vlan(efx
, 0);
685 efx_ef10_cleanup_vlans(efx
);
687 mutex_destroy(&nic_data
->vlan_lock
);
689 efx_mcdi_mon_remove(efx
);
691 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_primary_flag
);
693 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_link_control_flag
);
697 efx_nic_free_buffer(efx
, &nic_data
->mcdi_buf
);
700 efx
->nic_data
= NULL
;
704 static int efx_ef10_free_vis(struct efx_nic
*efx
)
706 MCDI_DECLARE_BUF_ERR(outbuf
);
708 int rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FREE_VIS
, NULL
, 0,
709 outbuf
, sizeof(outbuf
), &outlen
);
711 /* -EALREADY means nothing to free, so ignore */
715 efx_mcdi_display_error(efx
, MC_CMD_FREE_VIS
, 0, outbuf
, outlen
,
722 static void efx_ef10_free_piobufs(struct efx_nic
*efx
)
724 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
725 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FREE_PIOBUF_IN_LEN
);
729 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN
!= 0);
731 for (i
= 0; i
< nic_data
->n_piobufs
; i
++) {
732 MCDI_SET_DWORD(inbuf
, FREE_PIOBUF_IN_PIOBUF_HANDLE
,
733 nic_data
->piobuf_handle
[i
]);
734 rc
= efx_mcdi_rpc(efx
, MC_CMD_FREE_PIOBUF
, inbuf
, sizeof(inbuf
),
739 nic_data
->n_piobufs
= 0;
742 static int efx_ef10_alloc_piobufs(struct efx_nic
*efx
, unsigned int n
)
744 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
745 MCDI_DECLARE_BUF(outbuf
, MC_CMD_ALLOC_PIOBUF_OUT_LEN
);
750 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN
!= 0);
752 for (i
= 0; i
< n
; i
++) {
753 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_ALLOC_PIOBUF
, NULL
, 0,
754 outbuf
, sizeof(outbuf
), &outlen
);
756 /* Don't display the MC error if we didn't have space
759 if (!(efx_ef10_is_vf(efx
) && rc
== -ENOSPC
))
760 efx_mcdi_display_error(efx
, MC_CMD_ALLOC_PIOBUF
,
761 0, outbuf
, outlen
, rc
);
764 if (outlen
< MC_CMD_ALLOC_PIOBUF_OUT_LEN
) {
768 nic_data
->piobuf_handle
[i
] =
769 MCDI_DWORD(outbuf
, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE
);
770 netif_dbg(efx
, probe
, efx
->net_dev
,
771 "allocated PIO buffer %u handle %x\n", i
,
772 nic_data
->piobuf_handle
[i
]);
775 nic_data
->n_piobufs
= i
;
777 efx_ef10_free_piobufs(efx
);
781 static int efx_ef10_link_piobufs(struct efx_nic
*efx
)
783 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
784 _MCDI_DECLARE_BUF(inbuf
,
785 max(MC_CMD_LINK_PIOBUF_IN_LEN
,
786 MC_CMD_UNLINK_PIOBUF_IN_LEN
));
787 struct efx_channel
*channel
;
788 struct efx_tx_queue
*tx_queue
;
789 unsigned int offset
, index
;
792 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN
!= 0);
793 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN
!= 0);
795 memset(inbuf
, 0, sizeof(inbuf
));
797 /* Link a buffer to each VI in the write-combining mapping */
798 for (index
= 0; index
< nic_data
->n_piobufs
; ++index
) {
799 MCDI_SET_DWORD(inbuf
, LINK_PIOBUF_IN_PIOBUF_HANDLE
,
800 nic_data
->piobuf_handle
[index
]);
801 MCDI_SET_DWORD(inbuf
, LINK_PIOBUF_IN_TXQ_INSTANCE
,
802 nic_data
->pio_write_vi_base
+ index
);
803 rc
= efx_mcdi_rpc(efx
, MC_CMD_LINK_PIOBUF
,
804 inbuf
, MC_CMD_LINK_PIOBUF_IN_LEN
,
807 netif_err(efx
, drv
, efx
->net_dev
,
808 "failed to link VI %u to PIO buffer %u (%d)\n",
809 nic_data
->pio_write_vi_base
+ index
, index
,
813 netif_dbg(efx
, probe
, efx
->net_dev
,
814 "linked VI %u to PIO buffer %u\n",
815 nic_data
->pio_write_vi_base
+ index
, index
);
818 /* Link a buffer to each TX queue */
819 efx_for_each_channel(channel
, efx
) {
820 efx_for_each_channel_tx_queue(tx_queue
, channel
) {
821 /* We assign the PIO buffers to queues in
822 * reverse order to allow for the following
825 offset
= ((efx
->tx_channel_offset
+ efx
->n_tx_channels
-
826 tx_queue
->channel
->channel
- 1) *
828 index
= offset
/ ER_DZ_TX_PIOBUF_SIZE
;
829 offset
= offset
% ER_DZ_TX_PIOBUF_SIZE
;
831 /* When the host page size is 4K, the first
832 * host page in the WC mapping may be within
833 * the same VI page as the last TX queue. We
834 * can only link one buffer to each VI.
836 if (tx_queue
->queue
== nic_data
->pio_write_vi_base
) {
840 MCDI_SET_DWORD(inbuf
,
841 LINK_PIOBUF_IN_PIOBUF_HANDLE
,
842 nic_data
->piobuf_handle
[index
]);
843 MCDI_SET_DWORD(inbuf
,
844 LINK_PIOBUF_IN_TXQ_INSTANCE
,
846 rc
= efx_mcdi_rpc(efx
, MC_CMD_LINK_PIOBUF
,
847 inbuf
, MC_CMD_LINK_PIOBUF_IN_LEN
,
852 /* This is non-fatal; the TX path just
853 * won't use PIO for this queue
855 netif_err(efx
, drv
, efx
->net_dev
,
856 "failed to link VI %u to PIO buffer %u (%d)\n",
857 tx_queue
->queue
, index
, rc
);
858 tx_queue
->piobuf
= NULL
;
861 nic_data
->pio_write_base
+
862 index
* EFX_VI_PAGE_SIZE
+ offset
;
863 tx_queue
->piobuf_offset
= offset
;
864 netif_dbg(efx
, probe
, efx
->net_dev
,
865 "linked VI %u to PIO buffer %u offset %x addr %p\n",
866 tx_queue
->queue
, index
,
867 tx_queue
->piobuf_offset
,
877 MCDI_SET_DWORD(inbuf
, UNLINK_PIOBUF_IN_TXQ_INSTANCE
,
878 nic_data
->pio_write_vi_base
+ index
);
879 efx_mcdi_rpc(efx
, MC_CMD_UNLINK_PIOBUF
,
880 inbuf
, MC_CMD_UNLINK_PIOBUF_IN_LEN
,
886 static void efx_ef10_forget_old_piobufs(struct efx_nic
*efx
)
888 struct efx_channel
*channel
;
889 struct efx_tx_queue
*tx_queue
;
891 /* All our existing PIO buffers went away */
892 efx_for_each_channel(channel
, efx
)
893 efx_for_each_channel_tx_queue(tx_queue
, channel
)
894 tx_queue
->piobuf
= NULL
;
897 #else /* !EFX_USE_PIO */
899 static int efx_ef10_alloc_piobufs(struct efx_nic
*efx
, unsigned int n
)
901 return n
== 0 ? 0 : -ENOBUFS
;
904 static int efx_ef10_link_piobufs(struct efx_nic
*efx
)
909 static void efx_ef10_free_piobufs(struct efx_nic
*efx
)
913 static void efx_ef10_forget_old_piobufs(struct efx_nic
*efx
)
917 #endif /* EFX_USE_PIO */
919 static void efx_ef10_remove(struct efx_nic
*efx
)
921 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
924 #ifdef CONFIG_SFC_SRIOV
925 struct efx_ef10_nic_data
*nic_data_pf
;
926 struct pci_dev
*pci_dev_pf
;
927 struct efx_nic
*efx_pf
;
930 if (efx
->pci_dev
->is_virtfn
) {
931 pci_dev_pf
= efx
->pci_dev
->physfn
;
933 efx_pf
= pci_get_drvdata(pci_dev_pf
);
934 nic_data_pf
= efx_pf
->nic_data
;
935 vf
= nic_data_pf
->vf
+ nic_data
->vf_index
;
938 netif_info(efx
, drv
, efx
->net_dev
,
939 "Could not get the PF id from VF\n");
943 efx_ef10_cleanup_vlans(efx
);
944 mutex_destroy(&nic_data
->vlan_lock
);
948 efx_mcdi_mon_remove(efx
);
950 efx_ef10_rx_free_indir_table(efx
);
952 if (nic_data
->wc_membase
)
953 iounmap(nic_data
->wc_membase
);
955 rc
= efx_ef10_free_vis(efx
);
958 if (!nic_data
->must_restore_piobufs
)
959 efx_ef10_free_piobufs(efx
);
961 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_primary_flag
);
962 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_link_control_flag
);
965 efx_nic_free_buffer(efx
, &nic_data
->mcdi_buf
);
969 static int efx_ef10_probe_pf(struct efx_nic
*efx
)
971 return efx_ef10_probe(efx
);
974 int efx_ef10_vadaptor_query(struct efx_nic
*efx
, unsigned int port_id
,
975 u32
*port_flags
, u32
*vadaptor_flags
,
976 unsigned int *vlan_tags
)
978 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
979 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_QUERY_IN_LEN
);
980 MCDI_DECLARE_BUF(outbuf
, MC_CMD_VADAPTOR_QUERY_OUT_LEN
);
984 if (nic_data
->datapath_caps
&
985 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN
)) {
986 MCDI_SET_DWORD(inbuf
, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID
,
989 rc
= efx_mcdi_rpc(efx
, MC_CMD_VADAPTOR_QUERY
, inbuf
, sizeof(inbuf
),
990 outbuf
, sizeof(outbuf
), &outlen
);
994 if (outlen
< sizeof(outbuf
)) {
1001 *port_flags
= MCDI_DWORD(outbuf
, VADAPTOR_QUERY_OUT_PORT_FLAGS
);
1004 MCDI_DWORD(outbuf
, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS
);
1008 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS
);
1013 int efx_ef10_vadaptor_alloc(struct efx_nic
*efx
, unsigned int port_id
)
1015 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_ALLOC_IN_LEN
);
1017 MCDI_SET_DWORD(inbuf
, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID
, port_id
);
1018 return efx_mcdi_rpc(efx
, MC_CMD_VADAPTOR_ALLOC
, inbuf
, sizeof(inbuf
),
1022 int efx_ef10_vadaptor_free(struct efx_nic
*efx
, unsigned int port_id
)
1024 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_FREE_IN_LEN
);
1026 MCDI_SET_DWORD(inbuf
, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID
, port_id
);
1027 return efx_mcdi_rpc(efx
, MC_CMD_VADAPTOR_FREE
, inbuf
, sizeof(inbuf
),
1031 int efx_ef10_vport_add_mac(struct efx_nic
*efx
,
1032 unsigned int port_id
, u8
*mac
)
1034 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN
);
1036 MCDI_SET_DWORD(inbuf
, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID
, port_id
);
1037 ether_addr_copy(MCDI_PTR(inbuf
, VPORT_ADD_MAC_ADDRESS_IN_MACADDR
), mac
);
1039 return efx_mcdi_rpc(efx
, MC_CMD_VPORT_ADD_MAC_ADDRESS
, inbuf
,
1040 sizeof(inbuf
), NULL
, 0, NULL
);
1043 int efx_ef10_vport_del_mac(struct efx_nic
*efx
,
1044 unsigned int port_id
, u8
*mac
)
1046 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN
);
1048 MCDI_SET_DWORD(inbuf
, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID
, port_id
);
1049 ether_addr_copy(MCDI_PTR(inbuf
, VPORT_DEL_MAC_ADDRESS_IN_MACADDR
), mac
);
1051 return efx_mcdi_rpc(efx
, MC_CMD_VPORT_DEL_MAC_ADDRESS
, inbuf
,
1052 sizeof(inbuf
), NULL
, 0, NULL
);
1055 #ifdef CONFIG_SFC_SRIOV
1056 static int efx_ef10_probe_vf(struct efx_nic
*efx
)
1059 struct pci_dev
*pci_dev_pf
;
1061 /* If the parent PF has no VF data structure, it doesn't know about this
1062 * VF so fail probe. The VF needs to be re-created. This can happen
1063 * if the PF driver is unloaded while the VF is assigned to a guest.
1065 pci_dev_pf
= efx
->pci_dev
->physfn
;
1067 struct efx_nic
*efx_pf
= pci_get_drvdata(pci_dev_pf
);
1068 struct efx_ef10_nic_data
*nic_data_pf
= efx_pf
->nic_data
;
1070 if (!nic_data_pf
->vf
) {
1071 netif_info(efx
, drv
, efx
->net_dev
,
1072 "The VF cannot link to its parent PF; "
1073 "please destroy and re-create the VF\n");
1078 rc
= efx_ef10_probe(efx
);
1082 rc
= efx_ef10_get_vf_index(efx
);
1086 if (efx
->pci_dev
->is_virtfn
) {
1087 if (efx
->pci_dev
->physfn
) {
1088 struct efx_nic
*efx_pf
=
1089 pci_get_drvdata(efx
->pci_dev
->physfn
);
1090 struct efx_ef10_nic_data
*nic_data_p
= efx_pf
->nic_data
;
1091 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1093 nic_data_p
->vf
[nic_data
->vf_index
].efx
= efx
;
1094 nic_data_p
->vf
[nic_data
->vf_index
].pci_dev
=
1097 netif_info(efx
, drv
, efx
->net_dev
,
1098 "Could not get the PF id from VF\n");
1104 efx_ef10_remove(efx
);
1108 static int efx_ef10_probe_vf(struct efx_nic
*efx
__attribute__ ((unused
)))
1114 static int efx_ef10_alloc_vis(struct efx_nic
*efx
,
1115 unsigned int min_vis
, unsigned int max_vis
)
1117 MCDI_DECLARE_BUF(inbuf
, MC_CMD_ALLOC_VIS_IN_LEN
);
1118 MCDI_DECLARE_BUF(outbuf
, MC_CMD_ALLOC_VIS_OUT_LEN
);
1119 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1123 MCDI_SET_DWORD(inbuf
, ALLOC_VIS_IN_MIN_VI_COUNT
, min_vis
);
1124 MCDI_SET_DWORD(inbuf
, ALLOC_VIS_IN_MAX_VI_COUNT
, max_vis
);
1125 rc
= efx_mcdi_rpc(efx
, MC_CMD_ALLOC_VIS
, inbuf
, sizeof(inbuf
),
1126 outbuf
, sizeof(outbuf
), &outlen
);
1130 if (outlen
< MC_CMD_ALLOC_VIS_OUT_LEN
)
1133 netif_dbg(efx
, drv
, efx
->net_dev
, "base VI is A0x%03x\n",
1134 MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_BASE
));
1136 nic_data
->vi_base
= MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_BASE
);
1137 nic_data
->n_allocated_vis
= MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_COUNT
);
1141 /* Note that the failure path of this function does not free
1142 * resources, as this will be done by efx_ef10_remove().
1144 static int efx_ef10_dimension_resources(struct efx_nic
*efx
)
1146 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1147 unsigned int uc_mem_map_size
, wc_mem_map_size
;
1148 unsigned int min_vis
= max(EFX_TXQ_TYPES
,
1149 efx_separate_tx_channels
? 2 : 1);
1150 unsigned int channel_vis
, pio_write_vi_base
, max_vis
;
1151 void __iomem
*membase
;
1154 channel_vis
= max(efx
->n_channels
, efx
->n_tx_channels
* EFX_TXQ_TYPES
);
1157 /* Try to allocate PIO buffers if wanted and if the full
1158 * number of PIO buffers would be sufficient to allocate one
1159 * copy-buffer per TX channel. Failure is non-fatal, as there
1160 * are only a small number of PIO buffers shared between all
1161 * functions of the controller.
1163 if (efx_piobuf_size
!= 0 &&
1164 ER_DZ_TX_PIOBUF_SIZE
/ efx_piobuf_size
* EF10_TX_PIOBUF_COUNT
>=
1165 efx
->n_tx_channels
) {
1166 unsigned int n_piobufs
=
1167 DIV_ROUND_UP(efx
->n_tx_channels
,
1168 ER_DZ_TX_PIOBUF_SIZE
/ efx_piobuf_size
);
1170 rc
= efx_ef10_alloc_piobufs(efx
, n_piobufs
);
1172 netif_err(efx
, probe
, efx
->net_dev
,
1173 "failed to allocate PIO buffers (%d)\n", rc
);
1175 netif_dbg(efx
, probe
, efx
->net_dev
,
1176 "allocated %u PIO buffers\n", n_piobufs
);
1179 nic_data
->n_piobufs
= 0;
1182 /* PIO buffers should be mapped with write-combining enabled,
1183 * and we want to make single UC and WC mappings rather than
1184 * several of each (in fact that's the only option if host
1185 * page size is >4K). So we may allocate some extra VIs just
1186 * for writing PIO buffers through.
1188 * The UC mapping contains (channel_vis - 1) complete VIs and the
1189 * first half of the next VI. Then the WC mapping begins with
1190 * the second half of this last VI.
1192 uc_mem_map_size
= PAGE_ALIGN((channel_vis
- 1) * EFX_VI_PAGE_SIZE
+
1194 if (nic_data
->n_piobufs
) {
1195 /* pio_write_vi_base rounds down to give the number of complete
1196 * VIs inside the UC mapping.
1198 pio_write_vi_base
= uc_mem_map_size
/ EFX_VI_PAGE_SIZE
;
1199 wc_mem_map_size
= (PAGE_ALIGN((pio_write_vi_base
+
1200 nic_data
->n_piobufs
) *
1203 max_vis
= pio_write_vi_base
+ nic_data
->n_piobufs
;
1205 pio_write_vi_base
= 0;
1206 wc_mem_map_size
= 0;
1207 max_vis
= channel_vis
;
1210 /* In case the last attached driver failed to free VIs, do it now */
1211 rc
= efx_ef10_free_vis(efx
);
1215 rc
= efx_ef10_alloc_vis(efx
, min_vis
, max_vis
);
1219 if (nic_data
->n_allocated_vis
< channel_vis
) {
1220 netif_info(efx
, drv
, efx
->net_dev
,
1221 "Could not allocate enough VIs to satisfy RSS"
1222 " requirements. Performance may not be optimal.\n");
1223 /* We didn't get the VIs to populate our channels.
1224 * We could keep what we got but then we'd have more
1225 * interrupts than we need.
1226 * Instead calculate new max_channels and restart
1228 efx
->max_channels
= nic_data
->n_allocated_vis
;
1229 efx
->max_tx_channels
=
1230 nic_data
->n_allocated_vis
/ EFX_TXQ_TYPES
;
1232 efx_ef10_free_vis(efx
);
1236 /* If we didn't get enough VIs to map all the PIO buffers, free the
1239 if (nic_data
->n_piobufs
&&
1240 nic_data
->n_allocated_vis
<
1241 pio_write_vi_base
+ nic_data
->n_piobufs
) {
1242 netif_dbg(efx
, probe
, efx
->net_dev
,
1243 "%u VIs are not sufficient to map %u PIO buffers\n",
1244 nic_data
->n_allocated_vis
, nic_data
->n_piobufs
);
1245 efx_ef10_free_piobufs(efx
);
1248 /* Shrink the original UC mapping of the memory BAR */
1249 membase
= ioremap_nocache(efx
->membase_phys
, uc_mem_map_size
);
1251 netif_err(efx
, probe
, efx
->net_dev
,
1252 "could not shrink memory BAR to %x\n",
1256 iounmap(efx
->membase
);
1257 efx
->membase
= membase
;
1259 /* Set up the WC mapping if needed */
1260 if (wc_mem_map_size
) {
1261 nic_data
->wc_membase
= ioremap_wc(efx
->membase_phys
+
1264 if (!nic_data
->wc_membase
) {
1265 netif_err(efx
, probe
, efx
->net_dev
,
1266 "could not allocate WC mapping of size %x\n",
1270 nic_data
->pio_write_vi_base
= pio_write_vi_base
;
1271 nic_data
->pio_write_base
=
1272 nic_data
->wc_membase
+
1273 (pio_write_vi_base
* EFX_VI_PAGE_SIZE
+ ER_DZ_TX_PIOBUF
-
1276 rc
= efx_ef10_link_piobufs(efx
);
1278 efx_ef10_free_piobufs(efx
);
1281 netif_dbg(efx
, probe
, efx
->net_dev
,
1282 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1283 &efx
->membase_phys
, efx
->membase
, uc_mem_map_size
,
1284 nic_data
->wc_membase
, wc_mem_map_size
);
1289 static int efx_ef10_init_nic(struct efx_nic
*efx
)
1291 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1294 if (nic_data
->must_check_datapath_caps
) {
1295 rc
= efx_ef10_init_datapath_caps(efx
);
1298 nic_data
->must_check_datapath_caps
= false;
1301 if (nic_data
->must_realloc_vis
) {
1302 /* We cannot let the number of VIs change now */
1303 rc
= efx_ef10_alloc_vis(efx
, nic_data
->n_allocated_vis
,
1304 nic_data
->n_allocated_vis
);
1307 nic_data
->must_realloc_vis
= false;
1310 if (nic_data
->must_restore_piobufs
&& nic_data
->n_piobufs
) {
1311 rc
= efx_ef10_alloc_piobufs(efx
, nic_data
->n_piobufs
);
1313 rc
= efx_ef10_link_piobufs(efx
);
1315 efx_ef10_free_piobufs(efx
);
1318 /* Log an error on failure, but this is non-fatal */
1320 netif_err(efx
, drv
, efx
->net_dev
,
1321 "failed to restore PIO buffers (%d)\n", rc
);
1322 nic_data
->must_restore_piobufs
= false;
1325 /* don't fail init if RSS setup doesn't work */
1326 efx
->type
->rx_push_rss_config(efx
, false, efx
->rx_indir_table
);
1331 static void efx_ef10_reset_mc_allocations(struct efx_nic
*efx
)
1333 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1334 #ifdef CONFIG_SFC_SRIOV
1338 /* All our allocations have been reset */
1339 nic_data
->must_realloc_vis
= true;
1340 nic_data
->must_restore_filters
= true;
1341 nic_data
->must_restore_piobufs
= true;
1342 efx_ef10_forget_old_piobufs(efx
);
1343 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
1345 /* Driver-created vswitches and vports must be re-created */
1346 nic_data
->must_probe_vswitching
= true;
1347 nic_data
->vport_id
= EVB_PORT_ID_ASSIGNED
;
1348 #ifdef CONFIG_SFC_SRIOV
1350 for (i
= 0; i
< efx
->vf_count
; i
++)
1351 nic_data
->vf
[i
].vport_id
= 0;
1355 static enum reset_type
efx_ef10_map_reset_reason(enum reset_type reason
)
1357 if (reason
== RESET_TYPE_MC_FAILURE
)
1358 return RESET_TYPE_DATAPATH
;
1360 return efx_mcdi_map_reset_reason(reason
);
1363 static int efx_ef10_map_reset_flags(u32
*flags
)
1366 EF10_RESET_PORT
= ((ETH_RESET_MAC
| ETH_RESET_PHY
) <<
1367 ETH_RESET_SHARED_SHIFT
),
1368 EF10_RESET_MC
= ((ETH_RESET_DMA
| ETH_RESET_FILTER
|
1369 ETH_RESET_OFFLOAD
| ETH_RESET_MAC
|
1370 ETH_RESET_PHY
| ETH_RESET_MGMT
) <<
1371 ETH_RESET_SHARED_SHIFT
)
1374 /* We assume for now that our PCI function is permitted to
1378 if ((*flags
& EF10_RESET_MC
) == EF10_RESET_MC
) {
1379 *flags
&= ~EF10_RESET_MC
;
1380 return RESET_TYPE_WORLD
;
1383 if ((*flags
& EF10_RESET_PORT
) == EF10_RESET_PORT
) {
1384 *flags
&= ~EF10_RESET_PORT
;
1385 return RESET_TYPE_ALL
;
1388 /* no invisible reset implemented */
1393 static int efx_ef10_reset(struct efx_nic
*efx
, enum reset_type reset_type
)
1395 int rc
= efx_mcdi_reset(efx
, reset_type
);
1397 /* Unprivileged functions return -EPERM, but need to return success
1398 * here so that the datapath is brought back up.
1400 if (reset_type
== RESET_TYPE_WORLD
&& rc
== -EPERM
)
1403 /* If it was a port reset, trigger reallocation of MC resources.
1404 * Note that on an MC reset nothing needs to be done now because we'll
1405 * detect the MC reset later and handle it then.
1406 * For an FLR, we never get an MC reset event, but the MC has reset all
1407 * resources assigned to us, so we have to trigger reallocation now.
1409 if ((reset_type
== RESET_TYPE_ALL
||
1410 reset_type
== RESET_TYPE_MCDI_TIMEOUT
) && !rc
)
1411 efx_ef10_reset_mc_allocations(efx
);
1415 #define EF10_DMA_STAT(ext_name, mcdi_name) \
1416 [EF10_STAT_ ## ext_name] = \
1417 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1418 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1419 [EF10_STAT_ ## int_name] = \
1420 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1421 #define EF10_OTHER_STAT(ext_name) \
1422 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1423 #define GENERIC_SW_STAT(ext_name) \
1424 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1426 static const struct efx_hw_stat_desc efx_ef10_stat_desc
[EF10_STAT_COUNT
] = {
1427 EF10_DMA_STAT(port_tx_bytes
, TX_BYTES
),
1428 EF10_DMA_STAT(port_tx_packets
, TX_PKTS
),
1429 EF10_DMA_STAT(port_tx_pause
, TX_PAUSE_PKTS
),
1430 EF10_DMA_STAT(port_tx_control
, TX_CONTROL_PKTS
),
1431 EF10_DMA_STAT(port_tx_unicast
, TX_UNICAST_PKTS
),
1432 EF10_DMA_STAT(port_tx_multicast
, TX_MULTICAST_PKTS
),
1433 EF10_DMA_STAT(port_tx_broadcast
, TX_BROADCAST_PKTS
),
1434 EF10_DMA_STAT(port_tx_lt64
, TX_LT64_PKTS
),
1435 EF10_DMA_STAT(port_tx_64
, TX_64_PKTS
),
1436 EF10_DMA_STAT(port_tx_65_to_127
, TX_65_TO_127_PKTS
),
1437 EF10_DMA_STAT(port_tx_128_to_255
, TX_128_TO_255_PKTS
),
1438 EF10_DMA_STAT(port_tx_256_to_511
, TX_256_TO_511_PKTS
),
1439 EF10_DMA_STAT(port_tx_512_to_1023
, TX_512_TO_1023_PKTS
),
1440 EF10_DMA_STAT(port_tx_1024_to_15xx
, TX_1024_TO_15XX_PKTS
),
1441 EF10_DMA_STAT(port_tx_15xx_to_jumbo
, TX_15XX_TO_JUMBO_PKTS
),
1442 EF10_DMA_STAT(port_rx_bytes
, RX_BYTES
),
1443 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes
, RX_BAD_BYTES
),
1444 EF10_OTHER_STAT(port_rx_good_bytes
),
1445 EF10_OTHER_STAT(port_rx_bad_bytes
),
1446 EF10_DMA_STAT(port_rx_packets
, RX_PKTS
),
1447 EF10_DMA_STAT(port_rx_good
, RX_GOOD_PKTS
),
1448 EF10_DMA_STAT(port_rx_bad
, RX_BAD_FCS_PKTS
),
1449 EF10_DMA_STAT(port_rx_pause
, RX_PAUSE_PKTS
),
1450 EF10_DMA_STAT(port_rx_control
, RX_CONTROL_PKTS
),
1451 EF10_DMA_STAT(port_rx_unicast
, RX_UNICAST_PKTS
),
1452 EF10_DMA_STAT(port_rx_multicast
, RX_MULTICAST_PKTS
),
1453 EF10_DMA_STAT(port_rx_broadcast
, RX_BROADCAST_PKTS
),
1454 EF10_DMA_STAT(port_rx_lt64
, RX_UNDERSIZE_PKTS
),
1455 EF10_DMA_STAT(port_rx_64
, RX_64_PKTS
),
1456 EF10_DMA_STAT(port_rx_65_to_127
, RX_65_TO_127_PKTS
),
1457 EF10_DMA_STAT(port_rx_128_to_255
, RX_128_TO_255_PKTS
),
1458 EF10_DMA_STAT(port_rx_256_to_511
, RX_256_TO_511_PKTS
),
1459 EF10_DMA_STAT(port_rx_512_to_1023
, RX_512_TO_1023_PKTS
),
1460 EF10_DMA_STAT(port_rx_1024_to_15xx
, RX_1024_TO_15XX_PKTS
),
1461 EF10_DMA_STAT(port_rx_15xx_to_jumbo
, RX_15XX_TO_JUMBO_PKTS
),
1462 EF10_DMA_STAT(port_rx_gtjumbo
, RX_GTJUMBO_PKTS
),
1463 EF10_DMA_STAT(port_rx_bad_gtjumbo
, RX_JABBER_PKTS
),
1464 EF10_DMA_STAT(port_rx_overflow
, RX_OVERFLOW_PKTS
),
1465 EF10_DMA_STAT(port_rx_align_error
, RX_ALIGN_ERROR_PKTS
),
1466 EF10_DMA_STAT(port_rx_length_error
, RX_LENGTH_ERROR_PKTS
),
1467 EF10_DMA_STAT(port_rx_nodesc_drops
, RX_NODESC_DROPS
),
1468 GENERIC_SW_STAT(rx_nodesc_trunc
),
1469 GENERIC_SW_STAT(rx_noskb_drops
),
1470 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow
, PM_TRUNC_BB_OVERFLOW
),
1471 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow
, PM_DISCARD_BB_OVERFLOW
),
1472 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full
, PM_TRUNC_VFIFO_FULL
),
1473 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full
, PM_DISCARD_VFIFO_FULL
),
1474 EF10_DMA_STAT(port_rx_pm_trunc_qbb
, PM_TRUNC_QBB
),
1475 EF10_DMA_STAT(port_rx_pm_discard_qbb
, PM_DISCARD_QBB
),
1476 EF10_DMA_STAT(port_rx_pm_discard_mapping
, PM_DISCARD_MAPPING
),
1477 EF10_DMA_STAT(port_rx_dp_q_disabled_packets
, RXDP_Q_DISABLED_PKTS
),
1478 EF10_DMA_STAT(port_rx_dp_di_dropped_packets
, RXDP_DI_DROPPED_PKTS
),
1479 EF10_DMA_STAT(port_rx_dp_streaming_packets
, RXDP_STREAMING_PKTS
),
1480 EF10_DMA_STAT(port_rx_dp_hlb_fetch
, RXDP_HLB_FETCH_CONDITIONS
),
1481 EF10_DMA_STAT(port_rx_dp_hlb_wait
, RXDP_HLB_WAIT_CONDITIONS
),
1482 EF10_DMA_STAT(rx_unicast
, VADAPTER_RX_UNICAST_PACKETS
),
1483 EF10_DMA_STAT(rx_unicast_bytes
, VADAPTER_RX_UNICAST_BYTES
),
1484 EF10_DMA_STAT(rx_multicast
, VADAPTER_RX_MULTICAST_PACKETS
),
1485 EF10_DMA_STAT(rx_multicast_bytes
, VADAPTER_RX_MULTICAST_BYTES
),
1486 EF10_DMA_STAT(rx_broadcast
, VADAPTER_RX_BROADCAST_PACKETS
),
1487 EF10_DMA_STAT(rx_broadcast_bytes
, VADAPTER_RX_BROADCAST_BYTES
),
1488 EF10_DMA_STAT(rx_bad
, VADAPTER_RX_BAD_PACKETS
),
1489 EF10_DMA_STAT(rx_bad_bytes
, VADAPTER_RX_BAD_BYTES
),
1490 EF10_DMA_STAT(rx_overflow
, VADAPTER_RX_OVERFLOW
),
1491 EF10_DMA_STAT(tx_unicast
, VADAPTER_TX_UNICAST_PACKETS
),
1492 EF10_DMA_STAT(tx_unicast_bytes
, VADAPTER_TX_UNICAST_BYTES
),
1493 EF10_DMA_STAT(tx_multicast
, VADAPTER_TX_MULTICAST_PACKETS
),
1494 EF10_DMA_STAT(tx_multicast_bytes
, VADAPTER_TX_MULTICAST_BYTES
),
1495 EF10_DMA_STAT(tx_broadcast
, VADAPTER_TX_BROADCAST_PACKETS
),
1496 EF10_DMA_STAT(tx_broadcast_bytes
, VADAPTER_TX_BROADCAST_BYTES
),
1497 EF10_DMA_STAT(tx_bad
, VADAPTER_TX_BAD_PACKETS
),
1498 EF10_DMA_STAT(tx_bad_bytes
, VADAPTER_TX_BAD_BYTES
),
1499 EF10_DMA_STAT(tx_overflow
, VADAPTER_TX_OVERFLOW
),
1502 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1503 (1ULL << EF10_STAT_port_tx_packets) | \
1504 (1ULL << EF10_STAT_port_tx_pause) | \
1505 (1ULL << EF10_STAT_port_tx_unicast) | \
1506 (1ULL << EF10_STAT_port_tx_multicast) | \
1507 (1ULL << EF10_STAT_port_tx_broadcast) | \
1508 (1ULL << EF10_STAT_port_rx_bytes) | \
1510 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1511 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1512 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1513 (1ULL << EF10_STAT_port_rx_packets) | \
1514 (1ULL << EF10_STAT_port_rx_good) | \
1515 (1ULL << EF10_STAT_port_rx_bad) | \
1516 (1ULL << EF10_STAT_port_rx_pause) | \
1517 (1ULL << EF10_STAT_port_rx_control) | \
1518 (1ULL << EF10_STAT_port_rx_unicast) | \
1519 (1ULL << EF10_STAT_port_rx_multicast) | \
1520 (1ULL << EF10_STAT_port_rx_broadcast) | \
1521 (1ULL << EF10_STAT_port_rx_lt64) | \
1522 (1ULL << EF10_STAT_port_rx_64) | \
1523 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1524 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1525 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1526 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1527 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1528 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1529 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1530 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1531 (1ULL << EF10_STAT_port_rx_overflow) | \
1532 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1533 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1534 (1ULL << GENERIC_STAT_rx_noskb_drops))
1536 /* On 7000 series NICs, these statistics are only provided by the 10G MAC.
1537 * For a 10G/40G switchable port we do not expose these because they might
1538 * not include all the packets they should.
1539 * On 8000 series NICs these statistics are always provided.
1541 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1542 (1ULL << EF10_STAT_port_tx_lt64) | \
1543 (1ULL << EF10_STAT_port_tx_64) | \
1544 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1545 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1546 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1547 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1548 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1549 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1551 /* These statistics are only provided by the 40G MAC. For a 10G/40G
1552 * switchable port we do expose these because the errors will otherwise
1555 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1556 (1ULL << EF10_STAT_port_rx_length_error))
1558 /* These statistics are only provided if the firmware supports the
1559 * capability PM_AND_RXDP_COUNTERS.
1561 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
1562 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1563 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1564 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1565 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1566 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1567 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1568 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1569 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1570 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1571 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1572 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1573 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1575 static u64
efx_ef10_raw_stat_mask(struct efx_nic
*efx
)
1577 u64 raw_mask
= HUNT_COMMON_STAT_MASK
;
1578 u32 port_caps
= efx_mcdi_phy_get_caps(efx
);
1579 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1581 if (!(efx
->mcdi
->fn_flags
&
1582 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL
))
1585 if (port_caps
& (1 << MC_CMD_PHY_CAP_40000FDX_LBN
)) {
1586 raw_mask
|= HUNT_40G_EXTRA_STAT_MASK
;
1587 /* 8000 series have everything even at 40G */
1588 if (nic_data
->datapath_caps2
&
1589 (1 << MC_CMD_GET_CAPABILITIES_V2_OUT_MAC_STATS_40G_TX_SIZE_BINS_LBN
))
1590 raw_mask
|= HUNT_10G_ONLY_STAT_MASK
;
1592 raw_mask
|= HUNT_10G_ONLY_STAT_MASK
;
1595 if (nic_data
->datapath_caps
&
1596 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN
))
1597 raw_mask
|= HUNT_PM_AND_RXDP_STAT_MASK
;
1602 static void efx_ef10_get_stat_mask(struct efx_nic
*efx
, unsigned long *mask
)
1604 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1607 raw_mask
[0] = efx_ef10_raw_stat_mask(efx
);
1609 /* Only show vadaptor stats when EVB capability is present */
1610 if (nic_data
->datapath_caps
&
1611 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN
)) {
1612 raw_mask
[0] |= ~((1ULL << EF10_STAT_rx_unicast
) - 1);
1613 raw_mask
[1] = (1ULL << (EF10_STAT_COUNT
- 63)) - 1;
1618 #if BITS_PER_LONG == 64
1619 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT
) != 2);
1620 mask
[0] = raw_mask
[0];
1621 mask
[1] = raw_mask
[1];
1623 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT
) != 3);
1624 mask
[0] = raw_mask
[0] & 0xffffffff;
1625 mask
[1] = raw_mask
[0] >> 32;
1626 mask
[2] = raw_mask
[1] & 0xffffffff;
1630 static size_t efx_ef10_describe_stats(struct efx_nic
*efx
, u8
*names
)
1632 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1634 efx_ef10_get_stat_mask(efx
, mask
);
1635 return efx_nic_describe_stats(efx_ef10_stat_desc
, EF10_STAT_COUNT
,
1639 static size_t efx_ef10_update_stats_common(struct efx_nic
*efx
, u64
*full_stats
,
1640 struct rtnl_link_stats64
*core_stats
)
1642 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1643 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1644 u64
*stats
= nic_data
->stats
;
1645 size_t stats_count
= 0, index
;
1647 efx_ef10_get_stat_mask(efx
, mask
);
1650 for_each_set_bit(index
, mask
, EF10_STAT_COUNT
) {
1651 if (efx_ef10_stat_desc
[index
].name
) {
1652 *full_stats
++ = stats
[index
];
1661 if (nic_data
->datapath_caps
&
1662 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN
) {
1663 /* Use vadaptor stats. */
1664 core_stats
->rx_packets
= stats
[EF10_STAT_rx_unicast
] +
1665 stats
[EF10_STAT_rx_multicast
] +
1666 stats
[EF10_STAT_rx_broadcast
];
1667 core_stats
->tx_packets
= stats
[EF10_STAT_tx_unicast
] +
1668 stats
[EF10_STAT_tx_multicast
] +
1669 stats
[EF10_STAT_tx_broadcast
];
1670 core_stats
->rx_bytes
= stats
[EF10_STAT_rx_unicast_bytes
] +
1671 stats
[EF10_STAT_rx_multicast_bytes
] +
1672 stats
[EF10_STAT_rx_broadcast_bytes
];
1673 core_stats
->tx_bytes
= stats
[EF10_STAT_tx_unicast_bytes
] +
1674 stats
[EF10_STAT_tx_multicast_bytes
] +
1675 stats
[EF10_STAT_tx_broadcast_bytes
];
1676 core_stats
->rx_dropped
= stats
[GENERIC_STAT_rx_nodesc_trunc
] +
1677 stats
[GENERIC_STAT_rx_noskb_drops
];
1678 core_stats
->multicast
= stats
[EF10_STAT_rx_multicast
];
1679 core_stats
->rx_crc_errors
= stats
[EF10_STAT_rx_bad
];
1680 core_stats
->rx_fifo_errors
= stats
[EF10_STAT_rx_overflow
];
1681 core_stats
->rx_errors
= core_stats
->rx_crc_errors
;
1682 core_stats
->tx_errors
= stats
[EF10_STAT_tx_bad
];
1684 /* Use port stats. */
1685 core_stats
->rx_packets
= stats
[EF10_STAT_port_rx_packets
];
1686 core_stats
->tx_packets
= stats
[EF10_STAT_port_tx_packets
];
1687 core_stats
->rx_bytes
= stats
[EF10_STAT_port_rx_bytes
];
1688 core_stats
->tx_bytes
= stats
[EF10_STAT_port_tx_bytes
];
1689 core_stats
->rx_dropped
= stats
[EF10_STAT_port_rx_nodesc_drops
] +
1690 stats
[GENERIC_STAT_rx_nodesc_trunc
] +
1691 stats
[GENERIC_STAT_rx_noskb_drops
];
1692 core_stats
->multicast
= stats
[EF10_STAT_port_rx_multicast
];
1693 core_stats
->rx_length_errors
=
1694 stats
[EF10_STAT_port_rx_gtjumbo
] +
1695 stats
[EF10_STAT_port_rx_length_error
];
1696 core_stats
->rx_crc_errors
= stats
[EF10_STAT_port_rx_bad
];
1697 core_stats
->rx_frame_errors
=
1698 stats
[EF10_STAT_port_rx_align_error
];
1699 core_stats
->rx_fifo_errors
= stats
[EF10_STAT_port_rx_overflow
];
1700 core_stats
->rx_errors
= (core_stats
->rx_length_errors
+
1701 core_stats
->rx_crc_errors
+
1702 core_stats
->rx_frame_errors
);
1708 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic
*efx
)
1710 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1711 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1712 __le64 generation_start
, generation_end
;
1713 u64
*stats
= nic_data
->stats
;
1716 efx_ef10_get_stat_mask(efx
, mask
);
1718 dma_stats
= efx
->stats_buffer
.addr
;
1720 generation_end
= dma_stats
[MC_CMD_MAC_GENERATION_END
];
1721 if (generation_end
== EFX_MC_STATS_GENERATION_INVALID
)
1724 efx_nic_update_stats(efx_ef10_stat_desc
, EF10_STAT_COUNT
, mask
,
1725 stats
, efx
->stats_buffer
.addr
, false);
1727 generation_start
= dma_stats
[MC_CMD_MAC_GENERATION_START
];
1728 if (generation_end
!= generation_start
)
1731 /* Update derived statistics */
1732 efx_nic_fix_nodesc_drop_stat(efx
,
1733 &stats
[EF10_STAT_port_rx_nodesc_drops
]);
1734 stats
[EF10_STAT_port_rx_good_bytes
] =
1735 stats
[EF10_STAT_port_rx_bytes
] -
1736 stats
[EF10_STAT_port_rx_bytes_minus_good_bytes
];
1737 efx_update_diff_stat(&stats
[EF10_STAT_port_rx_bad_bytes
],
1738 stats
[EF10_STAT_port_rx_bytes_minus_good_bytes
]);
1739 efx_update_sw_stats(efx
, stats
);
1744 static size_t efx_ef10_update_stats_pf(struct efx_nic
*efx
, u64
*full_stats
,
1745 struct rtnl_link_stats64
*core_stats
)
1749 /* If we're unlucky enough to read statistics during the DMA, wait
1750 * up to 10ms for it to finish (typically takes <500us)
1752 for (retry
= 0; retry
< 100; ++retry
) {
1753 if (efx_ef10_try_update_nic_stats_pf(efx
) == 0)
1758 return efx_ef10_update_stats_common(efx
, full_stats
, core_stats
);
1761 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic
*efx
)
1763 MCDI_DECLARE_BUF(inbuf
, MC_CMD_MAC_STATS_IN_LEN
);
1764 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1765 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1766 __le64 generation_start
, generation_end
;
1767 u64
*stats
= nic_data
->stats
;
1768 u32 dma_len
= MC_CMD_MAC_NSTATS
* sizeof(u64
);
1769 struct efx_buffer stats_buf
;
1773 spin_unlock_bh(&efx
->stats_lock
);
1775 if (in_interrupt()) {
1776 /* If in atomic context, cannot update stats. Just update the
1777 * software stats and return so the caller can continue.
1779 spin_lock_bh(&efx
->stats_lock
);
1780 efx_update_sw_stats(efx
, stats
);
1784 efx_ef10_get_stat_mask(efx
, mask
);
1786 rc
= efx_nic_alloc_buffer(efx
, &stats_buf
, dma_len
, GFP_ATOMIC
);
1788 spin_lock_bh(&efx
->stats_lock
);
1792 dma_stats
= stats_buf
.addr
;
1793 dma_stats
[MC_CMD_MAC_GENERATION_END
] = EFX_MC_STATS_GENERATION_INVALID
;
1795 MCDI_SET_QWORD(inbuf
, MAC_STATS_IN_DMA_ADDR
, stats_buf
.dma_addr
);
1796 MCDI_POPULATE_DWORD_1(inbuf
, MAC_STATS_IN_CMD
,
1797 MAC_STATS_IN_DMA
, 1);
1798 MCDI_SET_DWORD(inbuf
, MAC_STATS_IN_DMA_LEN
, dma_len
);
1799 MCDI_SET_DWORD(inbuf
, MAC_STATS_IN_PORT_ID
, EVB_PORT_ID_ASSIGNED
);
1801 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_MAC_STATS
, inbuf
, sizeof(inbuf
),
1803 spin_lock_bh(&efx
->stats_lock
);
1805 /* Expect ENOENT if DMA queues have not been set up */
1806 if (rc
!= -ENOENT
|| atomic_read(&efx
->active_queues
))
1807 efx_mcdi_display_error(efx
, MC_CMD_MAC_STATS
,
1808 sizeof(inbuf
), NULL
, 0, rc
);
1812 generation_end
= dma_stats
[MC_CMD_MAC_GENERATION_END
];
1813 if (generation_end
== EFX_MC_STATS_GENERATION_INVALID
) {
1818 efx_nic_update_stats(efx_ef10_stat_desc
, EF10_STAT_COUNT
, mask
,
1819 stats
, stats_buf
.addr
, false);
1821 generation_start
= dma_stats
[MC_CMD_MAC_GENERATION_START
];
1822 if (generation_end
!= generation_start
) {
1827 efx_update_sw_stats(efx
, stats
);
1829 efx_nic_free_buffer(efx
, &stats_buf
);
1833 static size_t efx_ef10_update_stats_vf(struct efx_nic
*efx
, u64
*full_stats
,
1834 struct rtnl_link_stats64
*core_stats
)
1836 if (efx_ef10_try_update_nic_stats_vf(efx
))
1839 return efx_ef10_update_stats_common(efx
, full_stats
, core_stats
);
1842 static void efx_ef10_push_irq_moderation(struct efx_channel
*channel
)
1844 struct efx_nic
*efx
= channel
->efx
;
1845 unsigned int mode
, usecs
;
1846 efx_dword_t timer_cmd
;
1848 if (channel
->irq_moderation_us
) {
1850 usecs
= channel
->irq_moderation_us
;
1856 if (EFX_EF10_WORKAROUND_61265(efx
)) {
1857 MCDI_DECLARE_BUF(inbuf
, MC_CMD_SET_EVQ_TMR_IN_LEN
);
1858 unsigned int ns
= usecs
* 1000;
1860 MCDI_SET_DWORD(inbuf
, SET_EVQ_TMR_IN_INSTANCE
,
1862 MCDI_SET_DWORD(inbuf
, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS
, ns
);
1863 MCDI_SET_DWORD(inbuf
, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS
, ns
);
1864 MCDI_SET_DWORD(inbuf
, SET_EVQ_TMR_IN_TMR_MODE
, mode
);
1866 efx_mcdi_rpc_async(efx
, MC_CMD_SET_EVQ_TMR
,
1867 inbuf
, sizeof(inbuf
), 0, NULL
, 0);
1868 } else if (EFX_EF10_WORKAROUND_35388(efx
)) {
1869 unsigned int ticks
= efx_usecs_to_ticks(efx
, usecs
);
1871 EFX_POPULATE_DWORD_3(timer_cmd
, ERF_DD_EVQ_IND_TIMER_FLAGS
,
1872 EFE_DD_EVQ_IND_TIMER_FLAGS
,
1873 ERF_DD_EVQ_IND_TIMER_MODE
, mode
,
1874 ERF_DD_EVQ_IND_TIMER_VAL
, ticks
);
1875 efx_writed_page(efx
, &timer_cmd
, ER_DD_EVQ_INDIRECT
,
1878 unsigned int ticks
= efx_usecs_to_ticks(efx
, usecs
);
1880 EFX_POPULATE_DWORD_2(timer_cmd
, ERF_DZ_TC_TIMER_MODE
, mode
,
1881 ERF_DZ_TC_TIMER_VAL
, ticks
);
1882 efx_writed_page(efx
, &timer_cmd
, ER_DZ_EVQ_TMR
,
1887 static void efx_ef10_get_wol_vf(struct efx_nic
*efx
,
1888 struct ethtool_wolinfo
*wol
) {}
1890 static int efx_ef10_set_wol_vf(struct efx_nic
*efx
, u32 type
)
1895 static void efx_ef10_get_wol(struct efx_nic
*efx
, struct ethtool_wolinfo
*wol
)
1899 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
1902 static int efx_ef10_set_wol(struct efx_nic
*efx
, u32 type
)
1909 static void efx_ef10_mcdi_request(struct efx_nic
*efx
,
1910 const efx_dword_t
*hdr
, size_t hdr_len
,
1911 const efx_dword_t
*sdu
, size_t sdu_len
)
1913 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1914 u8
*pdu
= nic_data
->mcdi_buf
.addr
;
1916 memcpy(pdu
, hdr
, hdr_len
);
1917 memcpy(pdu
+ hdr_len
, sdu
, sdu_len
);
1920 /* The hardware provides 'low' and 'high' (doorbell) registers
1921 * for passing the 64-bit address of an MCDI request to
1922 * firmware. However the dwords are swapped by firmware. The
1923 * least significant bits of the doorbell are then 0 for all
1924 * MCDI requests due to alignment.
1926 _efx_writed(efx
, cpu_to_le32((u64
)nic_data
->mcdi_buf
.dma_addr
>> 32),
1928 _efx_writed(efx
, cpu_to_le32((u32
)nic_data
->mcdi_buf
.dma_addr
),
1932 static bool efx_ef10_mcdi_poll_response(struct efx_nic
*efx
)
1934 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1935 const efx_dword_t hdr
= *(const efx_dword_t
*)nic_data
->mcdi_buf
.addr
;
1938 return EFX_DWORD_FIELD(hdr
, MCDI_HEADER_RESPONSE
);
1942 efx_ef10_mcdi_read_response(struct efx_nic
*efx
, efx_dword_t
*outbuf
,
1943 size_t offset
, size_t outlen
)
1945 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1946 const u8
*pdu
= nic_data
->mcdi_buf
.addr
;
1948 memcpy(outbuf
, pdu
+ offset
, outlen
);
1951 static void efx_ef10_mcdi_reboot_detected(struct efx_nic
*efx
)
1953 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1955 /* All our allocations have been reset */
1956 efx_ef10_reset_mc_allocations(efx
);
1958 /* The datapath firmware might have been changed */
1959 nic_data
->must_check_datapath_caps
= true;
1961 /* MAC statistics have been cleared on the NIC; clear the local
1962 * statistic that we update with efx_update_diff_stat().
1964 nic_data
->stats
[EF10_STAT_port_rx_bad_bytes
] = 0;
1967 static int efx_ef10_mcdi_poll_reboot(struct efx_nic
*efx
)
1969 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1972 rc
= efx_ef10_get_warm_boot_count(efx
);
1974 /* The firmware is presumably in the process of
1975 * rebooting. However, we are supposed to report each
1976 * reboot just once, so we must only do that once we
1977 * can read and store the updated warm boot count.
1982 if (rc
== nic_data
->warm_boot_count
)
1985 nic_data
->warm_boot_count
= rc
;
1986 efx_ef10_mcdi_reboot_detected(efx
);
1991 /* Handle an MSI interrupt
1993 * Handle an MSI hardware interrupt. This routine schedules event
1994 * queue processing. No interrupt acknowledgement cycle is necessary.
1995 * Also, we never need to check that the interrupt is for us, since
1996 * MSI interrupts cannot be shared.
1998 static irqreturn_t
efx_ef10_msi_interrupt(int irq
, void *dev_id
)
2000 struct efx_msi_context
*context
= dev_id
;
2001 struct efx_nic
*efx
= context
->efx
;
2003 netif_vdbg(efx
, intr
, efx
->net_dev
,
2004 "IRQ %d on CPU %d\n", irq
, raw_smp_processor_id());
2006 if (likely(ACCESS_ONCE(efx
->irq_soft_enabled
))) {
2007 /* Note test interrupts */
2008 if (context
->index
== efx
->irq_level
)
2009 efx
->last_irq_cpu
= raw_smp_processor_id();
2011 /* Schedule processing of the channel */
2012 efx_schedule_channel_irq(efx
->channel
[context
->index
]);
2018 static irqreturn_t
efx_ef10_legacy_interrupt(int irq
, void *dev_id
)
2020 struct efx_nic
*efx
= dev_id
;
2021 bool soft_enabled
= ACCESS_ONCE(efx
->irq_soft_enabled
);
2022 struct efx_channel
*channel
;
2026 /* Read the ISR which also ACKs the interrupts */
2027 efx_readd(efx
, ®
, ER_DZ_BIU_INT_ISR
);
2028 queues
= EFX_DWORD_FIELD(reg
, ERF_DZ_ISR_REG
);
2033 if (likely(soft_enabled
)) {
2034 /* Note test interrupts */
2035 if (queues
& (1U << efx
->irq_level
))
2036 efx
->last_irq_cpu
= raw_smp_processor_id();
2038 efx_for_each_channel(channel
, efx
) {
2040 efx_schedule_channel_irq(channel
);
2045 netif_vdbg(efx
, intr
, efx
->net_dev
,
2046 "IRQ %d on CPU %d status " EFX_DWORD_FMT
"\n",
2047 irq
, raw_smp_processor_id(), EFX_DWORD_VAL(reg
));
2052 static int efx_ef10_irq_test_generate(struct efx_nic
*efx
)
2054 MCDI_DECLARE_BUF(inbuf
, MC_CMD_TRIGGER_INTERRUPT_IN_LEN
);
2056 if (efx_mcdi_set_workaround(efx
, MC_CMD_WORKAROUND_BUG41750
, true,
2060 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN
!= 0);
2062 MCDI_SET_DWORD(inbuf
, TRIGGER_INTERRUPT_IN_INTR_LEVEL
, efx
->irq_level
);
2063 return efx_mcdi_rpc(efx
, MC_CMD_TRIGGER_INTERRUPT
,
2064 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
2067 static int efx_ef10_tx_probe(struct efx_tx_queue
*tx_queue
)
2069 return efx_nic_alloc_buffer(tx_queue
->efx
, &tx_queue
->txd
.buf
,
2070 (tx_queue
->ptr_mask
+ 1) *
2071 sizeof(efx_qword_t
),
2075 /* This writes to the TX_DESC_WPTR and also pushes data */
2076 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue
*tx_queue
,
2077 const efx_qword_t
*txd
)
2079 unsigned int write_ptr
;
2082 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
2083 EFX_POPULATE_OWORD_1(reg
, ERF_DZ_TX_DESC_WPTR
, write_ptr
);
2084 reg
.qword
[0] = *txd
;
2085 efx_writeo_page(tx_queue
->efx
, ®
,
2086 ER_DZ_TX_DESC_UPD
, tx_queue
->queue
);
2089 static void efx_ef10_tx_init(struct efx_tx_queue
*tx_queue
)
2091 MCDI_DECLARE_BUF(inbuf
, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE
* 8 /
2093 bool csum_offload
= tx_queue
->queue
& EFX_TXQ_TYPE_OFFLOAD
;
2094 size_t entries
= tx_queue
->txd
.buf
.len
/ EFX_BUF_SIZE
;
2095 struct efx_channel
*channel
= tx_queue
->channel
;
2096 struct efx_nic
*efx
= tx_queue
->efx
;
2097 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2099 dma_addr_t dma_addr
;
2103 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN
!= 0);
2105 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_SIZE
, tx_queue
->ptr_mask
+ 1);
2106 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_TARGET_EVQ
, channel
->channel
);
2107 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_LABEL
, tx_queue
->queue
);
2108 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_INSTANCE
, tx_queue
->queue
);
2109 MCDI_POPULATE_DWORD_2(inbuf
, INIT_TXQ_IN_FLAGS
,
2110 INIT_TXQ_IN_FLAG_IP_CSUM_DIS
, !csum_offload
,
2111 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS
, !csum_offload
);
2112 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_OWNER_ID
, 0);
2113 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_PORT_ID
, nic_data
->vport_id
);
2115 dma_addr
= tx_queue
->txd
.buf
.dma_addr
;
2117 netif_dbg(efx
, hw
, efx
->net_dev
, "pushing TXQ %d. %zu entries (%llx)\n",
2118 tx_queue
->queue
, entries
, (u64
)dma_addr
);
2120 for (i
= 0; i
< entries
; ++i
) {
2121 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_TXQ_IN_DMA_ADDR
, i
, dma_addr
);
2122 dma_addr
+= EFX_BUF_SIZE
;
2125 inlen
= MC_CMD_INIT_TXQ_IN_LEN(entries
);
2127 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_TXQ
, inbuf
, inlen
,
2132 /* A previous user of this TX queue might have set us up the
2133 * bomb by writing a descriptor to the TX push collector but
2134 * not the doorbell. (Each collector belongs to a port, not a
2135 * queue or function, so cannot easily be reset.) We must
2136 * attempt to push a no-op descriptor in its place.
2138 tx_queue
->buffer
[0].flags
= EFX_TX_BUF_OPTION
;
2139 tx_queue
->insert_count
= 1;
2140 txd
= efx_tx_desc(tx_queue
, 0);
2141 EFX_POPULATE_QWORD_4(*txd
,
2142 ESF_DZ_TX_DESC_IS_OPT
, true,
2143 ESF_DZ_TX_OPTION_TYPE
,
2144 ESE_DZ_TX_OPTION_DESC_CRC_CSUM
,
2145 ESF_DZ_TX_OPTION_UDP_TCP_CSUM
, csum_offload
,
2146 ESF_DZ_TX_OPTION_IP_CSUM
, csum_offload
);
2147 tx_queue
->write_count
= 1;
2149 if (nic_data
->datapath_caps
&
2150 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN
)) {
2151 tx_queue
->tso_version
= 1;
2155 efx_ef10_push_tx_desc(tx_queue
, txd
);
2160 netdev_WARN(efx
->net_dev
, "failed to initialise TXQ %d\n",
2164 static void efx_ef10_tx_fini(struct efx_tx_queue
*tx_queue
)
2166 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_TXQ_IN_LEN
);
2167 MCDI_DECLARE_BUF_ERR(outbuf
);
2168 struct efx_nic
*efx
= tx_queue
->efx
;
2172 MCDI_SET_DWORD(inbuf
, FINI_TXQ_IN_INSTANCE
,
2175 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_TXQ
, inbuf
, sizeof(inbuf
),
2176 outbuf
, sizeof(outbuf
), &outlen
);
2178 if (rc
&& rc
!= -EALREADY
)
2184 efx_mcdi_display_error(efx
, MC_CMD_FINI_TXQ
, MC_CMD_FINI_TXQ_IN_LEN
,
2185 outbuf
, outlen
, rc
);
2188 static void efx_ef10_tx_remove(struct efx_tx_queue
*tx_queue
)
2190 efx_nic_free_buffer(tx_queue
->efx
, &tx_queue
->txd
.buf
);
2193 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2194 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue
*tx_queue
)
2196 unsigned int write_ptr
;
2199 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
2200 EFX_POPULATE_DWORD_1(reg
, ERF_DZ_TX_DESC_WPTR_DWORD
, write_ptr
);
2201 efx_writed_page(tx_queue
->efx
, ®
,
2202 ER_DZ_TX_DESC_UPD_DWORD
, tx_queue
->queue
);
2205 static void efx_ef10_tx_write(struct efx_tx_queue
*tx_queue
)
2207 unsigned int old_write_count
= tx_queue
->write_count
;
2208 struct efx_tx_buffer
*buffer
;
2209 unsigned int write_ptr
;
2212 tx_queue
->xmit_more_available
= false;
2213 if (unlikely(tx_queue
->write_count
== tx_queue
->insert_count
))
2217 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
2218 buffer
= &tx_queue
->buffer
[write_ptr
];
2219 txd
= efx_tx_desc(tx_queue
, write_ptr
);
2220 ++tx_queue
->write_count
;
2222 /* Create TX descriptor ring entry */
2223 if (buffer
->flags
& EFX_TX_BUF_OPTION
) {
2224 *txd
= buffer
->option
;
2226 BUILD_BUG_ON(EFX_TX_BUF_CONT
!= 1);
2227 EFX_POPULATE_QWORD_3(
2230 buffer
->flags
& EFX_TX_BUF_CONT
,
2231 ESF_DZ_TX_KER_BYTE_CNT
, buffer
->len
,
2232 ESF_DZ_TX_KER_BUF_ADDR
, buffer
->dma_addr
);
2234 } while (tx_queue
->write_count
!= tx_queue
->insert_count
);
2236 wmb(); /* Ensure descriptors are written before they are fetched */
2238 if (efx_nic_may_push_tx_desc(tx_queue
, old_write_count
)) {
2239 txd
= efx_tx_desc(tx_queue
,
2240 old_write_count
& tx_queue
->ptr_mask
);
2241 efx_ef10_push_tx_desc(tx_queue
, txd
);
2244 efx_ef10_notify_tx_desc(tx_queue
);
2248 static int efx_ef10_alloc_rss_context(struct efx_nic
*efx
, u32
*context
,
2249 bool exclusive
, unsigned *context_size
)
2251 MCDI_DECLARE_BUF(inbuf
, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN
);
2252 MCDI_DECLARE_BUF(outbuf
, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN
);
2253 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2256 u32 alloc_type
= exclusive
?
2257 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE
:
2258 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED
;
2259 unsigned rss_spread
= exclusive
?
2261 min(rounddown_pow_of_two(efx
->rss_spread
),
2262 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE
);
2264 if (!exclusive
&& rss_spread
== 1) {
2265 *context
= EFX_EF10_RSS_CONTEXT_INVALID
;
2271 if (nic_data
->datapath_caps
&
2272 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN
)
2275 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID
,
2276 nic_data
->vport_id
);
2277 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_TYPE
, alloc_type
);
2278 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES
, rss_spread
);
2280 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_ALLOC
, inbuf
, sizeof(inbuf
),
2281 outbuf
, sizeof(outbuf
), &outlen
);
2285 if (outlen
< MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN
)
2288 *context
= MCDI_DWORD(outbuf
, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID
);
2291 *context_size
= rss_spread
;
2296 static void efx_ef10_free_rss_context(struct efx_nic
*efx
, u32 context
)
2298 MCDI_DECLARE_BUF(inbuf
, MC_CMD_RSS_CONTEXT_FREE_IN_LEN
);
2301 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID
,
2304 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_FREE
, inbuf
, sizeof(inbuf
),
2309 static int efx_ef10_populate_rss_table(struct efx_nic
*efx
, u32 context
,
2310 const u32
*rx_indir_table
)
2312 MCDI_DECLARE_BUF(tablebuf
, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN
);
2313 MCDI_DECLARE_BUF(keybuf
, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN
);
2316 MCDI_SET_DWORD(tablebuf
, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID
,
2318 BUILD_BUG_ON(ARRAY_SIZE(efx
->rx_indir_table
) !=
2319 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN
);
2321 for (i
= 0; i
< ARRAY_SIZE(efx
->rx_indir_table
); ++i
)
2323 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE
)[i
] =
2324 (u8
) rx_indir_table
[i
];
2326 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_SET_TABLE
, tablebuf
,
2327 sizeof(tablebuf
), NULL
, 0, NULL
);
2331 MCDI_SET_DWORD(keybuf
, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID
,
2333 BUILD_BUG_ON(ARRAY_SIZE(efx
->rx_hash_key
) !=
2334 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN
);
2335 for (i
= 0; i
< ARRAY_SIZE(efx
->rx_hash_key
); ++i
)
2336 MCDI_PTR(keybuf
, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY
)[i
] =
2337 efx
->rx_hash_key
[i
];
2339 return efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_SET_KEY
, keybuf
,
2340 sizeof(keybuf
), NULL
, 0, NULL
);
2343 static void efx_ef10_rx_free_indir_table(struct efx_nic
*efx
)
2345 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2347 if (nic_data
->rx_rss_context
!= EFX_EF10_RSS_CONTEXT_INVALID
)
2348 efx_ef10_free_rss_context(efx
, nic_data
->rx_rss_context
);
2349 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
2352 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic
*efx
,
2353 unsigned *context_size
)
2355 u32 new_rx_rss_context
;
2356 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2357 int rc
= efx_ef10_alloc_rss_context(efx
, &new_rx_rss_context
,
2358 false, context_size
);
2363 nic_data
->rx_rss_context
= new_rx_rss_context
;
2364 nic_data
->rx_rss_context_exclusive
= false;
2365 efx_set_default_rx_indir_table(efx
);
2369 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic
*efx
,
2370 const u32
*rx_indir_table
)
2372 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2374 u32 new_rx_rss_context
;
2376 if (nic_data
->rx_rss_context
== EFX_EF10_RSS_CONTEXT_INVALID
||
2377 !nic_data
->rx_rss_context_exclusive
) {
2378 rc
= efx_ef10_alloc_rss_context(efx
, &new_rx_rss_context
,
2380 if (rc
== -EOPNOTSUPP
)
2385 new_rx_rss_context
= nic_data
->rx_rss_context
;
2388 rc
= efx_ef10_populate_rss_table(efx
, new_rx_rss_context
,
2393 if (nic_data
->rx_rss_context
!= new_rx_rss_context
)
2394 efx_ef10_rx_free_indir_table(efx
);
2395 nic_data
->rx_rss_context
= new_rx_rss_context
;
2396 nic_data
->rx_rss_context_exclusive
= true;
2397 if (rx_indir_table
!= efx
->rx_indir_table
)
2398 memcpy(efx
->rx_indir_table
, rx_indir_table
,
2399 sizeof(efx
->rx_indir_table
));
2403 if (new_rx_rss_context
!= nic_data
->rx_rss_context
)
2404 efx_ef10_free_rss_context(efx
, new_rx_rss_context
);
2406 netif_err(efx
, hw
, efx
->net_dev
, "%s: failed rc=%d\n", __func__
, rc
);
2410 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic
*efx
, bool user
,
2411 const u32
*rx_indir_table
)
2415 if (efx
->rss_spread
== 1)
2418 rc
= efx_ef10_rx_push_exclusive_rss_config(efx
, rx_indir_table
);
2420 if (rc
== -ENOBUFS
&& !user
) {
2421 unsigned context_size
;
2422 bool mismatch
= false;
2425 for (i
= 0; i
< ARRAY_SIZE(efx
->rx_indir_table
) && !mismatch
;
2427 mismatch
= rx_indir_table
[i
] !=
2428 ethtool_rxfh_indir_default(i
, efx
->rss_spread
);
2430 rc
= efx_ef10_rx_push_shared_rss_config(efx
, &context_size
);
2432 if (context_size
!= efx
->rss_spread
)
2433 netif_warn(efx
, probe
, efx
->net_dev
,
2434 "Could not allocate an exclusive RSS"
2435 " context; allocated a shared one of"
2437 " Wanted %u, got %u.\n",
2438 efx
->rss_spread
, context_size
);
2440 netif_warn(efx
, probe
, efx
->net_dev
,
2441 "Could not allocate an exclusive RSS"
2442 " context; allocated a shared one but"
2443 " could not apply custom"
2446 netif_info(efx
, probe
, efx
->net_dev
,
2447 "Could not allocate an exclusive RSS"
2448 " context; allocated a shared one.\n");
2454 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic
*efx
, bool user
,
2455 const u32
*rx_indir_table
2456 __attribute__ ((unused
)))
2458 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2462 if (nic_data
->rx_rss_context
!= EFX_EF10_RSS_CONTEXT_INVALID
)
2464 return efx_ef10_rx_push_shared_rss_config(efx
, NULL
);
2467 static int efx_ef10_rx_probe(struct efx_rx_queue
*rx_queue
)
2469 return efx_nic_alloc_buffer(rx_queue
->efx
, &rx_queue
->rxd
.buf
,
2470 (rx_queue
->ptr_mask
+ 1) *
2471 sizeof(efx_qword_t
),
2475 static void efx_ef10_rx_init(struct efx_rx_queue
*rx_queue
)
2477 MCDI_DECLARE_BUF(inbuf
,
2478 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE
* 8 /
2480 struct efx_channel
*channel
= efx_rx_queue_channel(rx_queue
);
2481 size_t entries
= rx_queue
->rxd
.buf
.len
/ EFX_BUF_SIZE
;
2482 struct efx_nic
*efx
= rx_queue
->efx
;
2483 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2485 dma_addr_t dma_addr
;
2488 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN
!= 0);
2490 rx_queue
->scatter_n
= 0;
2491 rx_queue
->scatter_len
= 0;
2493 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_SIZE
, rx_queue
->ptr_mask
+ 1);
2494 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_TARGET_EVQ
, channel
->channel
);
2495 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_LABEL
, efx_rx_queue_index(rx_queue
));
2496 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_INSTANCE
,
2497 efx_rx_queue_index(rx_queue
));
2498 MCDI_POPULATE_DWORD_2(inbuf
, INIT_RXQ_IN_FLAGS
,
2499 INIT_RXQ_IN_FLAG_PREFIX
, 1,
2500 INIT_RXQ_IN_FLAG_TIMESTAMP
, 1);
2501 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_OWNER_ID
, 0);
2502 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_PORT_ID
, nic_data
->vport_id
);
2504 dma_addr
= rx_queue
->rxd
.buf
.dma_addr
;
2506 netif_dbg(efx
, hw
, efx
->net_dev
, "pushing RXQ %d. %zu entries (%llx)\n",
2507 efx_rx_queue_index(rx_queue
), entries
, (u64
)dma_addr
);
2509 for (i
= 0; i
< entries
; ++i
) {
2510 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_RXQ_IN_DMA_ADDR
, i
, dma_addr
);
2511 dma_addr
+= EFX_BUF_SIZE
;
2514 inlen
= MC_CMD_INIT_RXQ_IN_LEN(entries
);
2516 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_RXQ
, inbuf
, inlen
,
2519 netdev_WARN(efx
->net_dev
, "failed to initialise RXQ %d\n",
2520 efx_rx_queue_index(rx_queue
));
2523 static void efx_ef10_rx_fini(struct efx_rx_queue
*rx_queue
)
2525 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_RXQ_IN_LEN
);
2526 MCDI_DECLARE_BUF_ERR(outbuf
);
2527 struct efx_nic
*efx
= rx_queue
->efx
;
2531 MCDI_SET_DWORD(inbuf
, FINI_RXQ_IN_INSTANCE
,
2532 efx_rx_queue_index(rx_queue
));
2534 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_RXQ
, inbuf
, sizeof(inbuf
),
2535 outbuf
, sizeof(outbuf
), &outlen
);
2537 if (rc
&& rc
!= -EALREADY
)
2543 efx_mcdi_display_error(efx
, MC_CMD_FINI_RXQ
, MC_CMD_FINI_RXQ_IN_LEN
,
2544 outbuf
, outlen
, rc
);
2547 static void efx_ef10_rx_remove(struct efx_rx_queue
*rx_queue
)
2549 efx_nic_free_buffer(rx_queue
->efx
, &rx_queue
->rxd
.buf
);
2552 /* This creates an entry in the RX descriptor queue */
2554 efx_ef10_build_rx_desc(struct efx_rx_queue
*rx_queue
, unsigned int index
)
2556 struct efx_rx_buffer
*rx_buf
;
2559 rxd
= efx_rx_desc(rx_queue
, index
);
2560 rx_buf
= efx_rx_buffer(rx_queue
, index
);
2561 EFX_POPULATE_QWORD_2(*rxd
,
2562 ESF_DZ_RX_KER_BYTE_CNT
, rx_buf
->len
,
2563 ESF_DZ_RX_KER_BUF_ADDR
, rx_buf
->dma_addr
);
2566 static void efx_ef10_rx_write(struct efx_rx_queue
*rx_queue
)
2568 struct efx_nic
*efx
= rx_queue
->efx
;
2569 unsigned int write_count
;
2572 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2573 write_count
= rx_queue
->added_count
& ~7;
2574 if (rx_queue
->notified_count
== write_count
)
2578 efx_ef10_build_rx_desc(
2580 rx_queue
->notified_count
& rx_queue
->ptr_mask
);
2581 while (++rx_queue
->notified_count
!= write_count
);
2584 EFX_POPULATE_DWORD_1(reg
, ERF_DZ_RX_DESC_WPTR
,
2585 write_count
& rx_queue
->ptr_mask
);
2586 efx_writed_page(efx
, ®
, ER_DZ_RX_DESC_UPD
,
2587 efx_rx_queue_index(rx_queue
));
2590 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete
;
2592 static void efx_ef10_rx_defer_refill(struct efx_rx_queue
*rx_queue
)
2594 struct efx_channel
*channel
= efx_rx_queue_channel(rx_queue
);
2595 MCDI_DECLARE_BUF(inbuf
, MC_CMD_DRIVER_EVENT_IN_LEN
);
2598 EFX_POPULATE_QWORD_2(event
,
2599 ESF_DZ_EV_CODE
, EFX_EF10_DRVGEN_EV
,
2600 ESF_DZ_EV_DATA
, EFX_EF10_REFILL
);
2602 MCDI_SET_DWORD(inbuf
, DRIVER_EVENT_IN_EVQ
, channel
->channel
);
2604 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2605 * already swapped the data to little-endian order.
2607 memcpy(MCDI_PTR(inbuf
, DRIVER_EVENT_IN_DATA
), &event
.u64
[0],
2608 sizeof(efx_qword_t
));
2610 efx_mcdi_rpc_async(channel
->efx
, MC_CMD_DRIVER_EVENT
,
2611 inbuf
, sizeof(inbuf
), 0,
2612 efx_ef10_rx_defer_refill_complete
, 0);
2616 efx_ef10_rx_defer_refill_complete(struct efx_nic
*efx
, unsigned long cookie
,
2617 int rc
, efx_dword_t
*outbuf
,
2618 size_t outlen_actual
)
2623 static int efx_ef10_ev_probe(struct efx_channel
*channel
)
2625 return efx_nic_alloc_buffer(channel
->efx
, &channel
->eventq
.buf
,
2626 (channel
->eventq_mask
+ 1) *
2627 sizeof(efx_qword_t
),
2631 static void efx_ef10_ev_fini(struct efx_channel
*channel
)
2633 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_EVQ_IN_LEN
);
2634 MCDI_DECLARE_BUF_ERR(outbuf
);
2635 struct efx_nic
*efx
= channel
->efx
;
2639 MCDI_SET_DWORD(inbuf
, FINI_EVQ_IN_INSTANCE
, channel
->channel
);
2641 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_EVQ
, inbuf
, sizeof(inbuf
),
2642 outbuf
, sizeof(outbuf
), &outlen
);
2644 if (rc
&& rc
!= -EALREADY
)
2650 efx_mcdi_display_error(efx
, MC_CMD_FINI_EVQ
, MC_CMD_FINI_EVQ_IN_LEN
,
2651 outbuf
, outlen
, rc
);
2654 static int efx_ef10_ev_init(struct efx_channel
*channel
)
2656 MCDI_DECLARE_BUF(inbuf
,
2657 MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_MAX_EVQ_SIZE
* 8 /
2659 MCDI_DECLARE_BUF(outbuf
, MC_CMD_INIT_EVQ_V2_OUT_LEN
);
2660 size_t entries
= channel
->eventq
.buf
.len
/ EFX_BUF_SIZE
;
2661 struct efx_nic
*efx
= channel
->efx
;
2662 struct efx_ef10_nic_data
*nic_data
;
2663 size_t inlen
, outlen
;
2664 unsigned int enabled
, implemented
;
2665 dma_addr_t dma_addr
;
2669 nic_data
= efx
->nic_data
;
2671 /* Fill event queue with all ones (i.e. empty events) */
2672 memset(channel
->eventq
.buf
.addr
, 0xff, channel
->eventq
.buf
.len
);
2674 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_SIZE
, channel
->eventq_mask
+ 1);
2675 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_INSTANCE
, channel
->channel
);
2676 /* INIT_EVQ expects index in vector table, not absolute */
2677 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_IRQ_NUM
, channel
->channel
);
2678 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_MODE
,
2679 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS
);
2680 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_LOAD
, 0);
2681 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_RELOAD
, 0);
2682 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_COUNT_MODE
,
2683 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS
);
2684 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_COUNT_THRSHLD
, 0);
2686 if (nic_data
->datapath_caps2
&
2687 1 << MC_CMD_GET_CAPABILITIES_V2_OUT_INIT_EVQ_V2_LBN
) {
2688 /* Use the new generic approach to specifying event queue
2689 * configuration, requesting lower latency or higher throughput.
2690 * The options that actually get used appear in the output.
2692 MCDI_POPULATE_DWORD_2(inbuf
, INIT_EVQ_V2_IN_FLAGS
,
2693 INIT_EVQ_V2_IN_FLAG_INTERRUPTING
, 1,
2694 INIT_EVQ_V2_IN_FLAG_TYPE
,
2695 MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO
);
2697 bool cut_thru
= !(nic_data
->datapath_caps
&
2698 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN
);
2700 MCDI_POPULATE_DWORD_4(inbuf
, INIT_EVQ_IN_FLAGS
,
2701 INIT_EVQ_IN_FLAG_INTERRUPTING
, 1,
2702 INIT_EVQ_IN_FLAG_RX_MERGE
, 1,
2703 INIT_EVQ_IN_FLAG_TX_MERGE
, 1,
2704 INIT_EVQ_IN_FLAG_CUT_THRU
, cut_thru
);
2707 dma_addr
= channel
->eventq
.buf
.dma_addr
;
2708 for (i
= 0; i
< entries
; ++i
) {
2709 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_EVQ_IN_DMA_ADDR
, i
, dma_addr
);
2710 dma_addr
+= EFX_BUF_SIZE
;
2713 inlen
= MC_CMD_INIT_EVQ_IN_LEN(entries
);
2715 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_EVQ
, inbuf
, inlen
,
2716 outbuf
, sizeof(outbuf
), &outlen
);
2718 if (outlen
>= MC_CMD_INIT_EVQ_V2_OUT_LEN
)
2719 netif_dbg(efx
, drv
, efx
->net_dev
,
2720 "Channel %d using event queue flags %08x\n",
2722 MCDI_DWORD(outbuf
, INIT_EVQ_V2_OUT_FLAGS
));
2724 /* IRQ return is ignored */
2725 if (channel
->channel
|| rc
)
2728 /* Successfully created event queue on channel 0 */
2729 rc
= efx_mcdi_get_workarounds(efx
, &implemented
, &enabled
);
2730 if (rc
== -ENOSYS
) {
2731 /* GET_WORKAROUNDS was implemented before this workaround,
2732 * thus it must be unavailable in this firmware.
2734 nic_data
->workaround_26807
= false;
2739 nic_data
->workaround_26807
=
2740 !!(enabled
& MC_CMD_GET_WORKAROUNDS_OUT_BUG26807
);
2742 if (implemented
& MC_CMD_GET_WORKAROUNDS_OUT_BUG26807
&&
2743 !nic_data
->workaround_26807
) {
2746 rc
= efx_mcdi_set_workaround(efx
,
2747 MC_CMD_WORKAROUND_BUG26807
,
2752 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN
) {
2753 netif_info(efx
, drv
, efx
->net_dev
,
2754 "other functions on NIC have been reset\n");
2756 /* With MCFW v4.6.x and earlier, the
2757 * boot count will have incremented,
2758 * so re-read the warm_boot_count
2759 * value now to ensure this function
2760 * doesn't think it has changed next
2763 rc
= efx_ef10_get_warm_boot_count(efx
);
2765 nic_data
->warm_boot_count
= rc
;
2769 nic_data
->workaround_26807
= true;
2770 } else if (rc
== -EPERM
) {
2780 efx_ef10_ev_fini(channel
);
2784 static void efx_ef10_ev_remove(struct efx_channel
*channel
)
2786 efx_nic_free_buffer(channel
->efx
, &channel
->eventq
.buf
);
2789 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue
*rx_queue
,
2790 unsigned int rx_queue_label
)
2792 struct efx_nic
*efx
= rx_queue
->efx
;
2794 netif_info(efx
, hw
, efx
->net_dev
,
2795 "rx event arrived on queue %d labeled as queue %u\n",
2796 efx_rx_queue_index(rx_queue
), rx_queue_label
);
2798 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
2802 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue
*rx_queue
,
2803 unsigned int actual
, unsigned int expected
)
2805 unsigned int dropped
= (actual
- expected
) & rx_queue
->ptr_mask
;
2806 struct efx_nic
*efx
= rx_queue
->efx
;
2808 netif_info(efx
, hw
, efx
->net_dev
,
2809 "dropped %d events (index=%d expected=%d)\n",
2810 dropped
, actual
, expected
);
2812 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
2815 /* partially received RX was aborted. clean up. */
2816 static void efx_ef10_handle_rx_abort(struct efx_rx_queue
*rx_queue
)
2818 unsigned int rx_desc_ptr
;
2820 netif_dbg(rx_queue
->efx
, hw
, rx_queue
->efx
->net_dev
,
2821 "scattered RX aborted (dropping %u buffers)\n",
2822 rx_queue
->scatter_n
);
2824 rx_desc_ptr
= rx_queue
->removed_count
& rx_queue
->ptr_mask
;
2826 efx_rx_packet(rx_queue
, rx_desc_ptr
, rx_queue
->scatter_n
,
2827 0, EFX_RX_PKT_DISCARD
);
2829 rx_queue
->removed_count
+= rx_queue
->scatter_n
;
2830 rx_queue
->scatter_n
= 0;
2831 rx_queue
->scatter_len
= 0;
2832 ++efx_rx_queue_channel(rx_queue
)->n_rx_nodesc_trunc
;
2835 static int efx_ef10_handle_rx_event(struct efx_channel
*channel
,
2836 const efx_qword_t
*event
)
2838 unsigned int rx_bytes
, next_ptr_lbits
, rx_queue_label
, rx_l4_class
;
2839 unsigned int n_descs
, n_packets
, i
;
2840 struct efx_nic
*efx
= channel
->efx
;
2841 struct efx_rx_queue
*rx_queue
;
2845 if (unlikely(ACCESS_ONCE(efx
->reset_pending
)))
2848 /* Basic packet information */
2849 rx_bytes
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_BYTES
);
2850 next_ptr_lbits
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_DSC_PTR_LBITS
);
2851 rx_queue_label
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_QLABEL
);
2852 rx_l4_class
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_L4_CLASS
);
2853 rx_cont
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_CONT
);
2855 if (EFX_QWORD_FIELD(*event
, ESF_DZ_RX_DROP_EVENT
))
2856 netdev_WARN(efx
->net_dev
, "saw RX_DROP_EVENT: event="
2858 EFX_QWORD_VAL(*event
));
2860 rx_queue
= efx_channel_get_rx_queue(channel
);
2862 if (unlikely(rx_queue_label
!= efx_rx_queue_index(rx_queue
)))
2863 efx_ef10_handle_rx_wrong_queue(rx_queue
, rx_queue_label
);
2865 n_descs
= ((next_ptr_lbits
- rx_queue
->removed_count
) &
2866 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH
) - 1));
2868 if (n_descs
!= rx_queue
->scatter_n
+ 1) {
2869 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2871 /* detect rx abort */
2872 if (unlikely(n_descs
== rx_queue
->scatter_n
)) {
2873 if (rx_queue
->scatter_n
== 0 || rx_bytes
!= 0)
2874 netdev_WARN(efx
->net_dev
,
2875 "invalid RX abort: scatter_n=%u event="
2877 rx_queue
->scatter_n
,
2878 EFX_QWORD_VAL(*event
));
2879 efx_ef10_handle_rx_abort(rx_queue
);
2883 /* Check that RX completion merging is valid, i.e.
2884 * the current firmware supports it and this is a
2885 * non-scattered packet.
2887 if (!(nic_data
->datapath_caps
&
2888 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN
)) ||
2889 rx_queue
->scatter_n
!= 0 || rx_cont
) {
2890 efx_ef10_handle_rx_bad_lbits(
2891 rx_queue
, next_ptr_lbits
,
2892 (rx_queue
->removed_count
+
2893 rx_queue
->scatter_n
+ 1) &
2894 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH
) - 1));
2898 /* Merged completion for multiple non-scattered packets */
2899 rx_queue
->scatter_n
= 1;
2900 rx_queue
->scatter_len
= 0;
2901 n_packets
= n_descs
;
2902 ++channel
->n_rx_merge_events
;
2903 channel
->n_rx_merge_packets
+= n_packets
;
2904 flags
|= EFX_RX_PKT_PREFIX_LEN
;
2906 ++rx_queue
->scatter_n
;
2907 rx_queue
->scatter_len
+= rx_bytes
;
2913 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_RX_ECRC_ERR
)))
2914 flags
|= EFX_RX_PKT_DISCARD
;
2916 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_RX_IPCKSUM_ERR
))) {
2917 channel
->n_rx_ip_hdr_chksum_err
+= n_packets
;
2918 } else if (unlikely(EFX_QWORD_FIELD(*event
,
2919 ESF_DZ_RX_TCPUDP_CKSUM_ERR
))) {
2920 channel
->n_rx_tcp_udp_chksum_err
+= n_packets
;
2921 } else if (rx_l4_class
== ESE_DZ_L4_CLASS_TCP
||
2922 rx_l4_class
== ESE_DZ_L4_CLASS_UDP
) {
2923 flags
|= EFX_RX_PKT_CSUMMED
;
2926 if (rx_l4_class
== ESE_DZ_L4_CLASS_TCP
)
2927 flags
|= EFX_RX_PKT_TCP
;
2929 channel
->irq_mod_score
+= 2 * n_packets
;
2931 /* Handle received packet(s) */
2932 for (i
= 0; i
< n_packets
; i
++) {
2933 efx_rx_packet(rx_queue
,
2934 rx_queue
->removed_count
& rx_queue
->ptr_mask
,
2935 rx_queue
->scatter_n
, rx_queue
->scatter_len
,
2937 rx_queue
->removed_count
+= rx_queue
->scatter_n
;
2940 rx_queue
->scatter_n
= 0;
2941 rx_queue
->scatter_len
= 0;
2947 efx_ef10_handle_tx_event(struct efx_channel
*channel
, efx_qword_t
*event
)
2949 struct efx_nic
*efx
= channel
->efx
;
2950 struct efx_tx_queue
*tx_queue
;
2951 unsigned int tx_ev_desc_ptr
;
2952 unsigned int tx_ev_q_label
;
2955 if (unlikely(ACCESS_ONCE(efx
->reset_pending
)))
2958 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_TX_DROP_EVENT
)))
2961 /* Transmit completion */
2962 tx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, ESF_DZ_TX_DESCR_INDX
);
2963 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, ESF_DZ_TX_QLABEL
);
2964 tx_queue
= efx_channel_get_tx_queue(channel
,
2965 tx_ev_q_label
% EFX_TXQ_TYPES
);
2966 tx_descs
= ((tx_ev_desc_ptr
+ 1 - tx_queue
->read_count
) &
2967 tx_queue
->ptr_mask
);
2968 efx_xmit_done(tx_queue
, tx_ev_desc_ptr
& tx_queue
->ptr_mask
);
2974 efx_ef10_handle_driver_event(struct efx_channel
*channel
, efx_qword_t
*event
)
2976 struct efx_nic
*efx
= channel
->efx
;
2979 subcode
= EFX_QWORD_FIELD(*event
, ESF_DZ_DRV_SUB_CODE
);
2982 case ESE_DZ_DRV_TIMER_EV
:
2983 case ESE_DZ_DRV_WAKE_UP_EV
:
2985 case ESE_DZ_DRV_START_UP_EV
:
2986 /* event queue init complete. ok. */
2989 netif_err(efx
, hw
, efx
->net_dev
,
2990 "channel %d unknown driver event type %d"
2991 " (data " EFX_QWORD_FMT
")\n",
2992 channel
->channel
, subcode
,
2993 EFX_QWORD_VAL(*event
));
2998 static void efx_ef10_handle_driver_generated_event(struct efx_channel
*channel
,
3001 struct efx_nic
*efx
= channel
->efx
;
3004 subcode
= EFX_QWORD_FIELD(*event
, EFX_DWORD_0
);
3008 channel
->event_test_cpu
= raw_smp_processor_id();
3010 case EFX_EF10_REFILL
:
3011 /* The queue must be empty, so we won't receive any rx
3012 * events, so efx_process_channel() won't refill the
3013 * queue. Refill it here
3015 efx_fast_push_rx_descriptors(&channel
->rx_queue
, true);
3018 netif_err(efx
, hw
, efx
->net_dev
,
3019 "channel %d unknown driver event type %u"
3020 " (data " EFX_QWORD_FMT
")\n",
3021 channel
->channel
, (unsigned) subcode
,
3022 EFX_QWORD_VAL(*event
));
3026 static int efx_ef10_ev_process(struct efx_channel
*channel
, int quota
)
3028 struct efx_nic
*efx
= channel
->efx
;
3029 efx_qword_t event
, *p_event
;
3030 unsigned int read_ptr
;
3038 read_ptr
= channel
->eventq_read_ptr
;
3041 p_event
= efx_event(channel
, read_ptr
);
3044 if (!efx_event_present(&event
))
3047 EFX_SET_QWORD(*p_event
);
3051 ev_code
= EFX_QWORD_FIELD(event
, ESF_DZ_EV_CODE
);
3053 netif_vdbg(efx
, drv
, efx
->net_dev
,
3054 "processing event on %d " EFX_QWORD_FMT
"\n",
3055 channel
->channel
, EFX_QWORD_VAL(event
));
3058 case ESE_DZ_EV_CODE_MCDI_EV
:
3059 efx_mcdi_process_event(channel
, &event
);
3061 case ESE_DZ_EV_CODE_RX_EV
:
3062 spent
+= efx_ef10_handle_rx_event(channel
, &event
);
3063 if (spent
>= quota
) {
3064 /* XXX can we split a merged event to
3065 * avoid going over-quota?
3071 case ESE_DZ_EV_CODE_TX_EV
:
3072 tx_descs
+= efx_ef10_handle_tx_event(channel
, &event
);
3073 if (tx_descs
> efx
->txq_entries
) {
3076 } else if (++spent
== quota
) {
3080 case ESE_DZ_EV_CODE_DRIVER_EV
:
3081 efx_ef10_handle_driver_event(channel
, &event
);
3082 if (++spent
== quota
)
3085 case EFX_EF10_DRVGEN_EV
:
3086 efx_ef10_handle_driver_generated_event(channel
, &event
);
3089 netif_err(efx
, hw
, efx
->net_dev
,
3090 "channel %d unknown event type %d"
3091 " (data " EFX_QWORD_FMT
")\n",
3092 channel
->channel
, ev_code
,
3093 EFX_QWORD_VAL(event
));
3098 channel
->eventq_read_ptr
= read_ptr
;
3102 static void efx_ef10_ev_read_ack(struct efx_channel
*channel
)
3104 struct efx_nic
*efx
= channel
->efx
;
3107 if (EFX_EF10_WORKAROUND_35388(efx
)) {
3108 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE
<
3109 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH
));
3110 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE
>
3111 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH
));
3113 EFX_POPULATE_DWORD_2(rptr
, ERF_DD_EVQ_IND_RPTR_FLAGS
,
3114 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH
,
3115 ERF_DD_EVQ_IND_RPTR
,
3116 (channel
->eventq_read_ptr
&
3117 channel
->eventq_mask
) >>
3118 ERF_DD_EVQ_IND_RPTR_WIDTH
);
3119 efx_writed_page(efx
, &rptr
, ER_DD_EVQ_INDIRECT
,
3121 EFX_POPULATE_DWORD_2(rptr
, ERF_DD_EVQ_IND_RPTR_FLAGS
,
3122 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW
,
3123 ERF_DD_EVQ_IND_RPTR
,
3124 channel
->eventq_read_ptr
&
3125 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH
) - 1));
3126 efx_writed_page(efx
, &rptr
, ER_DD_EVQ_INDIRECT
,
3129 EFX_POPULATE_DWORD_1(rptr
, ERF_DZ_EVQ_RPTR
,
3130 channel
->eventq_read_ptr
&
3131 channel
->eventq_mask
);
3132 efx_writed_page(efx
, &rptr
, ER_DZ_EVQ_RPTR
, channel
->channel
);
3136 static void efx_ef10_ev_test_generate(struct efx_channel
*channel
)
3138 MCDI_DECLARE_BUF(inbuf
, MC_CMD_DRIVER_EVENT_IN_LEN
);
3139 struct efx_nic
*efx
= channel
->efx
;
3143 EFX_POPULATE_QWORD_2(event
,
3144 ESF_DZ_EV_CODE
, EFX_EF10_DRVGEN_EV
,
3145 ESF_DZ_EV_DATA
, EFX_EF10_TEST
);
3147 MCDI_SET_DWORD(inbuf
, DRIVER_EVENT_IN_EVQ
, channel
->channel
);
3149 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3150 * already swapped the data to little-endian order.
3152 memcpy(MCDI_PTR(inbuf
, DRIVER_EVENT_IN_DATA
), &event
.u64
[0],
3153 sizeof(efx_qword_t
));
3155 rc
= efx_mcdi_rpc(efx
, MC_CMD_DRIVER_EVENT
, inbuf
, sizeof(inbuf
),
3164 netif_err(efx
, hw
, efx
->net_dev
, "%s: failed rc=%d\n", __func__
, rc
);
3167 void efx_ef10_handle_drain_event(struct efx_nic
*efx
)
3169 if (atomic_dec_and_test(&efx
->active_queues
))
3170 wake_up(&efx
->flush_wq
);
3172 WARN_ON(atomic_read(&efx
->active_queues
) < 0);
3175 static int efx_ef10_fini_dmaq(struct efx_nic
*efx
)
3177 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
3178 struct efx_channel
*channel
;
3179 struct efx_tx_queue
*tx_queue
;
3180 struct efx_rx_queue
*rx_queue
;
3183 /* If the MC has just rebooted, the TX/RX queues will have already been
3184 * torn down, but efx->active_queues needs to be set to zero.
3186 if (nic_data
->must_realloc_vis
) {
3187 atomic_set(&efx
->active_queues
, 0);
3191 /* Do not attempt to write to the NIC during EEH recovery */
3192 if (efx
->state
!= STATE_RECOVERY
) {
3193 efx_for_each_channel(channel
, efx
) {
3194 efx_for_each_channel_rx_queue(rx_queue
, channel
)
3195 efx_ef10_rx_fini(rx_queue
);
3196 efx_for_each_channel_tx_queue(tx_queue
, channel
)
3197 efx_ef10_tx_fini(tx_queue
);
3200 wait_event_timeout(efx
->flush_wq
,
3201 atomic_read(&efx
->active_queues
) == 0,
3202 msecs_to_jiffies(EFX_MAX_FLUSH_TIME
));
3203 pending
= atomic_read(&efx
->active_queues
);
3205 netif_err(efx
, hw
, efx
->net_dev
, "failed to flush %d queues\n",
3214 static void efx_ef10_prepare_flr(struct efx_nic
*efx
)
3216 atomic_set(&efx
->active_queues
, 0);
3219 static bool efx_ef10_filter_equal(const struct efx_filter_spec
*left
,
3220 const struct efx_filter_spec
*right
)
3222 if ((left
->match_flags
^ right
->match_flags
) |
3223 ((left
->flags
^ right
->flags
) &
3224 (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_TX
)))
3227 return memcmp(&left
->outer_vid
, &right
->outer_vid
,
3228 sizeof(struct efx_filter_spec
) -
3229 offsetof(struct efx_filter_spec
, outer_vid
)) == 0;
3232 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec
*spec
)
3234 BUILD_BUG_ON(offsetof(struct efx_filter_spec
, outer_vid
) & 3);
3235 return jhash2((const u32
*)&spec
->outer_vid
,
3236 (sizeof(struct efx_filter_spec
) -
3237 offsetof(struct efx_filter_spec
, outer_vid
)) / 4,
3239 /* XXX should we randomise the initval? */
3242 /* Decide whether a filter should be exclusive or else should allow
3243 * delivery to additional recipients. Currently we decide that
3244 * filters for specific local unicast MAC and IP addresses are
3247 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec
*spec
)
3249 if (spec
->match_flags
& EFX_FILTER_MATCH_LOC_MAC
&&
3250 !is_multicast_ether_addr(spec
->loc_mac
))
3253 if ((spec
->match_flags
&
3254 (EFX_FILTER_MATCH_ETHER_TYPE
| EFX_FILTER_MATCH_LOC_HOST
)) ==
3255 (EFX_FILTER_MATCH_ETHER_TYPE
| EFX_FILTER_MATCH_LOC_HOST
)) {
3256 if (spec
->ether_type
== htons(ETH_P_IP
) &&
3257 !ipv4_is_multicast(spec
->loc_host
[0]))
3259 if (spec
->ether_type
== htons(ETH_P_IPV6
) &&
3260 ((const u8
*)spec
->loc_host
)[0] != 0xff)
3267 static struct efx_filter_spec
*
3268 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table
*table
,
3269 unsigned int filter_idx
)
3271 return (struct efx_filter_spec
*)(table
->entry
[filter_idx
].spec
&
3272 ~EFX_EF10_FILTER_FLAGS
);
3276 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table
*table
,
3277 unsigned int filter_idx
)
3279 return table
->entry
[filter_idx
].spec
& EFX_EF10_FILTER_FLAGS
;
3283 efx_ef10_filter_set_entry(struct efx_ef10_filter_table
*table
,
3284 unsigned int filter_idx
,
3285 const struct efx_filter_spec
*spec
,
3288 table
->entry
[filter_idx
].spec
= (unsigned long)spec
| flags
;
3291 static void efx_ef10_filter_push_prep(struct efx_nic
*efx
,
3292 const struct efx_filter_spec
*spec
,
3293 efx_dword_t
*inbuf
, u64 handle
,
3296 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
3297 u32 flags
= spec
->flags
;
3299 memset(inbuf
, 0, MC_CMD_FILTER_OP_IN_LEN
);
3301 /* Remove RSS flag if we don't have an RSS context. */
3302 if (flags
& EFX_FILTER_FLAG_RX_RSS
&&
3303 spec
->rss_context
== EFX_FILTER_RSS_CONTEXT_DEFAULT
&&
3304 nic_data
->rx_rss_context
== EFX_EF10_RSS_CONTEXT_INVALID
)
3305 flags
&= ~EFX_FILTER_FLAG_RX_RSS
;
3308 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3309 MC_CMD_FILTER_OP_IN_OP_REPLACE
);
3310 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
, handle
);
3312 u32 match_fields
= 0;
3314 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3315 efx_ef10_filter_is_exclusive(spec
) ?
3316 MC_CMD_FILTER_OP_IN_OP_INSERT
:
3317 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE
);
3319 /* Convert match flags and values. Unlike almost
3320 * everything else in MCDI, these fields are in
3321 * network byte order.
3323 if (spec
->match_flags
& EFX_FILTER_MATCH_LOC_MAC_IG
)
3325 is_multicast_ether_addr(spec
->loc_mac
) ?
3326 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN
:
3327 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN
;
3328 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3329 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3331 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3332 mcdi_field ## _LBN; \
3334 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3335 sizeof(spec->gen_field)); \
3336 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3337 &spec->gen_field, sizeof(spec->gen_field)); \
3339 COPY_FIELD(REM_HOST
, rem_host
, SRC_IP
);
3340 COPY_FIELD(LOC_HOST
, loc_host
, DST_IP
);
3341 COPY_FIELD(REM_MAC
, rem_mac
, SRC_MAC
);
3342 COPY_FIELD(REM_PORT
, rem_port
, SRC_PORT
);
3343 COPY_FIELD(LOC_MAC
, loc_mac
, DST_MAC
);
3344 COPY_FIELD(LOC_PORT
, loc_port
, DST_PORT
);
3345 COPY_FIELD(ETHER_TYPE
, ether_type
, ETHER_TYPE
);
3346 COPY_FIELD(INNER_VID
, inner_vid
, INNER_VLAN
);
3347 COPY_FIELD(OUTER_VID
, outer_vid
, OUTER_VLAN
);
3348 COPY_FIELD(IP_PROTO
, ip_proto
, IP_PROTO
);
3350 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_MATCH_FIELDS
,
3354 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_PORT_ID
, nic_data
->vport_id
);
3355 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_DEST
,
3356 spec
->dmaq_id
== EFX_FILTER_RX_DMAQ_ID_DROP
?
3357 MC_CMD_FILTER_OP_IN_RX_DEST_DROP
:
3358 MC_CMD_FILTER_OP_IN_RX_DEST_HOST
);
3359 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_TX_DOMAIN
, 0);
3360 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_TX_DEST
,
3361 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT
);
3362 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_QUEUE
,
3363 spec
->dmaq_id
== EFX_FILTER_RX_DMAQ_ID_DROP
?
3365 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_MODE
,
3366 (flags
& EFX_FILTER_FLAG_RX_RSS
) ?
3367 MC_CMD_FILTER_OP_IN_RX_MODE_RSS
:
3368 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE
);
3369 if (flags
& EFX_FILTER_FLAG_RX_RSS
)
3370 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_CONTEXT
,
3371 spec
->rss_context
!=
3372 EFX_FILTER_RSS_CONTEXT_DEFAULT
?
3373 spec
->rss_context
: nic_data
->rx_rss_context
);
3376 static int efx_ef10_filter_push(struct efx_nic
*efx
,
3377 const struct efx_filter_spec
*spec
,
3378 u64
*handle
, bool replacing
)
3380 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
3381 MCDI_DECLARE_BUF(outbuf
, MC_CMD_FILTER_OP_OUT_LEN
);
3384 efx_ef10_filter_push_prep(efx
, spec
, inbuf
, *handle
, replacing
);
3385 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
),
3386 outbuf
, sizeof(outbuf
), NULL
);
3388 *handle
= MCDI_QWORD(outbuf
, FILTER_OP_OUT_HANDLE
);
3390 rc
= -EBUSY
; /* to match efx_farch_filter_insert() */
3394 static u32
efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec
*spec
)
3396 unsigned int match_flags
= spec
->match_flags
;
3399 if (match_flags
& EFX_FILTER_MATCH_LOC_MAC_IG
) {
3400 match_flags
&= ~EFX_FILTER_MATCH_LOC_MAC_IG
;
3402 is_multicast_ether_addr(spec
->loc_mac
) ?
3403 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN
) :
3404 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN
);
3407 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) { \
3408 unsigned int old_match_flags = match_flags; \
3409 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
3410 if (match_flags != old_match_flags) \
3412 (1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3413 mcdi_field ## _LBN); \
3415 MAP_FILTER_TO_MCDI_FLAG(REM_HOST
, SRC_IP
);
3416 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST
, DST_IP
);
3417 MAP_FILTER_TO_MCDI_FLAG(REM_MAC
, SRC_MAC
);
3418 MAP_FILTER_TO_MCDI_FLAG(REM_PORT
, SRC_PORT
);
3419 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC
, DST_MAC
);
3420 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT
, DST_PORT
);
3421 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE
, ETHER_TYPE
);
3422 MAP_FILTER_TO_MCDI_FLAG(INNER_VID
, INNER_VLAN
);
3423 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID
, OUTER_VLAN
);
3424 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO
, IP_PROTO
);
3425 #undef MAP_FILTER_TO_MCDI_FLAG
3427 /* Did we map them all? */
3428 WARN_ON_ONCE(match_flags
);
3433 static int efx_ef10_filter_pri(struct efx_ef10_filter_table
*table
,
3434 const struct efx_filter_spec
*spec
)
3436 u32 mcdi_flags
= efx_ef10_filter_mcdi_flags_from_spec(spec
);
3437 unsigned int match_pri
;
3440 match_pri
< table
->rx_match_count
;
3442 if (table
->rx_match_mcdi_flags
[match_pri
] == mcdi_flags
)
3445 return -EPROTONOSUPPORT
;
3448 static s32
efx_ef10_filter_insert(struct efx_nic
*efx
,
3449 struct efx_filter_spec
*spec
,
3452 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3453 DECLARE_BITMAP(mc_rem_map
, EFX_EF10_FILTER_SEARCH_LIMIT
);
3454 struct efx_filter_spec
*saved_spec
;
3455 unsigned int match_pri
, hash
;
3456 unsigned int priv_flags
;
3457 bool replacing
= false;
3463 /* For now, only support RX filters */
3464 if ((spec
->flags
& (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_TX
)) !=
3468 rc
= efx_ef10_filter_pri(table
, spec
);
3473 hash
= efx_ef10_filter_hash(spec
);
3474 is_mc_recip
= efx_filter_is_mc_recipient(spec
);
3476 bitmap_zero(mc_rem_map
, EFX_EF10_FILTER_SEARCH_LIMIT
);
3478 /* Find any existing filters with the same match tuple or
3479 * else a free slot to insert at. If any of them are busy,
3480 * we have to wait and retry.
3483 unsigned int depth
= 1;
3486 spin_lock_bh(&efx
->filter_lock
);
3489 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3490 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
3495 } else if (efx_ef10_filter_equal(spec
, saved_spec
)) {
3496 if (table
->entry
[i
].spec
&
3497 EFX_EF10_FILTER_FLAG_BUSY
)
3499 if (spec
->priority
< saved_spec
->priority
&&
3500 spec
->priority
!= EFX_FILTER_PRI_AUTO
) {
3505 /* This is the only one */
3506 if (spec
->priority
==
3507 saved_spec
->priority
&&
3514 } else if (spec
->priority
>
3515 saved_spec
->priority
||
3517 saved_spec
->priority
&&
3522 __set_bit(depth
, mc_rem_map
);
3526 /* Once we reach the maximum search depth, use
3527 * the first suitable slot or return -EBUSY if
3530 if (depth
== EFX_EF10_FILTER_SEARCH_LIMIT
) {
3531 if (ins_index
< 0) {
3541 prepare_to_wait(&table
->waitq
, &wait
, TASK_UNINTERRUPTIBLE
);
3542 spin_unlock_bh(&efx
->filter_lock
);
3547 /* Create a software table entry if necessary, and mark it
3548 * busy. We might yet fail to insert, but any attempt to
3549 * insert a conflicting filter while we're waiting for the
3550 * firmware must find the busy entry.
3552 saved_spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
3554 if (spec
->priority
== EFX_FILTER_PRI_AUTO
&&
3555 saved_spec
->priority
>= EFX_FILTER_PRI_AUTO
) {
3556 /* Just make sure it won't be removed */
3557 if (saved_spec
->priority
> EFX_FILTER_PRI_AUTO
)
3558 saved_spec
->flags
|= EFX_FILTER_FLAG_RX_OVER_AUTO
;
3559 table
->entry
[ins_index
].spec
&=
3560 ~EFX_EF10_FILTER_FLAG_AUTO_OLD
;
3565 priv_flags
= efx_ef10_filter_entry_flags(table
, ins_index
);
3567 saved_spec
= kmalloc(sizeof(*spec
), GFP_ATOMIC
);
3572 *saved_spec
= *spec
;
3575 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
,
3576 priv_flags
| EFX_EF10_FILTER_FLAG_BUSY
);
3578 /* Mark lower-priority multicast recipients busy prior to removal */
3580 unsigned int depth
, i
;
3582 for (depth
= 0; depth
< EFX_EF10_FILTER_SEARCH_LIMIT
; depth
++) {
3583 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3584 if (test_bit(depth
, mc_rem_map
))
3585 table
->entry
[i
].spec
|=
3586 EFX_EF10_FILTER_FLAG_BUSY
;
3590 spin_unlock_bh(&efx
->filter_lock
);
3592 rc
= efx_ef10_filter_push(efx
, spec
, &table
->entry
[ins_index
].handle
,
3595 /* Finalise the software table entry */
3596 spin_lock_bh(&efx
->filter_lock
);
3599 /* Update the fields that may differ */
3600 if (saved_spec
->priority
== EFX_FILTER_PRI_AUTO
)
3601 saved_spec
->flags
|=
3602 EFX_FILTER_FLAG_RX_OVER_AUTO
;
3603 saved_spec
->priority
= spec
->priority
;
3604 saved_spec
->flags
&= EFX_FILTER_FLAG_RX_OVER_AUTO
;
3605 saved_spec
->flags
|= spec
->flags
;
3606 saved_spec
->rss_context
= spec
->rss_context
;
3607 saved_spec
->dmaq_id
= spec
->dmaq_id
;
3609 } else if (!replacing
) {
3613 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
, priv_flags
);
3615 /* Remove and finalise entries for lower-priority multicast
3619 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
3620 unsigned int depth
, i
;
3622 memset(inbuf
, 0, sizeof(inbuf
));
3624 for (depth
= 0; depth
< EFX_EF10_FILTER_SEARCH_LIMIT
; depth
++) {
3625 if (!test_bit(depth
, mc_rem_map
))
3628 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3629 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
3630 priv_flags
= efx_ef10_filter_entry_flags(table
, i
);
3633 spin_unlock_bh(&efx
->filter_lock
);
3634 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3635 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
3636 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
3637 table
->entry
[i
].handle
);
3638 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
,
3639 inbuf
, sizeof(inbuf
),
3641 spin_lock_bh(&efx
->filter_lock
);
3649 priv_flags
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
3651 efx_ef10_filter_set_entry(table
, i
, saved_spec
,
3656 /* If successful, return the inserted filter ID */
3658 rc
= match_pri
* HUNT_FILTER_TBL_ROWS
+ ins_index
;
3660 wake_up_all(&table
->waitq
);
3662 spin_unlock_bh(&efx
->filter_lock
);
3663 finish_wait(&table
->waitq
, &wait
);
3667 static void efx_ef10_filter_update_rx_scatter(struct efx_nic
*efx
)
3669 /* no need to do anything here on EF10 */
3673 * If !by_index, remove by ID
3674 * If by_index, remove by index
3675 * Filter ID may come from userland and must be range-checked.
3677 static int efx_ef10_filter_remove_internal(struct efx_nic
*efx
,
3678 unsigned int priority_mask
,
3679 u32 filter_id
, bool by_index
)
3681 unsigned int filter_idx
= filter_id
% HUNT_FILTER_TBL_ROWS
;
3682 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3683 MCDI_DECLARE_BUF(inbuf
,
3684 MC_CMD_FILTER_OP_IN_HANDLE_OFST
+
3685 MC_CMD_FILTER_OP_IN_HANDLE_LEN
);
3686 struct efx_filter_spec
*spec
;
3690 /* Find the software table entry and mark it busy. Don't
3691 * remove it yet; any attempt to update while we're waiting
3692 * for the firmware must find the busy entry.
3695 spin_lock_bh(&efx
->filter_lock
);
3696 if (!(table
->entry
[filter_idx
].spec
&
3697 EFX_EF10_FILTER_FLAG_BUSY
))
3699 prepare_to_wait(&table
->waitq
, &wait
, TASK_UNINTERRUPTIBLE
);
3700 spin_unlock_bh(&efx
->filter_lock
);
3704 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3707 efx_ef10_filter_pri(table
, spec
) !=
3708 filter_id
/ HUNT_FILTER_TBL_ROWS
)) {
3713 if (spec
->flags
& EFX_FILTER_FLAG_RX_OVER_AUTO
&&
3714 priority_mask
== (1U << EFX_FILTER_PRI_AUTO
)) {
3715 /* Just remove flags */
3716 spec
->flags
&= ~EFX_FILTER_FLAG_RX_OVER_AUTO
;
3717 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_AUTO_OLD
;
3722 if (!(priority_mask
& (1U << spec
->priority
))) {
3727 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
3728 spin_unlock_bh(&efx
->filter_lock
);
3730 if (spec
->flags
& EFX_FILTER_FLAG_RX_OVER_AUTO
) {
3731 /* Reset to an automatic filter */
3733 struct efx_filter_spec new_spec
= *spec
;
3735 new_spec
.priority
= EFX_FILTER_PRI_AUTO
;
3736 new_spec
.flags
= (EFX_FILTER_FLAG_RX
|
3737 (efx_rss_enabled(efx
) ?
3738 EFX_FILTER_FLAG_RX_RSS
: 0));
3739 new_spec
.dmaq_id
= 0;
3740 new_spec
.rss_context
= EFX_FILTER_RSS_CONTEXT_DEFAULT
;
3741 rc
= efx_ef10_filter_push(efx
, &new_spec
,
3742 &table
->entry
[filter_idx
].handle
,
3745 spin_lock_bh(&efx
->filter_lock
);
3749 /* Really remove the filter */
3751 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3752 efx_ef10_filter_is_exclusive(spec
) ?
3753 MC_CMD_FILTER_OP_IN_OP_REMOVE
:
3754 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
3755 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
3756 table
->entry
[filter_idx
].handle
);
3757 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
,
3758 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
3760 spin_lock_bh(&efx
->filter_lock
);
3763 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
3767 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
3768 wake_up_all(&table
->waitq
);
3770 spin_unlock_bh(&efx
->filter_lock
);
3771 finish_wait(&table
->waitq
, &wait
);
3775 static int efx_ef10_filter_remove_safe(struct efx_nic
*efx
,
3776 enum efx_filter_priority priority
,
3779 return efx_ef10_filter_remove_internal(efx
, 1U << priority
,
3783 static u32
efx_ef10_filter_get_unsafe_id(struct efx_nic
*efx
, u32 filter_id
)
3785 return filter_id
% HUNT_FILTER_TBL_ROWS
;
3788 static void efx_ef10_filter_remove_unsafe(struct efx_nic
*efx
,
3789 enum efx_filter_priority priority
,
3792 if (filter_id
== EFX_EF10_FILTER_ID_INVALID
)
3794 efx_ef10_filter_remove_internal(efx
, 1U << priority
, filter_id
, true);
3797 static int efx_ef10_filter_get_safe(struct efx_nic
*efx
,
3798 enum efx_filter_priority priority
,
3799 u32 filter_id
, struct efx_filter_spec
*spec
)
3801 unsigned int filter_idx
= filter_id
% HUNT_FILTER_TBL_ROWS
;
3802 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3803 const struct efx_filter_spec
*saved_spec
;
3806 spin_lock_bh(&efx
->filter_lock
);
3807 saved_spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3808 if (saved_spec
&& saved_spec
->priority
== priority
&&
3809 efx_ef10_filter_pri(table
, saved_spec
) ==
3810 filter_id
/ HUNT_FILTER_TBL_ROWS
) {
3811 *spec
= *saved_spec
;
3816 spin_unlock_bh(&efx
->filter_lock
);
3820 static int efx_ef10_filter_clear_rx(struct efx_nic
*efx
,
3821 enum efx_filter_priority priority
)
3823 unsigned int priority_mask
;
3827 priority_mask
= (((1U << (priority
+ 1)) - 1) &
3828 ~(1U << EFX_FILTER_PRI_AUTO
));
3830 for (i
= 0; i
< HUNT_FILTER_TBL_ROWS
; i
++) {
3831 rc
= efx_ef10_filter_remove_internal(efx
, priority_mask
,
3833 if (rc
&& rc
!= -ENOENT
)
3840 static u32
efx_ef10_filter_count_rx_used(struct efx_nic
*efx
,
3841 enum efx_filter_priority priority
)
3843 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3844 unsigned int filter_idx
;
3847 spin_lock_bh(&efx
->filter_lock
);
3848 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
3849 if (table
->entry
[filter_idx
].spec
&&
3850 efx_ef10_filter_entry_spec(table
, filter_idx
)->priority
==
3854 spin_unlock_bh(&efx
->filter_lock
);
3858 static u32
efx_ef10_filter_get_rx_id_limit(struct efx_nic
*efx
)
3860 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3862 return table
->rx_match_count
* HUNT_FILTER_TBL_ROWS
;
3865 static s32
efx_ef10_filter_get_rx_ids(struct efx_nic
*efx
,
3866 enum efx_filter_priority priority
,
3869 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3870 struct efx_filter_spec
*spec
;
3871 unsigned int filter_idx
;
3874 spin_lock_bh(&efx
->filter_lock
);
3875 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
3876 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3877 if (spec
&& spec
->priority
== priority
) {
3878 if (count
== size
) {
3882 buf
[count
++] = (efx_ef10_filter_pri(table
, spec
) *
3883 HUNT_FILTER_TBL_ROWS
+
3887 spin_unlock_bh(&efx
->filter_lock
);
3891 #ifdef CONFIG_RFS_ACCEL
3893 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete
;
3895 static s32
efx_ef10_filter_rfs_insert(struct efx_nic
*efx
,
3896 struct efx_filter_spec
*spec
)
3898 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3899 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
3900 struct efx_filter_spec
*saved_spec
;
3901 unsigned int hash
, i
, depth
= 1;
3902 bool replacing
= false;
3907 /* Must be an RX filter without RSS and not for a multicast
3908 * destination address (RFS only works for connected sockets).
3909 * These restrictions allow us to pass only a tiny amount of
3910 * data through to the completion function.
3912 EFX_WARN_ON_PARANOID(spec
->flags
!=
3913 (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_RX_SCATTER
));
3914 EFX_WARN_ON_PARANOID(spec
->priority
!= EFX_FILTER_PRI_HINT
);
3915 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec
));
3917 hash
= efx_ef10_filter_hash(spec
);
3919 spin_lock_bh(&efx
->filter_lock
);
3921 /* Find any existing filter with the same match tuple or else
3922 * a free slot to insert at. If an existing filter is busy,
3923 * we have to give up.
3926 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3927 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
3932 } else if (efx_ef10_filter_equal(spec
, saved_spec
)) {
3933 if (table
->entry
[i
].spec
& EFX_EF10_FILTER_FLAG_BUSY
) {
3937 if (spec
->priority
< saved_spec
->priority
) {
3945 /* Once we reach the maximum search depth, use the
3946 * first suitable slot or return -EBUSY if there was
3949 if (depth
== EFX_EF10_FILTER_SEARCH_LIMIT
) {
3950 if (ins_index
< 0) {
3960 /* Create a software table entry if necessary, and mark it
3961 * busy. We might yet fail to insert, but any attempt to
3962 * insert a conflicting filter while we're waiting for the
3963 * firmware must find the busy entry.
3965 saved_spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
3969 saved_spec
= kmalloc(sizeof(*spec
), GFP_ATOMIC
);
3974 *saved_spec
= *spec
;
3976 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
,
3977 EFX_EF10_FILTER_FLAG_BUSY
);
3979 spin_unlock_bh(&efx
->filter_lock
);
3981 /* Pack up the variables needed on completion */
3982 cookie
= replacing
<< 31 | ins_index
<< 16 | spec
->dmaq_id
;
3984 efx_ef10_filter_push_prep(efx
, spec
, inbuf
,
3985 table
->entry
[ins_index
].handle
, replacing
);
3986 efx_mcdi_rpc_async(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
),
3987 MC_CMD_FILTER_OP_OUT_LEN
,
3988 efx_ef10_filter_rfs_insert_complete
, cookie
);
3993 spin_unlock_bh(&efx
->filter_lock
);
3998 efx_ef10_filter_rfs_insert_complete(struct efx_nic
*efx
, unsigned long cookie
,
3999 int rc
, efx_dword_t
*outbuf
,
4000 size_t outlen_actual
)
4002 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4003 unsigned int ins_index
, dmaq_id
;
4004 struct efx_filter_spec
*spec
;
4007 /* Unpack the cookie */
4008 replacing
= cookie
>> 31;
4009 ins_index
= (cookie
>> 16) & (HUNT_FILTER_TBL_ROWS
- 1);
4010 dmaq_id
= cookie
& 0xffff;
4012 spin_lock_bh(&efx
->filter_lock
);
4013 spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
4015 table
->entry
[ins_index
].handle
=
4016 MCDI_QWORD(outbuf
, FILTER_OP_OUT_HANDLE
);
4018 spec
->dmaq_id
= dmaq_id
;
4019 } else if (!replacing
) {
4023 efx_ef10_filter_set_entry(table
, ins_index
, spec
, 0);
4024 spin_unlock_bh(&efx
->filter_lock
);
4026 wake_up_all(&table
->waitq
);
4030 efx_ef10_filter_rfs_expire_complete(struct efx_nic
*efx
,
4031 unsigned long filter_idx
,
4032 int rc
, efx_dword_t
*outbuf
,
4033 size_t outlen_actual
);
4035 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic
*efx
, u32 flow_id
,
4036 unsigned int filter_idx
)
4038 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4039 struct efx_filter_spec
*spec
=
4040 efx_ef10_filter_entry_spec(table
, filter_idx
);
4041 MCDI_DECLARE_BUF(inbuf
,
4042 MC_CMD_FILTER_OP_IN_HANDLE_OFST
+
4043 MC_CMD_FILTER_OP_IN_HANDLE_LEN
);
4046 (table
->entry
[filter_idx
].spec
& EFX_EF10_FILTER_FLAG_BUSY
) ||
4047 spec
->priority
!= EFX_FILTER_PRI_HINT
||
4048 !rps_may_expire_flow(efx
->net_dev
, spec
->dmaq_id
,
4049 flow_id
, filter_idx
))
4052 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
4053 MC_CMD_FILTER_OP_IN_OP_REMOVE
);
4054 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
4055 table
->entry
[filter_idx
].handle
);
4056 if (efx_mcdi_rpc_async(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
), 0,
4057 efx_ef10_filter_rfs_expire_complete
, filter_idx
))
4060 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
4065 efx_ef10_filter_rfs_expire_complete(struct efx_nic
*efx
,
4066 unsigned long filter_idx
,
4067 int rc
, efx_dword_t
*outbuf
,
4068 size_t outlen_actual
)
4070 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4071 struct efx_filter_spec
*spec
=
4072 efx_ef10_filter_entry_spec(table
, filter_idx
);
4074 spin_lock_bh(&efx
->filter_lock
);
4077 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
4079 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
4080 wake_up_all(&table
->waitq
);
4081 spin_unlock_bh(&efx
->filter_lock
);
4084 #endif /* CONFIG_RFS_ACCEL */
4086 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags
)
4088 int match_flags
= 0;
4090 #define MAP_FLAG(gen_flag, mcdi_field) { \
4091 u32 old_mcdi_flags = mcdi_flags; \
4092 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
4093 mcdi_field ## _LBN); \
4094 if (mcdi_flags != old_mcdi_flags) \
4095 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
4097 MAP_FLAG(LOC_MAC_IG
, UNKNOWN_UCAST_DST
);
4098 MAP_FLAG(LOC_MAC_IG
, UNKNOWN_MCAST_DST
);
4099 MAP_FLAG(REM_HOST
, SRC_IP
);
4100 MAP_FLAG(LOC_HOST
, DST_IP
);
4101 MAP_FLAG(REM_MAC
, SRC_MAC
);
4102 MAP_FLAG(REM_PORT
, SRC_PORT
);
4103 MAP_FLAG(LOC_MAC
, DST_MAC
);
4104 MAP_FLAG(LOC_PORT
, DST_PORT
);
4105 MAP_FLAG(ETHER_TYPE
, ETHER_TYPE
);
4106 MAP_FLAG(INNER_VID
, INNER_VLAN
);
4107 MAP_FLAG(OUTER_VID
, OUTER_VLAN
);
4108 MAP_FLAG(IP_PROTO
, IP_PROTO
);
4111 /* Did we map them all? */
4118 static void efx_ef10_filter_cleanup_vlans(struct efx_nic
*efx
)
4120 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4121 struct efx_ef10_filter_vlan
*vlan
, *next_vlan
;
4123 /* See comment in efx_ef10_filter_table_remove() */
4124 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4130 list_for_each_entry_safe(vlan
, next_vlan
, &table
->vlan_list
, list
)
4131 efx_ef10_filter_del_vlan_internal(efx
, vlan
);
4134 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table
*table
,
4135 enum efx_filter_match_flags match_flags
)
4137 unsigned int match_pri
;
4141 match_pri
< table
->rx_match_count
;
4143 mf
= efx_ef10_filter_match_flags_from_mcdi(
4144 table
->rx_match_mcdi_flags
[match_pri
]);
4145 if (mf
== match_flags
)
4152 static int efx_ef10_filter_table_probe(struct efx_nic
*efx
)
4154 MCDI_DECLARE_BUF(inbuf
, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN
);
4155 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX
);
4156 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4157 struct net_device
*net_dev
= efx
->net_dev
;
4158 unsigned int pd_match_pri
, pd_match_count
;
4159 struct efx_ef10_filter_table
*table
;
4160 struct efx_ef10_vlan
*vlan
;
4164 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4167 if (efx
->filter_state
) /* already probed */
4170 table
= kzalloc(sizeof(*table
), GFP_KERNEL
);
4174 /* Find out which RX filter types are supported, and their priorities */
4175 MCDI_SET_DWORD(inbuf
, GET_PARSER_DISP_INFO_IN_OP
,
4176 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES
);
4177 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_PARSER_DISP_INFO
,
4178 inbuf
, sizeof(inbuf
), outbuf
, sizeof(outbuf
),
4182 pd_match_count
= MCDI_VAR_ARRAY_LEN(
4183 outlen
, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES
);
4184 table
->rx_match_count
= 0;
4186 for (pd_match_pri
= 0; pd_match_pri
< pd_match_count
; pd_match_pri
++) {
4190 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES
,
4192 rc
= efx_ef10_filter_match_flags_from_mcdi(mcdi_flags
);
4194 netif_dbg(efx
, probe
, efx
->net_dev
,
4195 "%s: fw flags %#x pri %u not supported in driver\n",
4196 __func__
, mcdi_flags
, pd_match_pri
);
4198 netif_dbg(efx
, probe
, efx
->net_dev
,
4199 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4200 __func__
, mcdi_flags
, pd_match_pri
,
4201 rc
, table
->rx_match_count
);
4202 table
->rx_match_mcdi_flags
[table
->rx_match_count
] = mcdi_flags
;
4203 table
->rx_match_count
++;
4207 if ((efx_supported_features(efx
) & NETIF_F_HW_VLAN_CTAG_FILTER
) &&
4208 !(efx_ef10_filter_match_supported(table
,
4209 (EFX_FILTER_MATCH_OUTER_VID
| EFX_FILTER_MATCH_LOC_MAC
)) &&
4210 efx_ef10_filter_match_supported(table
,
4211 (EFX_FILTER_MATCH_OUTER_VID
| EFX_FILTER_MATCH_LOC_MAC_IG
)))) {
4212 netif_info(efx
, probe
, net_dev
,
4213 "VLAN filters are not supported in this firmware variant\n");
4214 net_dev
->features
&= ~NETIF_F_HW_VLAN_CTAG_FILTER
;
4215 efx
->fixed_features
&= ~NETIF_F_HW_VLAN_CTAG_FILTER
;
4216 net_dev
->hw_features
&= ~NETIF_F_HW_VLAN_CTAG_FILTER
;
4219 table
->entry
= vzalloc(HUNT_FILTER_TBL_ROWS
* sizeof(*table
->entry
));
4220 if (!table
->entry
) {
4225 table
->mc_promisc_last
= false;
4226 table
->vlan_filter
=
4227 !!(efx
->net_dev
->features
& NETIF_F_HW_VLAN_CTAG_FILTER
);
4228 INIT_LIST_HEAD(&table
->vlan_list
);
4230 efx
->filter_state
= table
;
4231 init_waitqueue_head(&table
->waitq
);
4233 list_for_each_entry(vlan
, &nic_data
->vlan_list
, list
) {
4234 rc
= efx_ef10_filter_add_vlan(efx
, vlan
->vid
);
4242 efx_ef10_filter_cleanup_vlans(efx
);
4243 efx
->filter_state
= NULL
;
4249 /* Caller must hold efx->filter_sem for read if race against
4250 * efx_ef10_filter_table_remove() is possible
4252 static void efx_ef10_filter_table_restore(struct efx_nic
*efx
)
4254 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4255 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4256 struct efx_filter_spec
*spec
;
4257 unsigned int filter_idx
;
4258 bool failed
= false;
4261 WARN_ON(!rwsem_is_locked(&efx
->filter_sem
));
4263 if (!nic_data
->must_restore_filters
)
4269 spin_lock_bh(&efx
->filter_lock
);
4271 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
4272 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
4276 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
4277 spin_unlock_bh(&efx
->filter_lock
);
4279 rc
= efx_ef10_filter_push(efx
, spec
,
4280 &table
->entry
[filter_idx
].handle
,
4285 spin_lock_bh(&efx
->filter_lock
);
4288 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
4290 table
->entry
[filter_idx
].spec
&=
4291 ~EFX_EF10_FILTER_FLAG_BUSY
;
4295 spin_unlock_bh(&efx
->filter_lock
);
4298 netif_err(efx
, hw
, efx
->net_dev
,
4299 "unable to restore all filters\n");
4301 nic_data
->must_restore_filters
= false;
4304 static void efx_ef10_filter_table_remove(struct efx_nic
*efx
)
4306 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4307 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
4308 struct efx_filter_spec
*spec
;
4309 unsigned int filter_idx
;
4312 efx_ef10_filter_cleanup_vlans(efx
);
4313 efx
->filter_state
= NULL
;
4314 /* If we were called without locking, then it's not safe to free
4315 * the table as others might be using it. So we just WARN, leak
4316 * the memory, and potentially get an inconsistent filter table
4318 * This should never actually happen.
4320 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4326 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
4327 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
4331 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
4332 efx_ef10_filter_is_exclusive(spec
) ?
4333 MC_CMD_FILTER_OP_IN_OP_REMOVE
:
4334 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
4335 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
4336 table
->entry
[filter_idx
].handle
);
4337 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FILTER_OP
, inbuf
,
4338 sizeof(inbuf
), NULL
, 0, NULL
);
4340 netif_info(efx
, drv
, efx
->net_dev
,
4341 "%s: filter %04x remove failed\n",
4342 __func__
, filter_idx
);
4346 vfree(table
->entry
);
4350 static void efx_ef10_filter_mark_one_old(struct efx_nic
*efx
, uint16_t *id
)
4352 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4353 unsigned int filter_idx
;
4355 if (*id
!= EFX_EF10_FILTER_ID_INVALID
) {
4356 filter_idx
= efx_ef10_filter_get_unsafe_id(efx
, *id
);
4357 if (!table
->entry
[filter_idx
].spec
)
4358 netif_dbg(efx
, drv
, efx
->net_dev
,
4359 "marked null spec old %04x:%04x\n", *id
,
4361 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_AUTO_OLD
;
4362 *id
= EFX_EF10_FILTER_ID_INVALID
;
4366 /* Mark old per-VLAN filters that may need to be removed */
4367 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic
*efx
,
4368 struct efx_ef10_filter_vlan
*vlan
)
4370 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4373 for (i
= 0; i
< table
->dev_uc_count
; i
++)
4374 efx_ef10_filter_mark_one_old(efx
, &vlan
->uc
[i
]);
4375 for (i
= 0; i
< table
->dev_mc_count
; i
++)
4376 efx_ef10_filter_mark_one_old(efx
, &vlan
->mc
[i
]);
4377 efx_ef10_filter_mark_one_old(efx
, &vlan
->ucdef
);
4378 efx_ef10_filter_mark_one_old(efx
, &vlan
->bcast
);
4379 efx_ef10_filter_mark_one_old(efx
, &vlan
->mcdef
);
4382 /* Mark old filters that may need to be removed.
4383 * Caller must hold efx->filter_sem for read if race against
4384 * efx_ef10_filter_table_remove() is possible
4386 static void efx_ef10_filter_mark_old(struct efx_nic
*efx
)
4388 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4389 struct efx_ef10_filter_vlan
*vlan
;
4391 spin_lock_bh(&efx
->filter_lock
);
4392 list_for_each_entry(vlan
, &table
->vlan_list
, list
)
4393 _efx_ef10_filter_vlan_mark_old(efx
, vlan
);
4394 spin_unlock_bh(&efx
->filter_lock
);
4397 static void efx_ef10_filter_uc_addr_list(struct efx_nic
*efx
)
4399 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4400 struct net_device
*net_dev
= efx
->net_dev
;
4401 struct netdev_hw_addr
*uc
;
4405 addr_count
= netdev_uc_count(net_dev
);
4406 table
->uc_promisc
= !!(net_dev
->flags
& IFF_PROMISC
);
4407 table
->dev_uc_count
= 1 + addr_count
;
4408 ether_addr_copy(table
->dev_uc_list
[0].addr
, net_dev
->dev_addr
);
4410 netdev_for_each_uc_addr(uc
, net_dev
) {
4411 if (i
>= EFX_EF10_FILTER_DEV_UC_MAX
) {
4412 table
->uc_promisc
= true;
4415 ether_addr_copy(table
->dev_uc_list
[i
].addr
, uc
->addr
);
4420 static void efx_ef10_filter_mc_addr_list(struct efx_nic
*efx
)
4422 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4423 struct net_device
*net_dev
= efx
->net_dev
;
4424 struct netdev_hw_addr
*mc
;
4425 unsigned int i
, addr_count
;
4427 table
->mc_promisc
= !!(net_dev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
));
4429 addr_count
= netdev_mc_count(net_dev
);
4431 netdev_for_each_mc_addr(mc
, net_dev
) {
4432 if (i
>= EFX_EF10_FILTER_DEV_MC_MAX
) {
4433 table
->mc_promisc
= true;
4436 ether_addr_copy(table
->dev_mc_list
[i
].addr
, mc
->addr
);
4440 table
->dev_mc_count
= i
;
4443 static int efx_ef10_filter_insert_addr_list(struct efx_nic
*efx
,
4444 struct efx_ef10_filter_vlan
*vlan
,
4445 bool multicast
, bool rollback
)
4447 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4448 struct efx_ef10_dev_addr
*addr_list
;
4449 enum efx_filter_flags filter_flags
;
4450 struct efx_filter_spec spec
;
4458 addr_list
= table
->dev_mc_list
;
4459 addr_count
= table
->dev_mc_count
;
4462 addr_list
= table
->dev_uc_list
;
4463 addr_count
= table
->dev_uc_count
;
4467 filter_flags
= efx_rss_enabled(efx
) ? EFX_FILTER_FLAG_RX_RSS
: 0;
4469 /* Insert/renew filters */
4470 for (i
= 0; i
< addr_count
; i
++) {
4471 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
, filter_flags
, 0);
4472 efx_filter_set_eth_local(&spec
, vlan
->vid
, addr_list
[i
].addr
);
4473 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
4476 netif_info(efx
, drv
, efx
->net_dev
,
4477 "efx_ef10_filter_insert failed rc=%d\n",
4479 /* Fall back to promiscuous */
4480 for (j
= 0; j
< i
; j
++) {
4481 efx_ef10_filter_remove_unsafe(
4482 efx
, EFX_FILTER_PRI_AUTO
,
4484 ids
[j
] = EFX_EF10_FILTER_ID_INVALID
;
4488 /* mark as not inserted, and carry on */
4489 rc
= EFX_EF10_FILTER_ID_INVALID
;
4492 ids
[i
] = efx_ef10_filter_get_unsafe_id(efx
, rc
);
4495 if (multicast
&& rollback
) {
4496 /* Also need an Ethernet broadcast filter */
4497 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
, filter_flags
, 0);
4498 eth_broadcast_addr(baddr
);
4499 efx_filter_set_eth_local(&spec
, vlan
->vid
, baddr
);
4500 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
4502 netif_warn(efx
, drv
, efx
->net_dev
,
4503 "Broadcast filter insert failed rc=%d\n", rc
);
4504 /* Fall back to promiscuous */
4505 for (j
= 0; j
< i
; j
++) {
4506 efx_ef10_filter_remove_unsafe(
4507 efx
, EFX_FILTER_PRI_AUTO
,
4509 ids
[j
] = EFX_EF10_FILTER_ID_INVALID
;
4513 EFX_WARN_ON_PARANOID(vlan
->bcast
!=
4514 EFX_EF10_FILTER_ID_INVALID
);
4515 vlan
->bcast
= efx_ef10_filter_get_unsafe_id(efx
, rc
);
4522 static int efx_ef10_filter_insert_def(struct efx_nic
*efx
,
4523 struct efx_ef10_filter_vlan
*vlan
,
4524 bool multicast
, bool rollback
)
4526 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4527 enum efx_filter_flags filter_flags
;
4528 struct efx_filter_spec spec
;
4532 filter_flags
= efx_rss_enabled(efx
) ? EFX_FILTER_FLAG_RX_RSS
: 0;
4534 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
, filter_flags
, 0);
4537 efx_filter_set_mc_def(&spec
);
4539 efx_filter_set_uc_def(&spec
);
4541 if (vlan
->vid
!= EFX_FILTER_VID_UNSPEC
)
4542 efx_filter_set_eth_local(&spec
, vlan
->vid
, NULL
);
4544 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
4546 netif_printk(efx
, drv
, rc
== -EPERM
? KERN_DEBUG
: KERN_WARNING
,
4548 "%scast mismatch filter insert failed rc=%d\n",
4549 multicast
? "Multi" : "Uni", rc
);
4550 } else if (multicast
) {
4551 EFX_WARN_ON_PARANOID(vlan
->mcdef
!= EFX_EF10_FILTER_ID_INVALID
);
4552 vlan
->mcdef
= efx_ef10_filter_get_unsafe_id(efx
, rc
);
4553 if (!nic_data
->workaround_26807
) {
4554 /* Also need an Ethernet broadcast filter */
4555 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
,
4557 eth_broadcast_addr(baddr
);
4558 efx_filter_set_eth_local(&spec
, vlan
->vid
, baddr
);
4559 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
4561 netif_warn(efx
, drv
, efx
->net_dev
,
4562 "Broadcast filter insert failed rc=%d\n",
4565 /* Roll back the mc_def filter */
4566 efx_ef10_filter_remove_unsafe(
4567 efx
, EFX_FILTER_PRI_AUTO
,
4569 vlan
->mcdef
= EFX_EF10_FILTER_ID_INVALID
;
4573 EFX_WARN_ON_PARANOID(vlan
->bcast
!=
4574 EFX_EF10_FILTER_ID_INVALID
);
4575 vlan
->bcast
= efx_ef10_filter_get_unsafe_id(efx
, rc
);
4580 EFX_WARN_ON_PARANOID(vlan
->ucdef
!= EFX_EF10_FILTER_ID_INVALID
);
4587 /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4588 * flag or removes these filters, we don't need to hold the filter_lock while
4589 * scanning for these filters.
4591 static void efx_ef10_filter_remove_old(struct efx_nic
*efx
)
4593 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4594 int remove_failed
= 0;
4595 int remove_noent
= 0;
4599 for (i
= 0; i
< HUNT_FILTER_TBL_ROWS
; i
++) {
4600 if (ACCESS_ONCE(table
->entry
[i
].spec
) &
4601 EFX_EF10_FILTER_FLAG_AUTO_OLD
) {
4602 rc
= efx_ef10_filter_remove_internal(efx
,
4603 1U << EFX_FILTER_PRI_AUTO
, i
, true);
4612 netif_info(efx
, drv
, efx
->net_dev
,
4613 "%s: failed to remove %d filters\n",
4614 __func__
, remove_failed
);
4616 netif_info(efx
, drv
, efx
->net_dev
,
4617 "%s: failed to remove %d non-existent filters\n",
4618 __func__
, remove_noent
);
4621 static int efx_ef10_vport_set_mac_address(struct efx_nic
*efx
)
4623 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4624 u8 mac_old
[ETH_ALEN
];
4627 /* Only reconfigure a PF-created vport */
4628 if (is_zero_ether_addr(nic_data
->vport_mac
))
4631 efx_device_detach_sync(efx
);
4632 efx_net_stop(efx
->net_dev
);
4633 down_write(&efx
->filter_sem
);
4634 efx_ef10_filter_table_remove(efx
);
4635 up_write(&efx
->filter_sem
);
4637 rc
= efx_ef10_vadaptor_free(efx
, nic_data
->vport_id
);
4639 goto restore_filters
;
4641 ether_addr_copy(mac_old
, nic_data
->vport_mac
);
4642 rc
= efx_ef10_vport_del_mac(efx
, nic_data
->vport_id
,
4643 nic_data
->vport_mac
);
4645 goto restore_vadaptor
;
4647 rc
= efx_ef10_vport_add_mac(efx
, nic_data
->vport_id
,
4648 efx
->net_dev
->dev_addr
);
4650 ether_addr_copy(nic_data
->vport_mac
, efx
->net_dev
->dev_addr
);
4652 rc2
= efx_ef10_vport_add_mac(efx
, nic_data
->vport_id
, mac_old
);
4654 /* Failed to add original MAC, so clear vport_mac */
4655 eth_zero_addr(nic_data
->vport_mac
);
4661 rc2
= efx_ef10_vadaptor_alloc(efx
, nic_data
->vport_id
);
4665 down_write(&efx
->filter_sem
);
4666 rc2
= efx_ef10_filter_table_probe(efx
);
4667 up_write(&efx
->filter_sem
);
4671 rc2
= efx_net_open(efx
->net_dev
);
4675 netif_device_attach(efx
->net_dev
);
4680 netif_err(efx
, drv
, efx
->net_dev
,
4681 "Failed to restore when changing MAC address - scheduling reset\n");
4682 efx_schedule_reset(efx
, RESET_TYPE_DATAPATH
);
4684 return rc
? rc
: rc2
;
4687 /* Caller must hold efx->filter_sem for read if race against
4688 * efx_ef10_filter_table_remove() is possible
4690 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic
*efx
,
4691 struct efx_ef10_filter_vlan
*vlan
)
4693 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4694 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4696 /* Do not install unspecified VID if VLAN filtering is enabled.
4697 * Do not install all specified VIDs if VLAN filtering is disabled.
4699 if ((vlan
->vid
== EFX_FILTER_VID_UNSPEC
) == table
->vlan_filter
)
4702 /* Insert/renew unicast filters */
4703 if (table
->uc_promisc
) {
4704 efx_ef10_filter_insert_def(efx
, vlan
, false, false);
4705 efx_ef10_filter_insert_addr_list(efx
, vlan
, false, false);
4707 /* If any of the filters failed to insert, fall back to
4708 * promiscuous mode - add in the uc_def filter. But keep
4709 * our individual unicast filters.
4711 if (efx_ef10_filter_insert_addr_list(efx
, vlan
, false, false))
4712 efx_ef10_filter_insert_def(efx
, vlan
, false, false);
4715 /* Insert/renew multicast filters */
4716 /* If changing promiscuous state with cascaded multicast filters, remove
4717 * old filters first, so that packets are dropped rather than duplicated
4719 if (nic_data
->workaround_26807
&&
4720 table
->mc_promisc_last
!= table
->mc_promisc
)
4721 efx_ef10_filter_remove_old(efx
);
4722 if (table
->mc_promisc
) {
4723 if (nic_data
->workaround_26807
) {
4724 /* If we failed to insert promiscuous filters, rollback
4725 * and fall back to individual multicast filters
4727 if (efx_ef10_filter_insert_def(efx
, vlan
, true, true)) {
4728 /* Changing promisc state, so remove old filters */
4729 efx_ef10_filter_remove_old(efx
);
4730 efx_ef10_filter_insert_addr_list(efx
, vlan
,
4734 /* If we failed to insert promiscuous filters, don't
4735 * rollback. Regardless, also insert the mc_list
4737 efx_ef10_filter_insert_def(efx
, vlan
, true, false);
4738 efx_ef10_filter_insert_addr_list(efx
, vlan
, true, false);
4741 /* If any filters failed to insert, rollback and fall back to
4742 * promiscuous mode - mc_def filter and maybe broadcast. If
4743 * that fails, roll back again and insert as many of our
4744 * individual multicast filters as we can.
4746 if (efx_ef10_filter_insert_addr_list(efx
, vlan
, true, true)) {
4747 /* Changing promisc state, so remove old filters */
4748 if (nic_data
->workaround_26807
)
4749 efx_ef10_filter_remove_old(efx
);
4750 if (efx_ef10_filter_insert_def(efx
, vlan
, true, true))
4751 efx_ef10_filter_insert_addr_list(efx
, vlan
,
4757 /* Caller must hold efx->filter_sem for read if race against
4758 * efx_ef10_filter_table_remove() is possible
4760 static void efx_ef10_filter_sync_rx_mode(struct efx_nic
*efx
)
4762 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4763 struct net_device
*net_dev
= efx
->net_dev
;
4764 struct efx_ef10_filter_vlan
*vlan
;
4767 if (!efx_dev_registered(efx
))
4773 efx_ef10_filter_mark_old(efx
);
4775 /* Copy/convert the address lists; add the primary station
4776 * address and broadcast address
4778 netif_addr_lock_bh(net_dev
);
4779 efx_ef10_filter_uc_addr_list(efx
);
4780 efx_ef10_filter_mc_addr_list(efx
);
4781 netif_addr_unlock_bh(net_dev
);
4783 /* If VLAN filtering changes, all old filters are finally removed.
4784 * Do it in advance to avoid conflicts for unicast untagged and
4785 * VLAN 0 tagged filters.
4787 vlan_filter
= !!(net_dev
->features
& NETIF_F_HW_VLAN_CTAG_FILTER
);
4788 if (table
->vlan_filter
!= vlan_filter
) {
4789 table
->vlan_filter
= vlan_filter
;
4790 efx_ef10_filter_remove_old(efx
);
4793 list_for_each_entry(vlan
, &table
->vlan_list
, list
)
4794 efx_ef10_filter_vlan_sync_rx_mode(efx
, vlan
);
4796 efx_ef10_filter_remove_old(efx
);
4797 table
->mc_promisc_last
= table
->mc_promisc
;
4800 static struct efx_ef10_filter_vlan
*efx_ef10_filter_find_vlan(struct efx_nic
*efx
, u16 vid
)
4802 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4803 struct efx_ef10_filter_vlan
*vlan
;
4805 WARN_ON(!rwsem_is_locked(&efx
->filter_sem
));
4807 list_for_each_entry(vlan
, &table
->vlan_list
, list
) {
4808 if (vlan
->vid
== vid
)
4815 static int efx_ef10_filter_add_vlan(struct efx_nic
*efx
, u16 vid
)
4817 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4818 struct efx_ef10_filter_vlan
*vlan
;
4821 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4824 vlan
= efx_ef10_filter_find_vlan(efx
, vid
);
4825 if (WARN_ON(vlan
)) {
4826 netif_err(efx
, drv
, efx
->net_dev
,
4827 "VLAN %u already added\n", vid
);
4831 vlan
= kzalloc(sizeof(*vlan
), GFP_KERNEL
);
4837 for (i
= 0; i
< ARRAY_SIZE(vlan
->uc
); i
++)
4838 vlan
->uc
[i
] = EFX_EF10_FILTER_ID_INVALID
;
4839 for (i
= 0; i
< ARRAY_SIZE(vlan
->mc
); i
++)
4840 vlan
->mc
[i
] = EFX_EF10_FILTER_ID_INVALID
;
4841 vlan
->ucdef
= EFX_EF10_FILTER_ID_INVALID
;
4842 vlan
->bcast
= EFX_EF10_FILTER_ID_INVALID
;
4843 vlan
->mcdef
= EFX_EF10_FILTER_ID_INVALID
;
4845 list_add_tail(&vlan
->list
, &table
->vlan_list
);
4847 if (efx_dev_registered(efx
))
4848 efx_ef10_filter_vlan_sync_rx_mode(efx
, vlan
);
4853 static void efx_ef10_filter_del_vlan_internal(struct efx_nic
*efx
,
4854 struct efx_ef10_filter_vlan
*vlan
)
4858 /* See comment in efx_ef10_filter_table_remove() */
4859 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4862 list_del(&vlan
->list
);
4864 for (i
= 0; i
< ARRAY_SIZE(vlan
->uc
); i
++)
4865 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
,
4867 for (i
= 0; i
< ARRAY_SIZE(vlan
->mc
); i
++)
4868 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
,
4870 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
, vlan
->ucdef
);
4871 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
, vlan
->bcast
);
4872 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
, vlan
->mcdef
);
4877 static void efx_ef10_filter_del_vlan(struct efx_nic
*efx
, u16 vid
)
4879 struct efx_ef10_filter_vlan
*vlan
;
4881 /* See comment in efx_ef10_filter_table_remove() */
4882 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4885 vlan
= efx_ef10_filter_find_vlan(efx
, vid
);
4887 netif_err(efx
, drv
, efx
->net_dev
,
4888 "VLAN %u not found in filter state\n", vid
);
4892 efx_ef10_filter_del_vlan_internal(efx
, vlan
);
4895 static int efx_ef10_set_mac_address(struct efx_nic
*efx
)
4897 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_SET_MAC_IN_LEN
);
4898 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4899 bool was_enabled
= efx
->port_enabled
;
4902 efx_device_detach_sync(efx
);
4903 efx_net_stop(efx
->net_dev
);
4905 mutex_lock(&efx
->mac_lock
);
4906 down_write(&efx
->filter_sem
);
4907 efx_ef10_filter_table_remove(efx
);
4909 ether_addr_copy(MCDI_PTR(inbuf
, VADAPTOR_SET_MAC_IN_MACADDR
),
4910 efx
->net_dev
->dev_addr
);
4911 MCDI_SET_DWORD(inbuf
, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID
,
4912 nic_data
->vport_id
);
4913 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_VADAPTOR_SET_MAC
, inbuf
,
4914 sizeof(inbuf
), NULL
, 0, NULL
);
4916 efx_ef10_filter_table_probe(efx
);
4917 up_write(&efx
->filter_sem
);
4918 mutex_unlock(&efx
->mac_lock
);
4921 efx_net_open(efx
->net_dev
);
4922 netif_device_attach(efx
->net_dev
);
4924 #ifdef CONFIG_SFC_SRIOV
4925 if (efx
->pci_dev
->is_virtfn
&& efx
->pci_dev
->physfn
) {
4926 struct pci_dev
*pci_dev_pf
= efx
->pci_dev
->physfn
;
4929 struct efx_nic
*efx_pf
;
4931 /* Switch to PF and change MAC address on vport */
4932 efx_pf
= pci_get_drvdata(pci_dev_pf
);
4934 rc
= efx_ef10_sriov_set_vf_mac(efx_pf
,
4936 efx
->net_dev
->dev_addr
);
4938 struct efx_nic
*efx_pf
= pci_get_drvdata(pci_dev_pf
);
4939 struct efx_ef10_nic_data
*nic_data
= efx_pf
->nic_data
;
4942 /* MAC address successfully changed by VF (with MAC
4943 * spoofing) so update the parent PF if possible.
4945 for (i
= 0; i
< efx_pf
->vf_count
; ++i
) {
4946 struct ef10_vf
*vf
= nic_data
->vf
+ i
;
4948 if (vf
->efx
== efx
) {
4949 ether_addr_copy(vf
->mac
,
4950 efx
->net_dev
->dev_addr
);
4958 netif_err(efx
, drv
, efx
->net_dev
,
4959 "Cannot change MAC address; use sfboot to enable"
4960 " mac-spoofing on this interface\n");
4961 } else if (rc
== -ENOSYS
&& !efx_ef10_is_vf(efx
)) {
4962 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4963 * fall-back to the method of changing the MAC address on the
4964 * vport. This only applies to PFs because such versions of
4965 * MCFW do not support VFs.
4967 rc
= efx_ef10_vport_set_mac_address(efx
);
4969 efx_mcdi_display_error(efx
, MC_CMD_VADAPTOR_SET_MAC
,
4970 sizeof(inbuf
), NULL
, 0, rc
);
4976 static int efx_ef10_mac_reconfigure(struct efx_nic
*efx
)
4978 efx_ef10_filter_sync_rx_mode(efx
);
4980 return efx_mcdi_set_mac(efx
);
4983 static int efx_ef10_mac_reconfigure_vf(struct efx_nic
*efx
)
4985 efx_ef10_filter_sync_rx_mode(efx
);
4990 static int efx_ef10_start_bist(struct efx_nic
*efx
, u32 bist_type
)
4992 MCDI_DECLARE_BUF(inbuf
, MC_CMD_START_BIST_IN_LEN
);
4994 MCDI_SET_DWORD(inbuf
, START_BIST_IN_TYPE
, bist_type
);
4995 return efx_mcdi_rpc(efx
, MC_CMD_START_BIST
, inbuf
, sizeof(inbuf
),
4999 /* MC BISTs follow a different poll mechanism to phy BISTs.
5000 * The BIST is done in the poll handler on the MC, and the MCDI command
5001 * will block until the BIST is done.
5003 static int efx_ef10_poll_bist(struct efx_nic
*efx
)
5006 MCDI_DECLARE_BUF(outbuf
, MC_CMD_POLL_BIST_OUT_LEN
);
5010 rc
= efx_mcdi_rpc(efx
, MC_CMD_POLL_BIST
, NULL
, 0,
5011 outbuf
, sizeof(outbuf
), &outlen
);
5015 if (outlen
< MC_CMD_POLL_BIST_OUT_LEN
)
5018 result
= MCDI_DWORD(outbuf
, POLL_BIST_OUT_RESULT
);
5020 case MC_CMD_POLL_BIST_PASSED
:
5021 netif_dbg(efx
, hw
, efx
->net_dev
, "BIST passed.\n");
5023 case MC_CMD_POLL_BIST_TIMEOUT
:
5024 netif_err(efx
, hw
, efx
->net_dev
, "BIST timed out\n");
5026 case MC_CMD_POLL_BIST_FAILED
:
5027 netif_err(efx
, hw
, efx
->net_dev
, "BIST failed.\n");
5030 netif_err(efx
, hw
, efx
->net_dev
,
5031 "BIST returned unknown result %u", result
);
5036 static int efx_ef10_run_bist(struct efx_nic
*efx
, u32 bist_type
)
5040 netif_dbg(efx
, drv
, efx
->net_dev
, "starting BIST type %u\n", bist_type
);
5042 rc
= efx_ef10_start_bist(efx
, bist_type
);
5046 return efx_ef10_poll_bist(efx
);
5050 efx_ef10_test_chip(struct efx_nic
*efx
, struct efx_self_tests
*tests
)
5054 efx_reset_down(efx
, RESET_TYPE_WORLD
);
5056 rc
= efx_mcdi_rpc(efx
, MC_CMD_ENABLE_OFFLINE_BIST
,
5057 NULL
, 0, NULL
, 0, NULL
);
5061 tests
->memory
= efx_ef10_run_bist(efx
, MC_CMD_MC_MEM_BIST
) ? -1 : 1;
5062 tests
->registers
= efx_ef10_run_bist(efx
, MC_CMD_REG_BIST
) ? -1 : 1;
5064 rc
= efx_mcdi_reset(efx
, RESET_TYPE_WORLD
);
5069 rc2
= efx_reset_up(efx
, RESET_TYPE_WORLD
, rc
== 0);
5070 return rc
? rc
: rc2
;
5073 #ifdef CONFIG_SFC_MTD
5075 struct efx_ef10_nvram_type_info
{
5076 u16 type
, type_mask
;
5081 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types
[] = {
5082 { NVRAM_PARTITION_TYPE_MC_FIRMWARE
, 0, 0, "sfc_mcfw" },
5083 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP
, 0, 0, "sfc_mcfw_backup" },
5084 { NVRAM_PARTITION_TYPE_EXPANSION_ROM
, 0, 0, "sfc_exp_rom" },
5085 { NVRAM_PARTITION_TYPE_STATIC_CONFIG
, 0, 0, "sfc_static_cfg" },
5086 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG
, 0, 0, "sfc_dynamic_cfg" },
5087 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0
, 0, 0, "sfc_exp_rom_cfg" },
5088 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1
, 0, 1, "sfc_exp_rom_cfg" },
5089 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2
, 0, 2, "sfc_exp_rom_cfg" },
5090 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3
, 0, 3, "sfc_exp_rom_cfg" },
5091 { NVRAM_PARTITION_TYPE_LICENSE
, 0, 0, "sfc_license" },
5092 { NVRAM_PARTITION_TYPE_PHY_MIN
, 0xff, 0, "sfc_phy_fw" },
5095 static int efx_ef10_mtd_probe_partition(struct efx_nic
*efx
,
5096 struct efx_mcdi_mtd_partition
*part
,
5099 MCDI_DECLARE_BUF(inbuf
, MC_CMD_NVRAM_METADATA_IN_LEN
);
5100 MCDI_DECLARE_BUF(outbuf
, MC_CMD_NVRAM_METADATA_OUT_LENMAX
);
5101 const struct efx_ef10_nvram_type_info
*info
;
5102 size_t size
, erase_size
, outlen
;
5106 for (info
= efx_ef10_nvram_types
; ; info
++) {
5108 efx_ef10_nvram_types
+ ARRAY_SIZE(efx_ef10_nvram_types
))
5110 if ((type
& ~info
->type_mask
) == info
->type
)
5113 if (info
->port
!= efx_port_num(efx
))
5116 rc
= efx_mcdi_nvram_info(efx
, type
, &size
, &erase_size
, &protected);
5120 return -ENODEV
; /* hide it */
5122 part
->nvram_type
= type
;
5124 MCDI_SET_DWORD(inbuf
, NVRAM_METADATA_IN_TYPE
, type
);
5125 rc
= efx_mcdi_rpc(efx
, MC_CMD_NVRAM_METADATA
, inbuf
, sizeof(inbuf
),
5126 outbuf
, sizeof(outbuf
), &outlen
);
5129 if (outlen
< MC_CMD_NVRAM_METADATA_OUT_LENMIN
)
5131 if (MCDI_DWORD(outbuf
, NVRAM_METADATA_OUT_FLAGS
) &
5132 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN
))
5133 part
->fw_subtype
= MCDI_DWORD(outbuf
,
5134 NVRAM_METADATA_OUT_SUBTYPE
);
5136 part
->common
.dev_type_name
= "EF10 NVRAM manager";
5137 part
->common
.type_name
= info
->name
;
5139 part
->common
.mtd
.type
= MTD_NORFLASH
;
5140 part
->common
.mtd
.flags
= MTD_CAP_NORFLASH
;
5141 part
->common
.mtd
.size
= size
;
5142 part
->common
.mtd
.erasesize
= erase_size
;
5147 static int efx_ef10_mtd_probe(struct efx_nic
*efx
)
5149 MCDI_DECLARE_BUF(outbuf
, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX
);
5150 struct efx_mcdi_mtd_partition
*parts
;
5151 size_t outlen
, n_parts_total
, i
, n_parts
;
5157 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN
!= 0);
5158 rc
= efx_mcdi_rpc(efx
, MC_CMD_NVRAM_PARTITIONS
, NULL
, 0,
5159 outbuf
, sizeof(outbuf
), &outlen
);
5162 if (outlen
< MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN
)
5165 n_parts_total
= MCDI_DWORD(outbuf
, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS
);
5167 MCDI_VAR_ARRAY_LEN(outlen
, NVRAM_PARTITIONS_OUT_TYPE_ID
))
5170 parts
= kcalloc(n_parts_total
, sizeof(*parts
), GFP_KERNEL
);
5175 for (i
= 0; i
< n_parts_total
; i
++) {
5176 type
= MCDI_ARRAY_DWORD(outbuf
, NVRAM_PARTITIONS_OUT_TYPE_ID
,
5178 rc
= efx_ef10_mtd_probe_partition(efx
, &parts
[n_parts
], type
);
5181 else if (rc
!= -ENODEV
)
5185 rc
= efx_mtd_add(efx
, &parts
[0].common
, n_parts
, sizeof(*parts
));
5192 #endif /* CONFIG_SFC_MTD */
5194 static void efx_ef10_ptp_write_host_time(struct efx_nic
*efx
, u32 host_time
)
5196 _efx_writed(efx
, cpu_to_le32(host_time
), ER_DZ_MC_DB_LWRD
);
5199 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic
*efx
,
5202 static int efx_ef10_rx_enable_timestamping(struct efx_channel
*channel
,
5205 MCDI_DECLARE_BUF(inbuf
, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN
);
5208 if (channel
->sync_events_state
== SYNC_EVENTS_REQUESTED
||
5209 channel
->sync_events_state
== SYNC_EVENTS_VALID
||
5210 (temp
&& channel
->sync_events_state
== SYNC_EVENTS_DISABLED
))
5212 channel
->sync_events_state
= SYNC_EVENTS_REQUESTED
;
5214 MCDI_SET_DWORD(inbuf
, PTP_IN_OP
, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE
);
5215 MCDI_SET_DWORD(inbuf
, PTP_IN_PERIPH_ID
, 0);
5216 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE
,
5219 rc
= efx_mcdi_rpc(channel
->efx
, MC_CMD_PTP
,
5220 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
5223 channel
->sync_events_state
= temp
? SYNC_EVENTS_QUIESCENT
:
5224 SYNC_EVENTS_DISABLED
;
5229 static int efx_ef10_rx_disable_timestamping(struct efx_channel
*channel
,
5232 MCDI_DECLARE_BUF(inbuf
, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN
);
5235 if (channel
->sync_events_state
== SYNC_EVENTS_DISABLED
||
5236 (temp
&& channel
->sync_events_state
== SYNC_EVENTS_QUIESCENT
))
5238 if (channel
->sync_events_state
== SYNC_EVENTS_QUIESCENT
) {
5239 channel
->sync_events_state
= SYNC_EVENTS_DISABLED
;
5242 channel
->sync_events_state
= temp
? SYNC_EVENTS_QUIESCENT
:
5243 SYNC_EVENTS_DISABLED
;
5245 MCDI_SET_DWORD(inbuf
, PTP_IN_OP
, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE
);
5246 MCDI_SET_DWORD(inbuf
, PTP_IN_PERIPH_ID
, 0);
5247 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL
,
5248 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE
);
5249 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE
,
5252 rc
= efx_mcdi_rpc(channel
->efx
, MC_CMD_PTP
,
5253 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
5258 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic
*efx
, bool en
,
5261 int (*set
)(struct efx_channel
*channel
, bool temp
);
5262 struct efx_channel
*channel
;
5265 efx_ef10_rx_enable_timestamping
:
5266 efx_ef10_rx_disable_timestamping
;
5268 efx_for_each_channel(channel
, efx
) {
5269 int rc
= set(channel
, temp
);
5270 if (en
&& rc
!= 0) {
5271 efx_ef10_ptp_set_ts_sync_events(efx
, false, temp
);
5279 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic
*efx
,
5280 struct hwtstamp_config
*init
)
5285 static int efx_ef10_ptp_set_ts_config(struct efx_nic
*efx
,
5286 struct hwtstamp_config
*init
)
5290 switch (init
->rx_filter
) {
5291 case HWTSTAMP_FILTER_NONE
:
5292 efx_ef10_ptp_set_ts_sync_events(efx
, false, false);
5293 /* if TX timestamping is still requested then leave PTP on */
5294 return efx_ptp_change_mode(efx
,
5295 init
->tx_type
!= HWTSTAMP_TX_OFF
, 0);
5296 case HWTSTAMP_FILTER_ALL
:
5297 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
5298 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
5299 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
5300 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
5301 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
5302 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
5303 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
5304 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
5305 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
5306 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
5307 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
5308 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
5309 init
->rx_filter
= HWTSTAMP_FILTER_ALL
;
5310 rc
= efx_ptp_change_mode(efx
, true, 0);
5312 rc
= efx_ef10_ptp_set_ts_sync_events(efx
, true, false);
5314 efx_ptp_change_mode(efx
, false, 0);
5321 static int efx_ef10_vlan_rx_add_vid(struct efx_nic
*efx
, __be16 proto
, u16 vid
)
5323 if (proto
!= htons(ETH_P_8021Q
))
5326 return efx_ef10_add_vlan(efx
, vid
);
5329 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic
*efx
, __be16 proto
, u16 vid
)
5331 if (proto
!= htons(ETH_P_8021Q
))
5334 return efx_ef10_del_vlan(efx
, vid
);
5337 #define EF10_OFFLOAD_FEATURES \
5338 (NETIF_F_IP_CSUM | \
5339 NETIF_F_HW_VLAN_CTAG_FILTER | \
5340 NETIF_F_IPV6_CSUM | \
5344 const struct efx_nic_type efx_hunt_a0_vf_nic_type
= {
5346 .mem_bar
= EFX_MEM_VF_BAR
,
5347 .mem_map_size
= efx_ef10_mem_map_size
,
5348 .probe
= efx_ef10_probe_vf
,
5349 .remove
= efx_ef10_remove
,
5350 .dimension_resources
= efx_ef10_dimension_resources
,
5351 .init
= efx_ef10_init_nic
,
5352 .fini
= efx_port_dummy_op_void
,
5353 .map_reset_reason
= efx_ef10_map_reset_reason
,
5354 .map_reset_flags
= efx_ef10_map_reset_flags
,
5355 .reset
= efx_ef10_reset
,
5356 .probe_port
= efx_mcdi_port_probe
,
5357 .remove_port
= efx_mcdi_port_remove
,
5358 .fini_dmaq
= efx_ef10_fini_dmaq
,
5359 .prepare_flr
= efx_ef10_prepare_flr
,
5360 .finish_flr
= efx_port_dummy_op_void
,
5361 .describe_stats
= efx_ef10_describe_stats
,
5362 .update_stats
= efx_ef10_update_stats_vf
,
5363 .start_stats
= efx_port_dummy_op_void
,
5364 .pull_stats
= efx_port_dummy_op_void
,
5365 .stop_stats
= efx_port_dummy_op_void
,
5366 .set_id_led
= efx_mcdi_set_id_led
,
5367 .push_irq_moderation
= efx_ef10_push_irq_moderation
,
5368 .reconfigure_mac
= efx_ef10_mac_reconfigure_vf
,
5369 .check_mac_fault
= efx_mcdi_mac_check_fault
,
5370 .reconfigure_port
= efx_mcdi_port_reconfigure
,
5371 .get_wol
= efx_ef10_get_wol_vf
,
5372 .set_wol
= efx_ef10_set_wol_vf
,
5373 .resume_wol
= efx_port_dummy_op_void
,
5374 .mcdi_request
= efx_ef10_mcdi_request
,
5375 .mcdi_poll_response
= efx_ef10_mcdi_poll_response
,
5376 .mcdi_read_response
= efx_ef10_mcdi_read_response
,
5377 .mcdi_poll_reboot
= efx_ef10_mcdi_poll_reboot
,
5378 .mcdi_reboot_detected
= efx_ef10_mcdi_reboot_detected
,
5379 .irq_enable_master
= efx_port_dummy_op_void
,
5380 .irq_test_generate
= efx_ef10_irq_test_generate
,
5381 .irq_disable_non_ev
= efx_port_dummy_op_void
,
5382 .irq_handle_msi
= efx_ef10_msi_interrupt
,
5383 .irq_handle_legacy
= efx_ef10_legacy_interrupt
,
5384 .tx_probe
= efx_ef10_tx_probe
,
5385 .tx_init
= efx_ef10_tx_init
,
5386 .tx_remove
= efx_ef10_tx_remove
,
5387 .tx_write
= efx_ef10_tx_write
,
5388 .rx_push_rss_config
= efx_ef10_vf_rx_push_rss_config
,
5389 .rx_probe
= efx_ef10_rx_probe
,
5390 .rx_init
= efx_ef10_rx_init
,
5391 .rx_remove
= efx_ef10_rx_remove
,
5392 .rx_write
= efx_ef10_rx_write
,
5393 .rx_defer_refill
= efx_ef10_rx_defer_refill
,
5394 .ev_probe
= efx_ef10_ev_probe
,
5395 .ev_init
= efx_ef10_ev_init
,
5396 .ev_fini
= efx_ef10_ev_fini
,
5397 .ev_remove
= efx_ef10_ev_remove
,
5398 .ev_process
= efx_ef10_ev_process
,
5399 .ev_read_ack
= efx_ef10_ev_read_ack
,
5400 .ev_test_generate
= efx_ef10_ev_test_generate
,
5401 .filter_table_probe
= efx_ef10_filter_table_probe
,
5402 .filter_table_restore
= efx_ef10_filter_table_restore
,
5403 .filter_table_remove
= efx_ef10_filter_table_remove
,
5404 .filter_update_rx_scatter
= efx_ef10_filter_update_rx_scatter
,
5405 .filter_insert
= efx_ef10_filter_insert
,
5406 .filter_remove_safe
= efx_ef10_filter_remove_safe
,
5407 .filter_get_safe
= efx_ef10_filter_get_safe
,
5408 .filter_clear_rx
= efx_ef10_filter_clear_rx
,
5409 .filter_count_rx_used
= efx_ef10_filter_count_rx_used
,
5410 .filter_get_rx_id_limit
= efx_ef10_filter_get_rx_id_limit
,
5411 .filter_get_rx_ids
= efx_ef10_filter_get_rx_ids
,
5412 #ifdef CONFIG_RFS_ACCEL
5413 .filter_rfs_insert
= efx_ef10_filter_rfs_insert
,
5414 .filter_rfs_expire_one
= efx_ef10_filter_rfs_expire_one
,
5416 #ifdef CONFIG_SFC_MTD
5417 .mtd_probe
= efx_port_dummy_op_int
,
5419 .ptp_write_host_time
= efx_ef10_ptp_write_host_time_vf
,
5420 .ptp_set_ts_config
= efx_ef10_ptp_set_ts_config_vf
,
5421 .vlan_rx_add_vid
= efx_ef10_vlan_rx_add_vid
,
5422 .vlan_rx_kill_vid
= efx_ef10_vlan_rx_kill_vid
,
5423 #ifdef CONFIG_SFC_SRIOV
5424 .vswitching_probe
= efx_ef10_vswitching_probe_vf
,
5425 .vswitching_restore
= efx_ef10_vswitching_restore_vf
,
5426 .vswitching_remove
= efx_ef10_vswitching_remove_vf
,
5427 .sriov_get_phys_port_id
= efx_ef10_sriov_get_phys_port_id
,
5429 .get_mac_address
= efx_ef10_get_mac_address_vf
,
5430 .set_mac_address
= efx_ef10_set_mac_address
,
5432 .revision
= EFX_REV_HUNT_A0
,
5433 .max_dma_mask
= DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH
),
5434 .rx_prefix_size
= ES_DZ_RX_PREFIX_SIZE
,
5435 .rx_hash_offset
= ES_DZ_RX_PREFIX_HASH_OFST
,
5436 .rx_ts_offset
= ES_DZ_RX_PREFIX_TSTAMP_OFST
,
5437 .can_rx_scatter
= true,
5438 .always_rx_scatter
= true,
5439 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
5440 .timer_period_max
= 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH
,
5441 .offload_features
= EF10_OFFLOAD_FEATURES
,
5443 .max_rx_ip_filters
= HUNT_FILTER_TBL_ROWS
,
5444 .hwtstamp_filters
= 1 << HWTSTAMP_FILTER_NONE
|
5445 1 << HWTSTAMP_FILTER_ALL
,
5448 const struct efx_nic_type efx_hunt_a0_nic_type
= {
5450 .mem_bar
= EFX_MEM_BAR
,
5451 .mem_map_size
= efx_ef10_mem_map_size
,
5452 .probe
= efx_ef10_probe_pf
,
5453 .remove
= efx_ef10_remove
,
5454 .dimension_resources
= efx_ef10_dimension_resources
,
5455 .init
= efx_ef10_init_nic
,
5456 .fini
= efx_port_dummy_op_void
,
5457 .map_reset_reason
= efx_ef10_map_reset_reason
,
5458 .map_reset_flags
= efx_ef10_map_reset_flags
,
5459 .reset
= efx_ef10_reset
,
5460 .probe_port
= efx_mcdi_port_probe
,
5461 .remove_port
= efx_mcdi_port_remove
,
5462 .fini_dmaq
= efx_ef10_fini_dmaq
,
5463 .prepare_flr
= efx_ef10_prepare_flr
,
5464 .finish_flr
= efx_port_dummy_op_void
,
5465 .describe_stats
= efx_ef10_describe_stats
,
5466 .update_stats
= efx_ef10_update_stats_pf
,
5467 .start_stats
= efx_mcdi_mac_start_stats
,
5468 .pull_stats
= efx_mcdi_mac_pull_stats
,
5469 .stop_stats
= efx_mcdi_mac_stop_stats
,
5470 .set_id_led
= efx_mcdi_set_id_led
,
5471 .push_irq_moderation
= efx_ef10_push_irq_moderation
,
5472 .reconfigure_mac
= efx_ef10_mac_reconfigure
,
5473 .check_mac_fault
= efx_mcdi_mac_check_fault
,
5474 .reconfigure_port
= efx_mcdi_port_reconfigure
,
5475 .get_wol
= efx_ef10_get_wol
,
5476 .set_wol
= efx_ef10_set_wol
,
5477 .resume_wol
= efx_port_dummy_op_void
,
5478 .test_chip
= efx_ef10_test_chip
,
5479 .test_nvram
= efx_mcdi_nvram_test_all
,
5480 .mcdi_request
= efx_ef10_mcdi_request
,
5481 .mcdi_poll_response
= efx_ef10_mcdi_poll_response
,
5482 .mcdi_read_response
= efx_ef10_mcdi_read_response
,
5483 .mcdi_poll_reboot
= efx_ef10_mcdi_poll_reboot
,
5484 .mcdi_reboot_detected
= efx_ef10_mcdi_reboot_detected
,
5485 .irq_enable_master
= efx_port_dummy_op_void
,
5486 .irq_test_generate
= efx_ef10_irq_test_generate
,
5487 .irq_disable_non_ev
= efx_port_dummy_op_void
,
5488 .irq_handle_msi
= efx_ef10_msi_interrupt
,
5489 .irq_handle_legacy
= efx_ef10_legacy_interrupt
,
5490 .tx_probe
= efx_ef10_tx_probe
,
5491 .tx_init
= efx_ef10_tx_init
,
5492 .tx_remove
= efx_ef10_tx_remove
,
5493 .tx_write
= efx_ef10_tx_write
,
5494 .rx_push_rss_config
= efx_ef10_pf_rx_push_rss_config
,
5495 .rx_probe
= efx_ef10_rx_probe
,
5496 .rx_init
= efx_ef10_rx_init
,
5497 .rx_remove
= efx_ef10_rx_remove
,
5498 .rx_write
= efx_ef10_rx_write
,
5499 .rx_defer_refill
= efx_ef10_rx_defer_refill
,
5500 .ev_probe
= efx_ef10_ev_probe
,
5501 .ev_init
= efx_ef10_ev_init
,
5502 .ev_fini
= efx_ef10_ev_fini
,
5503 .ev_remove
= efx_ef10_ev_remove
,
5504 .ev_process
= efx_ef10_ev_process
,
5505 .ev_read_ack
= efx_ef10_ev_read_ack
,
5506 .ev_test_generate
= efx_ef10_ev_test_generate
,
5507 .filter_table_probe
= efx_ef10_filter_table_probe
,
5508 .filter_table_restore
= efx_ef10_filter_table_restore
,
5509 .filter_table_remove
= efx_ef10_filter_table_remove
,
5510 .filter_update_rx_scatter
= efx_ef10_filter_update_rx_scatter
,
5511 .filter_insert
= efx_ef10_filter_insert
,
5512 .filter_remove_safe
= efx_ef10_filter_remove_safe
,
5513 .filter_get_safe
= efx_ef10_filter_get_safe
,
5514 .filter_clear_rx
= efx_ef10_filter_clear_rx
,
5515 .filter_count_rx_used
= efx_ef10_filter_count_rx_used
,
5516 .filter_get_rx_id_limit
= efx_ef10_filter_get_rx_id_limit
,
5517 .filter_get_rx_ids
= efx_ef10_filter_get_rx_ids
,
5518 #ifdef CONFIG_RFS_ACCEL
5519 .filter_rfs_insert
= efx_ef10_filter_rfs_insert
,
5520 .filter_rfs_expire_one
= efx_ef10_filter_rfs_expire_one
,
5522 #ifdef CONFIG_SFC_MTD
5523 .mtd_probe
= efx_ef10_mtd_probe
,
5524 .mtd_rename
= efx_mcdi_mtd_rename
,
5525 .mtd_read
= efx_mcdi_mtd_read
,
5526 .mtd_erase
= efx_mcdi_mtd_erase
,
5527 .mtd_write
= efx_mcdi_mtd_write
,
5528 .mtd_sync
= efx_mcdi_mtd_sync
,
5530 .ptp_write_host_time
= efx_ef10_ptp_write_host_time
,
5531 .ptp_set_ts_sync_events
= efx_ef10_ptp_set_ts_sync_events
,
5532 .ptp_set_ts_config
= efx_ef10_ptp_set_ts_config
,
5533 .vlan_rx_add_vid
= efx_ef10_vlan_rx_add_vid
,
5534 .vlan_rx_kill_vid
= efx_ef10_vlan_rx_kill_vid
,
5535 #ifdef CONFIG_SFC_SRIOV
5536 .sriov_configure
= efx_ef10_sriov_configure
,
5537 .sriov_init
= efx_ef10_sriov_init
,
5538 .sriov_fini
= efx_ef10_sriov_fini
,
5539 .sriov_wanted
= efx_ef10_sriov_wanted
,
5540 .sriov_reset
= efx_ef10_sriov_reset
,
5541 .sriov_flr
= efx_ef10_sriov_flr
,
5542 .sriov_set_vf_mac
= efx_ef10_sriov_set_vf_mac
,
5543 .sriov_set_vf_vlan
= efx_ef10_sriov_set_vf_vlan
,
5544 .sriov_set_vf_spoofchk
= efx_ef10_sriov_set_vf_spoofchk
,
5545 .sriov_get_vf_config
= efx_ef10_sriov_get_vf_config
,
5546 .sriov_set_vf_link_state
= efx_ef10_sriov_set_vf_link_state
,
5547 .vswitching_probe
= efx_ef10_vswitching_probe_pf
,
5548 .vswitching_restore
= efx_ef10_vswitching_restore_pf
,
5549 .vswitching_remove
= efx_ef10_vswitching_remove_pf
,
5551 .get_mac_address
= efx_ef10_get_mac_address_pf
,
5552 .set_mac_address
= efx_ef10_set_mac_address
,
5554 .revision
= EFX_REV_HUNT_A0
,
5555 .max_dma_mask
= DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH
),
5556 .rx_prefix_size
= ES_DZ_RX_PREFIX_SIZE
,
5557 .rx_hash_offset
= ES_DZ_RX_PREFIX_HASH_OFST
,
5558 .rx_ts_offset
= ES_DZ_RX_PREFIX_TSTAMP_OFST
,
5559 .can_rx_scatter
= true,
5560 .always_rx_scatter
= true,
5561 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
5562 .timer_period_max
= 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH
,
5563 .offload_features
= EF10_OFFLOAD_FEATURES
,
5565 .max_rx_ip_filters
= HUNT_FILTER_TBL_ROWS
,
5566 .hwtstamp_filters
= 1 << HWTSTAMP_FILTER_NONE
|
5567 1 << HWTSTAMP_FILTER_ALL
,