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Merge tag 'seccomp-v4.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/kees...
[deliverable/linux.git] / drivers / net / ethernet / sfc / ef10.c
1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10 #include "net_driver.h"
11 #include "ef10_regs.h"
12 #include "io.h"
13 #include "mcdi.h"
14 #include "mcdi_pcol.h"
15 #include "nic.h"
16 #include "workarounds.h"
17 #include "selftest.h"
18 #include "ef10_sriov.h"
19 #include <linux/in.h>
20 #include <linux/jhash.h>
21 #include <linux/wait.h>
22 #include <linux/workqueue.h>
23
24 /* Hardware control for EF10 architecture including 'Huntington'. */
25
26 #define EFX_EF10_DRVGEN_EV 7
27 enum {
28 EFX_EF10_TEST = 1,
29 EFX_EF10_REFILL,
30 };
31
32 /* The reserved RSS context value */
33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
34 /* The maximum size of a shared RSS context */
35 /* TODO: this should really be from the mcdi protocol export */
36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
37
38 /* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
45 * table.
46 *
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
49 */
50 #define HUNT_FILTER_TBL_ROWS 8192
51
52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
53
54 #define EFX_EF10_FILTER_DEV_UC_MAX 32
55 #define EFX_EF10_FILTER_DEV_MC_MAX 256
56
57 /* VLAN list entry */
58 struct efx_ef10_vlan {
59 struct list_head list;
60 u16 vid;
61 };
62
63 /* Per-VLAN filters information */
64 struct efx_ef10_filter_vlan {
65 struct list_head list;
66 u16 vid;
67 u16 uc[EFX_EF10_FILTER_DEV_UC_MAX];
68 u16 mc[EFX_EF10_FILTER_DEV_MC_MAX];
69 u16 ucdef;
70 u16 bcast;
71 u16 mcdef;
72 };
73
74 struct efx_ef10_dev_addr {
75 u8 addr[ETH_ALEN];
76 };
77
78 struct efx_ef10_filter_table {
79 /* The MCDI match masks supported by this fw & hw, in order of priority */
80 u32 rx_match_mcdi_flags[
81 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM];
82 unsigned int rx_match_count;
83
84 struct {
85 unsigned long spec; /* pointer to spec plus flag bits */
86 /* BUSY flag indicates that an update is in progress. AUTO_OLD is
87 * used to mark and sweep MAC filters for the device address lists.
88 */
89 #define EFX_EF10_FILTER_FLAG_BUSY 1UL
90 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
91 #define EFX_EF10_FILTER_FLAGS 3UL
92 u64 handle; /* firmware handle */
93 } *entry;
94 wait_queue_head_t waitq;
95 /* Shadow of net_device address lists, guarded by mac_lock */
96 struct efx_ef10_dev_addr dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX];
97 struct efx_ef10_dev_addr dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX];
98 int dev_uc_count;
99 int dev_mc_count;
100 bool uc_promisc;
101 bool mc_promisc;
102 /* Whether in multicast promiscuous mode when last changed */
103 bool mc_promisc_last;
104 bool vlan_filter;
105 struct list_head vlan_list;
106 };
107
108 /* An arbitrary search limit for the software hash table */
109 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
110
111 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx);
112 static void efx_ef10_filter_table_remove(struct efx_nic *efx);
113 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid);
114 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
115 struct efx_ef10_filter_vlan *vlan);
116 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid);
117
118 static int efx_ef10_get_warm_boot_count(struct efx_nic *efx)
119 {
120 efx_dword_t reg;
121
122 efx_readd(efx, &reg, ER_DZ_BIU_MC_SFT_STATUS);
123 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ?
124 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO;
125 }
126
127 static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx)
128 {
129 int bar;
130
131 bar = efx->type->mem_bar;
132 return resource_size(&efx->pci_dev->resource[bar]);
133 }
134
135 static bool efx_ef10_is_vf(struct efx_nic *efx)
136 {
137 return efx->type->is_vf;
138 }
139
140 static int efx_ef10_get_pf_index(struct efx_nic *efx)
141 {
142 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
143 struct efx_ef10_nic_data *nic_data = efx->nic_data;
144 size_t outlen;
145 int rc;
146
147 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
148 sizeof(outbuf), &outlen);
149 if (rc)
150 return rc;
151 if (outlen < sizeof(outbuf))
152 return -EIO;
153
154 nic_data->pf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_PF);
155 return 0;
156 }
157
158 #ifdef CONFIG_SFC_SRIOV
159 static int efx_ef10_get_vf_index(struct efx_nic *efx)
160 {
161 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_FUNCTION_INFO_OUT_LEN);
162 struct efx_ef10_nic_data *nic_data = efx->nic_data;
163 size_t outlen;
164 int rc;
165
166 rc = efx_mcdi_rpc(efx, MC_CMD_GET_FUNCTION_INFO, NULL, 0, outbuf,
167 sizeof(outbuf), &outlen);
168 if (rc)
169 return rc;
170 if (outlen < sizeof(outbuf))
171 return -EIO;
172
173 nic_data->vf_index = MCDI_DWORD(outbuf, GET_FUNCTION_INFO_OUT_VF);
174 return 0;
175 }
176 #endif
177
178 static int efx_ef10_init_datapath_caps(struct efx_nic *efx)
179 {
180 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN);
181 struct efx_ef10_nic_data *nic_data = efx->nic_data;
182 size_t outlen;
183 int rc;
184
185 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0);
186
187 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0,
188 outbuf, sizeof(outbuf), &outlen);
189 if (rc)
190 return rc;
191 if (outlen < sizeof(outbuf)) {
192 netif_err(efx, drv, efx->net_dev,
193 "unable to read datapath firmware capabilities\n");
194 return -EIO;
195 }
196
197 nic_data->datapath_caps =
198 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1);
199
200 /* record the DPCPU firmware IDs to determine VEB vswitching support.
201 */
202 nic_data->rx_dpcpu_fw_id =
203 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID);
204 nic_data->tx_dpcpu_fw_id =
205 MCDI_WORD(outbuf, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID);
206
207 if (!(nic_data->datapath_caps &
208 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) {
209 netif_err(efx, probe, efx->net_dev,
210 "current firmware does not support an RX prefix\n");
211 return -ENODEV;
212 }
213
214 return 0;
215 }
216
217 static int efx_ef10_get_sysclk_freq(struct efx_nic *efx)
218 {
219 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN);
220 int rc;
221
222 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0,
223 outbuf, sizeof(outbuf), NULL);
224 if (rc)
225 return rc;
226 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ);
227 return rc > 0 ? rc : -ERANGE;
228 }
229
230 static int efx_ef10_get_mac_address_pf(struct efx_nic *efx, u8 *mac_address)
231 {
232 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN);
233 size_t outlen;
234 int rc;
235
236 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0);
237
238 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0,
239 outbuf, sizeof(outbuf), &outlen);
240 if (rc)
241 return rc;
242 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)
243 return -EIO;
244
245 ether_addr_copy(mac_address,
246 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE));
247 return 0;
248 }
249
250 static int efx_ef10_get_mac_address_vf(struct efx_nic *efx, u8 *mac_address)
251 {
252 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN);
253 MCDI_DECLARE_BUF(outbuf, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX);
254 size_t outlen;
255 int num_addrs, rc;
256
257 MCDI_SET_DWORD(inbuf, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
258 EVB_PORT_ID_ASSIGNED);
259 rc = efx_mcdi_rpc(efx, MC_CMD_VPORT_GET_MAC_ADDRESSES, inbuf,
260 sizeof(inbuf), outbuf, sizeof(outbuf), &outlen);
261
262 if (rc)
263 return rc;
264 if (outlen < MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN)
265 return -EIO;
266
267 num_addrs = MCDI_DWORD(outbuf,
268 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT);
269
270 WARN_ON(num_addrs != 1);
271
272 ether_addr_copy(mac_address,
273 MCDI_PTR(outbuf, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR));
274
275 return 0;
276 }
277
278 static ssize_t efx_ef10_show_link_control_flag(struct device *dev,
279 struct device_attribute *attr,
280 char *buf)
281 {
282 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
283
284 return sprintf(buf, "%d\n",
285 ((efx->mcdi->fn_flags) &
286 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
287 ? 1 : 0);
288 }
289
290 static ssize_t efx_ef10_show_primary_flag(struct device *dev,
291 struct device_attribute *attr,
292 char *buf)
293 {
294 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
295
296 return sprintf(buf, "%d\n",
297 ((efx->mcdi->fn_flags) &
298 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY))
299 ? 1 : 0);
300 }
301
302 static struct efx_ef10_vlan *efx_ef10_find_vlan(struct efx_nic *efx, u16 vid)
303 {
304 struct efx_ef10_nic_data *nic_data = efx->nic_data;
305 struct efx_ef10_vlan *vlan;
306
307 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
308
309 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
310 if (vlan->vid == vid)
311 return vlan;
312 }
313
314 return NULL;
315 }
316
317 static int efx_ef10_add_vlan(struct efx_nic *efx, u16 vid)
318 {
319 struct efx_ef10_nic_data *nic_data = efx->nic_data;
320 struct efx_ef10_vlan *vlan;
321 int rc;
322
323 mutex_lock(&nic_data->vlan_lock);
324
325 vlan = efx_ef10_find_vlan(efx, vid);
326 if (vlan) {
327 /* We add VID 0 on init. 8021q adds it on module init
328 * for all interfaces with VLAN filtring feature.
329 */
330 if (vid == 0)
331 goto done_unlock;
332 netif_warn(efx, drv, efx->net_dev,
333 "VLAN %u already added\n", vid);
334 rc = -EALREADY;
335 goto fail_exist;
336 }
337
338 rc = -ENOMEM;
339 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
340 if (!vlan)
341 goto fail_alloc;
342
343 vlan->vid = vid;
344
345 list_add_tail(&vlan->list, &nic_data->vlan_list);
346
347 if (efx->filter_state) {
348 mutex_lock(&efx->mac_lock);
349 down_write(&efx->filter_sem);
350 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
351 up_write(&efx->filter_sem);
352 mutex_unlock(&efx->mac_lock);
353 if (rc)
354 goto fail_filter_add_vlan;
355 }
356
357 done_unlock:
358 mutex_unlock(&nic_data->vlan_lock);
359 return 0;
360
361 fail_filter_add_vlan:
362 list_del(&vlan->list);
363 kfree(vlan);
364 fail_alloc:
365 fail_exist:
366 mutex_unlock(&nic_data->vlan_lock);
367 return rc;
368 }
369
370 static void efx_ef10_del_vlan_internal(struct efx_nic *efx,
371 struct efx_ef10_vlan *vlan)
372 {
373 struct efx_ef10_nic_data *nic_data = efx->nic_data;
374
375 WARN_ON(!mutex_is_locked(&nic_data->vlan_lock));
376
377 if (efx->filter_state) {
378 down_write(&efx->filter_sem);
379 efx_ef10_filter_del_vlan(efx, vlan->vid);
380 up_write(&efx->filter_sem);
381 }
382
383 list_del(&vlan->list);
384 kfree(vlan);
385 }
386
387 static int efx_ef10_del_vlan(struct efx_nic *efx, u16 vid)
388 {
389 struct efx_ef10_nic_data *nic_data = efx->nic_data;
390 struct efx_ef10_vlan *vlan;
391 int rc = 0;
392
393 /* 8021q removes VID 0 on module unload for all interfaces
394 * with VLAN filtering feature. We need to keep it to receive
395 * untagged traffic.
396 */
397 if (vid == 0)
398 return 0;
399
400 mutex_lock(&nic_data->vlan_lock);
401
402 vlan = efx_ef10_find_vlan(efx, vid);
403 if (!vlan) {
404 netif_err(efx, drv, efx->net_dev,
405 "VLAN %u to be deleted not found\n", vid);
406 rc = -ENOENT;
407 } else {
408 efx_ef10_del_vlan_internal(efx, vlan);
409 }
410
411 mutex_unlock(&nic_data->vlan_lock);
412
413 return rc;
414 }
415
416 static void efx_ef10_cleanup_vlans(struct efx_nic *efx)
417 {
418 struct efx_ef10_nic_data *nic_data = efx->nic_data;
419 struct efx_ef10_vlan *vlan, *next_vlan;
420
421 mutex_lock(&nic_data->vlan_lock);
422 list_for_each_entry_safe(vlan, next_vlan, &nic_data->vlan_list, list)
423 efx_ef10_del_vlan_internal(efx, vlan);
424 mutex_unlock(&nic_data->vlan_lock);
425 }
426
427 static DEVICE_ATTR(link_control_flag, 0444, efx_ef10_show_link_control_flag,
428 NULL);
429 static DEVICE_ATTR(primary_flag, 0444, efx_ef10_show_primary_flag, NULL);
430
431 static int efx_ef10_probe(struct efx_nic *efx)
432 {
433 struct efx_ef10_nic_data *nic_data;
434 struct net_device *net_dev = efx->net_dev;
435 int i, rc;
436
437 /* We can have one VI for each 8K region. However, until we
438 * use TX option descriptors we need two TX queues per channel.
439 */
440 efx->max_channels = min_t(unsigned int,
441 EFX_MAX_CHANNELS,
442 efx_ef10_mem_map_size(efx) /
443 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES));
444 efx->max_tx_channels = efx->max_channels;
445 if (WARN_ON(efx->max_channels == 0))
446 return -EIO;
447
448 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
449 if (!nic_data)
450 return -ENOMEM;
451 efx->nic_data = nic_data;
452
453 /* we assume later that we can copy from this buffer in dwords */
454 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2 % 4);
455
456 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf,
457 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL);
458 if (rc)
459 goto fail1;
460
461 /* Get the MC's warm boot count. In case it's rebooting right
462 * now, be prepared to retry.
463 */
464 i = 0;
465 for (;;) {
466 rc = efx_ef10_get_warm_boot_count(efx);
467 if (rc >= 0)
468 break;
469 if (++i == 5)
470 goto fail2;
471 ssleep(1);
472 }
473 nic_data->warm_boot_count = rc;
474
475 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
476
477 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
478
479 /* In case we're recovering from a crash (kexec), we want to
480 * cancel any outstanding request by the previous user of this
481 * function. We send a special message using the least
482 * significant bits of the 'high' (doorbell) register.
483 */
484 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD);
485
486 rc = efx_mcdi_init(efx);
487 if (rc)
488 goto fail2;
489
490 /* Reset (most) configuration for this function */
491 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
492 if (rc)
493 goto fail3;
494
495 /* Enable event logging */
496 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
497 if (rc)
498 goto fail3;
499
500 rc = device_create_file(&efx->pci_dev->dev,
501 &dev_attr_link_control_flag);
502 if (rc)
503 goto fail3;
504
505 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
506 if (rc)
507 goto fail4;
508
509 rc = efx_ef10_get_pf_index(efx);
510 if (rc)
511 goto fail5;
512
513 rc = efx_ef10_init_datapath_caps(efx);
514 if (rc < 0)
515 goto fail5;
516
517 efx->rx_packet_len_offset =
518 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE;
519
520 rc = efx_mcdi_port_get_number(efx);
521 if (rc < 0)
522 goto fail5;
523 efx->port_num = rc;
524 net_dev->dev_port = rc;
525
526 rc = efx->type->get_mac_address(efx, efx->net_dev->perm_addr);
527 if (rc)
528 goto fail5;
529
530 rc = efx_ef10_get_sysclk_freq(efx);
531 if (rc < 0)
532 goto fail5;
533 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */
534
535 /* Check whether firmware supports bug 35388 workaround.
536 * First try to enable it, then if we get EPERM, just
537 * ask if it's already enabled
538 */
539 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true, NULL);
540 if (rc == 0) {
541 nic_data->workaround_35388 = true;
542 } else if (rc == -EPERM) {
543 unsigned int enabled;
544
545 rc = efx_mcdi_get_workarounds(efx, NULL, &enabled);
546 if (rc)
547 goto fail3;
548 nic_data->workaround_35388 = enabled &
549 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388;
550 } else if (rc != -ENOSYS && rc != -ENOENT) {
551 goto fail5;
552 }
553 netif_dbg(efx, probe, efx->net_dev,
554 "workaround for bug 35388 is %sabled\n",
555 nic_data->workaround_35388 ? "en" : "dis");
556
557 rc = efx_mcdi_mon_probe(efx);
558 if (rc && rc != -EPERM)
559 goto fail5;
560
561 efx_ptp_probe(efx, NULL);
562
563 #ifdef CONFIG_SFC_SRIOV
564 if ((efx->pci_dev->physfn) && (!efx->pci_dev->is_physfn)) {
565 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
566 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
567
568 efx_pf->type->get_mac_address(efx_pf, nic_data->port_id);
569 } else
570 #endif
571 ether_addr_copy(nic_data->port_id, efx->net_dev->perm_addr);
572
573 INIT_LIST_HEAD(&nic_data->vlan_list);
574 mutex_init(&nic_data->vlan_lock);
575
576 /* Add unspecified VID to support VLAN filtering being disabled */
577 rc = efx_ef10_add_vlan(efx, EFX_FILTER_VID_UNSPEC);
578 if (rc)
579 goto fail_add_vid_unspec;
580
581 /* If VLAN filtering is enabled, we need VID 0 to get untagged
582 * traffic. It is added automatically if 8021q module is loaded,
583 * but we can't rely on it since module may be not loaded.
584 */
585 rc = efx_ef10_add_vlan(efx, 0);
586 if (rc)
587 goto fail_add_vid_0;
588
589 return 0;
590
591 fail_add_vid_0:
592 efx_ef10_cleanup_vlans(efx);
593 fail_add_vid_unspec:
594 mutex_destroy(&nic_data->vlan_lock);
595 efx_ptp_remove(efx);
596 efx_mcdi_mon_remove(efx);
597 fail5:
598 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
599 fail4:
600 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
601 fail3:
602 efx_mcdi_fini(efx);
603 fail2:
604 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
605 fail1:
606 kfree(nic_data);
607 efx->nic_data = NULL;
608 return rc;
609 }
610
611 static int efx_ef10_free_vis(struct efx_nic *efx)
612 {
613 MCDI_DECLARE_BUF_ERR(outbuf);
614 size_t outlen;
615 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0,
616 outbuf, sizeof(outbuf), &outlen);
617
618 /* -EALREADY means nothing to free, so ignore */
619 if (rc == -EALREADY)
620 rc = 0;
621 if (rc)
622 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen,
623 rc);
624 return rc;
625 }
626
627 #ifdef EFX_USE_PIO
628
629 static void efx_ef10_free_piobufs(struct efx_nic *efx)
630 {
631 struct efx_ef10_nic_data *nic_data = efx->nic_data;
632 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN);
633 unsigned int i;
634 int rc;
635
636 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0);
637
638 for (i = 0; i < nic_data->n_piobufs; i++) {
639 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE,
640 nic_data->piobuf_handle[i]);
641 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf),
642 NULL, 0, NULL);
643 WARN_ON(rc);
644 }
645
646 nic_data->n_piobufs = 0;
647 }
648
649 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
650 {
651 struct efx_ef10_nic_data *nic_data = efx->nic_data;
652 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN);
653 unsigned int i;
654 size_t outlen;
655 int rc = 0;
656
657 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0);
658
659 for (i = 0; i < n; i++) {
660 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0,
661 outbuf, sizeof(outbuf), &outlen);
662 if (rc) {
663 /* Don't display the MC error if we didn't have space
664 * for a VF.
665 */
666 if (!(efx_ef10_is_vf(efx) && rc == -ENOSPC))
667 efx_mcdi_display_error(efx, MC_CMD_ALLOC_PIOBUF,
668 0, outbuf, outlen, rc);
669 break;
670 }
671 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
672 rc = -EIO;
673 break;
674 }
675 nic_data->piobuf_handle[i] =
676 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
677 netif_dbg(efx, probe, efx->net_dev,
678 "allocated PIO buffer %u handle %x\n", i,
679 nic_data->piobuf_handle[i]);
680 }
681
682 nic_data->n_piobufs = i;
683 if (rc)
684 efx_ef10_free_piobufs(efx);
685 return rc;
686 }
687
688 static int efx_ef10_link_piobufs(struct efx_nic *efx)
689 {
690 struct efx_ef10_nic_data *nic_data = efx->nic_data;
691 _MCDI_DECLARE_BUF(inbuf,
692 max(MC_CMD_LINK_PIOBUF_IN_LEN,
693 MC_CMD_UNLINK_PIOBUF_IN_LEN));
694 struct efx_channel *channel;
695 struct efx_tx_queue *tx_queue;
696 unsigned int offset, index;
697 int rc;
698
699 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0);
700 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0);
701
702 memset(inbuf, 0, sizeof(inbuf));
703
704 /* Link a buffer to each VI in the write-combining mapping */
705 for (index = 0; index < nic_data->n_piobufs; ++index) {
706 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE,
707 nic_data->piobuf_handle[index]);
708 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE,
709 nic_data->pio_write_vi_base + index);
710 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
711 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
712 NULL, 0, NULL);
713 if (rc) {
714 netif_err(efx, drv, efx->net_dev,
715 "failed to link VI %u to PIO buffer %u (%d)\n",
716 nic_data->pio_write_vi_base + index, index,
717 rc);
718 goto fail;
719 }
720 netif_dbg(efx, probe, efx->net_dev,
721 "linked VI %u to PIO buffer %u\n",
722 nic_data->pio_write_vi_base + index, index);
723 }
724
725 /* Link a buffer to each TX queue */
726 efx_for_each_channel(channel, efx) {
727 efx_for_each_channel_tx_queue(tx_queue, channel) {
728 /* We assign the PIO buffers to queues in
729 * reverse order to allow for the following
730 * special case.
731 */
732 offset = ((efx->tx_channel_offset + efx->n_tx_channels -
733 tx_queue->channel->channel - 1) *
734 efx_piobuf_size);
735 index = offset / ER_DZ_TX_PIOBUF_SIZE;
736 offset = offset % ER_DZ_TX_PIOBUF_SIZE;
737
738 /* When the host page size is 4K, the first
739 * host page in the WC mapping may be within
740 * the same VI page as the last TX queue. We
741 * can only link one buffer to each VI.
742 */
743 if (tx_queue->queue == nic_data->pio_write_vi_base) {
744 BUG_ON(index != 0);
745 rc = 0;
746 } else {
747 MCDI_SET_DWORD(inbuf,
748 LINK_PIOBUF_IN_PIOBUF_HANDLE,
749 nic_data->piobuf_handle[index]);
750 MCDI_SET_DWORD(inbuf,
751 LINK_PIOBUF_IN_TXQ_INSTANCE,
752 tx_queue->queue);
753 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF,
754 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN,
755 NULL, 0, NULL);
756 }
757
758 if (rc) {
759 /* This is non-fatal; the TX path just
760 * won't use PIO for this queue
761 */
762 netif_err(efx, drv, efx->net_dev,
763 "failed to link VI %u to PIO buffer %u (%d)\n",
764 tx_queue->queue, index, rc);
765 tx_queue->piobuf = NULL;
766 } else {
767 tx_queue->piobuf =
768 nic_data->pio_write_base +
769 index * EFX_VI_PAGE_SIZE + offset;
770 tx_queue->piobuf_offset = offset;
771 netif_dbg(efx, probe, efx->net_dev,
772 "linked VI %u to PIO buffer %u offset %x addr %p\n",
773 tx_queue->queue, index,
774 tx_queue->piobuf_offset,
775 tx_queue->piobuf);
776 }
777 }
778 }
779
780 return 0;
781
782 fail:
783 while (index--) {
784 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE,
785 nic_data->pio_write_vi_base + index);
786 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF,
787 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN,
788 NULL, 0, NULL);
789 }
790 return rc;
791 }
792
793 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
794 {
795 struct efx_channel *channel;
796 struct efx_tx_queue *tx_queue;
797
798 /* All our existing PIO buffers went away */
799 efx_for_each_channel(channel, efx)
800 efx_for_each_channel_tx_queue(tx_queue, channel)
801 tx_queue->piobuf = NULL;
802 }
803
804 #else /* !EFX_USE_PIO */
805
806 static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n)
807 {
808 return n == 0 ? 0 : -ENOBUFS;
809 }
810
811 static int efx_ef10_link_piobufs(struct efx_nic *efx)
812 {
813 return 0;
814 }
815
816 static void efx_ef10_free_piobufs(struct efx_nic *efx)
817 {
818 }
819
820 static void efx_ef10_forget_old_piobufs(struct efx_nic *efx)
821 {
822 }
823
824 #endif /* EFX_USE_PIO */
825
826 static void efx_ef10_remove(struct efx_nic *efx)
827 {
828 struct efx_ef10_nic_data *nic_data = efx->nic_data;
829 int rc;
830
831 #ifdef CONFIG_SFC_SRIOV
832 struct efx_ef10_nic_data *nic_data_pf;
833 struct pci_dev *pci_dev_pf;
834 struct efx_nic *efx_pf;
835 struct ef10_vf *vf;
836
837 if (efx->pci_dev->is_virtfn) {
838 pci_dev_pf = efx->pci_dev->physfn;
839 if (pci_dev_pf) {
840 efx_pf = pci_get_drvdata(pci_dev_pf);
841 nic_data_pf = efx_pf->nic_data;
842 vf = nic_data_pf->vf + nic_data->vf_index;
843 vf->efx = NULL;
844 } else
845 netif_info(efx, drv, efx->net_dev,
846 "Could not get the PF id from VF\n");
847 }
848 #endif
849
850 efx_ef10_cleanup_vlans(efx);
851 mutex_destroy(&nic_data->vlan_lock);
852
853 efx_ptp_remove(efx);
854
855 efx_mcdi_mon_remove(efx);
856
857 efx_ef10_rx_free_indir_table(efx);
858
859 if (nic_data->wc_membase)
860 iounmap(nic_data->wc_membase);
861
862 rc = efx_ef10_free_vis(efx);
863 WARN_ON(rc != 0);
864
865 if (!nic_data->must_restore_piobufs)
866 efx_ef10_free_piobufs(efx);
867
868 device_remove_file(&efx->pci_dev->dev, &dev_attr_primary_flag);
869 device_remove_file(&efx->pci_dev->dev, &dev_attr_link_control_flag);
870
871 efx_mcdi_fini(efx);
872 efx_nic_free_buffer(efx, &nic_data->mcdi_buf);
873 kfree(nic_data);
874 }
875
876 static int efx_ef10_probe_pf(struct efx_nic *efx)
877 {
878 return efx_ef10_probe(efx);
879 }
880
881 int efx_ef10_vadaptor_query(struct efx_nic *efx, unsigned int port_id,
882 u32 *port_flags, u32 *vadaptor_flags,
883 unsigned int *vlan_tags)
884 {
885 struct efx_ef10_nic_data *nic_data = efx->nic_data;
886 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_QUERY_IN_LEN);
887 MCDI_DECLARE_BUF(outbuf, MC_CMD_VADAPTOR_QUERY_OUT_LEN);
888 size_t outlen;
889 int rc;
890
891 if (nic_data->datapath_caps &
892 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN)) {
893 MCDI_SET_DWORD(inbuf, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID,
894 port_id);
895
896 rc = efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_QUERY, inbuf, sizeof(inbuf),
897 outbuf, sizeof(outbuf), &outlen);
898 if (rc)
899 return rc;
900
901 if (outlen < sizeof(outbuf)) {
902 rc = -EIO;
903 return rc;
904 }
905 }
906
907 if (port_flags)
908 *port_flags = MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_PORT_FLAGS);
909 if (vadaptor_flags)
910 *vadaptor_flags =
911 MCDI_DWORD(outbuf, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS);
912 if (vlan_tags)
913 *vlan_tags =
914 MCDI_DWORD(outbuf,
915 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS);
916
917 return 0;
918 }
919
920 int efx_ef10_vadaptor_alloc(struct efx_nic *efx, unsigned int port_id)
921 {
922 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_ALLOC_IN_LEN);
923
924 MCDI_SET_DWORD(inbuf, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
925 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_ALLOC, inbuf, sizeof(inbuf),
926 NULL, 0, NULL);
927 }
928
929 int efx_ef10_vadaptor_free(struct efx_nic *efx, unsigned int port_id)
930 {
931 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_FREE_IN_LEN);
932
933 MCDI_SET_DWORD(inbuf, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
934 return efx_mcdi_rpc(efx, MC_CMD_VADAPTOR_FREE, inbuf, sizeof(inbuf),
935 NULL, 0, NULL);
936 }
937
938 int efx_ef10_vport_add_mac(struct efx_nic *efx,
939 unsigned int port_id, u8 *mac)
940 {
941 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN);
942
943 MCDI_SET_DWORD(inbuf, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID, port_id);
944 ether_addr_copy(MCDI_PTR(inbuf, VPORT_ADD_MAC_ADDRESS_IN_MACADDR), mac);
945
946 return efx_mcdi_rpc(efx, MC_CMD_VPORT_ADD_MAC_ADDRESS, inbuf,
947 sizeof(inbuf), NULL, 0, NULL);
948 }
949
950 int efx_ef10_vport_del_mac(struct efx_nic *efx,
951 unsigned int port_id, u8 *mac)
952 {
953 MCDI_DECLARE_BUF(inbuf, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN);
954
955 MCDI_SET_DWORD(inbuf, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID, port_id);
956 ether_addr_copy(MCDI_PTR(inbuf, VPORT_DEL_MAC_ADDRESS_IN_MACADDR), mac);
957
958 return efx_mcdi_rpc(efx, MC_CMD_VPORT_DEL_MAC_ADDRESS, inbuf,
959 sizeof(inbuf), NULL, 0, NULL);
960 }
961
962 #ifdef CONFIG_SFC_SRIOV
963 static int efx_ef10_probe_vf(struct efx_nic *efx)
964 {
965 int rc;
966 struct pci_dev *pci_dev_pf;
967
968 /* If the parent PF has no VF data structure, it doesn't know about this
969 * VF so fail probe. The VF needs to be re-created. This can happen
970 * if the PF driver is unloaded while the VF is assigned to a guest.
971 */
972 pci_dev_pf = efx->pci_dev->physfn;
973 if (pci_dev_pf) {
974 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
975 struct efx_ef10_nic_data *nic_data_pf = efx_pf->nic_data;
976
977 if (!nic_data_pf->vf) {
978 netif_info(efx, drv, efx->net_dev,
979 "The VF cannot link to its parent PF; "
980 "please destroy and re-create the VF\n");
981 return -EBUSY;
982 }
983 }
984
985 rc = efx_ef10_probe(efx);
986 if (rc)
987 return rc;
988
989 rc = efx_ef10_get_vf_index(efx);
990 if (rc)
991 goto fail;
992
993 if (efx->pci_dev->is_virtfn) {
994 if (efx->pci_dev->physfn) {
995 struct efx_nic *efx_pf =
996 pci_get_drvdata(efx->pci_dev->physfn);
997 struct efx_ef10_nic_data *nic_data_p = efx_pf->nic_data;
998 struct efx_ef10_nic_data *nic_data = efx->nic_data;
999
1000 nic_data_p->vf[nic_data->vf_index].efx = efx;
1001 nic_data_p->vf[nic_data->vf_index].pci_dev =
1002 efx->pci_dev;
1003 } else
1004 netif_info(efx, drv, efx->net_dev,
1005 "Could not get the PF id from VF\n");
1006 }
1007
1008 return 0;
1009
1010 fail:
1011 efx_ef10_remove(efx);
1012 return rc;
1013 }
1014 #else
1015 static int efx_ef10_probe_vf(struct efx_nic *efx __attribute__ ((unused)))
1016 {
1017 return 0;
1018 }
1019 #endif
1020
1021 static int efx_ef10_alloc_vis(struct efx_nic *efx,
1022 unsigned int min_vis, unsigned int max_vis)
1023 {
1024 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN);
1025 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN);
1026 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1027 size_t outlen;
1028 int rc;
1029
1030 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis);
1031 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis);
1032 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf),
1033 outbuf, sizeof(outbuf), &outlen);
1034 if (rc != 0)
1035 return rc;
1036
1037 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN)
1038 return -EIO;
1039
1040 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n",
1041 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE));
1042
1043 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE);
1044 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT);
1045 return 0;
1046 }
1047
1048 /* Note that the failure path of this function does not free
1049 * resources, as this will be done by efx_ef10_remove().
1050 */
1051 static int efx_ef10_dimension_resources(struct efx_nic *efx)
1052 {
1053 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1054 unsigned int uc_mem_map_size, wc_mem_map_size;
1055 unsigned int min_vis = max(EFX_TXQ_TYPES,
1056 efx_separate_tx_channels ? 2 : 1);
1057 unsigned int channel_vis, pio_write_vi_base, max_vis;
1058 void __iomem *membase;
1059 int rc;
1060
1061 channel_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1062
1063 #ifdef EFX_USE_PIO
1064 /* Try to allocate PIO buffers if wanted and if the full
1065 * number of PIO buffers would be sufficient to allocate one
1066 * copy-buffer per TX channel. Failure is non-fatal, as there
1067 * are only a small number of PIO buffers shared between all
1068 * functions of the controller.
1069 */
1070 if (efx_piobuf_size != 0 &&
1071 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >=
1072 efx->n_tx_channels) {
1073 unsigned int n_piobufs =
1074 DIV_ROUND_UP(efx->n_tx_channels,
1075 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size);
1076
1077 rc = efx_ef10_alloc_piobufs(efx, n_piobufs);
1078 if (rc)
1079 netif_err(efx, probe, efx->net_dev,
1080 "failed to allocate PIO buffers (%d)\n", rc);
1081 else
1082 netif_dbg(efx, probe, efx->net_dev,
1083 "allocated %u PIO buffers\n", n_piobufs);
1084 }
1085 #else
1086 nic_data->n_piobufs = 0;
1087 #endif
1088
1089 /* PIO buffers should be mapped with write-combining enabled,
1090 * and we want to make single UC and WC mappings rather than
1091 * several of each (in fact that's the only option if host
1092 * page size is >4K). So we may allocate some extra VIs just
1093 * for writing PIO buffers through.
1094 *
1095 * The UC mapping contains (channel_vis - 1) complete VIs and the
1096 * first half of the next VI. Then the WC mapping begins with
1097 * the second half of this last VI.
1098 */
1099 uc_mem_map_size = PAGE_ALIGN((channel_vis - 1) * EFX_VI_PAGE_SIZE +
1100 ER_DZ_TX_PIOBUF);
1101 if (nic_data->n_piobufs) {
1102 /* pio_write_vi_base rounds down to give the number of complete
1103 * VIs inside the UC mapping.
1104 */
1105 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE;
1106 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base +
1107 nic_data->n_piobufs) *
1108 EFX_VI_PAGE_SIZE) -
1109 uc_mem_map_size);
1110 max_vis = pio_write_vi_base + nic_data->n_piobufs;
1111 } else {
1112 pio_write_vi_base = 0;
1113 wc_mem_map_size = 0;
1114 max_vis = channel_vis;
1115 }
1116
1117 /* In case the last attached driver failed to free VIs, do it now */
1118 rc = efx_ef10_free_vis(efx);
1119 if (rc != 0)
1120 return rc;
1121
1122 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis);
1123 if (rc != 0)
1124 return rc;
1125
1126 if (nic_data->n_allocated_vis < channel_vis) {
1127 netif_info(efx, drv, efx->net_dev,
1128 "Could not allocate enough VIs to satisfy RSS"
1129 " requirements. Performance may not be optimal.\n");
1130 /* We didn't get the VIs to populate our channels.
1131 * We could keep what we got but then we'd have more
1132 * interrupts than we need.
1133 * Instead calculate new max_channels and restart
1134 */
1135 efx->max_channels = nic_data->n_allocated_vis;
1136 efx->max_tx_channels =
1137 nic_data->n_allocated_vis / EFX_TXQ_TYPES;
1138
1139 efx_ef10_free_vis(efx);
1140 return -EAGAIN;
1141 }
1142
1143 /* If we didn't get enough VIs to map all the PIO buffers, free the
1144 * PIO buffers
1145 */
1146 if (nic_data->n_piobufs &&
1147 nic_data->n_allocated_vis <
1148 pio_write_vi_base + nic_data->n_piobufs) {
1149 netif_dbg(efx, probe, efx->net_dev,
1150 "%u VIs are not sufficient to map %u PIO buffers\n",
1151 nic_data->n_allocated_vis, nic_data->n_piobufs);
1152 efx_ef10_free_piobufs(efx);
1153 }
1154
1155 /* Shrink the original UC mapping of the memory BAR */
1156 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size);
1157 if (!membase) {
1158 netif_err(efx, probe, efx->net_dev,
1159 "could not shrink memory BAR to %x\n",
1160 uc_mem_map_size);
1161 return -ENOMEM;
1162 }
1163 iounmap(efx->membase);
1164 efx->membase = membase;
1165
1166 /* Set up the WC mapping if needed */
1167 if (wc_mem_map_size) {
1168 nic_data->wc_membase = ioremap_wc(efx->membase_phys +
1169 uc_mem_map_size,
1170 wc_mem_map_size);
1171 if (!nic_data->wc_membase) {
1172 netif_err(efx, probe, efx->net_dev,
1173 "could not allocate WC mapping of size %x\n",
1174 wc_mem_map_size);
1175 return -ENOMEM;
1176 }
1177 nic_data->pio_write_vi_base = pio_write_vi_base;
1178 nic_data->pio_write_base =
1179 nic_data->wc_membase +
1180 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF -
1181 uc_mem_map_size);
1182
1183 rc = efx_ef10_link_piobufs(efx);
1184 if (rc)
1185 efx_ef10_free_piobufs(efx);
1186 }
1187
1188 netif_dbg(efx, probe, efx->net_dev,
1189 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1190 &efx->membase_phys, efx->membase, uc_mem_map_size,
1191 nic_data->wc_membase, wc_mem_map_size);
1192
1193 return 0;
1194 }
1195
1196 static int efx_ef10_init_nic(struct efx_nic *efx)
1197 {
1198 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1199 int rc;
1200
1201 if (nic_data->must_check_datapath_caps) {
1202 rc = efx_ef10_init_datapath_caps(efx);
1203 if (rc)
1204 return rc;
1205 nic_data->must_check_datapath_caps = false;
1206 }
1207
1208 if (nic_data->must_realloc_vis) {
1209 /* We cannot let the number of VIs change now */
1210 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis,
1211 nic_data->n_allocated_vis);
1212 if (rc)
1213 return rc;
1214 nic_data->must_realloc_vis = false;
1215 }
1216
1217 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) {
1218 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs);
1219 if (rc == 0) {
1220 rc = efx_ef10_link_piobufs(efx);
1221 if (rc)
1222 efx_ef10_free_piobufs(efx);
1223 }
1224
1225 /* Log an error on failure, but this is non-fatal */
1226 if (rc)
1227 netif_err(efx, drv, efx->net_dev,
1228 "failed to restore PIO buffers (%d)\n", rc);
1229 nic_data->must_restore_piobufs = false;
1230 }
1231
1232 /* don't fail init if RSS setup doesn't work */
1233 efx->type->rx_push_rss_config(efx, false, efx->rx_indir_table);
1234
1235 return 0;
1236 }
1237
1238 static void efx_ef10_reset_mc_allocations(struct efx_nic *efx)
1239 {
1240 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1241 #ifdef CONFIG_SFC_SRIOV
1242 unsigned int i;
1243 #endif
1244
1245 /* All our allocations have been reset */
1246 nic_data->must_realloc_vis = true;
1247 nic_data->must_restore_filters = true;
1248 nic_data->must_restore_piobufs = true;
1249 efx_ef10_forget_old_piobufs(efx);
1250 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
1251
1252 /* Driver-created vswitches and vports must be re-created */
1253 nic_data->must_probe_vswitching = true;
1254 nic_data->vport_id = EVB_PORT_ID_ASSIGNED;
1255 #ifdef CONFIG_SFC_SRIOV
1256 if (nic_data->vf)
1257 for (i = 0; i < efx->vf_count; i++)
1258 nic_data->vf[i].vport_id = 0;
1259 #endif
1260 }
1261
1262 static enum reset_type efx_ef10_map_reset_reason(enum reset_type reason)
1263 {
1264 if (reason == RESET_TYPE_MC_FAILURE)
1265 return RESET_TYPE_DATAPATH;
1266
1267 return efx_mcdi_map_reset_reason(reason);
1268 }
1269
1270 static int efx_ef10_map_reset_flags(u32 *flags)
1271 {
1272 enum {
1273 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) <<
1274 ETH_RESET_SHARED_SHIFT),
1275 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER |
1276 ETH_RESET_OFFLOAD | ETH_RESET_MAC |
1277 ETH_RESET_PHY | ETH_RESET_MGMT) <<
1278 ETH_RESET_SHARED_SHIFT)
1279 };
1280
1281 /* We assume for now that our PCI function is permitted to
1282 * reset everything.
1283 */
1284
1285 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) {
1286 *flags &= ~EF10_RESET_MC;
1287 return RESET_TYPE_WORLD;
1288 }
1289
1290 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) {
1291 *flags &= ~EF10_RESET_PORT;
1292 return RESET_TYPE_ALL;
1293 }
1294
1295 /* no invisible reset implemented */
1296
1297 return -EINVAL;
1298 }
1299
1300 static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type)
1301 {
1302 int rc = efx_mcdi_reset(efx, reset_type);
1303
1304 /* Unprivileged functions return -EPERM, but need to return success
1305 * here so that the datapath is brought back up.
1306 */
1307 if (reset_type == RESET_TYPE_WORLD && rc == -EPERM)
1308 rc = 0;
1309
1310 /* If it was a port reset, trigger reallocation of MC resources.
1311 * Note that on an MC reset nothing needs to be done now because we'll
1312 * detect the MC reset later and handle it then.
1313 * For an FLR, we never get an MC reset event, but the MC has reset all
1314 * resources assigned to us, so we have to trigger reallocation now.
1315 */
1316 if ((reset_type == RESET_TYPE_ALL ||
1317 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc)
1318 efx_ef10_reset_mc_allocations(efx);
1319 return rc;
1320 }
1321
1322 #define EF10_DMA_STAT(ext_name, mcdi_name) \
1323 [EF10_STAT_ ## ext_name] = \
1324 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1325 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1326 [EF10_STAT_ ## int_name] = \
1327 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1328 #define EF10_OTHER_STAT(ext_name) \
1329 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1330 #define GENERIC_SW_STAT(ext_name) \
1331 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1332
1333 static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = {
1334 EF10_DMA_STAT(port_tx_bytes, TX_BYTES),
1335 EF10_DMA_STAT(port_tx_packets, TX_PKTS),
1336 EF10_DMA_STAT(port_tx_pause, TX_PAUSE_PKTS),
1337 EF10_DMA_STAT(port_tx_control, TX_CONTROL_PKTS),
1338 EF10_DMA_STAT(port_tx_unicast, TX_UNICAST_PKTS),
1339 EF10_DMA_STAT(port_tx_multicast, TX_MULTICAST_PKTS),
1340 EF10_DMA_STAT(port_tx_broadcast, TX_BROADCAST_PKTS),
1341 EF10_DMA_STAT(port_tx_lt64, TX_LT64_PKTS),
1342 EF10_DMA_STAT(port_tx_64, TX_64_PKTS),
1343 EF10_DMA_STAT(port_tx_65_to_127, TX_65_TO_127_PKTS),
1344 EF10_DMA_STAT(port_tx_128_to_255, TX_128_TO_255_PKTS),
1345 EF10_DMA_STAT(port_tx_256_to_511, TX_256_TO_511_PKTS),
1346 EF10_DMA_STAT(port_tx_512_to_1023, TX_512_TO_1023_PKTS),
1347 EF10_DMA_STAT(port_tx_1024_to_15xx, TX_1024_TO_15XX_PKTS),
1348 EF10_DMA_STAT(port_tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS),
1349 EF10_DMA_STAT(port_rx_bytes, RX_BYTES),
1350 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes, RX_BAD_BYTES),
1351 EF10_OTHER_STAT(port_rx_good_bytes),
1352 EF10_OTHER_STAT(port_rx_bad_bytes),
1353 EF10_DMA_STAT(port_rx_packets, RX_PKTS),
1354 EF10_DMA_STAT(port_rx_good, RX_GOOD_PKTS),
1355 EF10_DMA_STAT(port_rx_bad, RX_BAD_FCS_PKTS),
1356 EF10_DMA_STAT(port_rx_pause, RX_PAUSE_PKTS),
1357 EF10_DMA_STAT(port_rx_control, RX_CONTROL_PKTS),
1358 EF10_DMA_STAT(port_rx_unicast, RX_UNICAST_PKTS),
1359 EF10_DMA_STAT(port_rx_multicast, RX_MULTICAST_PKTS),
1360 EF10_DMA_STAT(port_rx_broadcast, RX_BROADCAST_PKTS),
1361 EF10_DMA_STAT(port_rx_lt64, RX_UNDERSIZE_PKTS),
1362 EF10_DMA_STAT(port_rx_64, RX_64_PKTS),
1363 EF10_DMA_STAT(port_rx_65_to_127, RX_65_TO_127_PKTS),
1364 EF10_DMA_STAT(port_rx_128_to_255, RX_128_TO_255_PKTS),
1365 EF10_DMA_STAT(port_rx_256_to_511, RX_256_TO_511_PKTS),
1366 EF10_DMA_STAT(port_rx_512_to_1023, RX_512_TO_1023_PKTS),
1367 EF10_DMA_STAT(port_rx_1024_to_15xx, RX_1024_TO_15XX_PKTS),
1368 EF10_DMA_STAT(port_rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS),
1369 EF10_DMA_STAT(port_rx_gtjumbo, RX_GTJUMBO_PKTS),
1370 EF10_DMA_STAT(port_rx_bad_gtjumbo, RX_JABBER_PKTS),
1371 EF10_DMA_STAT(port_rx_overflow, RX_OVERFLOW_PKTS),
1372 EF10_DMA_STAT(port_rx_align_error, RX_ALIGN_ERROR_PKTS),
1373 EF10_DMA_STAT(port_rx_length_error, RX_LENGTH_ERROR_PKTS),
1374 EF10_DMA_STAT(port_rx_nodesc_drops, RX_NODESC_DROPS),
1375 GENERIC_SW_STAT(rx_nodesc_trunc),
1376 GENERIC_SW_STAT(rx_noskb_drops),
1377 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW),
1378 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW),
1379 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL),
1380 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL),
1381 EF10_DMA_STAT(port_rx_pm_trunc_qbb, PM_TRUNC_QBB),
1382 EF10_DMA_STAT(port_rx_pm_discard_qbb, PM_DISCARD_QBB),
1383 EF10_DMA_STAT(port_rx_pm_discard_mapping, PM_DISCARD_MAPPING),
1384 EF10_DMA_STAT(port_rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS),
1385 EF10_DMA_STAT(port_rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS),
1386 EF10_DMA_STAT(port_rx_dp_streaming_packets, RXDP_STREAMING_PKTS),
1387 EF10_DMA_STAT(port_rx_dp_hlb_fetch, RXDP_HLB_FETCH_CONDITIONS),
1388 EF10_DMA_STAT(port_rx_dp_hlb_wait, RXDP_HLB_WAIT_CONDITIONS),
1389 EF10_DMA_STAT(rx_unicast, VADAPTER_RX_UNICAST_PACKETS),
1390 EF10_DMA_STAT(rx_unicast_bytes, VADAPTER_RX_UNICAST_BYTES),
1391 EF10_DMA_STAT(rx_multicast, VADAPTER_RX_MULTICAST_PACKETS),
1392 EF10_DMA_STAT(rx_multicast_bytes, VADAPTER_RX_MULTICAST_BYTES),
1393 EF10_DMA_STAT(rx_broadcast, VADAPTER_RX_BROADCAST_PACKETS),
1394 EF10_DMA_STAT(rx_broadcast_bytes, VADAPTER_RX_BROADCAST_BYTES),
1395 EF10_DMA_STAT(rx_bad, VADAPTER_RX_BAD_PACKETS),
1396 EF10_DMA_STAT(rx_bad_bytes, VADAPTER_RX_BAD_BYTES),
1397 EF10_DMA_STAT(rx_overflow, VADAPTER_RX_OVERFLOW),
1398 EF10_DMA_STAT(tx_unicast, VADAPTER_TX_UNICAST_PACKETS),
1399 EF10_DMA_STAT(tx_unicast_bytes, VADAPTER_TX_UNICAST_BYTES),
1400 EF10_DMA_STAT(tx_multicast, VADAPTER_TX_MULTICAST_PACKETS),
1401 EF10_DMA_STAT(tx_multicast_bytes, VADAPTER_TX_MULTICAST_BYTES),
1402 EF10_DMA_STAT(tx_broadcast, VADAPTER_TX_BROADCAST_PACKETS),
1403 EF10_DMA_STAT(tx_broadcast_bytes, VADAPTER_TX_BROADCAST_BYTES),
1404 EF10_DMA_STAT(tx_bad, VADAPTER_TX_BAD_PACKETS),
1405 EF10_DMA_STAT(tx_bad_bytes, VADAPTER_TX_BAD_BYTES),
1406 EF10_DMA_STAT(tx_overflow, VADAPTER_TX_OVERFLOW),
1407 };
1408
1409 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1410 (1ULL << EF10_STAT_port_tx_packets) | \
1411 (1ULL << EF10_STAT_port_tx_pause) | \
1412 (1ULL << EF10_STAT_port_tx_unicast) | \
1413 (1ULL << EF10_STAT_port_tx_multicast) | \
1414 (1ULL << EF10_STAT_port_tx_broadcast) | \
1415 (1ULL << EF10_STAT_port_rx_bytes) | \
1416 (1ULL << \
1417 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1418 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1419 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1420 (1ULL << EF10_STAT_port_rx_packets) | \
1421 (1ULL << EF10_STAT_port_rx_good) | \
1422 (1ULL << EF10_STAT_port_rx_bad) | \
1423 (1ULL << EF10_STAT_port_rx_pause) | \
1424 (1ULL << EF10_STAT_port_rx_control) | \
1425 (1ULL << EF10_STAT_port_rx_unicast) | \
1426 (1ULL << EF10_STAT_port_rx_multicast) | \
1427 (1ULL << EF10_STAT_port_rx_broadcast) | \
1428 (1ULL << EF10_STAT_port_rx_lt64) | \
1429 (1ULL << EF10_STAT_port_rx_64) | \
1430 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1431 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1432 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1433 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1434 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1435 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1436 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1437 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1438 (1ULL << EF10_STAT_port_rx_overflow) | \
1439 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1440 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1441 (1ULL << GENERIC_STAT_rx_noskb_drops))
1442
1443 /* These statistics are only provided by the 10G MAC. For a 10G/40G
1444 * switchable port we do not expose these because they might not
1445 * include all the packets they should.
1446 */
1447 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1448 (1ULL << EF10_STAT_port_tx_lt64) | \
1449 (1ULL << EF10_STAT_port_tx_64) | \
1450 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1451 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1452 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1453 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1454 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1455 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1456
1457 /* These statistics are only provided by the 40G MAC. For a 10G/40G
1458 * switchable port we do expose these because the errors will otherwise
1459 * be silent.
1460 */
1461 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1462 (1ULL << EF10_STAT_port_rx_length_error))
1463
1464 /* These statistics are only provided if the firmware supports the
1465 * capability PM_AND_RXDP_COUNTERS.
1466 */
1467 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
1468 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1469 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1470 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1471 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1472 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1473 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1474 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1475 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1476 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1477 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1478 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1479 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1480
1481 static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx)
1482 {
1483 u64 raw_mask = HUNT_COMMON_STAT_MASK;
1484 u32 port_caps = efx_mcdi_phy_get_caps(efx);
1485 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1486
1487 if (!(efx->mcdi->fn_flags &
1488 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL))
1489 return 0;
1490
1491 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN))
1492 raw_mask |= HUNT_40G_EXTRA_STAT_MASK;
1493 else
1494 raw_mask |= HUNT_10G_ONLY_STAT_MASK;
1495
1496 if (nic_data->datapath_caps &
1497 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN))
1498 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK;
1499
1500 return raw_mask;
1501 }
1502
1503 static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask)
1504 {
1505 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1506 u64 raw_mask[2];
1507
1508 raw_mask[0] = efx_ef10_raw_stat_mask(efx);
1509
1510 /* Only show vadaptor stats when EVB capability is present */
1511 if (nic_data->datapath_caps &
1512 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN)) {
1513 raw_mask[0] |= ~((1ULL << EF10_STAT_rx_unicast) - 1);
1514 raw_mask[1] = (1ULL << (EF10_STAT_COUNT - 63)) - 1;
1515 } else {
1516 raw_mask[1] = 0;
1517 }
1518
1519 #if BITS_PER_LONG == 64
1520 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 2);
1521 mask[0] = raw_mask[0];
1522 mask[1] = raw_mask[1];
1523 #else
1524 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT) != 3);
1525 mask[0] = raw_mask[0] & 0xffffffff;
1526 mask[1] = raw_mask[0] >> 32;
1527 mask[2] = raw_mask[1] & 0xffffffff;
1528 #endif
1529 }
1530
1531 static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names)
1532 {
1533 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1534
1535 efx_ef10_get_stat_mask(efx, mask);
1536 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT,
1537 mask, names);
1538 }
1539
1540 static size_t efx_ef10_update_stats_common(struct efx_nic *efx, u64 *full_stats,
1541 struct rtnl_link_stats64 *core_stats)
1542 {
1543 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1544 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1545 u64 *stats = nic_data->stats;
1546 size_t stats_count = 0, index;
1547
1548 efx_ef10_get_stat_mask(efx, mask);
1549
1550 if (full_stats) {
1551 for_each_set_bit(index, mask, EF10_STAT_COUNT) {
1552 if (efx_ef10_stat_desc[index].name) {
1553 *full_stats++ = stats[index];
1554 ++stats_count;
1555 }
1556 }
1557 }
1558
1559 if (!core_stats)
1560 return stats_count;
1561
1562 if (nic_data->datapath_caps &
1563 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN) {
1564 /* Use vadaptor stats. */
1565 core_stats->rx_packets = stats[EF10_STAT_rx_unicast] +
1566 stats[EF10_STAT_rx_multicast] +
1567 stats[EF10_STAT_rx_broadcast];
1568 core_stats->tx_packets = stats[EF10_STAT_tx_unicast] +
1569 stats[EF10_STAT_tx_multicast] +
1570 stats[EF10_STAT_tx_broadcast];
1571 core_stats->rx_bytes = stats[EF10_STAT_rx_unicast_bytes] +
1572 stats[EF10_STAT_rx_multicast_bytes] +
1573 stats[EF10_STAT_rx_broadcast_bytes];
1574 core_stats->tx_bytes = stats[EF10_STAT_tx_unicast_bytes] +
1575 stats[EF10_STAT_tx_multicast_bytes] +
1576 stats[EF10_STAT_tx_broadcast_bytes];
1577 core_stats->rx_dropped = stats[GENERIC_STAT_rx_nodesc_trunc] +
1578 stats[GENERIC_STAT_rx_noskb_drops];
1579 core_stats->multicast = stats[EF10_STAT_rx_multicast];
1580 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad];
1581 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow];
1582 core_stats->rx_errors = core_stats->rx_crc_errors;
1583 core_stats->tx_errors = stats[EF10_STAT_tx_bad];
1584 } else {
1585 /* Use port stats. */
1586 core_stats->rx_packets = stats[EF10_STAT_port_rx_packets];
1587 core_stats->tx_packets = stats[EF10_STAT_port_tx_packets];
1588 core_stats->rx_bytes = stats[EF10_STAT_port_rx_bytes];
1589 core_stats->tx_bytes = stats[EF10_STAT_port_tx_bytes];
1590 core_stats->rx_dropped = stats[EF10_STAT_port_rx_nodesc_drops] +
1591 stats[GENERIC_STAT_rx_nodesc_trunc] +
1592 stats[GENERIC_STAT_rx_noskb_drops];
1593 core_stats->multicast = stats[EF10_STAT_port_rx_multicast];
1594 core_stats->rx_length_errors =
1595 stats[EF10_STAT_port_rx_gtjumbo] +
1596 stats[EF10_STAT_port_rx_length_error];
1597 core_stats->rx_crc_errors = stats[EF10_STAT_port_rx_bad];
1598 core_stats->rx_frame_errors =
1599 stats[EF10_STAT_port_rx_align_error];
1600 core_stats->rx_fifo_errors = stats[EF10_STAT_port_rx_overflow];
1601 core_stats->rx_errors = (core_stats->rx_length_errors +
1602 core_stats->rx_crc_errors +
1603 core_stats->rx_frame_errors);
1604 }
1605
1606 return stats_count;
1607 }
1608
1609 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic *efx)
1610 {
1611 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1612 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1613 __le64 generation_start, generation_end;
1614 u64 *stats = nic_data->stats;
1615 __le64 *dma_stats;
1616
1617 efx_ef10_get_stat_mask(efx, mask);
1618
1619 dma_stats = efx->stats_buffer.addr;
1620 nic_data = efx->nic_data;
1621
1622 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1623 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
1624 return 0;
1625 rmb();
1626 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1627 stats, efx->stats_buffer.addr, false);
1628 rmb();
1629 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1630 if (generation_end != generation_start)
1631 return -EAGAIN;
1632
1633 /* Update derived statistics */
1634 efx_nic_fix_nodesc_drop_stat(efx,
1635 &stats[EF10_STAT_port_rx_nodesc_drops]);
1636 stats[EF10_STAT_port_rx_good_bytes] =
1637 stats[EF10_STAT_port_rx_bytes] -
1638 stats[EF10_STAT_port_rx_bytes_minus_good_bytes];
1639 efx_update_diff_stat(&stats[EF10_STAT_port_rx_bad_bytes],
1640 stats[EF10_STAT_port_rx_bytes_minus_good_bytes]);
1641 efx_update_sw_stats(efx, stats);
1642 return 0;
1643 }
1644
1645
1646 static size_t efx_ef10_update_stats_pf(struct efx_nic *efx, u64 *full_stats,
1647 struct rtnl_link_stats64 *core_stats)
1648 {
1649 int retry;
1650
1651 /* If we're unlucky enough to read statistics during the DMA, wait
1652 * up to 10ms for it to finish (typically takes <500us)
1653 */
1654 for (retry = 0; retry < 100; ++retry) {
1655 if (efx_ef10_try_update_nic_stats_pf(efx) == 0)
1656 break;
1657 udelay(100);
1658 }
1659
1660 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1661 }
1662
1663 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic *efx)
1664 {
1665 MCDI_DECLARE_BUF(inbuf, MC_CMD_MAC_STATS_IN_LEN);
1666 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1667 DECLARE_BITMAP(mask, EF10_STAT_COUNT);
1668 __le64 generation_start, generation_end;
1669 u64 *stats = nic_data->stats;
1670 u32 dma_len = MC_CMD_MAC_NSTATS * sizeof(u64);
1671 struct efx_buffer stats_buf;
1672 __le64 *dma_stats;
1673 int rc;
1674
1675 spin_unlock_bh(&efx->stats_lock);
1676
1677 if (in_interrupt()) {
1678 /* If in atomic context, cannot update stats. Just update the
1679 * software stats and return so the caller can continue.
1680 */
1681 spin_lock_bh(&efx->stats_lock);
1682 efx_update_sw_stats(efx, stats);
1683 return 0;
1684 }
1685
1686 efx_ef10_get_stat_mask(efx, mask);
1687
1688 rc = efx_nic_alloc_buffer(efx, &stats_buf, dma_len, GFP_ATOMIC);
1689 if (rc) {
1690 spin_lock_bh(&efx->stats_lock);
1691 return rc;
1692 }
1693
1694 dma_stats = stats_buf.addr;
1695 dma_stats[MC_CMD_MAC_GENERATION_END] = EFX_MC_STATS_GENERATION_INVALID;
1696
1697 MCDI_SET_QWORD(inbuf, MAC_STATS_IN_DMA_ADDR, stats_buf.dma_addr);
1698 MCDI_POPULATE_DWORD_1(inbuf, MAC_STATS_IN_CMD,
1699 MAC_STATS_IN_DMA, 1);
1700 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_DMA_LEN, dma_len);
1701 MCDI_SET_DWORD(inbuf, MAC_STATS_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
1702
1703 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_MAC_STATS, inbuf, sizeof(inbuf),
1704 NULL, 0, NULL);
1705 spin_lock_bh(&efx->stats_lock);
1706 if (rc) {
1707 /* Expect ENOENT if DMA queues have not been set up */
1708 if (rc != -ENOENT || atomic_read(&efx->active_queues))
1709 efx_mcdi_display_error(efx, MC_CMD_MAC_STATS,
1710 sizeof(inbuf), NULL, 0, rc);
1711 goto out;
1712 }
1713
1714 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
1715 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) {
1716 WARN_ON_ONCE(1);
1717 goto out;
1718 }
1719 rmb();
1720 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask,
1721 stats, stats_buf.addr, false);
1722 rmb();
1723 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
1724 if (generation_end != generation_start) {
1725 rc = -EAGAIN;
1726 goto out;
1727 }
1728
1729 efx_update_sw_stats(efx, stats);
1730 out:
1731 efx_nic_free_buffer(efx, &stats_buf);
1732 return rc;
1733 }
1734
1735 static size_t efx_ef10_update_stats_vf(struct efx_nic *efx, u64 *full_stats,
1736 struct rtnl_link_stats64 *core_stats)
1737 {
1738 if (efx_ef10_try_update_nic_stats_vf(efx))
1739 return 0;
1740
1741 return efx_ef10_update_stats_common(efx, full_stats, core_stats);
1742 }
1743
1744 static void efx_ef10_push_irq_moderation(struct efx_channel *channel)
1745 {
1746 struct efx_nic *efx = channel->efx;
1747 unsigned int mode, value;
1748 efx_dword_t timer_cmd;
1749
1750 if (channel->irq_moderation) {
1751 mode = 3;
1752 value = channel->irq_moderation - 1;
1753 } else {
1754 mode = 0;
1755 value = 0;
1756 }
1757
1758 if (EFX_EF10_WORKAROUND_35388(efx)) {
1759 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS,
1760 EFE_DD_EVQ_IND_TIMER_FLAGS,
1761 ERF_DD_EVQ_IND_TIMER_MODE, mode,
1762 ERF_DD_EVQ_IND_TIMER_VAL, value);
1763 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT,
1764 channel->channel);
1765 } else {
1766 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode,
1767 ERF_DZ_TC_TIMER_VAL, value);
1768 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR,
1769 channel->channel);
1770 }
1771 }
1772
1773 static void efx_ef10_get_wol_vf(struct efx_nic *efx,
1774 struct ethtool_wolinfo *wol) {}
1775
1776 static int efx_ef10_set_wol_vf(struct efx_nic *efx, u32 type)
1777 {
1778 return -EOPNOTSUPP;
1779 }
1780
1781 static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1782 {
1783 wol->supported = 0;
1784 wol->wolopts = 0;
1785 memset(&wol->sopass, 0, sizeof(wol->sopass));
1786 }
1787
1788 static int efx_ef10_set_wol(struct efx_nic *efx, u32 type)
1789 {
1790 if (type != 0)
1791 return -EINVAL;
1792 return 0;
1793 }
1794
1795 static void efx_ef10_mcdi_request(struct efx_nic *efx,
1796 const efx_dword_t *hdr, size_t hdr_len,
1797 const efx_dword_t *sdu, size_t sdu_len)
1798 {
1799 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1800 u8 *pdu = nic_data->mcdi_buf.addr;
1801
1802 memcpy(pdu, hdr, hdr_len);
1803 memcpy(pdu + hdr_len, sdu, sdu_len);
1804 wmb();
1805
1806 /* The hardware provides 'low' and 'high' (doorbell) registers
1807 * for passing the 64-bit address of an MCDI request to
1808 * firmware. However the dwords are swapped by firmware. The
1809 * least significant bits of the doorbell are then 0 for all
1810 * MCDI requests due to alignment.
1811 */
1812 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32),
1813 ER_DZ_MC_DB_LWRD);
1814 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr),
1815 ER_DZ_MC_DB_HWRD);
1816 }
1817
1818 static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx)
1819 {
1820 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1821 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr;
1822
1823 rmb();
1824 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
1825 }
1826
1827 static void
1828 efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
1829 size_t offset, size_t outlen)
1830 {
1831 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1832 const u8 *pdu = nic_data->mcdi_buf.addr;
1833
1834 memcpy(outbuf, pdu + offset, outlen);
1835 }
1836
1837 static void efx_ef10_mcdi_reboot_detected(struct efx_nic *efx)
1838 {
1839 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1840
1841 /* All our allocations have been reset */
1842 efx_ef10_reset_mc_allocations(efx);
1843
1844 /* The datapath firmware might have been changed */
1845 nic_data->must_check_datapath_caps = true;
1846
1847 /* MAC statistics have been cleared on the NIC; clear the local
1848 * statistic that we update with efx_update_diff_stat().
1849 */
1850 nic_data->stats[EF10_STAT_port_rx_bad_bytes] = 0;
1851 }
1852
1853 static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx)
1854 {
1855 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1856 int rc;
1857
1858 rc = efx_ef10_get_warm_boot_count(efx);
1859 if (rc < 0) {
1860 /* The firmware is presumably in the process of
1861 * rebooting. However, we are supposed to report each
1862 * reboot just once, so we must only do that once we
1863 * can read and store the updated warm boot count.
1864 */
1865 return 0;
1866 }
1867
1868 if (rc == nic_data->warm_boot_count)
1869 return 0;
1870
1871 nic_data->warm_boot_count = rc;
1872 efx_ef10_mcdi_reboot_detected(efx);
1873
1874 return -EIO;
1875 }
1876
1877 /* Handle an MSI interrupt
1878 *
1879 * Handle an MSI hardware interrupt. This routine schedules event
1880 * queue processing. No interrupt acknowledgement cycle is necessary.
1881 * Also, we never need to check that the interrupt is for us, since
1882 * MSI interrupts cannot be shared.
1883 */
1884 static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id)
1885 {
1886 struct efx_msi_context *context = dev_id;
1887 struct efx_nic *efx = context->efx;
1888
1889 netif_vdbg(efx, intr, efx->net_dev,
1890 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id());
1891
1892 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) {
1893 /* Note test interrupts */
1894 if (context->index == efx->irq_level)
1895 efx->last_irq_cpu = raw_smp_processor_id();
1896
1897 /* Schedule processing of the channel */
1898 efx_schedule_channel_irq(efx->channel[context->index]);
1899 }
1900
1901 return IRQ_HANDLED;
1902 }
1903
1904 static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id)
1905 {
1906 struct efx_nic *efx = dev_id;
1907 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1908 struct efx_channel *channel;
1909 efx_dword_t reg;
1910 u32 queues;
1911
1912 /* Read the ISR which also ACKs the interrupts */
1913 efx_readd(efx, &reg, ER_DZ_BIU_INT_ISR);
1914 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG);
1915
1916 if (queues == 0)
1917 return IRQ_NONE;
1918
1919 if (likely(soft_enabled)) {
1920 /* Note test interrupts */
1921 if (queues & (1U << efx->irq_level))
1922 efx->last_irq_cpu = raw_smp_processor_id();
1923
1924 efx_for_each_channel(channel, efx) {
1925 if (queues & 1)
1926 efx_schedule_channel_irq(channel);
1927 queues >>= 1;
1928 }
1929 }
1930
1931 netif_vdbg(efx, intr, efx->net_dev,
1932 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1933 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1934
1935 return IRQ_HANDLED;
1936 }
1937
1938 static void efx_ef10_irq_test_generate(struct efx_nic *efx)
1939 {
1940 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN);
1941
1942 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0);
1943
1944 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level);
1945 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT,
1946 inbuf, sizeof(inbuf), NULL, 0, NULL);
1947 }
1948
1949 static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue)
1950 {
1951 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf,
1952 (tx_queue->ptr_mask + 1) *
1953 sizeof(efx_qword_t),
1954 GFP_KERNEL);
1955 }
1956
1957 /* This writes to the TX_DESC_WPTR and also pushes data */
1958 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue,
1959 const efx_qword_t *txd)
1960 {
1961 unsigned int write_ptr;
1962 efx_oword_t reg;
1963
1964 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
1965 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr);
1966 reg.qword[0] = *txd;
1967 efx_writeo_page(tx_queue->efx, &reg,
1968 ER_DZ_TX_DESC_UPD, tx_queue->queue);
1969 }
1970
1971 static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue)
1972 {
1973 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
1974 EFX_BUF_SIZE));
1975 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
1976 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE;
1977 struct efx_channel *channel = tx_queue->channel;
1978 struct efx_nic *efx = tx_queue->efx;
1979 struct efx_ef10_nic_data *nic_data = efx->nic_data;
1980 size_t inlen;
1981 dma_addr_t dma_addr;
1982 efx_qword_t *txd;
1983 int rc;
1984 int i;
1985 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN != 0);
1986
1987 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1);
1988 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel);
1989 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue);
1990 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue);
1991 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS,
1992 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload,
1993 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload);
1994 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0);
1995 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, nic_data->vport_id);
1996
1997 dma_addr = tx_queue->txd.buf.dma_addr;
1998
1999 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n",
2000 tx_queue->queue, entries, (u64)dma_addr);
2001
2002 for (i = 0; i < entries; ++i) {
2003 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr);
2004 dma_addr += EFX_BUF_SIZE;
2005 }
2006
2007 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries);
2008
2009 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen,
2010 NULL, 0, NULL);
2011 if (rc)
2012 goto fail;
2013
2014 /* A previous user of this TX queue might have set us up the
2015 * bomb by writing a descriptor to the TX push collector but
2016 * not the doorbell. (Each collector belongs to a port, not a
2017 * queue or function, so cannot easily be reset.) We must
2018 * attempt to push a no-op descriptor in its place.
2019 */
2020 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION;
2021 tx_queue->insert_count = 1;
2022 txd = efx_tx_desc(tx_queue, 0);
2023 EFX_POPULATE_QWORD_4(*txd,
2024 ESF_DZ_TX_DESC_IS_OPT, true,
2025 ESF_DZ_TX_OPTION_TYPE,
2026 ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
2027 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload,
2028 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload);
2029 tx_queue->write_count = 1;
2030
2031 if (nic_data->datapath_caps &
2032 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN)) {
2033 tx_queue->tso_version = 1;
2034 }
2035
2036 wmb();
2037 efx_ef10_push_tx_desc(tx_queue, txd);
2038
2039 return;
2040
2041 fail:
2042 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n",
2043 tx_queue->queue);
2044 }
2045
2046 static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue)
2047 {
2048 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN);
2049 MCDI_DECLARE_BUF_ERR(outbuf);
2050 struct efx_nic *efx = tx_queue->efx;
2051 size_t outlen;
2052 int rc;
2053
2054 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE,
2055 tx_queue->queue);
2056
2057 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf),
2058 outbuf, sizeof(outbuf), &outlen);
2059
2060 if (rc && rc != -EALREADY)
2061 goto fail;
2062
2063 return;
2064
2065 fail:
2066 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN,
2067 outbuf, outlen, rc);
2068 }
2069
2070 static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue)
2071 {
2072 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf);
2073 }
2074
2075 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2076 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue)
2077 {
2078 unsigned int write_ptr;
2079 efx_dword_t reg;
2080
2081 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2082 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr);
2083 efx_writed_page(tx_queue->efx, &reg,
2084 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue);
2085 }
2086
2087 static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue)
2088 {
2089 unsigned int old_write_count = tx_queue->write_count;
2090 struct efx_tx_buffer *buffer;
2091 unsigned int write_ptr;
2092 efx_qword_t *txd;
2093
2094 tx_queue->xmit_more_available = false;
2095 if (unlikely(tx_queue->write_count == tx_queue->insert_count))
2096 return;
2097
2098 do {
2099 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
2100 buffer = &tx_queue->buffer[write_ptr];
2101 txd = efx_tx_desc(tx_queue, write_ptr);
2102 ++tx_queue->write_count;
2103
2104 /* Create TX descriptor ring entry */
2105 if (buffer->flags & EFX_TX_BUF_OPTION) {
2106 *txd = buffer->option;
2107 } else {
2108 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
2109 EFX_POPULATE_QWORD_3(
2110 *txd,
2111 ESF_DZ_TX_KER_CONT,
2112 buffer->flags & EFX_TX_BUF_CONT,
2113 ESF_DZ_TX_KER_BYTE_CNT, buffer->len,
2114 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr);
2115 }
2116 } while (tx_queue->write_count != tx_queue->insert_count);
2117
2118 wmb(); /* Ensure descriptors are written before they are fetched */
2119
2120 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
2121 txd = efx_tx_desc(tx_queue,
2122 old_write_count & tx_queue->ptr_mask);
2123 efx_ef10_push_tx_desc(tx_queue, txd);
2124 ++tx_queue->pushes;
2125 } else {
2126 efx_ef10_notify_tx_desc(tx_queue);
2127 }
2128 }
2129
2130 static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context,
2131 bool exclusive, unsigned *context_size)
2132 {
2133 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN);
2134 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN);
2135 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2136 size_t outlen;
2137 int rc;
2138 u32 alloc_type = exclusive ?
2139 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE :
2140 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED;
2141 unsigned rss_spread = exclusive ?
2142 efx->rss_spread :
2143 min(rounddown_pow_of_two(efx->rss_spread),
2144 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE);
2145
2146 if (!exclusive && rss_spread == 1) {
2147 *context = EFX_EF10_RSS_CONTEXT_INVALID;
2148 if (context_size)
2149 *context_size = 1;
2150 return 0;
2151 }
2152
2153 if (nic_data->datapath_caps &
2154 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN)
2155 return -EOPNOTSUPP;
2156
2157 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID,
2158 nic_data->vport_id);
2159 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, alloc_type);
2160 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, rss_spread);
2161
2162 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf),
2163 outbuf, sizeof(outbuf), &outlen);
2164 if (rc != 0)
2165 return rc;
2166
2167 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)
2168 return -EIO;
2169
2170 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID);
2171
2172 if (context_size)
2173 *context_size = rss_spread;
2174
2175 return 0;
2176 }
2177
2178 static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context)
2179 {
2180 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN);
2181 int rc;
2182
2183 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID,
2184 context);
2185
2186 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf),
2187 NULL, 0, NULL);
2188 WARN_ON(rc != 0);
2189 }
2190
2191 static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context,
2192 const u32 *rx_indir_table)
2193 {
2194 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN);
2195 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN);
2196 int i, rc;
2197
2198 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID,
2199 context);
2200 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
2201 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN);
2202
2203 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i)
2204 MCDI_PTR(tablebuf,
2205 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] =
2206 (u8) rx_indir_table[i];
2207
2208 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf,
2209 sizeof(tablebuf), NULL, 0, NULL);
2210 if (rc != 0)
2211 return rc;
2212
2213 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID,
2214 context);
2215 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) !=
2216 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN);
2217 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i)
2218 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] =
2219 efx->rx_hash_key[i];
2220
2221 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf,
2222 sizeof(keybuf), NULL, 0, NULL);
2223 }
2224
2225 static void efx_ef10_rx_free_indir_table(struct efx_nic *efx)
2226 {
2227 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2228
2229 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2230 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context);
2231 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID;
2232 }
2233
2234 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic *efx,
2235 unsigned *context_size)
2236 {
2237 u32 new_rx_rss_context;
2238 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2239 int rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2240 false, context_size);
2241
2242 if (rc != 0)
2243 return rc;
2244
2245 nic_data->rx_rss_context = new_rx_rss_context;
2246 nic_data->rx_rss_context_exclusive = false;
2247 efx_set_default_rx_indir_table(efx);
2248 return 0;
2249 }
2250
2251 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic *efx,
2252 const u32 *rx_indir_table)
2253 {
2254 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2255 int rc;
2256 u32 new_rx_rss_context;
2257
2258 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID ||
2259 !nic_data->rx_rss_context_exclusive) {
2260 rc = efx_ef10_alloc_rss_context(efx, &new_rx_rss_context,
2261 true, NULL);
2262 if (rc == -EOPNOTSUPP)
2263 return rc;
2264 else if (rc != 0)
2265 goto fail1;
2266 } else {
2267 new_rx_rss_context = nic_data->rx_rss_context;
2268 }
2269
2270 rc = efx_ef10_populate_rss_table(efx, new_rx_rss_context,
2271 rx_indir_table);
2272 if (rc != 0)
2273 goto fail2;
2274
2275 if (nic_data->rx_rss_context != new_rx_rss_context)
2276 efx_ef10_rx_free_indir_table(efx);
2277 nic_data->rx_rss_context = new_rx_rss_context;
2278 nic_data->rx_rss_context_exclusive = true;
2279 if (rx_indir_table != efx->rx_indir_table)
2280 memcpy(efx->rx_indir_table, rx_indir_table,
2281 sizeof(efx->rx_indir_table));
2282 return 0;
2283
2284 fail2:
2285 if (new_rx_rss_context != nic_data->rx_rss_context)
2286 efx_ef10_free_rss_context(efx, new_rx_rss_context);
2287 fail1:
2288 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
2289 return rc;
2290 }
2291
2292 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic *efx, bool user,
2293 const u32 *rx_indir_table)
2294 {
2295 int rc;
2296
2297 if (efx->rss_spread == 1)
2298 return 0;
2299
2300 rc = efx_ef10_rx_push_exclusive_rss_config(efx, rx_indir_table);
2301
2302 if (rc == -ENOBUFS && !user) {
2303 unsigned context_size;
2304 bool mismatch = false;
2305 size_t i;
2306
2307 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table) && !mismatch;
2308 i++)
2309 mismatch = rx_indir_table[i] !=
2310 ethtool_rxfh_indir_default(i, efx->rss_spread);
2311
2312 rc = efx_ef10_rx_push_shared_rss_config(efx, &context_size);
2313 if (rc == 0) {
2314 if (context_size != efx->rss_spread)
2315 netif_warn(efx, probe, efx->net_dev,
2316 "Could not allocate an exclusive RSS"
2317 " context; allocated a shared one of"
2318 " different size."
2319 " Wanted %u, got %u.\n",
2320 efx->rss_spread, context_size);
2321 else if (mismatch)
2322 netif_warn(efx, probe, efx->net_dev,
2323 "Could not allocate an exclusive RSS"
2324 " context; allocated a shared one but"
2325 " could not apply custom"
2326 " indirection.\n");
2327 else
2328 netif_info(efx, probe, efx->net_dev,
2329 "Could not allocate an exclusive RSS"
2330 " context; allocated a shared one.\n");
2331 }
2332 }
2333 return rc;
2334 }
2335
2336 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic *efx, bool user,
2337 const u32 *rx_indir_table
2338 __attribute__ ((unused)))
2339 {
2340 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2341
2342 if (user)
2343 return -EOPNOTSUPP;
2344 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID)
2345 return 0;
2346 return efx_ef10_rx_push_shared_rss_config(efx, NULL);
2347 }
2348
2349 static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue)
2350 {
2351 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf,
2352 (rx_queue->ptr_mask + 1) *
2353 sizeof(efx_qword_t),
2354 GFP_KERNEL);
2355 }
2356
2357 static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue)
2358 {
2359 MCDI_DECLARE_BUF(inbuf,
2360 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 /
2361 EFX_BUF_SIZE));
2362 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2363 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE;
2364 struct efx_nic *efx = rx_queue->efx;
2365 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2366 size_t inlen;
2367 dma_addr_t dma_addr;
2368 int rc;
2369 int i;
2370 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN != 0);
2371
2372 rx_queue->scatter_n = 0;
2373 rx_queue->scatter_len = 0;
2374
2375 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1);
2376 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel);
2377 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue));
2378 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE,
2379 efx_rx_queue_index(rx_queue));
2380 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS,
2381 INIT_RXQ_IN_FLAG_PREFIX, 1,
2382 INIT_RXQ_IN_FLAG_TIMESTAMP, 1);
2383 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0);
2384 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, nic_data->vport_id);
2385
2386 dma_addr = rx_queue->rxd.buf.dma_addr;
2387
2388 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n",
2389 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr);
2390
2391 for (i = 0; i < entries; ++i) {
2392 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr);
2393 dma_addr += EFX_BUF_SIZE;
2394 }
2395
2396 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries);
2397
2398 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen,
2399 NULL, 0, NULL);
2400 if (rc)
2401 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n",
2402 efx_rx_queue_index(rx_queue));
2403 }
2404
2405 static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue)
2406 {
2407 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN);
2408 MCDI_DECLARE_BUF_ERR(outbuf);
2409 struct efx_nic *efx = rx_queue->efx;
2410 size_t outlen;
2411 int rc;
2412
2413 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE,
2414 efx_rx_queue_index(rx_queue));
2415
2416 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf),
2417 outbuf, sizeof(outbuf), &outlen);
2418
2419 if (rc && rc != -EALREADY)
2420 goto fail;
2421
2422 return;
2423
2424 fail:
2425 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN,
2426 outbuf, outlen, rc);
2427 }
2428
2429 static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue)
2430 {
2431 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf);
2432 }
2433
2434 /* This creates an entry in the RX descriptor queue */
2435 static inline void
2436 efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
2437 {
2438 struct efx_rx_buffer *rx_buf;
2439 efx_qword_t *rxd;
2440
2441 rxd = efx_rx_desc(rx_queue, index);
2442 rx_buf = efx_rx_buffer(rx_queue, index);
2443 EFX_POPULATE_QWORD_2(*rxd,
2444 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len,
2445 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
2446 }
2447
2448 static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue)
2449 {
2450 struct efx_nic *efx = rx_queue->efx;
2451 unsigned int write_count;
2452 efx_dword_t reg;
2453
2454 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2455 write_count = rx_queue->added_count & ~7;
2456 if (rx_queue->notified_count == write_count)
2457 return;
2458
2459 do
2460 efx_ef10_build_rx_desc(
2461 rx_queue,
2462 rx_queue->notified_count & rx_queue->ptr_mask);
2463 while (++rx_queue->notified_count != write_count);
2464
2465 wmb();
2466 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR,
2467 write_count & rx_queue->ptr_mask);
2468 efx_writed_page(efx, &reg, ER_DZ_RX_DESC_UPD,
2469 efx_rx_queue_index(rx_queue));
2470 }
2471
2472 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete;
2473
2474 static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue)
2475 {
2476 struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
2477 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
2478 efx_qword_t event;
2479
2480 EFX_POPULATE_QWORD_2(event,
2481 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
2482 ESF_DZ_EV_DATA, EFX_EF10_REFILL);
2483
2484 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
2485
2486 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2487 * already swapped the data to little-endian order.
2488 */
2489 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
2490 sizeof(efx_qword_t));
2491
2492 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT,
2493 inbuf, sizeof(inbuf), 0,
2494 efx_ef10_rx_defer_refill_complete, 0);
2495 }
2496
2497 static void
2498 efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie,
2499 int rc, efx_dword_t *outbuf,
2500 size_t outlen_actual)
2501 {
2502 /* nothing to do */
2503 }
2504
2505 static int efx_ef10_ev_probe(struct efx_channel *channel)
2506 {
2507 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf,
2508 (channel->eventq_mask + 1) *
2509 sizeof(efx_qword_t),
2510 GFP_KERNEL);
2511 }
2512
2513 static void efx_ef10_ev_fini(struct efx_channel *channel)
2514 {
2515 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN);
2516 MCDI_DECLARE_BUF_ERR(outbuf);
2517 struct efx_nic *efx = channel->efx;
2518 size_t outlen;
2519 int rc;
2520
2521 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel);
2522
2523 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf),
2524 outbuf, sizeof(outbuf), &outlen);
2525
2526 if (rc && rc != -EALREADY)
2527 goto fail;
2528
2529 return;
2530
2531 fail:
2532 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN,
2533 outbuf, outlen, rc);
2534 }
2535
2536 static int efx_ef10_ev_init(struct efx_channel *channel)
2537 {
2538 MCDI_DECLARE_BUF(inbuf,
2539 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 /
2540 EFX_BUF_SIZE));
2541 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN);
2542 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE;
2543 struct efx_nic *efx = channel->efx;
2544 struct efx_ef10_nic_data *nic_data;
2545 bool supports_rx_merge;
2546 size_t inlen, outlen;
2547 unsigned int enabled, implemented;
2548 dma_addr_t dma_addr;
2549 int rc;
2550 int i;
2551
2552 nic_data = efx->nic_data;
2553 supports_rx_merge =
2554 !!(nic_data->datapath_caps &
2555 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN);
2556
2557 /* Fill event queue with all ones (i.e. empty events) */
2558 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
2559
2560 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1);
2561 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel);
2562 /* INIT_EVQ expects index in vector table, not absolute */
2563 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel);
2564 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS,
2565 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
2566 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
2567 INIT_EVQ_IN_FLAG_TX_MERGE, 1,
2568 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge);
2569 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE,
2570 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
2571 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0);
2572 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0);
2573 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE,
2574 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
2575 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0);
2576
2577 dma_addr = channel->eventq.buf.dma_addr;
2578 for (i = 0; i < entries; ++i) {
2579 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr);
2580 dma_addr += EFX_BUF_SIZE;
2581 }
2582
2583 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries);
2584
2585 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen,
2586 outbuf, sizeof(outbuf), &outlen);
2587 /* IRQ return is ignored */
2588 if (channel->channel || rc)
2589 return rc;
2590
2591 /* Successfully created event queue on channel 0 */
2592 rc = efx_mcdi_get_workarounds(efx, &implemented, &enabled);
2593 if (rc == -ENOSYS) {
2594 /* GET_WORKAROUNDS was implemented before the bug26807
2595 * workaround, thus the latter must be unavailable in this fw
2596 */
2597 nic_data->workaround_26807 = false;
2598 rc = 0;
2599 } else if (rc) {
2600 goto fail;
2601 } else {
2602 nic_data->workaround_26807 =
2603 !!(enabled & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807);
2604
2605 if (implemented & MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 &&
2606 !nic_data->workaround_26807) {
2607 unsigned int flags;
2608
2609 rc = efx_mcdi_set_workaround(efx,
2610 MC_CMD_WORKAROUND_BUG26807,
2611 true, &flags);
2612
2613 if (!rc) {
2614 if (flags &
2615 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN) {
2616 netif_info(efx, drv, efx->net_dev,
2617 "other functions on NIC have been reset\n");
2618
2619 /* With MCFW v4.6.x and earlier, the
2620 * boot count will have incremented,
2621 * so re-read the warm_boot_count
2622 * value now to ensure this function
2623 * doesn't think it has changed next
2624 * time it checks.
2625 */
2626 rc = efx_ef10_get_warm_boot_count(efx);
2627 if (rc >= 0) {
2628 nic_data->warm_boot_count = rc;
2629 rc = 0;
2630 }
2631 }
2632 nic_data->workaround_26807 = true;
2633 } else if (rc == -EPERM) {
2634 rc = 0;
2635 }
2636 }
2637 }
2638
2639 if (!rc)
2640 return 0;
2641
2642 fail:
2643 efx_ef10_ev_fini(channel);
2644 return rc;
2645 }
2646
2647 static void efx_ef10_ev_remove(struct efx_channel *channel)
2648 {
2649 efx_nic_free_buffer(channel->efx, &channel->eventq.buf);
2650 }
2651
2652 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue,
2653 unsigned int rx_queue_label)
2654 {
2655 struct efx_nic *efx = rx_queue->efx;
2656
2657 netif_info(efx, hw, efx->net_dev,
2658 "rx event arrived on queue %d labeled as queue %u\n",
2659 efx_rx_queue_index(rx_queue), rx_queue_label);
2660
2661 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2662 }
2663
2664 static void
2665 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue,
2666 unsigned int actual, unsigned int expected)
2667 {
2668 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask;
2669 struct efx_nic *efx = rx_queue->efx;
2670
2671 netif_info(efx, hw, efx->net_dev,
2672 "dropped %d events (index=%d expected=%d)\n",
2673 dropped, actual, expected);
2674
2675 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
2676 }
2677
2678 /* partially received RX was aborted. clean up. */
2679 static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue)
2680 {
2681 unsigned int rx_desc_ptr;
2682
2683 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev,
2684 "scattered RX aborted (dropping %u buffers)\n",
2685 rx_queue->scatter_n);
2686
2687 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
2688
2689 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n,
2690 0, EFX_RX_PKT_DISCARD);
2691
2692 rx_queue->removed_count += rx_queue->scatter_n;
2693 rx_queue->scatter_n = 0;
2694 rx_queue->scatter_len = 0;
2695 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc;
2696 }
2697
2698 static int efx_ef10_handle_rx_event(struct efx_channel *channel,
2699 const efx_qword_t *event)
2700 {
2701 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class;
2702 unsigned int n_descs, n_packets, i;
2703 struct efx_nic *efx = channel->efx;
2704 struct efx_rx_queue *rx_queue;
2705 bool rx_cont;
2706 u16 flags = 0;
2707
2708 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2709 return 0;
2710
2711 /* Basic packet information */
2712 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES);
2713 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS);
2714 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL);
2715 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS);
2716 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT);
2717
2718 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT))
2719 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event="
2720 EFX_QWORD_FMT "\n",
2721 EFX_QWORD_VAL(*event));
2722
2723 rx_queue = efx_channel_get_rx_queue(channel);
2724
2725 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue)))
2726 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label);
2727
2728 n_descs = ((next_ptr_lbits - rx_queue->removed_count) &
2729 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2730
2731 if (n_descs != rx_queue->scatter_n + 1) {
2732 struct efx_ef10_nic_data *nic_data = efx->nic_data;
2733
2734 /* detect rx abort */
2735 if (unlikely(n_descs == rx_queue->scatter_n)) {
2736 if (rx_queue->scatter_n == 0 || rx_bytes != 0)
2737 netdev_WARN(efx->net_dev,
2738 "invalid RX abort: scatter_n=%u event="
2739 EFX_QWORD_FMT "\n",
2740 rx_queue->scatter_n,
2741 EFX_QWORD_VAL(*event));
2742 efx_ef10_handle_rx_abort(rx_queue);
2743 return 0;
2744 }
2745
2746 /* Check that RX completion merging is valid, i.e.
2747 * the current firmware supports it and this is a
2748 * non-scattered packet.
2749 */
2750 if (!(nic_data->datapath_caps &
2751 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) ||
2752 rx_queue->scatter_n != 0 || rx_cont) {
2753 efx_ef10_handle_rx_bad_lbits(
2754 rx_queue, next_ptr_lbits,
2755 (rx_queue->removed_count +
2756 rx_queue->scatter_n + 1) &
2757 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1));
2758 return 0;
2759 }
2760
2761 /* Merged completion for multiple non-scattered packets */
2762 rx_queue->scatter_n = 1;
2763 rx_queue->scatter_len = 0;
2764 n_packets = n_descs;
2765 ++channel->n_rx_merge_events;
2766 channel->n_rx_merge_packets += n_packets;
2767 flags |= EFX_RX_PKT_PREFIX_LEN;
2768 } else {
2769 ++rx_queue->scatter_n;
2770 rx_queue->scatter_len += rx_bytes;
2771 if (rx_cont)
2772 return 0;
2773 n_packets = 1;
2774 }
2775
2776 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR)))
2777 flags |= EFX_RX_PKT_DISCARD;
2778
2779 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) {
2780 channel->n_rx_ip_hdr_chksum_err += n_packets;
2781 } else if (unlikely(EFX_QWORD_FIELD(*event,
2782 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) {
2783 channel->n_rx_tcp_udp_chksum_err += n_packets;
2784 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP ||
2785 rx_l4_class == ESE_DZ_L4_CLASS_UDP) {
2786 flags |= EFX_RX_PKT_CSUMMED;
2787 }
2788
2789 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP)
2790 flags |= EFX_RX_PKT_TCP;
2791
2792 channel->irq_mod_score += 2 * n_packets;
2793
2794 /* Handle received packet(s) */
2795 for (i = 0; i < n_packets; i++) {
2796 efx_rx_packet(rx_queue,
2797 rx_queue->removed_count & rx_queue->ptr_mask,
2798 rx_queue->scatter_n, rx_queue->scatter_len,
2799 flags);
2800 rx_queue->removed_count += rx_queue->scatter_n;
2801 }
2802
2803 rx_queue->scatter_n = 0;
2804 rx_queue->scatter_len = 0;
2805
2806 return n_packets;
2807 }
2808
2809 static int
2810 efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
2811 {
2812 struct efx_nic *efx = channel->efx;
2813 struct efx_tx_queue *tx_queue;
2814 unsigned int tx_ev_desc_ptr;
2815 unsigned int tx_ev_q_label;
2816 int tx_descs = 0;
2817
2818 if (unlikely(ACCESS_ONCE(efx->reset_pending)))
2819 return 0;
2820
2821 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT)))
2822 return 0;
2823
2824 /* Transmit completion */
2825 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX);
2826 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL);
2827 tx_queue = efx_channel_get_tx_queue(channel,
2828 tx_ev_q_label % EFX_TXQ_TYPES);
2829 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) &
2830 tx_queue->ptr_mask);
2831 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask);
2832
2833 return tx_descs;
2834 }
2835
2836 static void
2837 efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
2838 {
2839 struct efx_nic *efx = channel->efx;
2840 int subcode;
2841
2842 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE);
2843
2844 switch (subcode) {
2845 case ESE_DZ_DRV_TIMER_EV:
2846 case ESE_DZ_DRV_WAKE_UP_EV:
2847 break;
2848 case ESE_DZ_DRV_START_UP_EV:
2849 /* event queue init complete. ok. */
2850 break;
2851 default:
2852 netif_err(efx, hw, efx->net_dev,
2853 "channel %d unknown driver event type %d"
2854 " (data " EFX_QWORD_FMT ")\n",
2855 channel->channel, subcode,
2856 EFX_QWORD_VAL(*event));
2857
2858 }
2859 }
2860
2861 static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel,
2862 efx_qword_t *event)
2863 {
2864 struct efx_nic *efx = channel->efx;
2865 u32 subcode;
2866
2867 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0);
2868
2869 switch (subcode) {
2870 case EFX_EF10_TEST:
2871 channel->event_test_cpu = raw_smp_processor_id();
2872 break;
2873 case EFX_EF10_REFILL:
2874 /* The queue must be empty, so we won't receive any rx
2875 * events, so efx_process_channel() won't refill the
2876 * queue. Refill it here
2877 */
2878 efx_fast_push_rx_descriptors(&channel->rx_queue, true);
2879 break;
2880 default:
2881 netif_err(efx, hw, efx->net_dev,
2882 "channel %d unknown driver event type %u"
2883 " (data " EFX_QWORD_FMT ")\n",
2884 channel->channel, (unsigned) subcode,
2885 EFX_QWORD_VAL(*event));
2886 }
2887 }
2888
2889 static int efx_ef10_ev_process(struct efx_channel *channel, int quota)
2890 {
2891 struct efx_nic *efx = channel->efx;
2892 efx_qword_t event, *p_event;
2893 unsigned int read_ptr;
2894 int ev_code;
2895 int tx_descs = 0;
2896 int spent = 0;
2897
2898 if (quota <= 0)
2899 return spent;
2900
2901 read_ptr = channel->eventq_read_ptr;
2902
2903 for (;;) {
2904 p_event = efx_event(channel, read_ptr);
2905 event = *p_event;
2906
2907 if (!efx_event_present(&event))
2908 break;
2909
2910 EFX_SET_QWORD(*p_event);
2911
2912 ++read_ptr;
2913
2914 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE);
2915
2916 netif_vdbg(efx, drv, efx->net_dev,
2917 "processing event on %d " EFX_QWORD_FMT "\n",
2918 channel->channel, EFX_QWORD_VAL(event));
2919
2920 switch (ev_code) {
2921 case ESE_DZ_EV_CODE_MCDI_EV:
2922 efx_mcdi_process_event(channel, &event);
2923 break;
2924 case ESE_DZ_EV_CODE_RX_EV:
2925 spent += efx_ef10_handle_rx_event(channel, &event);
2926 if (spent >= quota) {
2927 /* XXX can we split a merged event to
2928 * avoid going over-quota?
2929 */
2930 spent = quota;
2931 goto out;
2932 }
2933 break;
2934 case ESE_DZ_EV_CODE_TX_EV:
2935 tx_descs += efx_ef10_handle_tx_event(channel, &event);
2936 if (tx_descs > efx->txq_entries) {
2937 spent = quota;
2938 goto out;
2939 } else if (++spent == quota) {
2940 goto out;
2941 }
2942 break;
2943 case ESE_DZ_EV_CODE_DRIVER_EV:
2944 efx_ef10_handle_driver_event(channel, &event);
2945 if (++spent == quota)
2946 goto out;
2947 break;
2948 case EFX_EF10_DRVGEN_EV:
2949 efx_ef10_handle_driver_generated_event(channel, &event);
2950 break;
2951 default:
2952 netif_err(efx, hw, efx->net_dev,
2953 "channel %d unknown event type %d"
2954 " (data " EFX_QWORD_FMT ")\n",
2955 channel->channel, ev_code,
2956 EFX_QWORD_VAL(event));
2957 }
2958 }
2959
2960 out:
2961 channel->eventq_read_ptr = read_ptr;
2962 return spent;
2963 }
2964
2965 static void efx_ef10_ev_read_ack(struct efx_channel *channel)
2966 {
2967 struct efx_nic *efx = channel->efx;
2968 efx_dword_t rptr;
2969
2970 if (EFX_EF10_WORKAROUND_35388(efx)) {
2971 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE <
2972 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
2973 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE >
2974 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
2975
2976 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2977 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
2978 ERF_DD_EVQ_IND_RPTR,
2979 (channel->eventq_read_ptr &
2980 channel->eventq_mask) >>
2981 ERF_DD_EVQ_IND_RPTR_WIDTH);
2982 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2983 channel->channel);
2984 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS,
2985 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
2986 ERF_DD_EVQ_IND_RPTR,
2987 channel->eventq_read_ptr &
2988 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
2989 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT,
2990 channel->channel);
2991 } else {
2992 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR,
2993 channel->eventq_read_ptr &
2994 channel->eventq_mask);
2995 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel);
2996 }
2997 }
2998
2999 static void efx_ef10_ev_test_generate(struct efx_channel *channel)
3000 {
3001 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN);
3002 struct efx_nic *efx = channel->efx;
3003 efx_qword_t event;
3004 int rc;
3005
3006 EFX_POPULATE_QWORD_2(event,
3007 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV,
3008 ESF_DZ_EV_DATA, EFX_EF10_TEST);
3009
3010 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel);
3011
3012 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3013 * already swapped the data to little-endian order.
3014 */
3015 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0],
3016 sizeof(efx_qword_t));
3017
3018 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf),
3019 NULL, 0, NULL);
3020 if (rc != 0)
3021 goto fail;
3022
3023 return;
3024
3025 fail:
3026 WARN_ON(true);
3027 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
3028 }
3029
3030 void efx_ef10_handle_drain_event(struct efx_nic *efx)
3031 {
3032 if (atomic_dec_and_test(&efx->active_queues))
3033 wake_up(&efx->flush_wq);
3034
3035 WARN_ON(atomic_read(&efx->active_queues) < 0);
3036 }
3037
3038 static int efx_ef10_fini_dmaq(struct efx_nic *efx)
3039 {
3040 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3041 struct efx_channel *channel;
3042 struct efx_tx_queue *tx_queue;
3043 struct efx_rx_queue *rx_queue;
3044 int pending;
3045
3046 /* If the MC has just rebooted, the TX/RX queues will have already been
3047 * torn down, but efx->active_queues needs to be set to zero.
3048 */
3049 if (nic_data->must_realloc_vis) {
3050 atomic_set(&efx->active_queues, 0);
3051 return 0;
3052 }
3053
3054 /* Do not attempt to write to the NIC during EEH recovery */
3055 if (efx->state != STATE_RECOVERY) {
3056 efx_for_each_channel(channel, efx) {
3057 efx_for_each_channel_rx_queue(rx_queue, channel)
3058 efx_ef10_rx_fini(rx_queue);
3059 efx_for_each_channel_tx_queue(tx_queue, channel)
3060 efx_ef10_tx_fini(tx_queue);
3061 }
3062
3063 wait_event_timeout(efx->flush_wq,
3064 atomic_read(&efx->active_queues) == 0,
3065 msecs_to_jiffies(EFX_MAX_FLUSH_TIME));
3066 pending = atomic_read(&efx->active_queues);
3067 if (pending) {
3068 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n",
3069 pending);
3070 return -ETIMEDOUT;
3071 }
3072 }
3073
3074 return 0;
3075 }
3076
3077 static void efx_ef10_prepare_flr(struct efx_nic *efx)
3078 {
3079 atomic_set(&efx->active_queues, 0);
3080 }
3081
3082 static bool efx_ef10_filter_equal(const struct efx_filter_spec *left,
3083 const struct efx_filter_spec *right)
3084 {
3085 if ((left->match_flags ^ right->match_flags) |
3086 ((left->flags ^ right->flags) &
3087 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)))
3088 return false;
3089
3090 return memcmp(&left->outer_vid, &right->outer_vid,
3091 sizeof(struct efx_filter_spec) -
3092 offsetof(struct efx_filter_spec, outer_vid)) == 0;
3093 }
3094
3095 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec)
3096 {
3097 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3);
3098 return jhash2((const u32 *)&spec->outer_vid,
3099 (sizeof(struct efx_filter_spec) -
3100 offsetof(struct efx_filter_spec, outer_vid)) / 4,
3101 0);
3102 /* XXX should we randomise the initval? */
3103 }
3104
3105 /* Decide whether a filter should be exclusive or else should allow
3106 * delivery to additional recipients. Currently we decide that
3107 * filters for specific local unicast MAC and IP addresses are
3108 * exclusive.
3109 */
3110 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec)
3111 {
3112 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC &&
3113 !is_multicast_ether_addr(spec->loc_mac))
3114 return true;
3115
3116 if ((spec->match_flags &
3117 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) ==
3118 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) {
3119 if (spec->ether_type == htons(ETH_P_IP) &&
3120 !ipv4_is_multicast(spec->loc_host[0]))
3121 return true;
3122 if (spec->ether_type == htons(ETH_P_IPV6) &&
3123 ((const u8 *)spec->loc_host)[0] != 0xff)
3124 return true;
3125 }
3126
3127 return false;
3128 }
3129
3130 static struct efx_filter_spec *
3131 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table,
3132 unsigned int filter_idx)
3133 {
3134 return (struct efx_filter_spec *)(table->entry[filter_idx].spec &
3135 ~EFX_EF10_FILTER_FLAGS);
3136 }
3137
3138 static unsigned int
3139 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table,
3140 unsigned int filter_idx)
3141 {
3142 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS;
3143 }
3144
3145 static void
3146 efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table,
3147 unsigned int filter_idx,
3148 const struct efx_filter_spec *spec,
3149 unsigned int flags)
3150 {
3151 table->entry[filter_idx].spec = (unsigned long)spec | flags;
3152 }
3153
3154 static void efx_ef10_filter_push_prep(struct efx_nic *efx,
3155 const struct efx_filter_spec *spec,
3156 efx_dword_t *inbuf, u64 handle,
3157 bool replacing)
3158 {
3159 struct efx_ef10_nic_data *nic_data = efx->nic_data;
3160 u32 flags = spec->flags;
3161
3162 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN);
3163
3164 /* Remove RSS flag if we don't have an RSS context. */
3165 if (flags & EFX_FILTER_FLAG_RX_RSS &&
3166 spec->rss_context == EFX_FILTER_RSS_CONTEXT_DEFAULT &&
3167 nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID)
3168 flags &= ~EFX_FILTER_FLAG_RX_RSS;
3169
3170 if (replacing) {
3171 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3172 MC_CMD_FILTER_OP_IN_OP_REPLACE);
3173 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle);
3174 } else {
3175 u32 match_fields = 0;
3176
3177 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3178 efx_ef10_filter_is_exclusive(spec) ?
3179 MC_CMD_FILTER_OP_IN_OP_INSERT :
3180 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE);
3181
3182 /* Convert match flags and values. Unlike almost
3183 * everything else in MCDI, these fields are in
3184 * network byte order.
3185 */
3186 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG)
3187 match_fields |=
3188 is_multicast_ether_addr(spec->loc_mac) ?
3189 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN :
3190 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN;
3191 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3192 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3193 match_fields |= \
3194 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3195 mcdi_field ## _LBN; \
3196 BUILD_BUG_ON( \
3197 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3198 sizeof(spec->gen_field)); \
3199 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3200 &spec->gen_field, sizeof(spec->gen_field)); \
3201 }
3202 COPY_FIELD(REM_HOST, rem_host, SRC_IP);
3203 COPY_FIELD(LOC_HOST, loc_host, DST_IP);
3204 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC);
3205 COPY_FIELD(REM_PORT, rem_port, SRC_PORT);
3206 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC);
3207 COPY_FIELD(LOC_PORT, loc_port, DST_PORT);
3208 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE);
3209 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN);
3210 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN);
3211 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO);
3212 #undef COPY_FIELD
3213 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS,
3214 match_fields);
3215 }
3216
3217 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, nic_data->vport_id);
3218 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST,
3219 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3220 MC_CMD_FILTER_OP_IN_RX_DEST_DROP :
3221 MC_CMD_FILTER_OP_IN_RX_DEST_HOST);
3222 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DOMAIN, 0);
3223 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST,
3224 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT);
3225 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE,
3226 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ?
3227 0 : spec->dmaq_id);
3228 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE,
3229 (flags & EFX_FILTER_FLAG_RX_RSS) ?
3230 MC_CMD_FILTER_OP_IN_RX_MODE_RSS :
3231 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE);
3232 if (flags & EFX_FILTER_FLAG_RX_RSS)
3233 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT,
3234 spec->rss_context !=
3235 EFX_FILTER_RSS_CONTEXT_DEFAULT ?
3236 spec->rss_context : nic_data->rx_rss_context);
3237 }
3238
3239 static int efx_ef10_filter_push(struct efx_nic *efx,
3240 const struct efx_filter_spec *spec,
3241 u64 *handle, bool replacing)
3242 {
3243 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3244 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN);
3245 int rc;
3246
3247 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing);
3248 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3249 outbuf, sizeof(outbuf), NULL);
3250 if (rc == 0)
3251 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3252 if (rc == -ENOSPC)
3253 rc = -EBUSY; /* to match efx_farch_filter_insert() */
3254 return rc;
3255 }
3256
3257 static u32 efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec *spec)
3258 {
3259 unsigned int match_flags = spec->match_flags;
3260 u32 mcdi_flags = 0;
3261
3262 if (match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) {
3263 match_flags &= ~EFX_FILTER_MATCH_LOC_MAC_IG;
3264 mcdi_flags |=
3265 is_multicast_ether_addr(spec->loc_mac) ?
3266 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN) :
3267 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN);
3268 }
3269
3270 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) { \
3271 unsigned int old_match_flags = match_flags; \
3272 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
3273 if (match_flags != old_match_flags) \
3274 mcdi_flags |= \
3275 (1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3276 mcdi_field ## _LBN); \
3277 }
3278 MAP_FILTER_TO_MCDI_FLAG(REM_HOST, SRC_IP);
3279 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST, DST_IP);
3280 MAP_FILTER_TO_MCDI_FLAG(REM_MAC, SRC_MAC);
3281 MAP_FILTER_TO_MCDI_FLAG(REM_PORT, SRC_PORT);
3282 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC, DST_MAC);
3283 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT, DST_PORT);
3284 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE, ETHER_TYPE);
3285 MAP_FILTER_TO_MCDI_FLAG(INNER_VID, INNER_VLAN);
3286 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID, OUTER_VLAN);
3287 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO, IP_PROTO);
3288 #undef MAP_FILTER_TO_MCDI_FLAG
3289
3290 /* Did we map them all? */
3291 WARN_ON_ONCE(match_flags);
3292
3293 return mcdi_flags;
3294 }
3295
3296 static int efx_ef10_filter_pri(struct efx_ef10_filter_table *table,
3297 const struct efx_filter_spec *spec)
3298 {
3299 u32 mcdi_flags = efx_ef10_filter_mcdi_flags_from_spec(spec);
3300 unsigned int match_pri;
3301
3302 for (match_pri = 0;
3303 match_pri < table->rx_match_count;
3304 match_pri++)
3305 if (table->rx_match_mcdi_flags[match_pri] == mcdi_flags)
3306 return match_pri;
3307
3308 return -EPROTONOSUPPORT;
3309 }
3310
3311 static s32 efx_ef10_filter_insert(struct efx_nic *efx,
3312 struct efx_filter_spec *spec,
3313 bool replace_equal)
3314 {
3315 struct efx_ef10_filter_table *table = efx->filter_state;
3316 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3317 struct efx_filter_spec *saved_spec;
3318 unsigned int match_pri, hash;
3319 unsigned int priv_flags;
3320 bool replacing = false;
3321 int ins_index = -1;
3322 DEFINE_WAIT(wait);
3323 bool is_mc_recip;
3324 s32 rc;
3325
3326 /* For now, only support RX filters */
3327 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) !=
3328 EFX_FILTER_FLAG_RX)
3329 return -EINVAL;
3330
3331 rc = efx_ef10_filter_pri(table, spec);
3332 if (rc < 0)
3333 return rc;
3334 match_pri = rc;
3335
3336 hash = efx_ef10_filter_hash(spec);
3337 is_mc_recip = efx_filter_is_mc_recipient(spec);
3338 if (is_mc_recip)
3339 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT);
3340
3341 /* Find any existing filters with the same match tuple or
3342 * else a free slot to insert at. If any of them are busy,
3343 * we have to wait and retry.
3344 */
3345 for (;;) {
3346 unsigned int depth = 1;
3347 unsigned int i;
3348
3349 spin_lock_bh(&efx->filter_lock);
3350
3351 for (;;) {
3352 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3353 saved_spec = efx_ef10_filter_entry_spec(table, i);
3354
3355 if (!saved_spec) {
3356 if (ins_index < 0)
3357 ins_index = i;
3358 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3359 if (table->entry[i].spec &
3360 EFX_EF10_FILTER_FLAG_BUSY)
3361 break;
3362 if (spec->priority < saved_spec->priority &&
3363 spec->priority != EFX_FILTER_PRI_AUTO) {
3364 rc = -EPERM;
3365 goto out_unlock;
3366 }
3367 if (!is_mc_recip) {
3368 /* This is the only one */
3369 if (spec->priority ==
3370 saved_spec->priority &&
3371 !replace_equal) {
3372 rc = -EEXIST;
3373 goto out_unlock;
3374 }
3375 ins_index = i;
3376 goto found;
3377 } else if (spec->priority >
3378 saved_spec->priority ||
3379 (spec->priority ==
3380 saved_spec->priority &&
3381 replace_equal)) {
3382 if (ins_index < 0)
3383 ins_index = i;
3384 else
3385 __set_bit(depth, mc_rem_map);
3386 }
3387 }
3388
3389 /* Once we reach the maximum search depth, use
3390 * the first suitable slot or return -EBUSY if
3391 * there was none
3392 */
3393 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3394 if (ins_index < 0) {
3395 rc = -EBUSY;
3396 goto out_unlock;
3397 }
3398 goto found;
3399 }
3400
3401 ++depth;
3402 }
3403
3404 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3405 spin_unlock_bh(&efx->filter_lock);
3406 schedule();
3407 }
3408
3409 found:
3410 /* Create a software table entry if necessary, and mark it
3411 * busy. We might yet fail to insert, but any attempt to
3412 * insert a conflicting filter while we're waiting for the
3413 * firmware must find the busy entry.
3414 */
3415 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3416 if (saved_spec) {
3417 if (spec->priority == EFX_FILTER_PRI_AUTO &&
3418 saved_spec->priority >= EFX_FILTER_PRI_AUTO) {
3419 /* Just make sure it won't be removed */
3420 if (saved_spec->priority > EFX_FILTER_PRI_AUTO)
3421 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
3422 table->entry[ins_index].spec &=
3423 ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3424 rc = ins_index;
3425 goto out_unlock;
3426 }
3427 replacing = true;
3428 priv_flags = efx_ef10_filter_entry_flags(table, ins_index);
3429 } else {
3430 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3431 if (!saved_spec) {
3432 rc = -ENOMEM;
3433 goto out_unlock;
3434 }
3435 *saved_spec = *spec;
3436 priv_flags = 0;
3437 }
3438 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3439 priv_flags | EFX_EF10_FILTER_FLAG_BUSY);
3440
3441 /* Mark lower-priority multicast recipients busy prior to removal */
3442 if (is_mc_recip) {
3443 unsigned int depth, i;
3444
3445 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3446 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3447 if (test_bit(depth, mc_rem_map))
3448 table->entry[i].spec |=
3449 EFX_EF10_FILTER_FLAG_BUSY;
3450 }
3451 }
3452
3453 spin_unlock_bh(&efx->filter_lock);
3454
3455 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle,
3456 replacing);
3457
3458 /* Finalise the software table entry */
3459 spin_lock_bh(&efx->filter_lock);
3460 if (rc == 0) {
3461 if (replacing) {
3462 /* Update the fields that may differ */
3463 if (saved_spec->priority == EFX_FILTER_PRI_AUTO)
3464 saved_spec->flags |=
3465 EFX_FILTER_FLAG_RX_OVER_AUTO;
3466 saved_spec->priority = spec->priority;
3467 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO;
3468 saved_spec->flags |= spec->flags;
3469 saved_spec->rss_context = spec->rss_context;
3470 saved_spec->dmaq_id = spec->dmaq_id;
3471 }
3472 } else if (!replacing) {
3473 kfree(saved_spec);
3474 saved_spec = NULL;
3475 }
3476 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags);
3477
3478 /* Remove and finalise entries for lower-priority multicast
3479 * recipients
3480 */
3481 if (is_mc_recip) {
3482 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3483 unsigned int depth, i;
3484
3485 memset(inbuf, 0, sizeof(inbuf));
3486
3487 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) {
3488 if (!test_bit(depth, mc_rem_map))
3489 continue;
3490
3491 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3492 saved_spec = efx_ef10_filter_entry_spec(table, i);
3493 priv_flags = efx_ef10_filter_entry_flags(table, i);
3494
3495 if (rc == 0) {
3496 spin_unlock_bh(&efx->filter_lock);
3497 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3498 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3499 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3500 table->entry[i].handle);
3501 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3502 inbuf, sizeof(inbuf),
3503 NULL, 0, NULL);
3504 spin_lock_bh(&efx->filter_lock);
3505 }
3506
3507 if (rc == 0) {
3508 kfree(saved_spec);
3509 saved_spec = NULL;
3510 priv_flags = 0;
3511 } else {
3512 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY;
3513 }
3514 efx_ef10_filter_set_entry(table, i, saved_spec,
3515 priv_flags);
3516 }
3517 }
3518
3519 /* If successful, return the inserted filter ID */
3520 if (rc == 0)
3521 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index;
3522
3523 wake_up_all(&table->waitq);
3524 out_unlock:
3525 spin_unlock_bh(&efx->filter_lock);
3526 finish_wait(&table->waitq, &wait);
3527 return rc;
3528 }
3529
3530 static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx)
3531 {
3532 /* no need to do anything here on EF10 */
3533 }
3534
3535 /* Remove a filter.
3536 * If !by_index, remove by ID
3537 * If by_index, remove by index
3538 * Filter ID may come from userland and must be range-checked.
3539 */
3540 static int efx_ef10_filter_remove_internal(struct efx_nic *efx,
3541 unsigned int priority_mask,
3542 u32 filter_id, bool by_index)
3543 {
3544 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3545 struct efx_ef10_filter_table *table = efx->filter_state;
3546 MCDI_DECLARE_BUF(inbuf,
3547 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3548 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3549 struct efx_filter_spec *spec;
3550 DEFINE_WAIT(wait);
3551 int rc;
3552
3553 /* Find the software table entry and mark it busy. Don't
3554 * remove it yet; any attempt to update while we're waiting
3555 * for the firmware must find the busy entry.
3556 */
3557 for (;;) {
3558 spin_lock_bh(&efx->filter_lock);
3559 if (!(table->entry[filter_idx].spec &
3560 EFX_EF10_FILTER_FLAG_BUSY))
3561 break;
3562 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE);
3563 spin_unlock_bh(&efx->filter_lock);
3564 schedule();
3565 }
3566
3567 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3568 if (!spec ||
3569 (!by_index &&
3570 efx_ef10_filter_pri(table, spec) !=
3571 filter_id / HUNT_FILTER_TBL_ROWS)) {
3572 rc = -ENOENT;
3573 goto out_unlock;
3574 }
3575
3576 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO &&
3577 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) {
3578 /* Just remove flags */
3579 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO;
3580 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD;
3581 rc = 0;
3582 goto out_unlock;
3583 }
3584
3585 if (!(priority_mask & (1U << spec->priority))) {
3586 rc = -ENOENT;
3587 goto out_unlock;
3588 }
3589
3590 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3591 spin_unlock_bh(&efx->filter_lock);
3592
3593 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
3594 /* Reset to an automatic filter */
3595
3596 struct efx_filter_spec new_spec = *spec;
3597
3598 new_spec.priority = EFX_FILTER_PRI_AUTO;
3599 new_spec.flags = (EFX_FILTER_FLAG_RX |
3600 (efx_rss_enabled(efx) ?
3601 EFX_FILTER_FLAG_RX_RSS : 0));
3602 new_spec.dmaq_id = 0;
3603 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT;
3604 rc = efx_ef10_filter_push(efx, &new_spec,
3605 &table->entry[filter_idx].handle,
3606 true);
3607
3608 spin_lock_bh(&efx->filter_lock);
3609 if (rc == 0)
3610 *spec = new_spec;
3611 } else {
3612 /* Really remove the filter */
3613
3614 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3615 efx_ef10_filter_is_exclusive(spec) ?
3616 MC_CMD_FILTER_OP_IN_OP_REMOVE :
3617 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
3618 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3619 table->entry[filter_idx].handle);
3620 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP,
3621 inbuf, sizeof(inbuf), NULL, 0, NULL);
3622
3623 spin_lock_bh(&efx->filter_lock);
3624 if (rc == 0) {
3625 kfree(spec);
3626 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3627 }
3628 }
3629
3630 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3631 wake_up_all(&table->waitq);
3632 out_unlock:
3633 spin_unlock_bh(&efx->filter_lock);
3634 finish_wait(&table->waitq, &wait);
3635 return rc;
3636 }
3637
3638 static int efx_ef10_filter_remove_safe(struct efx_nic *efx,
3639 enum efx_filter_priority priority,
3640 u32 filter_id)
3641 {
3642 return efx_ef10_filter_remove_internal(efx, 1U << priority,
3643 filter_id, false);
3644 }
3645
3646 static u32 efx_ef10_filter_get_unsafe_id(struct efx_nic *efx, u32 filter_id)
3647 {
3648 return filter_id % HUNT_FILTER_TBL_ROWS;
3649 }
3650
3651 static void efx_ef10_filter_remove_unsafe(struct efx_nic *efx,
3652 enum efx_filter_priority priority,
3653 u32 filter_id)
3654 {
3655 if (filter_id == EFX_EF10_FILTER_ID_INVALID)
3656 return;
3657 efx_ef10_filter_remove_internal(efx, 1U << priority, filter_id, true);
3658 }
3659
3660 static int efx_ef10_filter_get_safe(struct efx_nic *efx,
3661 enum efx_filter_priority priority,
3662 u32 filter_id, struct efx_filter_spec *spec)
3663 {
3664 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS;
3665 struct efx_ef10_filter_table *table = efx->filter_state;
3666 const struct efx_filter_spec *saved_spec;
3667 int rc;
3668
3669 spin_lock_bh(&efx->filter_lock);
3670 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx);
3671 if (saved_spec && saved_spec->priority == priority &&
3672 efx_ef10_filter_pri(table, saved_spec) ==
3673 filter_id / HUNT_FILTER_TBL_ROWS) {
3674 *spec = *saved_spec;
3675 rc = 0;
3676 } else {
3677 rc = -ENOENT;
3678 }
3679 spin_unlock_bh(&efx->filter_lock);
3680 return rc;
3681 }
3682
3683 static int efx_ef10_filter_clear_rx(struct efx_nic *efx,
3684 enum efx_filter_priority priority)
3685 {
3686 unsigned int priority_mask;
3687 unsigned int i;
3688 int rc;
3689
3690 priority_mask = (((1U << (priority + 1)) - 1) &
3691 ~(1U << EFX_FILTER_PRI_AUTO));
3692
3693 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
3694 rc = efx_ef10_filter_remove_internal(efx, priority_mask,
3695 i, true);
3696 if (rc && rc != -ENOENT)
3697 return rc;
3698 }
3699
3700 return 0;
3701 }
3702
3703 static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx,
3704 enum efx_filter_priority priority)
3705 {
3706 struct efx_ef10_filter_table *table = efx->filter_state;
3707 unsigned int filter_idx;
3708 s32 count = 0;
3709
3710 spin_lock_bh(&efx->filter_lock);
3711 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3712 if (table->entry[filter_idx].spec &&
3713 efx_ef10_filter_entry_spec(table, filter_idx)->priority ==
3714 priority)
3715 ++count;
3716 }
3717 spin_unlock_bh(&efx->filter_lock);
3718 return count;
3719 }
3720
3721 static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx)
3722 {
3723 struct efx_ef10_filter_table *table = efx->filter_state;
3724
3725 return table->rx_match_count * HUNT_FILTER_TBL_ROWS;
3726 }
3727
3728 static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx,
3729 enum efx_filter_priority priority,
3730 u32 *buf, u32 size)
3731 {
3732 struct efx_ef10_filter_table *table = efx->filter_state;
3733 struct efx_filter_spec *spec;
3734 unsigned int filter_idx;
3735 s32 count = 0;
3736
3737 spin_lock_bh(&efx->filter_lock);
3738 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
3739 spec = efx_ef10_filter_entry_spec(table, filter_idx);
3740 if (spec && spec->priority == priority) {
3741 if (count == size) {
3742 count = -EMSGSIZE;
3743 break;
3744 }
3745 buf[count++] = (efx_ef10_filter_pri(table, spec) *
3746 HUNT_FILTER_TBL_ROWS +
3747 filter_idx);
3748 }
3749 }
3750 spin_unlock_bh(&efx->filter_lock);
3751 return count;
3752 }
3753
3754 #ifdef CONFIG_RFS_ACCEL
3755
3756 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete;
3757
3758 static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx,
3759 struct efx_filter_spec *spec)
3760 {
3761 struct efx_ef10_filter_table *table = efx->filter_state;
3762 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
3763 struct efx_filter_spec *saved_spec;
3764 unsigned int hash, i, depth = 1;
3765 bool replacing = false;
3766 int ins_index = -1;
3767 u64 cookie;
3768 s32 rc;
3769
3770 /* Must be an RX filter without RSS and not for a multicast
3771 * destination address (RFS only works for connected sockets).
3772 * These restrictions allow us to pass only a tiny amount of
3773 * data through to the completion function.
3774 */
3775 EFX_WARN_ON_PARANOID(spec->flags !=
3776 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER));
3777 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT);
3778 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec));
3779
3780 hash = efx_ef10_filter_hash(spec);
3781
3782 spin_lock_bh(&efx->filter_lock);
3783
3784 /* Find any existing filter with the same match tuple or else
3785 * a free slot to insert at. If an existing filter is busy,
3786 * we have to give up.
3787 */
3788 for (;;) {
3789 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1);
3790 saved_spec = efx_ef10_filter_entry_spec(table, i);
3791
3792 if (!saved_spec) {
3793 if (ins_index < 0)
3794 ins_index = i;
3795 } else if (efx_ef10_filter_equal(spec, saved_spec)) {
3796 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) {
3797 rc = -EBUSY;
3798 goto fail_unlock;
3799 }
3800 if (spec->priority < saved_spec->priority) {
3801 rc = -EPERM;
3802 goto fail_unlock;
3803 }
3804 ins_index = i;
3805 break;
3806 }
3807
3808 /* Once we reach the maximum search depth, use the
3809 * first suitable slot or return -EBUSY if there was
3810 * none
3811 */
3812 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) {
3813 if (ins_index < 0) {
3814 rc = -EBUSY;
3815 goto fail_unlock;
3816 }
3817 break;
3818 }
3819
3820 ++depth;
3821 }
3822
3823 /* Create a software table entry if necessary, and mark it
3824 * busy. We might yet fail to insert, but any attempt to
3825 * insert a conflicting filter while we're waiting for the
3826 * firmware must find the busy entry.
3827 */
3828 saved_spec = efx_ef10_filter_entry_spec(table, ins_index);
3829 if (saved_spec) {
3830 replacing = true;
3831 } else {
3832 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC);
3833 if (!saved_spec) {
3834 rc = -ENOMEM;
3835 goto fail_unlock;
3836 }
3837 *saved_spec = *spec;
3838 }
3839 efx_ef10_filter_set_entry(table, ins_index, saved_spec,
3840 EFX_EF10_FILTER_FLAG_BUSY);
3841
3842 spin_unlock_bh(&efx->filter_lock);
3843
3844 /* Pack up the variables needed on completion */
3845 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id;
3846
3847 efx_ef10_filter_push_prep(efx, spec, inbuf,
3848 table->entry[ins_index].handle, replacing);
3849 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf),
3850 MC_CMD_FILTER_OP_OUT_LEN,
3851 efx_ef10_filter_rfs_insert_complete, cookie);
3852
3853 return ins_index;
3854
3855 fail_unlock:
3856 spin_unlock_bh(&efx->filter_lock);
3857 return rc;
3858 }
3859
3860 static void
3861 efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie,
3862 int rc, efx_dword_t *outbuf,
3863 size_t outlen_actual)
3864 {
3865 struct efx_ef10_filter_table *table = efx->filter_state;
3866 unsigned int ins_index, dmaq_id;
3867 struct efx_filter_spec *spec;
3868 bool replacing;
3869
3870 /* Unpack the cookie */
3871 replacing = cookie >> 31;
3872 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1);
3873 dmaq_id = cookie & 0xffff;
3874
3875 spin_lock_bh(&efx->filter_lock);
3876 spec = efx_ef10_filter_entry_spec(table, ins_index);
3877 if (rc == 0) {
3878 table->entry[ins_index].handle =
3879 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE);
3880 if (replacing)
3881 spec->dmaq_id = dmaq_id;
3882 } else if (!replacing) {
3883 kfree(spec);
3884 spec = NULL;
3885 }
3886 efx_ef10_filter_set_entry(table, ins_index, spec, 0);
3887 spin_unlock_bh(&efx->filter_lock);
3888
3889 wake_up_all(&table->waitq);
3890 }
3891
3892 static void
3893 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3894 unsigned long filter_idx,
3895 int rc, efx_dword_t *outbuf,
3896 size_t outlen_actual);
3897
3898 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
3899 unsigned int filter_idx)
3900 {
3901 struct efx_ef10_filter_table *table = efx->filter_state;
3902 struct efx_filter_spec *spec =
3903 efx_ef10_filter_entry_spec(table, filter_idx);
3904 MCDI_DECLARE_BUF(inbuf,
3905 MC_CMD_FILTER_OP_IN_HANDLE_OFST +
3906 MC_CMD_FILTER_OP_IN_HANDLE_LEN);
3907
3908 if (!spec ||
3909 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) ||
3910 spec->priority != EFX_FILTER_PRI_HINT ||
3911 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id,
3912 flow_id, filter_idx))
3913 return false;
3914
3915 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
3916 MC_CMD_FILTER_OP_IN_OP_REMOVE);
3917 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
3918 table->entry[filter_idx].handle);
3919 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0,
3920 efx_ef10_filter_rfs_expire_complete, filter_idx))
3921 return false;
3922
3923 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
3924 return true;
3925 }
3926
3927 static void
3928 efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx,
3929 unsigned long filter_idx,
3930 int rc, efx_dword_t *outbuf,
3931 size_t outlen_actual)
3932 {
3933 struct efx_ef10_filter_table *table = efx->filter_state;
3934 struct efx_filter_spec *spec =
3935 efx_ef10_filter_entry_spec(table, filter_idx);
3936
3937 spin_lock_bh(&efx->filter_lock);
3938 if (rc == 0) {
3939 kfree(spec);
3940 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
3941 }
3942 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY;
3943 wake_up_all(&table->waitq);
3944 spin_unlock_bh(&efx->filter_lock);
3945 }
3946
3947 #endif /* CONFIG_RFS_ACCEL */
3948
3949 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags)
3950 {
3951 int match_flags = 0;
3952
3953 #define MAP_FLAG(gen_flag, mcdi_field) { \
3954 u32 old_mcdi_flags = mcdi_flags; \
3955 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3956 mcdi_field ## _LBN); \
3957 if (mcdi_flags != old_mcdi_flags) \
3958 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3959 }
3960 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST);
3961 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST);
3962 MAP_FLAG(REM_HOST, SRC_IP);
3963 MAP_FLAG(LOC_HOST, DST_IP);
3964 MAP_FLAG(REM_MAC, SRC_MAC);
3965 MAP_FLAG(REM_PORT, SRC_PORT);
3966 MAP_FLAG(LOC_MAC, DST_MAC);
3967 MAP_FLAG(LOC_PORT, DST_PORT);
3968 MAP_FLAG(ETHER_TYPE, ETHER_TYPE);
3969 MAP_FLAG(INNER_VID, INNER_VLAN);
3970 MAP_FLAG(OUTER_VID, OUTER_VLAN);
3971 MAP_FLAG(IP_PROTO, IP_PROTO);
3972 #undef MAP_FLAG
3973
3974 /* Did we map them all? */
3975 if (mcdi_flags)
3976 return -EINVAL;
3977
3978 return match_flags;
3979 }
3980
3981 static void efx_ef10_filter_cleanup_vlans(struct efx_nic *efx)
3982 {
3983 struct efx_ef10_filter_table *table = efx->filter_state;
3984 struct efx_ef10_filter_vlan *vlan, *next_vlan;
3985
3986 /* See comment in efx_ef10_filter_table_remove() */
3987 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
3988 return;
3989
3990 if (!table)
3991 return;
3992
3993 list_for_each_entry_safe(vlan, next_vlan, &table->vlan_list, list)
3994 efx_ef10_filter_del_vlan_internal(efx, vlan);
3995 }
3996
3997 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table *table,
3998 enum efx_filter_match_flags match_flags)
3999 {
4000 unsigned int match_pri;
4001 int mf;
4002
4003 for (match_pri = 0;
4004 match_pri < table->rx_match_count;
4005 match_pri++) {
4006 mf = efx_ef10_filter_match_flags_from_mcdi(
4007 table->rx_match_mcdi_flags[match_pri]);
4008 if (mf == match_flags)
4009 return true;
4010 }
4011
4012 return false;
4013 }
4014
4015 static int efx_ef10_filter_table_probe(struct efx_nic *efx)
4016 {
4017 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN);
4018 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX);
4019 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4020 struct net_device *net_dev = efx->net_dev;
4021 unsigned int pd_match_pri, pd_match_count;
4022 struct efx_ef10_filter_table *table;
4023 struct efx_ef10_vlan *vlan;
4024 size_t outlen;
4025 int rc;
4026
4027 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4028 return -EINVAL;
4029
4030 if (efx->filter_state) /* already probed */
4031 return 0;
4032
4033 table = kzalloc(sizeof(*table), GFP_KERNEL);
4034 if (!table)
4035 return -ENOMEM;
4036
4037 /* Find out which RX filter types are supported, and their priorities */
4038 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP,
4039 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES);
4040 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO,
4041 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf),
4042 &outlen);
4043 if (rc)
4044 goto fail;
4045 pd_match_count = MCDI_VAR_ARRAY_LEN(
4046 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES);
4047 table->rx_match_count = 0;
4048
4049 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) {
4050 u32 mcdi_flags =
4051 MCDI_ARRAY_DWORD(
4052 outbuf,
4053 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES,
4054 pd_match_pri);
4055 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags);
4056 if (rc < 0) {
4057 netif_dbg(efx, probe, efx->net_dev,
4058 "%s: fw flags %#x pri %u not supported in driver\n",
4059 __func__, mcdi_flags, pd_match_pri);
4060 } else {
4061 netif_dbg(efx, probe, efx->net_dev,
4062 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4063 __func__, mcdi_flags, pd_match_pri,
4064 rc, table->rx_match_count);
4065 table->rx_match_mcdi_flags[table->rx_match_count] = mcdi_flags;
4066 table->rx_match_count++;
4067 }
4068 }
4069
4070 if ((efx_supported_features(efx) & NETIF_F_HW_VLAN_CTAG_FILTER) &&
4071 !(efx_ef10_filter_match_supported(table,
4072 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC)) &&
4073 efx_ef10_filter_match_supported(table,
4074 (EFX_FILTER_MATCH_OUTER_VID | EFX_FILTER_MATCH_LOC_MAC_IG)))) {
4075 netif_info(efx, probe, net_dev,
4076 "VLAN filters are not supported in this firmware variant\n");
4077 net_dev->features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4078 efx->fixed_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4079 net_dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4080 }
4081
4082 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry));
4083 if (!table->entry) {
4084 rc = -ENOMEM;
4085 goto fail;
4086 }
4087
4088 table->mc_promisc_last = false;
4089 table->vlan_filter =
4090 !!(efx->net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4091 INIT_LIST_HEAD(&table->vlan_list);
4092
4093 efx->filter_state = table;
4094 init_waitqueue_head(&table->waitq);
4095
4096 list_for_each_entry(vlan, &nic_data->vlan_list, list) {
4097 rc = efx_ef10_filter_add_vlan(efx, vlan->vid);
4098 if (rc)
4099 goto fail_add_vlan;
4100 }
4101
4102 return 0;
4103
4104 fail_add_vlan:
4105 efx_ef10_filter_cleanup_vlans(efx);
4106 efx->filter_state = NULL;
4107 fail:
4108 kfree(table);
4109 return rc;
4110 }
4111
4112 /* Caller must hold efx->filter_sem for read if race against
4113 * efx_ef10_filter_table_remove() is possible
4114 */
4115 static void efx_ef10_filter_table_restore(struct efx_nic *efx)
4116 {
4117 struct efx_ef10_filter_table *table = efx->filter_state;
4118 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4119 struct efx_filter_spec *spec;
4120 unsigned int filter_idx;
4121 bool failed = false;
4122 int rc;
4123
4124 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4125
4126 if (!nic_data->must_restore_filters)
4127 return;
4128
4129 if (!table)
4130 return;
4131
4132 spin_lock_bh(&efx->filter_lock);
4133
4134 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4135 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4136 if (!spec)
4137 continue;
4138
4139 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY;
4140 spin_unlock_bh(&efx->filter_lock);
4141
4142 rc = efx_ef10_filter_push(efx, spec,
4143 &table->entry[filter_idx].handle,
4144 false);
4145 if (rc)
4146 failed = true;
4147
4148 spin_lock_bh(&efx->filter_lock);
4149 if (rc) {
4150 kfree(spec);
4151 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0);
4152 } else {
4153 table->entry[filter_idx].spec &=
4154 ~EFX_EF10_FILTER_FLAG_BUSY;
4155 }
4156 }
4157
4158 spin_unlock_bh(&efx->filter_lock);
4159
4160 if (failed)
4161 netif_err(efx, hw, efx->net_dev,
4162 "unable to restore all filters\n");
4163 else
4164 nic_data->must_restore_filters = false;
4165 }
4166
4167 static void efx_ef10_filter_table_remove(struct efx_nic *efx)
4168 {
4169 struct efx_ef10_filter_table *table = efx->filter_state;
4170 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN);
4171 struct efx_filter_spec *spec;
4172 unsigned int filter_idx;
4173 int rc;
4174
4175 efx_ef10_filter_cleanup_vlans(efx);
4176 efx->filter_state = NULL;
4177 /* If we were called without locking, then it's not safe to free
4178 * the table as others might be using it. So we just WARN, leak
4179 * the memory, and potentially get an inconsistent filter table
4180 * state.
4181 * This should never actually happen.
4182 */
4183 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4184 return;
4185
4186 if (!table)
4187 return;
4188
4189 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) {
4190 spec = efx_ef10_filter_entry_spec(table, filter_idx);
4191 if (!spec)
4192 continue;
4193
4194 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP,
4195 efx_ef10_filter_is_exclusive(spec) ?
4196 MC_CMD_FILTER_OP_IN_OP_REMOVE :
4197 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE);
4198 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE,
4199 table->entry[filter_idx].handle);
4200 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FILTER_OP, inbuf,
4201 sizeof(inbuf), NULL, 0, NULL);
4202 if (rc)
4203 netif_info(efx, drv, efx->net_dev,
4204 "%s: filter %04x remove failed\n",
4205 __func__, filter_idx);
4206 kfree(spec);
4207 }
4208
4209 vfree(table->entry);
4210 kfree(table);
4211 }
4212
4213 static void efx_ef10_filter_mark_one_old(struct efx_nic *efx, uint16_t *id)
4214 {
4215 struct efx_ef10_filter_table *table = efx->filter_state;
4216 unsigned int filter_idx;
4217
4218 if (*id != EFX_EF10_FILTER_ID_INVALID) {
4219 filter_idx = efx_ef10_filter_get_unsafe_id(efx, *id);
4220 if (!table->entry[filter_idx].spec)
4221 netif_dbg(efx, drv, efx->net_dev,
4222 "marked null spec old %04x:%04x\n", *id,
4223 filter_idx);
4224 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD;
4225 *id = EFX_EF10_FILTER_ID_INVALID;
4226 }
4227 }
4228
4229 /* Mark old per-VLAN filters that may need to be removed */
4230 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic *efx,
4231 struct efx_ef10_filter_vlan *vlan)
4232 {
4233 struct efx_ef10_filter_table *table = efx->filter_state;
4234 unsigned int i;
4235
4236 for (i = 0; i < table->dev_uc_count; i++)
4237 efx_ef10_filter_mark_one_old(efx, &vlan->uc[i]);
4238 for (i = 0; i < table->dev_mc_count; i++)
4239 efx_ef10_filter_mark_one_old(efx, &vlan->mc[i]);
4240 efx_ef10_filter_mark_one_old(efx, &vlan->ucdef);
4241 efx_ef10_filter_mark_one_old(efx, &vlan->bcast);
4242 efx_ef10_filter_mark_one_old(efx, &vlan->mcdef);
4243 }
4244
4245 /* Mark old filters that may need to be removed.
4246 * Caller must hold efx->filter_sem for read if race against
4247 * efx_ef10_filter_table_remove() is possible
4248 */
4249 static void efx_ef10_filter_mark_old(struct efx_nic *efx)
4250 {
4251 struct efx_ef10_filter_table *table = efx->filter_state;
4252 struct efx_ef10_filter_vlan *vlan;
4253
4254 spin_lock_bh(&efx->filter_lock);
4255 list_for_each_entry(vlan, &table->vlan_list, list)
4256 _efx_ef10_filter_vlan_mark_old(efx, vlan);
4257 spin_unlock_bh(&efx->filter_lock);
4258 }
4259
4260 static void efx_ef10_filter_uc_addr_list(struct efx_nic *efx)
4261 {
4262 struct efx_ef10_filter_table *table = efx->filter_state;
4263 struct net_device *net_dev = efx->net_dev;
4264 struct netdev_hw_addr *uc;
4265 int addr_count;
4266 unsigned int i;
4267
4268 addr_count = netdev_uc_count(net_dev);
4269 table->uc_promisc = !!(net_dev->flags & IFF_PROMISC);
4270 table->dev_uc_count = 1 + addr_count;
4271 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr);
4272 i = 1;
4273 netdev_for_each_uc_addr(uc, net_dev) {
4274 if (i >= EFX_EF10_FILTER_DEV_UC_MAX) {
4275 table->uc_promisc = true;
4276 break;
4277 }
4278 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr);
4279 i++;
4280 }
4281 }
4282
4283 static void efx_ef10_filter_mc_addr_list(struct efx_nic *efx)
4284 {
4285 struct efx_ef10_filter_table *table = efx->filter_state;
4286 struct net_device *net_dev = efx->net_dev;
4287 struct netdev_hw_addr *mc;
4288 unsigned int i, addr_count;
4289
4290 table->mc_promisc = !!(net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI));
4291
4292 addr_count = netdev_mc_count(net_dev);
4293 i = 0;
4294 netdev_for_each_mc_addr(mc, net_dev) {
4295 if (i >= EFX_EF10_FILTER_DEV_MC_MAX) {
4296 table->mc_promisc = true;
4297 break;
4298 }
4299 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr);
4300 i++;
4301 }
4302
4303 table->dev_mc_count = i;
4304 }
4305
4306 static int efx_ef10_filter_insert_addr_list(struct efx_nic *efx,
4307 struct efx_ef10_filter_vlan *vlan,
4308 bool multicast, bool rollback)
4309 {
4310 struct efx_ef10_filter_table *table = efx->filter_state;
4311 struct efx_ef10_dev_addr *addr_list;
4312 enum efx_filter_flags filter_flags;
4313 struct efx_filter_spec spec;
4314 u8 baddr[ETH_ALEN];
4315 unsigned int i, j;
4316 int addr_count;
4317 u16 *ids;
4318 int rc;
4319
4320 if (multicast) {
4321 addr_list = table->dev_mc_list;
4322 addr_count = table->dev_mc_count;
4323 ids = vlan->mc;
4324 } else {
4325 addr_list = table->dev_uc_list;
4326 addr_count = table->dev_uc_count;
4327 ids = vlan->uc;
4328 }
4329
4330 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4331
4332 /* Insert/renew filters */
4333 for (i = 0; i < addr_count; i++) {
4334 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4335 efx_filter_set_eth_local(&spec, vlan->vid, addr_list[i].addr);
4336 rc = efx_ef10_filter_insert(efx, &spec, true);
4337 if (rc < 0) {
4338 if (rollback) {
4339 netif_info(efx, drv, efx->net_dev,
4340 "efx_ef10_filter_insert failed rc=%d\n",
4341 rc);
4342 /* Fall back to promiscuous */
4343 for (j = 0; j < i; j++) {
4344 efx_ef10_filter_remove_unsafe(
4345 efx, EFX_FILTER_PRI_AUTO,
4346 ids[j]);
4347 ids[j] = EFX_EF10_FILTER_ID_INVALID;
4348 }
4349 return rc;
4350 } else {
4351 /* mark as not inserted, and carry on */
4352 rc = EFX_EF10_FILTER_ID_INVALID;
4353 }
4354 }
4355 ids[i] = efx_ef10_filter_get_unsafe_id(efx, rc);
4356 }
4357
4358 if (multicast && rollback) {
4359 /* Also need an Ethernet broadcast filter */
4360 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4361 eth_broadcast_addr(baddr);
4362 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
4363 rc = efx_ef10_filter_insert(efx, &spec, true);
4364 if (rc < 0) {
4365 netif_warn(efx, drv, efx->net_dev,
4366 "Broadcast filter insert failed rc=%d\n", rc);
4367 /* Fall back to promiscuous */
4368 for (j = 0; j < i; j++) {
4369 efx_ef10_filter_remove_unsafe(
4370 efx, EFX_FILTER_PRI_AUTO,
4371 ids[j]);
4372 ids[j] = EFX_EF10_FILTER_ID_INVALID;
4373 }
4374 return rc;
4375 } else {
4376 EFX_WARN_ON_PARANOID(vlan->bcast !=
4377 EFX_EF10_FILTER_ID_INVALID);
4378 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
4379 }
4380 }
4381
4382 return 0;
4383 }
4384
4385 static int efx_ef10_filter_insert_def(struct efx_nic *efx,
4386 struct efx_ef10_filter_vlan *vlan,
4387 bool multicast, bool rollback)
4388 {
4389 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4390 enum efx_filter_flags filter_flags;
4391 struct efx_filter_spec spec;
4392 u8 baddr[ETH_ALEN];
4393 int rc;
4394
4395 filter_flags = efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0;
4396
4397 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, 0);
4398
4399 if (multicast)
4400 efx_filter_set_mc_def(&spec);
4401 else
4402 efx_filter_set_uc_def(&spec);
4403
4404 if (vlan->vid != EFX_FILTER_VID_UNSPEC)
4405 efx_filter_set_eth_local(&spec, vlan->vid, NULL);
4406
4407 rc = efx_ef10_filter_insert(efx, &spec, true);
4408 if (rc < 0) {
4409 netif_printk(efx, drv, rc == -EPERM ? KERN_DEBUG : KERN_WARNING,
4410 efx->net_dev,
4411 "%scast mismatch filter insert failed rc=%d\n",
4412 multicast ? "Multi" : "Uni", rc);
4413 } else if (multicast) {
4414 EFX_WARN_ON_PARANOID(vlan->mcdef != EFX_EF10_FILTER_ID_INVALID);
4415 vlan->mcdef = efx_ef10_filter_get_unsafe_id(efx, rc);
4416 if (!nic_data->workaround_26807) {
4417 /* Also need an Ethernet broadcast filter */
4418 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO,
4419 filter_flags, 0);
4420 eth_broadcast_addr(baddr);
4421 efx_filter_set_eth_local(&spec, vlan->vid, baddr);
4422 rc = efx_ef10_filter_insert(efx, &spec, true);
4423 if (rc < 0) {
4424 netif_warn(efx, drv, efx->net_dev,
4425 "Broadcast filter insert failed rc=%d\n",
4426 rc);
4427 if (rollback) {
4428 /* Roll back the mc_def filter */
4429 efx_ef10_filter_remove_unsafe(
4430 efx, EFX_FILTER_PRI_AUTO,
4431 vlan->mcdef);
4432 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
4433 return rc;
4434 }
4435 } else {
4436 EFX_WARN_ON_PARANOID(vlan->bcast !=
4437 EFX_EF10_FILTER_ID_INVALID);
4438 vlan->bcast = efx_ef10_filter_get_unsafe_id(efx, rc);
4439 }
4440 }
4441 rc = 0;
4442 } else {
4443 EFX_WARN_ON_PARANOID(vlan->ucdef != EFX_EF10_FILTER_ID_INVALID);
4444 vlan->ucdef = rc;
4445 rc = 0;
4446 }
4447 return rc;
4448 }
4449
4450 /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4451 * flag or removes these filters, we don't need to hold the filter_lock while
4452 * scanning for these filters.
4453 */
4454 static void efx_ef10_filter_remove_old(struct efx_nic *efx)
4455 {
4456 struct efx_ef10_filter_table *table = efx->filter_state;
4457 int remove_failed = 0;
4458 int remove_noent = 0;
4459 int rc;
4460 int i;
4461
4462 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) {
4463 if (ACCESS_ONCE(table->entry[i].spec) &
4464 EFX_EF10_FILTER_FLAG_AUTO_OLD) {
4465 rc = efx_ef10_filter_remove_internal(efx,
4466 1U << EFX_FILTER_PRI_AUTO, i, true);
4467 if (rc == -ENOENT)
4468 remove_noent++;
4469 else if (rc)
4470 remove_failed++;
4471 }
4472 }
4473
4474 if (remove_failed)
4475 netif_info(efx, drv, efx->net_dev,
4476 "%s: failed to remove %d filters\n",
4477 __func__, remove_failed);
4478 if (remove_noent)
4479 netif_info(efx, drv, efx->net_dev,
4480 "%s: failed to remove %d non-existent filters\n",
4481 __func__, remove_noent);
4482 }
4483
4484 static int efx_ef10_vport_set_mac_address(struct efx_nic *efx)
4485 {
4486 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4487 u8 mac_old[ETH_ALEN];
4488 int rc, rc2;
4489
4490 /* Only reconfigure a PF-created vport */
4491 if (is_zero_ether_addr(nic_data->vport_mac))
4492 return 0;
4493
4494 efx_device_detach_sync(efx);
4495 efx_net_stop(efx->net_dev);
4496 down_write(&efx->filter_sem);
4497 efx_ef10_filter_table_remove(efx);
4498 up_write(&efx->filter_sem);
4499
4500 rc = efx_ef10_vadaptor_free(efx, nic_data->vport_id);
4501 if (rc)
4502 goto restore_filters;
4503
4504 ether_addr_copy(mac_old, nic_data->vport_mac);
4505 rc = efx_ef10_vport_del_mac(efx, nic_data->vport_id,
4506 nic_data->vport_mac);
4507 if (rc)
4508 goto restore_vadaptor;
4509
4510 rc = efx_ef10_vport_add_mac(efx, nic_data->vport_id,
4511 efx->net_dev->dev_addr);
4512 if (!rc) {
4513 ether_addr_copy(nic_data->vport_mac, efx->net_dev->dev_addr);
4514 } else {
4515 rc2 = efx_ef10_vport_add_mac(efx, nic_data->vport_id, mac_old);
4516 if (rc2) {
4517 /* Failed to add original MAC, so clear vport_mac */
4518 eth_zero_addr(nic_data->vport_mac);
4519 goto reset_nic;
4520 }
4521 }
4522
4523 restore_vadaptor:
4524 rc2 = efx_ef10_vadaptor_alloc(efx, nic_data->vport_id);
4525 if (rc2)
4526 goto reset_nic;
4527 restore_filters:
4528 down_write(&efx->filter_sem);
4529 rc2 = efx_ef10_filter_table_probe(efx);
4530 up_write(&efx->filter_sem);
4531 if (rc2)
4532 goto reset_nic;
4533
4534 rc2 = efx_net_open(efx->net_dev);
4535 if (rc2)
4536 goto reset_nic;
4537
4538 netif_device_attach(efx->net_dev);
4539
4540 return rc;
4541
4542 reset_nic:
4543 netif_err(efx, drv, efx->net_dev,
4544 "Failed to restore when changing MAC address - scheduling reset\n");
4545 efx_schedule_reset(efx, RESET_TYPE_DATAPATH);
4546
4547 return rc ? rc : rc2;
4548 }
4549
4550 /* Caller must hold efx->filter_sem for read if race against
4551 * efx_ef10_filter_table_remove() is possible
4552 */
4553 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic *efx,
4554 struct efx_ef10_filter_vlan *vlan)
4555 {
4556 struct efx_ef10_filter_table *table = efx->filter_state;
4557 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4558
4559 /* Do not install unspecified VID if VLAN filtering is enabled.
4560 * Do not install all specified VIDs if VLAN filtering is disabled.
4561 */
4562 if ((vlan->vid == EFX_FILTER_VID_UNSPEC) == table->vlan_filter)
4563 return;
4564
4565 /* Insert/renew unicast filters */
4566 if (table->uc_promisc) {
4567 efx_ef10_filter_insert_def(efx, vlan, false, false);
4568 efx_ef10_filter_insert_addr_list(efx, vlan, false, false);
4569 } else {
4570 /* If any of the filters failed to insert, fall back to
4571 * promiscuous mode - add in the uc_def filter. But keep
4572 * our individual unicast filters.
4573 */
4574 if (efx_ef10_filter_insert_addr_list(efx, vlan, false, false))
4575 efx_ef10_filter_insert_def(efx, vlan, false, false);
4576 }
4577
4578 /* Insert/renew multicast filters */
4579 /* If changing promiscuous state with cascaded multicast filters, remove
4580 * old filters first, so that packets are dropped rather than duplicated
4581 */
4582 if (nic_data->workaround_26807 &&
4583 table->mc_promisc_last != table->mc_promisc)
4584 efx_ef10_filter_remove_old(efx);
4585 if (table->mc_promisc) {
4586 if (nic_data->workaround_26807) {
4587 /* If we failed to insert promiscuous filters, rollback
4588 * and fall back to individual multicast filters
4589 */
4590 if (efx_ef10_filter_insert_def(efx, vlan, true, true)) {
4591 /* Changing promisc state, so remove old filters */
4592 efx_ef10_filter_remove_old(efx);
4593 efx_ef10_filter_insert_addr_list(efx, vlan,
4594 true, false);
4595 }
4596 } else {
4597 /* If we failed to insert promiscuous filters, don't
4598 * rollback. Regardless, also insert the mc_list
4599 */
4600 efx_ef10_filter_insert_def(efx, vlan, true, false);
4601 efx_ef10_filter_insert_addr_list(efx, vlan, true, false);
4602 }
4603 } else {
4604 /* If any filters failed to insert, rollback and fall back to
4605 * promiscuous mode - mc_def filter and maybe broadcast. If
4606 * that fails, roll back again and insert as many of our
4607 * individual multicast filters as we can.
4608 */
4609 if (efx_ef10_filter_insert_addr_list(efx, vlan, true, true)) {
4610 /* Changing promisc state, so remove old filters */
4611 if (nic_data->workaround_26807)
4612 efx_ef10_filter_remove_old(efx);
4613 if (efx_ef10_filter_insert_def(efx, vlan, true, true))
4614 efx_ef10_filter_insert_addr_list(efx, vlan,
4615 true, false);
4616 }
4617 }
4618 }
4619
4620 /* Caller must hold efx->filter_sem for read if race against
4621 * efx_ef10_filter_table_remove() is possible
4622 */
4623 static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx)
4624 {
4625 struct efx_ef10_filter_table *table = efx->filter_state;
4626 struct net_device *net_dev = efx->net_dev;
4627 struct efx_ef10_filter_vlan *vlan;
4628 bool vlan_filter;
4629
4630 if (!efx_dev_registered(efx))
4631 return;
4632
4633 if (!table)
4634 return;
4635
4636 efx_ef10_filter_mark_old(efx);
4637
4638 /* Copy/convert the address lists; add the primary station
4639 * address and broadcast address
4640 */
4641 netif_addr_lock_bh(net_dev);
4642 efx_ef10_filter_uc_addr_list(efx);
4643 efx_ef10_filter_mc_addr_list(efx);
4644 netif_addr_unlock_bh(net_dev);
4645
4646 /* If VLAN filtering changes, all old filters are finally removed.
4647 * Do it in advance to avoid conflicts for unicast untagged and
4648 * VLAN 0 tagged filters.
4649 */
4650 vlan_filter = !!(net_dev->features & NETIF_F_HW_VLAN_CTAG_FILTER);
4651 if (table->vlan_filter != vlan_filter) {
4652 table->vlan_filter = vlan_filter;
4653 efx_ef10_filter_remove_old(efx);
4654 }
4655
4656 list_for_each_entry(vlan, &table->vlan_list, list)
4657 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
4658
4659 efx_ef10_filter_remove_old(efx);
4660 table->mc_promisc_last = table->mc_promisc;
4661 }
4662
4663 static struct efx_ef10_filter_vlan *efx_ef10_filter_find_vlan(struct efx_nic *efx, u16 vid)
4664 {
4665 struct efx_ef10_filter_table *table = efx->filter_state;
4666 struct efx_ef10_filter_vlan *vlan;
4667
4668 WARN_ON(!rwsem_is_locked(&efx->filter_sem));
4669
4670 list_for_each_entry(vlan, &table->vlan_list, list) {
4671 if (vlan->vid == vid)
4672 return vlan;
4673 }
4674
4675 return NULL;
4676 }
4677
4678 static int efx_ef10_filter_add_vlan(struct efx_nic *efx, u16 vid)
4679 {
4680 struct efx_ef10_filter_table *table = efx->filter_state;
4681 struct efx_ef10_filter_vlan *vlan;
4682 unsigned int i;
4683
4684 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4685 return -EINVAL;
4686
4687 vlan = efx_ef10_filter_find_vlan(efx, vid);
4688 if (WARN_ON(vlan)) {
4689 netif_err(efx, drv, efx->net_dev,
4690 "VLAN %u already added\n", vid);
4691 return -EALREADY;
4692 }
4693
4694 vlan = kzalloc(sizeof(*vlan), GFP_KERNEL);
4695 if (!vlan)
4696 return -ENOMEM;
4697
4698 vlan->vid = vid;
4699
4700 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
4701 vlan->uc[i] = EFX_EF10_FILTER_ID_INVALID;
4702 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
4703 vlan->mc[i] = EFX_EF10_FILTER_ID_INVALID;
4704 vlan->ucdef = EFX_EF10_FILTER_ID_INVALID;
4705 vlan->bcast = EFX_EF10_FILTER_ID_INVALID;
4706 vlan->mcdef = EFX_EF10_FILTER_ID_INVALID;
4707
4708 list_add_tail(&vlan->list, &table->vlan_list);
4709
4710 if (efx_dev_registered(efx))
4711 efx_ef10_filter_vlan_sync_rx_mode(efx, vlan);
4712
4713 return 0;
4714 }
4715
4716 static void efx_ef10_filter_del_vlan_internal(struct efx_nic *efx,
4717 struct efx_ef10_filter_vlan *vlan)
4718 {
4719 unsigned int i;
4720
4721 /* See comment in efx_ef10_filter_table_remove() */
4722 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4723 return;
4724
4725 list_del(&vlan->list);
4726
4727 for (i = 0; i < ARRAY_SIZE(vlan->uc); i++)
4728 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
4729 vlan->uc[i]);
4730 for (i = 0; i < ARRAY_SIZE(vlan->mc); i++)
4731 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO,
4732 vlan->mc[i]);
4733 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->ucdef);
4734 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->bcast);
4735 efx_ef10_filter_remove_unsafe(efx, EFX_FILTER_PRI_AUTO, vlan->mcdef);
4736
4737 kfree(vlan);
4738 }
4739
4740 static void efx_ef10_filter_del_vlan(struct efx_nic *efx, u16 vid)
4741 {
4742 struct efx_ef10_filter_vlan *vlan;
4743
4744 /* See comment in efx_ef10_filter_table_remove() */
4745 if (!efx_rwsem_assert_write_locked(&efx->filter_sem))
4746 return;
4747
4748 vlan = efx_ef10_filter_find_vlan(efx, vid);
4749 if (!vlan) {
4750 netif_err(efx, drv, efx->net_dev,
4751 "VLAN %u not found in filter state\n", vid);
4752 return;
4753 }
4754
4755 efx_ef10_filter_del_vlan_internal(efx, vlan);
4756 }
4757
4758 static int efx_ef10_set_mac_address(struct efx_nic *efx)
4759 {
4760 MCDI_DECLARE_BUF(inbuf, MC_CMD_VADAPTOR_SET_MAC_IN_LEN);
4761 struct efx_ef10_nic_data *nic_data = efx->nic_data;
4762 bool was_enabled = efx->port_enabled;
4763 int rc;
4764
4765 efx_device_detach_sync(efx);
4766 efx_net_stop(efx->net_dev);
4767
4768 mutex_lock(&efx->mac_lock);
4769 down_write(&efx->filter_sem);
4770 efx_ef10_filter_table_remove(efx);
4771
4772 ether_addr_copy(MCDI_PTR(inbuf, VADAPTOR_SET_MAC_IN_MACADDR),
4773 efx->net_dev->dev_addr);
4774 MCDI_SET_DWORD(inbuf, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID,
4775 nic_data->vport_id);
4776 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_VADAPTOR_SET_MAC, inbuf,
4777 sizeof(inbuf), NULL, 0, NULL);
4778
4779 efx_ef10_filter_table_probe(efx);
4780 up_write(&efx->filter_sem);
4781 mutex_unlock(&efx->mac_lock);
4782
4783 if (was_enabled)
4784 efx_net_open(efx->net_dev);
4785 netif_device_attach(efx->net_dev);
4786
4787 #ifdef CONFIG_SFC_SRIOV
4788 if (efx->pci_dev->is_virtfn && efx->pci_dev->physfn) {
4789 struct pci_dev *pci_dev_pf = efx->pci_dev->physfn;
4790
4791 if (rc == -EPERM) {
4792 struct efx_nic *efx_pf;
4793
4794 /* Switch to PF and change MAC address on vport */
4795 efx_pf = pci_get_drvdata(pci_dev_pf);
4796
4797 rc = efx_ef10_sriov_set_vf_mac(efx_pf,
4798 nic_data->vf_index,
4799 efx->net_dev->dev_addr);
4800 } else if (!rc) {
4801 struct efx_nic *efx_pf = pci_get_drvdata(pci_dev_pf);
4802 struct efx_ef10_nic_data *nic_data = efx_pf->nic_data;
4803 unsigned int i;
4804
4805 /* MAC address successfully changed by VF (with MAC
4806 * spoofing) so update the parent PF if possible.
4807 */
4808 for (i = 0; i < efx_pf->vf_count; ++i) {
4809 struct ef10_vf *vf = nic_data->vf + i;
4810
4811 if (vf->efx == efx) {
4812 ether_addr_copy(vf->mac,
4813 efx->net_dev->dev_addr);
4814 return 0;
4815 }
4816 }
4817 }
4818 } else
4819 #endif
4820 if (rc == -EPERM) {
4821 netif_err(efx, drv, efx->net_dev,
4822 "Cannot change MAC address; use sfboot to enable"
4823 " mac-spoofing on this interface\n");
4824 } else if (rc == -ENOSYS && !efx_ef10_is_vf(efx)) {
4825 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4826 * fall-back to the method of changing the MAC address on the
4827 * vport. This only applies to PFs because such versions of
4828 * MCFW do not support VFs.
4829 */
4830 rc = efx_ef10_vport_set_mac_address(efx);
4831 } else {
4832 efx_mcdi_display_error(efx, MC_CMD_VADAPTOR_SET_MAC,
4833 sizeof(inbuf), NULL, 0, rc);
4834 }
4835
4836 return rc;
4837 }
4838
4839 static int efx_ef10_mac_reconfigure(struct efx_nic *efx)
4840 {
4841 efx_ef10_filter_sync_rx_mode(efx);
4842
4843 return efx_mcdi_set_mac(efx);
4844 }
4845
4846 static int efx_ef10_mac_reconfigure_vf(struct efx_nic *efx)
4847 {
4848 efx_ef10_filter_sync_rx_mode(efx);
4849
4850 return 0;
4851 }
4852
4853 static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type)
4854 {
4855 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN);
4856
4857 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type);
4858 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf),
4859 NULL, 0, NULL);
4860 }
4861
4862 /* MC BISTs follow a different poll mechanism to phy BISTs.
4863 * The BIST is done in the poll handler on the MC, and the MCDI command
4864 * will block until the BIST is done.
4865 */
4866 static int efx_ef10_poll_bist(struct efx_nic *efx)
4867 {
4868 int rc;
4869 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN);
4870 size_t outlen;
4871 u32 result;
4872
4873 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0,
4874 outbuf, sizeof(outbuf), &outlen);
4875 if (rc != 0)
4876 return rc;
4877
4878 if (outlen < MC_CMD_POLL_BIST_OUT_LEN)
4879 return -EIO;
4880
4881 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT);
4882 switch (result) {
4883 case MC_CMD_POLL_BIST_PASSED:
4884 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n");
4885 return 0;
4886 case MC_CMD_POLL_BIST_TIMEOUT:
4887 netif_err(efx, hw, efx->net_dev, "BIST timed out\n");
4888 return -EIO;
4889 case MC_CMD_POLL_BIST_FAILED:
4890 netif_err(efx, hw, efx->net_dev, "BIST failed.\n");
4891 return -EIO;
4892 default:
4893 netif_err(efx, hw, efx->net_dev,
4894 "BIST returned unknown result %u", result);
4895 return -EIO;
4896 }
4897 }
4898
4899 static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type)
4900 {
4901 int rc;
4902
4903 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type);
4904
4905 rc = efx_ef10_start_bist(efx, bist_type);
4906 if (rc != 0)
4907 return rc;
4908
4909 return efx_ef10_poll_bist(efx);
4910 }
4911
4912 static int
4913 efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
4914 {
4915 int rc, rc2;
4916
4917 efx_reset_down(efx, RESET_TYPE_WORLD);
4918
4919 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST,
4920 NULL, 0, NULL, 0, NULL);
4921 if (rc != 0)
4922 goto out;
4923
4924 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1;
4925 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1;
4926
4927 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD);
4928
4929 out:
4930 if (rc == -EPERM)
4931 rc = 0;
4932 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0);
4933 return rc ? rc : rc2;
4934 }
4935
4936 #ifdef CONFIG_SFC_MTD
4937
4938 struct efx_ef10_nvram_type_info {
4939 u16 type, type_mask;
4940 u8 port;
4941 const char *name;
4942 };
4943
4944 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = {
4945 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" },
4946 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" },
4947 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" },
4948 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" },
4949 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" },
4950 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" },
4951 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" },
4952 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" },
4953 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" },
4954 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" },
4955 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" },
4956 };
4957
4958 static int efx_ef10_mtd_probe_partition(struct efx_nic *efx,
4959 struct efx_mcdi_mtd_partition *part,
4960 unsigned int type)
4961 {
4962 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN);
4963 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX);
4964 const struct efx_ef10_nvram_type_info *info;
4965 size_t size, erase_size, outlen;
4966 bool protected;
4967 int rc;
4968
4969 for (info = efx_ef10_nvram_types; ; info++) {
4970 if (info ==
4971 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types))
4972 return -ENODEV;
4973 if ((type & ~info->type_mask) == info->type)
4974 break;
4975 }
4976 if (info->port != efx_port_num(efx))
4977 return -ENODEV;
4978
4979 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected);
4980 if (rc)
4981 return rc;
4982 if (protected)
4983 return -ENODEV; /* hide it */
4984
4985 part->nvram_type = type;
4986
4987 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type);
4988 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf),
4989 outbuf, sizeof(outbuf), &outlen);
4990 if (rc)
4991 return rc;
4992 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN)
4993 return -EIO;
4994 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) &
4995 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN))
4996 part->fw_subtype = MCDI_DWORD(outbuf,
4997 NVRAM_METADATA_OUT_SUBTYPE);
4998
4999 part->common.dev_type_name = "EF10 NVRAM manager";
5000 part->common.type_name = info->name;
5001
5002 part->common.mtd.type = MTD_NORFLASH;
5003 part->common.mtd.flags = MTD_CAP_NORFLASH;
5004 part->common.mtd.size = size;
5005 part->common.mtd.erasesize = erase_size;
5006
5007 return 0;
5008 }
5009
5010 static int efx_ef10_mtd_probe(struct efx_nic *efx)
5011 {
5012 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX);
5013 struct efx_mcdi_mtd_partition *parts;
5014 size_t outlen, n_parts_total, i, n_parts;
5015 unsigned int type;
5016 int rc;
5017
5018 ASSERT_RTNL();
5019
5020 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0);
5021 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0,
5022 outbuf, sizeof(outbuf), &outlen);
5023 if (rc)
5024 return rc;
5025 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN)
5026 return -EIO;
5027
5028 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS);
5029 if (n_parts_total >
5030 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID))
5031 return -EIO;
5032
5033 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL);
5034 if (!parts)
5035 return -ENOMEM;
5036
5037 n_parts = 0;
5038 for (i = 0; i < n_parts_total; i++) {
5039 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID,
5040 i);
5041 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type);
5042 if (rc == 0)
5043 n_parts++;
5044 else if (rc != -ENODEV)
5045 goto fail;
5046 }
5047
5048 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts));
5049 fail:
5050 if (rc)
5051 kfree(parts);
5052 return rc;
5053 }
5054
5055 #endif /* CONFIG_SFC_MTD */
5056
5057 static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time)
5058 {
5059 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD);
5060 }
5061
5062 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic *efx,
5063 u32 host_time) {}
5064
5065 static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel,
5066 bool temp)
5067 {
5068 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN);
5069 int rc;
5070
5071 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED ||
5072 channel->sync_events_state == SYNC_EVENTS_VALID ||
5073 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED))
5074 return 0;
5075 channel->sync_events_state = SYNC_EVENTS_REQUESTED;
5076
5077 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE);
5078 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5079 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE,
5080 channel->channel);
5081
5082 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5083 inbuf, sizeof(inbuf), NULL, 0, NULL);
5084
5085 if (rc != 0)
5086 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5087 SYNC_EVENTS_DISABLED;
5088
5089 return rc;
5090 }
5091
5092 static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel,
5093 bool temp)
5094 {
5095 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN);
5096 int rc;
5097
5098 if (channel->sync_events_state == SYNC_EVENTS_DISABLED ||
5099 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT))
5100 return 0;
5101 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) {
5102 channel->sync_events_state = SYNC_EVENTS_DISABLED;
5103 return 0;
5104 }
5105 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT :
5106 SYNC_EVENTS_DISABLED;
5107
5108 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE);
5109 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0);
5110 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL,
5111 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE);
5112 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE,
5113 channel->channel);
5114
5115 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP,
5116 inbuf, sizeof(inbuf), NULL, 0, NULL);
5117
5118 return rc;
5119 }
5120
5121 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en,
5122 bool temp)
5123 {
5124 int (*set)(struct efx_channel *channel, bool temp);
5125 struct efx_channel *channel;
5126
5127 set = en ?
5128 efx_ef10_rx_enable_timestamping :
5129 efx_ef10_rx_disable_timestamping;
5130
5131 efx_for_each_channel(channel, efx) {
5132 int rc = set(channel, temp);
5133 if (en && rc != 0) {
5134 efx_ef10_ptp_set_ts_sync_events(efx, false, temp);
5135 return rc;
5136 }
5137 }
5138
5139 return 0;
5140 }
5141
5142 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic *efx,
5143 struct hwtstamp_config *init)
5144 {
5145 return -EOPNOTSUPP;
5146 }
5147
5148 static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx,
5149 struct hwtstamp_config *init)
5150 {
5151 int rc;
5152
5153 switch (init->rx_filter) {
5154 case HWTSTAMP_FILTER_NONE:
5155 efx_ef10_ptp_set_ts_sync_events(efx, false, false);
5156 /* if TX timestamping is still requested then leave PTP on */
5157 return efx_ptp_change_mode(efx,
5158 init->tx_type != HWTSTAMP_TX_OFF, 0);
5159 case HWTSTAMP_FILTER_ALL:
5160 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
5161 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
5162 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5163 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
5164 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5165 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5166 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5167 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5168 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5169 case HWTSTAMP_FILTER_PTP_V2_EVENT:
5170 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5171 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5172 init->rx_filter = HWTSTAMP_FILTER_ALL;
5173 rc = efx_ptp_change_mode(efx, true, 0);
5174 if (!rc)
5175 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false);
5176 if (rc)
5177 efx_ptp_change_mode(efx, false, 0);
5178 return rc;
5179 default:
5180 return -ERANGE;
5181 }
5182 }
5183
5184 static int efx_ef10_vlan_rx_add_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5185 {
5186 if (proto != htons(ETH_P_8021Q))
5187 return -EINVAL;
5188
5189 return efx_ef10_add_vlan(efx, vid);
5190 }
5191
5192 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic *efx, __be16 proto, u16 vid)
5193 {
5194 if (proto != htons(ETH_P_8021Q))
5195 return -EINVAL;
5196
5197 return efx_ef10_del_vlan(efx, vid);
5198 }
5199
5200 #define EF10_OFFLOAD_FEATURES \
5201 (NETIF_F_IP_CSUM | \
5202 NETIF_F_HW_VLAN_CTAG_FILTER | \
5203 NETIF_F_IPV6_CSUM | \
5204 NETIF_F_RXHASH | \
5205 NETIF_F_NTUPLE)
5206
5207 const struct efx_nic_type efx_hunt_a0_vf_nic_type = {
5208 .is_vf = true,
5209 .mem_bar = EFX_MEM_VF_BAR,
5210 .mem_map_size = efx_ef10_mem_map_size,
5211 .probe = efx_ef10_probe_vf,
5212 .remove = efx_ef10_remove,
5213 .dimension_resources = efx_ef10_dimension_resources,
5214 .init = efx_ef10_init_nic,
5215 .fini = efx_port_dummy_op_void,
5216 .map_reset_reason = efx_ef10_map_reset_reason,
5217 .map_reset_flags = efx_ef10_map_reset_flags,
5218 .reset = efx_ef10_reset,
5219 .probe_port = efx_mcdi_port_probe,
5220 .remove_port = efx_mcdi_port_remove,
5221 .fini_dmaq = efx_ef10_fini_dmaq,
5222 .prepare_flr = efx_ef10_prepare_flr,
5223 .finish_flr = efx_port_dummy_op_void,
5224 .describe_stats = efx_ef10_describe_stats,
5225 .update_stats = efx_ef10_update_stats_vf,
5226 .start_stats = efx_port_dummy_op_void,
5227 .pull_stats = efx_port_dummy_op_void,
5228 .stop_stats = efx_port_dummy_op_void,
5229 .set_id_led = efx_mcdi_set_id_led,
5230 .push_irq_moderation = efx_ef10_push_irq_moderation,
5231 .reconfigure_mac = efx_ef10_mac_reconfigure_vf,
5232 .check_mac_fault = efx_mcdi_mac_check_fault,
5233 .reconfigure_port = efx_mcdi_port_reconfigure,
5234 .get_wol = efx_ef10_get_wol_vf,
5235 .set_wol = efx_ef10_set_wol_vf,
5236 .resume_wol = efx_port_dummy_op_void,
5237 .mcdi_request = efx_ef10_mcdi_request,
5238 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5239 .mcdi_read_response = efx_ef10_mcdi_read_response,
5240 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
5241 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
5242 .irq_enable_master = efx_port_dummy_op_void,
5243 .irq_test_generate = efx_ef10_irq_test_generate,
5244 .irq_disable_non_ev = efx_port_dummy_op_void,
5245 .irq_handle_msi = efx_ef10_msi_interrupt,
5246 .irq_handle_legacy = efx_ef10_legacy_interrupt,
5247 .tx_probe = efx_ef10_tx_probe,
5248 .tx_init = efx_ef10_tx_init,
5249 .tx_remove = efx_ef10_tx_remove,
5250 .tx_write = efx_ef10_tx_write,
5251 .rx_push_rss_config = efx_ef10_vf_rx_push_rss_config,
5252 .rx_probe = efx_ef10_rx_probe,
5253 .rx_init = efx_ef10_rx_init,
5254 .rx_remove = efx_ef10_rx_remove,
5255 .rx_write = efx_ef10_rx_write,
5256 .rx_defer_refill = efx_ef10_rx_defer_refill,
5257 .ev_probe = efx_ef10_ev_probe,
5258 .ev_init = efx_ef10_ev_init,
5259 .ev_fini = efx_ef10_ev_fini,
5260 .ev_remove = efx_ef10_ev_remove,
5261 .ev_process = efx_ef10_ev_process,
5262 .ev_read_ack = efx_ef10_ev_read_ack,
5263 .ev_test_generate = efx_ef10_ev_test_generate,
5264 .filter_table_probe = efx_ef10_filter_table_probe,
5265 .filter_table_restore = efx_ef10_filter_table_restore,
5266 .filter_table_remove = efx_ef10_filter_table_remove,
5267 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5268 .filter_insert = efx_ef10_filter_insert,
5269 .filter_remove_safe = efx_ef10_filter_remove_safe,
5270 .filter_get_safe = efx_ef10_filter_get_safe,
5271 .filter_clear_rx = efx_ef10_filter_clear_rx,
5272 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5273 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5274 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5275 #ifdef CONFIG_RFS_ACCEL
5276 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5277 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5278 #endif
5279 #ifdef CONFIG_SFC_MTD
5280 .mtd_probe = efx_port_dummy_op_int,
5281 #endif
5282 .ptp_write_host_time = efx_ef10_ptp_write_host_time_vf,
5283 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config_vf,
5284 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5285 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
5286 #ifdef CONFIG_SFC_SRIOV
5287 .vswitching_probe = efx_ef10_vswitching_probe_vf,
5288 .vswitching_restore = efx_ef10_vswitching_restore_vf,
5289 .vswitching_remove = efx_ef10_vswitching_remove_vf,
5290 .sriov_get_phys_port_id = efx_ef10_sriov_get_phys_port_id,
5291 #endif
5292 .get_mac_address = efx_ef10_get_mac_address_vf,
5293 .set_mac_address = efx_ef10_set_mac_address,
5294
5295 .revision = EFX_REV_HUNT_A0,
5296 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5297 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5298 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5299 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5300 .can_rx_scatter = true,
5301 .always_rx_scatter = true,
5302 .max_interrupt_mode = EFX_INT_MODE_MSIX,
5303 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
5304 .offload_features = EF10_OFFLOAD_FEATURES,
5305 .mcdi_max_ver = 2,
5306 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5307 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5308 1 << HWTSTAMP_FILTER_ALL,
5309 };
5310
5311 const struct efx_nic_type efx_hunt_a0_nic_type = {
5312 .is_vf = false,
5313 .mem_bar = EFX_MEM_BAR,
5314 .mem_map_size = efx_ef10_mem_map_size,
5315 .probe = efx_ef10_probe_pf,
5316 .remove = efx_ef10_remove,
5317 .dimension_resources = efx_ef10_dimension_resources,
5318 .init = efx_ef10_init_nic,
5319 .fini = efx_port_dummy_op_void,
5320 .map_reset_reason = efx_ef10_map_reset_reason,
5321 .map_reset_flags = efx_ef10_map_reset_flags,
5322 .reset = efx_ef10_reset,
5323 .probe_port = efx_mcdi_port_probe,
5324 .remove_port = efx_mcdi_port_remove,
5325 .fini_dmaq = efx_ef10_fini_dmaq,
5326 .prepare_flr = efx_ef10_prepare_flr,
5327 .finish_flr = efx_port_dummy_op_void,
5328 .describe_stats = efx_ef10_describe_stats,
5329 .update_stats = efx_ef10_update_stats_pf,
5330 .start_stats = efx_mcdi_mac_start_stats,
5331 .pull_stats = efx_mcdi_mac_pull_stats,
5332 .stop_stats = efx_mcdi_mac_stop_stats,
5333 .set_id_led = efx_mcdi_set_id_led,
5334 .push_irq_moderation = efx_ef10_push_irq_moderation,
5335 .reconfigure_mac = efx_ef10_mac_reconfigure,
5336 .check_mac_fault = efx_mcdi_mac_check_fault,
5337 .reconfigure_port = efx_mcdi_port_reconfigure,
5338 .get_wol = efx_ef10_get_wol,
5339 .set_wol = efx_ef10_set_wol,
5340 .resume_wol = efx_port_dummy_op_void,
5341 .test_chip = efx_ef10_test_chip,
5342 .test_nvram = efx_mcdi_nvram_test_all,
5343 .mcdi_request = efx_ef10_mcdi_request,
5344 .mcdi_poll_response = efx_ef10_mcdi_poll_response,
5345 .mcdi_read_response = efx_ef10_mcdi_read_response,
5346 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot,
5347 .mcdi_reboot_detected = efx_ef10_mcdi_reboot_detected,
5348 .irq_enable_master = efx_port_dummy_op_void,
5349 .irq_test_generate = efx_ef10_irq_test_generate,
5350 .irq_disable_non_ev = efx_port_dummy_op_void,
5351 .irq_handle_msi = efx_ef10_msi_interrupt,
5352 .irq_handle_legacy = efx_ef10_legacy_interrupt,
5353 .tx_probe = efx_ef10_tx_probe,
5354 .tx_init = efx_ef10_tx_init,
5355 .tx_remove = efx_ef10_tx_remove,
5356 .tx_write = efx_ef10_tx_write,
5357 .rx_push_rss_config = efx_ef10_pf_rx_push_rss_config,
5358 .rx_probe = efx_ef10_rx_probe,
5359 .rx_init = efx_ef10_rx_init,
5360 .rx_remove = efx_ef10_rx_remove,
5361 .rx_write = efx_ef10_rx_write,
5362 .rx_defer_refill = efx_ef10_rx_defer_refill,
5363 .ev_probe = efx_ef10_ev_probe,
5364 .ev_init = efx_ef10_ev_init,
5365 .ev_fini = efx_ef10_ev_fini,
5366 .ev_remove = efx_ef10_ev_remove,
5367 .ev_process = efx_ef10_ev_process,
5368 .ev_read_ack = efx_ef10_ev_read_ack,
5369 .ev_test_generate = efx_ef10_ev_test_generate,
5370 .filter_table_probe = efx_ef10_filter_table_probe,
5371 .filter_table_restore = efx_ef10_filter_table_restore,
5372 .filter_table_remove = efx_ef10_filter_table_remove,
5373 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter,
5374 .filter_insert = efx_ef10_filter_insert,
5375 .filter_remove_safe = efx_ef10_filter_remove_safe,
5376 .filter_get_safe = efx_ef10_filter_get_safe,
5377 .filter_clear_rx = efx_ef10_filter_clear_rx,
5378 .filter_count_rx_used = efx_ef10_filter_count_rx_used,
5379 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit,
5380 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids,
5381 #ifdef CONFIG_RFS_ACCEL
5382 .filter_rfs_insert = efx_ef10_filter_rfs_insert,
5383 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one,
5384 #endif
5385 #ifdef CONFIG_SFC_MTD
5386 .mtd_probe = efx_ef10_mtd_probe,
5387 .mtd_rename = efx_mcdi_mtd_rename,
5388 .mtd_read = efx_mcdi_mtd_read,
5389 .mtd_erase = efx_mcdi_mtd_erase,
5390 .mtd_write = efx_mcdi_mtd_write,
5391 .mtd_sync = efx_mcdi_mtd_sync,
5392 #endif
5393 .ptp_write_host_time = efx_ef10_ptp_write_host_time,
5394 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events,
5395 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config,
5396 .vlan_rx_add_vid = efx_ef10_vlan_rx_add_vid,
5397 .vlan_rx_kill_vid = efx_ef10_vlan_rx_kill_vid,
5398 #ifdef CONFIG_SFC_SRIOV
5399 .sriov_configure = efx_ef10_sriov_configure,
5400 .sriov_init = efx_ef10_sriov_init,
5401 .sriov_fini = efx_ef10_sriov_fini,
5402 .sriov_wanted = efx_ef10_sriov_wanted,
5403 .sriov_reset = efx_ef10_sriov_reset,
5404 .sriov_flr = efx_ef10_sriov_flr,
5405 .sriov_set_vf_mac = efx_ef10_sriov_set_vf_mac,
5406 .sriov_set_vf_vlan = efx_ef10_sriov_set_vf_vlan,
5407 .sriov_set_vf_spoofchk = efx_ef10_sriov_set_vf_spoofchk,
5408 .sriov_get_vf_config = efx_ef10_sriov_get_vf_config,
5409 .sriov_set_vf_link_state = efx_ef10_sriov_set_vf_link_state,
5410 .vswitching_probe = efx_ef10_vswitching_probe_pf,
5411 .vswitching_restore = efx_ef10_vswitching_restore_pf,
5412 .vswitching_remove = efx_ef10_vswitching_remove_pf,
5413 #endif
5414 .get_mac_address = efx_ef10_get_mac_address_pf,
5415 .set_mac_address = efx_ef10_set_mac_address,
5416
5417 .revision = EFX_REV_HUNT_A0,
5418 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH),
5419 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE,
5420 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST,
5421 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST,
5422 .can_rx_scatter = true,
5423 .always_rx_scatter = true,
5424 .max_interrupt_mode = EFX_INT_MODE_MSIX,
5425 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH,
5426 .offload_features = EF10_OFFLOAD_FEATURES,
5427 .mcdi_max_ver = 2,
5428 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS,
5429 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE |
5430 1 << HWTSTAMP_FILTER_ALL,
5431 };
Linux kernel - Deliverables
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