1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2012-2013 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include "net_driver.h"
11 #include "ef10_regs.h"
14 #include "mcdi_pcol.h"
16 #include "workarounds.h"
18 #include "ef10_sriov.h"
20 #include <linux/jhash.h>
21 #include <linux/wait.h>
22 #include <linux/workqueue.h>
24 /* Hardware control for EF10 architecture including 'Huntington'. */
26 #define EFX_EF10_DRVGEN_EV 7
32 /* The reserved RSS context value */
33 #define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff
34 /* The maximum size of a shared RSS context */
35 /* TODO: this should really be from the mcdi protocol export */
36 #define EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE 64UL
38 /* The filter table(s) are managed by firmware and we have write-only
39 * access. When removing filters we must identify them to the
40 * firmware by a 64-bit handle, but this is too wide for Linux kernel
41 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to
42 * be able to tell in advance whether a requested insertion will
43 * replace an existing filter. Therefore we maintain a software hash
44 * table, which should be at least as large as the hardware hash
47 * Huntington has a single 8K filter table shared between all filter
48 * types and both ports.
50 #define HUNT_FILTER_TBL_ROWS 8192
52 #define EFX_EF10_FILTER_ID_INVALID 0xffff
54 #define EFX_EF10_FILTER_DEV_UC_MAX 32
55 #define EFX_EF10_FILTER_DEV_MC_MAX 256
58 struct efx_ef10_vlan
{
59 struct list_head list
;
63 /* Per-VLAN filters information */
64 struct efx_ef10_filter_vlan
{
65 struct list_head list
;
67 u16 uc
[EFX_EF10_FILTER_DEV_UC_MAX
];
68 u16 mc
[EFX_EF10_FILTER_DEV_MC_MAX
];
74 struct efx_ef10_dev_addr
{
78 struct efx_ef10_filter_table
{
79 /* The MCDI match masks supported by this fw & hw, in order of priority */
80 u32 rx_match_mcdi_flags
[
81 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM
];
82 unsigned int rx_match_count
;
85 unsigned long spec
; /* pointer to spec plus flag bits */
86 /* BUSY flag indicates that an update is in progress. AUTO_OLD is
87 * used to mark and sweep MAC filters for the device address lists.
89 #define EFX_EF10_FILTER_FLAG_BUSY 1UL
90 #define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL
91 #define EFX_EF10_FILTER_FLAGS 3UL
92 u64 handle
; /* firmware handle */
94 wait_queue_head_t waitq
;
95 /* Shadow of net_device address lists, guarded by mac_lock */
96 struct efx_ef10_dev_addr dev_uc_list
[EFX_EF10_FILTER_DEV_UC_MAX
];
97 struct efx_ef10_dev_addr dev_mc_list
[EFX_EF10_FILTER_DEV_MC_MAX
];
102 /* Whether in multicast promiscuous mode when last changed */
103 bool mc_promisc_last
;
105 struct list_head vlan_list
;
108 /* An arbitrary search limit for the software hash table */
109 #define EFX_EF10_FILTER_SEARCH_LIMIT 200
111 static void efx_ef10_rx_free_indir_table(struct efx_nic
*efx
);
112 static void efx_ef10_filter_table_remove(struct efx_nic
*efx
);
113 static int efx_ef10_filter_add_vlan(struct efx_nic
*efx
, u16 vid
);
114 static void efx_ef10_filter_del_vlan_internal(struct efx_nic
*efx
,
115 struct efx_ef10_filter_vlan
*vlan
);
116 static void efx_ef10_filter_del_vlan(struct efx_nic
*efx
, u16 vid
);
118 static int efx_ef10_get_warm_boot_count(struct efx_nic
*efx
)
122 efx_readd(efx
, ®
, ER_DZ_BIU_MC_SFT_STATUS
);
123 return EFX_DWORD_FIELD(reg
, EFX_WORD_1
) == 0xb007 ?
124 EFX_DWORD_FIELD(reg
, EFX_WORD_0
) : -EIO
;
127 static unsigned int efx_ef10_mem_map_size(struct efx_nic
*efx
)
131 bar
= efx
->type
->mem_bar
;
132 return resource_size(&efx
->pci_dev
->resource
[bar
]);
135 static bool efx_ef10_is_vf(struct efx_nic
*efx
)
137 return efx
->type
->is_vf
;
140 static int efx_ef10_get_pf_index(struct efx_nic
*efx
)
142 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_FUNCTION_INFO_OUT_LEN
);
143 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
147 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_FUNCTION_INFO
, NULL
, 0, outbuf
,
148 sizeof(outbuf
), &outlen
);
151 if (outlen
< sizeof(outbuf
))
154 nic_data
->pf_index
= MCDI_DWORD(outbuf
, GET_FUNCTION_INFO_OUT_PF
);
158 #ifdef CONFIG_SFC_SRIOV
159 static int efx_ef10_get_vf_index(struct efx_nic
*efx
)
161 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_FUNCTION_INFO_OUT_LEN
);
162 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
166 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_FUNCTION_INFO
, NULL
, 0, outbuf
,
167 sizeof(outbuf
), &outlen
);
170 if (outlen
< sizeof(outbuf
))
173 nic_data
->vf_index
= MCDI_DWORD(outbuf
, GET_FUNCTION_INFO_OUT_VF
);
178 static int efx_ef10_init_datapath_caps(struct efx_nic
*efx
)
180 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_CAPABILITIES_OUT_LEN
);
181 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
185 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN
!= 0);
187 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_CAPABILITIES
, NULL
, 0,
188 outbuf
, sizeof(outbuf
), &outlen
);
191 if (outlen
< sizeof(outbuf
)) {
192 netif_err(efx
, drv
, efx
->net_dev
,
193 "unable to read datapath firmware capabilities\n");
197 nic_data
->datapath_caps
=
198 MCDI_DWORD(outbuf
, GET_CAPABILITIES_OUT_FLAGS1
);
200 /* record the DPCPU firmware IDs to determine VEB vswitching support.
202 nic_data
->rx_dpcpu_fw_id
=
203 MCDI_WORD(outbuf
, GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID
);
204 nic_data
->tx_dpcpu_fw_id
=
205 MCDI_WORD(outbuf
, GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID
);
207 if (!(nic_data
->datapath_caps
&
208 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN
))) {
209 netif_err(efx
, probe
, efx
->net_dev
,
210 "current firmware does not support an RX prefix\n");
217 static int efx_ef10_get_sysclk_freq(struct efx_nic
*efx
)
219 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_CLOCK_OUT_LEN
);
222 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_CLOCK
, NULL
, 0,
223 outbuf
, sizeof(outbuf
), NULL
);
226 rc
= MCDI_DWORD(outbuf
, GET_CLOCK_OUT_SYS_FREQ
);
227 return rc
> 0 ? rc
: -ERANGE
;
230 static int efx_ef10_get_mac_address_pf(struct efx_nic
*efx
, u8
*mac_address
)
232 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN
);
236 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN
!= 0);
238 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_MAC_ADDRESSES
, NULL
, 0,
239 outbuf
, sizeof(outbuf
), &outlen
);
242 if (outlen
< MC_CMD_GET_MAC_ADDRESSES_OUT_LEN
)
245 ether_addr_copy(mac_address
,
246 MCDI_PTR(outbuf
, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE
));
250 static int efx_ef10_get_mac_address_vf(struct efx_nic
*efx
, u8
*mac_address
)
252 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN
);
253 MCDI_DECLARE_BUF(outbuf
, MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX
);
257 MCDI_SET_DWORD(inbuf
, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID
,
258 EVB_PORT_ID_ASSIGNED
);
259 rc
= efx_mcdi_rpc(efx
, MC_CMD_VPORT_GET_MAC_ADDRESSES
, inbuf
,
260 sizeof(inbuf
), outbuf
, sizeof(outbuf
), &outlen
);
264 if (outlen
< MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN
)
267 num_addrs
= MCDI_DWORD(outbuf
,
268 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT
);
270 WARN_ON(num_addrs
!= 1);
272 ether_addr_copy(mac_address
,
273 MCDI_PTR(outbuf
, VPORT_GET_MAC_ADDRESSES_OUT_MACADDR
));
278 static ssize_t
efx_ef10_show_link_control_flag(struct device
*dev
,
279 struct device_attribute
*attr
,
282 struct efx_nic
*efx
= pci_get_drvdata(to_pci_dev(dev
));
284 return sprintf(buf
, "%d\n",
285 ((efx
->mcdi
->fn_flags
) &
286 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL
))
290 static ssize_t
efx_ef10_show_primary_flag(struct device
*dev
,
291 struct device_attribute
*attr
,
294 struct efx_nic
*efx
= pci_get_drvdata(to_pci_dev(dev
));
296 return sprintf(buf
, "%d\n",
297 ((efx
->mcdi
->fn_flags
) &
298 (1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY
))
302 static struct efx_ef10_vlan
*efx_ef10_find_vlan(struct efx_nic
*efx
, u16 vid
)
304 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
305 struct efx_ef10_vlan
*vlan
;
307 WARN_ON(!mutex_is_locked(&nic_data
->vlan_lock
));
309 list_for_each_entry(vlan
, &nic_data
->vlan_list
, list
) {
310 if (vlan
->vid
== vid
)
317 static int efx_ef10_add_vlan(struct efx_nic
*efx
, u16 vid
)
319 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
320 struct efx_ef10_vlan
*vlan
;
323 mutex_lock(&nic_data
->vlan_lock
);
325 vlan
= efx_ef10_find_vlan(efx
, vid
);
327 /* We add VID 0 on init. 8021q adds it on module init
328 * for all interfaces with VLAN filtring feature.
332 netif_warn(efx
, drv
, efx
->net_dev
,
333 "VLAN %u already added\n", vid
);
339 vlan
= kzalloc(sizeof(*vlan
), GFP_KERNEL
);
345 list_add_tail(&vlan
->list
, &nic_data
->vlan_list
);
347 if (efx
->filter_state
) {
348 mutex_lock(&efx
->mac_lock
);
349 down_write(&efx
->filter_sem
);
350 rc
= efx_ef10_filter_add_vlan(efx
, vlan
->vid
);
351 up_write(&efx
->filter_sem
);
352 mutex_unlock(&efx
->mac_lock
);
354 goto fail_filter_add_vlan
;
358 mutex_unlock(&nic_data
->vlan_lock
);
361 fail_filter_add_vlan
:
362 list_del(&vlan
->list
);
366 mutex_unlock(&nic_data
->vlan_lock
);
370 static void efx_ef10_del_vlan_internal(struct efx_nic
*efx
,
371 struct efx_ef10_vlan
*vlan
)
373 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
375 WARN_ON(!mutex_is_locked(&nic_data
->vlan_lock
));
377 if (efx
->filter_state
) {
378 down_write(&efx
->filter_sem
);
379 efx_ef10_filter_del_vlan(efx
, vlan
->vid
);
380 up_write(&efx
->filter_sem
);
383 list_del(&vlan
->list
);
387 static int efx_ef10_del_vlan(struct efx_nic
*efx
, u16 vid
)
389 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
390 struct efx_ef10_vlan
*vlan
;
393 /* 8021q removes VID 0 on module unload for all interfaces
394 * with VLAN filtering feature. We need to keep it to receive
400 mutex_lock(&nic_data
->vlan_lock
);
402 vlan
= efx_ef10_find_vlan(efx
, vid
);
404 netif_err(efx
, drv
, efx
->net_dev
,
405 "VLAN %u to be deleted not found\n", vid
);
408 efx_ef10_del_vlan_internal(efx
, vlan
);
411 mutex_unlock(&nic_data
->vlan_lock
);
416 static void efx_ef10_cleanup_vlans(struct efx_nic
*efx
)
418 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
419 struct efx_ef10_vlan
*vlan
, *next_vlan
;
421 mutex_lock(&nic_data
->vlan_lock
);
422 list_for_each_entry_safe(vlan
, next_vlan
, &nic_data
->vlan_list
, list
)
423 efx_ef10_del_vlan_internal(efx
, vlan
);
424 mutex_unlock(&nic_data
->vlan_lock
);
427 static DEVICE_ATTR(link_control_flag
, 0444, efx_ef10_show_link_control_flag
,
429 static DEVICE_ATTR(primary_flag
, 0444, efx_ef10_show_primary_flag
, NULL
);
431 static int efx_ef10_probe(struct efx_nic
*efx
)
433 struct efx_ef10_nic_data
*nic_data
;
434 struct net_device
*net_dev
= efx
->net_dev
;
437 /* We can have one VI for each 8K region. However, until we
438 * use TX option descriptors we need two TX queues per channel.
440 efx
->max_channels
= min_t(unsigned int,
442 efx_ef10_mem_map_size(efx
) /
443 (EFX_VI_PAGE_SIZE
* EFX_TXQ_TYPES
));
444 efx
->max_tx_channels
= efx
->max_channels
;
445 if (WARN_ON(efx
->max_channels
== 0))
448 nic_data
= kzalloc(sizeof(*nic_data
), GFP_KERNEL
);
451 efx
->nic_data
= nic_data
;
453 /* we assume later that we can copy from this buffer in dwords */
454 BUILD_BUG_ON(MCDI_CTL_SDU_LEN_MAX_V2
% 4);
456 rc
= efx_nic_alloc_buffer(efx
, &nic_data
->mcdi_buf
,
457 8 + MCDI_CTL_SDU_LEN_MAX_V2
, GFP_KERNEL
);
461 /* Get the MC's warm boot count. In case it's rebooting right
462 * now, be prepared to retry.
466 rc
= efx_ef10_get_warm_boot_count(efx
);
473 nic_data
->warm_boot_count
= rc
;
475 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
477 nic_data
->vport_id
= EVB_PORT_ID_ASSIGNED
;
479 /* In case we're recovering from a crash (kexec), we want to
480 * cancel any outstanding request by the previous user of this
481 * function. We send a special message using the least
482 * significant bits of the 'high' (doorbell) register.
484 _efx_writed(efx
, cpu_to_le32(1), ER_DZ_MC_DB_HWRD
);
486 rc
= efx_mcdi_init(efx
);
490 /* Reset (most) configuration for this function */
491 rc
= efx_mcdi_reset(efx
, RESET_TYPE_ALL
);
495 /* Enable event logging */
496 rc
= efx_mcdi_log_ctrl(efx
, true, false, 0);
500 rc
= device_create_file(&efx
->pci_dev
->dev
,
501 &dev_attr_link_control_flag
);
505 rc
= device_create_file(&efx
->pci_dev
->dev
, &dev_attr_primary_flag
);
509 rc
= efx_ef10_get_pf_index(efx
);
513 rc
= efx_ef10_init_datapath_caps(efx
);
517 efx
->rx_packet_len_offset
=
518 ES_DZ_RX_PREFIX_PKTLEN_OFST
- ES_DZ_RX_PREFIX_SIZE
;
520 rc
= efx_mcdi_port_get_number(efx
);
524 net_dev
->dev_port
= rc
;
526 rc
= efx
->type
->get_mac_address(efx
, efx
->net_dev
->perm_addr
);
530 rc
= efx_ef10_get_sysclk_freq(efx
);
533 efx
->timer_quantum_ns
= 1536000 / rc
; /* 1536 cycles */
535 /* Check whether firmware supports bug 35388 workaround.
536 * First try to enable it, then if we get EPERM, just
537 * ask if it's already enabled
539 rc
= efx_mcdi_set_workaround(efx
, MC_CMD_WORKAROUND_BUG35388
, true, NULL
);
541 nic_data
->workaround_35388
= true;
542 } else if (rc
== -EPERM
) {
543 unsigned int enabled
;
545 rc
= efx_mcdi_get_workarounds(efx
, NULL
, &enabled
);
548 nic_data
->workaround_35388
= enabled
&
549 MC_CMD_GET_WORKAROUNDS_OUT_BUG35388
;
550 } else if (rc
!= -ENOSYS
&& rc
!= -ENOENT
) {
553 netif_dbg(efx
, probe
, efx
->net_dev
,
554 "workaround for bug 35388 is %sabled\n",
555 nic_data
->workaround_35388
? "en" : "dis");
557 rc
= efx_mcdi_mon_probe(efx
);
558 if (rc
&& rc
!= -EPERM
)
561 efx_ptp_probe(efx
, NULL
);
563 #ifdef CONFIG_SFC_SRIOV
564 if ((efx
->pci_dev
->physfn
) && (!efx
->pci_dev
->is_physfn
)) {
565 struct pci_dev
*pci_dev_pf
= efx
->pci_dev
->physfn
;
566 struct efx_nic
*efx_pf
= pci_get_drvdata(pci_dev_pf
);
568 efx_pf
->type
->get_mac_address(efx_pf
, nic_data
->port_id
);
571 ether_addr_copy(nic_data
->port_id
, efx
->net_dev
->perm_addr
);
573 INIT_LIST_HEAD(&nic_data
->vlan_list
);
574 mutex_init(&nic_data
->vlan_lock
);
576 /* Add unspecified VID to support VLAN filtering being disabled */
577 rc
= efx_ef10_add_vlan(efx
, EFX_FILTER_VID_UNSPEC
);
579 goto fail_add_vid_unspec
;
581 /* If VLAN filtering is enabled, we need VID 0 to get untagged
582 * traffic. It is added automatically if 8021q module is loaded,
583 * but we can't rely on it since module may be not loaded.
585 rc
= efx_ef10_add_vlan(efx
, 0);
592 efx_ef10_cleanup_vlans(efx
);
594 mutex_destroy(&nic_data
->vlan_lock
);
596 efx_mcdi_mon_remove(efx
);
598 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_primary_flag
);
600 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_link_control_flag
);
604 efx_nic_free_buffer(efx
, &nic_data
->mcdi_buf
);
607 efx
->nic_data
= NULL
;
611 static int efx_ef10_free_vis(struct efx_nic
*efx
)
613 MCDI_DECLARE_BUF_ERR(outbuf
);
615 int rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FREE_VIS
, NULL
, 0,
616 outbuf
, sizeof(outbuf
), &outlen
);
618 /* -EALREADY means nothing to free, so ignore */
622 efx_mcdi_display_error(efx
, MC_CMD_FREE_VIS
, 0, outbuf
, outlen
,
629 static void efx_ef10_free_piobufs(struct efx_nic
*efx
)
631 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
632 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FREE_PIOBUF_IN_LEN
);
636 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN
!= 0);
638 for (i
= 0; i
< nic_data
->n_piobufs
; i
++) {
639 MCDI_SET_DWORD(inbuf
, FREE_PIOBUF_IN_PIOBUF_HANDLE
,
640 nic_data
->piobuf_handle
[i
]);
641 rc
= efx_mcdi_rpc(efx
, MC_CMD_FREE_PIOBUF
, inbuf
, sizeof(inbuf
),
646 nic_data
->n_piobufs
= 0;
649 static int efx_ef10_alloc_piobufs(struct efx_nic
*efx
, unsigned int n
)
651 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
652 MCDI_DECLARE_BUF(outbuf
, MC_CMD_ALLOC_PIOBUF_OUT_LEN
);
657 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN
!= 0);
659 for (i
= 0; i
< n
; i
++) {
660 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_ALLOC_PIOBUF
, NULL
, 0,
661 outbuf
, sizeof(outbuf
), &outlen
);
663 /* Don't display the MC error if we didn't have space
666 if (!(efx_ef10_is_vf(efx
) && rc
== -ENOSPC
))
667 efx_mcdi_display_error(efx
, MC_CMD_ALLOC_PIOBUF
,
668 0, outbuf
, outlen
, rc
);
671 if (outlen
< MC_CMD_ALLOC_PIOBUF_OUT_LEN
) {
675 nic_data
->piobuf_handle
[i
] =
676 MCDI_DWORD(outbuf
, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE
);
677 netif_dbg(efx
, probe
, efx
->net_dev
,
678 "allocated PIO buffer %u handle %x\n", i
,
679 nic_data
->piobuf_handle
[i
]);
682 nic_data
->n_piobufs
= i
;
684 efx_ef10_free_piobufs(efx
);
688 static int efx_ef10_link_piobufs(struct efx_nic
*efx
)
690 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
691 _MCDI_DECLARE_BUF(inbuf
,
692 max(MC_CMD_LINK_PIOBUF_IN_LEN
,
693 MC_CMD_UNLINK_PIOBUF_IN_LEN
));
694 struct efx_channel
*channel
;
695 struct efx_tx_queue
*tx_queue
;
696 unsigned int offset
, index
;
699 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN
!= 0);
700 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN
!= 0);
702 memset(inbuf
, 0, sizeof(inbuf
));
704 /* Link a buffer to each VI in the write-combining mapping */
705 for (index
= 0; index
< nic_data
->n_piobufs
; ++index
) {
706 MCDI_SET_DWORD(inbuf
, LINK_PIOBUF_IN_PIOBUF_HANDLE
,
707 nic_data
->piobuf_handle
[index
]);
708 MCDI_SET_DWORD(inbuf
, LINK_PIOBUF_IN_TXQ_INSTANCE
,
709 nic_data
->pio_write_vi_base
+ index
);
710 rc
= efx_mcdi_rpc(efx
, MC_CMD_LINK_PIOBUF
,
711 inbuf
, MC_CMD_LINK_PIOBUF_IN_LEN
,
714 netif_err(efx
, drv
, efx
->net_dev
,
715 "failed to link VI %u to PIO buffer %u (%d)\n",
716 nic_data
->pio_write_vi_base
+ index
, index
,
720 netif_dbg(efx
, probe
, efx
->net_dev
,
721 "linked VI %u to PIO buffer %u\n",
722 nic_data
->pio_write_vi_base
+ index
, index
);
725 /* Link a buffer to each TX queue */
726 efx_for_each_channel(channel
, efx
) {
727 efx_for_each_channel_tx_queue(tx_queue
, channel
) {
728 /* We assign the PIO buffers to queues in
729 * reverse order to allow for the following
732 offset
= ((efx
->tx_channel_offset
+ efx
->n_tx_channels
-
733 tx_queue
->channel
->channel
- 1) *
735 index
= offset
/ ER_DZ_TX_PIOBUF_SIZE
;
736 offset
= offset
% ER_DZ_TX_PIOBUF_SIZE
;
738 /* When the host page size is 4K, the first
739 * host page in the WC mapping may be within
740 * the same VI page as the last TX queue. We
741 * can only link one buffer to each VI.
743 if (tx_queue
->queue
== nic_data
->pio_write_vi_base
) {
747 MCDI_SET_DWORD(inbuf
,
748 LINK_PIOBUF_IN_PIOBUF_HANDLE
,
749 nic_data
->piobuf_handle
[index
]);
750 MCDI_SET_DWORD(inbuf
,
751 LINK_PIOBUF_IN_TXQ_INSTANCE
,
753 rc
= efx_mcdi_rpc(efx
, MC_CMD_LINK_PIOBUF
,
754 inbuf
, MC_CMD_LINK_PIOBUF_IN_LEN
,
759 /* This is non-fatal; the TX path just
760 * won't use PIO for this queue
762 netif_err(efx
, drv
, efx
->net_dev
,
763 "failed to link VI %u to PIO buffer %u (%d)\n",
764 tx_queue
->queue
, index
, rc
);
765 tx_queue
->piobuf
= NULL
;
768 nic_data
->pio_write_base
+
769 index
* EFX_VI_PAGE_SIZE
+ offset
;
770 tx_queue
->piobuf_offset
= offset
;
771 netif_dbg(efx
, probe
, efx
->net_dev
,
772 "linked VI %u to PIO buffer %u offset %x addr %p\n",
773 tx_queue
->queue
, index
,
774 tx_queue
->piobuf_offset
,
784 MCDI_SET_DWORD(inbuf
, UNLINK_PIOBUF_IN_TXQ_INSTANCE
,
785 nic_data
->pio_write_vi_base
+ index
);
786 efx_mcdi_rpc(efx
, MC_CMD_UNLINK_PIOBUF
,
787 inbuf
, MC_CMD_UNLINK_PIOBUF_IN_LEN
,
793 static void efx_ef10_forget_old_piobufs(struct efx_nic
*efx
)
795 struct efx_channel
*channel
;
796 struct efx_tx_queue
*tx_queue
;
798 /* All our existing PIO buffers went away */
799 efx_for_each_channel(channel
, efx
)
800 efx_for_each_channel_tx_queue(tx_queue
, channel
)
801 tx_queue
->piobuf
= NULL
;
804 #else /* !EFX_USE_PIO */
806 static int efx_ef10_alloc_piobufs(struct efx_nic
*efx
, unsigned int n
)
808 return n
== 0 ? 0 : -ENOBUFS
;
811 static int efx_ef10_link_piobufs(struct efx_nic
*efx
)
816 static void efx_ef10_free_piobufs(struct efx_nic
*efx
)
820 static void efx_ef10_forget_old_piobufs(struct efx_nic
*efx
)
824 #endif /* EFX_USE_PIO */
826 static void efx_ef10_remove(struct efx_nic
*efx
)
828 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
831 #ifdef CONFIG_SFC_SRIOV
832 struct efx_ef10_nic_data
*nic_data_pf
;
833 struct pci_dev
*pci_dev_pf
;
834 struct efx_nic
*efx_pf
;
837 if (efx
->pci_dev
->is_virtfn
) {
838 pci_dev_pf
= efx
->pci_dev
->physfn
;
840 efx_pf
= pci_get_drvdata(pci_dev_pf
);
841 nic_data_pf
= efx_pf
->nic_data
;
842 vf
= nic_data_pf
->vf
+ nic_data
->vf_index
;
845 netif_info(efx
, drv
, efx
->net_dev
,
846 "Could not get the PF id from VF\n");
850 efx_ef10_cleanup_vlans(efx
);
851 mutex_destroy(&nic_data
->vlan_lock
);
855 efx_mcdi_mon_remove(efx
);
857 efx_ef10_rx_free_indir_table(efx
);
859 if (nic_data
->wc_membase
)
860 iounmap(nic_data
->wc_membase
);
862 rc
= efx_ef10_free_vis(efx
);
865 if (!nic_data
->must_restore_piobufs
)
866 efx_ef10_free_piobufs(efx
);
868 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_primary_flag
);
869 device_remove_file(&efx
->pci_dev
->dev
, &dev_attr_link_control_flag
);
872 efx_nic_free_buffer(efx
, &nic_data
->mcdi_buf
);
876 static int efx_ef10_probe_pf(struct efx_nic
*efx
)
878 return efx_ef10_probe(efx
);
881 int efx_ef10_vadaptor_query(struct efx_nic
*efx
, unsigned int port_id
,
882 u32
*port_flags
, u32
*vadaptor_flags
,
883 unsigned int *vlan_tags
)
885 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
886 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_QUERY_IN_LEN
);
887 MCDI_DECLARE_BUF(outbuf
, MC_CMD_VADAPTOR_QUERY_OUT_LEN
);
891 if (nic_data
->datapath_caps
&
892 (1 << MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN
)) {
893 MCDI_SET_DWORD(inbuf
, VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID
,
896 rc
= efx_mcdi_rpc(efx
, MC_CMD_VADAPTOR_QUERY
, inbuf
, sizeof(inbuf
),
897 outbuf
, sizeof(outbuf
), &outlen
);
901 if (outlen
< sizeof(outbuf
)) {
908 *port_flags
= MCDI_DWORD(outbuf
, VADAPTOR_QUERY_OUT_PORT_FLAGS
);
911 MCDI_DWORD(outbuf
, VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS
);
915 VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS
);
920 int efx_ef10_vadaptor_alloc(struct efx_nic
*efx
, unsigned int port_id
)
922 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_ALLOC_IN_LEN
);
924 MCDI_SET_DWORD(inbuf
, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID
, port_id
);
925 return efx_mcdi_rpc(efx
, MC_CMD_VADAPTOR_ALLOC
, inbuf
, sizeof(inbuf
),
929 int efx_ef10_vadaptor_free(struct efx_nic
*efx
, unsigned int port_id
)
931 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_FREE_IN_LEN
);
933 MCDI_SET_DWORD(inbuf
, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID
, port_id
);
934 return efx_mcdi_rpc(efx
, MC_CMD_VADAPTOR_FREE
, inbuf
, sizeof(inbuf
),
938 int efx_ef10_vport_add_mac(struct efx_nic
*efx
,
939 unsigned int port_id
, u8
*mac
)
941 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN
);
943 MCDI_SET_DWORD(inbuf
, VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID
, port_id
);
944 ether_addr_copy(MCDI_PTR(inbuf
, VPORT_ADD_MAC_ADDRESS_IN_MACADDR
), mac
);
946 return efx_mcdi_rpc(efx
, MC_CMD_VPORT_ADD_MAC_ADDRESS
, inbuf
,
947 sizeof(inbuf
), NULL
, 0, NULL
);
950 int efx_ef10_vport_del_mac(struct efx_nic
*efx
,
951 unsigned int port_id
, u8
*mac
)
953 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN
);
955 MCDI_SET_DWORD(inbuf
, VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID
, port_id
);
956 ether_addr_copy(MCDI_PTR(inbuf
, VPORT_DEL_MAC_ADDRESS_IN_MACADDR
), mac
);
958 return efx_mcdi_rpc(efx
, MC_CMD_VPORT_DEL_MAC_ADDRESS
, inbuf
,
959 sizeof(inbuf
), NULL
, 0, NULL
);
962 #ifdef CONFIG_SFC_SRIOV
963 static int efx_ef10_probe_vf(struct efx_nic
*efx
)
966 struct pci_dev
*pci_dev_pf
;
968 /* If the parent PF has no VF data structure, it doesn't know about this
969 * VF so fail probe. The VF needs to be re-created. This can happen
970 * if the PF driver is unloaded while the VF is assigned to a guest.
972 pci_dev_pf
= efx
->pci_dev
->physfn
;
974 struct efx_nic
*efx_pf
= pci_get_drvdata(pci_dev_pf
);
975 struct efx_ef10_nic_data
*nic_data_pf
= efx_pf
->nic_data
;
977 if (!nic_data_pf
->vf
) {
978 netif_info(efx
, drv
, efx
->net_dev
,
979 "The VF cannot link to its parent PF; "
980 "please destroy and re-create the VF\n");
985 rc
= efx_ef10_probe(efx
);
989 rc
= efx_ef10_get_vf_index(efx
);
993 if (efx
->pci_dev
->is_virtfn
) {
994 if (efx
->pci_dev
->physfn
) {
995 struct efx_nic
*efx_pf
=
996 pci_get_drvdata(efx
->pci_dev
->physfn
);
997 struct efx_ef10_nic_data
*nic_data_p
= efx_pf
->nic_data
;
998 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1000 nic_data_p
->vf
[nic_data
->vf_index
].efx
= efx
;
1001 nic_data_p
->vf
[nic_data
->vf_index
].pci_dev
=
1004 netif_info(efx
, drv
, efx
->net_dev
,
1005 "Could not get the PF id from VF\n");
1011 efx_ef10_remove(efx
);
1015 static int efx_ef10_probe_vf(struct efx_nic
*efx
__attribute__ ((unused
)))
1021 static int efx_ef10_alloc_vis(struct efx_nic
*efx
,
1022 unsigned int min_vis
, unsigned int max_vis
)
1024 MCDI_DECLARE_BUF(inbuf
, MC_CMD_ALLOC_VIS_IN_LEN
);
1025 MCDI_DECLARE_BUF(outbuf
, MC_CMD_ALLOC_VIS_OUT_LEN
);
1026 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1030 MCDI_SET_DWORD(inbuf
, ALLOC_VIS_IN_MIN_VI_COUNT
, min_vis
);
1031 MCDI_SET_DWORD(inbuf
, ALLOC_VIS_IN_MAX_VI_COUNT
, max_vis
);
1032 rc
= efx_mcdi_rpc(efx
, MC_CMD_ALLOC_VIS
, inbuf
, sizeof(inbuf
),
1033 outbuf
, sizeof(outbuf
), &outlen
);
1037 if (outlen
< MC_CMD_ALLOC_VIS_OUT_LEN
)
1040 netif_dbg(efx
, drv
, efx
->net_dev
, "base VI is A0x%03x\n",
1041 MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_BASE
));
1043 nic_data
->vi_base
= MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_BASE
);
1044 nic_data
->n_allocated_vis
= MCDI_DWORD(outbuf
, ALLOC_VIS_OUT_VI_COUNT
);
1048 /* Note that the failure path of this function does not free
1049 * resources, as this will be done by efx_ef10_remove().
1051 static int efx_ef10_dimension_resources(struct efx_nic
*efx
)
1053 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1054 unsigned int uc_mem_map_size
, wc_mem_map_size
;
1055 unsigned int min_vis
= max(EFX_TXQ_TYPES
,
1056 efx_separate_tx_channels
? 2 : 1);
1057 unsigned int channel_vis
, pio_write_vi_base
, max_vis
;
1058 void __iomem
*membase
;
1061 channel_vis
= max(efx
->n_channels
, efx
->n_tx_channels
* EFX_TXQ_TYPES
);
1064 /* Try to allocate PIO buffers if wanted and if the full
1065 * number of PIO buffers would be sufficient to allocate one
1066 * copy-buffer per TX channel. Failure is non-fatal, as there
1067 * are only a small number of PIO buffers shared between all
1068 * functions of the controller.
1070 if (efx_piobuf_size
!= 0 &&
1071 ER_DZ_TX_PIOBUF_SIZE
/ efx_piobuf_size
* EF10_TX_PIOBUF_COUNT
>=
1072 efx
->n_tx_channels
) {
1073 unsigned int n_piobufs
=
1074 DIV_ROUND_UP(efx
->n_tx_channels
,
1075 ER_DZ_TX_PIOBUF_SIZE
/ efx_piobuf_size
);
1077 rc
= efx_ef10_alloc_piobufs(efx
, n_piobufs
);
1079 netif_err(efx
, probe
, efx
->net_dev
,
1080 "failed to allocate PIO buffers (%d)\n", rc
);
1082 netif_dbg(efx
, probe
, efx
->net_dev
,
1083 "allocated %u PIO buffers\n", n_piobufs
);
1086 nic_data
->n_piobufs
= 0;
1089 /* PIO buffers should be mapped with write-combining enabled,
1090 * and we want to make single UC and WC mappings rather than
1091 * several of each (in fact that's the only option if host
1092 * page size is >4K). So we may allocate some extra VIs just
1093 * for writing PIO buffers through.
1095 * The UC mapping contains (channel_vis - 1) complete VIs and the
1096 * first half of the next VI. Then the WC mapping begins with
1097 * the second half of this last VI.
1099 uc_mem_map_size
= PAGE_ALIGN((channel_vis
- 1) * EFX_VI_PAGE_SIZE
+
1101 if (nic_data
->n_piobufs
) {
1102 /* pio_write_vi_base rounds down to give the number of complete
1103 * VIs inside the UC mapping.
1105 pio_write_vi_base
= uc_mem_map_size
/ EFX_VI_PAGE_SIZE
;
1106 wc_mem_map_size
= (PAGE_ALIGN((pio_write_vi_base
+
1107 nic_data
->n_piobufs
) *
1110 max_vis
= pio_write_vi_base
+ nic_data
->n_piobufs
;
1112 pio_write_vi_base
= 0;
1113 wc_mem_map_size
= 0;
1114 max_vis
= channel_vis
;
1117 /* In case the last attached driver failed to free VIs, do it now */
1118 rc
= efx_ef10_free_vis(efx
);
1122 rc
= efx_ef10_alloc_vis(efx
, min_vis
, max_vis
);
1126 if (nic_data
->n_allocated_vis
< channel_vis
) {
1127 netif_info(efx
, drv
, efx
->net_dev
,
1128 "Could not allocate enough VIs to satisfy RSS"
1129 " requirements. Performance may not be optimal.\n");
1130 /* We didn't get the VIs to populate our channels.
1131 * We could keep what we got but then we'd have more
1132 * interrupts than we need.
1133 * Instead calculate new max_channels and restart
1135 efx
->max_channels
= nic_data
->n_allocated_vis
;
1136 efx
->max_tx_channels
=
1137 nic_data
->n_allocated_vis
/ EFX_TXQ_TYPES
;
1139 efx_ef10_free_vis(efx
);
1143 /* If we didn't get enough VIs to map all the PIO buffers, free the
1146 if (nic_data
->n_piobufs
&&
1147 nic_data
->n_allocated_vis
<
1148 pio_write_vi_base
+ nic_data
->n_piobufs
) {
1149 netif_dbg(efx
, probe
, efx
->net_dev
,
1150 "%u VIs are not sufficient to map %u PIO buffers\n",
1151 nic_data
->n_allocated_vis
, nic_data
->n_piobufs
);
1152 efx_ef10_free_piobufs(efx
);
1155 /* Shrink the original UC mapping of the memory BAR */
1156 membase
= ioremap_nocache(efx
->membase_phys
, uc_mem_map_size
);
1158 netif_err(efx
, probe
, efx
->net_dev
,
1159 "could not shrink memory BAR to %x\n",
1163 iounmap(efx
->membase
);
1164 efx
->membase
= membase
;
1166 /* Set up the WC mapping if needed */
1167 if (wc_mem_map_size
) {
1168 nic_data
->wc_membase
= ioremap_wc(efx
->membase_phys
+
1171 if (!nic_data
->wc_membase
) {
1172 netif_err(efx
, probe
, efx
->net_dev
,
1173 "could not allocate WC mapping of size %x\n",
1177 nic_data
->pio_write_vi_base
= pio_write_vi_base
;
1178 nic_data
->pio_write_base
=
1179 nic_data
->wc_membase
+
1180 (pio_write_vi_base
* EFX_VI_PAGE_SIZE
+ ER_DZ_TX_PIOBUF
-
1183 rc
= efx_ef10_link_piobufs(efx
);
1185 efx_ef10_free_piobufs(efx
);
1188 netif_dbg(efx
, probe
, efx
->net_dev
,
1189 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n",
1190 &efx
->membase_phys
, efx
->membase
, uc_mem_map_size
,
1191 nic_data
->wc_membase
, wc_mem_map_size
);
1196 static int efx_ef10_init_nic(struct efx_nic
*efx
)
1198 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1201 if (nic_data
->must_check_datapath_caps
) {
1202 rc
= efx_ef10_init_datapath_caps(efx
);
1205 nic_data
->must_check_datapath_caps
= false;
1208 if (nic_data
->must_realloc_vis
) {
1209 /* We cannot let the number of VIs change now */
1210 rc
= efx_ef10_alloc_vis(efx
, nic_data
->n_allocated_vis
,
1211 nic_data
->n_allocated_vis
);
1214 nic_data
->must_realloc_vis
= false;
1217 if (nic_data
->must_restore_piobufs
&& nic_data
->n_piobufs
) {
1218 rc
= efx_ef10_alloc_piobufs(efx
, nic_data
->n_piobufs
);
1220 rc
= efx_ef10_link_piobufs(efx
);
1222 efx_ef10_free_piobufs(efx
);
1225 /* Log an error on failure, but this is non-fatal */
1227 netif_err(efx
, drv
, efx
->net_dev
,
1228 "failed to restore PIO buffers (%d)\n", rc
);
1229 nic_data
->must_restore_piobufs
= false;
1232 /* don't fail init if RSS setup doesn't work */
1233 efx
->type
->rx_push_rss_config(efx
, false, efx
->rx_indir_table
);
1238 static void efx_ef10_reset_mc_allocations(struct efx_nic
*efx
)
1240 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1241 #ifdef CONFIG_SFC_SRIOV
1245 /* All our allocations have been reset */
1246 nic_data
->must_realloc_vis
= true;
1247 nic_data
->must_restore_filters
= true;
1248 nic_data
->must_restore_piobufs
= true;
1249 efx_ef10_forget_old_piobufs(efx
);
1250 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
1252 /* Driver-created vswitches and vports must be re-created */
1253 nic_data
->must_probe_vswitching
= true;
1254 nic_data
->vport_id
= EVB_PORT_ID_ASSIGNED
;
1255 #ifdef CONFIG_SFC_SRIOV
1257 for (i
= 0; i
< efx
->vf_count
; i
++)
1258 nic_data
->vf
[i
].vport_id
= 0;
1262 static enum reset_type
efx_ef10_map_reset_reason(enum reset_type reason
)
1264 if (reason
== RESET_TYPE_MC_FAILURE
)
1265 return RESET_TYPE_DATAPATH
;
1267 return efx_mcdi_map_reset_reason(reason
);
1270 static int efx_ef10_map_reset_flags(u32
*flags
)
1273 EF10_RESET_PORT
= ((ETH_RESET_MAC
| ETH_RESET_PHY
) <<
1274 ETH_RESET_SHARED_SHIFT
),
1275 EF10_RESET_MC
= ((ETH_RESET_DMA
| ETH_RESET_FILTER
|
1276 ETH_RESET_OFFLOAD
| ETH_RESET_MAC
|
1277 ETH_RESET_PHY
| ETH_RESET_MGMT
) <<
1278 ETH_RESET_SHARED_SHIFT
)
1281 /* We assume for now that our PCI function is permitted to
1285 if ((*flags
& EF10_RESET_MC
) == EF10_RESET_MC
) {
1286 *flags
&= ~EF10_RESET_MC
;
1287 return RESET_TYPE_WORLD
;
1290 if ((*flags
& EF10_RESET_PORT
) == EF10_RESET_PORT
) {
1291 *flags
&= ~EF10_RESET_PORT
;
1292 return RESET_TYPE_ALL
;
1295 /* no invisible reset implemented */
1300 static int efx_ef10_reset(struct efx_nic
*efx
, enum reset_type reset_type
)
1302 int rc
= efx_mcdi_reset(efx
, reset_type
);
1304 /* Unprivileged functions return -EPERM, but need to return success
1305 * here so that the datapath is brought back up.
1307 if (reset_type
== RESET_TYPE_WORLD
&& rc
== -EPERM
)
1310 /* If it was a port reset, trigger reallocation of MC resources.
1311 * Note that on an MC reset nothing needs to be done now because we'll
1312 * detect the MC reset later and handle it then.
1313 * For an FLR, we never get an MC reset event, but the MC has reset all
1314 * resources assigned to us, so we have to trigger reallocation now.
1316 if ((reset_type
== RESET_TYPE_ALL
||
1317 reset_type
== RESET_TYPE_MCDI_TIMEOUT
) && !rc
)
1318 efx_ef10_reset_mc_allocations(efx
);
1322 #define EF10_DMA_STAT(ext_name, mcdi_name) \
1323 [EF10_STAT_ ## ext_name] = \
1324 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1325 #define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \
1326 [EF10_STAT_ ## int_name] = \
1327 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
1328 #define EF10_OTHER_STAT(ext_name) \
1329 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1330 #define GENERIC_SW_STAT(ext_name) \
1331 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 }
1333 static const struct efx_hw_stat_desc efx_ef10_stat_desc
[EF10_STAT_COUNT
] = {
1334 EF10_DMA_STAT(port_tx_bytes
, TX_BYTES
),
1335 EF10_DMA_STAT(port_tx_packets
, TX_PKTS
),
1336 EF10_DMA_STAT(port_tx_pause
, TX_PAUSE_PKTS
),
1337 EF10_DMA_STAT(port_tx_control
, TX_CONTROL_PKTS
),
1338 EF10_DMA_STAT(port_tx_unicast
, TX_UNICAST_PKTS
),
1339 EF10_DMA_STAT(port_tx_multicast
, TX_MULTICAST_PKTS
),
1340 EF10_DMA_STAT(port_tx_broadcast
, TX_BROADCAST_PKTS
),
1341 EF10_DMA_STAT(port_tx_lt64
, TX_LT64_PKTS
),
1342 EF10_DMA_STAT(port_tx_64
, TX_64_PKTS
),
1343 EF10_DMA_STAT(port_tx_65_to_127
, TX_65_TO_127_PKTS
),
1344 EF10_DMA_STAT(port_tx_128_to_255
, TX_128_TO_255_PKTS
),
1345 EF10_DMA_STAT(port_tx_256_to_511
, TX_256_TO_511_PKTS
),
1346 EF10_DMA_STAT(port_tx_512_to_1023
, TX_512_TO_1023_PKTS
),
1347 EF10_DMA_STAT(port_tx_1024_to_15xx
, TX_1024_TO_15XX_PKTS
),
1348 EF10_DMA_STAT(port_tx_15xx_to_jumbo
, TX_15XX_TO_JUMBO_PKTS
),
1349 EF10_DMA_STAT(port_rx_bytes
, RX_BYTES
),
1350 EF10_DMA_INVIS_STAT(port_rx_bytes_minus_good_bytes
, RX_BAD_BYTES
),
1351 EF10_OTHER_STAT(port_rx_good_bytes
),
1352 EF10_OTHER_STAT(port_rx_bad_bytes
),
1353 EF10_DMA_STAT(port_rx_packets
, RX_PKTS
),
1354 EF10_DMA_STAT(port_rx_good
, RX_GOOD_PKTS
),
1355 EF10_DMA_STAT(port_rx_bad
, RX_BAD_FCS_PKTS
),
1356 EF10_DMA_STAT(port_rx_pause
, RX_PAUSE_PKTS
),
1357 EF10_DMA_STAT(port_rx_control
, RX_CONTROL_PKTS
),
1358 EF10_DMA_STAT(port_rx_unicast
, RX_UNICAST_PKTS
),
1359 EF10_DMA_STAT(port_rx_multicast
, RX_MULTICAST_PKTS
),
1360 EF10_DMA_STAT(port_rx_broadcast
, RX_BROADCAST_PKTS
),
1361 EF10_DMA_STAT(port_rx_lt64
, RX_UNDERSIZE_PKTS
),
1362 EF10_DMA_STAT(port_rx_64
, RX_64_PKTS
),
1363 EF10_DMA_STAT(port_rx_65_to_127
, RX_65_TO_127_PKTS
),
1364 EF10_DMA_STAT(port_rx_128_to_255
, RX_128_TO_255_PKTS
),
1365 EF10_DMA_STAT(port_rx_256_to_511
, RX_256_TO_511_PKTS
),
1366 EF10_DMA_STAT(port_rx_512_to_1023
, RX_512_TO_1023_PKTS
),
1367 EF10_DMA_STAT(port_rx_1024_to_15xx
, RX_1024_TO_15XX_PKTS
),
1368 EF10_DMA_STAT(port_rx_15xx_to_jumbo
, RX_15XX_TO_JUMBO_PKTS
),
1369 EF10_DMA_STAT(port_rx_gtjumbo
, RX_GTJUMBO_PKTS
),
1370 EF10_DMA_STAT(port_rx_bad_gtjumbo
, RX_JABBER_PKTS
),
1371 EF10_DMA_STAT(port_rx_overflow
, RX_OVERFLOW_PKTS
),
1372 EF10_DMA_STAT(port_rx_align_error
, RX_ALIGN_ERROR_PKTS
),
1373 EF10_DMA_STAT(port_rx_length_error
, RX_LENGTH_ERROR_PKTS
),
1374 EF10_DMA_STAT(port_rx_nodesc_drops
, RX_NODESC_DROPS
),
1375 GENERIC_SW_STAT(rx_nodesc_trunc
),
1376 GENERIC_SW_STAT(rx_noskb_drops
),
1377 EF10_DMA_STAT(port_rx_pm_trunc_bb_overflow
, PM_TRUNC_BB_OVERFLOW
),
1378 EF10_DMA_STAT(port_rx_pm_discard_bb_overflow
, PM_DISCARD_BB_OVERFLOW
),
1379 EF10_DMA_STAT(port_rx_pm_trunc_vfifo_full
, PM_TRUNC_VFIFO_FULL
),
1380 EF10_DMA_STAT(port_rx_pm_discard_vfifo_full
, PM_DISCARD_VFIFO_FULL
),
1381 EF10_DMA_STAT(port_rx_pm_trunc_qbb
, PM_TRUNC_QBB
),
1382 EF10_DMA_STAT(port_rx_pm_discard_qbb
, PM_DISCARD_QBB
),
1383 EF10_DMA_STAT(port_rx_pm_discard_mapping
, PM_DISCARD_MAPPING
),
1384 EF10_DMA_STAT(port_rx_dp_q_disabled_packets
, RXDP_Q_DISABLED_PKTS
),
1385 EF10_DMA_STAT(port_rx_dp_di_dropped_packets
, RXDP_DI_DROPPED_PKTS
),
1386 EF10_DMA_STAT(port_rx_dp_streaming_packets
, RXDP_STREAMING_PKTS
),
1387 EF10_DMA_STAT(port_rx_dp_hlb_fetch
, RXDP_HLB_FETCH_CONDITIONS
),
1388 EF10_DMA_STAT(port_rx_dp_hlb_wait
, RXDP_HLB_WAIT_CONDITIONS
),
1389 EF10_DMA_STAT(rx_unicast
, VADAPTER_RX_UNICAST_PACKETS
),
1390 EF10_DMA_STAT(rx_unicast_bytes
, VADAPTER_RX_UNICAST_BYTES
),
1391 EF10_DMA_STAT(rx_multicast
, VADAPTER_RX_MULTICAST_PACKETS
),
1392 EF10_DMA_STAT(rx_multicast_bytes
, VADAPTER_RX_MULTICAST_BYTES
),
1393 EF10_DMA_STAT(rx_broadcast
, VADAPTER_RX_BROADCAST_PACKETS
),
1394 EF10_DMA_STAT(rx_broadcast_bytes
, VADAPTER_RX_BROADCAST_BYTES
),
1395 EF10_DMA_STAT(rx_bad
, VADAPTER_RX_BAD_PACKETS
),
1396 EF10_DMA_STAT(rx_bad_bytes
, VADAPTER_RX_BAD_BYTES
),
1397 EF10_DMA_STAT(rx_overflow
, VADAPTER_RX_OVERFLOW
),
1398 EF10_DMA_STAT(tx_unicast
, VADAPTER_TX_UNICAST_PACKETS
),
1399 EF10_DMA_STAT(tx_unicast_bytes
, VADAPTER_TX_UNICAST_BYTES
),
1400 EF10_DMA_STAT(tx_multicast
, VADAPTER_TX_MULTICAST_PACKETS
),
1401 EF10_DMA_STAT(tx_multicast_bytes
, VADAPTER_TX_MULTICAST_BYTES
),
1402 EF10_DMA_STAT(tx_broadcast
, VADAPTER_TX_BROADCAST_PACKETS
),
1403 EF10_DMA_STAT(tx_broadcast_bytes
, VADAPTER_TX_BROADCAST_BYTES
),
1404 EF10_DMA_STAT(tx_bad
, VADAPTER_TX_BAD_PACKETS
),
1405 EF10_DMA_STAT(tx_bad_bytes
, VADAPTER_TX_BAD_BYTES
),
1406 EF10_DMA_STAT(tx_overflow
, VADAPTER_TX_OVERFLOW
),
1409 #define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_port_tx_bytes) | \
1410 (1ULL << EF10_STAT_port_tx_packets) | \
1411 (1ULL << EF10_STAT_port_tx_pause) | \
1412 (1ULL << EF10_STAT_port_tx_unicast) | \
1413 (1ULL << EF10_STAT_port_tx_multicast) | \
1414 (1ULL << EF10_STAT_port_tx_broadcast) | \
1415 (1ULL << EF10_STAT_port_rx_bytes) | \
1417 EF10_STAT_port_rx_bytes_minus_good_bytes) | \
1418 (1ULL << EF10_STAT_port_rx_good_bytes) | \
1419 (1ULL << EF10_STAT_port_rx_bad_bytes) | \
1420 (1ULL << EF10_STAT_port_rx_packets) | \
1421 (1ULL << EF10_STAT_port_rx_good) | \
1422 (1ULL << EF10_STAT_port_rx_bad) | \
1423 (1ULL << EF10_STAT_port_rx_pause) | \
1424 (1ULL << EF10_STAT_port_rx_control) | \
1425 (1ULL << EF10_STAT_port_rx_unicast) | \
1426 (1ULL << EF10_STAT_port_rx_multicast) | \
1427 (1ULL << EF10_STAT_port_rx_broadcast) | \
1428 (1ULL << EF10_STAT_port_rx_lt64) | \
1429 (1ULL << EF10_STAT_port_rx_64) | \
1430 (1ULL << EF10_STAT_port_rx_65_to_127) | \
1431 (1ULL << EF10_STAT_port_rx_128_to_255) | \
1432 (1ULL << EF10_STAT_port_rx_256_to_511) | \
1433 (1ULL << EF10_STAT_port_rx_512_to_1023) |\
1434 (1ULL << EF10_STAT_port_rx_1024_to_15xx) |\
1435 (1ULL << EF10_STAT_port_rx_15xx_to_jumbo) |\
1436 (1ULL << EF10_STAT_port_rx_gtjumbo) | \
1437 (1ULL << EF10_STAT_port_rx_bad_gtjumbo) |\
1438 (1ULL << EF10_STAT_port_rx_overflow) | \
1439 (1ULL << EF10_STAT_port_rx_nodesc_drops) |\
1440 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \
1441 (1ULL << GENERIC_STAT_rx_noskb_drops))
1443 /* These statistics are only provided by the 10G MAC. For a 10G/40G
1444 * switchable port we do not expose these because they might not
1445 * include all the packets they should.
1447 #define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_port_tx_control) | \
1448 (1ULL << EF10_STAT_port_tx_lt64) | \
1449 (1ULL << EF10_STAT_port_tx_64) | \
1450 (1ULL << EF10_STAT_port_tx_65_to_127) |\
1451 (1ULL << EF10_STAT_port_tx_128_to_255) |\
1452 (1ULL << EF10_STAT_port_tx_256_to_511) |\
1453 (1ULL << EF10_STAT_port_tx_512_to_1023) |\
1454 (1ULL << EF10_STAT_port_tx_1024_to_15xx) |\
1455 (1ULL << EF10_STAT_port_tx_15xx_to_jumbo))
1457 /* These statistics are only provided by the 40G MAC. For a 10G/40G
1458 * switchable port we do expose these because the errors will otherwise
1461 #define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_port_rx_align_error) |\
1462 (1ULL << EF10_STAT_port_rx_length_error))
1464 /* These statistics are only provided if the firmware supports the
1465 * capability PM_AND_RXDP_COUNTERS.
1467 #define HUNT_PM_AND_RXDP_STAT_MASK ( \
1468 (1ULL << EF10_STAT_port_rx_pm_trunc_bb_overflow) | \
1469 (1ULL << EF10_STAT_port_rx_pm_discard_bb_overflow) | \
1470 (1ULL << EF10_STAT_port_rx_pm_trunc_vfifo_full) | \
1471 (1ULL << EF10_STAT_port_rx_pm_discard_vfifo_full) | \
1472 (1ULL << EF10_STAT_port_rx_pm_trunc_qbb) | \
1473 (1ULL << EF10_STAT_port_rx_pm_discard_qbb) | \
1474 (1ULL << EF10_STAT_port_rx_pm_discard_mapping) | \
1475 (1ULL << EF10_STAT_port_rx_dp_q_disabled_packets) | \
1476 (1ULL << EF10_STAT_port_rx_dp_di_dropped_packets) | \
1477 (1ULL << EF10_STAT_port_rx_dp_streaming_packets) | \
1478 (1ULL << EF10_STAT_port_rx_dp_hlb_fetch) | \
1479 (1ULL << EF10_STAT_port_rx_dp_hlb_wait))
1481 static u64
efx_ef10_raw_stat_mask(struct efx_nic
*efx
)
1483 u64 raw_mask
= HUNT_COMMON_STAT_MASK
;
1484 u32 port_caps
= efx_mcdi_phy_get_caps(efx
);
1485 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1487 if (!(efx
->mcdi
->fn_flags
&
1488 1 << MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL
))
1491 if (port_caps
& (1 << MC_CMD_PHY_CAP_40000FDX_LBN
))
1492 raw_mask
|= HUNT_40G_EXTRA_STAT_MASK
;
1494 raw_mask
|= HUNT_10G_ONLY_STAT_MASK
;
1496 if (nic_data
->datapath_caps
&
1497 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN
))
1498 raw_mask
|= HUNT_PM_AND_RXDP_STAT_MASK
;
1503 static void efx_ef10_get_stat_mask(struct efx_nic
*efx
, unsigned long *mask
)
1505 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1508 raw_mask
[0] = efx_ef10_raw_stat_mask(efx
);
1510 /* Only show vadaptor stats when EVB capability is present */
1511 if (nic_data
->datapath_caps
&
1512 (1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN
)) {
1513 raw_mask
[0] |= ~((1ULL << EF10_STAT_rx_unicast
) - 1);
1514 raw_mask
[1] = (1ULL << (EF10_STAT_COUNT
- 63)) - 1;
1519 #if BITS_PER_LONG == 64
1520 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT
) != 2);
1521 mask
[0] = raw_mask
[0];
1522 mask
[1] = raw_mask
[1];
1524 BUILD_BUG_ON(BITS_TO_LONGS(EF10_STAT_COUNT
) != 3);
1525 mask
[0] = raw_mask
[0] & 0xffffffff;
1526 mask
[1] = raw_mask
[0] >> 32;
1527 mask
[2] = raw_mask
[1] & 0xffffffff;
1531 static size_t efx_ef10_describe_stats(struct efx_nic
*efx
, u8
*names
)
1533 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1535 efx_ef10_get_stat_mask(efx
, mask
);
1536 return efx_nic_describe_stats(efx_ef10_stat_desc
, EF10_STAT_COUNT
,
1540 static size_t efx_ef10_update_stats_common(struct efx_nic
*efx
, u64
*full_stats
,
1541 struct rtnl_link_stats64
*core_stats
)
1543 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1544 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1545 u64
*stats
= nic_data
->stats
;
1546 size_t stats_count
= 0, index
;
1548 efx_ef10_get_stat_mask(efx
, mask
);
1551 for_each_set_bit(index
, mask
, EF10_STAT_COUNT
) {
1552 if (efx_ef10_stat_desc
[index
].name
) {
1553 *full_stats
++ = stats
[index
];
1562 if (nic_data
->datapath_caps
&
1563 1 << MC_CMD_GET_CAPABILITIES_OUT_EVB_LBN
) {
1564 /* Use vadaptor stats. */
1565 core_stats
->rx_packets
= stats
[EF10_STAT_rx_unicast
] +
1566 stats
[EF10_STAT_rx_multicast
] +
1567 stats
[EF10_STAT_rx_broadcast
];
1568 core_stats
->tx_packets
= stats
[EF10_STAT_tx_unicast
] +
1569 stats
[EF10_STAT_tx_multicast
] +
1570 stats
[EF10_STAT_tx_broadcast
];
1571 core_stats
->rx_bytes
= stats
[EF10_STAT_rx_unicast_bytes
] +
1572 stats
[EF10_STAT_rx_multicast_bytes
] +
1573 stats
[EF10_STAT_rx_broadcast_bytes
];
1574 core_stats
->tx_bytes
= stats
[EF10_STAT_tx_unicast_bytes
] +
1575 stats
[EF10_STAT_tx_multicast_bytes
] +
1576 stats
[EF10_STAT_tx_broadcast_bytes
];
1577 core_stats
->rx_dropped
= stats
[GENERIC_STAT_rx_nodesc_trunc
] +
1578 stats
[GENERIC_STAT_rx_noskb_drops
];
1579 core_stats
->multicast
= stats
[EF10_STAT_rx_multicast
];
1580 core_stats
->rx_crc_errors
= stats
[EF10_STAT_rx_bad
];
1581 core_stats
->rx_fifo_errors
= stats
[EF10_STAT_rx_overflow
];
1582 core_stats
->rx_errors
= core_stats
->rx_crc_errors
;
1583 core_stats
->tx_errors
= stats
[EF10_STAT_tx_bad
];
1585 /* Use port stats. */
1586 core_stats
->rx_packets
= stats
[EF10_STAT_port_rx_packets
];
1587 core_stats
->tx_packets
= stats
[EF10_STAT_port_tx_packets
];
1588 core_stats
->rx_bytes
= stats
[EF10_STAT_port_rx_bytes
];
1589 core_stats
->tx_bytes
= stats
[EF10_STAT_port_tx_bytes
];
1590 core_stats
->rx_dropped
= stats
[EF10_STAT_port_rx_nodesc_drops
] +
1591 stats
[GENERIC_STAT_rx_nodesc_trunc
] +
1592 stats
[GENERIC_STAT_rx_noskb_drops
];
1593 core_stats
->multicast
= stats
[EF10_STAT_port_rx_multicast
];
1594 core_stats
->rx_length_errors
=
1595 stats
[EF10_STAT_port_rx_gtjumbo
] +
1596 stats
[EF10_STAT_port_rx_length_error
];
1597 core_stats
->rx_crc_errors
= stats
[EF10_STAT_port_rx_bad
];
1598 core_stats
->rx_frame_errors
=
1599 stats
[EF10_STAT_port_rx_align_error
];
1600 core_stats
->rx_fifo_errors
= stats
[EF10_STAT_port_rx_overflow
];
1601 core_stats
->rx_errors
= (core_stats
->rx_length_errors
+
1602 core_stats
->rx_crc_errors
+
1603 core_stats
->rx_frame_errors
);
1609 static int efx_ef10_try_update_nic_stats_pf(struct efx_nic
*efx
)
1611 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1612 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1613 __le64 generation_start
, generation_end
;
1614 u64
*stats
= nic_data
->stats
;
1617 efx_ef10_get_stat_mask(efx
, mask
);
1619 dma_stats
= efx
->stats_buffer
.addr
;
1620 nic_data
= efx
->nic_data
;
1622 generation_end
= dma_stats
[MC_CMD_MAC_GENERATION_END
];
1623 if (generation_end
== EFX_MC_STATS_GENERATION_INVALID
)
1626 efx_nic_update_stats(efx_ef10_stat_desc
, EF10_STAT_COUNT
, mask
,
1627 stats
, efx
->stats_buffer
.addr
, false);
1629 generation_start
= dma_stats
[MC_CMD_MAC_GENERATION_START
];
1630 if (generation_end
!= generation_start
)
1633 /* Update derived statistics */
1634 efx_nic_fix_nodesc_drop_stat(efx
,
1635 &stats
[EF10_STAT_port_rx_nodesc_drops
]);
1636 stats
[EF10_STAT_port_rx_good_bytes
] =
1637 stats
[EF10_STAT_port_rx_bytes
] -
1638 stats
[EF10_STAT_port_rx_bytes_minus_good_bytes
];
1639 efx_update_diff_stat(&stats
[EF10_STAT_port_rx_bad_bytes
],
1640 stats
[EF10_STAT_port_rx_bytes_minus_good_bytes
]);
1641 efx_update_sw_stats(efx
, stats
);
1646 static size_t efx_ef10_update_stats_pf(struct efx_nic
*efx
, u64
*full_stats
,
1647 struct rtnl_link_stats64
*core_stats
)
1651 /* If we're unlucky enough to read statistics during the DMA, wait
1652 * up to 10ms for it to finish (typically takes <500us)
1654 for (retry
= 0; retry
< 100; ++retry
) {
1655 if (efx_ef10_try_update_nic_stats_pf(efx
) == 0)
1660 return efx_ef10_update_stats_common(efx
, full_stats
, core_stats
);
1663 static int efx_ef10_try_update_nic_stats_vf(struct efx_nic
*efx
)
1665 MCDI_DECLARE_BUF(inbuf
, MC_CMD_MAC_STATS_IN_LEN
);
1666 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1667 DECLARE_BITMAP(mask
, EF10_STAT_COUNT
);
1668 __le64 generation_start
, generation_end
;
1669 u64
*stats
= nic_data
->stats
;
1670 u32 dma_len
= MC_CMD_MAC_NSTATS
* sizeof(u64
);
1671 struct efx_buffer stats_buf
;
1675 spin_unlock_bh(&efx
->stats_lock
);
1677 if (in_interrupt()) {
1678 /* If in atomic context, cannot update stats. Just update the
1679 * software stats and return so the caller can continue.
1681 spin_lock_bh(&efx
->stats_lock
);
1682 efx_update_sw_stats(efx
, stats
);
1686 efx_ef10_get_stat_mask(efx
, mask
);
1688 rc
= efx_nic_alloc_buffer(efx
, &stats_buf
, dma_len
, GFP_ATOMIC
);
1690 spin_lock_bh(&efx
->stats_lock
);
1694 dma_stats
= stats_buf
.addr
;
1695 dma_stats
[MC_CMD_MAC_GENERATION_END
] = EFX_MC_STATS_GENERATION_INVALID
;
1697 MCDI_SET_QWORD(inbuf
, MAC_STATS_IN_DMA_ADDR
, stats_buf
.dma_addr
);
1698 MCDI_POPULATE_DWORD_1(inbuf
, MAC_STATS_IN_CMD
,
1699 MAC_STATS_IN_DMA
, 1);
1700 MCDI_SET_DWORD(inbuf
, MAC_STATS_IN_DMA_LEN
, dma_len
);
1701 MCDI_SET_DWORD(inbuf
, MAC_STATS_IN_PORT_ID
, EVB_PORT_ID_ASSIGNED
);
1703 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_MAC_STATS
, inbuf
, sizeof(inbuf
),
1705 spin_lock_bh(&efx
->stats_lock
);
1707 /* Expect ENOENT if DMA queues have not been set up */
1708 if (rc
!= -ENOENT
|| atomic_read(&efx
->active_queues
))
1709 efx_mcdi_display_error(efx
, MC_CMD_MAC_STATS
,
1710 sizeof(inbuf
), NULL
, 0, rc
);
1714 generation_end
= dma_stats
[MC_CMD_MAC_GENERATION_END
];
1715 if (generation_end
== EFX_MC_STATS_GENERATION_INVALID
) {
1720 efx_nic_update_stats(efx_ef10_stat_desc
, EF10_STAT_COUNT
, mask
,
1721 stats
, stats_buf
.addr
, false);
1723 generation_start
= dma_stats
[MC_CMD_MAC_GENERATION_START
];
1724 if (generation_end
!= generation_start
) {
1729 efx_update_sw_stats(efx
, stats
);
1731 efx_nic_free_buffer(efx
, &stats_buf
);
1735 static size_t efx_ef10_update_stats_vf(struct efx_nic
*efx
, u64
*full_stats
,
1736 struct rtnl_link_stats64
*core_stats
)
1738 if (efx_ef10_try_update_nic_stats_vf(efx
))
1741 return efx_ef10_update_stats_common(efx
, full_stats
, core_stats
);
1744 static void efx_ef10_push_irq_moderation(struct efx_channel
*channel
)
1746 struct efx_nic
*efx
= channel
->efx
;
1747 unsigned int mode
, value
;
1748 efx_dword_t timer_cmd
;
1750 if (channel
->irq_moderation
) {
1752 value
= channel
->irq_moderation
- 1;
1758 if (EFX_EF10_WORKAROUND_35388(efx
)) {
1759 EFX_POPULATE_DWORD_3(timer_cmd
, ERF_DD_EVQ_IND_TIMER_FLAGS
,
1760 EFE_DD_EVQ_IND_TIMER_FLAGS
,
1761 ERF_DD_EVQ_IND_TIMER_MODE
, mode
,
1762 ERF_DD_EVQ_IND_TIMER_VAL
, value
);
1763 efx_writed_page(efx
, &timer_cmd
, ER_DD_EVQ_INDIRECT
,
1766 EFX_POPULATE_DWORD_2(timer_cmd
, ERF_DZ_TC_TIMER_MODE
, mode
,
1767 ERF_DZ_TC_TIMER_VAL
, value
);
1768 efx_writed_page(efx
, &timer_cmd
, ER_DZ_EVQ_TMR
,
1773 static void efx_ef10_get_wol_vf(struct efx_nic
*efx
,
1774 struct ethtool_wolinfo
*wol
) {}
1776 static int efx_ef10_set_wol_vf(struct efx_nic
*efx
, u32 type
)
1781 static void efx_ef10_get_wol(struct efx_nic
*efx
, struct ethtool_wolinfo
*wol
)
1785 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
1788 static int efx_ef10_set_wol(struct efx_nic
*efx
, u32 type
)
1795 static void efx_ef10_mcdi_request(struct efx_nic
*efx
,
1796 const efx_dword_t
*hdr
, size_t hdr_len
,
1797 const efx_dword_t
*sdu
, size_t sdu_len
)
1799 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1800 u8
*pdu
= nic_data
->mcdi_buf
.addr
;
1802 memcpy(pdu
, hdr
, hdr_len
);
1803 memcpy(pdu
+ hdr_len
, sdu
, sdu_len
);
1806 /* The hardware provides 'low' and 'high' (doorbell) registers
1807 * for passing the 64-bit address of an MCDI request to
1808 * firmware. However the dwords are swapped by firmware. The
1809 * least significant bits of the doorbell are then 0 for all
1810 * MCDI requests due to alignment.
1812 _efx_writed(efx
, cpu_to_le32((u64
)nic_data
->mcdi_buf
.dma_addr
>> 32),
1814 _efx_writed(efx
, cpu_to_le32((u32
)nic_data
->mcdi_buf
.dma_addr
),
1818 static bool efx_ef10_mcdi_poll_response(struct efx_nic
*efx
)
1820 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1821 const efx_dword_t hdr
= *(const efx_dword_t
*)nic_data
->mcdi_buf
.addr
;
1824 return EFX_DWORD_FIELD(hdr
, MCDI_HEADER_RESPONSE
);
1828 efx_ef10_mcdi_read_response(struct efx_nic
*efx
, efx_dword_t
*outbuf
,
1829 size_t offset
, size_t outlen
)
1831 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1832 const u8
*pdu
= nic_data
->mcdi_buf
.addr
;
1834 memcpy(outbuf
, pdu
+ offset
, outlen
);
1837 static void efx_ef10_mcdi_reboot_detected(struct efx_nic
*efx
)
1839 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1841 /* All our allocations have been reset */
1842 efx_ef10_reset_mc_allocations(efx
);
1844 /* The datapath firmware might have been changed */
1845 nic_data
->must_check_datapath_caps
= true;
1847 /* MAC statistics have been cleared on the NIC; clear the local
1848 * statistic that we update with efx_update_diff_stat().
1850 nic_data
->stats
[EF10_STAT_port_rx_bad_bytes
] = 0;
1853 static int efx_ef10_mcdi_poll_reboot(struct efx_nic
*efx
)
1855 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1858 rc
= efx_ef10_get_warm_boot_count(efx
);
1860 /* The firmware is presumably in the process of
1861 * rebooting. However, we are supposed to report each
1862 * reboot just once, so we must only do that once we
1863 * can read and store the updated warm boot count.
1868 if (rc
== nic_data
->warm_boot_count
)
1871 nic_data
->warm_boot_count
= rc
;
1872 efx_ef10_mcdi_reboot_detected(efx
);
1877 /* Handle an MSI interrupt
1879 * Handle an MSI hardware interrupt. This routine schedules event
1880 * queue processing. No interrupt acknowledgement cycle is necessary.
1881 * Also, we never need to check that the interrupt is for us, since
1882 * MSI interrupts cannot be shared.
1884 static irqreturn_t
efx_ef10_msi_interrupt(int irq
, void *dev_id
)
1886 struct efx_msi_context
*context
= dev_id
;
1887 struct efx_nic
*efx
= context
->efx
;
1889 netif_vdbg(efx
, intr
, efx
->net_dev
,
1890 "IRQ %d on CPU %d\n", irq
, raw_smp_processor_id());
1892 if (likely(ACCESS_ONCE(efx
->irq_soft_enabled
))) {
1893 /* Note test interrupts */
1894 if (context
->index
== efx
->irq_level
)
1895 efx
->last_irq_cpu
= raw_smp_processor_id();
1897 /* Schedule processing of the channel */
1898 efx_schedule_channel_irq(efx
->channel
[context
->index
]);
1904 static irqreturn_t
efx_ef10_legacy_interrupt(int irq
, void *dev_id
)
1906 struct efx_nic
*efx
= dev_id
;
1907 bool soft_enabled
= ACCESS_ONCE(efx
->irq_soft_enabled
);
1908 struct efx_channel
*channel
;
1912 /* Read the ISR which also ACKs the interrupts */
1913 efx_readd(efx
, ®
, ER_DZ_BIU_INT_ISR
);
1914 queues
= EFX_DWORD_FIELD(reg
, ERF_DZ_ISR_REG
);
1919 if (likely(soft_enabled
)) {
1920 /* Note test interrupts */
1921 if (queues
& (1U << efx
->irq_level
))
1922 efx
->last_irq_cpu
= raw_smp_processor_id();
1924 efx_for_each_channel(channel
, efx
) {
1926 efx_schedule_channel_irq(channel
);
1931 netif_vdbg(efx
, intr
, efx
->net_dev
,
1932 "IRQ %d on CPU %d status " EFX_DWORD_FMT
"\n",
1933 irq
, raw_smp_processor_id(), EFX_DWORD_VAL(reg
));
1938 static void efx_ef10_irq_test_generate(struct efx_nic
*efx
)
1940 MCDI_DECLARE_BUF(inbuf
, MC_CMD_TRIGGER_INTERRUPT_IN_LEN
);
1942 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN
!= 0);
1944 MCDI_SET_DWORD(inbuf
, TRIGGER_INTERRUPT_IN_INTR_LEVEL
, efx
->irq_level
);
1945 (void) efx_mcdi_rpc(efx
, MC_CMD_TRIGGER_INTERRUPT
,
1946 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
1949 static int efx_ef10_tx_probe(struct efx_tx_queue
*tx_queue
)
1951 return efx_nic_alloc_buffer(tx_queue
->efx
, &tx_queue
->txd
.buf
,
1952 (tx_queue
->ptr_mask
+ 1) *
1953 sizeof(efx_qword_t
),
1957 /* This writes to the TX_DESC_WPTR and also pushes data */
1958 static inline void efx_ef10_push_tx_desc(struct efx_tx_queue
*tx_queue
,
1959 const efx_qword_t
*txd
)
1961 unsigned int write_ptr
;
1964 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
1965 EFX_POPULATE_OWORD_1(reg
, ERF_DZ_TX_DESC_WPTR
, write_ptr
);
1966 reg
.qword
[0] = *txd
;
1967 efx_writeo_page(tx_queue
->efx
, ®
,
1968 ER_DZ_TX_DESC_UPD
, tx_queue
->queue
);
1971 static void efx_ef10_tx_init(struct efx_tx_queue
*tx_queue
)
1973 MCDI_DECLARE_BUF(inbuf
, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE
* 8 /
1975 bool csum_offload
= tx_queue
->queue
& EFX_TXQ_TYPE_OFFLOAD
;
1976 size_t entries
= tx_queue
->txd
.buf
.len
/ EFX_BUF_SIZE
;
1977 struct efx_channel
*channel
= tx_queue
->channel
;
1978 struct efx_nic
*efx
= tx_queue
->efx
;
1979 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
1981 dma_addr_t dma_addr
;
1985 BUILD_BUG_ON(MC_CMD_INIT_TXQ_OUT_LEN
!= 0);
1987 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_SIZE
, tx_queue
->ptr_mask
+ 1);
1988 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_TARGET_EVQ
, channel
->channel
);
1989 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_LABEL
, tx_queue
->queue
);
1990 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_INSTANCE
, tx_queue
->queue
);
1991 MCDI_POPULATE_DWORD_2(inbuf
, INIT_TXQ_IN_FLAGS
,
1992 INIT_TXQ_IN_FLAG_IP_CSUM_DIS
, !csum_offload
,
1993 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS
, !csum_offload
);
1994 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_OWNER_ID
, 0);
1995 MCDI_SET_DWORD(inbuf
, INIT_TXQ_IN_PORT_ID
, nic_data
->vport_id
);
1997 dma_addr
= tx_queue
->txd
.buf
.dma_addr
;
1999 netif_dbg(efx
, hw
, efx
->net_dev
, "pushing TXQ %d. %zu entries (%llx)\n",
2000 tx_queue
->queue
, entries
, (u64
)dma_addr
);
2002 for (i
= 0; i
< entries
; ++i
) {
2003 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_TXQ_IN_DMA_ADDR
, i
, dma_addr
);
2004 dma_addr
+= EFX_BUF_SIZE
;
2007 inlen
= MC_CMD_INIT_TXQ_IN_LEN(entries
);
2009 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_TXQ
, inbuf
, inlen
,
2014 /* A previous user of this TX queue might have set us up the
2015 * bomb by writing a descriptor to the TX push collector but
2016 * not the doorbell. (Each collector belongs to a port, not a
2017 * queue or function, so cannot easily be reset.) We must
2018 * attempt to push a no-op descriptor in its place.
2020 tx_queue
->buffer
[0].flags
= EFX_TX_BUF_OPTION
;
2021 tx_queue
->insert_count
= 1;
2022 txd
= efx_tx_desc(tx_queue
, 0);
2023 EFX_POPULATE_QWORD_4(*txd
,
2024 ESF_DZ_TX_DESC_IS_OPT
, true,
2025 ESF_DZ_TX_OPTION_TYPE
,
2026 ESE_DZ_TX_OPTION_DESC_CRC_CSUM
,
2027 ESF_DZ_TX_OPTION_UDP_TCP_CSUM
, csum_offload
,
2028 ESF_DZ_TX_OPTION_IP_CSUM
, csum_offload
);
2029 tx_queue
->write_count
= 1;
2031 if (nic_data
->datapath_caps
&
2032 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN
)) {
2033 tx_queue
->tso_version
= 1;
2037 efx_ef10_push_tx_desc(tx_queue
, txd
);
2042 netdev_WARN(efx
->net_dev
, "failed to initialise TXQ %d\n",
2046 static void efx_ef10_tx_fini(struct efx_tx_queue
*tx_queue
)
2048 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_TXQ_IN_LEN
);
2049 MCDI_DECLARE_BUF_ERR(outbuf
);
2050 struct efx_nic
*efx
= tx_queue
->efx
;
2054 MCDI_SET_DWORD(inbuf
, FINI_TXQ_IN_INSTANCE
,
2057 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_TXQ
, inbuf
, sizeof(inbuf
),
2058 outbuf
, sizeof(outbuf
), &outlen
);
2060 if (rc
&& rc
!= -EALREADY
)
2066 efx_mcdi_display_error(efx
, MC_CMD_FINI_TXQ
, MC_CMD_FINI_TXQ_IN_LEN
,
2067 outbuf
, outlen
, rc
);
2070 static void efx_ef10_tx_remove(struct efx_tx_queue
*tx_queue
)
2072 efx_nic_free_buffer(tx_queue
->efx
, &tx_queue
->txd
.buf
);
2075 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
2076 static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue
*tx_queue
)
2078 unsigned int write_ptr
;
2081 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
2082 EFX_POPULATE_DWORD_1(reg
, ERF_DZ_TX_DESC_WPTR_DWORD
, write_ptr
);
2083 efx_writed_page(tx_queue
->efx
, ®
,
2084 ER_DZ_TX_DESC_UPD_DWORD
, tx_queue
->queue
);
2087 static void efx_ef10_tx_write(struct efx_tx_queue
*tx_queue
)
2089 unsigned int old_write_count
= tx_queue
->write_count
;
2090 struct efx_tx_buffer
*buffer
;
2091 unsigned int write_ptr
;
2094 tx_queue
->xmit_more_available
= false;
2095 if (unlikely(tx_queue
->write_count
== tx_queue
->insert_count
))
2099 write_ptr
= tx_queue
->write_count
& tx_queue
->ptr_mask
;
2100 buffer
= &tx_queue
->buffer
[write_ptr
];
2101 txd
= efx_tx_desc(tx_queue
, write_ptr
);
2102 ++tx_queue
->write_count
;
2104 /* Create TX descriptor ring entry */
2105 if (buffer
->flags
& EFX_TX_BUF_OPTION
) {
2106 *txd
= buffer
->option
;
2108 BUILD_BUG_ON(EFX_TX_BUF_CONT
!= 1);
2109 EFX_POPULATE_QWORD_3(
2112 buffer
->flags
& EFX_TX_BUF_CONT
,
2113 ESF_DZ_TX_KER_BYTE_CNT
, buffer
->len
,
2114 ESF_DZ_TX_KER_BUF_ADDR
, buffer
->dma_addr
);
2116 } while (tx_queue
->write_count
!= tx_queue
->insert_count
);
2118 wmb(); /* Ensure descriptors are written before they are fetched */
2120 if (efx_nic_may_push_tx_desc(tx_queue
, old_write_count
)) {
2121 txd
= efx_tx_desc(tx_queue
,
2122 old_write_count
& tx_queue
->ptr_mask
);
2123 efx_ef10_push_tx_desc(tx_queue
, txd
);
2126 efx_ef10_notify_tx_desc(tx_queue
);
2130 static int efx_ef10_alloc_rss_context(struct efx_nic
*efx
, u32
*context
,
2131 bool exclusive
, unsigned *context_size
)
2133 MCDI_DECLARE_BUF(inbuf
, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN
);
2134 MCDI_DECLARE_BUF(outbuf
, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN
);
2135 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2138 u32 alloc_type
= exclusive
?
2139 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE
:
2140 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED
;
2141 unsigned rss_spread
= exclusive
?
2143 min(rounddown_pow_of_two(efx
->rss_spread
),
2144 EFX_EF10_MAX_SHARED_RSS_CONTEXT_SIZE
);
2146 if (!exclusive
&& rss_spread
== 1) {
2147 *context
= EFX_EF10_RSS_CONTEXT_INVALID
;
2153 if (nic_data
->datapath_caps
&
2154 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_LBN
)
2157 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID
,
2158 nic_data
->vport_id
);
2159 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_TYPE
, alloc_type
);
2160 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES
, rss_spread
);
2162 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_ALLOC
, inbuf
, sizeof(inbuf
),
2163 outbuf
, sizeof(outbuf
), &outlen
);
2167 if (outlen
< MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN
)
2170 *context
= MCDI_DWORD(outbuf
, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID
);
2173 *context_size
= rss_spread
;
2178 static void efx_ef10_free_rss_context(struct efx_nic
*efx
, u32 context
)
2180 MCDI_DECLARE_BUF(inbuf
, MC_CMD_RSS_CONTEXT_FREE_IN_LEN
);
2183 MCDI_SET_DWORD(inbuf
, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID
,
2186 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_FREE
, inbuf
, sizeof(inbuf
),
2191 static int efx_ef10_populate_rss_table(struct efx_nic
*efx
, u32 context
,
2192 const u32
*rx_indir_table
)
2194 MCDI_DECLARE_BUF(tablebuf
, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN
);
2195 MCDI_DECLARE_BUF(keybuf
, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN
);
2198 MCDI_SET_DWORD(tablebuf
, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID
,
2200 BUILD_BUG_ON(ARRAY_SIZE(efx
->rx_indir_table
) !=
2201 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN
);
2203 for (i
= 0; i
< ARRAY_SIZE(efx
->rx_indir_table
); ++i
)
2205 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE
)[i
] =
2206 (u8
) rx_indir_table
[i
];
2208 rc
= efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_SET_TABLE
, tablebuf
,
2209 sizeof(tablebuf
), NULL
, 0, NULL
);
2213 MCDI_SET_DWORD(keybuf
, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID
,
2215 BUILD_BUG_ON(ARRAY_SIZE(efx
->rx_hash_key
) !=
2216 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN
);
2217 for (i
= 0; i
< ARRAY_SIZE(efx
->rx_hash_key
); ++i
)
2218 MCDI_PTR(keybuf
, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY
)[i
] =
2219 efx
->rx_hash_key
[i
];
2221 return efx_mcdi_rpc(efx
, MC_CMD_RSS_CONTEXT_SET_KEY
, keybuf
,
2222 sizeof(keybuf
), NULL
, 0, NULL
);
2225 static void efx_ef10_rx_free_indir_table(struct efx_nic
*efx
)
2227 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2229 if (nic_data
->rx_rss_context
!= EFX_EF10_RSS_CONTEXT_INVALID
)
2230 efx_ef10_free_rss_context(efx
, nic_data
->rx_rss_context
);
2231 nic_data
->rx_rss_context
= EFX_EF10_RSS_CONTEXT_INVALID
;
2234 static int efx_ef10_rx_push_shared_rss_config(struct efx_nic
*efx
,
2235 unsigned *context_size
)
2237 u32 new_rx_rss_context
;
2238 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2239 int rc
= efx_ef10_alloc_rss_context(efx
, &new_rx_rss_context
,
2240 false, context_size
);
2245 nic_data
->rx_rss_context
= new_rx_rss_context
;
2246 nic_data
->rx_rss_context_exclusive
= false;
2247 efx_set_default_rx_indir_table(efx
);
2251 static int efx_ef10_rx_push_exclusive_rss_config(struct efx_nic
*efx
,
2252 const u32
*rx_indir_table
)
2254 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2256 u32 new_rx_rss_context
;
2258 if (nic_data
->rx_rss_context
== EFX_EF10_RSS_CONTEXT_INVALID
||
2259 !nic_data
->rx_rss_context_exclusive
) {
2260 rc
= efx_ef10_alloc_rss_context(efx
, &new_rx_rss_context
,
2262 if (rc
== -EOPNOTSUPP
)
2267 new_rx_rss_context
= nic_data
->rx_rss_context
;
2270 rc
= efx_ef10_populate_rss_table(efx
, new_rx_rss_context
,
2275 if (nic_data
->rx_rss_context
!= new_rx_rss_context
)
2276 efx_ef10_rx_free_indir_table(efx
);
2277 nic_data
->rx_rss_context
= new_rx_rss_context
;
2278 nic_data
->rx_rss_context_exclusive
= true;
2279 if (rx_indir_table
!= efx
->rx_indir_table
)
2280 memcpy(efx
->rx_indir_table
, rx_indir_table
,
2281 sizeof(efx
->rx_indir_table
));
2285 if (new_rx_rss_context
!= nic_data
->rx_rss_context
)
2286 efx_ef10_free_rss_context(efx
, new_rx_rss_context
);
2288 netif_err(efx
, hw
, efx
->net_dev
, "%s: failed rc=%d\n", __func__
, rc
);
2292 static int efx_ef10_pf_rx_push_rss_config(struct efx_nic
*efx
, bool user
,
2293 const u32
*rx_indir_table
)
2297 if (efx
->rss_spread
== 1)
2300 rc
= efx_ef10_rx_push_exclusive_rss_config(efx
, rx_indir_table
);
2302 if (rc
== -ENOBUFS
&& !user
) {
2303 unsigned context_size
;
2304 bool mismatch
= false;
2307 for (i
= 0; i
< ARRAY_SIZE(efx
->rx_indir_table
) && !mismatch
;
2309 mismatch
= rx_indir_table
[i
] !=
2310 ethtool_rxfh_indir_default(i
, efx
->rss_spread
);
2312 rc
= efx_ef10_rx_push_shared_rss_config(efx
, &context_size
);
2314 if (context_size
!= efx
->rss_spread
)
2315 netif_warn(efx
, probe
, efx
->net_dev
,
2316 "Could not allocate an exclusive RSS"
2317 " context; allocated a shared one of"
2319 " Wanted %u, got %u.\n",
2320 efx
->rss_spread
, context_size
);
2322 netif_warn(efx
, probe
, efx
->net_dev
,
2323 "Could not allocate an exclusive RSS"
2324 " context; allocated a shared one but"
2325 " could not apply custom"
2328 netif_info(efx
, probe
, efx
->net_dev
,
2329 "Could not allocate an exclusive RSS"
2330 " context; allocated a shared one.\n");
2336 static int efx_ef10_vf_rx_push_rss_config(struct efx_nic
*efx
, bool user
,
2337 const u32
*rx_indir_table
2338 __attribute__ ((unused
)))
2340 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2344 if (nic_data
->rx_rss_context
!= EFX_EF10_RSS_CONTEXT_INVALID
)
2346 return efx_ef10_rx_push_shared_rss_config(efx
, NULL
);
2349 static int efx_ef10_rx_probe(struct efx_rx_queue
*rx_queue
)
2351 return efx_nic_alloc_buffer(rx_queue
->efx
, &rx_queue
->rxd
.buf
,
2352 (rx_queue
->ptr_mask
+ 1) *
2353 sizeof(efx_qword_t
),
2357 static void efx_ef10_rx_init(struct efx_rx_queue
*rx_queue
)
2359 MCDI_DECLARE_BUF(inbuf
,
2360 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE
* 8 /
2362 struct efx_channel
*channel
= efx_rx_queue_channel(rx_queue
);
2363 size_t entries
= rx_queue
->rxd
.buf
.len
/ EFX_BUF_SIZE
;
2364 struct efx_nic
*efx
= rx_queue
->efx
;
2365 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2367 dma_addr_t dma_addr
;
2370 BUILD_BUG_ON(MC_CMD_INIT_RXQ_OUT_LEN
!= 0);
2372 rx_queue
->scatter_n
= 0;
2373 rx_queue
->scatter_len
= 0;
2375 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_SIZE
, rx_queue
->ptr_mask
+ 1);
2376 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_TARGET_EVQ
, channel
->channel
);
2377 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_LABEL
, efx_rx_queue_index(rx_queue
));
2378 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_INSTANCE
,
2379 efx_rx_queue_index(rx_queue
));
2380 MCDI_POPULATE_DWORD_2(inbuf
, INIT_RXQ_IN_FLAGS
,
2381 INIT_RXQ_IN_FLAG_PREFIX
, 1,
2382 INIT_RXQ_IN_FLAG_TIMESTAMP
, 1);
2383 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_OWNER_ID
, 0);
2384 MCDI_SET_DWORD(inbuf
, INIT_RXQ_IN_PORT_ID
, nic_data
->vport_id
);
2386 dma_addr
= rx_queue
->rxd
.buf
.dma_addr
;
2388 netif_dbg(efx
, hw
, efx
->net_dev
, "pushing RXQ %d. %zu entries (%llx)\n",
2389 efx_rx_queue_index(rx_queue
), entries
, (u64
)dma_addr
);
2391 for (i
= 0; i
< entries
; ++i
) {
2392 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_RXQ_IN_DMA_ADDR
, i
, dma_addr
);
2393 dma_addr
+= EFX_BUF_SIZE
;
2396 inlen
= MC_CMD_INIT_RXQ_IN_LEN(entries
);
2398 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_RXQ
, inbuf
, inlen
,
2401 netdev_WARN(efx
->net_dev
, "failed to initialise RXQ %d\n",
2402 efx_rx_queue_index(rx_queue
));
2405 static void efx_ef10_rx_fini(struct efx_rx_queue
*rx_queue
)
2407 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_RXQ_IN_LEN
);
2408 MCDI_DECLARE_BUF_ERR(outbuf
);
2409 struct efx_nic
*efx
= rx_queue
->efx
;
2413 MCDI_SET_DWORD(inbuf
, FINI_RXQ_IN_INSTANCE
,
2414 efx_rx_queue_index(rx_queue
));
2416 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_RXQ
, inbuf
, sizeof(inbuf
),
2417 outbuf
, sizeof(outbuf
), &outlen
);
2419 if (rc
&& rc
!= -EALREADY
)
2425 efx_mcdi_display_error(efx
, MC_CMD_FINI_RXQ
, MC_CMD_FINI_RXQ_IN_LEN
,
2426 outbuf
, outlen
, rc
);
2429 static void efx_ef10_rx_remove(struct efx_rx_queue
*rx_queue
)
2431 efx_nic_free_buffer(rx_queue
->efx
, &rx_queue
->rxd
.buf
);
2434 /* This creates an entry in the RX descriptor queue */
2436 efx_ef10_build_rx_desc(struct efx_rx_queue
*rx_queue
, unsigned int index
)
2438 struct efx_rx_buffer
*rx_buf
;
2441 rxd
= efx_rx_desc(rx_queue
, index
);
2442 rx_buf
= efx_rx_buffer(rx_queue
, index
);
2443 EFX_POPULATE_QWORD_2(*rxd
,
2444 ESF_DZ_RX_KER_BYTE_CNT
, rx_buf
->len
,
2445 ESF_DZ_RX_KER_BUF_ADDR
, rx_buf
->dma_addr
);
2448 static void efx_ef10_rx_write(struct efx_rx_queue
*rx_queue
)
2450 struct efx_nic
*efx
= rx_queue
->efx
;
2451 unsigned int write_count
;
2454 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */
2455 write_count
= rx_queue
->added_count
& ~7;
2456 if (rx_queue
->notified_count
== write_count
)
2460 efx_ef10_build_rx_desc(
2462 rx_queue
->notified_count
& rx_queue
->ptr_mask
);
2463 while (++rx_queue
->notified_count
!= write_count
);
2466 EFX_POPULATE_DWORD_1(reg
, ERF_DZ_RX_DESC_WPTR
,
2467 write_count
& rx_queue
->ptr_mask
);
2468 efx_writed_page(efx
, ®
, ER_DZ_RX_DESC_UPD
,
2469 efx_rx_queue_index(rx_queue
));
2472 static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete
;
2474 static void efx_ef10_rx_defer_refill(struct efx_rx_queue
*rx_queue
)
2476 struct efx_channel
*channel
= efx_rx_queue_channel(rx_queue
);
2477 MCDI_DECLARE_BUF(inbuf
, MC_CMD_DRIVER_EVENT_IN_LEN
);
2480 EFX_POPULATE_QWORD_2(event
,
2481 ESF_DZ_EV_CODE
, EFX_EF10_DRVGEN_EV
,
2482 ESF_DZ_EV_DATA
, EFX_EF10_REFILL
);
2484 MCDI_SET_DWORD(inbuf
, DRIVER_EVENT_IN_EVQ
, channel
->channel
);
2486 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
2487 * already swapped the data to little-endian order.
2489 memcpy(MCDI_PTR(inbuf
, DRIVER_EVENT_IN_DATA
), &event
.u64
[0],
2490 sizeof(efx_qword_t
));
2492 efx_mcdi_rpc_async(channel
->efx
, MC_CMD_DRIVER_EVENT
,
2493 inbuf
, sizeof(inbuf
), 0,
2494 efx_ef10_rx_defer_refill_complete
, 0);
2498 efx_ef10_rx_defer_refill_complete(struct efx_nic
*efx
, unsigned long cookie
,
2499 int rc
, efx_dword_t
*outbuf
,
2500 size_t outlen_actual
)
2505 static int efx_ef10_ev_probe(struct efx_channel
*channel
)
2507 return efx_nic_alloc_buffer(channel
->efx
, &channel
->eventq
.buf
,
2508 (channel
->eventq_mask
+ 1) *
2509 sizeof(efx_qword_t
),
2513 static void efx_ef10_ev_fini(struct efx_channel
*channel
)
2515 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FINI_EVQ_IN_LEN
);
2516 MCDI_DECLARE_BUF_ERR(outbuf
);
2517 struct efx_nic
*efx
= channel
->efx
;
2521 MCDI_SET_DWORD(inbuf
, FINI_EVQ_IN_INSTANCE
, channel
->channel
);
2523 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FINI_EVQ
, inbuf
, sizeof(inbuf
),
2524 outbuf
, sizeof(outbuf
), &outlen
);
2526 if (rc
&& rc
!= -EALREADY
)
2532 efx_mcdi_display_error(efx
, MC_CMD_FINI_EVQ
, MC_CMD_FINI_EVQ_IN_LEN
,
2533 outbuf
, outlen
, rc
);
2536 static int efx_ef10_ev_init(struct efx_channel
*channel
)
2538 MCDI_DECLARE_BUF(inbuf
,
2539 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE
* 8 /
2541 MCDI_DECLARE_BUF(outbuf
, MC_CMD_INIT_EVQ_OUT_LEN
);
2542 size_t entries
= channel
->eventq
.buf
.len
/ EFX_BUF_SIZE
;
2543 struct efx_nic
*efx
= channel
->efx
;
2544 struct efx_ef10_nic_data
*nic_data
;
2545 bool supports_rx_merge
;
2546 size_t inlen
, outlen
;
2547 unsigned int enabled
, implemented
;
2548 dma_addr_t dma_addr
;
2552 nic_data
= efx
->nic_data
;
2554 !!(nic_data
->datapath_caps
&
2555 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN
);
2557 /* Fill event queue with all ones (i.e. empty events) */
2558 memset(channel
->eventq
.buf
.addr
, 0xff, channel
->eventq
.buf
.len
);
2560 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_SIZE
, channel
->eventq_mask
+ 1);
2561 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_INSTANCE
, channel
->channel
);
2562 /* INIT_EVQ expects index in vector table, not absolute */
2563 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_IRQ_NUM
, channel
->channel
);
2564 MCDI_POPULATE_DWORD_4(inbuf
, INIT_EVQ_IN_FLAGS
,
2565 INIT_EVQ_IN_FLAG_INTERRUPTING
, 1,
2566 INIT_EVQ_IN_FLAG_RX_MERGE
, 1,
2567 INIT_EVQ_IN_FLAG_TX_MERGE
, 1,
2568 INIT_EVQ_IN_FLAG_CUT_THRU
, !supports_rx_merge
);
2569 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_MODE
,
2570 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS
);
2571 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_LOAD
, 0);
2572 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_TMR_RELOAD
, 0);
2573 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_COUNT_MODE
,
2574 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS
);
2575 MCDI_SET_DWORD(inbuf
, INIT_EVQ_IN_COUNT_THRSHLD
, 0);
2577 dma_addr
= channel
->eventq
.buf
.dma_addr
;
2578 for (i
= 0; i
< entries
; ++i
) {
2579 MCDI_SET_ARRAY_QWORD(inbuf
, INIT_EVQ_IN_DMA_ADDR
, i
, dma_addr
);
2580 dma_addr
+= EFX_BUF_SIZE
;
2583 inlen
= MC_CMD_INIT_EVQ_IN_LEN(entries
);
2585 rc
= efx_mcdi_rpc(efx
, MC_CMD_INIT_EVQ
, inbuf
, inlen
,
2586 outbuf
, sizeof(outbuf
), &outlen
);
2587 /* IRQ return is ignored */
2588 if (channel
->channel
|| rc
)
2591 /* Successfully created event queue on channel 0 */
2592 rc
= efx_mcdi_get_workarounds(efx
, &implemented
, &enabled
);
2593 if (rc
== -ENOSYS
) {
2594 /* GET_WORKAROUNDS was implemented before the bug26807
2595 * workaround, thus the latter must be unavailable in this fw
2597 nic_data
->workaround_26807
= false;
2602 nic_data
->workaround_26807
=
2603 !!(enabled
& MC_CMD_GET_WORKAROUNDS_OUT_BUG26807
);
2605 if (implemented
& MC_CMD_GET_WORKAROUNDS_OUT_BUG26807
&&
2606 !nic_data
->workaround_26807
) {
2609 rc
= efx_mcdi_set_workaround(efx
,
2610 MC_CMD_WORKAROUND_BUG26807
,
2615 1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN
) {
2616 netif_info(efx
, drv
, efx
->net_dev
,
2617 "other functions on NIC have been reset\n");
2619 /* With MCFW v4.6.x and earlier, the
2620 * boot count will have incremented,
2621 * so re-read the warm_boot_count
2622 * value now to ensure this function
2623 * doesn't think it has changed next
2626 rc
= efx_ef10_get_warm_boot_count(efx
);
2628 nic_data
->warm_boot_count
= rc
;
2632 nic_data
->workaround_26807
= true;
2633 } else if (rc
== -EPERM
) {
2643 efx_ef10_ev_fini(channel
);
2647 static void efx_ef10_ev_remove(struct efx_channel
*channel
)
2649 efx_nic_free_buffer(channel
->efx
, &channel
->eventq
.buf
);
2652 static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue
*rx_queue
,
2653 unsigned int rx_queue_label
)
2655 struct efx_nic
*efx
= rx_queue
->efx
;
2657 netif_info(efx
, hw
, efx
->net_dev
,
2658 "rx event arrived on queue %d labeled as queue %u\n",
2659 efx_rx_queue_index(rx_queue
), rx_queue_label
);
2661 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
2665 efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue
*rx_queue
,
2666 unsigned int actual
, unsigned int expected
)
2668 unsigned int dropped
= (actual
- expected
) & rx_queue
->ptr_mask
;
2669 struct efx_nic
*efx
= rx_queue
->efx
;
2671 netif_info(efx
, hw
, efx
->net_dev
,
2672 "dropped %d events (index=%d expected=%d)\n",
2673 dropped
, actual
, expected
);
2675 efx_schedule_reset(efx
, RESET_TYPE_DISABLE
);
2678 /* partially received RX was aborted. clean up. */
2679 static void efx_ef10_handle_rx_abort(struct efx_rx_queue
*rx_queue
)
2681 unsigned int rx_desc_ptr
;
2683 netif_dbg(rx_queue
->efx
, hw
, rx_queue
->efx
->net_dev
,
2684 "scattered RX aborted (dropping %u buffers)\n",
2685 rx_queue
->scatter_n
);
2687 rx_desc_ptr
= rx_queue
->removed_count
& rx_queue
->ptr_mask
;
2689 efx_rx_packet(rx_queue
, rx_desc_ptr
, rx_queue
->scatter_n
,
2690 0, EFX_RX_PKT_DISCARD
);
2692 rx_queue
->removed_count
+= rx_queue
->scatter_n
;
2693 rx_queue
->scatter_n
= 0;
2694 rx_queue
->scatter_len
= 0;
2695 ++efx_rx_queue_channel(rx_queue
)->n_rx_nodesc_trunc
;
2698 static int efx_ef10_handle_rx_event(struct efx_channel
*channel
,
2699 const efx_qword_t
*event
)
2701 unsigned int rx_bytes
, next_ptr_lbits
, rx_queue_label
, rx_l4_class
;
2702 unsigned int n_descs
, n_packets
, i
;
2703 struct efx_nic
*efx
= channel
->efx
;
2704 struct efx_rx_queue
*rx_queue
;
2708 if (unlikely(ACCESS_ONCE(efx
->reset_pending
)))
2711 /* Basic packet information */
2712 rx_bytes
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_BYTES
);
2713 next_ptr_lbits
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_DSC_PTR_LBITS
);
2714 rx_queue_label
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_QLABEL
);
2715 rx_l4_class
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_L4_CLASS
);
2716 rx_cont
= EFX_QWORD_FIELD(*event
, ESF_DZ_RX_CONT
);
2718 if (EFX_QWORD_FIELD(*event
, ESF_DZ_RX_DROP_EVENT
))
2719 netdev_WARN(efx
->net_dev
, "saw RX_DROP_EVENT: event="
2721 EFX_QWORD_VAL(*event
));
2723 rx_queue
= efx_channel_get_rx_queue(channel
);
2725 if (unlikely(rx_queue_label
!= efx_rx_queue_index(rx_queue
)))
2726 efx_ef10_handle_rx_wrong_queue(rx_queue
, rx_queue_label
);
2728 n_descs
= ((next_ptr_lbits
- rx_queue
->removed_count
) &
2729 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH
) - 1));
2731 if (n_descs
!= rx_queue
->scatter_n
+ 1) {
2732 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
2734 /* detect rx abort */
2735 if (unlikely(n_descs
== rx_queue
->scatter_n
)) {
2736 if (rx_queue
->scatter_n
== 0 || rx_bytes
!= 0)
2737 netdev_WARN(efx
->net_dev
,
2738 "invalid RX abort: scatter_n=%u event="
2740 rx_queue
->scatter_n
,
2741 EFX_QWORD_VAL(*event
));
2742 efx_ef10_handle_rx_abort(rx_queue
);
2746 /* Check that RX completion merging is valid, i.e.
2747 * the current firmware supports it and this is a
2748 * non-scattered packet.
2750 if (!(nic_data
->datapath_caps
&
2751 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN
)) ||
2752 rx_queue
->scatter_n
!= 0 || rx_cont
) {
2753 efx_ef10_handle_rx_bad_lbits(
2754 rx_queue
, next_ptr_lbits
,
2755 (rx_queue
->removed_count
+
2756 rx_queue
->scatter_n
+ 1) &
2757 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH
) - 1));
2761 /* Merged completion for multiple non-scattered packets */
2762 rx_queue
->scatter_n
= 1;
2763 rx_queue
->scatter_len
= 0;
2764 n_packets
= n_descs
;
2765 ++channel
->n_rx_merge_events
;
2766 channel
->n_rx_merge_packets
+= n_packets
;
2767 flags
|= EFX_RX_PKT_PREFIX_LEN
;
2769 ++rx_queue
->scatter_n
;
2770 rx_queue
->scatter_len
+= rx_bytes
;
2776 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_RX_ECRC_ERR
)))
2777 flags
|= EFX_RX_PKT_DISCARD
;
2779 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_RX_IPCKSUM_ERR
))) {
2780 channel
->n_rx_ip_hdr_chksum_err
+= n_packets
;
2781 } else if (unlikely(EFX_QWORD_FIELD(*event
,
2782 ESF_DZ_RX_TCPUDP_CKSUM_ERR
))) {
2783 channel
->n_rx_tcp_udp_chksum_err
+= n_packets
;
2784 } else if (rx_l4_class
== ESE_DZ_L4_CLASS_TCP
||
2785 rx_l4_class
== ESE_DZ_L4_CLASS_UDP
) {
2786 flags
|= EFX_RX_PKT_CSUMMED
;
2789 if (rx_l4_class
== ESE_DZ_L4_CLASS_TCP
)
2790 flags
|= EFX_RX_PKT_TCP
;
2792 channel
->irq_mod_score
+= 2 * n_packets
;
2794 /* Handle received packet(s) */
2795 for (i
= 0; i
< n_packets
; i
++) {
2796 efx_rx_packet(rx_queue
,
2797 rx_queue
->removed_count
& rx_queue
->ptr_mask
,
2798 rx_queue
->scatter_n
, rx_queue
->scatter_len
,
2800 rx_queue
->removed_count
+= rx_queue
->scatter_n
;
2803 rx_queue
->scatter_n
= 0;
2804 rx_queue
->scatter_len
= 0;
2810 efx_ef10_handle_tx_event(struct efx_channel
*channel
, efx_qword_t
*event
)
2812 struct efx_nic
*efx
= channel
->efx
;
2813 struct efx_tx_queue
*tx_queue
;
2814 unsigned int tx_ev_desc_ptr
;
2815 unsigned int tx_ev_q_label
;
2818 if (unlikely(ACCESS_ONCE(efx
->reset_pending
)))
2821 if (unlikely(EFX_QWORD_FIELD(*event
, ESF_DZ_TX_DROP_EVENT
)))
2824 /* Transmit completion */
2825 tx_ev_desc_ptr
= EFX_QWORD_FIELD(*event
, ESF_DZ_TX_DESCR_INDX
);
2826 tx_ev_q_label
= EFX_QWORD_FIELD(*event
, ESF_DZ_TX_QLABEL
);
2827 tx_queue
= efx_channel_get_tx_queue(channel
,
2828 tx_ev_q_label
% EFX_TXQ_TYPES
);
2829 tx_descs
= ((tx_ev_desc_ptr
+ 1 - tx_queue
->read_count
) &
2830 tx_queue
->ptr_mask
);
2831 efx_xmit_done(tx_queue
, tx_ev_desc_ptr
& tx_queue
->ptr_mask
);
2837 efx_ef10_handle_driver_event(struct efx_channel
*channel
, efx_qword_t
*event
)
2839 struct efx_nic
*efx
= channel
->efx
;
2842 subcode
= EFX_QWORD_FIELD(*event
, ESF_DZ_DRV_SUB_CODE
);
2845 case ESE_DZ_DRV_TIMER_EV
:
2846 case ESE_DZ_DRV_WAKE_UP_EV
:
2848 case ESE_DZ_DRV_START_UP_EV
:
2849 /* event queue init complete. ok. */
2852 netif_err(efx
, hw
, efx
->net_dev
,
2853 "channel %d unknown driver event type %d"
2854 " (data " EFX_QWORD_FMT
")\n",
2855 channel
->channel
, subcode
,
2856 EFX_QWORD_VAL(*event
));
2861 static void efx_ef10_handle_driver_generated_event(struct efx_channel
*channel
,
2864 struct efx_nic
*efx
= channel
->efx
;
2867 subcode
= EFX_QWORD_FIELD(*event
, EFX_DWORD_0
);
2871 channel
->event_test_cpu
= raw_smp_processor_id();
2873 case EFX_EF10_REFILL
:
2874 /* The queue must be empty, so we won't receive any rx
2875 * events, so efx_process_channel() won't refill the
2876 * queue. Refill it here
2878 efx_fast_push_rx_descriptors(&channel
->rx_queue
, true);
2881 netif_err(efx
, hw
, efx
->net_dev
,
2882 "channel %d unknown driver event type %u"
2883 " (data " EFX_QWORD_FMT
")\n",
2884 channel
->channel
, (unsigned) subcode
,
2885 EFX_QWORD_VAL(*event
));
2889 static int efx_ef10_ev_process(struct efx_channel
*channel
, int quota
)
2891 struct efx_nic
*efx
= channel
->efx
;
2892 efx_qword_t event
, *p_event
;
2893 unsigned int read_ptr
;
2901 read_ptr
= channel
->eventq_read_ptr
;
2904 p_event
= efx_event(channel
, read_ptr
);
2907 if (!efx_event_present(&event
))
2910 EFX_SET_QWORD(*p_event
);
2914 ev_code
= EFX_QWORD_FIELD(event
, ESF_DZ_EV_CODE
);
2916 netif_vdbg(efx
, drv
, efx
->net_dev
,
2917 "processing event on %d " EFX_QWORD_FMT
"\n",
2918 channel
->channel
, EFX_QWORD_VAL(event
));
2921 case ESE_DZ_EV_CODE_MCDI_EV
:
2922 efx_mcdi_process_event(channel
, &event
);
2924 case ESE_DZ_EV_CODE_RX_EV
:
2925 spent
+= efx_ef10_handle_rx_event(channel
, &event
);
2926 if (spent
>= quota
) {
2927 /* XXX can we split a merged event to
2928 * avoid going over-quota?
2934 case ESE_DZ_EV_CODE_TX_EV
:
2935 tx_descs
+= efx_ef10_handle_tx_event(channel
, &event
);
2936 if (tx_descs
> efx
->txq_entries
) {
2939 } else if (++spent
== quota
) {
2943 case ESE_DZ_EV_CODE_DRIVER_EV
:
2944 efx_ef10_handle_driver_event(channel
, &event
);
2945 if (++spent
== quota
)
2948 case EFX_EF10_DRVGEN_EV
:
2949 efx_ef10_handle_driver_generated_event(channel
, &event
);
2952 netif_err(efx
, hw
, efx
->net_dev
,
2953 "channel %d unknown event type %d"
2954 " (data " EFX_QWORD_FMT
")\n",
2955 channel
->channel
, ev_code
,
2956 EFX_QWORD_VAL(event
));
2961 channel
->eventq_read_ptr
= read_ptr
;
2965 static void efx_ef10_ev_read_ack(struct efx_channel
*channel
)
2967 struct efx_nic
*efx
= channel
->efx
;
2970 if (EFX_EF10_WORKAROUND_35388(efx
)) {
2971 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE
<
2972 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH
));
2973 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE
>
2974 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH
));
2976 EFX_POPULATE_DWORD_2(rptr
, ERF_DD_EVQ_IND_RPTR_FLAGS
,
2977 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH
,
2978 ERF_DD_EVQ_IND_RPTR
,
2979 (channel
->eventq_read_ptr
&
2980 channel
->eventq_mask
) >>
2981 ERF_DD_EVQ_IND_RPTR_WIDTH
);
2982 efx_writed_page(efx
, &rptr
, ER_DD_EVQ_INDIRECT
,
2984 EFX_POPULATE_DWORD_2(rptr
, ERF_DD_EVQ_IND_RPTR_FLAGS
,
2985 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW
,
2986 ERF_DD_EVQ_IND_RPTR
,
2987 channel
->eventq_read_ptr
&
2988 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH
) - 1));
2989 efx_writed_page(efx
, &rptr
, ER_DD_EVQ_INDIRECT
,
2992 EFX_POPULATE_DWORD_1(rptr
, ERF_DZ_EVQ_RPTR
,
2993 channel
->eventq_read_ptr
&
2994 channel
->eventq_mask
);
2995 efx_writed_page(efx
, &rptr
, ER_DZ_EVQ_RPTR
, channel
->channel
);
2999 static void efx_ef10_ev_test_generate(struct efx_channel
*channel
)
3001 MCDI_DECLARE_BUF(inbuf
, MC_CMD_DRIVER_EVENT_IN_LEN
);
3002 struct efx_nic
*efx
= channel
->efx
;
3006 EFX_POPULATE_QWORD_2(event
,
3007 ESF_DZ_EV_CODE
, EFX_EF10_DRVGEN_EV
,
3008 ESF_DZ_EV_DATA
, EFX_EF10_TEST
);
3010 MCDI_SET_DWORD(inbuf
, DRIVER_EVENT_IN_EVQ
, channel
->channel
);
3012 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has
3013 * already swapped the data to little-endian order.
3015 memcpy(MCDI_PTR(inbuf
, DRIVER_EVENT_IN_DATA
), &event
.u64
[0],
3016 sizeof(efx_qword_t
));
3018 rc
= efx_mcdi_rpc(efx
, MC_CMD_DRIVER_EVENT
, inbuf
, sizeof(inbuf
),
3027 netif_err(efx
, hw
, efx
->net_dev
, "%s: failed rc=%d\n", __func__
, rc
);
3030 void efx_ef10_handle_drain_event(struct efx_nic
*efx
)
3032 if (atomic_dec_and_test(&efx
->active_queues
))
3033 wake_up(&efx
->flush_wq
);
3035 WARN_ON(atomic_read(&efx
->active_queues
) < 0);
3038 static int efx_ef10_fini_dmaq(struct efx_nic
*efx
)
3040 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
3041 struct efx_channel
*channel
;
3042 struct efx_tx_queue
*tx_queue
;
3043 struct efx_rx_queue
*rx_queue
;
3046 /* If the MC has just rebooted, the TX/RX queues will have already been
3047 * torn down, but efx->active_queues needs to be set to zero.
3049 if (nic_data
->must_realloc_vis
) {
3050 atomic_set(&efx
->active_queues
, 0);
3054 /* Do not attempt to write to the NIC during EEH recovery */
3055 if (efx
->state
!= STATE_RECOVERY
) {
3056 efx_for_each_channel(channel
, efx
) {
3057 efx_for_each_channel_rx_queue(rx_queue
, channel
)
3058 efx_ef10_rx_fini(rx_queue
);
3059 efx_for_each_channel_tx_queue(tx_queue
, channel
)
3060 efx_ef10_tx_fini(tx_queue
);
3063 wait_event_timeout(efx
->flush_wq
,
3064 atomic_read(&efx
->active_queues
) == 0,
3065 msecs_to_jiffies(EFX_MAX_FLUSH_TIME
));
3066 pending
= atomic_read(&efx
->active_queues
);
3068 netif_err(efx
, hw
, efx
->net_dev
, "failed to flush %d queues\n",
3077 static void efx_ef10_prepare_flr(struct efx_nic
*efx
)
3079 atomic_set(&efx
->active_queues
, 0);
3082 static bool efx_ef10_filter_equal(const struct efx_filter_spec
*left
,
3083 const struct efx_filter_spec
*right
)
3085 if ((left
->match_flags
^ right
->match_flags
) |
3086 ((left
->flags
^ right
->flags
) &
3087 (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_TX
)))
3090 return memcmp(&left
->outer_vid
, &right
->outer_vid
,
3091 sizeof(struct efx_filter_spec
) -
3092 offsetof(struct efx_filter_spec
, outer_vid
)) == 0;
3095 static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec
*spec
)
3097 BUILD_BUG_ON(offsetof(struct efx_filter_spec
, outer_vid
) & 3);
3098 return jhash2((const u32
*)&spec
->outer_vid
,
3099 (sizeof(struct efx_filter_spec
) -
3100 offsetof(struct efx_filter_spec
, outer_vid
)) / 4,
3102 /* XXX should we randomise the initval? */
3105 /* Decide whether a filter should be exclusive or else should allow
3106 * delivery to additional recipients. Currently we decide that
3107 * filters for specific local unicast MAC and IP addresses are
3110 static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec
*spec
)
3112 if (spec
->match_flags
& EFX_FILTER_MATCH_LOC_MAC
&&
3113 !is_multicast_ether_addr(spec
->loc_mac
))
3116 if ((spec
->match_flags
&
3117 (EFX_FILTER_MATCH_ETHER_TYPE
| EFX_FILTER_MATCH_LOC_HOST
)) ==
3118 (EFX_FILTER_MATCH_ETHER_TYPE
| EFX_FILTER_MATCH_LOC_HOST
)) {
3119 if (spec
->ether_type
== htons(ETH_P_IP
) &&
3120 !ipv4_is_multicast(spec
->loc_host
[0]))
3122 if (spec
->ether_type
== htons(ETH_P_IPV6
) &&
3123 ((const u8
*)spec
->loc_host
)[0] != 0xff)
3130 static struct efx_filter_spec
*
3131 efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table
*table
,
3132 unsigned int filter_idx
)
3134 return (struct efx_filter_spec
*)(table
->entry
[filter_idx
].spec
&
3135 ~EFX_EF10_FILTER_FLAGS
);
3139 efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table
*table
,
3140 unsigned int filter_idx
)
3142 return table
->entry
[filter_idx
].spec
& EFX_EF10_FILTER_FLAGS
;
3146 efx_ef10_filter_set_entry(struct efx_ef10_filter_table
*table
,
3147 unsigned int filter_idx
,
3148 const struct efx_filter_spec
*spec
,
3151 table
->entry
[filter_idx
].spec
= (unsigned long)spec
| flags
;
3154 static void efx_ef10_filter_push_prep(struct efx_nic
*efx
,
3155 const struct efx_filter_spec
*spec
,
3156 efx_dword_t
*inbuf
, u64 handle
,
3159 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
3160 u32 flags
= spec
->flags
;
3162 memset(inbuf
, 0, MC_CMD_FILTER_OP_IN_LEN
);
3164 /* Remove RSS flag if we don't have an RSS context. */
3165 if (flags
& EFX_FILTER_FLAG_RX_RSS
&&
3166 spec
->rss_context
== EFX_FILTER_RSS_CONTEXT_DEFAULT
&&
3167 nic_data
->rx_rss_context
== EFX_EF10_RSS_CONTEXT_INVALID
)
3168 flags
&= ~EFX_FILTER_FLAG_RX_RSS
;
3171 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3172 MC_CMD_FILTER_OP_IN_OP_REPLACE
);
3173 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
, handle
);
3175 u32 match_fields
= 0;
3177 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3178 efx_ef10_filter_is_exclusive(spec
) ?
3179 MC_CMD_FILTER_OP_IN_OP_INSERT
:
3180 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE
);
3182 /* Convert match flags and values. Unlike almost
3183 * everything else in MCDI, these fields are in
3184 * network byte order.
3186 if (spec
->match_flags
& EFX_FILTER_MATCH_LOC_MAC_IG
)
3188 is_multicast_ether_addr(spec
->loc_mac
) ?
3189 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN
:
3190 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN
;
3191 #define COPY_FIELD(gen_flag, gen_field, mcdi_field) \
3192 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \
3194 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3195 mcdi_field ## _LBN; \
3197 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \
3198 sizeof(spec->gen_field)); \
3199 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \
3200 &spec->gen_field, sizeof(spec->gen_field)); \
3202 COPY_FIELD(REM_HOST
, rem_host
, SRC_IP
);
3203 COPY_FIELD(LOC_HOST
, loc_host
, DST_IP
);
3204 COPY_FIELD(REM_MAC
, rem_mac
, SRC_MAC
);
3205 COPY_FIELD(REM_PORT
, rem_port
, SRC_PORT
);
3206 COPY_FIELD(LOC_MAC
, loc_mac
, DST_MAC
);
3207 COPY_FIELD(LOC_PORT
, loc_port
, DST_PORT
);
3208 COPY_FIELD(ETHER_TYPE
, ether_type
, ETHER_TYPE
);
3209 COPY_FIELD(INNER_VID
, inner_vid
, INNER_VLAN
);
3210 COPY_FIELD(OUTER_VID
, outer_vid
, OUTER_VLAN
);
3211 COPY_FIELD(IP_PROTO
, ip_proto
, IP_PROTO
);
3213 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_MATCH_FIELDS
,
3217 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_PORT_ID
, nic_data
->vport_id
);
3218 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_DEST
,
3219 spec
->dmaq_id
== EFX_FILTER_RX_DMAQ_ID_DROP
?
3220 MC_CMD_FILTER_OP_IN_RX_DEST_DROP
:
3221 MC_CMD_FILTER_OP_IN_RX_DEST_HOST
);
3222 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_TX_DOMAIN
, 0);
3223 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_TX_DEST
,
3224 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT
);
3225 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_QUEUE
,
3226 spec
->dmaq_id
== EFX_FILTER_RX_DMAQ_ID_DROP
?
3228 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_MODE
,
3229 (flags
& EFX_FILTER_FLAG_RX_RSS
) ?
3230 MC_CMD_FILTER_OP_IN_RX_MODE_RSS
:
3231 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE
);
3232 if (flags
& EFX_FILTER_FLAG_RX_RSS
)
3233 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_RX_CONTEXT
,
3234 spec
->rss_context
!=
3235 EFX_FILTER_RSS_CONTEXT_DEFAULT
?
3236 spec
->rss_context
: nic_data
->rx_rss_context
);
3239 static int efx_ef10_filter_push(struct efx_nic
*efx
,
3240 const struct efx_filter_spec
*spec
,
3241 u64
*handle
, bool replacing
)
3243 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
3244 MCDI_DECLARE_BUF(outbuf
, MC_CMD_FILTER_OP_OUT_LEN
);
3247 efx_ef10_filter_push_prep(efx
, spec
, inbuf
, *handle
, replacing
);
3248 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
),
3249 outbuf
, sizeof(outbuf
), NULL
);
3251 *handle
= MCDI_QWORD(outbuf
, FILTER_OP_OUT_HANDLE
);
3253 rc
= -EBUSY
; /* to match efx_farch_filter_insert() */
3257 static u32
efx_ef10_filter_mcdi_flags_from_spec(const struct efx_filter_spec
*spec
)
3259 unsigned int match_flags
= spec
->match_flags
;
3262 if (match_flags
& EFX_FILTER_MATCH_LOC_MAC_IG
) {
3263 match_flags
&= ~EFX_FILTER_MATCH_LOC_MAC_IG
;
3265 is_multicast_ether_addr(spec
->loc_mac
) ?
3266 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN
) :
3267 (1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN
);
3270 #define MAP_FILTER_TO_MCDI_FLAG(gen_flag, mcdi_field) { \
3271 unsigned int old_match_flags = match_flags; \
3272 match_flags &= ~EFX_FILTER_MATCH_ ## gen_flag; \
3273 if (match_flags != old_match_flags) \
3275 (1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3276 mcdi_field ## _LBN); \
3278 MAP_FILTER_TO_MCDI_FLAG(REM_HOST
, SRC_IP
);
3279 MAP_FILTER_TO_MCDI_FLAG(LOC_HOST
, DST_IP
);
3280 MAP_FILTER_TO_MCDI_FLAG(REM_MAC
, SRC_MAC
);
3281 MAP_FILTER_TO_MCDI_FLAG(REM_PORT
, SRC_PORT
);
3282 MAP_FILTER_TO_MCDI_FLAG(LOC_MAC
, DST_MAC
);
3283 MAP_FILTER_TO_MCDI_FLAG(LOC_PORT
, DST_PORT
);
3284 MAP_FILTER_TO_MCDI_FLAG(ETHER_TYPE
, ETHER_TYPE
);
3285 MAP_FILTER_TO_MCDI_FLAG(INNER_VID
, INNER_VLAN
);
3286 MAP_FILTER_TO_MCDI_FLAG(OUTER_VID
, OUTER_VLAN
);
3287 MAP_FILTER_TO_MCDI_FLAG(IP_PROTO
, IP_PROTO
);
3288 #undef MAP_FILTER_TO_MCDI_FLAG
3290 /* Did we map them all? */
3291 WARN_ON_ONCE(match_flags
);
3296 static int efx_ef10_filter_pri(struct efx_ef10_filter_table
*table
,
3297 const struct efx_filter_spec
*spec
)
3299 u32 mcdi_flags
= efx_ef10_filter_mcdi_flags_from_spec(spec
);
3300 unsigned int match_pri
;
3303 match_pri
< table
->rx_match_count
;
3305 if (table
->rx_match_mcdi_flags
[match_pri
] == mcdi_flags
)
3308 return -EPROTONOSUPPORT
;
3311 static s32
efx_ef10_filter_insert(struct efx_nic
*efx
,
3312 struct efx_filter_spec
*spec
,
3315 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3316 DECLARE_BITMAP(mc_rem_map
, EFX_EF10_FILTER_SEARCH_LIMIT
);
3317 struct efx_filter_spec
*saved_spec
;
3318 unsigned int match_pri
, hash
;
3319 unsigned int priv_flags
;
3320 bool replacing
= false;
3326 /* For now, only support RX filters */
3327 if ((spec
->flags
& (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_TX
)) !=
3331 rc
= efx_ef10_filter_pri(table
, spec
);
3336 hash
= efx_ef10_filter_hash(spec
);
3337 is_mc_recip
= efx_filter_is_mc_recipient(spec
);
3339 bitmap_zero(mc_rem_map
, EFX_EF10_FILTER_SEARCH_LIMIT
);
3341 /* Find any existing filters with the same match tuple or
3342 * else a free slot to insert at. If any of them are busy,
3343 * we have to wait and retry.
3346 unsigned int depth
= 1;
3349 spin_lock_bh(&efx
->filter_lock
);
3352 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3353 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
3358 } else if (efx_ef10_filter_equal(spec
, saved_spec
)) {
3359 if (table
->entry
[i
].spec
&
3360 EFX_EF10_FILTER_FLAG_BUSY
)
3362 if (spec
->priority
< saved_spec
->priority
&&
3363 spec
->priority
!= EFX_FILTER_PRI_AUTO
) {
3368 /* This is the only one */
3369 if (spec
->priority
==
3370 saved_spec
->priority
&&
3377 } else if (spec
->priority
>
3378 saved_spec
->priority
||
3380 saved_spec
->priority
&&
3385 __set_bit(depth
, mc_rem_map
);
3389 /* Once we reach the maximum search depth, use
3390 * the first suitable slot or return -EBUSY if
3393 if (depth
== EFX_EF10_FILTER_SEARCH_LIMIT
) {
3394 if (ins_index
< 0) {
3404 prepare_to_wait(&table
->waitq
, &wait
, TASK_UNINTERRUPTIBLE
);
3405 spin_unlock_bh(&efx
->filter_lock
);
3410 /* Create a software table entry if necessary, and mark it
3411 * busy. We might yet fail to insert, but any attempt to
3412 * insert a conflicting filter while we're waiting for the
3413 * firmware must find the busy entry.
3415 saved_spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
3417 if (spec
->priority
== EFX_FILTER_PRI_AUTO
&&
3418 saved_spec
->priority
>= EFX_FILTER_PRI_AUTO
) {
3419 /* Just make sure it won't be removed */
3420 if (saved_spec
->priority
> EFX_FILTER_PRI_AUTO
)
3421 saved_spec
->flags
|= EFX_FILTER_FLAG_RX_OVER_AUTO
;
3422 table
->entry
[ins_index
].spec
&=
3423 ~EFX_EF10_FILTER_FLAG_AUTO_OLD
;
3428 priv_flags
= efx_ef10_filter_entry_flags(table
, ins_index
);
3430 saved_spec
= kmalloc(sizeof(*spec
), GFP_ATOMIC
);
3435 *saved_spec
= *spec
;
3438 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
,
3439 priv_flags
| EFX_EF10_FILTER_FLAG_BUSY
);
3441 /* Mark lower-priority multicast recipients busy prior to removal */
3443 unsigned int depth
, i
;
3445 for (depth
= 0; depth
< EFX_EF10_FILTER_SEARCH_LIMIT
; depth
++) {
3446 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3447 if (test_bit(depth
, mc_rem_map
))
3448 table
->entry
[i
].spec
|=
3449 EFX_EF10_FILTER_FLAG_BUSY
;
3453 spin_unlock_bh(&efx
->filter_lock
);
3455 rc
= efx_ef10_filter_push(efx
, spec
, &table
->entry
[ins_index
].handle
,
3458 /* Finalise the software table entry */
3459 spin_lock_bh(&efx
->filter_lock
);
3462 /* Update the fields that may differ */
3463 if (saved_spec
->priority
== EFX_FILTER_PRI_AUTO
)
3464 saved_spec
->flags
|=
3465 EFX_FILTER_FLAG_RX_OVER_AUTO
;
3466 saved_spec
->priority
= spec
->priority
;
3467 saved_spec
->flags
&= EFX_FILTER_FLAG_RX_OVER_AUTO
;
3468 saved_spec
->flags
|= spec
->flags
;
3469 saved_spec
->rss_context
= spec
->rss_context
;
3470 saved_spec
->dmaq_id
= spec
->dmaq_id
;
3472 } else if (!replacing
) {
3476 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
, priv_flags
);
3478 /* Remove and finalise entries for lower-priority multicast
3482 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
3483 unsigned int depth
, i
;
3485 memset(inbuf
, 0, sizeof(inbuf
));
3487 for (depth
= 0; depth
< EFX_EF10_FILTER_SEARCH_LIMIT
; depth
++) {
3488 if (!test_bit(depth
, mc_rem_map
))
3491 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3492 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
3493 priv_flags
= efx_ef10_filter_entry_flags(table
, i
);
3496 spin_unlock_bh(&efx
->filter_lock
);
3497 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3498 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
3499 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
3500 table
->entry
[i
].handle
);
3501 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
,
3502 inbuf
, sizeof(inbuf
),
3504 spin_lock_bh(&efx
->filter_lock
);
3512 priv_flags
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
3514 efx_ef10_filter_set_entry(table
, i
, saved_spec
,
3519 /* If successful, return the inserted filter ID */
3521 rc
= match_pri
* HUNT_FILTER_TBL_ROWS
+ ins_index
;
3523 wake_up_all(&table
->waitq
);
3525 spin_unlock_bh(&efx
->filter_lock
);
3526 finish_wait(&table
->waitq
, &wait
);
3530 static void efx_ef10_filter_update_rx_scatter(struct efx_nic
*efx
)
3532 /* no need to do anything here on EF10 */
3536 * If !by_index, remove by ID
3537 * If by_index, remove by index
3538 * Filter ID may come from userland and must be range-checked.
3540 static int efx_ef10_filter_remove_internal(struct efx_nic
*efx
,
3541 unsigned int priority_mask
,
3542 u32 filter_id
, bool by_index
)
3544 unsigned int filter_idx
= filter_id
% HUNT_FILTER_TBL_ROWS
;
3545 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3546 MCDI_DECLARE_BUF(inbuf
,
3547 MC_CMD_FILTER_OP_IN_HANDLE_OFST
+
3548 MC_CMD_FILTER_OP_IN_HANDLE_LEN
);
3549 struct efx_filter_spec
*spec
;
3553 /* Find the software table entry and mark it busy. Don't
3554 * remove it yet; any attempt to update while we're waiting
3555 * for the firmware must find the busy entry.
3558 spin_lock_bh(&efx
->filter_lock
);
3559 if (!(table
->entry
[filter_idx
].spec
&
3560 EFX_EF10_FILTER_FLAG_BUSY
))
3562 prepare_to_wait(&table
->waitq
, &wait
, TASK_UNINTERRUPTIBLE
);
3563 spin_unlock_bh(&efx
->filter_lock
);
3567 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3570 efx_ef10_filter_pri(table
, spec
) !=
3571 filter_id
/ HUNT_FILTER_TBL_ROWS
)) {
3576 if (spec
->flags
& EFX_FILTER_FLAG_RX_OVER_AUTO
&&
3577 priority_mask
== (1U << EFX_FILTER_PRI_AUTO
)) {
3578 /* Just remove flags */
3579 spec
->flags
&= ~EFX_FILTER_FLAG_RX_OVER_AUTO
;
3580 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_AUTO_OLD
;
3585 if (!(priority_mask
& (1U << spec
->priority
))) {
3590 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
3591 spin_unlock_bh(&efx
->filter_lock
);
3593 if (spec
->flags
& EFX_FILTER_FLAG_RX_OVER_AUTO
) {
3594 /* Reset to an automatic filter */
3596 struct efx_filter_spec new_spec
= *spec
;
3598 new_spec
.priority
= EFX_FILTER_PRI_AUTO
;
3599 new_spec
.flags
= (EFX_FILTER_FLAG_RX
|
3600 (efx_rss_enabled(efx
) ?
3601 EFX_FILTER_FLAG_RX_RSS
: 0));
3602 new_spec
.dmaq_id
= 0;
3603 new_spec
.rss_context
= EFX_FILTER_RSS_CONTEXT_DEFAULT
;
3604 rc
= efx_ef10_filter_push(efx
, &new_spec
,
3605 &table
->entry
[filter_idx
].handle
,
3608 spin_lock_bh(&efx
->filter_lock
);
3612 /* Really remove the filter */
3614 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3615 efx_ef10_filter_is_exclusive(spec
) ?
3616 MC_CMD_FILTER_OP_IN_OP_REMOVE
:
3617 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
3618 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
3619 table
->entry
[filter_idx
].handle
);
3620 rc
= efx_mcdi_rpc(efx
, MC_CMD_FILTER_OP
,
3621 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
3623 spin_lock_bh(&efx
->filter_lock
);
3626 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
3630 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
3631 wake_up_all(&table
->waitq
);
3633 spin_unlock_bh(&efx
->filter_lock
);
3634 finish_wait(&table
->waitq
, &wait
);
3638 static int efx_ef10_filter_remove_safe(struct efx_nic
*efx
,
3639 enum efx_filter_priority priority
,
3642 return efx_ef10_filter_remove_internal(efx
, 1U << priority
,
3646 static u32
efx_ef10_filter_get_unsafe_id(struct efx_nic
*efx
, u32 filter_id
)
3648 return filter_id
% HUNT_FILTER_TBL_ROWS
;
3651 static void efx_ef10_filter_remove_unsafe(struct efx_nic
*efx
,
3652 enum efx_filter_priority priority
,
3655 if (filter_id
== EFX_EF10_FILTER_ID_INVALID
)
3657 efx_ef10_filter_remove_internal(efx
, 1U << priority
, filter_id
, true);
3660 static int efx_ef10_filter_get_safe(struct efx_nic
*efx
,
3661 enum efx_filter_priority priority
,
3662 u32 filter_id
, struct efx_filter_spec
*spec
)
3664 unsigned int filter_idx
= filter_id
% HUNT_FILTER_TBL_ROWS
;
3665 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3666 const struct efx_filter_spec
*saved_spec
;
3669 spin_lock_bh(&efx
->filter_lock
);
3670 saved_spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3671 if (saved_spec
&& saved_spec
->priority
== priority
&&
3672 efx_ef10_filter_pri(table
, saved_spec
) ==
3673 filter_id
/ HUNT_FILTER_TBL_ROWS
) {
3674 *spec
= *saved_spec
;
3679 spin_unlock_bh(&efx
->filter_lock
);
3683 static int efx_ef10_filter_clear_rx(struct efx_nic
*efx
,
3684 enum efx_filter_priority priority
)
3686 unsigned int priority_mask
;
3690 priority_mask
= (((1U << (priority
+ 1)) - 1) &
3691 ~(1U << EFX_FILTER_PRI_AUTO
));
3693 for (i
= 0; i
< HUNT_FILTER_TBL_ROWS
; i
++) {
3694 rc
= efx_ef10_filter_remove_internal(efx
, priority_mask
,
3696 if (rc
&& rc
!= -ENOENT
)
3703 static u32
efx_ef10_filter_count_rx_used(struct efx_nic
*efx
,
3704 enum efx_filter_priority priority
)
3706 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3707 unsigned int filter_idx
;
3710 spin_lock_bh(&efx
->filter_lock
);
3711 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
3712 if (table
->entry
[filter_idx
].spec
&&
3713 efx_ef10_filter_entry_spec(table
, filter_idx
)->priority
==
3717 spin_unlock_bh(&efx
->filter_lock
);
3721 static u32
efx_ef10_filter_get_rx_id_limit(struct efx_nic
*efx
)
3723 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3725 return table
->rx_match_count
* HUNT_FILTER_TBL_ROWS
;
3728 static s32
efx_ef10_filter_get_rx_ids(struct efx_nic
*efx
,
3729 enum efx_filter_priority priority
,
3732 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3733 struct efx_filter_spec
*spec
;
3734 unsigned int filter_idx
;
3737 spin_lock_bh(&efx
->filter_lock
);
3738 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
3739 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
3740 if (spec
&& spec
->priority
== priority
) {
3741 if (count
== size
) {
3745 buf
[count
++] = (efx_ef10_filter_pri(table
, spec
) *
3746 HUNT_FILTER_TBL_ROWS
+
3750 spin_unlock_bh(&efx
->filter_lock
);
3754 #ifdef CONFIG_RFS_ACCEL
3756 static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete
;
3758 static s32
efx_ef10_filter_rfs_insert(struct efx_nic
*efx
,
3759 struct efx_filter_spec
*spec
)
3761 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3762 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
3763 struct efx_filter_spec
*saved_spec
;
3764 unsigned int hash
, i
, depth
= 1;
3765 bool replacing
= false;
3770 /* Must be an RX filter without RSS and not for a multicast
3771 * destination address (RFS only works for connected sockets).
3772 * These restrictions allow us to pass only a tiny amount of
3773 * data through to the completion function.
3775 EFX_WARN_ON_PARANOID(spec
->flags
!=
3776 (EFX_FILTER_FLAG_RX
| EFX_FILTER_FLAG_RX_SCATTER
));
3777 EFX_WARN_ON_PARANOID(spec
->priority
!= EFX_FILTER_PRI_HINT
);
3778 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec
));
3780 hash
= efx_ef10_filter_hash(spec
);
3782 spin_lock_bh(&efx
->filter_lock
);
3784 /* Find any existing filter with the same match tuple or else
3785 * a free slot to insert at. If an existing filter is busy,
3786 * we have to give up.
3789 i
= (hash
+ depth
) & (HUNT_FILTER_TBL_ROWS
- 1);
3790 saved_spec
= efx_ef10_filter_entry_spec(table
, i
);
3795 } else if (efx_ef10_filter_equal(spec
, saved_spec
)) {
3796 if (table
->entry
[i
].spec
& EFX_EF10_FILTER_FLAG_BUSY
) {
3800 if (spec
->priority
< saved_spec
->priority
) {
3808 /* Once we reach the maximum search depth, use the
3809 * first suitable slot or return -EBUSY if there was
3812 if (depth
== EFX_EF10_FILTER_SEARCH_LIMIT
) {
3813 if (ins_index
< 0) {
3823 /* Create a software table entry if necessary, and mark it
3824 * busy. We might yet fail to insert, but any attempt to
3825 * insert a conflicting filter while we're waiting for the
3826 * firmware must find the busy entry.
3828 saved_spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
3832 saved_spec
= kmalloc(sizeof(*spec
), GFP_ATOMIC
);
3837 *saved_spec
= *spec
;
3839 efx_ef10_filter_set_entry(table
, ins_index
, saved_spec
,
3840 EFX_EF10_FILTER_FLAG_BUSY
);
3842 spin_unlock_bh(&efx
->filter_lock
);
3844 /* Pack up the variables needed on completion */
3845 cookie
= replacing
<< 31 | ins_index
<< 16 | spec
->dmaq_id
;
3847 efx_ef10_filter_push_prep(efx
, spec
, inbuf
,
3848 table
->entry
[ins_index
].handle
, replacing
);
3849 efx_mcdi_rpc_async(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
),
3850 MC_CMD_FILTER_OP_OUT_LEN
,
3851 efx_ef10_filter_rfs_insert_complete
, cookie
);
3856 spin_unlock_bh(&efx
->filter_lock
);
3861 efx_ef10_filter_rfs_insert_complete(struct efx_nic
*efx
, unsigned long cookie
,
3862 int rc
, efx_dword_t
*outbuf
,
3863 size_t outlen_actual
)
3865 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3866 unsigned int ins_index
, dmaq_id
;
3867 struct efx_filter_spec
*spec
;
3870 /* Unpack the cookie */
3871 replacing
= cookie
>> 31;
3872 ins_index
= (cookie
>> 16) & (HUNT_FILTER_TBL_ROWS
- 1);
3873 dmaq_id
= cookie
& 0xffff;
3875 spin_lock_bh(&efx
->filter_lock
);
3876 spec
= efx_ef10_filter_entry_spec(table
, ins_index
);
3878 table
->entry
[ins_index
].handle
=
3879 MCDI_QWORD(outbuf
, FILTER_OP_OUT_HANDLE
);
3881 spec
->dmaq_id
= dmaq_id
;
3882 } else if (!replacing
) {
3886 efx_ef10_filter_set_entry(table
, ins_index
, spec
, 0);
3887 spin_unlock_bh(&efx
->filter_lock
);
3889 wake_up_all(&table
->waitq
);
3893 efx_ef10_filter_rfs_expire_complete(struct efx_nic
*efx
,
3894 unsigned long filter_idx
,
3895 int rc
, efx_dword_t
*outbuf
,
3896 size_t outlen_actual
);
3898 static bool efx_ef10_filter_rfs_expire_one(struct efx_nic
*efx
, u32 flow_id
,
3899 unsigned int filter_idx
)
3901 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3902 struct efx_filter_spec
*spec
=
3903 efx_ef10_filter_entry_spec(table
, filter_idx
);
3904 MCDI_DECLARE_BUF(inbuf
,
3905 MC_CMD_FILTER_OP_IN_HANDLE_OFST
+
3906 MC_CMD_FILTER_OP_IN_HANDLE_LEN
);
3909 (table
->entry
[filter_idx
].spec
& EFX_EF10_FILTER_FLAG_BUSY
) ||
3910 spec
->priority
!= EFX_FILTER_PRI_HINT
||
3911 !rps_may_expire_flow(efx
->net_dev
, spec
->dmaq_id
,
3912 flow_id
, filter_idx
))
3915 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
3916 MC_CMD_FILTER_OP_IN_OP_REMOVE
);
3917 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
3918 table
->entry
[filter_idx
].handle
);
3919 if (efx_mcdi_rpc_async(efx
, MC_CMD_FILTER_OP
, inbuf
, sizeof(inbuf
), 0,
3920 efx_ef10_filter_rfs_expire_complete
, filter_idx
))
3923 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
3928 efx_ef10_filter_rfs_expire_complete(struct efx_nic
*efx
,
3929 unsigned long filter_idx
,
3930 int rc
, efx_dword_t
*outbuf
,
3931 size_t outlen_actual
)
3933 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3934 struct efx_filter_spec
*spec
=
3935 efx_ef10_filter_entry_spec(table
, filter_idx
);
3937 spin_lock_bh(&efx
->filter_lock
);
3940 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
3942 table
->entry
[filter_idx
].spec
&= ~EFX_EF10_FILTER_FLAG_BUSY
;
3943 wake_up_all(&table
->waitq
);
3944 spin_unlock_bh(&efx
->filter_lock
);
3947 #endif /* CONFIG_RFS_ACCEL */
3949 static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags
)
3951 int match_flags
= 0;
3953 #define MAP_FLAG(gen_flag, mcdi_field) { \
3954 u32 old_mcdi_flags = mcdi_flags; \
3955 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \
3956 mcdi_field ## _LBN); \
3957 if (mcdi_flags != old_mcdi_flags) \
3958 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \
3960 MAP_FLAG(LOC_MAC_IG
, UNKNOWN_UCAST_DST
);
3961 MAP_FLAG(LOC_MAC_IG
, UNKNOWN_MCAST_DST
);
3962 MAP_FLAG(REM_HOST
, SRC_IP
);
3963 MAP_FLAG(LOC_HOST
, DST_IP
);
3964 MAP_FLAG(REM_MAC
, SRC_MAC
);
3965 MAP_FLAG(REM_PORT
, SRC_PORT
);
3966 MAP_FLAG(LOC_MAC
, DST_MAC
);
3967 MAP_FLAG(LOC_PORT
, DST_PORT
);
3968 MAP_FLAG(ETHER_TYPE
, ETHER_TYPE
);
3969 MAP_FLAG(INNER_VID
, INNER_VLAN
);
3970 MAP_FLAG(OUTER_VID
, OUTER_VLAN
);
3971 MAP_FLAG(IP_PROTO
, IP_PROTO
);
3974 /* Did we map them all? */
3981 static void efx_ef10_filter_cleanup_vlans(struct efx_nic
*efx
)
3983 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
3984 struct efx_ef10_filter_vlan
*vlan
, *next_vlan
;
3986 /* See comment in efx_ef10_filter_table_remove() */
3987 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
3993 list_for_each_entry_safe(vlan
, next_vlan
, &table
->vlan_list
, list
)
3994 efx_ef10_filter_del_vlan_internal(efx
, vlan
);
3997 static bool efx_ef10_filter_match_supported(struct efx_ef10_filter_table
*table
,
3998 enum efx_filter_match_flags match_flags
)
4000 unsigned int match_pri
;
4004 match_pri
< table
->rx_match_count
;
4006 mf
= efx_ef10_filter_match_flags_from_mcdi(
4007 table
->rx_match_mcdi_flags
[match_pri
]);
4008 if (mf
== match_flags
)
4015 static int efx_ef10_filter_table_probe(struct efx_nic
*efx
)
4017 MCDI_DECLARE_BUF(inbuf
, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN
);
4018 MCDI_DECLARE_BUF(outbuf
, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX
);
4019 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4020 struct net_device
*net_dev
= efx
->net_dev
;
4021 unsigned int pd_match_pri
, pd_match_count
;
4022 struct efx_ef10_filter_table
*table
;
4023 struct efx_ef10_vlan
*vlan
;
4027 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4030 if (efx
->filter_state
) /* already probed */
4033 table
= kzalloc(sizeof(*table
), GFP_KERNEL
);
4037 /* Find out which RX filter types are supported, and their priorities */
4038 MCDI_SET_DWORD(inbuf
, GET_PARSER_DISP_INFO_IN_OP
,
4039 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES
);
4040 rc
= efx_mcdi_rpc(efx
, MC_CMD_GET_PARSER_DISP_INFO
,
4041 inbuf
, sizeof(inbuf
), outbuf
, sizeof(outbuf
),
4045 pd_match_count
= MCDI_VAR_ARRAY_LEN(
4046 outlen
, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES
);
4047 table
->rx_match_count
= 0;
4049 for (pd_match_pri
= 0; pd_match_pri
< pd_match_count
; pd_match_pri
++) {
4053 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES
,
4055 rc
= efx_ef10_filter_match_flags_from_mcdi(mcdi_flags
);
4057 netif_dbg(efx
, probe
, efx
->net_dev
,
4058 "%s: fw flags %#x pri %u not supported in driver\n",
4059 __func__
, mcdi_flags
, pd_match_pri
);
4061 netif_dbg(efx
, probe
, efx
->net_dev
,
4062 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n",
4063 __func__
, mcdi_flags
, pd_match_pri
,
4064 rc
, table
->rx_match_count
);
4065 table
->rx_match_mcdi_flags
[table
->rx_match_count
] = mcdi_flags
;
4066 table
->rx_match_count
++;
4070 if ((efx_supported_features(efx
) & NETIF_F_HW_VLAN_CTAG_FILTER
) &&
4071 !(efx_ef10_filter_match_supported(table
,
4072 (EFX_FILTER_MATCH_OUTER_VID
| EFX_FILTER_MATCH_LOC_MAC
)) &&
4073 efx_ef10_filter_match_supported(table
,
4074 (EFX_FILTER_MATCH_OUTER_VID
| EFX_FILTER_MATCH_LOC_MAC_IG
)))) {
4075 netif_info(efx
, probe
, net_dev
,
4076 "VLAN filters are not supported in this firmware variant\n");
4077 net_dev
->features
&= ~NETIF_F_HW_VLAN_CTAG_FILTER
;
4078 efx
->fixed_features
&= ~NETIF_F_HW_VLAN_CTAG_FILTER
;
4079 net_dev
->hw_features
&= ~NETIF_F_HW_VLAN_CTAG_FILTER
;
4082 table
->entry
= vzalloc(HUNT_FILTER_TBL_ROWS
* sizeof(*table
->entry
));
4083 if (!table
->entry
) {
4088 table
->mc_promisc_last
= false;
4089 table
->vlan_filter
=
4090 !!(efx
->net_dev
->features
& NETIF_F_HW_VLAN_CTAG_FILTER
);
4091 INIT_LIST_HEAD(&table
->vlan_list
);
4093 efx
->filter_state
= table
;
4094 init_waitqueue_head(&table
->waitq
);
4096 list_for_each_entry(vlan
, &nic_data
->vlan_list
, list
) {
4097 rc
= efx_ef10_filter_add_vlan(efx
, vlan
->vid
);
4105 efx_ef10_filter_cleanup_vlans(efx
);
4106 efx
->filter_state
= NULL
;
4112 /* Caller must hold efx->filter_sem for read if race against
4113 * efx_ef10_filter_table_remove() is possible
4115 static void efx_ef10_filter_table_restore(struct efx_nic
*efx
)
4117 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4118 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4119 struct efx_filter_spec
*spec
;
4120 unsigned int filter_idx
;
4121 bool failed
= false;
4124 WARN_ON(!rwsem_is_locked(&efx
->filter_sem
));
4126 if (!nic_data
->must_restore_filters
)
4132 spin_lock_bh(&efx
->filter_lock
);
4134 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
4135 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
4139 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_BUSY
;
4140 spin_unlock_bh(&efx
->filter_lock
);
4142 rc
= efx_ef10_filter_push(efx
, spec
,
4143 &table
->entry
[filter_idx
].handle
,
4148 spin_lock_bh(&efx
->filter_lock
);
4151 efx_ef10_filter_set_entry(table
, filter_idx
, NULL
, 0);
4153 table
->entry
[filter_idx
].spec
&=
4154 ~EFX_EF10_FILTER_FLAG_BUSY
;
4158 spin_unlock_bh(&efx
->filter_lock
);
4161 netif_err(efx
, hw
, efx
->net_dev
,
4162 "unable to restore all filters\n");
4164 nic_data
->must_restore_filters
= false;
4167 static void efx_ef10_filter_table_remove(struct efx_nic
*efx
)
4169 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4170 MCDI_DECLARE_BUF(inbuf
, MC_CMD_FILTER_OP_IN_LEN
);
4171 struct efx_filter_spec
*spec
;
4172 unsigned int filter_idx
;
4175 efx_ef10_filter_cleanup_vlans(efx
);
4176 efx
->filter_state
= NULL
;
4177 /* If we were called without locking, then it's not safe to free
4178 * the table as others might be using it. So we just WARN, leak
4179 * the memory, and potentially get an inconsistent filter table
4181 * This should never actually happen.
4183 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4189 for (filter_idx
= 0; filter_idx
< HUNT_FILTER_TBL_ROWS
; filter_idx
++) {
4190 spec
= efx_ef10_filter_entry_spec(table
, filter_idx
);
4194 MCDI_SET_DWORD(inbuf
, FILTER_OP_IN_OP
,
4195 efx_ef10_filter_is_exclusive(spec
) ?
4196 MC_CMD_FILTER_OP_IN_OP_REMOVE
:
4197 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE
);
4198 MCDI_SET_QWORD(inbuf
, FILTER_OP_IN_HANDLE
,
4199 table
->entry
[filter_idx
].handle
);
4200 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_FILTER_OP
, inbuf
,
4201 sizeof(inbuf
), NULL
, 0, NULL
);
4203 netif_info(efx
, drv
, efx
->net_dev
,
4204 "%s: filter %04x remove failed\n",
4205 __func__
, filter_idx
);
4209 vfree(table
->entry
);
4213 static void efx_ef10_filter_mark_one_old(struct efx_nic
*efx
, uint16_t *id
)
4215 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4216 unsigned int filter_idx
;
4218 if (*id
!= EFX_EF10_FILTER_ID_INVALID
) {
4219 filter_idx
= efx_ef10_filter_get_unsafe_id(efx
, *id
);
4220 if (!table
->entry
[filter_idx
].spec
)
4221 netif_dbg(efx
, drv
, efx
->net_dev
,
4222 "marked null spec old %04x:%04x\n", *id
,
4224 table
->entry
[filter_idx
].spec
|= EFX_EF10_FILTER_FLAG_AUTO_OLD
;
4225 *id
= EFX_EF10_FILTER_ID_INVALID
;
4229 /* Mark old per-VLAN filters that may need to be removed */
4230 static void _efx_ef10_filter_vlan_mark_old(struct efx_nic
*efx
,
4231 struct efx_ef10_filter_vlan
*vlan
)
4233 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4236 for (i
= 0; i
< table
->dev_uc_count
; i
++)
4237 efx_ef10_filter_mark_one_old(efx
, &vlan
->uc
[i
]);
4238 for (i
= 0; i
< table
->dev_mc_count
; i
++)
4239 efx_ef10_filter_mark_one_old(efx
, &vlan
->mc
[i
]);
4240 efx_ef10_filter_mark_one_old(efx
, &vlan
->ucdef
);
4241 efx_ef10_filter_mark_one_old(efx
, &vlan
->bcast
);
4242 efx_ef10_filter_mark_one_old(efx
, &vlan
->mcdef
);
4245 /* Mark old filters that may need to be removed.
4246 * Caller must hold efx->filter_sem for read if race against
4247 * efx_ef10_filter_table_remove() is possible
4249 static void efx_ef10_filter_mark_old(struct efx_nic
*efx
)
4251 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4252 struct efx_ef10_filter_vlan
*vlan
;
4254 spin_lock_bh(&efx
->filter_lock
);
4255 list_for_each_entry(vlan
, &table
->vlan_list
, list
)
4256 _efx_ef10_filter_vlan_mark_old(efx
, vlan
);
4257 spin_unlock_bh(&efx
->filter_lock
);
4260 static void efx_ef10_filter_uc_addr_list(struct efx_nic
*efx
)
4262 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4263 struct net_device
*net_dev
= efx
->net_dev
;
4264 struct netdev_hw_addr
*uc
;
4268 addr_count
= netdev_uc_count(net_dev
);
4269 table
->uc_promisc
= !!(net_dev
->flags
& IFF_PROMISC
);
4270 table
->dev_uc_count
= 1 + addr_count
;
4271 ether_addr_copy(table
->dev_uc_list
[0].addr
, net_dev
->dev_addr
);
4273 netdev_for_each_uc_addr(uc
, net_dev
) {
4274 if (i
>= EFX_EF10_FILTER_DEV_UC_MAX
) {
4275 table
->uc_promisc
= true;
4278 ether_addr_copy(table
->dev_uc_list
[i
].addr
, uc
->addr
);
4283 static void efx_ef10_filter_mc_addr_list(struct efx_nic
*efx
)
4285 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4286 struct net_device
*net_dev
= efx
->net_dev
;
4287 struct netdev_hw_addr
*mc
;
4288 unsigned int i
, addr_count
;
4290 table
->mc_promisc
= !!(net_dev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
));
4292 addr_count
= netdev_mc_count(net_dev
);
4294 netdev_for_each_mc_addr(mc
, net_dev
) {
4295 if (i
>= EFX_EF10_FILTER_DEV_MC_MAX
) {
4296 table
->mc_promisc
= true;
4299 ether_addr_copy(table
->dev_mc_list
[i
].addr
, mc
->addr
);
4303 table
->dev_mc_count
= i
;
4306 static int efx_ef10_filter_insert_addr_list(struct efx_nic
*efx
,
4307 struct efx_ef10_filter_vlan
*vlan
,
4308 bool multicast
, bool rollback
)
4310 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4311 struct efx_ef10_dev_addr
*addr_list
;
4312 enum efx_filter_flags filter_flags
;
4313 struct efx_filter_spec spec
;
4321 addr_list
= table
->dev_mc_list
;
4322 addr_count
= table
->dev_mc_count
;
4325 addr_list
= table
->dev_uc_list
;
4326 addr_count
= table
->dev_uc_count
;
4330 filter_flags
= efx_rss_enabled(efx
) ? EFX_FILTER_FLAG_RX_RSS
: 0;
4332 /* Insert/renew filters */
4333 for (i
= 0; i
< addr_count
; i
++) {
4334 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
, filter_flags
, 0);
4335 efx_filter_set_eth_local(&spec
, vlan
->vid
, addr_list
[i
].addr
);
4336 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
4339 netif_info(efx
, drv
, efx
->net_dev
,
4340 "efx_ef10_filter_insert failed rc=%d\n",
4342 /* Fall back to promiscuous */
4343 for (j
= 0; j
< i
; j
++) {
4344 efx_ef10_filter_remove_unsafe(
4345 efx
, EFX_FILTER_PRI_AUTO
,
4347 ids
[j
] = EFX_EF10_FILTER_ID_INVALID
;
4351 /* mark as not inserted, and carry on */
4352 rc
= EFX_EF10_FILTER_ID_INVALID
;
4355 ids
[i
] = efx_ef10_filter_get_unsafe_id(efx
, rc
);
4358 if (multicast
&& rollback
) {
4359 /* Also need an Ethernet broadcast filter */
4360 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
, filter_flags
, 0);
4361 eth_broadcast_addr(baddr
);
4362 efx_filter_set_eth_local(&spec
, vlan
->vid
, baddr
);
4363 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
4365 netif_warn(efx
, drv
, efx
->net_dev
,
4366 "Broadcast filter insert failed rc=%d\n", rc
);
4367 /* Fall back to promiscuous */
4368 for (j
= 0; j
< i
; j
++) {
4369 efx_ef10_filter_remove_unsafe(
4370 efx
, EFX_FILTER_PRI_AUTO
,
4372 ids
[j
] = EFX_EF10_FILTER_ID_INVALID
;
4376 EFX_WARN_ON_PARANOID(vlan
->bcast
!=
4377 EFX_EF10_FILTER_ID_INVALID
);
4378 vlan
->bcast
= efx_ef10_filter_get_unsafe_id(efx
, rc
);
4385 static int efx_ef10_filter_insert_def(struct efx_nic
*efx
,
4386 struct efx_ef10_filter_vlan
*vlan
,
4387 bool multicast
, bool rollback
)
4389 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4390 enum efx_filter_flags filter_flags
;
4391 struct efx_filter_spec spec
;
4395 filter_flags
= efx_rss_enabled(efx
) ? EFX_FILTER_FLAG_RX_RSS
: 0;
4397 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
, filter_flags
, 0);
4400 efx_filter_set_mc_def(&spec
);
4402 efx_filter_set_uc_def(&spec
);
4404 if (vlan
->vid
!= EFX_FILTER_VID_UNSPEC
)
4405 efx_filter_set_eth_local(&spec
, vlan
->vid
, NULL
);
4407 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
4409 netif_printk(efx
, drv
, rc
== -EPERM
? KERN_DEBUG
: KERN_WARNING
,
4411 "%scast mismatch filter insert failed rc=%d\n",
4412 multicast
? "Multi" : "Uni", rc
);
4413 } else if (multicast
) {
4414 EFX_WARN_ON_PARANOID(vlan
->mcdef
!= EFX_EF10_FILTER_ID_INVALID
);
4415 vlan
->mcdef
= efx_ef10_filter_get_unsafe_id(efx
, rc
);
4416 if (!nic_data
->workaround_26807
) {
4417 /* Also need an Ethernet broadcast filter */
4418 efx_filter_init_rx(&spec
, EFX_FILTER_PRI_AUTO
,
4420 eth_broadcast_addr(baddr
);
4421 efx_filter_set_eth_local(&spec
, vlan
->vid
, baddr
);
4422 rc
= efx_ef10_filter_insert(efx
, &spec
, true);
4424 netif_warn(efx
, drv
, efx
->net_dev
,
4425 "Broadcast filter insert failed rc=%d\n",
4428 /* Roll back the mc_def filter */
4429 efx_ef10_filter_remove_unsafe(
4430 efx
, EFX_FILTER_PRI_AUTO
,
4432 vlan
->mcdef
= EFX_EF10_FILTER_ID_INVALID
;
4436 EFX_WARN_ON_PARANOID(vlan
->bcast
!=
4437 EFX_EF10_FILTER_ID_INVALID
);
4438 vlan
->bcast
= efx_ef10_filter_get_unsafe_id(efx
, rc
);
4443 EFX_WARN_ON_PARANOID(vlan
->ucdef
!= EFX_EF10_FILTER_ID_INVALID
);
4450 /* Remove filters that weren't renewed. Since nothing else changes the AUTO_OLD
4451 * flag or removes these filters, we don't need to hold the filter_lock while
4452 * scanning for these filters.
4454 static void efx_ef10_filter_remove_old(struct efx_nic
*efx
)
4456 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4457 int remove_failed
= 0;
4458 int remove_noent
= 0;
4462 for (i
= 0; i
< HUNT_FILTER_TBL_ROWS
; i
++) {
4463 if (ACCESS_ONCE(table
->entry
[i
].spec
) &
4464 EFX_EF10_FILTER_FLAG_AUTO_OLD
) {
4465 rc
= efx_ef10_filter_remove_internal(efx
,
4466 1U << EFX_FILTER_PRI_AUTO
, i
, true);
4475 netif_info(efx
, drv
, efx
->net_dev
,
4476 "%s: failed to remove %d filters\n",
4477 __func__
, remove_failed
);
4479 netif_info(efx
, drv
, efx
->net_dev
,
4480 "%s: failed to remove %d non-existent filters\n",
4481 __func__
, remove_noent
);
4484 static int efx_ef10_vport_set_mac_address(struct efx_nic
*efx
)
4486 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4487 u8 mac_old
[ETH_ALEN
];
4490 /* Only reconfigure a PF-created vport */
4491 if (is_zero_ether_addr(nic_data
->vport_mac
))
4494 efx_device_detach_sync(efx
);
4495 efx_net_stop(efx
->net_dev
);
4496 down_write(&efx
->filter_sem
);
4497 efx_ef10_filter_table_remove(efx
);
4498 up_write(&efx
->filter_sem
);
4500 rc
= efx_ef10_vadaptor_free(efx
, nic_data
->vport_id
);
4502 goto restore_filters
;
4504 ether_addr_copy(mac_old
, nic_data
->vport_mac
);
4505 rc
= efx_ef10_vport_del_mac(efx
, nic_data
->vport_id
,
4506 nic_data
->vport_mac
);
4508 goto restore_vadaptor
;
4510 rc
= efx_ef10_vport_add_mac(efx
, nic_data
->vport_id
,
4511 efx
->net_dev
->dev_addr
);
4513 ether_addr_copy(nic_data
->vport_mac
, efx
->net_dev
->dev_addr
);
4515 rc2
= efx_ef10_vport_add_mac(efx
, nic_data
->vport_id
, mac_old
);
4517 /* Failed to add original MAC, so clear vport_mac */
4518 eth_zero_addr(nic_data
->vport_mac
);
4524 rc2
= efx_ef10_vadaptor_alloc(efx
, nic_data
->vport_id
);
4528 down_write(&efx
->filter_sem
);
4529 rc2
= efx_ef10_filter_table_probe(efx
);
4530 up_write(&efx
->filter_sem
);
4534 rc2
= efx_net_open(efx
->net_dev
);
4538 netif_device_attach(efx
->net_dev
);
4543 netif_err(efx
, drv
, efx
->net_dev
,
4544 "Failed to restore when changing MAC address - scheduling reset\n");
4545 efx_schedule_reset(efx
, RESET_TYPE_DATAPATH
);
4547 return rc
? rc
: rc2
;
4550 /* Caller must hold efx->filter_sem for read if race against
4551 * efx_ef10_filter_table_remove() is possible
4553 static void efx_ef10_filter_vlan_sync_rx_mode(struct efx_nic
*efx
,
4554 struct efx_ef10_filter_vlan
*vlan
)
4556 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4557 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4559 /* Do not install unspecified VID if VLAN filtering is enabled.
4560 * Do not install all specified VIDs if VLAN filtering is disabled.
4562 if ((vlan
->vid
== EFX_FILTER_VID_UNSPEC
) == table
->vlan_filter
)
4565 /* Insert/renew unicast filters */
4566 if (table
->uc_promisc
) {
4567 efx_ef10_filter_insert_def(efx
, vlan
, false, false);
4568 efx_ef10_filter_insert_addr_list(efx
, vlan
, false, false);
4570 /* If any of the filters failed to insert, fall back to
4571 * promiscuous mode - add in the uc_def filter. But keep
4572 * our individual unicast filters.
4574 if (efx_ef10_filter_insert_addr_list(efx
, vlan
, false, false))
4575 efx_ef10_filter_insert_def(efx
, vlan
, false, false);
4578 /* Insert/renew multicast filters */
4579 /* If changing promiscuous state with cascaded multicast filters, remove
4580 * old filters first, so that packets are dropped rather than duplicated
4582 if (nic_data
->workaround_26807
&&
4583 table
->mc_promisc_last
!= table
->mc_promisc
)
4584 efx_ef10_filter_remove_old(efx
);
4585 if (table
->mc_promisc
) {
4586 if (nic_data
->workaround_26807
) {
4587 /* If we failed to insert promiscuous filters, rollback
4588 * and fall back to individual multicast filters
4590 if (efx_ef10_filter_insert_def(efx
, vlan
, true, true)) {
4591 /* Changing promisc state, so remove old filters */
4592 efx_ef10_filter_remove_old(efx
);
4593 efx_ef10_filter_insert_addr_list(efx
, vlan
,
4597 /* If we failed to insert promiscuous filters, don't
4598 * rollback. Regardless, also insert the mc_list
4600 efx_ef10_filter_insert_def(efx
, vlan
, true, false);
4601 efx_ef10_filter_insert_addr_list(efx
, vlan
, true, false);
4604 /* If any filters failed to insert, rollback and fall back to
4605 * promiscuous mode - mc_def filter and maybe broadcast. If
4606 * that fails, roll back again and insert as many of our
4607 * individual multicast filters as we can.
4609 if (efx_ef10_filter_insert_addr_list(efx
, vlan
, true, true)) {
4610 /* Changing promisc state, so remove old filters */
4611 if (nic_data
->workaround_26807
)
4612 efx_ef10_filter_remove_old(efx
);
4613 if (efx_ef10_filter_insert_def(efx
, vlan
, true, true))
4614 efx_ef10_filter_insert_addr_list(efx
, vlan
,
4620 /* Caller must hold efx->filter_sem for read if race against
4621 * efx_ef10_filter_table_remove() is possible
4623 static void efx_ef10_filter_sync_rx_mode(struct efx_nic
*efx
)
4625 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4626 struct net_device
*net_dev
= efx
->net_dev
;
4627 struct efx_ef10_filter_vlan
*vlan
;
4630 if (!efx_dev_registered(efx
))
4636 efx_ef10_filter_mark_old(efx
);
4638 /* Copy/convert the address lists; add the primary station
4639 * address and broadcast address
4641 netif_addr_lock_bh(net_dev
);
4642 efx_ef10_filter_uc_addr_list(efx
);
4643 efx_ef10_filter_mc_addr_list(efx
);
4644 netif_addr_unlock_bh(net_dev
);
4646 /* If VLAN filtering changes, all old filters are finally removed.
4647 * Do it in advance to avoid conflicts for unicast untagged and
4648 * VLAN 0 tagged filters.
4650 vlan_filter
= !!(net_dev
->features
& NETIF_F_HW_VLAN_CTAG_FILTER
);
4651 if (table
->vlan_filter
!= vlan_filter
) {
4652 table
->vlan_filter
= vlan_filter
;
4653 efx_ef10_filter_remove_old(efx
);
4656 list_for_each_entry(vlan
, &table
->vlan_list
, list
)
4657 efx_ef10_filter_vlan_sync_rx_mode(efx
, vlan
);
4659 efx_ef10_filter_remove_old(efx
);
4660 table
->mc_promisc_last
= table
->mc_promisc
;
4663 static struct efx_ef10_filter_vlan
*efx_ef10_filter_find_vlan(struct efx_nic
*efx
, u16 vid
)
4665 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4666 struct efx_ef10_filter_vlan
*vlan
;
4668 WARN_ON(!rwsem_is_locked(&efx
->filter_sem
));
4670 list_for_each_entry(vlan
, &table
->vlan_list
, list
) {
4671 if (vlan
->vid
== vid
)
4678 static int efx_ef10_filter_add_vlan(struct efx_nic
*efx
, u16 vid
)
4680 struct efx_ef10_filter_table
*table
= efx
->filter_state
;
4681 struct efx_ef10_filter_vlan
*vlan
;
4684 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4687 vlan
= efx_ef10_filter_find_vlan(efx
, vid
);
4688 if (WARN_ON(vlan
)) {
4689 netif_err(efx
, drv
, efx
->net_dev
,
4690 "VLAN %u already added\n", vid
);
4694 vlan
= kzalloc(sizeof(*vlan
), GFP_KERNEL
);
4700 for (i
= 0; i
< ARRAY_SIZE(vlan
->uc
); i
++)
4701 vlan
->uc
[i
] = EFX_EF10_FILTER_ID_INVALID
;
4702 for (i
= 0; i
< ARRAY_SIZE(vlan
->mc
); i
++)
4703 vlan
->mc
[i
] = EFX_EF10_FILTER_ID_INVALID
;
4704 vlan
->ucdef
= EFX_EF10_FILTER_ID_INVALID
;
4705 vlan
->bcast
= EFX_EF10_FILTER_ID_INVALID
;
4706 vlan
->mcdef
= EFX_EF10_FILTER_ID_INVALID
;
4708 list_add_tail(&vlan
->list
, &table
->vlan_list
);
4710 if (efx_dev_registered(efx
))
4711 efx_ef10_filter_vlan_sync_rx_mode(efx
, vlan
);
4716 static void efx_ef10_filter_del_vlan_internal(struct efx_nic
*efx
,
4717 struct efx_ef10_filter_vlan
*vlan
)
4721 /* See comment in efx_ef10_filter_table_remove() */
4722 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4725 list_del(&vlan
->list
);
4727 for (i
= 0; i
< ARRAY_SIZE(vlan
->uc
); i
++)
4728 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
,
4730 for (i
= 0; i
< ARRAY_SIZE(vlan
->mc
); i
++)
4731 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
,
4733 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
, vlan
->ucdef
);
4734 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
, vlan
->bcast
);
4735 efx_ef10_filter_remove_unsafe(efx
, EFX_FILTER_PRI_AUTO
, vlan
->mcdef
);
4740 static void efx_ef10_filter_del_vlan(struct efx_nic
*efx
, u16 vid
)
4742 struct efx_ef10_filter_vlan
*vlan
;
4744 /* See comment in efx_ef10_filter_table_remove() */
4745 if (!efx_rwsem_assert_write_locked(&efx
->filter_sem
))
4748 vlan
= efx_ef10_filter_find_vlan(efx
, vid
);
4750 netif_err(efx
, drv
, efx
->net_dev
,
4751 "VLAN %u not found in filter state\n", vid
);
4755 efx_ef10_filter_del_vlan_internal(efx
, vlan
);
4758 static int efx_ef10_set_mac_address(struct efx_nic
*efx
)
4760 MCDI_DECLARE_BUF(inbuf
, MC_CMD_VADAPTOR_SET_MAC_IN_LEN
);
4761 struct efx_ef10_nic_data
*nic_data
= efx
->nic_data
;
4762 bool was_enabled
= efx
->port_enabled
;
4765 efx_device_detach_sync(efx
);
4766 efx_net_stop(efx
->net_dev
);
4768 mutex_lock(&efx
->mac_lock
);
4769 down_write(&efx
->filter_sem
);
4770 efx_ef10_filter_table_remove(efx
);
4772 ether_addr_copy(MCDI_PTR(inbuf
, VADAPTOR_SET_MAC_IN_MACADDR
),
4773 efx
->net_dev
->dev_addr
);
4774 MCDI_SET_DWORD(inbuf
, VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID
,
4775 nic_data
->vport_id
);
4776 rc
= efx_mcdi_rpc_quiet(efx
, MC_CMD_VADAPTOR_SET_MAC
, inbuf
,
4777 sizeof(inbuf
), NULL
, 0, NULL
);
4779 efx_ef10_filter_table_probe(efx
);
4780 up_write(&efx
->filter_sem
);
4781 mutex_unlock(&efx
->mac_lock
);
4784 efx_net_open(efx
->net_dev
);
4785 netif_device_attach(efx
->net_dev
);
4787 #ifdef CONFIG_SFC_SRIOV
4788 if (efx
->pci_dev
->is_virtfn
&& efx
->pci_dev
->physfn
) {
4789 struct pci_dev
*pci_dev_pf
= efx
->pci_dev
->physfn
;
4792 struct efx_nic
*efx_pf
;
4794 /* Switch to PF and change MAC address on vport */
4795 efx_pf
= pci_get_drvdata(pci_dev_pf
);
4797 rc
= efx_ef10_sriov_set_vf_mac(efx_pf
,
4799 efx
->net_dev
->dev_addr
);
4801 struct efx_nic
*efx_pf
= pci_get_drvdata(pci_dev_pf
);
4802 struct efx_ef10_nic_data
*nic_data
= efx_pf
->nic_data
;
4805 /* MAC address successfully changed by VF (with MAC
4806 * spoofing) so update the parent PF if possible.
4808 for (i
= 0; i
< efx_pf
->vf_count
; ++i
) {
4809 struct ef10_vf
*vf
= nic_data
->vf
+ i
;
4811 if (vf
->efx
== efx
) {
4812 ether_addr_copy(vf
->mac
,
4813 efx
->net_dev
->dev_addr
);
4821 netif_err(efx
, drv
, efx
->net_dev
,
4822 "Cannot change MAC address; use sfboot to enable"
4823 " mac-spoofing on this interface\n");
4824 } else if (rc
== -ENOSYS
&& !efx_ef10_is_vf(efx
)) {
4825 /* If the active MCFW does not support MC_CMD_VADAPTOR_SET_MAC
4826 * fall-back to the method of changing the MAC address on the
4827 * vport. This only applies to PFs because such versions of
4828 * MCFW do not support VFs.
4830 rc
= efx_ef10_vport_set_mac_address(efx
);
4832 efx_mcdi_display_error(efx
, MC_CMD_VADAPTOR_SET_MAC
,
4833 sizeof(inbuf
), NULL
, 0, rc
);
4839 static int efx_ef10_mac_reconfigure(struct efx_nic
*efx
)
4841 efx_ef10_filter_sync_rx_mode(efx
);
4843 return efx_mcdi_set_mac(efx
);
4846 static int efx_ef10_mac_reconfigure_vf(struct efx_nic
*efx
)
4848 efx_ef10_filter_sync_rx_mode(efx
);
4853 static int efx_ef10_start_bist(struct efx_nic
*efx
, u32 bist_type
)
4855 MCDI_DECLARE_BUF(inbuf
, MC_CMD_START_BIST_IN_LEN
);
4857 MCDI_SET_DWORD(inbuf
, START_BIST_IN_TYPE
, bist_type
);
4858 return efx_mcdi_rpc(efx
, MC_CMD_START_BIST
, inbuf
, sizeof(inbuf
),
4862 /* MC BISTs follow a different poll mechanism to phy BISTs.
4863 * The BIST is done in the poll handler on the MC, and the MCDI command
4864 * will block until the BIST is done.
4866 static int efx_ef10_poll_bist(struct efx_nic
*efx
)
4869 MCDI_DECLARE_BUF(outbuf
, MC_CMD_POLL_BIST_OUT_LEN
);
4873 rc
= efx_mcdi_rpc(efx
, MC_CMD_POLL_BIST
, NULL
, 0,
4874 outbuf
, sizeof(outbuf
), &outlen
);
4878 if (outlen
< MC_CMD_POLL_BIST_OUT_LEN
)
4881 result
= MCDI_DWORD(outbuf
, POLL_BIST_OUT_RESULT
);
4883 case MC_CMD_POLL_BIST_PASSED
:
4884 netif_dbg(efx
, hw
, efx
->net_dev
, "BIST passed.\n");
4886 case MC_CMD_POLL_BIST_TIMEOUT
:
4887 netif_err(efx
, hw
, efx
->net_dev
, "BIST timed out\n");
4889 case MC_CMD_POLL_BIST_FAILED
:
4890 netif_err(efx
, hw
, efx
->net_dev
, "BIST failed.\n");
4893 netif_err(efx
, hw
, efx
->net_dev
,
4894 "BIST returned unknown result %u", result
);
4899 static int efx_ef10_run_bist(struct efx_nic
*efx
, u32 bist_type
)
4903 netif_dbg(efx
, drv
, efx
->net_dev
, "starting BIST type %u\n", bist_type
);
4905 rc
= efx_ef10_start_bist(efx
, bist_type
);
4909 return efx_ef10_poll_bist(efx
);
4913 efx_ef10_test_chip(struct efx_nic
*efx
, struct efx_self_tests
*tests
)
4917 efx_reset_down(efx
, RESET_TYPE_WORLD
);
4919 rc
= efx_mcdi_rpc(efx
, MC_CMD_ENABLE_OFFLINE_BIST
,
4920 NULL
, 0, NULL
, 0, NULL
);
4924 tests
->memory
= efx_ef10_run_bist(efx
, MC_CMD_MC_MEM_BIST
) ? -1 : 1;
4925 tests
->registers
= efx_ef10_run_bist(efx
, MC_CMD_REG_BIST
) ? -1 : 1;
4927 rc
= efx_mcdi_reset(efx
, RESET_TYPE_WORLD
);
4932 rc2
= efx_reset_up(efx
, RESET_TYPE_WORLD
, rc
== 0);
4933 return rc
? rc
: rc2
;
4936 #ifdef CONFIG_SFC_MTD
4938 struct efx_ef10_nvram_type_info
{
4939 u16 type
, type_mask
;
4944 static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types
[] = {
4945 { NVRAM_PARTITION_TYPE_MC_FIRMWARE
, 0, 0, "sfc_mcfw" },
4946 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP
, 0, 0, "sfc_mcfw_backup" },
4947 { NVRAM_PARTITION_TYPE_EXPANSION_ROM
, 0, 0, "sfc_exp_rom" },
4948 { NVRAM_PARTITION_TYPE_STATIC_CONFIG
, 0, 0, "sfc_static_cfg" },
4949 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG
, 0, 0, "sfc_dynamic_cfg" },
4950 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0
, 0, 0, "sfc_exp_rom_cfg" },
4951 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1
, 0, 1, "sfc_exp_rom_cfg" },
4952 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2
, 0, 2, "sfc_exp_rom_cfg" },
4953 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3
, 0, 3, "sfc_exp_rom_cfg" },
4954 { NVRAM_PARTITION_TYPE_LICENSE
, 0, 0, "sfc_license" },
4955 { NVRAM_PARTITION_TYPE_PHY_MIN
, 0xff, 0, "sfc_phy_fw" },
4958 static int efx_ef10_mtd_probe_partition(struct efx_nic
*efx
,
4959 struct efx_mcdi_mtd_partition
*part
,
4962 MCDI_DECLARE_BUF(inbuf
, MC_CMD_NVRAM_METADATA_IN_LEN
);
4963 MCDI_DECLARE_BUF(outbuf
, MC_CMD_NVRAM_METADATA_OUT_LENMAX
);
4964 const struct efx_ef10_nvram_type_info
*info
;
4965 size_t size
, erase_size
, outlen
;
4969 for (info
= efx_ef10_nvram_types
; ; info
++) {
4971 efx_ef10_nvram_types
+ ARRAY_SIZE(efx_ef10_nvram_types
))
4973 if ((type
& ~info
->type_mask
) == info
->type
)
4976 if (info
->port
!= efx_port_num(efx
))
4979 rc
= efx_mcdi_nvram_info(efx
, type
, &size
, &erase_size
, &protected);
4983 return -ENODEV
; /* hide it */
4985 part
->nvram_type
= type
;
4987 MCDI_SET_DWORD(inbuf
, NVRAM_METADATA_IN_TYPE
, type
);
4988 rc
= efx_mcdi_rpc(efx
, MC_CMD_NVRAM_METADATA
, inbuf
, sizeof(inbuf
),
4989 outbuf
, sizeof(outbuf
), &outlen
);
4992 if (outlen
< MC_CMD_NVRAM_METADATA_OUT_LENMIN
)
4994 if (MCDI_DWORD(outbuf
, NVRAM_METADATA_OUT_FLAGS
) &
4995 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN
))
4996 part
->fw_subtype
= MCDI_DWORD(outbuf
,
4997 NVRAM_METADATA_OUT_SUBTYPE
);
4999 part
->common
.dev_type_name
= "EF10 NVRAM manager";
5000 part
->common
.type_name
= info
->name
;
5002 part
->common
.mtd
.type
= MTD_NORFLASH
;
5003 part
->common
.mtd
.flags
= MTD_CAP_NORFLASH
;
5004 part
->common
.mtd
.size
= size
;
5005 part
->common
.mtd
.erasesize
= erase_size
;
5010 static int efx_ef10_mtd_probe(struct efx_nic
*efx
)
5012 MCDI_DECLARE_BUF(outbuf
, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX
);
5013 struct efx_mcdi_mtd_partition
*parts
;
5014 size_t outlen
, n_parts_total
, i
, n_parts
;
5020 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN
!= 0);
5021 rc
= efx_mcdi_rpc(efx
, MC_CMD_NVRAM_PARTITIONS
, NULL
, 0,
5022 outbuf
, sizeof(outbuf
), &outlen
);
5025 if (outlen
< MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN
)
5028 n_parts_total
= MCDI_DWORD(outbuf
, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS
);
5030 MCDI_VAR_ARRAY_LEN(outlen
, NVRAM_PARTITIONS_OUT_TYPE_ID
))
5033 parts
= kcalloc(n_parts_total
, sizeof(*parts
), GFP_KERNEL
);
5038 for (i
= 0; i
< n_parts_total
; i
++) {
5039 type
= MCDI_ARRAY_DWORD(outbuf
, NVRAM_PARTITIONS_OUT_TYPE_ID
,
5041 rc
= efx_ef10_mtd_probe_partition(efx
, &parts
[n_parts
], type
);
5044 else if (rc
!= -ENODEV
)
5048 rc
= efx_mtd_add(efx
, &parts
[0].common
, n_parts
, sizeof(*parts
));
5055 #endif /* CONFIG_SFC_MTD */
5057 static void efx_ef10_ptp_write_host_time(struct efx_nic
*efx
, u32 host_time
)
5059 _efx_writed(efx
, cpu_to_le32(host_time
), ER_DZ_MC_DB_LWRD
);
5062 static void efx_ef10_ptp_write_host_time_vf(struct efx_nic
*efx
,
5065 static int efx_ef10_rx_enable_timestamping(struct efx_channel
*channel
,
5068 MCDI_DECLARE_BUF(inbuf
, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN
);
5071 if (channel
->sync_events_state
== SYNC_EVENTS_REQUESTED
||
5072 channel
->sync_events_state
== SYNC_EVENTS_VALID
||
5073 (temp
&& channel
->sync_events_state
== SYNC_EVENTS_DISABLED
))
5075 channel
->sync_events_state
= SYNC_EVENTS_REQUESTED
;
5077 MCDI_SET_DWORD(inbuf
, PTP_IN_OP
, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE
);
5078 MCDI_SET_DWORD(inbuf
, PTP_IN_PERIPH_ID
, 0);
5079 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE
,
5082 rc
= efx_mcdi_rpc(channel
->efx
, MC_CMD_PTP
,
5083 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
5086 channel
->sync_events_state
= temp
? SYNC_EVENTS_QUIESCENT
:
5087 SYNC_EVENTS_DISABLED
;
5092 static int efx_ef10_rx_disable_timestamping(struct efx_channel
*channel
,
5095 MCDI_DECLARE_BUF(inbuf
, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN
);
5098 if (channel
->sync_events_state
== SYNC_EVENTS_DISABLED
||
5099 (temp
&& channel
->sync_events_state
== SYNC_EVENTS_QUIESCENT
))
5101 if (channel
->sync_events_state
== SYNC_EVENTS_QUIESCENT
) {
5102 channel
->sync_events_state
= SYNC_EVENTS_DISABLED
;
5105 channel
->sync_events_state
= temp
? SYNC_EVENTS_QUIESCENT
:
5106 SYNC_EVENTS_DISABLED
;
5108 MCDI_SET_DWORD(inbuf
, PTP_IN_OP
, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE
);
5109 MCDI_SET_DWORD(inbuf
, PTP_IN_PERIPH_ID
, 0);
5110 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL
,
5111 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE
);
5112 MCDI_SET_DWORD(inbuf
, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE
,
5115 rc
= efx_mcdi_rpc(channel
->efx
, MC_CMD_PTP
,
5116 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
5121 static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic
*efx
, bool en
,
5124 int (*set
)(struct efx_channel
*channel
, bool temp
);
5125 struct efx_channel
*channel
;
5128 efx_ef10_rx_enable_timestamping
:
5129 efx_ef10_rx_disable_timestamping
;
5131 efx_for_each_channel(channel
, efx
) {
5132 int rc
= set(channel
, temp
);
5133 if (en
&& rc
!= 0) {
5134 efx_ef10_ptp_set_ts_sync_events(efx
, false, temp
);
5142 static int efx_ef10_ptp_set_ts_config_vf(struct efx_nic
*efx
,
5143 struct hwtstamp_config
*init
)
5148 static int efx_ef10_ptp_set_ts_config(struct efx_nic
*efx
,
5149 struct hwtstamp_config
*init
)
5153 switch (init
->rx_filter
) {
5154 case HWTSTAMP_FILTER_NONE
:
5155 efx_ef10_ptp_set_ts_sync_events(efx
, false, false);
5156 /* if TX timestamping is still requested then leave PTP on */
5157 return efx_ptp_change_mode(efx
,
5158 init
->tx_type
!= HWTSTAMP_TX_OFF
, 0);
5159 case HWTSTAMP_FILTER_ALL
:
5160 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
5161 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
5162 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
5163 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
5164 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
5165 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
5166 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
5167 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
5168 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
5169 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
5170 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
5171 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
5172 init
->rx_filter
= HWTSTAMP_FILTER_ALL
;
5173 rc
= efx_ptp_change_mode(efx
, true, 0);
5175 rc
= efx_ef10_ptp_set_ts_sync_events(efx
, true, false);
5177 efx_ptp_change_mode(efx
, false, 0);
5184 static int efx_ef10_vlan_rx_add_vid(struct efx_nic
*efx
, __be16 proto
, u16 vid
)
5186 if (proto
!= htons(ETH_P_8021Q
))
5189 return efx_ef10_add_vlan(efx
, vid
);
5192 static int efx_ef10_vlan_rx_kill_vid(struct efx_nic
*efx
, __be16 proto
, u16 vid
)
5194 if (proto
!= htons(ETH_P_8021Q
))
5197 return efx_ef10_del_vlan(efx
, vid
);
5200 #define EF10_OFFLOAD_FEATURES \
5201 (NETIF_F_IP_CSUM | \
5202 NETIF_F_HW_VLAN_CTAG_FILTER | \
5203 NETIF_F_IPV6_CSUM | \
5207 const struct efx_nic_type efx_hunt_a0_vf_nic_type
= {
5209 .mem_bar
= EFX_MEM_VF_BAR
,
5210 .mem_map_size
= efx_ef10_mem_map_size
,
5211 .probe
= efx_ef10_probe_vf
,
5212 .remove
= efx_ef10_remove
,
5213 .dimension_resources
= efx_ef10_dimension_resources
,
5214 .init
= efx_ef10_init_nic
,
5215 .fini
= efx_port_dummy_op_void
,
5216 .map_reset_reason
= efx_ef10_map_reset_reason
,
5217 .map_reset_flags
= efx_ef10_map_reset_flags
,
5218 .reset
= efx_ef10_reset
,
5219 .probe_port
= efx_mcdi_port_probe
,
5220 .remove_port
= efx_mcdi_port_remove
,
5221 .fini_dmaq
= efx_ef10_fini_dmaq
,
5222 .prepare_flr
= efx_ef10_prepare_flr
,
5223 .finish_flr
= efx_port_dummy_op_void
,
5224 .describe_stats
= efx_ef10_describe_stats
,
5225 .update_stats
= efx_ef10_update_stats_vf
,
5226 .start_stats
= efx_port_dummy_op_void
,
5227 .pull_stats
= efx_port_dummy_op_void
,
5228 .stop_stats
= efx_port_dummy_op_void
,
5229 .set_id_led
= efx_mcdi_set_id_led
,
5230 .push_irq_moderation
= efx_ef10_push_irq_moderation
,
5231 .reconfigure_mac
= efx_ef10_mac_reconfigure_vf
,
5232 .check_mac_fault
= efx_mcdi_mac_check_fault
,
5233 .reconfigure_port
= efx_mcdi_port_reconfigure
,
5234 .get_wol
= efx_ef10_get_wol_vf
,
5235 .set_wol
= efx_ef10_set_wol_vf
,
5236 .resume_wol
= efx_port_dummy_op_void
,
5237 .mcdi_request
= efx_ef10_mcdi_request
,
5238 .mcdi_poll_response
= efx_ef10_mcdi_poll_response
,
5239 .mcdi_read_response
= efx_ef10_mcdi_read_response
,
5240 .mcdi_poll_reboot
= efx_ef10_mcdi_poll_reboot
,
5241 .mcdi_reboot_detected
= efx_ef10_mcdi_reboot_detected
,
5242 .irq_enable_master
= efx_port_dummy_op_void
,
5243 .irq_test_generate
= efx_ef10_irq_test_generate
,
5244 .irq_disable_non_ev
= efx_port_dummy_op_void
,
5245 .irq_handle_msi
= efx_ef10_msi_interrupt
,
5246 .irq_handle_legacy
= efx_ef10_legacy_interrupt
,
5247 .tx_probe
= efx_ef10_tx_probe
,
5248 .tx_init
= efx_ef10_tx_init
,
5249 .tx_remove
= efx_ef10_tx_remove
,
5250 .tx_write
= efx_ef10_tx_write
,
5251 .rx_push_rss_config
= efx_ef10_vf_rx_push_rss_config
,
5252 .rx_probe
= efx_ef10_rx_probe
,
5253 .rx_init
= efx_ef10_rx_init
,
5254 .rx_remove
= efx_ef10_rx_remove
,
5255 .rx_write
= efx_ef10_rx_write
,
5256 .rx_defer_refill
= efx_ef10_rx_defer_refill
,
5257 .ev_probe
= efx_ef10_ev_probe
,
5258 .ev_init
= efx_ef10_ev_init
,
5259 .ev_fini
= efx_ef10_ev_fini
,
5260 .ev_remove
= efx_ef10_ev_remove
,
5261 .ev_process
= efx_ef10_ev_process
,
5262 .ev_read_ack
= efx_ef10_ev_read_ack
,
5263 .ev_test_generate
= efx_ef10_ev_test_generate
,
5264 .filter_table_probe
= efx_ef10_filter_table_probe
,
5265 .filter_table_restore
= efx_ef10_filter_table_restore
,
5266 .filter_table_remove
= efx_ef10_filter_table_remove
,
5267 .filter_update_rx_scatter
= efx_ef10_filter_update_rx_scatter
,
5268 .filter_insert
= efx_ef10_filter_insert
,
5269 .filter_remove_safe
= efx_ef10_filter_remove_safe
,
5270 .filter_get_safe
= efx_ef10_filter_get_safe
,
5271 .filter_clear_rx
= efx_ef10_filter_clear_rx
,
5272 .filter_count_rx_used
= efx_ef10_filter_count_rx_used
,
5273 .filter_get_rx_id_limit
= efx_ef10_filter_get_rx_id_limit
,
5274 .filter_get_rx_ids
= efx_ef10_filter_get_rx_ids
,
5275 #ifdef CONFIG_RFS_ACCEL
5276 .filter_rfs_insert
= efx_ef10_filter_rfs_insert
,
5277 .filter_rfs_expire_one
= efx_ef10_filter_rfs_expire_one
,
5279 #ifdef CONFIG_SFC_MTD
5280 .mtd_probe
= efx_port_dummy_op_int
,
5282 .ptp_write_host_time
= efx_ef10_ptp_write_host_time_vf
,
5283 .ptp_set_ts_config
= efx_ef10_ptp_set_ts_config_vf
,
5284 .vlan_rx_add_vid
= efx_ef10_vlan_rx_add_vid
,
5285 .vlan_rx_kill_vid
= efx_ef10_vlan_rx_kill_vid
,
5286 #ifdef CONFIG_SFC_SRIOV
5287 .vswitching_probe
= efx_ef10_vswitching_probe_vf
,
5288 .vswitching_restore
= efx_ef10_vswitching_restore_vf
,
5289 .vswitching_remove
= efx_ef10_vswitching_remove_vf
,
5290 .sriov_get_phys_port_id
= efx_ef10_sriov_get_phys_port_id
,
5292 .get_mac_address
= efx_ef10_get_mac_address_vf
,
5293 .set_mac_address
= efx_ef10_set_mac_address
,
5295 .revision
= EFX_REV_HUNT_A0
,
5296 .max_dma_mask
= DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH
),
5297 .rx_prefix_size
= ES_DZ_RX_PREFIX_SIZE
,
5298 .rx_hash_offset
= ES_DZ_RX_PREFIX_HASH_OFST
,
5299 .rx_ts_offset
= ES_DZ_RX_PREFIX_TSTAMP_OFST
,
5300 .can_rx_scatter
= true,
5301 .always_rx_scatter
= true,
5302 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
5303 .timer_period_max
= 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH
,
5304 .offload_features
= EF10_OFFLOAD_FEATURES
,
5306 .max_rx_ip_filters
= HUNT_FILTER_TBL_ROWS
,
5307 .hwtstamp_filters
= 1 << HWTSTAMP_FILTER_NONE
|
5308 1 << HWTSTAMP_FILTER_ALL
,
5311 const struct efx_nic_type efx_hunt_a0_nic_type
= {
5313 .mem_bar
= EFX_MEM_BAR
,
5314 .mem_map_size
= efx_ef10_mem_map_size
,
5315 .probe
= efx_ef10_probe_pf
,
5316 .remove
= efx_ef10_remove
,
5317 .dimension_resources
= efx_ef10_dimension_resources
,
5318 .init
= efx_ef10_init_nic
,
5319 .fini
= efx_port_dummy_op_void
,
5320 .map_reset_reason
= efx_ef10_map_reset_reason
,
5321 .map_reset_flags
= efx_ef10_map_reset_flags
,
5322 .reset
= efx_ef10_reset
,
5323 .probe_port
= efx_mcdi_port_probe
,
5324 .remove_port
= efx_mcdi_port_remove
,
5325 .fini_dmaq
= efx_ef10_fini_dmaq
,
5326 .prepare_flr
= efx_ef10_prepare_flr
,
5327 .finish_flr
= efx_port_dummy_op_void
,
5328 .describe_stats
= efx_ef10_describe_stats
,
5329 .update_stats
= efx_ef10_update_stats_pf
,
5330 .start_stats
= efx_mcdi_mac_start_stats
,
5331 .pull_stats
= efx_mcdi_mac_pull_stats
,
5332 .stop_stats
= efx_mcdi_mac_stop_stats
,
5333 .set_id_led
= efx_mcdi_set_id_led
,
5334 .push_irq_moderation
= efx_ef10_push_irq_moderation
,
5335 .reconfigure_mac
= efx_ef10_mac_reconfigure
,
5336 .check_mac_fault
= efx_mcdi_mac_check_fault
,
5337 .reconfigure_port
= efx_mcdi_port_reconfigure
,
5338 .get_wol
= efx_ef10_get_wol
,
5339 .set_wol
= efx_ef10_set_wol
,
5340 .resume_wol
= efx_port_dummy_op_void
,
5341 .test_chip
= efx_ef10_test_chip
,
5342 .test_nvram
= efx_mcdi_nvram_test_all
,
5343 .mcdi_request
= efx_ef10_mcdi_request
,
5344 .mcdi_poll_response
= efx_ef10_mcdi_poll_response
,
5345 .mcdi_read_response
= efx_ef10_mcdi_read_response
,
5346 .mcdi_poll_reboot
= efx_ef10_mcdi_poll_reboot
,
5347 .mcdi_reboot_detected
= efx_ef10_mcdi_reboot_detected
,
5348 .irq_enable_master
= efx_port_dummy_op_void
,
5349 .irq_test_generate
= efx_ef10_irq_test_generate
,
5350 .irq_disable_non_ev
= efx_port_dummy_op_void
,
5351 .irq_handle_msi
= efx_ef10_msi_interrupt
,
5352 .irq_handle_legacy
= efx_ef10_legacy_interrupt
,
5353 .tx_probe
= efx_ef10_tx_probe
,
5354 .tx_init
= efx_ef10_tx_init
,
5355 .tx_remove
= efx_ef10_tx_remove
,
5356 .tx_write
= efx_ef10_tx_write
,
5357 .rx_push_rss_config
= efx_ef10_pf_rx_push_rss_config
,
5358 .rx_probe
= efx_ef10_rx_probe
,
5359 .rx_init
= efx_ef10_rx_init
,
5360 .rx_remove
= efx_ef10_rx_remove
,
5361 .rx_write
= efx_ef10_rx_write
,
5362 .rx_defer_refill
= efx_ef10_rx_defer_refill
,
5363 .ev_probe
= efx_ef10_ev_probe
,
5364 .ev_init
= efx_ef10_ev_init
,
5365 .ev_fini
= efx_ef10_ev_fini
,
5366 .ev_remove
= efx_ef10_ev_remove
,
5367 .ev_process
= efx_ef10_ev_process
,
5368 .ev_read_ack
= efx_ef10_ev_read_ack
,
5369 .ev_test_generate
= efx_ef10_ev_test_generate
,
5370 .filter_table_probe
= efx_ef10_filter_table_probe
,
5371 .filter_table_restore
= efx_ef10_filter_table_restore
,
5372 .filter_table_remove
= efx_ef10_filter_table_remove
,
5373 .filter_update_rx_scatter
= efx_ef10_filter_update_rx_scatter
,
5374 .filter_insert
= efx_ef10_filter_insert
,
5375 .filter_remove_safe
= efx_ef10_filter_remove_safe
,
5376 .filter_get_safe
= efx_ef10_filter_get_safe
,
5377 .filter_clear_rx
= efx_ef10_filter_clear_rx
,
5378 .filter_count_rx_used
= efx_ef10_filter_count_rx_used
,
5379 .filter_get_rx_id_limit
= efx_ef10_filter_get_rx_id_limit
,
5380 .filter_get_rx_ids
= efx_ef10_filter_get_rx_ids
,
5381 #ifdef CONFIG_RFS_ACCEL
5382 .filter_rfs_insert
= efx_ef10_filter_rfs_insert
,
5383 .filter_rfs_expire_one
= efx_ef10_filter_rfs_expire_one
,
5385 #ifdef CONFIG_SFC_MTD
5386 .mtd_probe
= efx_ef10_mtd_probe
,
5387 .mtd_rename
= efx_mcdi_mtd_rename
,
5388 .mtd_read
= efx_mcdi_mtd_read
,
5389 .mtd_erase
= efx_mcdi_mtd_erase
,
5390 .mtd_write
= efx_mcdi_mtd_write
,
5391 .mtd_sync
= efx_mcdi_mtd_sync
,
5393 .ptp_write_host_time
= efx_ef10_ptp_write_host_time
,
5394 .ptp_set_ts_sync_events
= efx_ef10_ptp_set_ts_sync_events
,
5395 .ptp_set_ts_config
= efx_ef10_ptp_set_ts_config
,
5396 .vlan_rx_add_vid
= efx_ef10_vlan_rx_add_vid
,
5397 .vlan_rx_kill_vid
= efx_ef10_vlan_rx_kill_vid
,
5398 #ifdef CONFIG_SFC_SRIOV
5399 .sriov_configure
= efx_ef10_sriov_configure
,
5400 .sriov_init
= efx_ef10_sriov_init
,
5401 .sriov_fini
= efx_ef10_sriov_fini
,
5402 .sriov_wanted
= efx_ef10_sriov_wanted
,
5403 .sriov_reset
= efx_ef10_sriov_reset
,
5404 .sriov_flr
= efx_ef10_sriov_flr
,
5405 .sriov_set_vf_mac
= efx_ef10_sriov_set_vf_mac
,
5406 .sriov_set_vf_vlan
= efx_ef10_sriov_set_vf_vlan
,
5407 .sriov_set_vf_spoofchk
= efx_ef10_sriov_set_vf_spoofchk
,
5408 .sriov_get_vf_config
= efx_ef10_sriov_get_vf_config
,
5409 .sriov_set_vf_link_state
= efx_ef10_sriov_set_vf_link_state
,
5410 .vswitching_probe
= efx_ef10_vswitching_probe_pf
,
5411 .vswitching_restore
= efx_ef10_vswitching_restore_pf
,
5412 .vswitching_remove
= efx_ef10_vswitching_remove_pf
,
5414 .get_mac_address
= efx_ef10_get_mac_address_pf
,
5415 .set_mac_address
= efx_ef10_set_mac_address
,
5417 .revision
= EFX_REV_HUNT_A0
,
5418 .max_dma_mask
= DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH
),
5419 .rx_prefix_size
= ES_DZ_RX_PREFIX_SIZE
,
5420 .rx_hash_offset
= ES_DZ_RX_PREFIX_HASH_OFST
,
5421 .rx_ts_offset
= ES_DZ_RX_PREFIX_TSTAMP_OFST
,
5422 .can_rx_scatter
= true,
5423 .always_rx_scatter
= true,
5424 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
5425 .timer_period_max
= 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH
,
5426 .offload_features
= EF10_OFFLOAD_FEATURES
,
5428 .max_rx_ip_filters
= HUNT_FILTER_TBL_ROWS
,
5429 .hwtstamp_filters
= 1 << HWTSTAMP_FILTER_NONE
|
5430 1 << HWTSTAMP_FILTER_ALL
,