1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2013 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/if_vlan.h>
20 #include <linux/timer.h>
21 #include <linux/mdio.h>
22 #include <linux/list.h>
23 #include <linux/pci.h>
24 #include <linux/device.h>
25 #include <linux/highmem.h>
26 #include <linux/workqueue.h>
27 #include <linux/mutex.h>
28 #include <linux/rwsem.h>
29 #include <linux/vmalloc.h>
30 #include <linux/i2c.h>
31 #include <linux/mtd/mtd.h>
32 #include <net/busy_poll.h>
38 /**************************************************************************
42 **************************************************************************/
44 #define EFX_DRIVER_VERSION "4.0"
47 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
48 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
50 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
51 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
54 /**************************************************************************
58 **************************************************************************/
60 #define EFX_MAX_CHANNELS 32U
61 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
62 #define EFX_EXTRA_CHANNEL_IOV 0
63 #define EFX_EXTRA_CHANNEL_PTP 1
64 #define EFX_MAX_EXTRA_CHANNELS 2U
66 /* Checksum generation is a per-queue option in hardware, so each
67 * queue visible to the networking core is backed by two hardware TX
69 #define EFX_MAX_TX_TC 2
70 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
71 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */
72 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */
73 #define EFX_TXQ_TYPES 4
74 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
76 /* Maximum possible MTU the driver supports */
77 #define EFX_MAX_MTU (9 * 1024)
79 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
80 * and should be a multiple of the cache line size.
82 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
84 /* If possible, we should ensure cache line alignment at start and end
85 * of every buffer. Otherwise, we just need to ensure 4-byte
86 * alignment of the network header.
89 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES
91 #define EFX_RX_BUF_ALIGNMENT 4
94 /* Forward declare Precision Time Protocol (PTP) support structure. */
96 struct hwtstamp_config
;
98 struct efx_self_tests
;
101 * struct efx_buffer - A general-purpose DMA buffer
102 * @addr: host base address of the buffer
103 * @dma_addr: DMA base address of the buffer
104 * @len: Buffer length, in bytes
106 * The NIC uses these buffers for its interrupt status registers and
116 * struct efx_special_buffer - DMA buffer entered into buffer table
117 * @buf: Standard &struct efx_buffer
118 * @index: Buffer index within controller;s buffer table
119 * @entries: Number of buffer table entries
121 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE.
122 * Event and descriptor rings are addressed via one or more buffer
123 * table entries (and so can be physically non-contiguous, although we
124 * currently do not take advantage of that). On Falcon and Siena we
125 * have to take care of allocating and initialising the entries
126 * ourselves. On later hardware this is managed by the firmware and
127 * @index and @entries are left as 0.
129 struct efx_special_buffer
{
130 struct efx_buffer buf
;
132 unsigned int entries
;
136 * struct efx_tx_buffer - buffer state for a TX descriptor
137 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
138 * freed when descriptor completes
139 * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be
140 * freed when descriptor completes.
141 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor.
142 * @dma_addr: DMA address of the fragment.
143 * @flags: Flags for allocation and DMA mapping type
144 * @len: Length of this fragment.
145 * This field is zero when the queue slot is empty.
146 * @unmap_len: Length of this fragment to unmap
147 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
148 * Only valid if @unmap_len != 0.
150 struct efx_tx_buffer
{
152 const struct sk_buff
*skb
;
159 unsigned short flags
;
161 unsigned short unmap_len
;
162 unsigned short dma_offset
;
164 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */
165 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */
166 #define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */
167 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */
168 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */
171 * struct efx_tx_queue - An Efx TX queue
173 * This is a ring buffer of TX fragments.
174 * Since the TX completion path always executes on the same
175 * CPU and the xmit path can operate on different CPUs,
176 * performance is increased by ensuring that the completion
177 * path and the xmit path operate on different cache lines.
178 * This is particularly important if the xmit path is always
179 * executing on one CPU which is different from the completion
180 * path. There is also a cache line for members which are
181 * read but not written on the fast path.
183 * @efx: The associated Efx NIC
184 * @queue: DMA queue number
185 * @channel: The associated channel
186 * @core_txq: The networking core TX queue structure
187 * @buffer: The software buffer ring
188 * @tsoh_page: Array of pages of TSO header buffers
189 * @txd: The hardware descriptor ring
190 * @ptr_mask: The size of the ring minus 1.
191 * @piobuf: PIO buffer region for this TX queue (shared with its partner).
192 * Size of the region is efx_piobuf_size.
193 * @piobuf_offset: Buffer offset to be specified in PIO descriptors
194 * @initialised: Has hardware queue been initialised?
195 * @read_count: Current read pointer.
196 * This is the number of buffers that have been removed from both rings.
197 * @old_write_count: The value of @write_count when last checked.
198 * This is here for performance reasons. The xmit path will
199 * only get the up-to-date value of @write_count if this
200 * variable indicates that the queue is empty. This is to
201 * avoid cache-line ping-pong between the xmit path and the
203 * @merge_events: Number of TX merged completion events
204 * @insert_count: Current insert pointer
205 * This is the number of buffers that have been added to the
207 * @write_count: Current write pointer
208 * This is the number of buffers that have been added to the
210 * @old_read_count: The value of read_count when last checked.
211 * This is here for performance reasons. The xmit path will
212 * only get the up-to-date value of read_count if this
213 * variable indicates that the queue is full. This is to
214 * avoid cache-line ping-pong between the xmit path and the
216 * @tso_bursts: Number of times TSO xmit invoked by kernel
217 * @tso_long_headers: Number of packets with headers too long for standard
219 * @tso_packets: Number of packets via the TSO xmit path
220 * @pushes: Number of times the TX push feature has been used
221 * @pio_packets: Number of times the TX PIO feature has been used
222 * @empty_read_count: If the completion path has seen the queue as empty
223 * and the transmission path has not yet checked this, the value of
224 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
226 struct efx_tx_queue
{
227 /* Members which don't change on the fast path */
228 struct efx_nic
*efx ____cacheline_aligned_in_smp
;
230 struct efx_channel
*channel
;
231 struct netdev_queue
*core_txq
;
232 struct efx_tx_buffer
*buffer
;
233 struct efx_buffer
*tsoh_page
;
234 struct efx_special_buffer txd
;
235 unsigned int ptr_mask
;
236 void __iomem
*piobuf
;
237 unsigned int piobuf_offset
;
240 /* Members used mainly on the completion path */
241 unsigned int read_count ____cacheline_aligned_in_smp
;
242 unsigned int old_write_count
;
243 unsigned int merge_events
;
244 unsigned int bytes_compl
;
245 unsigned int pkts_compl
;
247 /* Members used only on the xmit path */
248 unsigned int insert_count ____cacheline_aligned_in_smp
;
249 unsigned int write_count
;
250 unsigned int old_read_count
;
251 unsigned int tso_bursts
;
252 unsigned int tso_long_headers
;
253 unsigned int tso_packets
;
255 unsigned int pio_packets
;
256 /* Statistics to supplement MAC stats */
257 unsigned long tx_packets
;
259 /* Members shared between paths and sometimes updated */
260 unsigned int empty_read_count ____cacheline_aligned_in_smp
;
261 #define EFX_EMPTY_COUNT_VALID 0x80000000
262 atomic_t flush_outstanding
;
266 * struct efx_rx_buffer - An Efx RX data buffer
267 * @dma_addr: DMA base address of the buffer
268 * @page: The associated page buffer.
269 * Will be %NULL if the buffer slot is currently free.
270 * @page_offset: If pending: offset in @page of DMA base address.
271 * If completed: offset in @page of Ethernet header.
272 * @len: If pending: length for DMA descriptor.
273 * If completed: received length, excluding hash prefix.
274 * @flags: Flags for buffer and packet state. These are only set on the
275 * first buffer of a scattered packet.
277 struct efx_rx_buffer
{
284 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001
285 #define EFX_RX_PKT_CSUMMED 0x0002
286 #define EFX_RX_PKT_DISCARD 0x0004
287 #define EFX_RX_PKT_TCP 0x0040
288 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */
291 * struct efx_rx_page_state - Page-based rx buffer state
293 * Inserted at the start of every page allocated for receive buffers.
294 * Used to facilitate sharing dma mappings between recycled rx buffers
295 * and those passed up to the kernel.
297 * @dma_addr: The dma address of this page.
299 struct efx_rx_page_state
{
302 unsigned int __pad
[0] ____cacheline_aligned
;
306 * struct efx_rx_queue - An Efx RX queue
307 * @efx: The associated Efx NIC
308 * @core_index: Index of network core RX queue. Will be >= 0 iff this
309 * is associated with a real RX queue.
310 * @buffer: The software buffer ring
311 * @rxd: The hardware descriptor ring
312 * @ptr_mask: The size of the ring minus 1.
313 * @refill_enabled: Enable refill whenever fill level is low
314 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
315 * @rxq_flush_pending.
316 * @added_count: Number of buffers added to the receive queue.
317 * @notified_count: Number of buffers given to NIC (<= @added_count).
318 * @removed_count: Number of buffers removed from the receive queue.
319 * @scatter_n: Used by NIC specific receive code.
320 * @scatter_len: Used by NIC specific receive code.
321 * @page_ring: The ring to store DMA mapped pages for reuse.
322 * @page_add: Counter to calculate the write pointer for the recycle ring.
323 * @page_remove: Counter to calculate the read pointer for the recycle ring.
324 * @page_recycle_count: The number of pages that have been recycled.
325 * @page_recycle_failed: The number of pages that couldn't be recycled because
326 * the kernel still held a reference to them.
327 * @page_recycle_full: The number of pages that were released because the
328 * recycle ring was full.
329 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
330 * @max_fill: RX descriptor maximum fill level (<= ring size)
331 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
333 * @min_fill: RX descriptor minimum non-zero fill level.
334 * This records the minimum fill level observed when a ring
335 * refill was triggered.
336 * @recycle_count: RX buffer recycle counter.
337 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
339 struct efx_rx_queue
{
342 struct efx_rx_buffer
*buffer
;
343 struct efx_special_buffer rxd
;
344 unsigned int ptr_mask
;
348 unsigned int added_count
;
349 unsigned int notified_count
;
350 unsigned int removed_count
;
351 unsigned int scatter_n
;
352 unsigned int scatter_len
;
353 struct page
**page_ring
;
354 unsigned int page_add
;
355 unsigned int page_remove
;
356 unsigned int page_recycle_count
;
357 unsigned int page_recycle_failed
;
358 unsigned int page_recycle_full
;
359 unsigned int page_ptr_mask
;
360 unsigned int max_fill
;
361 unsigned int fast_fill_trigger
;
362 unsigned int min_fill
;
363 unsigned int min_overfill
;
364 unsigned int recycle_count
;
365 struct timer_list slow_fill
;
366 unsigned int slow_fill_count
;
367 /* Statistics to supplement MAC stats */
368 unsigned long rx_packets
;
371 enum efx_sync_events_state
{
372 SYNC_EVENTS_DISABLED
= 0,
373 SYNC_EVENTS_QUIESCENT
,
374 SYNC_EVENTS_REQUESTED
,
379 * struct efx_channel - An Efx channel
381 * A channel comprises an event queue, at least one TX queue, at least
382 * one RX queue, and an associated tasklet for processing the event
385 * @efx: Associated Efx NIC
386 * @channel: Channel instance number
387 * @type: Channel type definition
388 * @eventq_init: Event queue initialised flag
389 * @enabled: Channel enabled indicator
390 * @irq: IRQ number (MSI and MSI-X only)
391 * @irq_moderation: IRQ moderation value (in hardware ticks)
392 * @napi_dev: Net device used with NAPI
393 * @napi_str: NAPI control structure
394 * @state: state for NAPI vs busy polling
395 * @state_lock: lock protecting @state
396 * @eventq: Event queue buffer
397 * @eventq_mask: Event queue pointer mask
398 * @eventq_read_ptr: Event queue read pointer
399 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
400 * @irq_count: Number of IRQs since last adaptive moderation decision
401 * @irq_mod_score: IRQ moderation score
402 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
403 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
404 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
405 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
406 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
407 * @n_rx_overlength: Count of RX_OVERLENGTH errors
408 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
409 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
410 * lack of descriptors
411 * @n_rx_merge_events: Number of RX merged completion events
412 * @n_rx_merge_packets: Number of RX packets completed by merged events
413 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
414 * __efx_rx_packet(), or zero if there is none
415 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
416 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0
417 * @rx_queue: RX queue for this channel
418 * @tx_queue: TX queues for this channel
419 * @sync_events_state: Current state of sync events on this channel
420 * @sync_timestamp_major: Major part of the last ptp sync event
421 * @sync_timestamp_minor: Minor part of the last ptp sync event
426 const struct efx_channel_type
*type
;
430 unsigned int irq_moderation
;
431 struct net_device
*napi_dev
;
432 struct napi_struct napi_str
;
433 #ifdef CONFIG_NET_RX_BUSY_POLL
435 spinlock_t state_lock
;
436 #define EFX_CHANNEL_STATE_IDLE 0
437 #define EFX_CHANNEL_STATE_NAPI (1 << 0) /* NAPI owns this channel */
438 #define EFX_CHANNEL_STATE_POLL (1 << 1) /* poll owns this channel */
439 #define EFX_CHANNEL_STATE_DISABLED (1 << 2) /* channel is disabled */
440 #define EFX_CHANNEL_STATE_NAPI_YIELD (1 << 3) /* NAPI yielded this channel */
441 #define EFX_CHANNEL_STATE_POLL_YIELD (1 << 4) /* poll yielded this channel */
442 #define EFX_CHANNEL_OWNED \
443 (EFX_CHANNEL_STATE_NAPI | EFX_CHANNEL_STATE_POLL)
444 #define EFX_CHANNEL_LOCKED \
445 (EFX_CHANNEL_OWNED | EFX_CHANNEL_STATE_DISABLED)
446 #define EFX_CHANNEL_USER_PEND \
447 (EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_POLL_YIELD)
448 #endif /* CONFIG_NET_RX_BUSY_POLL */
449 struct efx_special_buffer eventq
;
450 unsigned int eventq_mask
;
451 unsigned int eventq_read_ptr
;
454 unsigned int irq_count
;
455 unsigned int irq_mod_score
;
456 #ifdef CONFIG_RFS_ACCEL
457 unsigned int rfs_filters_added
;
460 unsigned n_rx_tobe_disc
;
461 unsigned n_rx_ip_hdr_chksum_err
;
462 unsigned n_rx_tcp_udp_chksum_err
;
463 unsigned n_rx_mcast_mismatch
;
464 unsigned n_rx_frm_trunc
;
465 unsigned n_rx_overlength
;
466 unsigned n_skbuff_leaks
;
467 unsigned int n_rx_nodesc_trunc
;
468 unsigned int n_rx_merge_events
;
469 unsigned int n_rx_merge_packets
;
471 unsigned int rx_pkt_n_frags
;
472 unsigned int rx_pkt_index
;
474 struct efx_rx_queue rx_queue
;
475 struct efx_tx_queue tx_queue
[EFX_TXQ_TYPES
];
477 enum efx_sync_events_state sync_events_state
;
478 u32 sync_timestamp_major
;
479 u32 sync_timestamp_minor
;
482 #ifdef CONFIG_NET_RX_BUSY_POLL
483 static inline void efx_channel_init_lock(struct efx_channel
*channel
)
485 spin_lock_init(&channel
->state_lock
);
488 /* Called from the device poll routine to get ownership of a channel. */
489 static inline bool efx_channel_lock_napi(struct efx_channel
*channel
)
493 spin_lock_bh(&channel
->state_lock
);
494 if (channel
->state
& EFX_CHANNEL_LOCKED
) {
495 WARN_ON(channel
->state
& EFX_CHANNEL_STATE_NAPI
);
496 channel
->state
|= EFX_CHANNEL_STATE_NAPI_YIELD
;
499 /* we don't care if someone yielded */
500 channel
->state
= EFX_CHANNEL_STATE_NAPI
;
502 spin_unlock_bh(&channel
->state_lock
);
506 static inline void efx_channel_unlock_napi(struct efx_channel
*channel
)
508 spin_lock_bh(&channel
->state_lock
);
509 WARN_ON(channel
->state
&
510 (EFX_CHANNEL_STATE_POLL
| EFX_CHANNEL_STATE_NAPI_YIELD
));
512 channel
->state
&= EFX_CHANNEL_STATE_DISABLED
;
513 spin_unlock_bh(&channel
->state_lock
);
516 /* Called from efx_busy_poll(). */
517 static inline bool efx_channel_lock_poll(struct efx_channel
*channel
)
521 spin_lock_bh(&channel
->state_lock
);
522 if ((channel
->state
& EFX_CHANNEL_LOCKED
)) {
523 channel
->state
|= EFX_CHANNEL_STATE_POLL_YIELD
;
526 /* preserve yield marks */
527 channel
->state
|= EFX_CHANNEL_STATE_POLL
;
529 spin_unlock_bh(&channel
->state_lock
);
533 /* Returns true if NAPI tried to get the channel while it was locked. */
534 static inline void efx_channel_unlock_poll(struct efx_channel
*channel
)
536 spin_lock_bh(&channel
->state_lock
);
537 WARN_ON(channel
->state
& EFX_CHANNEL_STATE_NAPI
);
539 /* will reset state to idle, unless channel is disabled */
540 channel
->state
&= EFX_CHANNEL_STATE_DISABLED
;
541 spin_unlock_bh(&channel
->state_lock
);
544 /* True if a socket is polling, even if it did not get the lock. */
545 static inline bool efx_channel_busy_polling(struct efx_channel
*channel
)
547 WARN_ON(!(channel
->state
& EFX_CHANNEL_OWNED
));
548 return channel
->state
& EFX_CHANNEL_USER_PEND
;
551 static inline void efx_channel_enable(struct efx_channel
*channel
)
553 spin_lock_bh(&channel
->state_lock
);
554 channel
->state
= EFX_CHANNEL_STATE_IDLE
;
555 spin_unlock_bh(&channel
->state_lock
);
558 /* False if the channel is currently owned. */
559 static inline bool efx_channel_disable(struct efx_channel
*channel
)
563 spin_lock_bh(&channel
->state_lock
);
564 if (channel
->state
& EFX_CHANNEL_OWNED
)
566 channel
->state
|= EFX_CHANNEL_STATE_DISABLED
;
567 spin_unlock_bh(&channel
->state_lock
);
572 #else /* CONFIG_NET_RX_BUSY_POLL */
574 static inline void efx_channel_init_lock(struct efx_channel
*channel
)
578 static inline bool efx_channel_lock_napi(struct efx_channel
*channel
)
583 static inline void efx_channel_unlock_napi(struct efx_channel
*channel
)
587 static inline bool efx_channel_lock_poll(struct efx_channel
*channel
)
592 static inline void efx_channel_unlock_poll(struct efx_channel
*channel
)
596 static inline bool efx_channel_busy_polling(struct efx_channel
*channel
)
601 static inline void efx_channel_enable(struct efx_channel
*channel
)
605 static inline bool efx_channel_disable(struct efx_channel
*channel
)
609 #endif /* CONFIG_NET_RX_BUSY_POLL */
612 * struct efx_msi_context - Context for each MSI
613 * @efx: The associated NIC
614 * @index: Index of the channel/IRQ
615 * @name: Name of the channel/IRQ
617 * Unlike &struct efx_channel, this is never reallocated and is always
618 * safe for the IRQ handler to access.
620 struct efx_msi_context
{
623 char name
[IFNAMSIZ
+ 6];
627 * struct efx_channel_type - distinguishes traffic and extra channels
628 * @handle_no_channel: Handle failure to allocate an extra channel
629 * @pre_probe: Set up extra state prior to initialisation
630 * @post_remove: Tear down extra state after finalisation, if allocated.
631 * May be called on channels that have not been probed.
632 * @get_name: Generate the channel's name (used for its IRQ handler)
633 * @copy: Copy the channel state prior to reallocation. May be %NULL if
634 * reallocation is not supported.
635 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
636 * @keep_eventq: Flag for whether event queue should be kept initialised
637 * while the device is stopped
639 struct efx_channel_type
{
640 void (*handle_no_channel
)(struct efx_nic
*);
641 int (*pre_probe
)(struct efx_channel
*);
642 void (*post_remove
)(struct efx_channel
*);
643 void (*get_name
)(struct efx_channel
*, char *buf
, size_t len
);
644 struct efx_channel
*(*copy
)(const struct efx_channel
*);
645 bool (*receive_skb
)(struct efx_channel
*, struct sk_buff
*);
655 #define STRING_TABLE_LOOKUP(val, member) \
656 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
658 extern const char *const efx_loopback_mode_names
[];
659 extern const unsigned int efx_loopback_mode_max
;
660 #define LOOPBACK_MODE(efx) \
661 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
663 extern const char *const efx_reset_type_names
[];
664 extern const unsigned int efx_reset_type_max
;
665 #define RESET_TYPE(type) \
666 STRING_TABLE_LOOKUP(type, efx_reset_type)
669 /* Be careful if altering to correct macro below */
670 EFX_INT_MODE_MSIX
= 0,
671 EFX_INT_MODE_MSI
= 1,
672 EFX_INT_MODE_LEGACY
= 2,
673 EFX_INT_MODE_MAX
/* Insert any new items before this */
675 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
678 STATE_UNINIT
= 0, /* device being probed/removed or is frozen */
679 STATE_READY
= 1, /* hardware ready and netdev registered */
680 STATE_DISABLED
= 2, /* device disabled due to hardware errors */
681 STATE_RECOVERY
= 3, /* device recovering from PCI error */
684 /* Forward declaration */
687 /* Pseudo bit-mask flow control field */
688 #define EFX_FC_RX FLOW_CTRL_RX
689 #define EFX_FC_TX FLOW_CTRL_TX
690 #define EFX_FC_AUTO 4
693 * struct efx_link_state - Current state of the link
695 * @fd: Link is full-duplex
696 * @fc: Actual flow control flags
697 * @speed: Link speed (Mbps)
699 struct efx_link_state
{
706 static inline bool efx_link_state_equal(const struct efx_link_state
*left
,
707 const struct efx_link_state
*right
)
709 return left
->up
== right
->up
&& left
->fd
== right
->fd
&&
710 left
->fc
== right
->fc
&& left
->speed
== right
->speed
;
714 * struct efx_phy_operations - Efx PHY operations table
715 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
716 * efx->loopback_modes.
717 * @init: Initialise PHY
718 * @fini: Shut down PHY
719 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
720 * @poll: Update @link_state and report whether it changed.
721 * Serialised by the mac_lock.
722 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
723 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
724 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
725 * (only needed where AN bit is set in mmds)
726 * @test_alive: Test that PHY is 'alive' (online)
727 * @test_name: Get the name of a PHY-specific test/result
728 * @run_tests: Run tests and record results as appropriate (offline).
729 * Flags are the ethtool tests flags.
731 struct efx_phy_operations
{
732 int (*probe
) (struct efx_nic
*efx
);
733 int (*init
) (struct efx_nic
*efx
);
734 void (*fini
) (struct efx_nic
*efx
);
735 void (*remove
) (struct efx_nic
*efx
);
736 int (*reconfigure
) (struct efx_nic
*efx
);
737 bool (*poll
) (struct efx_nic
*efx
);
738 void (*get_settings
) (struct efx_nic
*efx
,
739 struct ethtool_cmd
*ecmd
);
740 int (*set_settings
) (struct efx_nic
*efx
,
741 struct ethtool_cmd
*ecmd
);
742 void (*set_npage_adv
) (struct efx_nic
*efx
, u32
);
743 int (*test_alive
) (struct efx_nic
*efx
);
744 const char *(*test_name
) (struct efx_nic
*efx
, unsigned int index
);
745 int (*run_tests
) (struct efx_nic
*efx
, int *results
, unsigned flags
);
746 int (*get_module_eeprom
) (struct efx_nic
*efx
,
747 struct ethtool_eeprom
*ee
,
749 int (*get_module_info
) (struct efx_nic
*efx
,
750 struct ethtool_modinfo
*modinfo
);
754 * enum efx_phy_mode - PHY operating mode flags
755 * @PHY_MODE_NORMAL: on and should pass traffic
756 * @PHY_MODE_TX_DISABLED: on with TX disabled
757 * @PHY_MODE_LOW_POWER: set to low power through MDIO
758 * @PHY_MODE_OFF: switched off through external control
759 * @PHY_MODE_SPECIAL: on but will not pass traffic
763 PHY_MODE_TX_DISABLED
= 1,
764 PHY_MODE_LOW_POWER
= 2,
766 PHY_MODE_SPECIAL
= 8,
769 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode
)
771 return !!(mode
& ~PHY_MODE_TX_DISABLED
);
775 * struct efx_hw_stat_desc - Description of a hardware statistic
776 * @name: Name of the statistic as visible through ethtool, or %NULL if
777 * it should not be exposed
778 * @dma_width: Width in bits (0 for non-DMA statistics)
779 * @offset: Offset within stats (ignored for non-DMA statistics)
781 struct efx_hw_stat_desc
{
787 /* Number of bits used in a multicast filter hash address */
788 #define EFX_MCAST_HASH_BITS 8
790 /* Number of (single-bit) entries in a multicast filter hash */
791 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
793 /* An Efx multicast filter hash */
794 union efx_multicast_hash
{
795 u8 byte
[EFX_MCAST_HASH_ENTRIES
/ 8];
796 efx_oword_t oword
[EFX_MCAST_HASH_ENTRIES
/ sizeof(efx_oword_t
) / 8];
802 * struct efx_nic - an Efx NIC
803 * @name: Device name (net device name or bus id before net device registered)
804 * @pci_dev: The PCI device
805 * @node: List node for maintaning primary/secondary function lists
806 * @primary: &struct efx_nic instance for the primary function of this
807 * controller. May be the same structure, and may be %NULL if no
808 * primary function is bound. Serialised by rtnl_lock.
809 * @secondary_list: List of &struct efx_nic instances for the secondary PCI
810 * functions of the controller, if this is for the primary function.
811 * Serialised by rtnl_lock.
812 * @type: Controller type attributes
813 * @legacy_irq: IRQ number
814 * @workqueue: Workqueue for port reconfigures and the HW monitor.
815 * Work items do not hold and must not acquire RTNL.
816 * @workqueue_name: Name of workqueue
817 * @reset_work: Scheduled reset workitem
818 * @membase_phys: Memory BAR value as physical address
819 * @membase: Memory BAR value
820 * @interrupt_mode: Interrupt mode
821 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
822 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
823 * @irq_rx_moderation: IRQ moderation time for RX event queues
824 * @msg_enable: Log message enable flags
825 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
826 * @reset_pending: Bitmask for pending resets
827 * @tx_queue: TX DMA queues
828 * @rx_queue: RX DMA queues
830 * @msi_context: Context for each MSI
831 * @extra_channel_types: Types of extra (non-traffic) channels that
832 * should be allocated for this NIC
833 * @rxq_entries: Size of receive queues requested by user.
834 * @txq_entries: Size of transmit queues requested by user.
835 * @txq_stop_thresh: TX queue fill level at or above which we stop it.
836 * @txq_wake_thresh: TX queue fill level at or below which we wake it.
837 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
838 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
839 * @sram_lim_qw: Qword address limit of SRAM
840 * @next_buffer_table: First available buffer table id
841 * @n_channels: Number of channels in use
842 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
843 * @n_tx_channels: Number of channels used for TX
844 * @rx_ip_align: RX DMA address offset to have IP header aligned in
845 * in accordance with NET_IP_ALIGN
846 * @rx_dma_len: Current maximum RX DMA length
847 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
848 * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
849 * for use in sk_buff::truesize
850 * @rx_prefix_size: Size of RX prefix before packet data
851 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
852 * (valid only if @rx_prefix_size != 0; always negative)
853 * @rx_packet_len_offset: Offset of RX packet length from start of packet data
854 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
855 * @rx_packet_ts_offset: Offset of timestamp from start of packet data
856 * (valid only if channel->sync_timestamps_enabled; always negative)
857 * @rx_hash_key: Toeplitz hash key for RSS
858 * @rx_indir_table: Indirection table for RSS
859 * @rx_scatter: Scatter mode enabled for receives
860 * @int_error_count: Number of internal errors seen recently
861 * @int_error_expire: Time at which error count will be expired
862 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
863 * acknowledge but do nothing else.
864 * @irq_status: Interrupt status buffer
865 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
866 * @irq_level: IRQ level/index for IRQs not triggered by an event queue
867 * @selftest_work: Work item for asynchronous self-test
868 * @mtd_list: List of MTDs attached to the NIC
869 * @nic_data: Hardware dependent state
870 * @mcdi: Management-Controller-to-Driver Interface state
871 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
872 * efx_monitor() and efx_reconfigure_port()
873 * @port_enabled: Port enabled indicator.
874 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
875 * efx_mac_work() with kernel interfaces. Safe to read under any
876 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
877 * be held to modify it.
878 * @port_initialized: Port initialized?
879 * @net_dev: Operating system network device. Consider holding the rtnl lock
880 * @stats_buffer: DMA buffer for statistics
881 * @phy_type: PHY type
882 * @phy_op: PHY interface
883 * @phy_data: PHY private data (including PHY-specific stats)
884 * @mdio: PHY MDIO interface
885 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
886 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
887 * @link_advertising: Autonegotiation advertising flags
888 * @link_state: Current state of the link
889 * @n_link_state_changes: Number of times the link has changed state
890 * @unicast_filter: Flag for Falcon-arch simple unicast filter.
891 * Protected by @mac_lock.
892 * @multicast_hash: Multicast hash table for Falcon-arch.
893 * Protected by @mac_lock.
894 * @wanted_fc: Wanted flow control flags
895 * @fc_disable: When non-zero flow control is disabled. Typically used to
896 * ensure that network back pressure doesn't delay dma queue flushes.
897 * Serialised by the rtnl lock.
898 * @mac_work: Work item for changing MAC promiscuity and multicast hash
899 * @loopback_mode: Loopback status
900 * @loopback_modes: Supported loopback mode bitmask
901 * @loopback_selftest: Offline self-test private state
902 * @filter_sem: Filter table rw_semaphore, for freeing the table
903 * @filter_lock: Filter table lock, for mere content changes
904 * @filter_state: Architecture-dependent filter table state
905 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
906 * indexed by filter ID
907 * @rps_expire_index: Next index to check for expiry in @rps_flow_id
908 * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
909 * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
910 * Decremented when the efx_flush_rx_queue() is called.
911 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
912 * completed (either success or failure). Not used when MCDI is used to
913 * flush receive queues.
914 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
915 * @vf_count: Number of VFs intended to be enabled.
916 * @vf_init_count: Number of VFs that have been fully initialised.
917 * @vi_scale: log2 number of vnics per VF.
918 * @ptp_data: PTP state data
919 * @vpd_sn: Serial number read from VPD
920 * @monitor_work: Hardware monitor workitem
921 * @biu_lock: BIU (bus interface unit) lock
922 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This
923 * field is used by efx_test_interrupts() to verify that an
924 * interrupt has occurred.
925 * @stats_lock: Statistics update lock. Must be held when calling
926 * efx_nic_type::{update,start,stop}_stats.
927 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
929 * This is stored in the private area of the &struct net_device.
932 /* The following fields should be written very rarely */
935 struct list_head node
;
936 struct efx_nic
*primary
;
937 struct list_head secondary_list
;
938 struct pci_dev
*pci_dev
;
939 unsigned int port_num
;
940 const struct efx_nic_type
*type
;
942 bool eeh_disabled_legacy_irq
;
943 struct workqueue_struct
*workqueue
;
944 char workqueue_name
[16];
945 struct work_struct reset_work
;
946 resource_size_t membase_phys
;
947 void __iomem
*membase
;
949 enum efx_int_mode interrupt_mode
;
950 unsigned int timer_quantum_ns
;
951 bool irq_rx_adaptive
;
952 unsigned int irq_rx_moderation
;
955 enum nic_state state
;
956 unsigned long reset_pending
;
958 struct efx_channel
*channel
[EFX_MAX_CHANNELS
];
959 struct efx_msi_context msi_context
[EFX_MAX_CHANNELS
];
960 const struct efx_channel_type
*
961 extra_channel_type
[EFX_MAX_EXTRA_CHANNELS
];
963 unsigned rxq_entries
;
964 unsigned txq_entries
;
965 unsigned int txq_stop_thresh
;
966 unsigned int txq_wake_thresh
;
970 unsigned sram_lim_qw
;
971 unsigned next_buffer_table
;
973 unsigned int max_channels
;
975 unsigned n_rx_channels
;
977 unsigned tx_channel_offset
;
978 unsigned n_tx_channels
;
979 unsigned int rx_ip_align
;
980 unsigned int rx_dma_len
;
981 unsigned int rx_buffer_order
;
982 unsigned int rx_buffer_truesize
;
983 unsigned int rx_page_buf_step
;
984 unsigned int rx_bufs_per_page
;
985 unsigned int rx_pages_per_batch
;
986 unsigned int rx_prefix_size
;
987 int rx_packet_hash_offset
;
988 int rx_packet_len_offset
;
989 int rx_packet_ts_offset
;
991 u32 rx_indir_table
[128];
994 unsigned int_error_count
;
995 unsigned long int_error_expire
;
997 bool irq_soft_enabled
;
998 struct efx_buffer irq_status
;
999 unsigned irq_zero_count
;
1001 struct delayed_work selftest_work
;
1003 #ifdef CONFIG_SFC_MTD
1004 struct list_head mtd_list
;
1008 struct efx_mcdi_data
*mcdi
;
1010 struct mutex mac_lock
;
1011 struct work_struct mac_work
;
1014 bool mc_bist_for_other_fn
;
1015 bool port_initialized
;
1016 struct net_device
*net_dev
;
1018 struct efx_buffer stats_buffer
;
1019 u64 rx_nodesc_drops_total
;
1020 u64 rx_nodesc_drops_while_down
;
1021 bool rx_nodesc_drops_prev_state
;
1023 unsigned int phy_type
;
1024 const struct efx_phy_operations
*phy_op
;
1026 struct mdio_if_info mdio
;
1027 unsigned int mdio_bus
;
1028 enum efx_phy_mode phy_mode
;
1030 u32 link_advertising
;
1031 struct efx_link_state link_state
;
1032 unsigned int n_link_state_changes
;
1034 bool unicast_filter
;
1035 union efx_multicast_hash multicast_hash
;
1037 unsigned fc_disable
;
1040 enum efx_loopback_mode loopback_mode
;
1043 void *loopback_selftest
;
1045 struct rw_semaphore filter_sem
;
1046 spinlock_t filter_lock
;
1048 #ifdef CONFIG_RFS_ACCEL
1050 unsigned int rps_expire_index
;
1053 atomic_t active_queues
;
1054 atomic_t rxq_flush_pending
;
1055 atomic_t rxq_flush_outstanding
;
1056 wait_queue_head_t flush_wq
;
1058 #ifdef CONFIG_SFC_SRIOV
1060 unsigned vf_init_count
;
1064 struct efx_ptp_data
*ptp_data
;
1068 /* The following fields may be written more often */
1070 struct delayed_work monitor_work ____cacheline_aligned_in_smp
;
1071 spinlock_t biu_lock
;
1073 spinlock_t stats_lock
;
1074 atomic_t n_rx_noskb_drops
;
1077 static inline int efx_dev_registered(struct efx_nic
*efx
)
1079 return efx
->net_dev
->reg_state
== NETREG_REGISTERED
;
1082 static inline unsigned int efx_port_num(struct efx_nic
*efx
)
1084 return efx
->port_num
;
1087 struct efx_mtd_partition
{
1088 struct list_head node
;
1089 struct mtd_info mtd
;
1090 const char *dev_type_name
;
1091 const char *type_name
;
1092 char name
[IFNAMSIZ
+ 20];
1096 * struct efx_nic_type - Efx device type definition
1097 * @mem_bar: Get the memory BAR
1098 * @mem_map_size: Get memory BAR mapped size
1099 * @probe: Probe the controller
1100 * @remove: Free resources allocated by probe()
1101 * @init: Initialise the controller
1102 * @dimension_resources: Dimension controller resources (buffer table,
1103 * and VIs once the available interrupt resources are clear)
1104 * @fini: Shut down the controller
1105 * @monitor: Periodic function for polling link state and hardware monitor
1106 * @map_reset_reason: Map ethtool reset reason to a reset method
1107 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
1108 * @reset: Reset the controller hardware and possibly the PHY. This will
1109 * be called while the controller is uninitialised.
1110 * @probe_port: Probe the MAC and PHY
1111 * @remove_port: Free resources allocated by probe_port()
1112 * @handle_global_event: Handle a "global" event (may be %NULL)
1113 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1114 * @prepare_flush: Prepare the hardware for flushing the DMA queues
1115 * (for Falcon architecture)
1116 * @finish_flush: Clean up after flushing the DMA queues (for Falcon
1118 * @prepare_flr: Prepare for an FLR
1119 * @finish_flr: Clean up after an FLR
1120 * @describe_stats: Describe statistics for ethtool
1121 * @update_stats: Update statistics not provided by event handling.
1122 * Either argument may be %NULL.
1123 * @start_stats: Start the regular fetching of statistics
1124 * @pull_stats: Pull stats from the NIC and wait until they arrive.
1125 * @stop_stats: Stop the regular fetching of statistics
1126 * @set_id_led: Set state of identifying LED or revert to automatic function
1127 * @push_irq_moderation: Apply interrupt moderation value
1128 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
1129 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1130 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
1131 * to the hardware. Serialised by the mac_lock.
1132 * @check_mac_fault: Check MAC fault state. True if fault present.
1133 * @get_wol: Get WoL configuration from driver state
1134 * @set_wol: Push WoL configuration to the NIC
1135 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
1136 * @test_chip: Test registers. May use efx_farch_test_registers(), and is
1137 * expected to reset the NIC.
1138 * @test_nvram: Test validity of NVRAM contents
1139 * @mcdi_request: Send an MCDI request with the given header and SDU.
1140 * The SDU length may be any value from 0 up to the protocol-
1141 * defined maximum, but its buffer will be padded to a multiple
1143 * @mcdi_poll_response: Test whether an MCDI response is available.
1144 * @mcdi_read_response: Read the MCDI response PDU. The offset will
1145 * be a multiple of 4. The length may not be, but the buffer
1146 * will be padded so it is safe to round up.
1147 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so,
1148 * return an appropriate error code for aborting any current
1149 * request; otherwise return 0.
1150 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must
1151 * be separately enabled after this.
1152 * @irq_test_generate: Generate a test IRQ
1153 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
1154 * queue must be separately disabled before this.
1155 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is
1156 * a pointer to the &struct efx_msi_context for the channel.
1157 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument
1158 * is a pointer to the &struct efx_nic.
1159 * @tx_probe: Allocate resources for TX queue
1160 * @tx_init: Initialise TX queue on the NIC
1161 * @tx_remove: Free resources for TX queue
1162 * @tx_write: Write TX descriptors and doorbell
1163 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC
1164 * @rx_probe: Allocate resources for RX queue
1165 * @rx_init: Initialise RX queue on the NIC
1166 * @rx_remove: Free resources for RX queue
1167 * @rx_write: Write RX descriptors and doorbell
1168 * @rx_defer_refill: Generate a refill reminder event
1169 * @ev_probe: Allocate resources for event queue
1170 * @ev_init: Initialise event queue on the NIC
1171 * @ev_fini: Deinitialise event queue on the NIC
1172 * @ev_remove: Free resources for event queue
1173 * @ev_process: Process events for a queue, up to the given NAPI quota
1174 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1175 * @ev_test_generate: Generate a test event
1176 * @filter_table_probe: Probe filter capabilities and set up filter software state
1177 * @filter_table_restore: Restore filters removed from hardware
1178 * @filter_table_remove: Remove filters from hardware and tear down software state
1179 * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1180 * @filter_insert: add or replace a filter
1181 * @filter_remove_safe: remove a filter by ID, carefully
1182 * @filter_get_safe: retrieve a filter by ID, carefully
1183 * @filter_clear_rx: Remove all RX filters whose priority is less than or
1184 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO
1185 * @filter_count_rx_used: Get the number of filters in use at a given priority
1186 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
1187 * @filter_get_rx_ids: Get list of RX filters at a given priority
1188 * @filter_rfs_insert: Add or replace a filter for RFS. This must be
1189 * atomic. The hardware change may be asynchronous but should
1190 * not be delayed for long. It may fail if this can't be done
1192 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
1193 * This must check whether the specified table entry is used by RFS
1194 * and that rps_may_expire_flow() returns true for it.
1195 * @mtd_probe: Probe and add MTD partitions associated with this net device,
1196 * using efx_mtd_add()
1197 * @mtd_rename: Set an MTD partition name using the net device name
1198 * @mtd_read: Read from an MTD partition
1199 * @mtd_erase: Erase part of an MTD partition
1200 * @mtd_write: Write to an MTD partition
1201 * @mtd_sync: Wait for write-back to complete on MTD partition. This
1202 * also notifies the driver that a writer has finished using this
1204 * @ptp_write_host_time: Send host time to MC as part of sync protocol
1205 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1206 * timestamping, possibly only temporarily for the purposes of a reset.
1207 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags
1208 * and tx_type will already have been validated but this operation
1209 * must validate and update rx_filter.
1210 * @set_mac_address: Set the MAC address of the device
1211 * @revision: Hardware architecture revision
1212 * @txd_ptr_tbl_base: TX descriptor ring base address
1213 * @rxd_ptr_tbl_base: RX descriptor ring base address
1214 * @buf_tbl_base: Buffer table base address
1215 * @evq_ptr_tbl_base: Event queue pointer table base address
1216 * @evq_rptr_tbl_base: Event queue read-pointer table base address
1217 * @max_dma_mask: Maximum possible DMA mask
1218 * @rx_prefix_size: Size of RX prefix before packet data
1219 * @rx_hash_offset: Offset of RX flow hash within prefix
1220 * @rx_ts_offset: Offset of timestamp within prefix
1221 * @rx_buffer_padding: Size of padding at end of RX packet
1222 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
1223 * @always_rx_scatter: NIC will always scatter packets to multiple buffers
1224 * @max_interrupt_mode: Highest capability interrupt mode supported
1225 * from &enum efx_init_mode.
1226 * @timer_period_max: Maximum period of interrupt timer (in ticks)
1227 * @offload_features: net_device feature flags for protocol offload
1228 * features implemented in hardware
1229 * @mcdi_max_ver: Maximum MCDI version supported
1230 * @hwtstamp_filters: Mask of hardware timestamp filter types supported
1232 struct efx_nic_type
{
1234 unsigned int mem_bar
;
1235 unsigned int (*mem_map_size
)(struct efx_nic
*efx
);
1236 int (*probe
)(struct efx_nic
*efx
);
1237 void (*remove
)(struct efx_nic
*efx
);
1238 int (*init
)(struct efx_nic
*efx
);
1239 int (*dimension_resources
)(struct efx_nic
*efx
);
1240 void (*fini
)(struct efx_nic
*efx
);
1241 void (*monitor
)(struct efx_nic
*efx
);
1242 enum reset_type (*map_reset_reason
)(enum reset_type reason
);
1243 int (*map_reset_flags
)(u32
*flags
);
1244 int (*reset
)(struct efx_nic
*efx
, enum reset_type method
);
1245 int (*probe_port
)(struct efx_nic
*efx
);
1246 void (*remove_port
)(struct efx_nic
*efx
);
1247 bool (*handle_global_event
)(struct efx_channel
*channel
, efx_qword_t
*);
1248 int (*fini_dmaq
)(struct efx_nic
*efx
);
1249 void (*prepare_flush
)(struct efx_nic
*efx
);
1250 void (*finish_flush
)(struct efx_nic
*efx
);
1251 void (*prepare_flr
)(struct efx_nic
*efx
);
1252 void (*finish_flr
)(struct efx_nic
*efx
);
1253 size_t (*describe_stats
)(struct efx_nic
*efx
, u8
*names
);
1254 size_t (*update_stats
)(struct efx_nic
*efx
, u64
*full_stats
,
1255 struct rtnl_link_stats64
*core_stats
);
1256 void (*start_stats
)(struct efx_nic
*efx
);
1257 void (*pull_stats
)(struct efx_nic
*efx
);
1258 void (*stop_stats
)(struct efx_nic
*efx
);
1259 void (*set_id_led
)(struct efx_nic
*efx
, enum efx_led_mode mode
);
1260 void (*push_irq_moderation
)(struct efx_channel
*channel
);
1261 int (*reconfigure_port
)(struct efx_nic
*efx
);
1262 void (*prepare_enable_fc_tx
)(struct efx_nic
*efx
);
1263 int (*reconfigure_mac
)(struct efx_nic
*efx
);
1264 bool (*check_mac_fault
)(struct efx_nic
*efx
);
1265 void (*get_wol
)(struct efx_nic
*efx
, struct ethtool_wolinfo
*wol
);
1266 int (*set_wol
)(struct efx_nic
*efx
, u32 type
);
1267 void (*resume_wol
)(struct efx_nic
*efx
);
1268 int (*test_chip
)(struct efx_nic
*efx
, struct efx_self_tests
*tests
);
1269 int (*test_nvram
)(struct efx_nic
*efx
);
1270 void (*mcdi_request
)(struct efx_nic
*efx
,
1271 const efx_dword_t
*hdr
, size_t hdr_len
,
1272 const efx_dword_t
*sdu
, size_t sdu_len
);
1273 bool (*mcdi_poll_response
)(struct efx_nic
*efx
);
1274 void (*mcdi_read_response
)(struct efx_nic
*efx
, efx_dword_t
*pdu
,
1275 size_t pdu_offset
, size_t pdu_len
);
1276 int (*mcdi_poll_reboot
)(struct efx_nic
*efx
);
1277 void (*irq_enable_master
)(struct efx_nic
*efx
);
1278 void (*irq_test_generate
)(struct efx_nic
*efx
);
1279 void (*irq_disable_non_ev
)(struct efx_nic
*efx
);
1280 irqreturn_t (*irq_handle_msi
)(int irq
, void *dev_id
);
1281 irqreturn_t (*irq_handle_legacy
)(int irq
, void *dev_id
);
1282 int (*tx_probe
)(struct efx_tx_queue
*tx_queue
);
1283 void (*tx_init
)(struct efx_tx_queue
*tx_queue
);
1284 void (*tx_remove
)(struct efx_tx_queue
*tx_queue
);
1285 void (*tx_write
)(struct efx_tx_queue
*tx_queue
);
1286 int (*rx_push_rss_config
)(struct efx_nic
*efx
, bool user
,
1287 const u32
*rx_indir_table
);
1288 int (*rx_probe
)(struct efx_rx_queue
*rx_queue
);
1289 void (*rx_init
)(struct efx_rx_queue
*rx_queue
);
1290 void (*rx_remove
)(struct efx_rx_queue
*rx_queue
);
1291 void (*rx_write
)(struct efx_rx_queue
*rx_queue
);
1292 void (*rx_defer_refill
)(struct efx_rx_queue
*rx_queue
);
1293 int (*ev_probe
)(struct efx_channel
*channel
);
1294 int (*ev_init
)(struct efx_channel
*channel
);
1295 void (*ev_fini
)(struct efx_channel
*channel
);
1296 void (*ev_remove
)(struct efx_channel
*channel
);
1297 int (*ev_process
)(struct efx_channel
*channel
, int quota
);
1298 void (*ev_read_ack
)(struct efx_channel
*channel
);
1299 void (*ev_test_generate
)(struct efx_channel
*channel
);
1300 int (*filter_table_probe
)(struct efx_nic
*efx
);
1301 void (*filter_table_restore
)(struct efx_nic
*efx
);
1302 void (*filter_table_remove
)(struct efx_nic
*efx
);
1303 void (*filter_update_rx_scatter
)(struct efx_nic
*efx
);
1304 s32 (*filter_insert
)(struct efx_nic
*efx
,
1305 struct efx_filter_spec
*spec
, bool replace
);
1306 int (*filter_remove_safe
)(struct efx_nic
*efx
,
1307 enum efx_filter_priority priority
,
1309 int (*filter_get_safe
)(struct efx_nic
*efx
,
1310 enum efx_filter_priority priority
,
1311 u32 filter_id
, struct efx_filter_spec
*);
1312 int (*filter_clear_rx
)(struct efx_nic
*efx
,
1313 enum efx_filter_priority priority
);
1314 u32 (*filter_count_rx_used
)(struct efx_nic
*efx
,
1315 enum efx_filter_priority priority
);
1316 u32 (*filter_get_rx_id_limit
)(struct efx_nic
*efx
);
1317 s32 (*filter_get_rx_ids
)(struct efx_nic
*efx
,
1318 enum efx_filter_priority priority
,
1319 u32
*buf
, u32 size
);
1320 #ifdef CONFIG_RFS_ACCEL
1321 s32 (*filter_rfs_insert
)(struct efx_nic
*efx
,
1322 struct efx_filter_spec
*spec
);
1323 bool (*filter_rfs_expire_one
)(struct efx_nic
*efx
, u32 flow_id
,
1324 unsigned int index
);
1326 #ifdef CONFIG_SFC_MTD
1327 int (*mtd_probe
)(struct efx_nic
*efx
);
1328 void (*mtd_rename
)(struct efx_mtd_partition
*part
);
1329 int (*mtd_read
)(struct mtd_info
*mtd
, loff_t start
, size_t len
,
1330 size_t *retlen
, u8
*buffer
);
1331 int (*mtd_erase
)(struct mtd_info
*mtd
, loff_t start
, size_t len
);
1332 int (*mtd_write
)(struct mtd_info
*mtd
, loff_t start
, size_t len
,
1333 size_t *retlen
, const u8
*buffer
);
1334 int (*mtd_sync
)(struct mtd_info
*mtd
);
1336 void (*ptp_write_host_time
)(struct efx_nic
*efx
, u32 host_time
);
1337 int (*ptp_set_ts_sync_events
)(struct efx_nic
*efx
, bool en
, bool temp
);
1338 int (*ptp_set_ts_config
)(struct efx_nic
*efx
,
1339 struct hwtstamp_config
*init
);
1340 int (*sriov_configure
)(struct efx_nic
*efx
, int num_vfs
);
1341 int (*sriov_init
)(struct efx_nic
*efx
);
1342 void (*sriov_fini
)(struct efx_nic
*efx
);
1343 bool (*sriov_wanted
)(struct efx_nic
*efx
);
1344 void (*sriov_reset
)(struct efx_nic
*efx
);
1345 void (*sriov_flr
)(struct efx_nic
*efx
, unsigned vf_i
);
1346 int (*sriov_set_vf_mac
)(struct efx_nic
*efx
, int vf_i
, u8
*mac
);
1347 int (*sriov_set_vf_vlan
)(struct efx_nic
*efx
, int vf_i
, u16 vlan
,
1349 int (*sriov_set_vf_spoofchk
)(struct efx_nic
*efx
, int vf_i
,
1351 int (*sriov_get_vf_config
)(struct efx_nic
*efx
, int vf_i
,
1352 struct ifla_vf_info
*ivi
);
1353 int (*sriov_set_vf_link_state
)(struct efx_nic
*efx
, int vf_i
,
1355 int (*sriov_get_phys_port_id
)(struct efx_nic
*efx
,
1356 struct netdev_phys_item_id
*ppid
);
1357 int (*vswitching_probe
)(struct efx_nic
*efx
);
1358 int (*vswitching_restore
)(struct efx_nic
*efx
);
1359 void (*vswitching_remove
)(struct efx_nic
*efx
);
1360 int (*get_mac_address
)(struct efx_nic
*efx
, unsigned char *perm_addr
);
1361 int (*set_mac_address
)(struct efx_nic
*efx
);
1364 unsigned int txd_ptr_tbl_base
;
1365 unsigned int rxd_ptr_tbl_base
;
1366 unsigned int buf_tbl_base
;
1367 unsigned int evq_ptr_tbl_base
;
1368 unsigned int evq_rptr_tbl_base
;
1370 unsigned int rx_prefix_size
;
1371 unsigned int rx_hash_offset
;
1372 unsigned int rx_ts_offset
;
1373 unsigned int rx_buffer_padding
;
1374 bool can_rx_scatter
;
1375 bool always_rx_scatter
;
1376 unsigned int max_interrupt_mode
;
1377 unsigned int timer_period_max
;
1378 netdev_features_t offload_features
;
1380 unsigned int max_rx_ip_filters
;
1381 u32 hwtstamp_filters
;
1384 /**************************************************************************
1386 * Prototypes and inline functions
1388 *************************************************************************/
1390 static inline struct efx_channel
*
1391 efx_get_channel(struct efx_nic
*efx
, unsigned index
)
1393 EFX_BUG_ON_PARANOID(index
>= efx
->n_channels
);
1394 return efx
->channel
[index
];
1397 /* Iterate over all used channels */
1398 #define efx_for_each_channel(_channel, _efx) \
1399 for (_channel = (_efx)->channel[0]; \
1401 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
1402 (_efx)->channel[_channel->channel + 1] : NULL)
1404 /* Iterate over all used channels in reverse */
1405 #define efx_for_each_channel_rev(_channel, _efx) \
1406 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
1408 _channel = _channel->channel ? \
1409 (_efx)->channel[_channel->channel - 1] : NULL)
1411 static inline struct efx_tx_queue
*
1412 efx_get_tx_queue(struct efx_nic
*efx
, unsigned index
, unsigned type
)
1414 EFX_BUG_ON_PARANOID(index
>= efx
->n_tx_channels
||
1415 type
>= EFX_TXQ_TYPES
);
1416 return &efx
->channel
[efx
->tx_channel_offset
+ index
]->tx_queue
[type
];
1419 static inline bool efx_channel_has_tx_queues(struct efx_channel
*channel
)
1421 return channel
->channel
- channel
->efx
->tx_channel_offset
<
1422 channel
->efx
->n_tx_channels
;
1425 static inline struct efx_tx_queue
*
1426 efx_channel_get_tx_queue(struct efx_channel
*channel
, unsigned type
)
1428 EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel
) ||
1429 type
>= EFX_TXQ_TYPES
);
1430 return &channel
->tx_queue
[type
];
1433 static inline bool efx_tx_queue_used(struct efx_tx_queue
*tx_queue
)
1435 return !(tx_queue
->efx
->net_dev
->num_tc
< 2 &&
1436 tx_queue
->queue
& EFX_TXQ_TYPE_HIGHPRI
);
1439 /* Iterate over all TX queues belonging to a channel */
1440 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
1441 if (!efx_channel_has_tx_queues(_channel)) \
1444 for (_tx_queue = (_channel)->tx_queue; \
1445 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
1446 efx_tx_queue_used(_tx_queue); \
1449 /* Iterate over all possible TX queues belonging to a channel */
1450 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \
1451 if (!efx_channel_has_tx_queues(_channel)) \
1454 for (_tx_queue = (_channel)->tx_queue; \
1455 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
1458 static inline bool efx_channel_has_rx_queue(struct efx_channel
*channel
)
1460 return channel
->rx_queue
.core_index
>= 0;
1463 static inline struct efx_rx_queue
*
1464 efx_channel_get_rx_queue(struct efx_channel
*channel
)
1466 EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel
));
1467 return &channel
->rx_queue
;
1470 /* Iterate over all RX queues belonging to a channel */
1471 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
1472 if (!efx_channel_has_rx_queue(_channel)) \
1475 for (_rx_queue = &(_channel)->rx_queue; \
1479 static inline struct efx_channel
*
1480 efx_rx_queue_channel(struct efx_rx_queue
*rx_queue
)
1482 return container_of(rx_queue
, struct efx_channel
, rx_queue
);
1485 static inline int efx_rx_queue_index(struct efx_rx_queue
*rx_queue
)
1487 return efx_rx_queue_channel(rx_queue
)->channel
;
1490 /* Returns a pointer to the specified receive buffer in the RX
1493 static inline struct efx_rx_buffer
*efx_rx_buffer(struct efx_rx_queue
*rx_queue
,
1496 return &rx_queue
->buffer
[index
];
1500 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1502 * This calculates the maximum frame length that will be used for a
1503 * given MTU. The frame length will be equal to the MTU plus a
1504 * constant amount of header space and padding. This is the quantity
1505 * that the net driver will program into the MAC as the maximum frame
1508 * The 10G MAC requires 8-byte alignment on the frame
1509 * length, so we round up to the nearest 8.
1511 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1512 * XGMII cycle). If the frame length reaches the maximum value in the
1513 * same cycle, the XMAC can miss the IPG altogether. We work around
1514 * this by adding a further 16 bytes.
1516 #define EFX_MAX_FRAME_LEN(mtu) \
1517 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
1519 static inline bool efx_xmit_with_hwtstamp(struct sk_buff
*skb
)
1521 return skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
;
1523 static inline void efx_xmit_hwtstamp_pending(struct sk_buff
*skb
)
1525 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
1528 #endif /* EFX_NET_DRIVER_H */