2 * dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
4 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
6 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/stmmac.h>
20 #include <linux/bitops.h>
21 #include <linux/clk.h>
22 #include <linux/phy.h>
23 #include <linux/of_net.h>
24 #include <linux/gpio.h>
25 #include <linux/module.h>
26 #include <linux/of_gpio.h>
27 #include <linux/of_device.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/delay.h>
31 #include <linux/mfd/syscon.h>
32 #include <linux/regmap.h>
33 #include <linux/pm_runtime.h>
35 #include "stmmac_platform.h"
39 void (*set_to_rgmii
)(struct rk_priv_data
*bsp_priv
,
40 int tx_delay
, int rx_delay
);
41 void (*set_to_rmii
)(struct rk_priv_data
*bsp_priv
);
42 void (*set_rgmii_speed
)(struct rk_priv_data
*bsp_priv
, int speed
);
43 void (*set_rmii_speed
)(struct rk_priv_data
*bsp_priv
, int speed
);
47 struct platform_device
*pdev
;
49 struct regulator
*regulator
;
51 const struct rk_gmac_ops
*ops
;
57 struct clk
*gmac_clkin
;
58 struct clk
*mac_clk_rx
;
59 struct clk
*mac_clk_tx
;
60 struct clk
*clk_mac_ref
;
61 struct clk
*clk_mac_refout
;
71 #define HIWORD_UPDATE(val, mask, shift) \
72 ((val) << (shift) | (mask) << ((shift) + 16))
74 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
75 #define GRF_CLR_BIT(nr) (BIT(nr+16))
77 #define RK3228_GRF_MAC_CON0 0x0900
78 #define RK3228_GRF_MAC_CON1 0x0904
80 /* RK3228_GRF_MAC_CON0 */
81 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
82 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
84 /* RK3228_GRF_MAC_CON1 */
85 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \
86 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
87 #define RK3228_GMAC_PHY_INTF_SEL_RMII \
88 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
89 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
90 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
91 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
92 #define RK3228_GMAC_SPEED_100M GRF_BIT(2)
93 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
94 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
95 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
96 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9))
97 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9))
98 #define RK3228_GMAC_RMII_MODE GRF_BIT(10)
99 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
100 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
101 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
102 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
103 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
105 static void rk3228_set_to_rgmii(struct rk_priv_data
*bsp_priv
,
106 int tx_delay
, int rx_delay
)
108 struct device
*dev
= &bsp_priv
->pdev
->dev
;
110 if (IS_ERR(bsp_priv
->grf
)) {
111 dev_err(dev
, "Missing rockchip,grf property\n");
115 regmap_write(bsp_priv
->grf
, RK3228_GRF_MAC_CON1
,
116 RK3228_GMAC_PHY_INTF_SEL_RGMII
|
117 RK3228_GMAC_RMII_MODE_CLR
|
118 RK3228_GMAC_RXCLK_DLY_ENABLE
|
119 RK3228_GMAC_TXCLK_DLY_ENABLE
);
121 regmap_write(bsp_priv
->grf
, RK3228_GRF_MAC_CON0
,
122 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay
) |
123 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay
));
126 static void rk3228_set_to_rmii(struct rk_priv_data
*bsp_priv
)
128 struct device
*dev
= &bsp_priv
->pdev
->dev
;
130 if (IS_ERR(bsp_priv
->grf
)) {
131 dev_err(dev
, "Missing rockchip,grf property\n");
135 regmap_write(bsp_priv
->grf
, RK3228_GRF_MAC_CON1
,
136 RK3228_GMAC_PHY_INTF_SEL_RMII
|
137 RK3228_GMAC_RMII_MODE
);
139 /* set MAC to RMII mode */
140 regmap_write(bsp_priv
->grf
, RK3228_GRF_MAC_CON1
, GRF_BIT(11));
143 static void rk3228_set_rgmii_speed(struct rk_priv_data
*bsp_priv
, int speed
)
145 struct device
*dev
= &bsp_priv
->pdev
->dev
;
147 if (IS_ERR(bsp_priv
->grf
)) {
148 dev_err(dev
, "Missing rockchip,grf property\n");
153 regmap_write(bsp_priv
->grf
, RK3228_GRF_MAC_CON1
,
154 RK3228_GMAC_CLK_2_5M
);
155 else if (speed
== 100)
156 regmap_write(bsp_priv
->grf
, RK3228_GRF_MAC_CON1
,
157 RK3228_GMAC_CLK_25M
);
158 else if (speed
== 1000)
159 regmap_write(bsp_priv
->grf
, RK3228_GRF_MAC_CON1
,
160 RK3228_GMAC_CLK_125M
);
162 dev_err(dev
, "unknown speed value for RGMII! speed=%d", speed
);
165 static void rk3228_set_rmii_speed(struct rk_priv_data
*bsp_priv
, int speed
)
167 struct device
*dev
= &bsp_priv
->pdev
->dev
;
169 if (IS_ERR(bsp_priv
->grf
)) {
170 dev_err(dev
, "Missing rockchip,grf property\n");
175 regmap_write(bsp_priv
->grf
, RK3228_GRF_MAC_CON1
,
176 RK3228_GMAC_RMII_CLK_2_5M
|
177 RK3228_GMAC_SPEED_10M
);
178 else if (speed
== 100)
179 regmap_write(bsp_priv
->grf
, RK3228_GRF_MAC_CON1
,
180 RK3228_GMAC_RMII_CLK_25M
|
181 RK3228_GMAC_SPEED_100M
);
183 dev_err(dev
, "unknown speed value for RMII! speed=%d", speed
);
186 static const struct rk_gmac_ops rk3228_ops
= {
187 .set_to_rgmii
= rk3228_set_to_rgmii
,
188 .set_to_rmii
= rk3228_set_to_rmii
,
189 .set_rgmii_speed
= rk3228_set_rgmii_speed
,
190 .set_rmii_speed
= rk3228_set_rmii_speed
,
193 #define RK3288_GRF_SOC_CON1 0x0248
194 #define RK3288_GRF_SOC_CON3 0x0250
196 /*RK3288_GRF_SOC_CON1*/
197 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \
199 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
201 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
202 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
203 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
204 #define RK3288_GMAC_SPEED_100M GRF_BIT(10)
205 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
206 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
207 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
208 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
209 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
210 #define RK3288_GMAC_RMII_MODE GRF_BIT(14)
211 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
213 /*RK3288_GRF_SOC_CON3*/
214 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
215 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
216 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
217 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
218 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
219 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
221 static void rk3288_set_to_rgmii(struct rk_priv_data
*bsp_priv
,
222 int tx_delay
, int rx_delay
)
224 struct device
*dev
= &bsp_priv
->pdev
->dev
;
226 if (IS_ERR(bsp_priv
->grf
)) {
227 dev_err(dev
, "Missing rockchip,grf property\n");
231 regmap_write(bsp_priv
->grf
, RK3288_GRF_SOC_CON1
,
232 RK3288_GMAC_PHY_INTF_SEL_RGMII
|
233 RK3288_GMAC_RMII_MODE_CLR
);
234 regmap_write(bsp_priv
->grf
, RK3288_GRF_SOC_CON3
,
235 RK3288_GMAC_RXCLK_DLY_ENABLE
|
236 RK3288_GMAC_TXCLK_DLY_ENABLE
|
237 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay
) |
238 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay
));
241 static void rk3288_set_to_rmii(struct rk_priv_data
*bsp_priv
)
243 struct device
*dev
= &bsp_priv
->pdev
->dev
;
245 if (IS_ERR(bsp_priv
->grf
)) {
246 dev_err(dev
, "Missing rockchip,grf property\n");
250 regmap_write(bsp_priv
->grf
, RK3288_GRF_SOC_CON1
,
251 RK3288_GMAC_PHY_INTF_SEL_RMII
| RK3288_GMAC_RMII_MODE
);
254 static void rk3288_set_rgmii_speed(struct rk_priv_data
*bsp_priv
, int speed
)
256 struct device
*dev
= &bsp_priv
->pdev
->dev
;
258 if (IS_ERR(bsp_priv
->grf
)) {
259 dev_err(dev
, "Missing rockchip,grf property\n");
264 regmap_write(bsp_priv
->grf
, RK3288_GRF_SOC_CON1
,
265 RK3288_GMAC_CLK_2_5M
);
266 else if (speed
== 100)
267 regmap_write(bsp_priv
->grf
, RK3288_GRF_SOC_CON1
,
268 RK3288_GMAC_CLK_25M
);
269 else if (speed
== 1000)
270 regmap_write(bsp_priv
->grf
, RK3288_GRF_SOC_CON1
,
271 RK3288_GMAC_CLK_125M
);
273 dev_err(dev
, "unknown speed value for RGMII! speed=%d", speed
);
276 static void rk3288_set_rmii_speed(struct rk_priv_data
*bsp_priv
, int speed
)
278 struct device
*dev
= &bsp_priv
->pdev
->dev
;
280 if (IS_ERR(bsp_priv
->grf
)) {
281 dev_err(dev
, "Missing rockchip,grf property\n");
286 regmap_write(bsp_priv
->grf
, RK3288_GRF_SOC_CON1
,
287 RK3288_GMAC_RMII_CLK_2_5M
|
288 RK3288_GMAC_SPEED_10M
);
289 } else if (speed
== 100) {
290 regmap_write(bsp_priv
->grf
, RK3288_GRF_SOC_CON1
,
291 RK3288_GMAC_RMII_CLK_25M
|
292 RK3288_GMAC_SPEED_100M
);
294 dev_err(dev
, "unknown speed value for RMII! speed=%d", speed
);
298 static const struct rk_gmac_ops rk3288_ops
= {
299 .set_to_rgmii
= rk3288_set_to_rgmii
,
300 .set_to_rmii
= rk3288_set_to_rmii
,
301 .set_rgmii_speed
= rk3288_set_rgmii_speed
,
302 .set_rmii_speed
= rk3288_set_rmii_speed
,
305 #define RK3366_GRF_SOC_CON6 0x0418
306 #define RK3366_GRF_SOC_CON7 0x041c
308 /* RK3366_GRF_SOC_CON6 */
309 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
311 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
313 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
314 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
315 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
316 #define RK3366_GMAC_SPEED_100M GRF_BIT(7)
317 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
318 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
319 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
320 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
321 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
322 #define RK3366_GMAC_RMII_MODE GRF_BIT(6)
323 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
325 /* RK3366_GRF_SOC_CON7 */
326 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
327 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
328 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
329 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
330 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
331 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
333 static void rk3366_set_to_rgmii(struct rk_priv_data
*bsp_priv
,
334 int tx_delay
, int rx_delay
)
336 struct device
*dev
= &bsp_priv
->pdev
->dev
;
338 if (IS_ERR(bsp_priv
->grf
)) {
339 dev_err(dev
, "%s: Missing rockchip,grf property\n", __func__
);
343 regmap_write(bsp_priv
->grf
, RK3366_GRF_SOC_CON6
,
344 RK3366_GMAC_PHY_INTF_SEL_RGMII
|
345 RK3366_GMAC_RMII_MODE_CLR
);
346 regmap_write(bsp_priv
->grf
, RK3366_GRF_SOC_CON7
,
347 RK3366_GMAC_RXCLK_DLY_ENABLE
|
348 RK3366_GMAC_TXCLK_DLY_ENABLE
|
349 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay
) |
350 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay
));
353 static void rk3366_set_to_rmii(struct rk_priv_data
*bsp_priv
)
355 struct device
*dev
= &bsp_priv
->pdev
->dev
;
357 if (IS_ERR(bsp_priv
->grf
)) {
358 dev_err(dev
, "%s: Missing rockchip,grf property\n", __func__
);
362 regmap_write(bsp_priv
->grf
, RK3366_GRF_SOC_CON6
,
363 RK3366_GMAC_PHY_INTF_SEL_RMII
| RK3366_GMAC_RMII_MODE
);
366 static void rk3366_set_rgmii_speed(struct rk_priv_data
*bsp_priv
, int speed
)
368 struct device
*dev
= &bsp_priv
->pdev
->dev
;
370 if (IS_ERR(bsp_priv
->grf
)) {
371 dev_err(dev
, "%s: Missing rockchip,grf property\n", __func__
);
376 regmap_write(bsp_priv
->grf
, RK3366_GRF_SOC_CON6
,
377 RK3366_GMAC_CLK_2_5M
);
378 else if (speed
== 100)
379 regmap_write(bsp_priv
->grf
, RK3366_GRF_SOC_CON6
,
380 RK3366_GMAC_CLK_25M
);
381 else if (speed
== 1000)
382 regmap_write(bsp_priv
->grf
, RK3366_GRF_SOC_CON6
,
383 RK3366_GMAC_CLK_125M
);
385 dev_err(dev
, "unknown speed value for RGMII! speed=%d", speed
);
388 static void rk3366_set_rmii_speed(struct rk_priv_data
*bsp_priv
, int speed
)
390 struct device
*dev
= &bsp_priv
->pdev
->dev
;
392 if (IS_ERR(bsp_priv
->grf
)) {
393 dev_err(dev
, "%s: Missing rockchip,grf property\n", __func__
);
398 regmap_write(bsp_priv
->grf
, RK3366_GRF_SOC_CON6
,
399 RK3366_GMAC_RMII_CLK_2_5M
|
400 RK3366_GMAC_SPEED_10M
);
401 } else if (speed
== 100) {
402 regmap_write(bsp_priv
->grf
, RK3366_GRF_SOC_CON6
,
403 RK3366_GMAC_RMII_CLK_25M
|
404 RK3366_GMAC_SPEED_100M
);
406 dev_err(dev
, "unknown speed value for RMII! speed=%d", speed
);
410 static const struct rk_gmac_ops rk3366_ops
= {
411 .set_to_rgmii
= rk3366_set_to_rgmii
,
412 .set_to_rmii
= rk3366_set_to_rmii
,
413 .set_rgmii_speed
= rk3366_set_rgmii_speed
,
414 .set_rmii_speed
= rk3366_set_rmii_speed
,
417 #define RK3368_GRF_SOC_CON15 0x043c
418 #define RK3368_GRF_SOC_CON16 0x0440
420 /* RK3368_GRF_SOC_CON15 */
421 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
423 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
425 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
426 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
427 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
428 #define RK3368_GMAC_SPEED_100M GRF_BIT(7)
429 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
430 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
431 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
432 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
433 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
434 #define RK3368_GMAC_RMII_MODE GRF_BIT(6)
435 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
437 /* RK3368_GRF_SOC_CON16 */
438 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
439 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
440 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
441 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
442 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
443 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
445 static void rk3368_set_to_rgmii(struct rk_priv_data
*bsp_priv
,
446 int tx_delay
, int rx_delay
)
448 struct device
*dev
= &bsp_priv
->pdev
->dev
;
450 if (IS_ERR(bsp_priv
->grf
)) {
451 dev_err(dev
, "%s: Missing rockchip,grf property\n", __func__
);
455 regmap_write(bsp_priv
->grf
, RK3368_GRF_SOC_CON15
,
456 RK3368_GMAC_PHY_INTF_SEL_RGMII
|
457 RK3368_GMAC_RMII_MODE_CLR
);
458 regmap_write(bsp_priv
->grf
, RK3368_GRF_SOC_CON16
,
459 RK3368_GMAC_RXCLK_DLY_ENABLE
|
460 RK3368_GMAC_TXCLK_DLY_ENABLE
|
461 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay
) |
462 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay
));
465 static void rk3368_set_to_rmii(struct rk_priv_data
*bsp_priv
)
467 struct device
*dev
= &bsp_priv
->pdev
->dev
;
469 if (IS_ERR(bsp_priv
->grf
)) {
470 dev_err(dev
, "%s: Missing rockchip,grf property\n", __func__
);
474 regmap_write(bsp_priv
->grf
, RK3368_GRF_SOC_CON15
,
475 RK3368_GMAC_PHY_INTF_SEL_RMII
| RK3368_GMAC_RMII_MODE
);
478 static void rk3368_set_rgmii_speed(struct rk_priv_data
*bsp_priv
, int speed
)
480 struct device
*dev
= &bsp_priv
->pdev
->dev
;
482 if (IS_ERR(bsp_priv
->grf
)) {
483 dev_err(dev
, "%s: Missing rockchip,grf property\n", __func__
);
488 regmap_write(bsp_priv
->grf
, RK3368_GRF_SOC_CON15
,
489 RK3368_GMAC_CLK_2_5M
);
490 else if (speed
== 100)
491 regmap_write(bsp_priv
->grf
, RK3368_GRF_SOC_CON15
,
492 RK3368_GMAC_CLK_25M
);
493 else if (speed
== 1000)
494 regmap_write(bsp_priv
->grf
, RK3368_GRF_SOC_CON15
,
495 RK3368_GMAC_CLK_125M
);
497 dev_err(dev
, "unknown speed value for RGMII! speed=%d", speed
);
500 static void rk3368_set_rmii_speed(struct rk_priv_data
*bsp_priv
, int speed
)
502 struct device
*dev
= &bsp_priv
->pdev
->dev
;
504 if (IS_ERR(bsp_priv
->grf
)) {
505 dev_err(dev
, "%s: Missing rockchip,grf property\n", __func__
);
510 regmap_write(bsp_priv
->grf
, RK3368_GRF_SOC_CON15
,
511 RK3368_GMAC_RMII_CLK_2_5M
|
512 RK3368_GMAC_SPEED_10M
);
513 } else if (speed
== 100) {
514 regmap_write(bsp_priv
->grf
, RK3368_GRF_SOC_CON15
,
515 RK3368_GMAC_RMII_CLK_25M
|
516 RK3368_GMAC_SPEED_100M
);
518 dev_err(dev
, "unknown speed value for RMII! speed=%d", speed
);
522 static const struct rk_gmac_ops rk3368_ops
= {
523 .set_to_rgmii
= rk3368_set_to_rgmii
,
524 .set_to_rmii
= rk3368_set_to_rmii
,
525 .set_rgmii_speed
= rk3368_set_rgmii_speed
,
526 .set_rmii_speed
= rk3368_set_rmii_speed
,
529 #define RK3399_GRF_SOC_CON5 0xc214
530 #define RK3399_GRF_SOC_CON6 0xc218
532 /* RK3399_GRF_SOC_CON5 */
533 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
535 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
537 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
538 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
539 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
540 #define RK3399_GMAC_SPEED_100M GRF_BIT(7)
541 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
542 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
543 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
544 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
545 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
546 #define RK3399_GMAC_RMII_MODE GRF_BIT(6)
547 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
549 /* RK3399_GRF_SOC_CON6 */
550 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
551 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
552 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
553 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
554 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
555 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
557 static void rk3399_set_to_rgmii(struct rk_priv_data
*bsp_priv
,
558 int tx_delay
, int rx_delay
)
560 struct device
*dev
= &bsp_priv
->pdev
->dev
;
562 if (IS_ERR(bsp_priv
->grf
)) {
563 dev_err(dev
, "%s: Missing rockchip,grf property\n", __func__
);
567 regmap_write(bsp_priv
->grf
, RK3399_GRF_SOC_CON5
,
568 RK3399_GMAC_PHY_INTF_SEL_RGMII
|
569 RK3399_GMAC_RMII_MODE_CLR
);
570 regmap_write(bsp_priv
->grf
, RK3399_GRF_SOC_CON6
,
571 RK3399_GMAC_RXCLK_DLY_ENABLE
|
572 RK3399_GMAC_TXCLK_DLY_ENABLE
|
573 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay
) |
574 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay
));
577 static void rk3399_set_to_rmii(struct rk_priv_data
*bsp_priv
)
579 struct device
*dev
= &bsp_priv
->pdev
->dev
;
581 if (IS_ERR(bsp_priv
->grf
)) {
582 dev_err(dev
, "%s: Missing rockchip,grf property\n", __func__
);
586 regmap_write(bsp_priv
->grf
, RK3399_GRF_SOC_CON5
,
587 RK3399_GMAC_PHY_INTF_SEL_RMII
| RK3399_GMAC_RMII_MODE
);
590 static void rk3399_set_rgmii_speed(struct rk_priv_data
*bsp_priv
, int speed
)
592 struct device
*dev
= &bsp_priv
->pdev
->dev
;
594 if (IS_ERR(bsp_priv
->grf
)) {
595 dev_err(dev
, "%s: Missing rockchip,grf property\n", __func__
);
600 regmap_write(bsp_priv
->grf
, RK3399_GRF_SOC_CON5
,
601 RK3399_GMAC_CLK_2_5M
);
602 else if (speed
== 100)
603 regmap_write(bsp_priv
->grf
, RK3399_GRF_SOC_CON5
,
604 RK3399_GMAC_CLK_25M
);
605 else if (speed
== 1000)
606 regmap_write(bsp_priv
->grf
, RK3399_GRF_SOC_CON5
,
607 RK3399_GMAC_CLK_125M
);
609 dev_err(dev
, "unknown speed value for RGMII! speed=%d", speed
);
612 static void rk3399_set_rmii_speed(struct rk_priv_data
*bsp_priv
, int speed
)
614 struct device
*dev
= &bsp_priv
->pdev
->dev
;
616 if (IS_ERR(bsp_priv
->grf
)) {
617 dev_err(dev
, "%s: Missing rockchip,grf property\n", __func__
);
622 regmap_write(bsp_priv
->grf
, RK3399_GRF_SOC_CON5
,
623 RK3399_GMAC_RMII_CLK_2_5M
|
624 RK3399_GMAC_SPEED_10M
);
625 } else if (speed
== 100) {
626 regmap_write(bsp_priv
->grf
, RK3399_GRF_SOC_CON5
,
627 RK3399_GMAC_RMII_CLK_25M
|
628 RK3399_GMAC_SPEED_100M
);
630 dev_err(dev
, "unknown speed value for RMII! speed=%d", speed
);
634 static const struct rk_gmac_ops rk3399_ops
= {
635 .set_to_rgmii
= rk3399_set_to_rgmii
,
636 .set_to_rmii
= rk3399_set_to_rmii
,
637 .set_rgmii_speed
= rk3399_set_rgmii_speed
,
638 .set_rmii_speed
= rk3399_set_rmii_speed
,
641 static int gmac_clk_init(struct rk_priv_data
*bsp_priv
)
643 struct device
*dev
= &bsp_priv
->pdev
->dev
;
645 bsp_priv
->clk_enabled
= false;
647 bsp_priv
->mac_clk_rx
= devm_clk_get(dev
, "mac_clk_rx");
648 if (IS_ERR(bsp_priv
->mac_clk_rx
))
649 dev_err(dev
, "cannot get clock %s\n",
652 bsp_priv
->mac_clk_tx
= devm_clk_get(dev
, "mac_clk_tx");
653 if (IS_ERR(bsp_priv
->mac_clk_tx
))
654 dev_err(dev
, "cannot get clock %s\n",
657 bsp_priv
->aclk_mac
= devm_clk_get(dev
, "aclk_mac");
658 if (IS_ERR(bsp_priv
->aclk_mac
))
659 dev_err(dev
, "cannot get clock %s\n",
662 bsp_priv
->pclk_mac
= devm_clk_get(dev
, "pclk_mac");
663 if (IS_ERR(bsp_priv
->pclk_mac
))
664 dev_err(dev
, "cannot get clock %s\n",
667 bsp_priv
->clk_mac
= devm_clk_get(dev
, "stmmaceth");
668 if (IS_ERR(bsp_priv
->clk_mac
))
669 dev_err(dev
, "cannot get clock %s\n",
672 if (bsp_priv
->phy_iface
== PHY_INTERFACE_MODE_RMII
) {
673 bsp_priv
->clk_mac_ref
= devm_clk_get(dev
, "clk_mac_ref");
674 if (IS_ERR(bsp_priv
->clk_mac_ref
))
675 dev_err(dev
, "cannot get clock %s\n",
678 if (!bsp_priv
->clock_input
) {
679 bsp_priv
->clk_mac_refout
=
680 devm_clk_get(dev
, "clk_mac_refout");
681 if (IS_ERR(bsp_priv
->clk_mac_refout
))
682 dev_err(dev
, "cannot get clock %s\n",
687 if (bsp_priv
->clock_input
) {
688 dev_info(dev
, "clock input from PHY\n");
690 if (bsp_priv
->phy_iface
== PHY_INTERFACE_MODE_RMII
)
691 clk_set_rate(bsp_priv
->clk_mac
, 50000000);
697 static int gmac_clk_enable(struct rk_priv_data
*bsp_priv
, bool enable
)
699 int phy_iface
= bsp_priv
->phy_iface
;
702 if (!bsp_priv
->clk_enabled
) {
703 if (phy_iface
== PHY_INTERFACE_MODE_RMII
) {
704 if (!IS_ERR(bsp_priv
->mac_clk_rx
))
706 bsp_priv
->mac_clk_rx
);
708 if (!IS_ERR(bsp_priv
->clk_mac_ref
))
710 bsp_priv
->clk_mac_ref
);
712 if (!IS_ERR(bsp_priv
->clk_mac_refout
))
714 bsp_priv
->clk_mac_refout
);
717 if (!IS_ERR(bsp_priv
->aclk_mac
))
718 clk_prepare_enable(bsp_priv
->aclk_mac
);
720 if (!IS_ERR(bsp_priv
->pclk_mac
))
721 clk_prepare_enable(bsp_priv
->pclk_mac
);
723 if (!IS_ERR(bsp_priv
->mac_clk_tx
))
724 clk_prepare_enable(bsp_priv
->mac_clk_tx
);
727 * if (!IS_ERR(bsp_priv->clk_mac))
728 * clk_prepare_enable(bsp_priv->clk_mac);
731 bsp_priv
->clk_enabled
= true;
734 if (bsp_priv
->clk_enabled
) {
735 if (phy_iface
== PHY_INTERFACE_MODE_RMII
) {
736 if (!IS_ERR(bsp_priv
->mac_clk_rx
))
737 clk_disable_unprepare(
738 bsp_priv
->mac_clk_rx
);
740 if (!IS_ERR(bsp_priv
->clk_mac_ref
))
741 clk_disable_unprepare(
742 bsp_priv
->clk_mac_ref
);
744 if (!IS_ERR(bsp_priv
->clk_mac_refout
))
745 clk_disable_unprepare(
746 bsp_priv
->clk_mac_refout
);
749 if (!IS_ERR(bsp_priv
->aclk_mac
))
750 clk_disable_unprepare(bsp_priv
->aclk_mac
);
752 if (!IS_ERR(bsp_priv
->pclk_mac
))
753 clk_disable_unprepare(bsp_priv
->pclk_mac
);
755 if (!IS_ERR(bsp_priv
->mac_clk_tx
))
756 clk_disable_unprepare(bsp_priv
->mac_clk_tx
);
758 * if (!IS_ERR(bsp_priv->clk_mac))
759 * clk_disable_unprepare(bsp_priv->clk_mac);
761 bsp_priv
->clk_enabled
= false;
768 static int phy_power_on(struct rk_priv_data
*bsp_priv
, bool enable
)
770 struct regulator
*ldo
= bsp_priv
->regulator
;
772 struct device
*dev
= &bsp_priv
->pdev
->dev
;
775 dev_err(dev
, "no regulator found\n");
780 ret
= regulator_enable(ldo
);
782 dev_err(dev
, "fail to enable phy-supply\n");
784 ret
= regulator_disable(ldo
);
786 dev_err(dev
, "fail to disable phy-supply\n");
792 static struct rk_priv_data
*rk_gmac_setup(struct platform_device
*pdev
,
793 const struct rk_gmac_ops
*ops
)
795 struct rk_priv_data
*bsp_priv
;
796 struct device
*dev
= &pdev
->dev
;
798 const char *strings
= NULL
;
801 bsp_priv
= devm_kzalloc(dev
, sizeof(*bsp_priv
), GFP_KERNEL
);
803 return ERR_PTR(-ENOMEM
);
805 bsp_priv
->phy_iface
= of_get_phy_mode(dev
->of_node
);
808 bsp_priv
->regulator
= devm_regulator_get_optional(dev
, "phy");
809 if (IS_ERR(bsp_priv
->regulator
)) {
810 if (PTR_ERR(bsp_priv
->regulator
) == -EPROBE_DEFER
) {
811 dev_err(dev
, "phy regulator is not available yet, deferred probing\n");
812 return ERR_PTR(-EPROBE_DEFER
);
814 dev_err(dev
, "no regulator found\n");
815 bsp_priv
->regulator
= NULL
;
818 ret
= of_property_read_string(dev
->of_node
, "clock_in_out", &strings
);
820 dev_err(dev
, "Can not read property: clock_in_out.\n");
821 bsp_priv
->clock_input
= true;
823 dev_info(dev
, "clock input or output? (%s).\n",
825 if (!strcmp(strings
, "input"))
826 bsp_priv
->clock_input
= true;
828 bsp_priv
->clock_input
= false;
831 ret
= of_property_read_u32(dev
->of_node
, "tx_delay", &value
);
833 bsp_priv
->tx_delay
= 0x30;
834 dev_err(dev
, "Can not read property: tx_delay.");
835 dev_err(dev
, "set tx_delay to 0x%x\n",
838 dev_info(dev
, "TX delay(0x%x).\n", value
);
839 bsp_priv
->tx_delay
= value
;
842 ret
= of_property_read_u32(dev
->of_node
, "rx_delay", &value
);
844 bsp_priv
->rx_delay
= 0x10;
845 dev_err(dev
, "Can not read property: rx_delay.");
846 dev_err(dev
, "set rx_delay to 0x%x\n",
849 dev_info(dev
, "RX delay(0x%x).\n", value
);
850 bsp_priv
->rx_delay
= value
;
853 bsp_priv
->grf
= syscon_regmap_lookup_by_phandle(dev
->of_node
,
855 bsp_priv
->pdev
= pdev
;
857 gmac_clk_init(bsp_priv
);
862 static int rk_gmac_powerup(struct rk_priv_data
*bsp_priv
)
865 struct device
*dev
= &bsp_priv
->pdev
->dev
;
868 if (bsp_priv
->phy_iface
== PHY_INTERFACE_MODE_RGMII
) {
869 dev_info(dev
, "init for RGMII\n");
870 bsp_priv
->ops
->set_to_rgmii(bsp_priv
, bsp_priv
->tx_delay
,
872 } else if (bsp_priv
->phy_iface
== PHY_INTERFACE_MODE_RMII
) {
873 dev_info(dev
, "init for RMII\n");
874 bsp_priv
->ops
->set_to_rmii(bsp_priv
);
876 dev_err(dev
, "NO interface defined!\n");
879 ret
= phy_power_on(bsp_priv
, true);
883 ret
= gmac_clk_enable(bsp_priv
, true);
887 pm_runtime_enable(dev
);
888 pm_runtime_get_sync(dev
);
893 static void rk_gmac_powerdown(struct rk_priv_data
*gmac
)
895 struct device
*dev
= &gmac
->pdev
->dev
;
897 pm_runtime_put_sync(dev
);
898 pm_runtime_disable(dev
);
900 phy_power_on(gmac
, false);
901 gmac_clk_enable(gmac
, false);
904 static int rk_gmac_init(struct platform_device
*pdev
, void *priv
)
906 struct rk_priv_data
*bsp_priv
= priv
;
908 return rk_gmac_powerup(bsp_priv
);
911 static void rk_gmac_exit(struct platform_device
*pdev
, void *priv
)
913 struct rk_priv_data
*bsp_priv
= priv
;
915 rk_gmac_powerdown(bsp_priv
);
918 static void rk_gmac_suspend(struct platform_device
*pdev
, void *priv
)
920 struct rk_priv_data
*bsp_priv
= priv
;
922 /* Keep the PHY up if we use Wake-on-Lan. */
923 if (device_may_wakeup(&pdev
->dev
))
926 rk_gmac_powerdown(bsp_priv
);
927 bsp_priv
->suspended
= true;
930 static void rk_gmac_resume(struct platform_device
*pdev
, void *priv
)
932 struct rk_priv_data
*bsp_priv
= priv
;
934 /* The PHY was up for Wake-on-Lan. */
935 if (!bsp_priv
->suspended
)
938 rk_gmac_powerup(bsp_priv
);
939 bsp_priv
->suspended
= false;
942 static void rk_fix_speed(void *priv
, unsigned int speed
)
944 struct rk_priv_data
*bsp_priv
= priv
;
945 struct device
*dev
= &bsp_priv
->pdev
->dev
;
947 if (bsp_priv
->phy_iface
== PHY_INTERFACE_MODE_RGMII
)
948 bsp_priv
->ops
->set_rgmii_speed(bsp_priv
, speed
);
949 else if (bsp_priv
->phy_iface
== PHY_INTERFACE_MODE_RMII
)
950 bsp_priv
->ops
->set_rmii_speed(bsp_priv
, speed
);
952 dev_err(dev
, "unsupported interface %d", bsp_priv
->phy_iface
);
955 static int rk_gmac_probe(struct platform_device
*pdev
)
957 struct plat_stmmacenet_data
*plat_dat
;
958 struct stmmac_resources stmmac_res
;
959 const struct rk_gmac_ops
*data
;
962 data
= of_device_get_match_data(&pdev
->dev
);
964 dev_err(&pdev
->dev
, "no of match data provided\n");
968 ret
= stmmac_get_platform_resources(pdev
, &stmmac_res
);
972 plat_dat
= stmmac_probe_config_dt(pdev
, &stmmac_res
.mac
);
973 if (IS_ERR(plat_dat
))
974 return PTR_ERR(plat_dat
);
976 plat_dat
->has_gmac
= true;
977 plat_dat
->init
= rk_gmac_init
;
978 plat_dat
->exit
= rk_gmac_exit
;
979 plat_dat
->fix_mac_speed
= rk_fix_speed
;
980 plat_dat
->suspend
= rk_gmac_suspend
;
981 plat_dat
->resume
= rk_gmac_resume
;
983 plat_dat
->bsp_priv
= rk_gmac_setup(pdev
, data
);
984 if (IS_ERR(plat_dat
->bsp_priv
))
985 return PTR_ERR(plat_dat
->bsp_priv
);
987 ret
= rk_gmac_init(pdev
, plat_dat
->bsp_priv
);
991 return stmmac_dvr_probe(&pdev
->dev
, plat_dat
, &stmmac_res
);
994 static const struct of_device_id rk_gmac_dwmac_match
[] = {
995 { .compatible
= "rockchip,rk3228-gmac", .data
= &rk3228_ops
},
996 { .compatible
= "rockchip,rk3288-gmac", .data
= &rk3288_ops
},
997 { .compatible
= "rockchip,rk3366-gmac", .data
= &rk3366_ops
},
998 { .compatible
= "rockchip,rk3368-gmac", .data
= &rk3368_ops
},
999 { .compatible
= "rockchip,rk3399-gmac", .data
= &rk3399_ops
},
1002 MODULE_DEVICE_TABLE(of
, rk_gmac_dwmac_match
);
1004 static struct platform_driver rk_gmac_dwmac_driver
= {
1005 .probe
= rk_gmac_probe
,
1006 .remove
= stmmac_pltfr_remove
,
1008 .name
= "rk_gmac-dwmac",
1009 .pm
= &stmmac_pltfr_pm_ops
,
1010 .of_match_table
= rk_gmac_dwmac_match
,
1013 module_platform_driver(rk_gmac_dwmac_driver
);
1015 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
1016 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
1017 MODULE_LICENSE("GPL");