2 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
3 * DWC Ether MAC version 4.00 has been used for developing this code.
5 * This only implements the mac core functions for this chip.
7 * Copyright (C) 2015 STMicroelectronics Ltd
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * Author: Alexandre Torgue <alexandre.torgue@st.com>
16 #include <linux/crc32.h>
17 #include <linux/slab.h>
18 #include <linux/ethtool.h>
20 #include "stmmac_pcs.h"
23 static void dwmac4_core_init(struct mac_device_info
*hw
, int mtu
)
25 void __iomem
*ioaddr
= hw
->pcsr
;
26 u32 value
= readl(ioaddr
+ GMAC_CONFIG
);
28 value
|= GMAC_CORE_INIT
;
31 value
|= GMAC_CONFIG_2K
;
33 value
|= GMAC_CONFIG_JE
;
36 value
|= GMAC_CONFIG_TE
;
38 if (hw
->ps
== SPEED_1000
) {
39 value
&= ~GMAC_CONFIG_PS
;
41 value
|= GMAC_CONFIG_PS
;
43 if (hw
->ps
== SPEED_10
)
44 value
&= ~GMAC_CONFIG_FES
;
46 value
|= GMAC_CONFIG_FES
;
50 writel(value
, ioaddr
+ GMAC_CONFIG
);
52 /* Mask GMAC interrupts */
53 value
= GMAC_INT_DEFAULT_MASK
;
55 value
|= GMAC_INT_PMT_EN
;
57 value
|= GMAC_PCS_IRQ_DEFAULT
;
59 writel(value
, ioaddr
+ GMAC_INT_EN
);
62 static void dwmac4_dump_regs(struct mac_device_info
*hw
)
64 void __iomem
*ioaddr
= hw
->pcsr
;
67 pr_debug("\tDWMAC4 regs (base addr = 0x%p)\n", ioaddr
);
69 for (i
= 0; i
< GMAC_REG_NUM
; i
++) {
72 pr_debug("\tReg No. %d (offset 0x%x): 0x%08x\n", i
,
73 offset
, readl(ioaddr
+ offset
));
77 static int dwmac4_rx_ipc_enable(struct mac_device_info
*hw
)
79 void __iomem
*ioaddr
= hw
->pcsr
;
80 u32 value
= readl(ioaddr
+ GMAC_CONFIG
);
83 value
|= GMAC_CONFIG_IPC
;
85 value
&= ~GMAC_CONFIG_IPC
;
87 writel(value
, ioaddr
+ GMAC_CONFIG
);
89 value
= readl(ioaddr
+ GMAC_CONFIG
);
91 return !!(value
& GMAC_CONFIG_IPC
);
94 static void dwmac4_pmt(struct mac_device_info
*hw
, unsigned long mode
)
96 void __iomem
*ioaddr
= hw
->pcsr
;
99 if (mode
& WAKE_MAGIC
) {
100 pr_debug("GMAC: WOL Magic frame\n");
101 pmt
|= power_down
| magic_pkt_en
;
103 if (mode
& WAKE_UCAST
) {
104 pr_debug("GMAC: WOL on global unicast\n");
105 pmt
|= global_unicast
;
108 writel(pmt
, ioaddr
+ GMAC_PMT
);
111 static void dwmac4_set_umac_addr(struct mac_device_info
*hw
,
112 unsigned char *addr
, unsigned int reg_n
)
114 void __iomem
*ioaddr
= hw
->pcsr
;
116 stmmac_dwmac4_set_mac_addr(ioaddr
, addr
, GMAC_ADDR_HIGH(reg_n
),
117 GMAC_ADDR_LOW(reg_n
));
120 static void dwmac4_get_umac_addr(struct mac_device_info
*hw
,
121 unsigned char *addr
, unsigned int reg_n
)
123 void __iomem
*ioaddr
= hw
->pcsr
;
125 stmmac_dwmac4_get_mac_addr(ioaddr
, addr
, GMAC_ADDR_HIGH(reg_n
),
126 GMAC_ADDR_LOW(reg_n
));
129 static void dwmac4_set_filter(struct mac_device_info
*hw
,
130 struct net_device
*dev
)
132 void __iomem
*ioaddr
= (void __iomem
*)dev
->base_addr
;
133 unsigned int value
= 0;
135 if (dev
->flags
& IFF_PROMISC
) {
136 value
= GMAC_PACKET_FILTER_PR
;
137 } else if ((dev
->flags
& IFF_ALLMULTI
) ||
138 (netdev_mc_count(dev
) > HASH_TABLE_SIZE
)) {
140 value
= GMAC_PACKET_FILTER_PM
;
141 /* Set the 64 bits of the HASH tab. To be updated if taller
144 writel(0xffffffff, ioaddr
+ GMAC_HASH_TAB_0_31
);
145 writel(0xffffffff, ioaddr
+ GMAC_HASH_TAB_32_63
);
146 } else if (!netdev_mc_empty(dev
)) {
148 struct netdev_hw_addr
*ha
;
150 /* Hash filter for multicast */
151 value
= GMAC_PACKET_FILTER_HMC
;
153 memset(mc_filter
, 0, sizeof(mc_filter
));
154 netdev_for_each_mc_addr(ha
, dev
) {
155 /* The upper 6 bits of the calculated CRC are used to
156 * index the content of the Hash Table Reg 0 and 1.
159 (bitrev32(~crc32_le(~0, ha
->addr
, 6)) >> 26);
160 /* The most significant bit determines the register
161 * to use while the other 5 bits determines the bit
162 * within the selected register
164 mc_filter
[bit_nr
>> 5] |= (1 << (bit_nr
& 0x1F));
166 writel(mc_filter
[0], ioaddr
+ GMAC_HASH_TAB_0_31
);
167 writel(mc_filter
[1], ioaddr
+ GMAC_HASH_TAB_32_63
);
170 /* Handle multiple unicast addresses */
171 if (netdev_uc_count(dev
) > GMAC_MAX_PERFECT_ADDRESSES
) {
172 /* Switch to promiscuous mode if more than 128 addrs
175 value
|= GMAC_PACKET_FILTER_PR
;
176 } else if (!netdev_uc_empty(dev
)) {
178 struct netdev_hw_addr
*ha
;
180 netdev_for_each_uc_addr(ha
, dev
) {
181 dwmac4_set_umac_addr(hw
, ha
->addr
, reg
);
186 writel(value
, ioaddr
+ GMAC_PACKET_FILTER
);
189 static void dwmac4_flow_ctrl(struct mac_device_info
*hw
, unsigned int duplex
,
190 unsigned int fc
, unsigned int pause_time
)
192 void __iomem
*ioaddr
= hw
->pcsr
;
193 u32 channel
= STMMAC_CHAN0
; /* FIXME */
194 unsigned int flow
= 0;
196 pr_debug("GMAC Flow-Control:\n");
198 pr_debug("\tReceive Flow-Control ON\n");
199 flow
|= GMAC_RX_FLOW_CTRL_RFE
;
200 writel(flow
, ioaddr
+ GMAC_RX_FLOW_CTRL
);
203 pr_debug("\tTransmit Flow-Control ON\n");
204 flow
|= GMAC_TX_FLOW_CTRL_TFE
;
205 writel(flow
, ioaddr
+ GMAC_QX_TX_FLOW_CTRL(channel
));
208 pr_debug("\tduplex mode: PAUSE %d\n", pause_time
);
209 flow
|= (pause_time
<< GMAC_TX_FLOW_CTRL_PT_SHIFT
);
210 writel(flow
, ioaddr
+ GMAC_QX_TX_FLOW_CTRL(channel
));
215 static void dwmac4_ctrl_ane(void __iomem
*ioaddr
, bool ane
, bool srgmi_ral
,
218 dwmac_ctrl_ane(ioaddr
, GMAC_PCS_BASE
, ane
, srgmi_ral
, loopback
);
221 static void dwmac4_rane(void __iomem
*ioaddr
, bool restart
)
223 dwmac_rane(ioaddr
, GMAC_PCS_BASE
, restart
);
226 static void dwmac4_get_adv_lp(void __iomem
*ioaddr
, struct rgmii_adv
*adv
)
228 dwmac_get_adv_lp(ioaddr
, GMAC_PCS_BASE
, adv
);
231 /* RGMII or SMII interface */
232 static void dwmac4_phystatus(void __iomem
*ioaddr
, struct stmmac_extra_stats
*x
)
236 status
= readl(ioaddr
+ GMAC_PHYIF_CONTROL_STATUS
);
239 /* Check the link status */
240 if (status
& GMAC_PHYIF_CTRLSTATUS_LNKSTS
) {
245 speed_value
= ((status
& GMAC_PHYIF_CTRLSTATUS_SPEED
) >>
246 GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT
);
247 if (speed_value
== GMAC_PHYIF_CTRLSTATUS_SPEED_125
)
248 x
->pcs_speed
= SPEED_1000
;
249 else if (speed_value
== GMAC_PHYIF_CTRLSTATUS_SPEED_25
)
250 x
->pcs_speed
= SPEED_100
;
252 x
->pcs_speed
= SPEED_10
;
254 x
->pcs_duplex
= (status
& GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK
);
256 pr_info("Link is Up - %d/%s\n", (int)x
->pcs_speed
,
257 x
->pcs_duplex
? "Full" : "Half");
260 pr_info("Link is Down\n");
264 static int dwmac4_irq_status(struct mac_device_info
*hw
,
265 struct stmmac_extra_stats
*x
)
267 void __iomem
*ioaddr
= hw
->pcsr
;
268 u32 mtl_int_qx_status
;
272 intr_status
= readl(ioaddr
+ GMAC_INT_STATUS
);
274 /* Not used events (e.g. MMC interrupts) are not handled. */
275 if ((intr_status
& mmc_tx_irq
))
277 if (unlikely(intr_status
& mmc_rx_irq
))
279 if (unlikely(intr_status
& mmc_rx_csum_offload_irq
))
280 x
->mmc_rx_csum_offload_irq_n
++;
281 /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
282 if (unlikely(intr_status
& pmt_irq
)) {
283 readl(ioaddr
+ GMAC_PMT
);
284 x
->irq_receive_pmt_irq_n
++;
287 mtl_int_qx_status
= readl(ioaddr
+ MTL_INT_STATUS
);
288 /* Check MTL Interrupt: Currently only one queue is used: Q0. */
289 if (mtl_int_qx_status
& MTL_INT_Q0
) {
290 /* read Queue 0 Interrupt status */
291 u32 status
= readl(ioaddr
+ MTL_CHAN_INT_CTRL(STMMAC_CHAN0
));
293 if (status
& MTL_RX_OVERFLOW_INT
) {
294 /* clear Interrupt */
295 writel(status
| MTL_RX_OVERFLOW_INT
,
296 ioaddr
+ MTL_CHAN_INT_CTRL(STMMAC_CHAN0
));
297 ret
= CORE_IRQ_MTL_RX_OVERFLOW
;
301 dwmac_pcs_isr(ioaddr
, GMAC_PCS_BASE
, intr_status
, x
);
302 if (intr_status
& PCS_RGSMIIIS_IRQ
)
303 dwmac4_phystatus(ioaddr
, x
);
308 static void dwmac4_debug(void __iomem
*ioaddr
, struct stmmac_extra_stats
*x
)
312 /* Currently only channel 0 is supported */
313 value
= readl(ioaddr
+ MTL_CHAN_TX_DEBUG(STMMAC_CHAN0
));
315 if (value
& MTL_DEBUG_TXSTSFSTS
)
316 x
->mtl_tx_status_fifo_full
++;
317 if (value
& MTL_DEBUG_TXFSTS
)
318 x
->mtl_tx_fifo_not_empty
++;
319 if (value
& MTL_DEBUG_TWCSTS
)
321 if (value
& MTL_DEBUG_TRCSTS_MASK
) {
322 u32 trcsts
= (value
& MTL_DEBUG_TRCSTS_MASK
)
323 >> MTL_DEBUG_TRCSTS_SHIFT
;
324 if (trcsts
== MTL_DEBUG_TRCSTS_WRITE
)
325 x
->mtl_tx_fifo_read_ctrl_write
++;
326 else if (trcsts
== MTL_DEBUG_TRCSTS_TXW
)
327 x
->mtl_tx_fifo_read_ctrl_wait
++;
328 else if (trcsts
== MTL_DEBUG_TRCSTS_READ
)
329 x
->mtl_tx_fifo_read_ctrl_read
++;
331 x
->mtl_tx_fifo_read_ctrl_idle
++;
333 if (value
& MTL_DEBUG_TXPAUSED
)
334 x
->mac_tx_in_pause
++;
336 value
= readl(ioaddr
+ MTL_CHAN_RX_DEBUG(STMMAC_CHAN0
));
338 if (value
& MTL_DEBUG_RXFSTS_MASK
) {
339 u32 rxfsts
= (value
& MTL_DEBUG_RXFSTS_MASK
)
340 >> MTL_DEBUG_RRCSTS_SHIFT
;
342 if (rxfsts
== MTL_DEBUG_RXFSTS_FULL
)
343 x
->mtl_rx_fifo_fill_level_full
++;
344 else if (rxfsts
== MTL_DEBUG_RXFSTS_AT
)
345 x
->mtl_rx_fifo_fill_above_thresh
++;
346 else if (rxfsts
== MTL_DEBUG_RXFSTS_BT
)
347 x
->mtl_rx_fifo_fill_below_thresh
++;
349 x
->mtl_rx_fifo_fill_level_empty
++;
351 if (value
& MTL_DEBUG_RRCSTS_MASK
) {
352 u32 rrcsts
= (value
& MTL_DEBUG_RRCSTS_MASK
) >>
353 MTL_DEBUG_RRCSTS_SHIFT
;
355 if (rrcsts
== MTL_DEBUG_RRCSTS_FLUSH
)
356 x
->mtl_rx_fifo_read_ctrl_flush
++;
357 else if (rrcsts
== MTL_DEBUG_RRCSTS_RSTAT
)
358 x
->mtl_rx_fifo_read_ctrl_read_data
++;
359 else if (rrcsts
== MTL_DEBUG_RRCSTS_RDATA
)
360 x
->mtl_rx_fifo_read_ctrl_status
++;
362 x
->mtl_rx_fifo_read_ctrl_idle
++;
364 if (value
& MTL_DEBUG_RWCSTS
)
365 x
->mtl_rx_fifo_ctrl_active
++;
368 value
= readl(ioaddr
+ GMAC_DEBUG
);
370 if (value
& GMAC_DEBUG_TFCSTS_MASK
) {
371 u32 tfcsts
= (value
& GMAC_DEBUG_TFCSTS_MASK
)
372 >> GMAC_DEBUG_TFCSTS_SHIFT
;
374 if (tfcsts
== GMAC_DEBUG_TFCSTS_XFER
)
375 x
->mac_tx_frame_ctrl_xfer
++;
376 else if (tfcsts
== GMAC_DEBUG_TFCSTS_GEN_PAUSE
)
377 x
->mac_tx_frame_ctrl_pause
++;
378 else if (tfcsts
== GMAC_DEBUG_TFCSTS_WAIT
)
379 x
->mac_tx_frame_ctrl_wait
++;
381 x
->mac_tx_frame_ctrl_idle
++;
383 if (value
& GMAC_DEBUG_TPESTS
)
384 x
->mac_gmii_tx_proto_engine
++;
385 if (value
& GMAC_DEBUG_RFCFCSTS_MASK
)
386 x
->mac_rx_frame_ctrl_fifo
= (value
& GMAC_DEBUG_RFCFCSTS_MASK
)
387 >> GMAC_DEBUG_RFCFCSTS_SHIFT
;
388 if (value
& GMAC_DEBUG_RPESTS
)
389 x
->mac_gmii_rx_proto_engine
++;
392 static const struct stmmac_ops dwmac4_ops
= {
393 .core_init
= dwmac4_core_init
,
394 .rx_ipc
= dwmac4_rx_ipc_enable
,
395 .dump_regs
= dwmac4_dump_regs
,
396 .host_irq_status
= dwmac4_irq_status
,
397 .flow_ctrl
= dwmac4_flow_ctrl
,
399 .set_umac_addr
= dwmac4_set_umac_addr
,
400 .get_umac_addr
= dwmac4_get_umac_addr
,
401 .pcs_ctrl_ane
= dwmac4_ctrl_ane
,
402 .pcs_rane
= dwmac4_rane
,
403 .pcs_get_adv_lp
= dwmac4_get_adv_lp
,
404 .debug
= dwmac4_debug
,
405 .set_filter
= dwmac4_set_filter
,
408 struct mac_device_info
*dwmac4_setup(void __iomem
*ioaddr
, int mcbins
,
409 int perfect_uc_entries
, int *synopsys_id
)
411 struct mac_device_info
*mac
;
412 u32 hwid
= readl(ioaddr
+ GMAC_VERSION
);
414 mac
= kzalloc(sizeof(const struct mac_device_info
), GFP_KERNEL
);
419 mac
->multicast_filter_bins
= mcbins
;
420 mac
->unicast_filter_entries
= perfect_uc_entries
;
421 mac
->mcast_bits_log2
= 0;
423 if (mac
->multicast_filter_bins
)
424 mac
->mcast_bits_log2
= ilog2(mac
->multicast_filter_bins
);
426 mac
->mac
= &dwmac4_ops
;
428 mac
->link
.port
= GMAC_CONFIG_PS
;
429 mac
->link
.duplex
= GMAC_CONFIG_DM
;
430 mac
->link
.speed
= GMAC_CONFIG_FES
;
431 mac
->mii
.addr
= GMAC_MDIO_ADDR
;
432 mac
->mii
.data
= GMAC_MDIO_DATA
;
434 /* Get and dump the chip ID */
435 *synopsys_id
= stmmac_get_synopsys_id(hwid
);
437 if (*synopsys_id
> DWMAC_CORE_4_00
)
438 mac
->dma
= &dwmac410_dma_ops
;
440 mac
->dma
= &dwmac4_dma_ops
;