1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #include <linux/pinctrl/consumer.h>
47 #ifdef CONFIG_DEBUG_FS
48 #include <linux/debugfs.h>
49 #include <linux/seq_file.h>
50 #endif /* CONFIG_DEBUG_FS */
51 #include <linux/net_tstamp.h>
52 #include "stmmac_ptp.h"
54 #include <linux/reset.h>
56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
58 /* Module parameters */
60 static int watchdog
= TX_TIMEO
;
61 module_param(watchdog
, int, S_IRUGO
| S_IWUSR
);
62 MODULE_PARM_DESC(watchdog
, "Transmit timeout in milliseconds (default 5s)");
64 static int debug
= -1;
65 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
66 MODULE_PARM_DESC(debug
, "Message Level (-1: default, 0: no output, 16: all)");
68 static int phyaddr
= -1;
69 module_param(phyaddr
, int, S_IRUGO
);
70 MODULE_PARM_DESC(phyaddr
, "Physical device address");
72 #define DMA_TX_SIZE 256
73 static int dma_txsize
= DMA_TX_SIZE
;
74 module_param(dma_txsize
, int, S_IRUGO
| S_IWUSR
);
75 MODULE_PARM_DESC(dma_txsize
, "Number of descriptors in the TX list");
77 #define DMA_RX_SIZE 256
78 static int dma_rxsize
= DMA_RX_SIZE
;
79 module_param(dma_rxsize
, int, S_IRUGO
| S_IWUSR
);
80 MODULE_PARM_DESC(dma_rxsize
, "Number of descriptors in the RX list");
82 static int flow_ctrl
= FLOW_OFF
;
83 module_param(flow_ctrl
, int, S_IRUGO
| S_IWUSR
);
84 MODULE_PARM_DESC(flow_ctrl
, "Flow control ability [on/off]");
86 static int pause
= PAUSE_TIME
;
87 module_param(pause
, int, S_IRUGO
| S_IWUSR
);
88 MODULE_PARM_DESC(pause
, "Flow Control Pause Time");
91 static int tc
= TC_DEFAULT
;
92 module_param(tc
, int, S_IRUGO
| S_IWUSR
);
93 MODULE_PARM_DESC(tc
, "DMA threshold control value");
95 #define DEFAULT_BUFSIZE 1536
96 static int buf_sz
= DEFAULT_BUFSIZE
;
97 module_param(buf_sz
, int, S_IRUGO
| S_IWUSR
);
98 MODULE_PARM_DESC(buf_sz
, "DMA buffer size");
100 static const u32 default_msg_level
= (NETIF_MSG_DRV
| NETIF_MSG_PROBE
|
101 NETIF_MSG_LINK
| NETIF_MSG_IFUP
|
102 NETIF_MSG_IFDOWN
| NETIF_MSG_TIMER
);
104 #define STMMAC_DEFAULT_LPI_TIMER 1000
105 static int eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
106 module_param(eee_timer
, int, S_IRUGO
| S_IWUSR
);
107 MODULE_PARM_DESC(eee_timer
, "LPI tx expiration time in msec");
108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
110 /* By default the driver will use the ring mode to manage tx and rx descriptors
111 * but passing this value so user can force to use the chain instead of the ring
113 static unsigned int chain_mode
;
114 module_param(chain_mode
, int, S_IRUGO
);
115 MODULE_PARM_DESC(chain_mode
, "To use chain instead of ring mode");
117 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
);
119 #ifdef CONFIG_DEBUG_FS
120 static int stmmac_init_fs(struct net_device
*dev
);
121 static void stmmac_exit_fs(void);
124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
127 * stmmac_verify_args - verify the driver parameters.
128 * Description: it verifies if some wrong parameter is passed to the driver.
129 * Note that wrong parameters are replaced with the default values.
131 static void stmmac_verify_args(void)
133 if (unlikely(watchdog
< 0))
135 if (unlikely(dma_rxsize
< 0))
136 dma_rxsize
= DMA_RX_SIZE
;
137 if (unlikely(dma_txsize
< 0))
138 dma_txsize
= DMA_TX_SIZE
;
139 if (unlikely((buf_sz
< DEFAULT_BUFSIZE
) || (buf_sz
> BUF_SIZE_16KiB
)))
140 buf_sz
= DEFAULT_BUFSIZE
;
141 if (unlikely(flow_ctrl
> 1))
142 flow_ctrl
= FLOW_AUTO
;
143 else if (likely(flow_ctrl
< 0))
144 flow_ctrl
= FLOW_OFF
;
145 if (unlikely((pause
< 0) || (pause
> 0xffff)))
148 eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
152 * stmmac_clk_csr_set - dynamically set the MDC clock
153 * @priv: driver private structure
154 * Description: this is to dynamically set the MDC clock according to the csr
157 * If a specific clk_csr value is passed from the platform
158 * this means that the CSR Clock Range selection cannot be
159 * changed at run-time and it is fixed (as reported in the driver
160 * documentation). Viceversa the driver will try to set the MDC
161 * clock dynamically according to the actual clock input.
163 static void stmmac_clk_csr_set(struct stmmac_priv
*priv
)
167 clk_rate
= clk_get_rate(priv
->stmmac_clk
);
169 /* Platform provided default clk_csr would be assumed valid
170 * for all other cases except for the below mentioned ones.
171 * For values higher than the IEEE 802.3 specified frequency
172 * we can not estimate the proper divider as it is not known
173 * the frequency of clk_csr_i. So we do not change the default
176 if (!(priv
->clk_csr
& MAC_CSR_H_FRQ_MASK
)) {
177 if (clk_rate
< CSR_F_35M
)
178 priv
->clk_csr
= STMMAC_CSR_20_35M
;
179 else if ((clk_rate
>= CSR_F_35M
) && (clk_rate
< CSR_F_60M
))
180 priv
->clk_csr
= STMMAC_CSR_35_60M
;
181 else if ((clk_rate
>= CSR_F_60M
) && (clk_rate
< CSR_F_100M
))
182 priv
->clk_csr
= STMMAC_CSR_60_100M
;
183 else if ((clk_rate
>= CSR_F_100M
) && (clk_rate
< CSR_F_150M
))
184 priv
->clk_csr
= STMMAC_CSR_100_150M
;
185 else if ((clk_rate
>= CSR_F_150M
) && (clk_rate
< CSR_F_250M
))
186 priv
->clk_csr
= STMMAC_CSR_150_250M
;
187 else if ((clk_rate
>= CSR_F_250M
) && (clk_rate
< CSR_F_300M
))
188 priv
->clk_csr
= STMMAC_CSR_250_300M
;
192 static void print_pkt(unsigned char *buf
, int len
)
194 pr_debug("len = %d byte, buf addr: 0x%p\n", len
, buf
);
195 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
, buf
, len
);
198 /* minimum number of free TX descriptors required to wake up TX process */
199 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
201 static inline u32
stmmac_tx_avail(struct stmmac_priv
*priv
)
203 return priv
->dirty_tx
+ priv
->dma_tx_size
- priv
->cur_tx
- 1;
207 * stmmac_hw_fix_mac_speed: callback for speed selection
208 * @priv: driver private structure
209 * Description: on some platforms (e.g. ST), some HW system configuraton
210 * registers have to be set according to the link speed negotiated.
212 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv
*priv
)
214 struct phy_device
*phydev
= priv
->phydev
;
216 if (likely(priv
->plat
->fix_mac_speed
))
217 priv
->plat
->fix_mac_speed(priv
->plat
->bsp_priv
, phydev
->speed
);
221 * stmmac_enable_eee_mode: Check and enter in LPI mode
222 * @priv: driver private structure
223 * Description: this function is to verify and enter in LPI mode for EEE.
225 static void stmmac_enable_eee_mode(struct stmmac_priv
*priv
)
227 /* Check and enter in LPI mode */
228 if ((priv
->dirty_tx
== priv
->cur_tx
) &&
229 (priv
->tx_path_in_lpi_mode
== false))
230 priv
->hw
->mac
->set_eee_mode(priv
->hw
);
234 * stmmac_disable_eee_mode: disable/exit from EEE
235 * @priv: driver private structure
236 * Description: this function is to exit and disable EEE in case of
237 * LPI state is true. This is called by the xmit.
239 void stmmac_disable_eee_mode(struct stmmac_priv
*priv
)
241 priv
->hw
->mac
->reset_eee_mode(priv
->hw
);
242 del_timer_sync(&priv
->eee_ctrl_timer
);
243 priv
->tx_path_in_lpi_mode
= false;
247 * stmmac_eee_ctrl_timer: EEE TX SW timer.
250 * if there is no data transfer and if we are not in LPI state,
251 * then MAC Transmitter can be moved to LPI state.
253 static void stmmac_eee_ctrl_timer(unsigned long arg
)
255 struct stmmac_priv
*priv
= (struct stmmac_priv
*)arg
;
257 stmmac_enable_eee_mode(priv
);
258 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
262 * stmmac_eee_init: init EEE
263 * @priv: driver private structure
265 * If the EEE support has been enabled while configuring the driver,
266 * if the GMAC actually supports the EEE (from the HW cap reg) and the
267 * phy can also manage EEE, so enable the LPI state and start the timer
268 * to verify if the tx path can enter in LPI state.
270 bool stmmac_eee_init(struct stmmac_priv
*priv
)
272 char *phy_bus_name
= priv
->plat
->phy_bus_name
;
276 /* Using PCS we cannot dial with the phy registers at this stage
277 * so we do not support extra feature like EEE.
279 if ((priv
->pcs
== STMMAC_PCS_RGMII
) || (priv
->pcs
== STMMAC_PCS_TBI
) ||
280 (priv
->pcs
== STMMAC_PCS_RTBI
))
283 /* Never init EEE in case of a switch is attached */
284 if (phy_bus_name
&& (!strcmp(phy_bus_name
, "fixed")))
287 /* MAC core supports the EEE feature. */
288 if (priv
->dma_cap
.eee
) {
289 int tx_lpi_timer
= priv
->tx_lpi_timer
;
291 /* Check if the PHY supports EEE */
292 if (phy_init_eee(priv
->phydev
, 1)) {
293 /* To manage at run-time if the EEE cannot be supported
294 * anymore (for example because the lp caps have been
296 * In that case the driver disable own timers.
298 spin_lock_irqsave(&priv
->lock
, flags
);
299 if (priv
->eee_active
) {
300 pr_debug("stmmac: disable EEE\n");
301 del_timer_sync(&priv
->eee_ctrl_timer
);
302 priv
->hw
->mac
->set_eee_timer(priv
->hw
, 0,
305 priv
->eee_active
= 0;
306 spin_unlock_irqrestore(&priv
->lock
, flags
);
309 /* Activate the EEE and start timers */
310 spin_lock_irqsave(&priv
->lock
, flags
);
311 if (!priv
->eee_active
) {
312 priv
->eee_active
= 1;
313 init_timer(&priv
->eee_ctrl_timer
);
314 priv
->eee_ctrl_timer
.function
= stmmac_eee_ctrl_timer
;
315 priv
->eee_ctrl_timer
.data
= (unsigned long)priv
;
316 priv
->eee_ctrl_timer
.expires
= STMMAC_LPI_T(eee_timer
);
317 add_timer(&priv
->eee_ctrl_timer
);
319 priv
->hw
->mac
->set_eee_timer(priv
->hw
,
320 STMMAC_DEFAULT_LIT_LS
,
323 /* Set HW EEE according to the speed */
324 priv
->hw
->mac
->set_eee_pls(priv
->hw
, priv
->phydev
->link
);
327 spin_unlock_irqrestore(&priv
->lock
, flags
);
329 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
335 /* stmmac_get_tx_hwtstamp: get HW TX timestamps
336 * @priv: driver private structure
337 * @entry : descriptor index to be used.
338 * @skb : the socket buffer
340 * This function will read timestamp from the descriptor & pass it to stack.
341 * and also perform some sanity checks.
343 static void stmmac_get_tx_hwtstamp(struct stmmac_priv
*priv
,
344 unsigned int entry
, struct sk_buff
*skb
)
346 struct skb_shared_hwtstamps shhwtstamp
;
350 if (!priv
->hwts_tx_en
)
353 /* exit if skb doesn't support hw tstamp */
354 if (likely(!skb
|| !(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)))
358 desc
= (priv
->dma_etx
+ entry
);
360 desc
= (priv
->dma_tx
+ entry
);
362 /* check tx tstamp status */
363 if (!priv
->hw
->desc
->get_tx_timestamp_status((struct dma_desc
*)desc
))
366 /* get the valid tstamp */
367 ns
= priv
->hw
->desc
->get_timestamp(desc
, priv
->adv_ts
);
369 memset(&shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
370 shhwtstamp
.hwtstamp
= ns_to_ktime(ns
);
371 /* pass tstamp to stack */
372 skb_tstamp_tx(skb
, &shhwtstamp
);
377 /* stmmac_get_rx_hwtstamp: get HW RX timestamps
378 * @priv: driver private structure
379 * @entry : descriptor index to be used.
380 * @skb : the socket buffer
382 * This function will read received packet's timestamp from the descriptor
383 * and pass it to stack. It also perform some sanity checks.
385 static void stmmac_get_rx_hwtstamp(struct stmmac_priv
*priv
,
386 unsigned int entry
, struct sk_buff
*skb
)
388 struct skb_shared_hwtstamps
*shhwtstamp
= NULL
;
392 if (!priv
->hwts_rx_en
)
396 desc
= (priv
->dma_erx
+ entry
);
398 desc
= (priv
->dma_rx
+ entry
);
400 /* exit if rx tstamp is not valid */
401 if (!priv
->hw
->desc
->get_rx_timestamp_status(desc
, priv
->adv_ts
))
404 /* get valid tstamp */
405 ns
= priv
->hw
->desc
->get_timestamp(desc
, priv
->adv_ts
);
406 shhwtstamp
= skb_hwtstamps(skb
);
407 memset(shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
408 shhwtstamp
->hwtstamp
= ns_to_ktime(ns
);
412 * stmmac_hwtstamp_ioctl - control hardware timestamping.
413 * @dev: device pointer.
414 * @ifr: An IOCTL specefic structure, that can contain a pointer to
415 * a proprietary structure used to pass information to the driver.
417 * This function configures the MAC to enable/disable both outgoing(TX)
418 * and incoming(RX) packets time stamping based on user input.
420 * 0 on success and an appropriate -ve integer on failure.
422 static int stmmac_hwtstamp_ioctl(struct net_device
*dev
, struct ifreq
*ifr
)
424 struct stmmac_priv
*priv
= netdev_priv(dev
);
425 struct hwtstamp_config config
;
430 u32 ptp_over_ipv4_udp
= 0;
431 u32 ptp_over_ipv6_udp
= 0;
432 u32 ptp_over_ethernet
= 0;
433 u32 snap_type_sel
= 0;
434 u32 ts_master_en
= 0;
438 if (!(priv
->dma_cap
.time_stamp
|| priv
->adv_ts
)) {
439 netdev_alert(priv
->dev
, "No support for HW time stamping\n");
440 priv
->hwts_tx_en
= 0;
441 priv
->hwts_rx_en
= 0;
446 if (copy_from_user(&config
, ifr
->ifr_data
,
447 sizeof(struct hwtstamp_config
)))
450 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
451 __func__
, config
.flags
, config
.tx_type
, config
.rx_filter
);
453 /* reserved for future extensions */
457 if (config
.tx_type
!= HWTSTAMP_TX_OFF
&&
458 config
.tx_type
!= HWTSTAMP_TX_ON
)
462 switch (config
.rx_filter
) {
463 case HWTSTAMP_FILTER_NONE
:
464 /* time stamp no incoming packet at all */
465 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
468 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
469 /* PTP v1, UDP, any kind of event packet */
470 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
471 /* take time stamp for all event messages */
472 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
474 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
475 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
478 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
479 /* PTP v1, UDP, Sync packet */
480 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_SYNC
;
481 /* take time stamp for SYNC messages only */
482 ts_event_en
= PTP_TCR_TSEVNTENA
;
484 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
485 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
488 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
489 /* PTP v1, UDP, Delay_req packet */
490 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
;
491 /* take time stamp for Delay_Req messages only */
492 ts_master_en
= PTP_TCR_TSMSTRENA
;
493 ts_event_en
= PTP_TCR_TSEVNTENA
;
495 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
496 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
499 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
500 /* PTP v2, UDP, any kind of event packet */
501 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_EVENT
;
502 ptp_v2
= PTP_TCR_TSVER2ENA
;
503 /* take time stamp for all event messages */
504 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
506 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
507 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
510 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
511 /* PTP v2, UDP, Sync packet */
512 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_SYNC
;
513 ptp_v2
= PTP_TCR_TSVER2ENA
;
514 /* take time stamp for SYNC messages only */
515 ts_event_en
= PTP_TCR_TSEVNTENA
;
517 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
518 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
521 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
522 /* PTP v2, UDP, Delay_req packet */
523 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
;
524 ptp_v2
= PTP_TCR_TSVER2ENA
;
525 /* take time stamp for Delay_Req messages only */
526 ts_master_en
= PTP_TCR_TSMSTRENA
;
527 ts_event_en
= PTP_TCR_TSEVNTENA
;
529 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
530 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
533 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
534 /* PTP v2/802.AS1 any layer, any kind of event packet */
535 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
536 ptp_v2
= PTP_TCR_TSVER2ENA
;
537 /* take time stamp for all event messages */
538 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
540 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
541 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
542 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
545 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
546 /* PTP v2/802.AS1, any layer, Sync packet */
547 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_SYNC
;
548 ptp_v2
= PTP_TCR_TSVER2ENA
;
549 /* take time stamp for SYNC messages only */
550 ts_event_en
= PTP_TCR_TSEVNTENA
;
552 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
553 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
554 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
557 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
558 /* PTP v2/802.AS1, any layer, Delay_req packet */
559 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
;
560 ptp_v2
= PTP_TCR_TSVER2ENA
;
561 /* take time stamp for Delay_Req messages only */
562 ts_master_en
= PTP_TCR_TSMSTRENA
;
563 ts_event_en
= PTP_TCR_TSEVNTENA
;
565 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
566 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
567 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
570 case HWTSTAMP_FILTER_ALL
:
571 /* time stamp any incoming packet */
572 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
573 tstamp_all
= PTP_TCR_TSENALL
;
580 switch (config
.rx_filter
) {
581 case HWTSTAMP_FILTER_NONE
:
582 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
585 /* PTP v1, UDP, any kind of event packet */
586 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
590 priv
->hwts_rx_en
= ((config
.rx_filter
== HWTSTAMP_FILTER_NONE
) ? 0 : 1);
591 priv
->hwts_tx_en
= config
.tx_type
== HWTSTAMP_TX_ON
;
593 if (!priv
->hwts_tx_en
&& !priv
->hwts_rx_en
)
594 priv
->hw
->ptp
->config_hw_tstamping(priv
->ioaddr
, 0);
596 value
= (PTP_TCR_TSENA
| PTP_TCR_TSCFUPDT
| PTP_TCR_TSCTRLSSR
|
597 tstamp_all
| ptp_v2
| ptp_over_ethernet
|
598 ptp_over_ipv6_udp
| ptp_over_ipv4_udp
| ts_event_en
|
599 ts_master_en
| snap_type_sel
);
601 priv
->hw
->ptp
->config_hw_tstamping(priv
->ioaddr
, value
);
603 /* program Sub Second Increment reg */
604 priv
->hw
->ptp
->config_sub_second_increment(priv
->ioaddr
);
606 /* calculate default added value:
608 * addend = (2^32)/freq_div_ratio;
609 * where, freq_div_ratio = clk_ptp_ref_i/50MHz
610 * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
611 * NOTE: clk_ptp_ref_i should be >= 50MHz to
612 * achive 20ns accuracy.
614 * 2^x * y == (y << x), hence
615 * 2^32 * 50000000 ==> (50000000 << 32)
617 temp
= (u64
) (50000000ULL << 32);
618 priv
->default_addend
= div_u64(temp
, priv
->clk_ptp_rate
);
619 priv
->hw
->ptp
->config_addend(priv
->ioaddr
,
620 priv
->default_addend
);
622 /* initialize system time */
623 getnstimeofday(&now
);
624 priv
->hw
->ptp
->init_systime(priv
->ioaddr
, now
.tv_sec
,
628 return copy_to_user(ifr
->ifr_data
, &config
,
629 sizeof(struct hwtstamp_config
)) ? -EFAULT
: 0;
633 * stmmac_init_ptp: init PTP
634 * @priv: driver private structure
635 * Description: this is to verify if the HW supports the PTPv1 or v2.
636 * This is done by looking at the HW cap. register.
637 * Also it registers the ptp driver.
639 static int stmmac_init_ptp(struct stmmac_priv
*priv
)
641 if (!(priv
->dma_cap
.time_stamp
|| priv
->dma_cap
.atime_stamp
))
644 /* Fall-back to main clock in case of no PTP ref is passed */
645 priv
->clk_ptp_ref
= devm_clk_get(priv
->device
, "clk_ptp_ref");
646 if (IS_ERR(priv
->clk_ptp_ref
)) {
647 priv
->clk_ptp_rate
= clk_get_rate(priv
->stmmac_clk
);
648 priv
->clk_ptp_ref
= NULL
;
650 clk_prepare_enable(priv
->clk_ptp_ref
);
651 priv
->clk_ptp_rate
= clk_get_rate(priv
->clk_ptp_ref
);
655 if (priv
->dma_cap
.atime_stamp
&& priv
->extend_desc
)
658 if (netif_msg_hw(priv
) && priv
->dma_cap
.time_stamp
)
659 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
661 if (netif_msg_hw(priv
) && priv
->adv_ts
)
662 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
664 priv
->hw
->ptp
= &stmmac_ptp
;
665 priv
->hwts_tx_en
= 0;
666 priv
->hwts_rx_en
= 0;
668 return stmmac_ptp_register(priv
);
671 static void stmmac_release_ptp(struct stmmac_priv
*priv
)
673 if (priv
->clk_ptp_ref
)
674 clk_disable_unprepare(priv
->clk_ptp_ref
);
675 stmmac_ptp_unregister(priv
);
680 * @dev: net device structure
681 * Description: it adjusts the link parameters.
683 static void stmmac_adjust_link(struct net_device
*dev
)
685 struct stmmac_priv
*priv
= netdev_priv(dev
);
686 struct phy_device
*phydev
= priv
->phydev
;
689 unsigned int fc
= priv
->flow_ctrl
, pause_time
= priv
->pause
;
694 spin_lock_irqsave(&priv
->lock
, flags
);
697 u32 ctrl
= readl(priv
->ioaddr
+ MAC_CTRL_REG
);
699 /* Now we make sure that we can be in full duplex mode.
700 * If not, we operate in half-duplex mode. */
701 if (phydev
->duplex
!= priv
->oldduplex
) {
703 if (!(phydev
->duplex
))
704 ctrl
&= ~priv
->hw
->link
.duplex
;
706 ctrl
|= priv
->hw
->link
.duplex
;
707 priv
->oldduplex
= phydev
->duplex
;
709 /* Flow Control operation */
711 priv
->hw
->mac
->flow_ctrl(priv
->hw
, phydev
->duplex
,
714 if (phydev
->speed
!= priv
->speed
) {
716 switch (phydev
->speed
) {
718 if (likely(priv
->plat
->has_gmac
))
719 ctrl
&= ~priv
->hw
->link
.port
;
720 stmmac_hw_fix_mac_speed(priv
);
724 if (priv
->plat
->has_gmac
) {
725 ctrl
|= priv
->hw
->link
.port
;
726 if (phydev
->speed
== SPEED_100
) {
727 ctrl
|= priv
->hw
->link
.speed
;
729 ctrl
&= ~(priv
->hw
->link
.speed
);
732 ctrl
&= ~priv
->hw
->link
.port
;
734 stmmac_hw_fix_mac_speed(priv
);
737 if (netif_msg_link(priv
))
738 pr_warn("%s: Speed (%d) not 10/100\n",
739 dev
->name
, phydev
->speed
);
743 priv
->speed
= phydev
->speed
;
746 writel(ctrl
, priv
->ioaddr
+ MAC_CTRL_REG
);
748 if (!priv
->oldlink
) {
752 } else if (priv
->oldlink
) {
756 priv
->oldduplex
= -1;
759 if (new_state
&& netif_msg_link(priv
))
760 phy_print_status(phydev
);
762 spin_unlock_irqrestore(&priv
->lock
, flags
);
764 /* At this stage, it could be needed to setup the EEE or adjust some
765 * MAC related HW registers.
767 priv
->eee_enabled
= stmmac_eee_init(priv
);
771 * stmmac_check_pcs_mode: verify if RGMII/SGMII is supported
772 * @priv: driver private structure
773 * Description: this is to verify if the HW supports the PCS.
774 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
775 * configured for the TBI, RTBI, or SGMII PHY interface.
777 static void stmmac_check_pcs_mode(struct stmmac_priv
*priv
)
779 int interface
= priv
->plat
->interface
;
781 if (priv
->dma_cap
.pcs
) {
782 if ((interface
== PHY_INTERFACE_MODE_RGMII
) ||
783 (interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
784 (interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
785 (interface
== PHY_INTERFACE_MODE_RGMII_TXID
)) {
786 pr_debug("STMMAC: PCS RGMII support enable\n");
787 priv
->pcs
= STMMAC_PCS_RGMII
;
788 } else if (interface
== PHY_INTERFACE_MODE_SGMII
) {
789 pr_debug("STMMAC: PCS SGMII support enable\n");
790 priv
->pcs
= STMMAC_PCS_SGMII
;
796 * stmmac_init_phy - PHY initialization
797 * @dev: net device structure
798 * Description: it initializes the driver's PHY state, and attaches the PHY
803 static int stmmac_init_phy(struct net_device
*dev
)
805 struct stmmac_priv
*priv
= netdev_priv(dev
);
806 struct phy_device
*phydev
;
807 char phy_id_fmt
[MII_BUS_ID_SIZE
+ 3];
808 char bus_id
[MII_BUS_ID_SIZE
];
809 int interface
= priv
->plat
->interface
;
810 int max_speed
= priv
->plat
->max_speed
;
813 priv
->oldduplex
= -1;
815 if (priv
->plat
->phy_bus_name
)
816 snprintf(bus_id
, MII_BUS_ID_SIZE
, "%s-%x",
817 priv
->plat
->phy_bus_name
, priv
->plat
->bus_id
);
819 snprintf(bus_id
, MII_BUS_ID_SIZE
, "stmmac-%x",
822 snprintf(phy_id_fmt
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
, bus_id
,
823 priv
->plat
->phy_addr
);
824 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt
);
826 phydev
= phy_connect(dev
, phy_id_fmt
, &stmmac_adjust_link
, interface
);
828 if (IS_ERR(phydev
)) {
829 pr_err("%s: Could not attach to PHY\n", dev
->name
);
830 return PTR_ERR(phydev
);
833 /* Stop Advertising 1000BASE Capability if interface is not GMII */
834 if ((interface
== PHY_INTERFACE_MODE_MII
) ||
835 (interface
== PHY_INTERFACE_MODE_RMII
) ||
836 (max_speed
< 1000 && max_speed
> 0))
837 phydev
->advertising
&= ~(SUPPORTED_1000baseT_Half
|
838 SUPPORTED_1000baseT_Full
);
841 * Broken HW is sometimes missing the pull-up resistor on the
842 * MDIO line, which results in reads to non-existent devices returning
843 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
845 * Note: phydev->phy_id is the result of reading the UID PHY registers.
847 if (phydev
->phy_id
== 0) {
848 phy_disconnect(phydev
);
851 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
852 " Link = %d\n", dev
->name
, phydev
->phy_id
, phydev
->link
);
854 priv
->phydev
= phydev
;
860 * stmmac_display_ring: display ring
861 * @head: pointer to the head of the ring passed.
862 * @size: size of the ring.
863 * @extend_desc: to verify if extended descriptors are used.
864 * Description: display the control/status and buffer descriptors.
866 static void stmmac_display_ring(void *head
, int size
, int extend_desc
)
869 struct dma_extended_desc
*ep
= (struct dma_extended_desc
*)head
;
870 struct dma_desc
*p
= (struct dma_desc
*)head
;
872 for (i
= 0; i
< size
; i
++) {
876 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
877 i
, (unsigned int)virt_to_phys(ep
),
878 (unsigned int)x
, (unsigned int)(x
>> 32),
879 ep
->basic
.des2
, ep
->basic
.des3
);
883 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
884 i
, (unsigned int)virt_to_phys(p
),
885 (unsigned int)x
, (unsigned int)(x
>> 32),
893 static void stmmac_display_rings(struct stmmac_priv
*priv
)
895 unsigned int txsize
= priv
->dma_tx_size
;
896 unsigned int rxsize
= priv
->dma_rx_size
;
898 if (priv
->extend_desc
) {
899 pr_info("Extended RX descriptor ring:\n");
900 stmmac_display_ring((void *)priv
->dma_erx
, rxsize
, 1);
901 pr_info("Extended TX descriptor ring:\n");
902 stmmac_display_ring((void *)priv
->dma_etx
, txsize
, 1);
904 pr_info("RX descriptor ring:\n");
905 stmmac_display_ring((void *)priv
->dma_rx
, rxsize
, 0);
906 pr_info("TX descriptor ring:\n");
907 stmmac_display_ring((void *)priv
->dma_tx
, txsize
, 0);
911 static int stmmac_set_bfsize(int mtu
, int bufsize
)
915 if (mtu
>= BUF_SIZE_4KiB
)
917 else if (mtu
>= BUF_SIZE_2KiB
)
919 else if (mtu
> DEFAULT_BUFSIZE
)
922 ret
= DEFAULT_BUFSIZE
;
928 * stmmac_clear_descriptors: clear descriptors
929 * @priv: driver private structure
930 * Description: this function is called to clear the tx and rx descriptors
931 * in case of both basic and extended descriptors are used.
933 static void stmmac_clear_descriptors(struct stmmac_priv
*priv
)
936 unsigned int txsize
= priv
->dma_tx_size
;
937 unsigned int rxsize
= priv
->dma_rx_size
;
939 /* Clear the Rx/Tx descriptors */
940 for (i
= 0; i
< rxsize
; i
++)
941 if (priv
->extend_desc
)
942 priv
->hw
->desc
->init_rx_desc(&priv
->dma_erx
[i
].basic
,
943 priv
->use_riwt
, priv
->mode
,
946 priv
->hw
->desc
->init_rx_desc(&priv
->dma_rx
[i
],
947 priv
->use_riwt
, priv
->mode
,
949 for (i
= 0; i
< txsize
; i
++)
950 if (priv
->extend_desc
)
951 priv
->hw
->desc
->init_tx_desc(&priv
->dma_etx
[i
].basic
,
955 priv
->hw
->desc
->init_tx_desc(&priv
->dma_tx
[i
],
960 static int stmmac_init_rx_buffers(struct stmmac_priv
*priv
, struct dma_desc
*p
,
965 skb
= __netdev_alloc_skb(priv
->dev
, priv
->dma_buf_sz
+ NET_IP_ALIGN
,
968 pr_err("%s: Rx init fails; skb is NULL\n", __func__
);
971 skb_reserve(skb
, NET_IP_ALIGN
);
972 priv
->rx_skbuff
[i
] = skb
;
973 priv
->rx_skbuff_dma
[i
] = dma_map_single(priv
->device
, skb
->data
,
976 if (dma_mapping_error(priv
->device
, priv
->rx_skbuff_dma
[i
])) {
977 pr_err("%s: DMA mapping error\n", __func__
);
978 dev_kfree_skb_any(skb
);
982 p
->des2
= priv
->rx_skbuff_dma
[i
];
984 if ((priv
->hw
->mode
->init_desc3
) &&
985 (priv
->dma_buf_sz
== BUF_SIZE_16KiB
))
986 priv
->hw
->mode
->init_desc3(p
);
991 static void stmmac_free_rx_buffers(struct stmmac_priv
*priv
, int i
)
993 if (priv
->rx_skbuff
[i
]) {
994 dma_unmap_single(priv
->device
, priv
->rx_skbuff_dma
[i
],
995 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
996 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
998 priv
->rx_skbuff
[i
] = NULL
;
1002 * init_dma_desc_rings - init the RX/TX descriptor rings
1003 * @dev: net device structure
1004 * Description: this function initializes the DMA RX/TX descriptors
1005 * and allocates the socket buffers. It suppors the chained and ring
1008 static int init_dma_desc_rings(struct net_device
*dev
, gfp_t flags
)
1011 struct stmmac_priv
*priv
= netdev_priv(dev
);
1012 unsigned int txsize
= priv
->dma_tx_size
;
1013 unsigned int rxsize
= priv
->dma_rx_size
;
1014 unsigned int bfsize
= 0;
1017 if (priv
->hw
->mode
->set_16kib_bfsize
)
1018 bfsize
= priv
->hw
->mode
->set_16kib_bfsize(dev
->mtu
);
1020 if (bfsize
< BUF_SIZE_16KiB
)
1021 bfsize
= stmmac_set_bfsize(dev
->mtu
, priv
->dma_buf_sz
);
1023 priv
->dma_buf_sz
= bfsize
;
1025 if (netif_msg_probe(priv
))
1026 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__
,
1027 txsize
, rxsize
, bfsize
);
1029 if (netif_msg_probe(priv
)) {
1030 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__
,
1031 (u32
) priv
->dma_rx_phy
, (u32
) priv
->dma_tx_phy
);
1033 /* RX INITIALIZATION */
1034 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1036 for (i
= 0; i
< rxsize
; i
++) {
1038 if (priv
->extend_desc
)
1039 p
= &((priv
->dma_erx
+ i
)->basic
);
1041 p
= priv
->dma_rx
+ i
;
1043 ret
= stmmac_init_rx_buffers(priv
, p
, i
, flags
);
1045 goto err_init_rx_buffers
;
1047 if (netif_msg_probe(priv
))
1048 pr_debug("[%p]\t[%p]\t[%x]\n", priv
->rx_skbuff
[i
],
1049 priv
->rx_skbuff
[i
]->data
,
1050 (unsigned int)priv
->rx_skbuff_dma
[i
]);
1053 priv
->dirty_rx
= (unsigned int)(i
- rxsize
);
1056 /* Setup the chained descriptor addresses */
1057 if (priv
->mode
== STMMAC_CHAIN_MODE
) {
1058 if (priv
->extend_desc
) {
1059 priv
->hw
->mode
->init(priv
->dma_erx
, priv
->dma_rx_phy
,
1061 priv
->hw
->mode
->init(priv
->dma_etx
, priv
->dma_tx_phy
,
1064 priv
->hw
->mode
->init(priv
->dma_rx
, priv
->dma_rx_phy
,
1066 priv
->hw
->mode
->init(priv
->dma_tx
, priv
->dma_tx_phy
,
1071 /* TX INITIALIZATION */
1072 for (i
= 0; i
< txsize
; i
++) {
1074 if (priv
->extend_desc
)
1075 p
= &((priv
->dma_etx
+ i
)->basic
);
1077 p
= priv
->dma_tx
+ i
;
1079 priv
->tx_skbuff_dma
[i
].buf
= 0;
1080 priv
->tx_skbuff_dma
[i
].map_as_page
= false;
1081 priv
->tx_skbuff
[i
] = NULL
;
1087 stmmac_clear_descriptors(priv
);
1089 if (netif_msg_hw(priv
))
1090 stmmac_display_rings(priv
);
1093 err_init_rx_buffers
:
1095 stmmac_free_rx_buffers(priv
, i
);
1099 static void dma_free_rx_skbufs(struct stmmac_priv
*priv
)
1103 for (i
= 0; i
< priv
->dma_rx_size
; i
++)
1104 stmmac_free_rx_buffers(priv
, i
);
1107 static void dma_free_tx_skbufs(struct stmmac_priv
*priv
)
1111 for (i
= 0; i
< priv
->dma_tx_size
; i
++) {
1114 if (priv
->extend_desc
)
1115 p
= &((priv
->dma_etx
+ i
)->basic
);
1117 p
= priv
->dma_tx
+ i
;
1119 if (priv
->tx_skbuff_dma
[i
].buf
) {
1120 if (priv
->tx_skbuff_dma
[i
].map_as_page
)
1121 dma_unmap_page(priv
->device
,
1122 priv
->tx_skbuff_dma
[i
].buf
,
1123 priv
->hw
->desc
->get_tx_len(p
),
1126 dma_unmap_single(priv
->device
,
1127 priv
->tx_skbuff_dma
[i
].buf
,
1128 priv
->hw
->desc
->get_tx_len(p
),
1132 if (priv
->tx_skbuff
[i
] != NULL
) {
1133 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
1134 priv
->tx_skbuff
[i
] = NULL
;
1135 priv
->tx_skbuff_dma
[i
].buf
= 0;
1136 priv
->tx_skbuff_dma
[i
].map_as_page
= false;
1141 static int alloc_dma_desc_resources(struct stmmac_priv
*priv
)
1143 unsigned int txsize
= priv
->dma_tx_size
;
1144 unsigned int rxsize
= priv
->dma_rx_size
;
1147 priv
->rx_skbuff_dma
= kmalloc_array(rxsize
, sizeof(dma_addr_t
),
1149 if (!priv
->rx_skbuff_dma
)
1152 priv
->rx_skbuff
= kmalloc_array(rxsize
, sizeof(struct sk_buff
*),
1154 if (!priv
->rx_skbuff
)
1157 priv
->tx_skbuff_dma
= kmalloc_array(txsize
,
1158 sizeof(*priv
->tx_skbuff_dma
),
1160 if (!priv
->tx_skbuff_dma
)
1161 goto err_tx_skbuff_dma
;
1163 priv
->tx_skbuff
= kmalloc_array(txsize
, sizeof(struct sk_buff
*),
1165 if (!priv
->tx_skbuff
)
1168 if (priv
->extend_desc
) {
1169 priv
->dma_erx
= dma_alloc_coherent(priv
->device
, rxsize
*
1177 priv
->dma_etx
= dma_alloc_coherent(priv
->device
, txsize
*
1182 if (!priv
->dma_etx
) {
1183 dma_free_coherent(priv
->device
, priv
->dma_rx_size
*
1184 sizeof(struct dma_extended_desc
),
1185 priv
->dma_erx
, priv
->dma_rx_phy
);
1189 priv
->dma_rx
= dma_alloc_coherent(priv
->device
, rxsize
*
1190 sizeof(struct dma_desc
),
1196 priv
->dma_tx
= dma_alloc_coherent(priv
->device
, txsize
*
1197 sizeof(struct dma_desc
),
1200 if (!priv
->dma_tx
) {
1201 dma_free_coherent(priv
->device
, priv
->dma_rx_size
*
1202 sizeof(struct dma_desc
),
1203 priv
->dma_rx
, priv
->dma_rx_phy
);
1211 kfree(priv
->tx_skbuff
);
1213 kfree(priv
->tx_skbuff_dma
);
1215 kfree(priv
->rx_skbuff
);
1217 kfree(priv
->rx_skbuff_dma
);
1221 static void free_dma_desc_resources(struct stmmac_priv
*priv
)
1223 /* Release the DMA TX/RX socket buffers */
1224 dma_free_rx_skbufs(priv
);
1225 dma_free_tx_skbufs(priv
);
1227 /* Free DMA regions of consistent memory previously allocated */
1228 if (!priv
->extend_desc
) {
1229 dma_free_coherent(priv
->device
,
1230 priv
->dma_tx_size
* sizeof(struct dma_desc
),
1231 priv
->dma_tx
, priv
->dma_tx_phy
);
1232 dma_free_coherent(priv
->device
,
1233 priv
->dma_rx_size
* sizeof(struct dma_desc
),
1234 priv
->dma_rx
, priv
->dma_rx_phy
);
1236 dma_free_coherent(priv
->device
, priv
->dma_tx_size
*
1237 sizeof(struct dma_extended_desc
),
1238 priv
->dma_etx
, priv
->dma_tx_phy
);
1239 dma_free_coherent(priv
->device
, priv
->dma_rx_size
*
1240 sizeof(struct dma_extended_desc
),
1241 priv
->dma_erx
, priv
->dma_rx_phy
);
1243 kfree(priv
->rx_skbuff_dma
);
1244 kfree(priv
->rx_skbuff
);
1245 kfree(priv
->tx_skbuff_dma
);
1246 kfree(priv
->tx_skbuff
);
1250 * stmmac_dma_operation_mode - HW DMA operation mode
1251 * @priv: driver private structure
1252 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
1253 * or Store-And-Forward capability.
1255 static void stmmac_dma_operation_mode(struct stmmac_priv
*priv
)
1257 if (priv
->plat
->force_thresh_dma_mode
)
1258 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, tc
);
1259 else if (priv
->plat
->force_sf_dma_mode
|| priv
->plat
->tx_coe
) {
1261 * In case of GMAC, SF mode can be enabled
1262 * to perform the TX COE in HW. This depends on:
1263 * 1) TX COE if actually supported
1264 * 2) There is no bugged Jumbo frame support
1265 * that needs to not insert csum in the TDES.
1267 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, SF_DMA_MODE
, SF_DMA_MODE
);
1270 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, SF_DMA_MODE
);
1275 * @priv: driver private structure
1276 * Description: it reclaims resources after transmission completes.
1278 static void stmmac_tx_clean(struct stmmac_priv
*priv
)
1280 unsigned int txsize
= priv
->dma_tx_size
;
1282 spin_lock(&priv
->tx_lock
);
1284 priv
->xstats
.tx_clean
++;
1286 while (priv
->dirty_tx
!= priv
->cur_tx
) {
1288 unsigned int entry
= priv
->dirty_tx
% txsize
;
1289 struct sk_buff
*skb
= priv
->tx_skbuff
[entry
];
1292 if (priv
->extend_desc
)
1293 p
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
1295 p
= priv
->dma_tx
+ entry
;
1297 /* Check if the descriptor is owned by the DMA. */
1298 if (priv
->hw
->desc
->get_tx_owner(p
))
1301 /* Verify tx error by looking at the last segment. */
1302 last
= priv
->hw
->desc
->get_tx_ls(p
);
1305 priv
->hw
->desc
->tx_status(&priv
->dev
->stats
,
1308 if (likely(tx_error
== 0)) {
1309 priv
->dev
->stats
.tx_packets
++;
1310 priv
->xstats
.tx_pkt_n
++;
1312 priv
->dev
->stats
.tx_errors
++;
1314 stmmac_get_tx_hwtstamp(priv
, entry
, skb
);
1316 if (netif_msg_tx_done(priv
))
1317 pr_debug("%s: curr %d, dirty %d\n", __func__
,
1318 priv
->cur_tx
, priv
->dirty_tx
);
1320 if (likely(priv
->tx_skbuff_dma
[entry
].buf
)) {
1321 if (priv
->tx_skbuff_dma
[entry
].map_as_page
)
1322 dma_unmap_page(priv
->device
,
1323 priv
->tx_skbuff_dma
[entry
].buf
,
1324 priv
->hw
->desc
->get_tx_len(p
),
1327 dma_unmap_single(priv
->device
,
1328 priv
->tx_skbuff_dma
[entry
].buf
,
1329 priv
->hw
->desc
->get_tx_len(p
),
1331 priv
->tx_skbuff_dma
[entry
].buf
= 0;
1332 priv
->tx_skbuff_dma
[entry
].map_as_page
= false;
1334 priv
->hw
->mode
->clean_desc3(priv
, p
);
1336 if (likely(skb
!= NULL
)) {
1337 dev_consume_skb_any(skb
);
1338 priv
->tx_skbuff
[entry
] = NULL
;
1341 priv
->hw
->desc
->release_tx_desc(p
, priv
->mode
);
1345 if (unlikely(netif_queue_stopped(priv
->dev
) &&
1346 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH(priv
))) {
1347 netif_tx_lock(priv
->dev
);
1348 if (netif_queue_stopped(priv
->dev
) &&
1349 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH(priv
)) {
1350 if (netif_msg_tx_done(priv
))
1351 pr_debug("%s: restart transmit\n", __func__
);
1352 netif_wake_queue(priv
->dev
);
1354 netif_tx_unlock(priv
->dev
);
1357 if ((priv
->eee_enabled
) && (!priv
->tx_path_in_lpi_mode
)) {
1358 stmmac_enable_eee_mode(priv
);
1359 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
1361 spin_unlock(&priv
->tx_lock
);
1364 static inline void stmmac_enable_dma_irq(struct stmmac_priv
*priv
)
1366 priv
->hw
->dma
->enable_dma_irq(priv
->ioaddr
);
1369 static inline void stmmac_disable_dma_irq(struct stmmac_priv
*priv
)
1371 priv
->hw
->dma
->disable_dma_irq(priv
->ioaddr
);
1375 * stmmac_tx_err: irq tx error mng function
1376 * @priv: driver private structure
1377 * Description: it cleans the descriptors and restarts the transmission
1378 * in case of errors.
1380 static void stmmac_tx_err(struct stmmac_priv
*priv
)
1383 int txsize
= priv
->dma_tx_size
;
1384 netif_stop_queue(priv
->dev
);
1386 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1387 dma_free_tx_skbufs(priv
);
1388 for (i
= 0; i
< txsize
; i
++)
1389 if (priv
->extend_desc
)
1390 priv
->hw
->desc
->init_tx_desc(&priv
->dma_etx
[i
].basic
,
1394 priv
->hw
->desc
->init_tx_desc(&priv
->dma_tx
[i
],
1399 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1401 priv
->dev
->stats
.tx_errors
++;
1402 netif_wake_queue(priv
->dev
);
1406 * stmmac_dma_interrupt: DMA ISR
1407 * @priv: driver private structure
1408 * Description: this is the DMA ISR. It is called by the main ISR.
1409 * It calls the dwmac dma routine to understand which type of interrupt
1410 * happened. In case of there is a Normal interrupt and either TX or RX
1411 * interrupt happened so the NAPI is scheduled.
1413 static void stmmac_dma_interrupt(struct stmmac_priv
*priv
)
1417 status
= priv
->hw
->dma
->dma_interrupt(priv
->ioaddr
, &priv
->xstats
);
1418 if (likely((status
& handle_rx
)) || (status
& handle_tx
)) {
1419 if (likely(napi_schedule_prep(&priv
->napi
))) {
1420 stmmac_disable_dma_irq(priv
);
1421 __napi_schedule(&priv
->napi
);
1424 if (unlikely(status
& tx_hard_error_bump_tc
)) {
1425 /* Try to bump up the dma threshold on this failure */
1426 if (unlikely(tc
!= SF_DMA_MODE
) && (tc
<= 256)) {
1428 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, SF_DMA_MODE
);
1429 priv
->xstats
.threshold
= tc
;
1431 } else if (unlikely(status
== tx_hard_error
))
1432 stmmac_tx_err(priv
);
1436 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1437 * @priv: driver private structure
1438 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1440 static void stmmac_mmc_setup(struct stmmac_priv
*priv
)
1442 unsigned int mode
= MMC_CNTRL_RESET_ON_READ
| MMC_CNTRL_COUNTER_RESET
|
1443 MMC_CNTRL_PRESET
| MMC_CNTRL_FULL_HALF_PRESET
;
1445 dwmac_mmc_intr_all_mask(priv
->ioaddr
);
1447 if (priv
->dma_cap
.rmon
) {
1448 dwmac_mmc_ctrl(priv
->ioaddr
, mode
);
1449 memset(&priv
->mmc
, 0, sizeof(struct stmmac_counters
));
1451 pr_info(" No MAC Management Counters available\n");
1454 static u32
stmmac_get_synopsys_id(struct stmmac_priv
*priv
)
1456 u32 hwid
= priv
->hw
->synopsys_uid
;
1458 /* Check Synopsys Id (not available on old chips) */
1460 u32 uid
= ((hwid
& 0x0000ff00) >> 8);
1461 u32 synid
= (hwid
& 0x000000ff);
1463 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1472 * stmmac_selec_desc_mode: to select among: normal/alternate/extend descriptors
1473 * @priv: driver private structure
1474 * Description: select the Enhanced/Alternate or Normal descriptors.
1475 * In case of Enhanced/Alternate, it looks at the extended descriptors are
1476 * supported by the HW cap. register.
1478 static void stmmac_selec_desc_mode(struct stmmac_priv
*priv
)
1480 if (priv
->plat
->enh_desc
) {
1481 pr_info(" Enhanced/Alternate descriptors\n");
1483 /* GMAC older than 3.50 has no extended descriptors */
1484 if (priv
->synopsys_id
>= DWMAC_CORE_3_50
) {
1485 pr_info("\tEnabled extended descriptors\n");
1486 priv
->extend_desc
= 1;
1488 pr_warn("Extended descriptors not supported\n");
1490 priv
->hw
->desc
= &enh_desc_ops
;
1492 pr_info(" Normal descriptors\n");
1493 priv
->hw
->desc
= &ndesc_ops
;
1498 * stmmac_get_hw_features: get MAC capabilities from the HW cap. register.
1499 * @priv: driver private structure
1501 * new GMAC chip generations have a new register to indicate the
1502 * presence of the optional feature/functions.
1503 * This can be also used to override the value passed through the
1504 * platform and necessary for old MAC10/100 and GMAC chips.
1506 static int stmmac_get_hw_features(struct stmmac_priv
*priv
)
1510 if (priv
->hw
->dma
->get_hw_feature
) {
1511 hw_cap
= priv
->hw
->dma
->get_hw_feature(priv
->ioaddr
);
1513 priv
->dma_cap
.mbps_10_100
= (hw_cap
& DMA_HW_FEAT_MIISEL
);
1514 priv
->dma_cap
.mbps_1000
= (hw_cap
& DMA_HW_FEAT_GMIISEL
) >> 1;
1515 priv
->dma_cap
.half_duplex
= (hw_cap
& DMA_HW_FEAT_HDSEL
) >> 2;
1516 priv
->dma_cap
.hash_filter
= (hw_cap
& DMA_HW_FEAT_HASHSEL
) >> 4;
1517 priv
->dma_cap
.multi_addr
= (hw_cap
& DMA_HW_FEAT_ADDMAC
) >> 5;
1518 priv
->dma_cap
.pcs
= (hw_cap
& DMA_HW_FEAT_PCSSEL
) >> 6;
1519 priv
->dma_cap
.sma_mdio
= (hw_cap
& DMA_HW_FEAT_SMASEL
) >> 8;
1520 priv
->dma_cap
.pmt_remote_wake_up
=
1521 (hw_cap
& DMA_HW_FEAT_RWKSEL
) >> 9;
1522 priv
->dma_cap
.pmt_magic_frame
=
1523 (hw_cap
& DMA_HW_FEAT_MGKSEL
) >> 10;
1525 priv
->dma_cap
.rmon
= (hw_cap
& DMA_HW_FEAT_MMCSEL
) >> 11;
1526 /* IEEE 1588-2002 */
1527 priv
->dma_cap
.time_stamp
=
1528 (hw_cap
& DMA_HW_FEAT_TSVER1SEL
) >> 12;
1529 /* IEEE 1588-2008 */
1530 priv
->dma_cap
.atime_stamp
=
1531 (hw_cap
& DMA_HW_FEAT_TSVER2SEL
) >> 13;
1532 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1533 priv
->dma_cap
.eee
= (hw_cap
& DMA_HW_FEAT_EEESEL
) >> 14;
1534 priv
->dma_cap
.av
= (hw_cap
& DMA_HW_FEAT_AVSEL
) >> 15;
1535 /* TX and RX csum */
1536 priv
->dma_cap
.tx_coe
= (hw_cap
& DMA_HW_FEAT_TXCOESEL
) >> 16;
1537 priv
->dma_cap
.rx_coe_type1
=
1538 (hw_cap
& DMA_HW_FEAT_RXTYP1COE
) >> 17;
1539 priv
->dma_cap
.rx_coe_type2
=
1540 (hw_cap
& DMA_HW_FEAT_RXTYP2COE
) >> 18;
1541 priv
->dma_cap
.rxfifo_over_2048
=
1542 (hw_cap
& DMA_HW_FEAT_RXFIFOSIZE
) >> 19;
1543 /* TX and RX number of channels */
1544 priv
->dma_cap
.number_rx_channel
=
1545 (hw_cap
& DMA_HW_FEAT_RXCHCNT
) >> 20;
1546 priv
->dma_cap
.number_tx_channel
=
1547 (hw_cap
& DMA_HW_FEAT_TXCHCNT
) >> 22;
1548 /* Alternate (enhanced) DESC mode */
1549 priv
->dma_cap
.enh_desc
= (hw_cap
& DMA_HW_FEAT_ENHDESSEL
) >> 24;
1556 * stmmac_check_ether_addr: check if the MAC addr is valid
1557 * @priv: driver private structure
1559 * it is to verify if the MAC address is valid, in case of failures it
1560 * generates a random MAC address
1562 static void stmmac_check_ether_addr(struct stmmac_priv
*priv
)
1564 if (!is_valid_ether_addr(priv
->dev
->dev_addr
)) {
1565 priv
->hw
->mac
->get_umac_addr(priv
->hw
,
1566 priv
->dev
->dev_addr
, 0);
1567 if (!is_valid_ether_addr(priv
->dev
->dev_addr
))
1568 eth_hw_addr_random(priv
->dev
);
1569 pr_info("%s: device MAC address %pM\n", priv
->dev
->name
,
1570 priv
->dev
->dev_addr
);
1575 * stmmac_init_dma_engine: DMA init.
1576 * @priv: driver private structure
1578 * It inits the DMA invoking the specific MAC/GMAC callback.
1579 * Some DMA parameters can be passed from the platform;
1580 * in case of these are not passed a default is kept for the MAC or GMAC.
1582 static int stmmac_init_dma_engine(struct stmmac_priv
*priv
)
1584 int pbl
= DEFAULT_DMA_PBL
, fixed_burst
= 0, burst_len
= 0;
1585 int mixed_burst
= 0;
1588 if (priv
->plat
->dma_cfg
) {
1589 pbl
= priv
->plat
->dma_cfg
->pbl
;
1590 fixed_burst
= priv
->plat
->dma_cfg
->fixed_burst
;
1591 mixed_burst
= priv
->plat
->dma_cfg
->mixed_burst
;
1592 burst_len
= priv
->plat
->dma_cfg
->burst_len
;
1595 if (priv
->extend_desc
&& (priv
->mode
== STMMAC_RING_MODE
))
1598 return priv
->hw
->dma
->init(priv
->ioaddr
, pbl
, fixed_burst
, mixed_burst
,
1599 burst_len
, priv
->dma_tx_phy
,
1600 priv
->dma_rx_phy
, atds
);
1604 * stmmac_tx_timer: mitigation sw timer for tx.
1605 * @data: data pointer
1607 * This is the timer handler to directly invoke the stmmac_tx_clean.
1609 static void stmmac_tx_timer(unsigned long data
)
1611 struct stmmac_priv
*priv
= (struct stmmac_priv
*)data
;
1613 stmmac_tx_clean(priv
);
1617 * stmmac_init_tx_coalesce: init tx mitigation options.
1618 * @priv: driver private structure
1620 * This inits the transmit coalesce parameters: i.e. timer rate,
1621 * timer handler and default threshold used for enabling the
1622 * interrupt on completion bit.
1624 static void stmmac_init_tx_coalesce(struct stmmac_priv
*priv
)
1626 priv
->tx_coal_frames
= STMMAC_TX_FRAMES
;
1627 priv
->tx_coal_timer
= STMMAC_COAL_TX_TIMER
;
1628 init_timer(&priv
->txtimer
);
1629 priv
->txtimer
.expires
= STMMAC_COAL_TIMER(priv
->tx_coal_timer
);
1630 priv
->txtimer
.data
= (unsigned long)priv
;
1631 priv
->txtimer
.function
= stmmac_tx_timer
;
1632 add_timer(&priv
->txtimer
);
1636 * stmmac_hw_setup: setup mac in a usable state.
1637 * @dev : pointer to the device structure.
1639 * This function sets up the ip in a usable state.
1641 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1644 static int stmmac_hw_setup(struct net_device
*dev
)
1646 struct stmmac_priv
*priv
= netdev_priv(dev
);
1649 /* DMA initialization and SW reset */
1650 ret
= stmmac_init_dma_engine(priv
);
1652 pr_err("%s: DMA engine initialization failed\n", __func__
);
1656 /* Copy the MAC addr into the HW */
1657 priv
->hw
->mac
->set_umac_addr(priv
->hw
, dev
->dev_addr
, 0);
1659 /* If required, perform hw setup of the bus. */
1660 if (priv
->plat
->bus_setup
)
1661 priv
->plat
->bus_setup(priv
->ioaddr
);
1663 /* Initialize the MAC Core */
1664 priv
->hw
->mac
->core_init(priv
->hw
, dev
->mtu
);
1666 ret
= priv
->hw
->mac
->rx_ipc(priv
->hw
);
1668 pr_warn(" RX IPC Checksum Offload disabled\n");
1669 priv
->plat
->rx_coe
= STMMAC_RX_COE_NONE
;
1670 priv
->hw
->rx_csum
= 0;
1673 /* Enable the MAC Rx/Tx */
1674 stmmac_set_mac(priv
->ioaddr
, true);
1676 /* Set the HW DMA mode and the COE */
1677 stmmac_dma_operation_mode(priv
);
1679 stmmac_mmc_setup(priv
);
1681 ret
= stmmac_init_ptp(priv
);
1682 if (ret
&& ret
!= -EOPNOTSUPP
)
1683 pr_warn("%s: failed PTP initialisation\n", __func__
);
1685 #ifdef CONFIG_DEBUG_FS
1686 ret
= stmmac_init_fs(dev
);
1688 pr_warn("%s: failed debugFS registration\n", __func__
);
1690 /* Start the ball rolling... */
1691 pr_debug("%s: DMA RX/TX processes started...\n", dev
->name
);
1692 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1693 priv
->hw
->dma
->start_rx(priv
->ioaddr
);
1695 /* Dump DMA/MAC registers */
1696 if (netif_msg_hw(priv
)) {
1697 priv
->hw
->mac
->dump_regs(priv
->hw
);
1698 priv
->hw
->dma
->dump_regs(priv
->ioaddr
);
1700 priv
->tx_lpi_timer
= STMMAC_DEFAULT_TWT_LS
;
1702 if ((priv
->use_riwt
) && (priv
->hw
->dma
->rx_watchdog
)) {
1703 priv
->rx_riwt
= MAX_DMA_RIWT
;
1704 priv
->hw
->dma
->rx_watchdog(priv
->ioaddr
, MAX_DMA_RIWT
);
1707 if (priv
->pcs
&& priv
->hw
->mac
->ctrl_ane
)
1708 priv
->hw
->mac
->ctrl_ane(priv
->hw
, 0);
1714 * stmmac_open - open entry point of the driver
1715 * @dev : pointer to the device structure.
1717 * This function is the open entry point of the driver.
1719 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1722 static int stmmac_open(struct net_device
*dev
)
1724 struct stmmac_priv
*priv
= netdev_priv(dev
);
1727 stmmac_check_ether_addr(priv
);
1729 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
1730 priv
->pcs
!= STMMAC_PCS_RTBI
) {
1731 ret
= stmmac_init_phy(dev
);
1733 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1739 /* Extra statistics */
1740 memset(&priv
->xstats
, 0, sizeof(struct stmmac_extra_stats
));
1741 priv
->xstats
.threshold
= tc
;
1743 /* Create and initialize the TX/RX descriptors chains. */
1744 priv
->dma_tx_size
= STMMAC_ALIGN(dma_txsize
);
1745 priv
->dma_rx_size
= STMMAC_ALIGN(dma_rxsize
);
1746 priv
->dma_buf_sz
= STMMAC_ALIGN(buf_sz
);
1748 ret
= alloc_dma_desc_resources(priv
);
1750 pr_err("%s: DMA descriptors allocation failed\n", __func__
);
1751 goto dma_desc_error
;
1754 ret
= init_dma_desc_rings(dev
, GFP_KERNEL
);
1756 pr_err("%s: DMA descriptors initialization failed\n", __func__
);
1760 ret
= stmmac_hw_setup(dev
);
1762 pr_err("%s: Hw setup failed\n", __func__
);
1766 stmmac_init_tx_coalesce(priv
);
1769 phy_start(priv
->phydev
);
1771 /* Request the IRQ lines */
1772 ret
= request_irq(dev
->irq
, stmmac_interrupt
,
1773 IRQF_SHARED
, dev
->name
, dev
);
1774 if (unlikely(ret
< 0)) {
1775 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1776 __func__
, dev
->irq
, ret
);
1780 /* Request the Wake IRQ in case of another line is used for WoL */
1781 if (priv
->wol_irq
!= dev
->irq
) {
1782 ret
= request_irq(priv
->wol_irq
, stmmac_interrupt
,
1783 IRQF_SHARED
, dev
->name
, dev
);
1784 if (unlikely(ret
< 0)) {
1785 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1786 __func__
, priv
->wol_irq
, ret
);
1791 /* Request the IRQ lines */
1792 if (priv
->lpi_irq
> 0) {
1793 ret
= request_irq(priv
->lpi_irq
, stmmac_interrupt
, IRQF_SHARED
,
1795 if (unlikely(ret
< 0)) {
1796 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1797 __func__
, priv
->lpi_irq
, ret
);
1802 napi_enable(&priv
->napi
);
1803 netif_start_queue(dev
);
1808 if (priv
->wol_irq
!= dev
->irq
)
1809 free_irq(priv
->wol_irq
, dev
);
1811 free_irq(dev
->irq
, dev
);
1814 free_dma_desc_resources(priv
);
1817 phy_disconnect(priv
->phydev
);
1823 * stmmac_release - close entry point of the driver
1824 * @dev : device pointer.
1826 * This is the stop entry point of the driver.
1828 static int stmmac_release(struct net_device
*dev
)
1830 struct stmmac_priv
*priv
= netdev_priv(dev
);
1832 if (priv
->eee_enabled
)
1833 del_timer_sync(&priv
->eee_ctrl_timer
);
1835 /* Stop and disconnect the PHY */
1837 phy_stop(priv
->phydev
);
1838 phy_disconnect(priv
->phydev
);
1839 priv
->phydev
= NULL
;
1842 netif_stop_queue(dev
);
1844 napi_disable(&priv
->napi
);
1846 del_timer_sync(&priv
->txtimer
);
1848 /* Free the IRQ lines */
1849 free_irq(dev
->irq
, dev
);
1850 if (priv
->wol_irq
!= dev
->irq
)
1851 free_irq(priv
->wol_irq
, dev
);
1852 if (priv
->lpi_irq
> 0)
1853 free_irq(priv
->lpi_irq
, dev
);
1855 /* Stop TX/RX DMA and clear the descriptors */
1856 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1857 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
1859 /* Release and free the Rx/Tx resources */
1860 free_dma_desc_resources(priv
);
1862 /* Disable the MAC Rx/Tx */
1863 stmmac_set_mac(priv
->ioaddr
, false);
1865 netif_carrier_off(dev
);
1867 #ifdef CONFIG_DEBUG_FS
1871 stmmac_release_ptp(priv
);
1877 * stmmac_xmit: Tx entry point of the driver
1878 * @skb : the socket buffer
1879 * @dev : device pointer
1880 * Description : this is the tx entry point of the driver.
1881 * It programs the chain or the ring and supports oversized frames
1884 static netdev_tx_t
stmmac_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1886 struct stmmac_priv
*priv
= netdev_priv(dev
);
1887 unsigned int txsize
= priv
->dma_tx_size
;
1889 int i
, csum_insertion
= 0, is_jumbo
= 0;
1890 int nfrags
= skb_shinfo(skb
)->nr_frags
;
1891 struct dma_desc
*desc
, *first
;
1892 unsigned int nopaged_len
= skb_headlen(skb
);
1893 unsigned int enh_desc
= priv
->plat
->enh_desc
;
1895 spin_lock(&priv
->tx_lock
);
1897 if (unlikely(stmmac_tx_avail(priv
) < nfrags
+ 1)) {
1898 spin_unlock(&priv
->tx_lock
);
1899 if (!netif_queue_stopped(dev
)) {
1900 netif_stop_queue(dev
);
1901 /* This is a hard error, log it. */
1902 pr_err("%s: Tx Ring full when queue awake\n", __func__
);
1904 return NETDEV_TX_BUSY
;
1907 if (priv
->tx_path_in_lpi_mode
)
1908 stmmac_disable_eee_mode(priv
);
1910 entry
= priv
->cur_tx
% txsize
;
1912 csum_insertion
= (skb
->ip_summed
== CHECKSUM_PARTIAL
);
1914 if (priv
->extend_desc
)
1915 desc
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
1917 desc
= priv
->dma_tx
+ entry
;
1921 /* To program the descriptors according to the size of the frame */
1923 is_jumbo
= priv
->hw
->mode
->is_jumbo_frm(skb
->len
, enh_desc
);
1925 if (likely(!is_jumbo
)) {
1926 desc
->des2
= dma_map_single(priv
->device
, skb
->data
,
1927 nopaged_len
, DMA_TO_DEVICE
);
1928 if (dma_mapping_error(priv
->device
, desc
->des2
))
1930 priv
->tx_skbuff_dma
[entry
].buf
= desc
->des2
;
1931 priv
->hw
->desc
->prepare_tx_desc(desc
, 1, nopaged_len
,
1932 csum_insertion
, priv
->mode
);
1935 entry
= priv
->hw
->mode
->jumbo_frm(priv
, skb
, csum_insertion
);
1936 if (unlikely(entry
< 0))
1940 for (i
= 0; i
< nfrags
; i
++) {
1941 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1942 int len
= skb_frag_size(frag
);
1944 priv
->tx_skbuff
[entry
] = NULL
;
1945 entry
= (++priv
->cur_tx
) % txsize
;
1946 if (priv
->extend_desc
)
1947 desc
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
1949 desc
= priv
->dma_tx
+ entry
;
1951 desc
->des2
= skb_frag_dma_map(priv
->device
, frag
, 0, len
,
1953 if (dma_mapping_error(priv
->device
, desc
->des2
))
1954 goto dma_map_err
; /* should reuse desc w/o issues */
1956 priv
->tx_skbuff_dma
[entry
].buf
= desc
->des2
;
1957 priv
->tx_skbuff_dma
[entry
].map_as_page
= true;
1958 priv
->hw
->desc
->prepare_tx_desc(desc
, 0, len
, csum_insertion
,
1961 priv
->hw
->desc
->set_tx_owner(desc
);
1965 priv
->tx_skbuff
[entry
] = skb
;
1967 /* Finalize the latest segment. */
1968 priv
->hw
->desc
->close_tx_desc(desc
);
1971 /* According to the coalesce parameter the IC bit for the latest
1972 * segment could be reset and the timer re-started to invoke the
1973 * stmmac_tx function. This approach takes care about the fragments.
1975 priv
->tx_count_frames
+= nfrags
+ 1;
1976 if (priv
->tx_coal_frames
> priv
->tx_count_frames
) {
1977 priv
->hw
->desc
->clear_tx_ic(desc
);
1978 priv
->xstats
.tx_reset_ic_bit
++;
1979 mod_timer(&priv
->txtimer
,
1980 STMMAC_COAL_TIMER(priv
->tx_coal_timer
));
1982 priv
->tx_count_frames
= 0;
1984 /* To avoid raise condition */
1985 priv
->hw
->desc
->set_tx_owner(first
);
1990 if (netif_msg_pktdata(priv
)) {
1991 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
1992 __func__
, (priv
->cur_tx
% txsize
),
1993 (priv
->dirty_tx
% txsize
), entry
, first
, nfrags
);
1995 if (priv
->extend_desc
)
1996 stmmac_display_ring((void *)priv
->dma_etx
, txsize
, 1);
1998 stmmac_display_ring((void *)priv
->dma_tx
, txsize
, 0);
2000 pr_debug(">>> frame to be transmitted: ");
2001 print_pkt(skb
->data
, skb
->len
);
2003 if (unlikely(stmmac_tx_avail(priv
) <= (MAX_SKB_FRAGS
+ 1))) {
2004 if (netif_msg_hw(priv
))
2005 pr_debug("%s: stop transmitted packets\n", __func__
);
2006 netif_stop_queue(dev
);
2009 dev
->stats
.tx_bytes
+= skb
->len
;
2011 if (unlikely((skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) &&
2012 priv
->hwts_tx_en
)) {
2013 /* declare that device is doing timestamping */
2014 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
2015 priv
->hw
->desc
->enable_tx_timestamp(first
);
2018 if (!priv
->hwts_tx_en
)
2019 skb_tx_timestamp(skb
);
2021 priv
->hw
->dma
->enable_dma_transmission(priv
->ioaddr
);
2023 spin_unlock(&priv
->tx_lock
);
2024 return NETDEV_TX_OK
;
2027 spin_unlock(&priv
->tx_lock
);
2028 dev_err(priv
->device
, "Tx dma map failed\n");
2030 priv
->dev
->stats
.tx_dropped
++;
2031 return NETDEV_TX_OK
;
2034 static void stmmac_rx_vlan(struct net_device
*dev
, struct sk_buff
*skb
)
2036 struct ethhdr
*ehdr
;
2039 if ((dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) ==
2040 NETIF_F_HW_VLAN_CTAG_RX
&&
2041 !__vlan_get_tag(skb
, &vlanid
)) {
2042 /* pop the vlan tag */
2043 ehdr
= (struct ethhdr
*)skb
->data
;
2044 memmove(skb
->data
+ VLAN_HLEN
, ehdr
, ETH_ALEN
* 2);
2045 skb_pull(skb
, VLAN_HLEN
);
2046 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vlanid
);
2052 * stmmac_rx_refill: refill used skb preallocated buffers
2053 * @priv: driver private structure
2054 * Description : this is to reallocate the skb for the reception process
2055 * that is based on zero-copy.
2057 static inline void stmmac_rx_refill(struct stmmac_priv
*priv
)
2059 unsigned int rxsize
= priv
->dma_rx_size
;
2060 int bfsize
= priv
->dma_buf_sz
;
2062 for (; priv
->cur_rx
- priv
->dirty_rx
> 0; priv
->dirty_rx
++) {
2063 unsigned int entry
= priv
->dirty_rx
% rxsize
;
2066 if (priv
->extend_desc
)
2067 p
= (struct dma_desc
*)(priv
->dma_erx
+ entry
);
2069 p
= priv
->dma_rx
+ entry
;
2071 if (likely(priv
->rx_skbuff
[entry
] == NULL
)) {
2072 struct sk_buff
*skb
;
2074 skb
= netdev_alloc_skb_ip_align(priv
->dev
, bfsize
);
2076 if (unlikely(skb
== NULL
))
2079 priv
->rx_skbuff
[entry
] = skb
;
2080 priv
->rx_skbuff_dma
[entry
] =
2081 dma_map_single(priv
->device
, skb
->data
, bfsize
,
2083 if (dma_mapping_error(priv
->device
,
2084 priv
->rx_skbuff_dma
[entry
])) {
2085 dev_err(priv
->device
, "Rx dma map failed\n");
2089 p
->des2
= priv
->rx_skbuff_dma
[entry
];
2091 priv
->hw
->mode
->refill_desc3(priv
, p
);
2093 if (netif_msg_rx_status(priv
))
2094 pr_debug("\trefill entry #%d\n", entry
);
2097 priv
->hw
->desc
->set_rx_owner(p
);
2103 * stmmac_rx_refill: refill used skb preallocated buffers
2104 * @priv: driver private structure
2105 * @limit: napi bugget.
2106 * Description : this the function called by the napi poll method.
2107 * It gets all the frames inside the ring.
2109 static int stmmac_rx(struct stmmac_priv
*priv
, int limit
)
2111 unsigned int rxsize
= priv
->dma_rx_size
;
2112 unsigned int entry
= priv
->cur_rx
% rxsize
;
2113 unsigned int next_entry
;
2114 unsigned int count
= 0;
2115 int coe
= priv
->hw
->rx_csum
;
2117 if (netif_msg_rx_status(priv
)) {
2118 pr_debug("%s: descriptor ring:\n", __func__
);
2119 if (priv
->extend_desc
)
2120 stmmac_display_ring((void *)priv
->dma_erx
, rxsize
, 1);
2122 stmmac_display_ring((void *)priv
->dma_rx
, rxsize
, 0);
2124 while (count
< limit
) {
2128 if (priv
->extend_desc
)
2129 p
= (struct dma_desc
*)(priv
->dma_erx
+ entry
);
2131 p
= priv
->dma_rx
+ entry
;
2133 if (priv
->hw
->desc
->get_rx_owner(p
))
2138 next_entry
= (++priv
->cur_rx
) % rxsize
;
2139 if (priv
->extend_desc
)
2140 prefetch(priv
->dma_erx
+ next_entry
);
2142 prefetch(priv
->dma_rx
+ next_entry
);
2144 /* read the status of the incoming frame */
2145 status
= priv
->hw
->desc
->rx_status(&priv
->dev
->stats
,
2147 if ((priv
->extend_desc
) && (priv
->hw
->desc
->rx_extended_status
))
2148 priv
->hw
->desc
->rx_extended_status(&priv
->dev
->stats
,
2152 if (unlikely(status
== discard_frame
)) {
2153 priv
->dev
->stats
.rx_errors
++;
2154 if (priv
->hwts_rx_en
&& !priv
->extend_desc
) {
2155 /* DESC2 & DESC3 will be overwitten by device
2156 * with timestamp value, hence reinitialize
2157 * them in stmmac_rx_refill() function so that
2158 * device can reuse it.
2160 priv
->rx_skbuff
[entry
] = NULL
;
2161 dma_unmap_single(priv
->device
,
2162 priv
->rx_skbuff_dma
[entry
],
2167 struct sk_buff
*skb
;
2170 frame_len
= priv
->hw
->desc
->get_rx_frame_len(p
, coe
);
2172 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2173 * Type frames (LLC/LLC-SNAP)
2175 if (unlikely(status
!= llc_snap
))
2176 frame_len
-= ETH_FCS_LEN
;
2178 if (netif_msg_rx_status(priv
)) {
2179 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2181 if (frame_len
> ETH_FRAME_LEN
)
2182 pr_debug("\tframe size %d, COE: %d\n",
2185 skb
= priv
->rx_skbuff
[entry
];
2186 if (unlikely(!skb
)) {
2187 pr_err("%s: Inconsistent Rx descriptor chain\n",
2189 priv
->dev
->stats
.rx_dropped
++;
2192 prefetch(skb
->data
- NET_IP_ALIGN
);
2193 priv
->rx_skbuff
[entry
] = NULL
;
2195 stmmac_get_rx_hwtstamp(priv
, entry
, skb
);
2197 skb_put(skb
, frame_len
);
2198 dma_unmap_single(priv
->device
,
2199 priv
->rx_skbuff_dma
[entry
],
2200 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
2202 if (netif_msg_pktdata(priv
)) {
2203 pr_debug("frame received (%dbytes)", frame_len
);
2204 print_pkt(skb
->data
, frame_len
);
2207 stmmac_rx_vlan(priv
->dev
, skb
);
2209 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
2212 skb_checksum_none_assert(skb
);
2214 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2216 napi_gro_receive(&priv
->napi
, skb
);
2218 priv
->dev
->stats
.rx_packets
++;
2219 priv
->dev
->stats
.rx_bytes
+= frame_len
;
2224 stmmac_rx_refill(priv
);
2226 priv
->xstats
.rx_pkt_n
+= count
;
2232 * stmmac_poll - stmmac poll method (NAPI)
2233 * @napi : pointer to the napi structure.
2234 * @budget : maximum number of packets that the current CPU can receive from
2237 * To look at the incoming frames and clear the tx resources.
2239 static int stmmac_poll(struct napi_struct
*napi
, int budget
)
2241 struct stmmac_priv
*priv
= container_of(napi
, struct stmmac_priv
, napi
);
2244 priv
->xstats
.napi_poll
++;
2245 stmmac_tx_clean(priv
);
2247 work_done
= stmmac_rx(priv
, budget
);
2248 if (work_done
< budget
) {
2249 napi_complete(napi
);
2250 stmmac_enable_dma_irq(priv
);
2257 * @dev : Pointer to net device structure
2258 * Description: this function is called when a packet transmission fails to
2259 * complete within a reasonable time. The driver will mark the error in the
2260 * netdev structure and arrange for the device to be reset to a sane state
2261 * in order to transmit a new packet.
2263 static void stmmac_tx_timeout(struct net_device
*dev
)
2265 struct stmmac_priv
*priv
= netdev_priv(dev
);
2267 /* Clear Tx resources and restart transmitting again */
2268 stmmac_tx_err(priv
);
2272 * stmmac_set_rx_mode - entry point for multicast addressing
2273 * @dev : pointer to the device structure
2275 * This function is a driver entry point which gets called by the kernel
2276 * whenever multicast addresses must be enabled/disabled.
2280 static void stmmac_set_rx_mode(struct net_device
*dev
)
2282 struct stmmac_priv
*priv
= netdev_priv(dev
);
2284 priv
->hw
->mac
->set_filter(priv
->hw
, dev
);
2288 * stmmac_change_mtu - entry point to change MTU size for the device.
2289 * @dev : device pointer.
2290 * @new_mtu : the new MTU size for the device.
2291 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2292 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2293 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2295 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2298 static int stmmac_change_mtu(struct net_device
*dev
, int new_mtu
)
2300 struct stmmac_priv
*priv
= netdev_priv(dev
);
2303 if (netif_running(dev
)) {
2304 pr_err("%s: must be stopped to change its MTU\n", dev
->name
);
2308 if (priv
->plat
->enh_desc
)
2309 max_mtu
= JUMBO_LEN
;
2311 max_mtu
= SKB_MAX_HEAD(NET_SKB_PAD
+ NET_IP_ALIGN
);
2313 if (priv
->plat
->maxmtu
< max_mtu
)
2314 max_mtu
= priv
->plat
->maxmtu
;
2316 if ((new_mtu
< 46) || (new_mtu
> max_mtu
)) {
2317 pr_err("%s: invalid MTU, max MTU is: %d\n", dev
->name
, max_mtu
);
2322 netdev_update_features(dev
);
2327 static netdev_features_t
stmmac_fix_features(struct net_device
*dev
,
2328 netdev_features_t features
)
2330 struct stmmac_priv
*priv
= netdev_priv(dev
);
2332 if (priv
->plat
->rx_coe
== STMMAC_RX_COE_NONE
)
2333 features
&= ~NETIF_F_RXCSUM
;
2335 if (!priv
->plat
->tx_coe
)
2336 features
&= ~NETIF_F_ALL_CSUM
;
2338 /* Some GMAC devices have a bugged Jumbo frame support that
2339 * needs to have the Tx COE disabled for oversized frames
2340 * (due to limited buffer sizes). In this case we disable
2341 * the TX csum insertionin the TDES and not use SF.
2343 if (priv
->plat
->bugged_jumbo
&& (dev
->mtu
> ETH_DATA_LEN
))
2344 features
&= ~NETIF_F_ALL_CSUM
;
2349 static int stmmac_set_features(struct net_device
*netdev
,
2350 netdev_features_t features
)
2352 struct stmmac_priv
*priv
= netdev_priv(netdev
);
2354 /* Keep the COE Type in case of csum is supporting */
2355 if (features
& NETIF_F_RXCSUM
)
2356 priv
->hw
->rx_csum
= priv
->plat
->rx_coe
;
2358 priv
->hw
->rx_csum
= 0;
2359 /* No check needed because rx_coe has been set before and it will be
2360 * fixed in case of issue.
2362 priv
->hw
->mac
->rx_ipc(priv
->hw
);
2368 * stmmac_interrupt - main ISR
2369 * @irq: interrupt number.
2370 * @dev_id: to pass the net device pointer.
2371 * Description: this is the main driver interrupt service routine.
2372 * It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
2375 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
)
2377 struct net_device
*dev
= (struct net_device
*)dev_id
;
2378 struct stmmac_priv
*priv
= netdev_priv(dev
);
2381 pm_wakeup_event(priv
->device
, 0);
2383 if (unlikely(!dev
)) {
2384 pr_err("%s: invalid dev pointer\n", __func__
);
2388 /* To handle GMAC own interrupts */
2389 if (priv
->plat
->has_gmac
) {
2390 int status
= priv
->hw
->mac
->host_irq_status(priv
->hw
,
2392 if (unlikely(status
)) {
2393 /* For LPI we need to save the tx status */
2394 if (status
& CORE_IRQ_TX_PATH_IN_LPI_MODE
)
2395 priv
->tx_path_in_lpi_mode
= true;
2396 if (status
& CORE_IRQ_TX_PATH_EXIT_LPI_MODE
)
2397 priv
->tx_path_in_lpi_mode
= false;
2401 /* To handle DMA interrupts */
2402 stmmac_dma_interrupt(priv
);
2407 #ifdef CONFIG_NET_POLL_CONTROLLER
2408 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2409 * to allow network I/O with interrupts disabled.
2411 static void stmmac_poll_controller(struct net_device
*dev
)
2413 disable_irq(dev
->irq
);
2414 stmmac_interrupt(dev
->irq
, dev
);
2415 enable_irq(dev
->irq
);
2420 * stmmac_ioctl - Entry point for the Ioctl
2421 * @dev: Device pointer.
2422 * @rq: An IOCTL specefic structure, that can contain a pointer to
2423 * a proprietary structure used to pass information to the driver.
2424 * @cmd: IOCTL command
2426 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2428 static int stmmac_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2430 struct stmmac_priv
*priv
= netdev_priv(dev
);
2431 int ret
= -EOPNOTSUPP
;
2433 if (!netif_running(dev
))
2442 ret
= phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
2445 ret
= stmmac_hwtstamp_ioctl(dev
, rq
);
2454 #ifdef CONFIG_DEBUG_FS
2455 static struct dentry
*stmmac_fs_dir
;
2456 static struct dentry
*stmmac_rings_status
;
2457 static struct dentry
*stmmac_dma_cap
;
2459 static void sysfs_display_ring(void *head
, int size
, int extend_desc
,
2460 struct seq_file
*seq
)
2463 struct dma_extended_desc
*ep
= (struct dma_extended_desc
*)head
;
2464 struct dma_desc
*p
= (struct dma_desc
*)head
;
2466 for (i
= 0; i
< size
; i
++) {
2470 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2471 i
, (unsigned int)virt_to_phys(ep
),
2472 (unsigned int)x
, (unsigned int)(x
>> 32),
2473 ep
->basic
.des2
, ep
->basic
.des3
);
2477 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2478 i
, (unsigned int)virt_to_phys(ep
),
2479 (unsigned int)x
, (unsigned int)(x
>> 32),
2483 seq_printf(seq
, "\n");
2487 static int stmmac_sysfs_ring_read(struct seq_file
*seq
, void *v
)
2489 struct net_device
*dev
= seq
->private;
2490 struct stmmac_priv
*priv
= netdev_priv(dev
);
2491 unsigned int txsize
= priv
->dma_tx_size
;
2492 unsigned int rxsize
= priv
->dma_rx_size
;
2494 if (priv
->extend_desc
) {
2495 seq_printf(seq
, "Extended RX descriptor ring:\n");
2496 sysfs_display_ring((void *)priv
->dma_erx
, rxsize
, 1, seq
);
2497 seq_printf(seq
, "Extended TX descriptor ring:\n");
2498 sysfs_display_ring((void *)priv
->dma_etx
, txsize
, 1, seq
);
2500 seq_printf(seq
, "RX descriptor ring:\n");
2501 sysfs_display_ring((void *)priv
->dma_rx
, rxsize
, 0, seq
);
2502 seq_printf(seq
, "TX descriptor ring:\n");
2503 sysfs_display_ring((void *)priv
->dma_tx
, txsize
, 0, seq
);
2509 static int stmmac_sysfs_ring_open(struct inode
*inode
, struct file
*file
)
2511 return single_open(file
, stmmac_sysfs_ring_read
, inode
->i_private
);
2514 static const struct file_operations stmmac_rings_status_fops
= {
2515 .owner
= THIS_MODULE
,
2516 .open
= stmmac_sysfs_ring_open
,
2518 .llseek
= seq_lseek
,
2519 .release
= single_release
,
2522 static int stmmac_sysfs_dma_cap_read(struct seq_file
*seq
, void *v
)
2524 struct net_device
*dev
= seq
->private;
2525 struct stmmac_priv
*priv
= netdev_priv(dev
);
2527 if (!priv
->hw_cap_support
) {
2528 seq_printf(seq
, "DMA HW features not supported\n");
2532 seq_printf(seq
, "==============================\n");
2533 seq_printf(seq
, "\tDMA HW features\n");
2534 seq_printf(seq
, "==============================\n");
2536 seq_printf(seq
, "\t10/100 Mbps %s\n",
2537 (priv
->dma_cap
.mbps_10_100
) ? "Y" : "N");
2538 seq_printf(seq
, "\t1000 Mbps %s\n",
2539 (priv
->dma_cap
.mbps_1000
) ? "Y" : "N");
2540 seq_printf(seq
, "\tHalf duple %s\n",
2541 (priv
->dma_cap
.half_duplex
) ? "Y" : "N");
2542 seq_printf(seq
, "\tHash Filter: %s\n",
2543 (priv
->dma_cap
.hash_filter
) ? "Y" : "N");
2544 seq_printf(seq
, "\tMultiple MAC address registers: %s\n",
2545 (priv
->dma_cap
.multi_addr
) ? "Y" : "N");
2546 seq_printf(seq
, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2547 (priv
->dma_cap
.pcs
) ? "Y" : "N");
2548 seq_printf(seq
, "\tSMA (MDIO) Interface: %s\n",
2549 (priv
->dma_cap
.sma_mdio
) ? "Y" : "N");
2550 seq_printf(seq
, "\tPMT Remote wake up: %s\n",
2551 (priv
->dma_cap
.pmt_remote_wake_up
) ? "Y" : "N");
2552 seq_printf(seq
, "\tPMT Magic Frame: %s\n",
2553 (priv
->dma_cap
.pmt_magic_frame
) ? "Y" : "N");
2554 seq_printf(seq
, "\tRMON module: %s\n",
2555 (priv
->dma_cap
.rmon
) ? "Y" : "N");
2556 seq_printf(seq
, "\tIEEE 1588-2002 Time Stamp: %s\n",
2557 (priv
->dma_cap
.time_stamp
) ? "Y" : "N");
2558 seq_printf(seq
, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2559 (priv
->dma_cap
.atime_stamp
) ? "Y" : "N");
2560 seq_printf(seq
, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2561 (priv
->dma_cap
.eee
) ? "Y" : "N");
2562 seq_printf(seq
, "\tAV features: %s\n", (priv
->dma_cap
.av
) ? "Y" : "N");
2563 seq_printf(seq
, "\tChecksum Offload in TX: %s\n",
2564 (priv
->dma_cap
.tx_coe
) ? "Y" : "N");
2565 seq_printf(seq
, "\tIP Checksum Offload (type1) in RX: %s\n",
2566 (priv
->dma_cap
.rx_coe_type1
) ? "Y" : "N");
2567 seq_printf(seq
, "\tIP Checksum Offload (type2) in RX: %s\n",
2568 (priv
->dma_cap
.rx_coe_type2
) ? "Y" : "N");
2569 seq_printf(seq
, "\tRXFIFO > 2048bytes: %s\n",
2570 (priv
->dma_cap
.rxfifo_over_2048
) ? "Y" : "N");
2571 seq_printf(seq
, "\tNumber of Additional RX channel: %d\n",
2572 priv
->dma_cap
.number_rx_channel
);
2573 seq_printf(seq
, "\tNumber of Additional TX channel: %d\n",
2574 priv
->dma_cap
.number_tx_channel
);
2575 seq_printf(seq
, "\tEnhanced descriptors: %s\n",
2576 (priv
->dma_cap
.enh_desc
) ? "Y" : "N");
2581 static int stmmac_sysfs_dma_cap_open(struct inode
*inode
, struct file
*file
)
2583 return single_open(file
, stmmac_sysfs_dma_cap_read
, inode
->i_private
);
2586 static const struct file_operations stmmac_dma_cap_fops
= {
2587 .owner
= THIS_MODULE
,
2588 .open
= stmmac_sysfs_dma_cap_open
,
2590 .llseek
= seq_lseek
,
2591 .release
= single_release
,
2594 static int stmmac_init_fs(struct net_device
*dev
)
2596 /* Create debugfs entries */
2597 stmmac_fs_dir
= debugfs_create_dir(STMMAC_RESOURCE_NAME
, NULL
);
2599 if (!stmmac_fs_dir
|| IS_ERR(stmmac_fs_dir
)) {
2600 pr_err("ERROR %s, debugfs create directory failed\n",
2601 STMMAC_RESOURCE_NAME
);
2606 /* Entry to report DMA RX/TX rings */
2607 stmmac_rings_status
= debugfs_create_file("descriptors_status",
2608 S_IRUGO
, stmmac_fs_dir
, dev
,
2609 &stmmac_rings_status_fops
);
2611 if (!stmmac_rings_status
|| IS_ERR(stmmac_rings_status
)) {
2612 pr_info("ERROR creating stmmac ring debugfs file\n");
2613 debugfs_remove(stmmac_fs_dir
);
2618 /* Entry to report the DMA HW features */
2619 stmmac_dma_cap
= debugfs_create_file("dma_cap", S_IRUGO
, stmmac_fs_dir
,
2620 dev
, &stmmac_dma_cap_fops
);
2622 if (!stmmac_dma_cap
|| IS_ERR(stmmac_dma_cap
)) {
2623 pr_info("ERROR creating stmmac MMC debugfs file\n");
2624 debugfs_remove(stmmac_rings_status
);
2625 debugfs_remove(stmmac_fs_dir
);
2633 static void stmmac_exit_fs(void)
2635 debugfs_remove(stmmac_rings_status
);
2636 debugfs_remove(stmmac_dma_cap
);
2637 debugfs_remove(stmmac_fs_dir
);
2639 #endif /* CONFIG_DEBUG_FS */
2641 static const struct net_device_ops stmmac_netdev_ops
= {
2642 .ndo_open
= stmmac_open
,
2643 .ndo_start_xmit
= stmmac_xmit
,
2644 .ndo_stop
= stmmac_release
,
2645 .ndo_change_mtu
= stmmac_change_mtu
,
2646 .ndo_fix_features
= stmmac_fix_features
,
2647 .ndo_set_features
= stmmac_set_features
,
2648 .ndo_set_rx_mode
= stmmac_set_rx_mode
,
2649 .ndo_tx_timeout
= stmmac_tx_timeout
,
2650 .ndo_do_ioctl
= stmmac_ioctl
,
2651 #ifdef CONFIG_NET_POLL_CONTROLLER
2652 .ndo_poll_controller
= stmmac_poll_controller
,
2654 .ndo_set_mac_address
= eth_mac_addr
,
2658 * stmmac_hw_init - Init the MAC device
2659 * @priv: driver private structure
2660 * Description: this function detects which MAC device
2661 * (GMAC/MAC10-100) has to attached, checks the HW capability
2662 * (if supported) and sets the driver's features (for example
2663 * to use the ring or chaine mode or support the normal/enh
2664 * descriptor structure).
2666 static int stmmac_hw_init(struct stmmac_priv
*priv
)
2668 struct mac_device_info
*mac
;
2670 /* Identify the MAC HW device */
2671 if (priv
->plat
->has_gmac
) {
2672 priv
->dev
->priv_flags
|= IFF_UNICAST_FLT
;
2673 mac
= dwmac1000_setup(priv
->ioaddr
,
2674 priv
->plat
->multicast_filter_bins
,
2675 priv
->plat
->unicast_filter_entries
);
2677 mac
= dwmac100_setup(priv
->ioaddr
);
2684 /* Get and dump the chip ID */
2685 priv
->synopsys_id
= stmmac_get_synopsys_id(priv
);
2687 /* To use the chained or ring mode */
2689 priv
->hw
->mode
= &chain_mode_ops
;
2690 pr_info(" Chain mode enabled\n");
2691 priv
->mode
= STMMAC_CHAIN_MODE
;
2693 priv
->hw
->mode
= &ring_mode_ops
;
2694 pr_info(" Ring mode enabled\n");
2695 priv
->mode
= STMMAC_RING_MODE
;
2698 /* Get the HW capability (new GMAC newer than 3.50a) */
2699 priv
->hw_cap_support
= stmmac_get_hw_features(priv
);
2700 if (priv
->hw_cap_support
) {
2701 pr_info(" DMA HW capability register supported");
2703 /* We can override some gmac/dma configuration fields: e.g.
2704 * enh_desc, tx_coe (e.g. that are passed through the
2705 * platform) with the values from the HW capability
2706 * register (if supported).
2708 priv
->plat
->enh_desc
= priv
->dma_cap
.enh_desc
;
2709 priv
->plat
->pmt
= priv
->dma_cap
.pmt_remote_wake_up
;
2711 priv
->plat
->tx_coe
= priv
->dma_cap
.tx_coe
;
2713 if (priv
->dma_cap
.rx_coe_type2
)
2714 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE2
;
2715 else if (priv
->dma_cap
.rx_coe_type1
)
2716 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE1
;
2719 pr_info(" No HW DMA feature register supported");
2721 /* To use alternate (extended) or normal descriptor structures */
2722 stmmac_selec_desc_mode(priv
);
2724 if (priv
->plat
->rx_coe
) {
2725 priv
->hw
->rx_csum
= priv
->plat
->rx_coe
;
2726 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2727 priv
->plat
->rx_coe
);
2729 if (priv
->plat
->tx_coe
)
2730 pr_info(" TX Checksum insertion supported\n");
2732 if (priv
->plat
->pmt
) {
2733 pr_info(" Wake-Up On Lan supported\n");
2734 device_set_wakeup_capable(priv
->device
, 1);
2742 * @device: device pointer
2743 * @plat_dat: platform data pointer
2744 * @addr: iobase memory address
2745 * Description: this is the main probe function used to
2746 * call the alloc_etherdev, allocate the priv structure.
2748 struct stmmac_priv
*stmmac_dvr_probe(struct device
*device
,
2749 struct plat_stmmacenet_data
*plat_dat
,
2753 struct net_device
*ndev
= NULL
;
2754 struct stmmac_priv
*priv
;
2756 ndev
= alloc_etherdev(sizeof(struct stmmac_priv
));
2760 SET_NETDEV_DEV(ndev
, device
);
2762 priv
= netdev_priv(ndev
);
2763 priv
->device
= device
;
2766 stmmac_set_ethtool_ops(ndev
);
2767 priv
->pause
= pause
;
2768 priv
->plat
= plat_dat
;
2769 priv
->ioaddr
= addr
;
2770 priv
->dev
->base_addr
= (unsigned long)addr
;
2772 /* Verify driver arguments */
2773 stmmac_verify_args();
2775 /* Override with kernel parameters if supplied XXX CRS XXX
2776 * this needs to have multiple instances
2778 if ((phyaddr
>= 0) && (phyaddr
<= 31))
2779 priv
->plat
->phy_addr
= phyaddr
;
2781 priv
->stmmac_clk
= devm_clk_get(priv
->device
, STMMAC_RESOURCE_NAME
);
2782 if (IS_ERR(priv
->stmmac_clk
)) {
2783 dev_warn(priv
->device
, "%s: warning: cannot get CSR clock\n",
2785 /* If failed to obtain stmmac_clk and specific clk_csr value
2786 * is NOT passed from the platform, probe fail.
2788 if (!priv
->plat
->clk_csr
) {
2789 ret
= PTR_ERR(priv
->stmmac_clk
);
2792 priv
->stmmac_clk
= NULL
;
2795 clk_prepare_enable(priv
->stmmac_clk
);
2797 priv
->stmmac_rst
= devm_reset_control_get(priv
->device
,
2798 STMMAC_RESOURCE_NAME
);
2799 if (IS_ERR(priv
->stmmac_rst
)) {
2800 if (PTR_ERR(priv
->stmmac_rst
) == -EPROBE_DEFER
) {
2801 ret
= -EPROBE_DEFER
;
2804 dev_info(priv
->device
, "no reset control found\n");
2805 priv
->stmmac_rst
= NULL
;
2807 if (priv
->stmmac_rst
)
2808 reset_control_deassert(priv
->stmmac_rst
);
2810 /* Init MAC and get the capabilities */
2811 ret
= stmmac_hw_init(priv
);
2815 ndev
->netdev_ops
= &stmmac_netdev_ops
;
2817 ndev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
2819 ndev
->features
|= ndev
->hw_features
| NETIF_F_HIGHDMA
;
2820 ndev
->watchdog_timeo
= msecs_to_jiffies(watchdog
);
2821 #ifdef STMMAC_VLAN_TAG_USED
2822 /* Both mac100 and gmac support receive VLAN tag detection */
2823 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_RX
;
2825 priv
->msg_enable
= netif_msg_init(debug
, default_msg_level
);
2828 priv
->flow_ctrl
= FLOW_AUTO
; /* RX/TX pause on */
2830 /* Rx Watchdog is available in the COREs newer than the 3.40.
2831 * In some case, for example on bugged HW this feature
2832 * has to be disable and this can be done by passing the
2833 * riwt_off field from the platform.
2835 if ((priv
->synopsys_id
>= DWMAC_CORE_3_50
) && (!priv
->plat
->riwt_off
)) {
2837 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2840 netif_napi_add(ndev
, &priv
->napi
, stmmac_poll
, 64);
2842 spin_lock_init(&priv
->lock
);
2843 spin_lock_init(&priv
->tx_lock
);
2845 ret
= register_netdev(ndev
);
2847 pr_err("%s: ERROR %i registering the device\n", __func__
, ret
);
2848 goto error_netdev_register
;
2851 /* If a specific clk_csr value is passed from the platform
2852 * this means that the CSR Clock Range selection cannot be
2853 * changed at run-time and it is fixed. Viceversa the driver'll try to
2854 * set the MDC clock dynamically according to the csr actual
2857 if (!priv
->plat
->clk_csr
)
2858 stmmac_clk_csr_set(priv
);
2860 priv
->clk_csr
= priv
->plat
->clk_csr
;
2862 stmmac_check_pcs_mode(priv
);
2864 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
2865 priv
->pcs
!= STMMAC_PCS_RTBI
) {
2866 /* MDIO bus Registration */
2867 ret
= stmmac_mdio_register(ndev
);
2869 pr_debug("%s: MDIO bus (id: %d) registration failed",
2870 __func__
, priv
->plat
->bus_id
);
2871 goto error_mdio_register
;
2877 error_mdio_register
:
2878 unregister_netdev(ndev
);
2879 error_netdev_register
:
2880 netif_napi_del(&priv
->napi
);
2882 clk_disable_unprepare(priv
->stmmac_clk
);
2886 return ERR_PTR(ret
);
2891 * @ndev: net device pointer
2892 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2893 * changes the link status, releases the DMA descriptor rings.
2895 int stmmac_dvr_remove(struct net_device
*ndev
)
2897 struct stmmac_priv
*priv
= netdev_priv(ndev
);
2899 pr_info("%s:\n\tremoving driver", __func__
);
2901 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
2902 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
2904 stmmac_set_mac(priv
->ioaddr
, false);
2905 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
2906 priv
->pcs
!= STMMAC_PCS_RTBI
)
2907 stmmac_mdio_unregister(ndev
);
2908 netif_carrier_off(ndev
);
2909 unregister_netdev(ndev
);
2910 if (priv
->stmmac_rst
)
2911 reset_control_assert(priv
->stmmac_rst
);
2912 clk_disable_unprepare(priv
->stmmac_clk
);
2919 int stmmac_suspend(struct net_device
*ndev
)
2921 struct stmmac_priv
*priv
= netdev_priv(ndev
);
2922 unsigned long flags
;
2924 if (!ndev
|| !netif_running(ndev
))
2928 phy_stop(priv
->phydev
);
2930 spin_lock_irqsave(&priv
->lock
, flags
);
2932 netif_device_detach(ndev
);
2933 netif_stop_queue(ndev
);
2935 napi_disable(&priv
->napi
);
2937 /* Stop TX/RX DMA */
2938 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
2939 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
2941 stmmac_clear_descriptors(priv
);
2943 /* Enable Power down mode by programming the PMT regs */
2944 if (device_may_wakeup(priv
->device
)) {
2945 priv
->hw
->mac
->pmt(priv
->hw
, priv
->wolopts
);
2948 stmmac_set_mac(priv
->ioaddr
, false);
2949 pinctrl_pm_select_sleep_state(priv
->device
);
2950 /* Disable clock in case of PWM is off */
2951 clk_disable(priv
->stmmac_clk
);
2953 spin_unlock_irqrestore(&priv
->lock
, flags
);
2957 priv
->oldduplex
= -1;
2961 int stmmac_resume(struct net_device
*ndev
)
2963 struct stmmac_priv
*priv
= netdev_priv(ndev
);
2964 unsigned long flags
;
2966 if (!netif_running(ndev
))
2969 spin_lock_irqsave(&priv
->lock
, flags
);
2971 /* Power Down bit, into the PM register, is cleared
2972 * automatically as soon as a magic packet or a Wake-up frame
2973 * is received. Anyway, it's better to manually clear
2974 * this bit because it can generate problems while resuming
2975 * from another devices (e.g. serial console).
2977 if (device_may_wakeup(priv
->device
)) {
2978 priv
->hw
->mac
->pmt(priv
->hw
, 0);
2981 pinctrl_pm_select_default_state(priv
->device
);
2982 /* enable the clk prevously disabled */
2983 clk_enable(priv
->stmmac_clk
);
2984 /* reset the phy so that it's ready */
2986 stmmac_mdio_reset(priv
->mii
);
2989 netif_device_attach(ndev
);
2991 init_dma_desc_rings(ndev
, GFP_ATOMIC
);
2992 stmmac_hw_setup(ndev
);
2993 stmmac_init_tx_coalesce(priv
);
2995 napi_enable(&priv
->napi
);
2997 netif_start_queue(ndev
);
2999 spin_unlock_irqrestore(&priv
->lock
, flags
);
3002 phy_start(priv
->phydev
);
3006 #endif /* CONFIG_PM */
3008 /* Driver can be configured w/ and w/ both PCI and Platf drivers
3009 * depending on the configuration selected.
3011 static int __init
stmmac_init(void)
3015 ret
= stmmac_register_platform();
3018 ret
= stmmac_register_pci();
3023 stmmac_unregister_platform();
3025 pr_err("stmmac: driver registration failed\n");
3029 static void __exit
stmmac_exit(void)
3031 stmmac_unregister_platform();
3032 stmmac_unregister_pci();
3035 module_init(stmmac_init
);
3036 module_exit(stmmac_exit
);
3039 static int __init
stmmac_cmdline_opt(char *str
)
3045 while ((opt
= strsep(&str
, ",")) != NULL
) {
3046 if (!strncmp(opt
, "debug:", 6)) {
3047 if (kstrtoint(opt
+ 6, 0, &debug
))
3049 } else if (!strncmp(opt
, "phyaddr:", 8)) {
3050 if (kstrtoint(opt
+ 8, 0, &phyaddr
))
3052 } else if (!strncmp(opt
, "dma_txsize:", 11)) {
3053 if (kstrtoint(opt
+ 11, 0, &dma_txsize
))
3055 } else if (!strncmp(opt
, "dma_rxsize:", 11)) {
3056 if (kstrtoint(opt
+ 11, 0, &dma_rxsize
))
3058 } else if (!strncmp(opt
, "buf_sz:", 7)) {
3059 if (kstrtoint(opt
+ 7, 0, &buf_sz
))
3061 } else if (!strncmp(opt
, "tc:", 3)) {
3062 if (kstrtoint(opt
+ 3, 0, &tc
))
3064 } else if (!strncmp(opt
, "watchdog:", 9)) {
3065 if (kstrtoint(opt
+ 9, 0, &watchdog
))
3067 } else if (!strncmp(opt
, "flow_ctrl:", 10)) {
3068 if (kstrtoint(opt
+ 10, 0, &flow_ctrl
))
3070 } else if (!strncmp(opt
, "pause:", 6)) {
3071 if (kstrtoint(opt
+ 6, 0, &pause
))
3073 } else if (!strncmp(opt
, "eee_timer:", 10)) {
3074 if (kstrtoint(opt
+ 10, 0, &eee_timer
))
3076 } else if (!strncmp(opt
, "chain_mode:", 11)) {
3077 if (kstrtoint(opt
+ 11, 0, &chain_mode
))
3084 pr_err("%s: ERROR broken module parameter conversion", __func__
);
3088 __setup("stmmaceth=", stmmac_cmdline_opt
);
3091 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3092 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3093 MODULE_LICENSE("GPL");