1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #include <linux/pinctrl/consumer.h>
47 #ifdef CONFIG_DEBUG_FS
48 #include <linux/debugfs.h>
49 #include <linux/seq_file.h>
50 #endif /* CONFIG_DEBUG_FS */
51 #include <linux/net_tstamp.h>
52 #include "stmmac_ptp.h"
54 #include <linux/reset.h>
55 #include <linux/of_mdio.h>
56 #include "dwmac1000.h"
58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
60 /* Module parameters */
62 static int watchdog
= TX_TIMEO
;
63 module_param(watchdog
, int, S_IRUGO
| S_IWUSR
);
64 MODULE_PARM_DESC(watchdog
, "Transmit timeout in milliseconds (default 5s)");
66 static int debug
= -1;
67 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
68 MODULE_PARM_DESC(debug
, "Message Level (-1: default, 0: no output, 16: all)");
70 static int phyaddr
= -1;
71 module_param(phyaddr
, int, S_IRUGO
);
72 MODULE_PARM_DESC(phyaddr
, "Physical device address");
74 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
75 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
77 static int flow_ctrl
= FLOW_OFF
;
78 module_param(flow_ctrl
, int, S_IRUGO
| S_IWUSR
);
79 MODULE_PARM_DESC(flow_ctrl
, "Flow control ability [on/off]");
81 static int pause
= PAUSE_TIME
;
82 module_param(pause
, int, S_IRUGO
| S_IWUSR
);
83 MODULE_PARM_DESC(pause
, "Flow Control Pause Time");
86 static int tc
= TC_DEFAULT
;
87 module_param(tc
, int, S_IRUGO
| S_IWUSR
);
88 MODULE_PARM_DESC(tc
, "DMA threshold control value");
90 #define DEFAULT_BUFSIZE 1536
91 static int buf_sz
= DEFAULT_BUFSIZE
;
92 module_param(buf_sz
, int, S_IRUGO
| S_IWUSR
);
93 MODULE_PARM_DESC(buf_sz
, "DMA buffer size");
95 #define STMMAC_RX_COPYBREAK 256
97 static const u32 default_msg_level
= (NETIF_MSG_DRV
| NETIF_MSG_PROBE
|
98 NETIF_MSG_LINK
| NETIF_MSG_IFUP
|
99 NETIF_MSG_IFDOWN
| NETIF_MSG_TIMER
);
101 #define STMMAC_DEFAULT_LPI_TIMER 1000
102 static int eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
103 module_param(eee_timer
, int, S_IRUGO
| S_IWUSR
);
104 MODULE_PARM_DESC(eee_timer
, "LPI tx expiration time in msec");
105 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
107 /* By default the driver will use the ring mode to manage tx and rx descriptors
108 * but passing this value so user can force to use the chain instead of the ring
110 static unsigned int chain_mode
;
111 module_param(chain_mode
, int, S_IRUGO
);
112 MODULE_PARM_DESC(chain_mode
, "To use chain instead of ring mode");
114 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
);
116 #ifdef CONFIG_DEBUG_FS
117 static int stmmac_init_fs(struct net_device
*dev
);
118 static void stmmac_exit_fs(struct net_device
*dev
);
121 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
124 * stmmac_verify_args - verify the driver parameters.
125 * Description: it checks the driver parameters and set a default in case of
128 static void stmmac_verify_args(void)
130 if (unlikely(watchdog
< 0))
132 if (unlikely((buf_sz
< DEFAULT_BUFSIZE
) || (buf_sz
> BUF_SIZE_16KiB
)))
133 buf_sz
= DEFAULT_BUFSIZE
;
134 if (unlikely(flow_ctrl
> 1))
135 flow_ctrl
= FLOW_AUTO
;
136 else if (likely(flow_ctrl
< 0))
137 flow_ctrl
= FLOW_OFF
;
138 if (unlikely((pause
< 0) || (pause
> 0xffff)))
141 eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
145 * stmmac_clk_csr_set - dynamically set the MDC clock
146 * @priv: driver private structure
147 * Description: this is to dynamically set the MDC clock according to the csr
150 * If a specific clk_csr value is passed from the platform
151 * this means that the CSR Clock Range selection cannot be
152 * changed at run-time and it is fixed (as reported in the driver
153 * documentation). Viceversa the driver will try to set the MDC
154 * clock dynamically according to the actual clock input.
156 static void stmmac_clk_csr_set(struct stmmac_priv
*priv
)
160 clk_rate
= clk_get_rate(priv
->stmmac_clk
);
162 /* Platform provided default clk_csr would be assumed valid
163 * for all other cases except for the below mentioned ones.
164 * For values higher than the IEEE 802.3 specified frequency
165 * we can not estimate the proper divider as it is not known
166 * the frequency of clk_csr_i. So we do not change the default
169 if (!(priv
->clk_csr
& MAC_CSR_H_FRQ_MASK
)) {
170 if (clk_rate
< CSR_F_35M
)
171 priv
->clk_csr
= STMMAC_CSR_20_35M
;
172 else if ((clk_rate
>= CSR_F_35M
) && (clk_rate
< CSR_F_60M
))
173 priv
->clk_csr
= STMMAC_CSR_35_60M
;
174 else if ((clk_rate
>= CSR_F_60M
) && (clk_rate
< CSR_F_100M
))
175 priv
->clk_csr
= STMMAC_CSR_60_100M
;
176 else if ((clk_rate
>= CSR_F_100M
) && (clk_rate
< CSR_F_150M
))
177 priv
->clk_csr
= STMMAC_CSR_100_150M
;
178 else if ((clk_rate
>= CSR_F_150M
) && (clk_rate
< CSR_F_250M
))
179 priv
->clk_csr
= STMMAC_CSR_150_250M
;
180 else if ((clk_rate
>= CSR_F_250M
) && (clk_rate
< CSR_F_300M
))
181 priv
->clk_csr
= STMMAC_CSR_250_300M
;
185 static void print_pkt(unsigned char *buf
, int len
)
187 pr_debug("len = %d byte, buf addr: 0x%p\n", len
, buf
);
188 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
, buf
, len
);
191 static inline u32
stmmac_tx_avail(struct stmmac_priv
*priv
)
195 if (priv
->dirty_tx
> priv
->cur_tx
)
196 avail
= priv
->dirty_tx
- priv
->cur_tx
- 1;
198 avail
= DMA_TX_SIZE
- priv
->cur_tx
+ priv
->dirty_tx
- 1;
203 static inline u32
stmmac_rx_dirty(struct stmmac_priv
*priv
)
207 if (priv
->dirty_rx
<= priv
->cur_rx
)
208 dirty
= priv
->cur_rx
- priv
->dirty_rx
;
210 dirty
= DMA_RX_SIZE
- priv
->dirty_rx
+ priv
->cur_rx
;
216 * stmmac_hw_fix_mac_speed - callback for speed selection
217 * @priv: driver private structure
218 * Description: on some platforms (e.g. ST), some HW system configuraton
219 * registers have to be set according to the link speed negotiated.
221 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv
*priv
)
223 struct phy_device
*phydev
= priv
->phydev
;
225 if (likely(priv
->plat
->fix_mac_speed
))
226 priv
->plat
->fix_mac_speed(priv
->plat
->bsp_priv
, phydev
->speed
);
230 * stmmac_enable_eee_mode - check and enter in LPI mode
231 * @priv: driver private structure
232 * Description: this function is to verify and enter in LPI mode in case of
235 static void stmmac_enable_eee_mode(struct stmmac_priv
*priv
)
237 /* Check and enter in LPI mode */
238 if ((priv
->dirty_tx
== priv
->cur_tx
) &&
239 (priv
->tx_path_in_lpi_mode
== false))
240 priv
->hw
->mac
->set_eee_mode(priv
->hw
);
244 * stmmac_disable_eee_mode - disable and exit from LPI mode
245 * @priv: driver private structure
246 * Description: this function is to exit and disable EEE in case of
247 * LPI state is true. This is called by the xmit.
249 void stmmac_disable_eee_mode(struct stmmac_priv
*priv
)
251 priv
->hw
->mac
->reset_eee_mode(priv
->hw
);
252 del_timer_sync(&priv
->eee_ctrl_timer
);
253 priv
->tx_path_in_lpi_mode
= false;
257 * stmmac_eee_ctrl_timer - EEE TX SW timer.
260 * if there is no data transfer and if we are not in LPI state,
261 * then MAC Transmitter can be moved to LPI state.
263 static void stmmac_eee_ctrl_timer(unsigned long arg
)
265 struct stmmac_priv
*priv
= (struct stmmac_priv
*)arg
;
267 stmmac_enable_eee_mode(priv
);
268 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
272 * stmmac_eee_init - init EEE
273 * @priv: driver private structure
275 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
276 * can also manage EEE, this function enable the LPI state and start related
279 bool stmmac_eee_init(struct stmmac_priv
*priv
)
284 /* Using PCS we cannot dial with the phy registers at this stage
285 * so we do not support extra feature like EEE.
287 if ((priv
->pcs
== STMMAC_PCS_RGMII
) || (priv
->pcs
== STMMAC_PCS_TBI
) ||
288 (priv
->pcs
== STMMAC_PCS_RTBI
))
291 /* MAC core supports the EEE feature. */
292 if (priv
->dma_cap
.eee
) {
293 int tx_lpi_timer
= priv
->tx_lpi_timer
;
295 /* Check if the PHY supports EEE */
296 if (phy_init_eee(priv
->phydev
, 1)) {
297 /* To manage at run-time if the EEE cannot be supported
298 * anymore (for example because the lp caps have been
300 * In that case the driver disable own timers.
302 spin_lock_irqsave(&priv
->lock
, flags
);
303 if (priv
->eee_active
) {
304 pr_debug("stmmac: disable EEE\n");
305 del_timer_sync(&priv
->eee_ctrl_timer
);
306 priv
->hw
->mac
->set_eee_timer(priv
->hw
, 0,
309 priv
->eee_active
= 0;
310 spin_unlock_irqrestore(&priv
->lock
, flags
);
313 /* Activate the EEE and start timers */
314 spin_lock_irqsave(&priv
->lock
, flags
);
315 if (!priv
->eee_active
) {
316 priv
->eee_active
= 1;
317 setup_timer(&priv
->eee_ctrl_timer
,
318 stmmac_eee_ctrl_timer
,
319 (unsigned long)priv
);
320 mod_timer(&priv
->eee_ctrl_timer
,
321 STMMAC_LPI_T(eee_timer
));
323 priv
->hw
->mac
->set_eee_timer(priv
->hw
,
324 STMMAC_DEFAULT_LIT_LS
,
327 /* Set HW EEE according to the speed */
328 priv
->hw
->mac
->set_eee_pls(priv
->hw
, priv
->phydev
->link
);
331 spin_unlock_irqrestore(&priv
->lock
, flags
);
333 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
339 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
340 * @priv: driver private structure
341 * @entry : descriptor index to be used.
342 * @skb : the socket buffer
344 * This function will read timestamp from the descriptor & pass it to stack.
345 * and also perform some sanity checks.
347 static void stmmac_get_tx_hwtstamp(struct stmmac_priv
*priv
,
348 unsigned int entry
, struct sk_buff
*skb
)
350 struct skb_shared_hwtstamps shhwtstamp
;
354 if (!priv
->hwts_tx_en
)
357 /* exit if skb doesn't support hw tstamp */
358 if (likely(!skb
|| !(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)))
362 desc
= (priv
->dma_etx
+ entry
);
364 desc
= (priv
->dma_tx
+ entry
);
366 /* check tx tstamp status */
367 if (!priv
->hw
->desc
->get_tx_timestamp_status((struct dma_desc
*)desc
))
370 /* get the valid tstamp */
371 ns
= priv
->hw
->desc
->get_timestamp(desc
, priv
->adv_ts
);
373 memset(&shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
374 shhwtstamp
.hwtstamp
= ns_to_ktime(ns
);
375 /* pass tstamp to stack */
376 skb_tstamp_tx(skb
, &shhwtstamp
);
381 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
382 * @priv: driver private structure
383 * @entry : descriptor index to be used.
384 * @skb : the socket buffer
386 * This function will read received packet's timestamp from the descriptor
387 * and pass it to stack. It also perform some sanity checks.
389 static void stmmac_get_rx_hwtstamp(struct stmmac_priv
*priv
,
390 unsigned int entry
, struct sk_buff
*skb
)
392 struct skb_shared_hwtstamps
*shhwtstamp
= NULL
;
396 if (!priv
->hwts_rx_en
)
400 desc
= (priv
->dma_erx
+ entry
);
402 desc
= (priv
->dma_rx
+ entry
);
404 /* exit if rx tstamp is not valid */
405 if (!priv
->hw
->desc
->get_rx_timestamp_status(desc
, priv
->adv_ts
))
408 /* get valid tstamp */
409 ns
= priv
->hw
->desc
->get_timestamp(desc
, priv
->adv_ts
);
410 shhwtstamp
= skb_hwtstamps(skb
);
411 memset(shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
412 shhwtstamp
->hwtstamp
= ns_to_ktime(ns
);
416 * stmmac_hwtstamp_ioctl - control hardware timestamping.
417 * @dev: device pointer.
418 * @ifr: An IOCTL specefic structure, that can contain a pointer to
419 * a proprietary structure used to pass information to the driver.
421 * This function configures the MAC to enable/disable both outgoing(TX)
422 * and incoming(RX) packets time stamping based on user input.
424 * 0 on success and an appropriate -ve integer on failure.
426 static int stmmac_hwtstamp_ioctl(struct net_device
*dev
, struct ifreq
*ifr
)
428 struct stmmac_priv
*priv
= netdev_priv(dev
);
429 struct hwtstamp_config config
;
430 struct timespec64 now
;
434 u32 ptp_over_ipv4_udp
= 0;
435 u32 ptp_over_ipv6_udp
= 0;
436 u32 ptp_over_ethernet
= 0;
437 u32 snap_type_sel
= 0;
438 u32 ts_master_en
= 0;
443 if (!(priv
->dma_cap
.time_stamp
|| priv
->adv_ts
)) {
444 netdev_alert(priv
->dev
, "No support for HW time stamping\n");
445 priv
->hwts_tx_en
= 0;
446 priv
->hwts_rx_en
= 0;
451 if (copy_from_user(&config
, ifr
->ifr_data
,
452 sizeof(struct hwtstamp_config
)))
455 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
456 __func__
, config
.flags
, config
.tx_type
, config
.rx_filter
);
458 /* reserved for future extensions */
462 if (config
.tx_type
!= HWTSTAMP_TX_OFF
&&
463 config
.tx_type
!= HWTSTAMP_TX_ON
)
467 switch (config
.rx_filter
) {
468 case HWTSTAMP_FILTER_NONE
:
469 /* time stamp no incoming packet at all */
470 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
473 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
474 /* PTP v1, UDP, any kind of event packet */
475 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
476 /* take time stamp for all event messages */
477 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
479 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
480 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
483 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
484 /* PTP v1, UDP, Sync packet */
485 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_SYNC
;
486 /* take time stamp for SYNC messages only */
487 ts_event_en
= PTP_TCR_TSEVNTENA
;
489 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
490 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
493 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
494 /* PTP v1, UDP, Delay_req packet */
495 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
;
496 /* take time stamp for Delay_Req messages only */
497 ts_master_en
= PTP_TCR_TSMSTRENA
;
498 ts_event_en
= PTP_TCR_TSEVNTENA
;
500 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
501 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
504 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
505 /* PTP v2, UDP, any kind of event packet */
506 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_EVENT
;
507 ptp_v2
= PTP_TCR_TSVER2ENA
;
508 /* take time stamp for all event messages */
509 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
511 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
512 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
515 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
516 /* PTP v2, UDP, Sync packet */
517 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_SYNC
;
518 ptp_v2
= PTP_TCR_TSVER2ENA
;
519 /* take time stamp for SYNC messages only */
520 ts_event_en
= PTP_TCR_TSEVNTENA
;
522 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
523 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
526 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
527 /* PTP v2, UDP, Delay_req packet */
528 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
;
529 ptp_v2
= PTP_TCR_TSVER2ENA
;
530 /* take time stamp for Delay_Req messages only */
531 ts_master_en
= PTP_TCR_TSMSTRENA
;
532 ts_event_en
= PTP_TCR_TSEVNTENA
;
534 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
535 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
538 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
539 /* PTP v2/802.AS1 any layer, any kind of event packet */
540 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
541 ptp_v2
= PTP_TCR_TSVER2ENA
;
542 /* take time stamp for all event messages */
543 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
545 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
546 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
547 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
550 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
551 /* PTP v2/802.AS1, any layer, Sync packet */
552 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_SYNC
;
553 ptp_v2
= PTP_TCR_TSVER2ENA
;
554 /* take time stamp for SYNC messages only */
555 ts_event_en
= PTP_TCR_TSEVNTENA
;
557 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
558 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
559 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
562 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
563 /* PTP v2/802.AS1, any layer, Delay_req packet */
564 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
;
565 ptp_v2
= PTP_TCR_TSVER2ENA
;
566 /* take time stamp for Delay_Req messages only */
567 ts_master_en
= PTP_TCR_TSMSTRENA
;
568 ts_event_en
= PTP_TCR_TSEVNTENA
;
570 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
571 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
572 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
575 case HWTSTAMP_FILTER_ALL
:
576 /* time stamp any incoming packet */
577 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
578 tstamp_all
= PTP_TCR_TSENALL
;
585 switch (config
.rx_filter
) {
586 case HWTSTAMP_FILTER_NONE
:
587 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
590 /* PTP v1, UDP, any kind of event packet */
591 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
595 priv
->hwts_rx_en
= ((config
.rx_filter
== HWTSTAMP_FILTER_NONE
) ? 0 : 1);
596 priv
->hwts_tx_en
= config
.tx_type
== HWTSTAMP_TX_ON
;
598 if (!priv
->hwts_tx_en
&& !priv
->hwts_rx_en
)
599 priv
->hw
->ptp
->config_hw_tstamping(priv
->ioaddr
, 0);
601 value
= (PTP_TCR_TSENA
| PTP_TCR_TSCFUPDT
| PTP_TCR_TSCTRLSSR
|
602 tstamp_all
| ptp_v2
| ptp_over_ethernet
|
603 ptp_over_ipv6_udp
| ptp_over_ipv4_udp
| ts_event_en
|
604 ts_master_en
| snap_type_sel
);
605 priv
->hw
->ptp
->config_hw_tstamping(priv
->ioaddr
, value
);
607 /* program Sub Second Increment reg */
608 sec_inc
= priv
->hw
->ptp
->config_sub_second_increment(
609 priv
->ioaddr
, priv
->clk_ptp_rate
);
610 temp
= div_u64(1000000000ULL, sec_inc
);
612 /* calculate default added value:
614 * addend = (2^32)/freq_div_ratio;
615 * where, freq_div_ratio = 1e9ns/sec_inc
617 temp
= (u64
)(temp
<< 32);
618 priv
->default_addend
= div_u64(temp
, priv
->clk_ptp_rate
);
619 priv
->hw
->ptp
->config_addend(priv
->ioaddr
,
620 priv
->default_addend
);
622 /* initialize system time */
623 ktime_get_real_ts64(&now
);
625 /* lower 32 bits of tv_sec are safe until y2106 */
626 priv
->hw
->ptp
->init_systime(priv
->ioaddr
, (u32
)now
.tv_sec
,
630 return copy_to_user(ifr
->ifr_data
, &config
,
631 sizeof(struct hwtstamp_config
)) ? -EFAULT
: 0;
635 * stmmac_init_ptp - init PTP
636 * @priv: driver private structure
637 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
638 * This is done by looking at the HW cap. register.
639 * This function also registers the ptp driver.
641 static int stmmac_init_ptp(struct stmmac_priv
*priv
)
643 if (!(priv
->dma_cap
.time_stamp
|| priv
->dma_cap
.atime_stamp
))
646 /* Fall-back to main clock in case of no PTP ref is passed */
647 priv
->clk_ptp_ref
= devm_clk_get(priv
->device
, "clk_ptp_ref");
648 if (IS_ERR(priv
->clk_ptp_ref
)) {
649 priv
->clk_ptp_rate
= clk_get_rate(priv
->stmmac_clk
);
650 priv
->clk_ptp_ref
= NULL
;
652 clk_prepare_enable(priv
->clk_ptp_ref
);
653 priv
->clk_ptp_rate
= clk_get_rate(priv
->clk_ptp_ref
);
657 if (priv
->dma_cap
.atime_stamp
&& priv
->extend_desc
)
660 if (netif_msg_hw(priv
) && priv
->dma_cap
.time_stamp
)
661 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
663 if (netif_msg_hw(priv
) && priv
->adv_ts
)
664 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
666 priv
->hw
->ptp
= &stmmac_ptp
;
667 priv
->hwts_tx_en
= 0;
668 priv
->hwts_rx_en
= 0;
670 return stmmac_ptp_register(priv
);
673 static void stmmac_release_ptp(struct stmmac_priv
*priv
)
675 if (priv
->clk_ptp_ref
)
676 clk_disable_unprepare(priv
->clk_ptp_ref
);
677 stmmac_ptp_unregister(priv
);
681 * stmmac_adjust_link - adjusts the link parameters
682 * @dev: net device structure
683 * Description: this is the helper called by the physical abstraction layer
684 * drivers to communicate the phy link status. According the speed and duplex
685 * this driver can invoke registered glue-logic as well.
686 * It also invoke the eee initialization because it could happen when switch
687 * on different networks (that are eee capable).
689 static void stmmac_adjust_link(struct net_device
*dev
)
691 struct stmmac_priv
*priv
= netdev_priv(dev
);
692 struct phy_device
*phydev
= priv
->phydev
;
695 unsigned int fc
= priv
->flow_ctrl
, pause_time
= priv
->pause
;
700 spin_lock_irqsave(&priv
->lock
, flags
);
703 u32 ctrl
= readl(priv
->ioaddr
+ MAC_CTRL_REG
);
705 /* Now we make sure that we can be in full duplex mode.
706 * If not, we operate in half-duplex mode. */
707 if (phydev
->duplex
!= priv
->oldduplex
) {
709 if (!(phydev
->duplex
))
710 ctrl
&= ~priv
->hw
->link
.duplex
;
712 ctrl
|= priv
->hw
->link
.duplex
;
713 priv
->oldduplex
= phydev
->duplex
;
715 /* Flow Control operation */
717 priv
->hw
->mac
->flow_ctrl(priv
->hw
, phydev
->duplex
,
720 if (phydev
->speed
!= priv
->speed
) {
722 switch (phydev
->speed
) {
724 if (likely(priv
->plat
->has_gmac
))
725 ctrl
&= ~priv
->hw
->link
.port
;
726 stmmac_hw_fix_mac_speed(priv
);
730 if (priv
->plat
->has_gmac
) {
731 ctrl
|= priv
->hw
->link
.port
;
732 if (phydev
->speed
== SPEED_100
) {
733 ctrl
|= priv
->hw
->link
.speed
;
735 ctrl
&= ~(priv
->hw
->link
.speed
);
738 ctrl
&= ~priv
->hw
->link
.port
;
740 stmmac_hw_fix_mac_speed(priv
);
743 if (netif_msg_link(priv
))
744 pr_warn("%s: Speed (%d) not 10/100\n",
745 dev
->name
, phydev
->speed
);
749 priv
->speed
= phydev
->speed
;
752 writel(ctrl
, priv
->ioaddr
+ MAC_CTRL_REG
);
754 if (!priv
->oldlink
) {
758 } else if (priv
->oldlink
) {
762 priv
->oldduplex
= -1;
765 if (new_state
&& netif_msg_link(priv
))
766 phy_print_status(phydev
);
768 spin_unlock_irqrestore(&priv
->lock
, flags
);
770 if (phydev
->is_pseudo_fixed_link
)
771 /* Stop PHY layer to call the hook to adjust the link in case
772 * of a switch is attached to the stmmac driver.
774 phydev
->irq
= PHY_IGNORE_INTERRUPT
;
776 /* At this stage, init the EEE if supported.
777 * Never called in case of fixed_link.
779 priv
->eee_enabled
= stmmac_eee_init(priv
);
783 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
784 * @priv: driver private structure
785 * Description: this is to verify if the HW supports the PCS.
786 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
787 * configured for the TBI, RTBI, or SGMII PHY interface.
789 static void stmmac_check_pcs_mode(struct stmmac_priv
*priv
)
791 int interface
= priv
->plat
->interface
;
793 if (priv
->dma_cap
.pcs
) {
794 if ((interface
== PHY_INTERFACE_MODE_RGMII
) ||
795 (interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
796 (interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
797 (interface
== PHY_INTERFACE_MODE_RGMII_TXID
)) {
798 pr_debug("STMMAC: PCS RGMII support enable\n");
799 priv
->pcs
= STMMAC_PCS_RGMII
;
800 } else if (interface
== PHY_INTERFACE_MODE_SGMII
) {
801 pr_debug("STMMAC: PCS SGMII support enable\n");
802 priv
->pcs
= STMMAC_PCS_SGMII
;
808 * stmmac_init_phy - PHY initialization
809 * @dev: net device structure
810 * Description: it initializes the driver's PHY state, and attaches the PHY
815 static int stmmac_init_phy(struct net_device
*dev
)
817 struct stmmac_priv
*priv
= netdev_priv(dev
);
818 struct phy_device
*phydev
;
819 char phy_id_fmt
[MII_BUS_ID_SIZE
+ 3];
820 char bus_id
[MII_BUS_ID_SIZE
];
821 int interface
= priv
->plat
->interface
;
822 int max_speed
= priv
->plat
->max_speed
;
825 priv
->oldduplex
= -1;
827 if (priv
->plat
->phy_node
) {
828 phydev
= of_phy_connect(dev
, priv
->plat
->phy_node
,
829 &stmmac_adjust_link
, 0, interface
);
831 snprintf(bus_id
, MII_BUS_ID_SIZE
, "stmmac-%x",
834 snprintf(phy_id_fmt
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
, bus_id
,
835 priv
->plat
->phy_addr
);
836 pr_debug("stmmac_init_phy: trying to attach to %s\n",
839 phydev
= phy_connect(dev
, phy_id_fmt
, &stmmac_adjust_link
,
843 if (IS_ERR_OR_NULL(phydev
)) {
844 pr_err("%s: Could not attach to PHY\n", dev
->name
);
848 return PTR_ERR(phydev
);
851 /* Stop Advertising 1000BASE Capability if interface is not GMII */
852 if ((interface
== PHY_INTERFACE_MODE_MII
) ||
853 (interface
== PHY_INTERFACE_MODE_RMII
) ||
854 (max_speed
< 1000 && max_speed
> 0))
855 phydev
->advertising
&= ~(SUPPORTED_1000baseT_Half
|
856 SUPPORTED_1000baseT_Full
);
859 * Broken HW is sometimes missing the pull-up resistor on the
860 * MDIO line, which results in reads to non-existent devices returning
861 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
863 * Note: phydev->phy_id is the result of reading the UID PHY registers.
865 if (!priv
->plat
->phy_node
&& phydev
->phy_id
== 0) {
866 phy_disconnect(phydev
);
870 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
871 " Link = %d\n", dev
->name
, phydev
->phy_id
, phydev
->link
);
873 priv
->phydev
= phydev
;
879 * stmmac_display_ring - display ring
880 * @head: pointer to the head of the ring passed.
881 * @size: size of the ring.
882 * @extend_desc: to verify if extended descriptors are used.
883 * Description: display the control/status and buffer descriptors.
885 static void stmmac_display_ring(void *head
, int size
, int extend_desc
)
888 struct dma_extended_desc
*ep
= (struct dma_extended_desc
*)head
;
889 struct dma_desc
*p
= (struct dma_desc
*)head
;
891 for (i
= 0; i
< size
; i
++) {
895 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
896 i
, (unsigned int)virt_to_phys(ep
),
897 (unsigned int)x
, (unsigned int)(x
>> 32),
898 ep
->basic
.des2
, ep
->basic
.des3
);
902 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
903 i
, (unsigned int)virt_to_phys(p
),
904 (unsigned int)x
, (unsigned int)(x
>> 32),
912 static void stmmac_display_rings(struct stmmac_priv
*priv
)
914 if (priv
->extend_desc
) {
915 pr_info("Extended RX descriptor ring:\n");
916 stmmac_display_ring((void *)priv
->dma_erx
, DMA_RX_SIZE
, 1);
917 pr_info("Extended TX descriptor ring:\n");
918 stmmac_display_ring((void *)priv
->dma_etx
, DMA_TX_SIZE
, 1);
920 pr_info("RX descriptor ring:\n");
921 stmmac_display_ring((void *)priv
->dma_rx
, DMA_RX_SIZE
, 0);
922 pr_info("TX descriptor ring:\n");
923 stmmac_display_ring((void *)priv
->dma_tx
, DMA_TX_SIZE
, 0);
927 static int stmmac_set_bfsize(int mtu
, int bufsize
)
931 if (mtu
>= BUF_SIZE_4KiB
)
933 else if (mtu
>= BUF_SIZE_2KiB
)
935 else if (mtu
> DEFAULT_BUFSIZE
)
938 ret
= DEFAULT_BUFSIZE
;
944 * stmmac_clear_descriptors - clear descriptors
945 * @priv: driver private structure
946 * Description: this function is called to clear the tx and rx descriptors
947 * in case of both basic and extended descriptors are used.
949 static void stmmac_clear_descriptors(struct stmmac_priv
*priv
)
953 /* Clear the Rx/Tx descriptors */
954 for (i
= 0; i
< DMA_RX_SIZE
; i
++)
955 if (priv
->extend_desc
)
956 priv
->hw
->desc
->init_rx_desc(&priv
->dma_erx
[i
].basic
,
957 priv
->use_riwt
, priv
->mode
,
958 (i
== DMA_RX_SIZE
- 1));
960 priv
->hw
->desc
->init_rx_desc(&priv
->dma_rx
[i
],
961 priv
->use_riwt
, priv
->mode
,
962 (i
== DMA_RX_SIZE
- 1));
963 for (i
= 0; i
< DMA_TX_SIZE
; i
++)
964 if (priv
->extend_desc
)
965 priv
->hw
->desc
->init_tx_desc(&priv
->dma_etx
[i
].basic
,
967 (i
== DMA_TX_SIZE
- 1));
969 priv
->hw
->desc
->init_tx_desc(&priv
->dma_tx
[i
],
971 (i
== DMA_TX_SIZE
- 1));
975 * stmmac_init_rx_buffers - init the RX descriptor buffer.
976 * @priv: driver private structure
977 * @p: descriptor pointer
978 * @i: descriptor index
980 * Description: this function is called to allocate a receive buffer, perform
981 * the DMA mapping and init the descriptor.
983 static int stmmac_init_rx_buffers(struct stmmac_priv
*priv
, struct dma_desc
*p
,
988 skb
= __netdev_alloc_skb_ip_align(priv
->dev
, priv
->dma_buf_sz
, flags
);
990 pr_err("%s: Rx init fails; skb is NULL\n", __func__
);
993 priv
->rx_skbuff
[i
] = skb
;
994 priv
->rx_skbuff_dma
[i
] = dma_map_single(priv
->device
, skb
->data
,
997 if (dma_mapping_error(priv
->device
, priv
->rx_skbuff_dma
[i
])) {
998 pr_err("%s: DMA mapping error\n", __func__
);
999 dev_kfree_skb_any(skb
);
1003 p
->des2
= priv
->rx_skbuff_dma
[i
];
1005 if ((priv
->hw
->mode
->init_desc3
) &&
1006 (priv
->dma_buf_sz
== BUF_SIZE_16KiB
))
1007 priv
->hw
->mode
->init_desc3(p
);
1012 static void stmmac_free_rx_buffers(struct stmmac_priv
*priv
, int i
)
1014 if (priv
->rx_skbuff
[i
]) {
1015 dma_unmap_single(priv
->device
, priv
->rx_skbuff_dma
[i
],
1016 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
1017 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
1019 priv
->rx_skbuff
[i
] = NULL
;
1023 * init_dma_desc_rings - init the RX/TX descriptor rings
1024 * @dev: net device structure
1026 * Description: this function initializes the DMA RX/TX descriptors
1027 * and allocates the socket buffers. It suppors the chained and ring
1030 static int init_dma_desc_rings(struct net_device
*dev
, gfp_t flags
)
1033 struct stmmac_priv
*priv
= netdev_priv(dev
);
1034 unsigned int bfsize
= 0;
1037 if (priv
->hw
->mode
->set_16kib_bfsize
)
1038 bfsize
= priv
->hw
->mode
->set_16kib_bfsize(dev
->mtu
);
1040 if (bfsize
< BUF_SIZE_16KiB
)
1041 bfsize
= stmmac_set_bfsize(dev
->mtu
, priv
->dma_buf_sz
);
1043 priv
->dma_buf_sz
= bfsize
;
1045 if (netif_msg_probe(priv
)) {
1046 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__
,
1047 (u32
) priv
->dma_rx_phy
, (u32
) priv
->dma_tx_phy
);
1049 /* RX INITIALIZATION */
1050 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1052 for (i
= 0; i
< DMA_RX_SIZE
; i
++) {
1054 if (priv
->extend_desc
)
1055 p
= &((priv
->dma_erx
+ i
)->basic
);
1057 p
= priv
->dma_rx
+ i
;
1059 ret
= stmmac_init_rx_buffers(priv
, p
, i
, flags
);
1061 goto err_init_rx_buffers
;
1063 if (netif_msg_probe(priv
))
1064 pr_debug("[%p]\t[%p]\t[%x]\n", priv
->rx_skbuff
[i
],
1065 priv
->rx_skbuff
[i
]->data
,
1066 (unsigned int)priv
->rx_skbuff_dma
[i
]);
1069 priv
->dirty_rx
= (unsigned int)(i
- DMA_RX_SIZE
);
1072 /* Setup the chained descriptor addresses */
1073 if (priv
->mode
== STMMAC_CHAIN_MODE
) {
1074 if (priv
->extend_desc
) {
1075 priv
->hw
->mode
->init(priv
->dma_erx
, priv
->dma_rx_phy
,
1077 priv
->hw
->mode
->init(priv
->dma_etx
, priv
->dma_tx_phy
,
1080 priv
->hw
->mode
->init(priv
->dma_rx
, priv
->dma_rx_phy
,
1082 priv
->hw
->mode
->init(priv
->dma_tx
, priv
->dma_tx_phy
,
1087 /* TX INITIALIZATION */
1088 for (i
= 0; i
< DMA_TX_SIZE
; i
++) {
1090 if (priv
->extend_desc
)
1091 p
= &((priv
->dma_etx
+ i
)->basic
);
1093 p
= priv
->dma_tx
+ i
;
1095 priv
->tx_skbuff_dma
[i
].buf
= 0;
1096 priv
->tx_skbuff_dma
[i
].map_as_page
= false;
1097 priv
->tx_skbuff_dma
[i
].len
= 0;
1098 priv
->tx_skbuff_dma
[i
].last_segment
= false;
1099 priv
->tx_skbuff
[i
] = NULL
;
1104 netdev_reset_queue(priv
->dev
);
1106 stmmac_clear_descriptors(priv
);
1108 if (netif_msg_hw(priv
))
1109 stmmac_display_rings(priv
);
1112 err_init_rx_buffers
:
1114 stmmac_free_rx_buffers(priv
, i
);
1118 static void dma_free_rx_skbufs(struct stmmac_priv
*priv
)
1122 for (i
= 0; i
< DMA_RX_SIZE
; i
++)
1123 stmmac_free_rx_buffers(priv
, i
);
1126 static void dma_free_tx_skbufs(struct stmmac_priv
*priv
)
1130 for (i
= 0; i
< DMA_TX_SIZE
; i
++) {
1133 if (priv
->extend_desc
)
1134 p
= &((priv
->dma_etx
+ i
)->basic
);
1136 p
= priv
->dma_tx
+ i
;
1138 if (priv
->tx_skbuff_dma
[i
].buf
) {
1139 if (priv
->tx_skbuff_dma
[i
].map_as_page
)
1140 dma_unmap_page(priv
->device
,
1141 priv
->tx_skbuff_dma
[i
].buf
,
1142 priv
->tx_skbuff_dma
[i
].len
,
1145 dma_unmap_single(priv
->device
,
1146 priv
->tx_skbuff_dma
[i
].buf
,
1147 priv
->tx_skbuff_dma
[i
].len
,
1151 if (priv
->tx_skbuff
[i
] != NULL
) {
1152 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
1153 priv
->tx_skbuff
[i
] = NULL
;
1154 priv
->tx_skbuff_dma
[i
].buf
= 0;
1155 priv
->tx_skbuff_dma
[i
].map_as_page
= false;
1161 * alloc_dma_desc_resources - alloc TX/RX resources.
1162 * @priv: private structure
1163 * Description: according to which descriptor can be used (extend or basic)
1164 * this function allocates the resources for TX and RX paths. In case of
1165 * reception, for example, it pre-allocated the RX socket buffer in order to
1166 * allow zero-copy mechanism.
1168 static int alloc_dma_desc_resources(struct stmmac_priv
*priv
)
1172 priv
->rx_skbuff_dma
= kmalloc_array(DMA_RX_SIZE
, sizeof(dma_addr_t
),
1174 if (!priv
->rx_skbuff_dma
)
1177 priv
->rx_skbuff
= kmalloc_array(DMA_RX_SIZE
, sizeof(struct sk_buff
*),
1179 if (!priv
->rx_skbuff
)
1182 priv
->tx_skbuff_dma
= kmalloc_array(DMA_TX_SIZE
,
1183 sizeof(*priv
->tx_skbuff_dma
),
1185 if (!priv
->tx_skbuff_dma
)
1186 goto err_tx_skbuff_dma
;
1188 priv
->tx_skbuff
= kmalloc_array(DMA_TX_SIZE
, sizeof(struct sk_buff
*),
1190 if (!priv
->tx_skbuff
)
1193 if (priv
->extend_desc
) {
1194 priv
->dma_erx
= dma_zalloc_coherent(priv
->device
, DMA_RX_SIZE
*
1202 priv
->dma_etx
= dma_zalloc_coherent(priv
->device
, DMA_TX_SIZE
*
1207 if (!priv
->dma_etx
) {
1208 dma_free_coherent(priv
->device
, DMA_RX_SIZE
*
1209 sizeof(struct dma_extended_desc
),
1210 priv
->dma_erx
, priv
->dma_rx_phy
);
1214 priv
->dma_rx
= dma_zalloc_coherent(priv
->device
, DMA_RX_SIZE
*
1215 sizeof(struct dma_desc
),
1221 priv
->dma_tx
= dma_zalloc_coherent(priv
->device
, DMA_TX_SIZE
*
1222 sizeof(struct dma_desc
),
1225 if (!priv
->dma_tx
) {
1226 dma_free_coherent(priv
->device
, DMA_RX_SIZE
*
1227 sizeof(struct dma_desc
),
1228 priv
->dma_rx
, priv
->dma_rx_phy
);
1236 kfree(priv
->tx_skbuff
);
1238 kfree(priv
->tx_skbuff_dma
);
1240 kfree(priv
->rx_skbuff
);
1242 kfree(priv
->rx_skbuff_dma
);
1246 static void free_dma_desc_resources(struct stmmac_priv
*priv
)
1248 /* Release the DMA TX/RX socket buffers */
1249 dma_free_rx_skbufs(priv
);
1250 dma_free_tx_skbufs(priv
);
1252 /* Free DMA regions of consistent memory previously allocated */
1253 if (!priv
->extend_desc
) {
1254 dma_free_coherent(priv
->device
,
1255 DMA_TX_SIZE
* sizeof(struct dma_desc
),
1256 priv
->dma_tx
, priv
->dma_tx_phy
);
1257 dma_free_coherent(priv
->device
,
1258 DMA_RX_SIZE
* sizeof(struct dma_desc
),
1259 priv
->dma_rx
, priv
->dma_rx_phy
);
1261 dma_free_coherent(priv
->device
, DMA_TX_SIZE
*
1262 sizeof(struct dma_extended_desc
),
1263 priv
->dma_etx
, priv
->dma_tx_phy
);
1264 dma_free_coherent(priv
->device
, DMA_RX_SIZE
*
1265 sizeof(struct dma_extended_desc
),
1266 priv
->dma_erx
, priv
->dma_rx_phy
);
1268 kfree(priv
->rx_skbuff_dma
);
1269 kfree(priv
->rx_skbuff
);
1270 kfree(priv
->tx_skbuff_dma
);
1271 kfree(priv
->tx_skbuff
);
1275 * stmmac_dma_operation_mode - HW DMA operation mode
1276 * @priv: driver private structure
1277 * Description: it is used for configuring the DMA operation mode register in
1278 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1280 static void stmmac_dma_operation_mode(struct stmmac_priv
*priv
)
1282 int rxfifosz
= priv
->plat
->rx_fifo_size
;
1284 if (priv
->plat
->force_thresh_dma_mode
)
1285 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, tc
, rxfifosz
);
1286 else if (priv
->plat
->force_sf_dma_mode
|| priv
->plat
->tx_coe
) {
1288 * In case of GMAC, SF mode can be enabled
1289 * to perform the TX COE in HW. This depends on:
1290 * 1) TX COE if actually supported
1291 * 2) There is no bugged Jumbo frame support
1292 * that needs to not insert csum in the TDES.
1294 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, SF_DMA_MODE
, SF_DMA_MODE
,
1296 priv
->xstats
.threshold
= SF_DMA_MODE
;
1298 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, SF_DMA_MODE
,
1303 * stmmac_tx_clean - to manage the transmission completion
1304 * @priv: driver private structure
1305 * Description: it reclaims the transmit resources after transmission completes.
1307 static void stmmac_tx_clean(struct stmmac_priv
*priv
)
1309 unsigned int bytes_compl
= 0, pkts_compl
= 0;
1310 unsigned int entry
= priv
->dirty_tx
;
1312 spin_lock(&priv
->tx_lock
);
1314 priv
->xstats
.tx_clean
++;
1316 while (entry
!= priv
->cur_tx
) {
1317 struct sk_buff
*skb
= priv
->tx_skbuff
[entry
];
1321 if (priv
->extend_desc
)
1322 p
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
1324 p
= priv
->dma_tx
+ entry
;
1326 status
= priv
->hw
->desc
->tx_status(&priv
->dev
->stats
,
1329 /* Check if the descriptor is owned by the DMA */
1330 if (unlikely(status
& tx_dma_own
))
1333 /* Just consider the last segment and ...*/
1334 if (likely(!(status
& tx_not_ls
))) {
1335 /* ... verify the status error condition */
1336 if (unlikely(status
& tx_err
)) {
1337 priv
->dev
->stats
.tx_errors
++;
1339 priv
->dev
->stats
.tx_packets
++;
1340 priv
->xstats
.tx_pkt_n
++;
1342 stmmac_get_tx_hwtstamp(priv
, entry
, skb
);
1345 if (likely(priv
->tx_skbuff_dma
[entry
].buf
)) {
1346 if (priv
->tx_skbuff_dma
[entry
].map_as_page
)
1347 dma_unmap_page(priv
->device
,
1348 priv
->tx_skbuff_dma
[entry
].buf
,
1349 priv
->tx_skbuff_dma
[entry
].len
,
1352 dma_unmap_single(priv
->device
,
1353 priv
->tx_skbuff_dma
[entry
].buf
,
1354 priv
->tx_skbuff_dma
[entry
].len
,
1356 priv
->tx_skbuff_dma
[entry
].buf
= 0;
1357 priv
->tx_skbuff_dma
[entry
].map_as_page
= false;
1359 priv
->hw
->mode
->clean_desc3(priv
, p
);
1360 priv
->tx_skbuff_dma
[entry
].last_segment
= false;
1361 priv
->tx_skbuff_dma
[entry
].is_jumbo
= false;
1363 if (likely(skb
!= NULL
)) {
1365 bytes_compl
+= skb
->len
;
1366 dev_consume_skb_any(skb
);
1367 priv
->tx_skbuff
[entry
] = NULL
;
1370 priv
->hw
->desc
->release_tx_desc(p
, priv
->mode
);
1372 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
1374 priv
->dirty_tx
= entry
;
1376 netdev_completed_queue(priv
->dev
, pkts_compl
, bytes_compl
);
1378 if (unlikely(netif_queue_stopped(priv
->dev
) &&
1379 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH
)) {
1380 netif_tx_lock(priv
->dev
);
1381 if (netif_queue_stopped(priv
->dev
) &&
1382 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH
) {
1383 if (netif_msg_tx_done(priv
))
1384 pr_debug("%s: restart transmit\n", __func__
);
1385 netif_wake_queue(priv
->dev
);
1387 netif_tx_unlock(priv
->dev
);
1390 if ((priv
->eee_enabled
) && (!priv
->tx_path_in_lpi_mode
)) {
1391 stmmac_enable_eee_mode(priv
);
1392 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
1394 spin_unlock(&priv
->tx_lock
);
1397 static inline void stmmac_enable_dma_irq(struct stmmac_priv
*priv
)
1399 priv
->hw
->dma
->enable_dma_irq(priv
->ioaddr
);
1402 static inline void stmmac_disable_dma_irq(struct stmmac_priv
*priv
)
1404 priv
->hw
->dma
->disable_dma_irq(priv
->ioaddr
);
1408 * stmmac_tx_err - to manage the tx error
1409 * @priv: driver private structure
1410 * Description: it cleans the descriptors and restarts the transmission
1411 * in case of transmission errors.
1413 static void stmmac_tx_err(struct stmmac_priv
*priv
)
1416 netif_stop_queue(priv
->dev
);
1418 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1419 dma_free_tx_skbufs(priv
);
1420 for (i
= 0; i
< DMA_TX_SIZE
; i
++)
1421 if (priv
->extend_desc
)
1422 priv
->hw
->desc
->init_tx_desc(&priv
->dma_etx
[i
].basic
,
1424 (i
== DMA_TX_SIZE
- 1));
1426 priv
->hw
->desc
->init_tx_desc(&priv
->dma_tx
[i
],
1428 (i
== DMA_TX_SIZE
- 1));
1431 netdev_reset_queue(priv
->dev
);
1432 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1434 priv
->dev
->stats
.tx_errors
++;
1435 netif_wake_queue(priv
->dev
);
1439 * stmmac_dma_interrupt - DMA ISR
1440 * @priv: driver private structure
1441 * Description: this is the DMA ISR. It is called by the main ISR.
1442 * It calls the dwmac dma routine and schedule poll method in case of some
1445 static void stmmac_dma_interrupt(struct stmmac_priv
*priv
)
1448 int rxfifosz
= priv
->plat
->rx_fifo_size
;
1450 status
= priv
->hw
->dma
->dma_interrupt(priv
->ioaddr
, &priv
->xstats
);
1451 if (likely((status
& handle_rx
)) || (status
& handle_tx
)) {
1452 if (likely(napi_schedule_prep(&priv
->napi
))) {
1453 stmmac_disable_dma_irq(priv
);
1454 __napi_schedule(&priv
->napi
);
1457 if (unlikely(status
& tx_hard_error_bump_tc
)) {
1458 /* Try to bump up the dma threshold on this failure */
1459 if (unlikely(priv
->xstats
.threshold
!= SF_DMA_MODE
) &&
1462 if (priv
->plat
->force_thresh_dma_mode
)
1463 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, tc
,
1466 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
,
1467 SF_DMA_MODE
, rxfifosz
);
1468 priv
->xstats
.threshold
= tc
;
1470 } else if (unlikely(status
== tx_hard_error
))
1471 stmmac_tx_err(priv
);
1475 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1476 * @priv: driver private structure
1477 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1479 static void stmmac_mmc_setup(struct stmmac_priv
*priv
)
1481 unsigned int mode
= MMC_CNTRL_RESET_ON_READ
| MMC_CNTRL_COUNTER_RESET
|
1482 MMC_CNTRL_PRESET
| MMC_CNTRL_FULL_HALF_PRESET
;
1484 dwmac_mmc_intr_all_mask(priv
->ioaddr
);
1486 if (priv
->dma_cap
.rmon
) {
1487 dwmac_mmc_ctrl(priv
->ioaddr
, mode
);
1488 memset(&priv
->mmc
, 0, sizeof(struct stmmac_counters
));
1490 pr_info(" No MAC Management Counters available\n");
1494 * stmmac_get_synopsys_id - return the SYINID.
1495 * @priv: driver private structure
1496 * Description: this simple function is to decode and return the SYINID
1497 * starting from the HW core register.
1499 static u32
stmmac_get_synopsys_id(struct stmmac_priv
*priv
)
1501 u32 hwid
= priv
->hw
->synopsys_uid
;
1503 /* Check Synopsys Id (not available on old chips) */
1505 u32 uid
= ((hwid
& 0x0000ff00) >> 8);
1506 u32 synid
= (hwid
& 0x000000ff);
1508 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1517 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1518 * @priv: driver private structure
1519 * Description: select the Enhanced/Alternate or Normal descriptors.
1520 * In case of Enhanced/Alternate, it checks if the extended descriptors are
1521 * supported by the HW capability register.
1523 static void stmmac_selec_desc_mode(struct stmmac_priv
*priv
)
1525 if (priv
->plat
->enh_desc
) {
1526 pr_info(" Enhanced/Alternate descriptors\n");
1528 /* GMAC older than 3.50 has no extended descriptors */
1529 if (priv
->synopsys_id
>= DWMAC_CORE_3_50
) {
1530 pr_info("\tEnabled extended descriptors\n");
1531 priv
->extend_desc
= 1;
1533 pr_warn("Extended descriptors not supported\n");
1535 priv
->hw
->desc
= &enh_desc_ops
;
1537 pr_info(" Normal descriptors\n");
1538 priv
->hw
->desc
= &ndesc_ops
;
1543 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1544 * @priv: driver private structure
1546 * new GMAC chip generations have a new register to indicate the
1547 * presence of the optional feature/functions.
1548 * This can be also used to override the value passed through the
1549 * platform and necessary for old MAC10/100 and GMAC chips.
1551 static int stmmac_get_hw_features(struct stmmac_priv
*priv
)
1555 if (priv
->hw
->dma
->get_hw_feature
) {
1556 hw_cap
= priv
->hw
->dma
->get_hw_feature(priv
->ioaddr
);
1558 priv
->dma_cap
.mbps_10_100
= (hw_cap
& DMA_HW_FEAT_MIISEL
);
1559 priv
->dma_cap
.mbps_1000
= (hw_cap
& DMA_HW_FEAT_GMIISEL
) >> 1;
1560 priv
->dma_cap
.half_duplex
= (hw_cap
& DMA_HW_FEAT_HDSEL
) >> 2;
1561 priv
->dma_cap
.hash_filter
= (hw_cap
& DMA_HW_FEAT_HASHSEL
) >> 4;
1562 priv
->dma_cap
.multi_addr
= (hw_cap
& DMA_HW_FEAT_ADDMAC
) >> 5;
1563 priv
->dma_cap
.pcs
= (hw_cap
& DMA_HW_FEAT_PCSSEL
) >> 6;
1564 priv
->dma_cap
.sma_mdio
= (hw_cap
& DMA_HW_FEAT_SMASEL
) >> 8;
1565 priv
->dma_cap
.pmt_remote_wake_up
=
1566 (hw_cap
& DMA_HW_FEAT_RWKSEL
) >> 9;
1567 priv
->dma_cap
.pmt_magic_frame
=
1568 (hw_cap
& DMA_HW_FEAT_MGKSEL
) >> 10;
1570 priv
->dma_cap
.rmon
= (hw_cap
& DMA_HW_FEAT_MMCSEL
) >> 11;
1571 /* IEEE 1588-2002 */
1572 priv
->dma_cap
.time_stamp
=
1573 (hw_cap
& DMA_HW_FEAT_TSVER1SEL
) >> 12;
1574 /* IEEE 1588-2008 */
1575 priv
->dma_cap
.atime_stamp
=
1576 (hw_cap
& DMA_HW_FEAT_TSVER2SEL
) >> 13;
1577 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1578 priv
->dma_cap
.eee
= (hw_cap
& DMA_HW_FEAT_EEESEL
) >> 14;
1579 priv
->dma_cap
.av
= (hw_cap
& DMA_HW_FEAT_AVSEL
) >> 15;
1580 /* TX and RX csum */
1581 priv
->dma_cap
.tx_coe
= (hw_cap
& DMA_HW_FEAT_TXCOESEL
) >> 16;
1582 priv
->dma_cap
.rx_coe_type1
=
1583 (hw_cap
& DMA_HW_FEAT_RXTYP1COE
) >> 17;
1584 priv
->dma_cap
.rx_coe_type2
=
1585 (hw_cap
& DMA_HW_FEAT_RXTYP2COE
) >> 18;
1586 priv
->dma_cap
.rxfifo_over_2048
=
1587 (hw_cap
& DMA_HW_FEAT_RXFIFOSIZE
) >> 19;
1588 /* TX and RX number of channels */
1589 priv
->dma_cap
.number_rx_channel
=
1590 (hw_cap
& DMA_HW_FEAT_RXCHCNT
) >> 20;
1591 priv
->dma_cap
.number_tx_channel
=
1592 (hw_cap
& DMA_HW_FEAT_TXCHCNT
) >> 22;
1593 /* Alternate (enhanced) DESC mode */
1594 priv
->dma_cap
.enh_desc
= (hw_cap
& DMA_HW_FEAT_ENHDESSEL
) >> 24;
1601 * stmmac_check_ether_addr - check if the MAC addr is valid
1602 * @priv: driver private structure
1604 * it is to verify if the MAC address is valid, in case of failures it
1605 * generates a random MAC address
1607 static void stmmac_check_ether_addr(struct stmmac_priv
*priv
)
1609 if (!is_valid_ether_addr(priv
->dev
->dev_addr
)) {
1610 priv
->hw
->mac
->get_umac_addr(priv
->hw
,
1611 priv
->dev
->dev_addr
, 0);
1612 if (!is_valid_ether_addr(priv
->dev
->dev_addr
))
1613 eth_hw_addr_random(priv
->dev
);
1614 pr_info("%s: device MAC address %pM\n", priv
->dev
->name
,
1615 priv
->dev
->dev_addr
);
1620 * stmmac_init_dma_engine - DMA init.
1621 * @priv: driver private structure
1623 * It inits the DMA invoking the specific MAC/GMAC callback.
1624 * Some DMA parameters can be passed from the platform;
1625 * in case of these are not passed a default is kept for the MAC or GMAC.
1627 static int stmmac_init_dma_engine(struct stmmac_priv
*priv
)
1629 int pbl
= DEFAULT_DMA_PBL
, fixed_burst
= 0, aal
= 0;
1630 int mixed_burst
= 0;
1634 if (priv
->plat
->dma_cfg
) {
1635 pbl
= priv
->plat
->dma_cfg
->pbl
;
1636 fixed_burst
= priv
->plat
->dma_cfg
->fixed_burst
;
1637 mixed_burst
= priv
->plat
->dma_cfg
->mixed_burst
;
1638 aal
= priv
->plat
->dma_cfg
->aal
;
1641 if (priv
->extend_desc
&& (priv
->mode
== STMMAC_RING_MODE
))
1644 ret
= priv
->hw
->dma
->reset(priv
->ioaddr
);
1646 dev_err(priv
->device
, "Failed to reset the dma\n");
1650 priv
->hw
->dma
->init(priv
->ioaddr
, pbl
, fixed_burst
, mixed_burst
,
1651 aal
, priv
->dma_tx_phy
, priv
->dma_rx_phy
, atds
);
1653 if ((priv
->synopsys_id
>= DWMAC_CORE_3_50
) &&
1654 (priv
->plat
->axi
&& priv
->hw
->dma
->axi
))
1655 priv
->hw
->dma
->axi(priv
->ioaddr
, priv
->plat
->axi
);
1661 * stmmac_tx_timer - mitigation sw timer for tx.
1662 * @data: data pointer
1664 * This is the timer handler to directly invoke the stmmac_tx_clean.
1666 static void stmmac_tx_timer(unsigned long data
)
1668 struct stmmac_priv
*priv
= (struct stmmac_priv
*)data
;
1670 stmmac_tx_clean(priv
);
1674 * stmmac_init_tx_coalesce - init tx mitigation options.
1675 * @priv: driver private structure
1677 * This inits the transmit coalesce parameters: i.e. timer rate,
1678 * timer handler and default threshold used for enabling the
1679 * interrupt on completion bit.
1681 static void stmmac_init_tx_coalesce(struct stmmac_priv
*priv
)
1683 priv
->tx_coal_frames
= STMMAC_TX_FRAMES
;
1684 priv
->tx_coal_timer
= STMMAC_COAL_TX_TIMER
;
1685 init_timer(&priv
->txtimer
);
1686 priv
->txtimer
.expires
= STMMAC_COAL_TIMER(priv
->tx_coal_timer
);
1687 priv
->txtimer
.data
= (unsigned long)priv
;
1688 priv
->txtimer
.function
= stmmac_tx_timer
;
1689 add_timer(&priv
->txtimer
);
1693 * stmmac_hw_setup - setup mac in a usable state.
1694 * @dev : pointer to the device structure.
1696 * this is the main function to setup the HW in a usable state because the
1697 * dma engine is reset, the core registers are configured (e.g. AXI,
1698 * Checksum features, timers). The DMA is ready to start receiving and
1701 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1704 static int stmmac_hw_setup(struct net_device
*dev
, bool init_ptp
)
1706 struct stmmac_priv
*priv
= netdev_priv(dev
);
1709 /* DMA initialization and SW reset */
1710 ret
= stmmac_init_dma_engine(priv
);
1712 pr_err("%s: DMA engine initialization failed\n", __func__
);
1716 /* Copy the MAC addr into the HW */
1717 priv
->hw
->mac
->set_umac_addr(priv
->hw
, dev
->dev_addr
, 0);
1719 /* If required, perform hw setup of the bus. */
1720 if (priv
->plat
->bus_setup
)
1721 priv
->plat
->bus_setup(priv
->ioaddr
);
1723 /* Initialize the MAC Core */
1724 priv
->hw
->mac
->core_init(priv
->hw
, dev
->mtu
);
1726 ret
= priv
->hw
->mac
->rx_ipc(priv
->hw
);
1728 pr_warn(" RX IPC Checksum Offload disabled\n");
1729 priv
->plat
->rx_coe
= STMMAC_RX_COE_NONE
;
1730 priv
->hw
->rx_csum
= 0;
1733 /* Enable the MAC Rx/Tx */
1734 stmmac_set_mac(priv
->ioaddr
, true);
1736 /* Set the HW DMA mode and the COE */
1737 stmmac_dma_operation_mode(priv
);
1739 stmmac_mmc_setup(priv
);
1742 ret
= stmmac_init_ptp(priv
);
1743 if (ret
&& ret
!= -EOPNOTSUPP
)
1744 pr_warn("%s: failed PTP initialisation\n", __func__
);
1747 #ifdef CONFIG_DEBUG_FS
1748 ret
= stmmac_init_fs(dev
);
1750 pr_warn("%s: failed debugFS registration\n", __func__
);
1752 /* Start the ball rolling... */
1753 pr_debug("%s: DMA RX/TX processes started...\n", dev
->name
);
1754 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1755 priv
->hw
->dma
->start_rx(priv
->ioaddr
);
1757 /* Dump DMA/MAC registers */
1758 if (netif_msg_hw(priv
)) {
1759 priv
->hw
->mac
->dump_regs(priv
->hw
);
1760 priv
->hw
->dma
->dump_regs(priv
->ioaddr
);
1762 priv
->tx_lpi_timer
= STMMAC_DEFAULT_TWT_LS
;
1764 if ((priv
->use_riwt
) && (priv
->hw
->dma
->rx_watchdog
)) {
1765 priv
->rx_riwt
= MAX_DMA_RIWT
;
1766 priv
->hw
->dma
->rx_watchdog(priv
->ioaddr
, MAX_DMA_RIWT
);
1769 if (priv
->pcs
&& priv
->hw
->mac
->ctrl_ane
)
1770 priv
->hw
->mac
->ctrl_ane(priv
->hw
, 0);
1776 * stmmac_open - open entry point of the driver
1777 * @dev : pointer to the device structure.
1779 * This function is the open entry point of the driver.
1781 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1784 static int stmmac_open(struct net_device
*dev
)
1786 struct stmmac_priv
*priv
= netdev_priv(dev
);
1789 stmmac_check_ether_addr(priv
);
1791 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
1792 priv
->pcs
!= STMMAC_PCS_RTBI
) {
1793 ret
= stmmac_init_phy(dev
);
1795 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1801 /* Extra statistics */
1802 memset(&priv
->xstats
, 0, sizeof(struct stmmac_extra_stats
));
1803 priv
->xstats
.threshold
= tc
;
1805 priv
->dma_buf_sz
= STMMAC_ALIGN(buf_sz
);
1806 priv
->rx_copybreak
= STMMAC_RX_COPYBREAK
;
1808 ret
= alloc_dma_desc_resources(priv
);
1810 pr_err("%s: DMA descriptors allocation failed\n", __func__
);
1811 goto dma_desc_error
;
1814 ret
= init_dma_desc_rings(dev
, GFP_KERNEL
);
1816 pr_err("%s: DMA descriptors initialization failed\n", __func__
);
1820 ret
= stmmac_hw_setup(dev
, true);
1822 pr_err("%s: Hw setup failed\n", __func__
);
1826 stmmac_init_tx_coalesce(priv
);
1829 phy_start(priv
->phydev
);
1831 /* Request the IRQ lines */
1832 ret
= request_irq(dev
->irq
, stmmac_interrupt
,
1833 IRQF_SHARED
, dev
->name
, dev
);
1834 if (unlikely(ret
< 0)) {
1835 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1836 __func__
, dev
->irq
, ret
);
1840 /* Request the Wake IRQ in case of another line is used for WoL */
1841 if (priv
->wol_irq
!= dev
->irq
) {
1842 ret
= request_irq(priv
->wol_irq
, stmmac_interrupt
,
1843 IRQF_SHARED
, dev
->name
, dev
);
1844 if (unlikely(ret
< 0)) {
1845 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1846 __func__
, priv
->wol_irq
, ret
);
1851 /* Request the IRQ lines */
1852 if (priv
->lpi_irq
> 0) {
1853 ret
= request_irq(priv
->lpi_irq
, stmmac_interrupt
, IRQF_SHARED
,
1855 if (unlikely(ret
< 0)) {
1856 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1857 __func__
, priv
->lpi_irq
, ret
);
1862 napi_enable(&priv
->napi
);
1863 netif_start_queue(dev
);
1868 if (priv
->wol_irq
!= dev
->irq
)
1869 free_irq(priv
->wol_irq
, dev
);
1871 free_irq(dev
->irq
, dev
);
1874 free_dma_desc_resources(priv
);
1877 phy_disconnect(priv
->phydev
);
1883 * stmmac_release - close entry point of the driver
1884 * @dev : device pointer.
1886 * This is the stop entry point of the driver.
1888 static int stmmac_release(struct net_device
*dev
)
1890 struct stmmac_priv
*priv
= netdev_priv(dev
);
1892 if (priv
->eee_enabled
)
1893 del_timer_sync(&priv
->eee_ctrl_timer
);
1895 /* Stop and disconnect the PHY */
1897 phy_stop(priv
->phydev
);
1898 phy_disconnect(priv
->phydev
);
1899 priv
->phydev
= NULL
;
1902 netif_stop_queue(dev
);
1904 napi_disable(&priv
->napi
);
1906 del_timer_sync(&priv
->txtimer
);
1908 /* Free the IRQ lines */
1909 free_irq(dev
->irq
, dev
);
1910 if (priv
->wol_irq
!= dev
->irq
)
1911 free_irq(priv
->wol_irq
, dev
);
1912 if (priv
->lpi_irq
> 0)
1913 free_irq(priv
->lpi_irq
, dev
);
1915 /* Stop TX/RX DMA and clear the descriptors */
1916 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1917 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
1919 /* Release and free the Rx/Tx resources */
1920 free_dma_desc_resources(priv
);
1922 /* Disable the MAC Rx/Tx */
1923 stmmac_set_mac(priv
->ioaddr
, false);
1925 netif_carrier_off(dev
);
1927 #ifdef CONFIG_DEBUG_FS
1928 stmmac_exit_fs(dev
);
1931 stmmac_release_ptp(priv
);
1937 * stmmac_xmit - Tx entry point of the driver
1938 * @skb : the socket buffer
1939 * @dev : device pointer
1940 * Description : this is the tx entry point of the driver.
1941 * It programs the chain or the ring and supports oversized frames
1944 static netdev_tx_t
stmmac_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1946 struct stmmac_priv
*priv
= netdev_priv(dev
);
1947 unsigned int nopaged_len
= skb_headlen(skb
);
1948 int i
, csum_insertion
= 0, is_jumbo
= 0;
1949 int nfrags
= skb_shinfo(skb
)->nr_frags
;
1950 unsigned int entry
, first_entry
;
1951 struct dma_desc
*desc
, *first
;
1952 unsigned int enh_desc
;
1954 spin_lock(&priv
->tx_lock
);
1956 if (unlikely(stmmac_tx_avail(priv
) < nfrags
+ 1)) {
1957 spin_unlock(&priv
->tx_lock
);
1958 if (!netif_queue_stopped(dev
)) {
1959 netif_stop_queue(dev
);
1960 /* This is a hard error, log it. */
1961 pr_err("%s: Tx Ring full when queue awake\n", __func__
);
1963 return NETDEV_TX_BUSY
;
1966 if (priv
->tx_path_in_lpi_mode
)
1967 stmmac_disable_eee_mode(priv
);
1969 entry
= priv
->cur_tx
;
1970 first_entry
= entry
;
1972 csum_insertion
= (skb
->ip_summed
== CHECKSUM_PARTIAL
);
1974 if (likely(priv
->extend_desc
))
1975 desc
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
1977 desc
= priv
->dma_tx
+ entry
;
1981 priv
->tx_skbuff
[first_entry
] = skb
;
1983 enh_desc
= priv
->plat
->enh_desc
;
1984 /* To program the descriptors according to the size of the frame */
1986 is_jumbo
= priv
->hw
->mode
->is_jumbo_frm(skb
->len
, enh_desc
);
1988 if (unlikely(is_jumbo
)) {
1989 entry
= priv
->hw
->mode
->jumbo_frm(priv
, skb
, csum_insertion
);
1990 if (unlikely(entry
< 0))
1994 for (i
= 0; i
< nfrags
; i
++) {
1995 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1996 int len
= skb_frag_size(frag
);
1997 bool last_segment
= (i
== (nfrags
- 1));
1999 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
2001 if (likely(priv
->extend_desc
))
2002 desc
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
2004 desc
= priv
->dma_tx
+ entry
;
2006 desc
->des2
= skb_frag_dma_map(priv
->device
, frag
, 0, len
,
2008 if (dma_mapping_error(priv
->device
, desc
->des2
))
2009 goto dma_map_err
; /* should reuse desc w/o issues */
2011 priv
->tx_skbuff
[entry
] = NULL
;
2012 priv
->tx_skbuff_dma
[entry
].buf
= desc
->des2
;
2013 priv
->tx_skbuff_dma
[entry
].map_as_page
= true;
2014 priv
->tx_skbuff_dma
[entry
].len
= len
;
2015 priv
->tx_skbuff_dma
[entry
].last_segment
= last_segment
;
2017 /* Prepare the descriptor and set the own bit too */
2018 priv
->hw
->desc
->prepare_tx_desc(desc
, 0, len
, csum_insertion
,
2019 priv
->mode
, 1, last_segment
);
2022 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
2024 priv
->cur_tx
= entry
;
2026 if (netif_msg_pktdata(priv
)) {
2027 pr_debug("%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
2028 __func__
, priv
->cur_tx
, priv
->dirty_tx
, first_entry
,
2029 entry
, first
, nfrags
);
2031 if (priv
->extend_desc
)
2032 stmmac_display_ring((void *)priv
->dma_etx
,
2035 stmmac_display_ring((void *)priv
->dma_tx
,
2038 pr_debug(">>> frame to be transmitted: ");
2039 print_pkt(skb
->data
, skb
->len
);
2042 if (unlikely(stmmac_tx_avail(priv
) <= (MAX_SKB_FRAGS
+ 1))) {
2043 if (netif_msg_hw(priv
))
2044 pr_debug("%s: stop transmitted packets\n", __func__
);
2045 netif_stop_queue(dev
);
2048 dev
->stats
.tx_bytes
+= skb
->len
;
2050 /* According to the coalesce parameter the IC bit for the latest
2051 * segment is reset and the timer re-started to clean the tx status.
2052 * This approach takes care about the fragments: desc is the first
2053 * element in case of no SG.
2055 priv
->tx_count_frames
+= nfrags
+ 1;
2056 if (likely(priv
->tx_coal_frames
> priv
->tx_count_frames
)) {
2057 mod_timer(&priv
->txtimer
,
2058 STMMAC_COAL_TIMER(priv
->tx_coal_timer
));
2060 priv
->tx_count_frames
= 0;
2061 priv
->hw
->desc
->set_tx_ic(desc
);
2062 priv
->xstats
.tx_set_ic_bit
++;
2065 if (!priv
->hwts_tx_en
)
2066 skb_tx_timestamp(skb
);
2068 /* Ready to fill the first descriptor and set the OWN bit w/o any
2069 * problems because all the descriptors are actually ready to be
2070 * passed to the DMA engine.
2072 if (likely(!is_jumbo
)) {
2073 bool last_segment
= (nfrags
== 0);
2075 first
->des2
= dma_map_single(priv
->device
, skb
->data
,
2076 nopaged_len
, DMA_TO_DEVICE
);
2077 if (dma_mapping_error(priv
->device
, first
->des2
))
2080 priv
->tx_skbuff_dma
[first_entry
].buf
= first
->des2
;
2081 priv
->tx_skbuff_dma
[first_entry
].len
= nopaged_len
;
2082 priv
->tx_skbuff_dma
[first_entry
].last_segment
= last_segment
;
2084 if (unlikely((skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) &&
2085 priv
->hwts_tx_en
)) {
2086 /* declare that device is doing timestamping */
2087 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
2088 priv
->hw
->desc
->enable_tx_timestamp(first
);
2091 /* Prepare the first descriptor setting the OWN bit too */
2092 priv
->hw
->desc
->prepare_tx_desc(first
, 1, nopaged_len
,
2093 csum_insertion
, priv
->mode
, 1,
2096 /* The own bit must be the latest setting done when prepare the
2097 * descriptor and then barrier is needed to make sure that
2098 * all is coherent before granting the DMA engine.
2103 netdev_sent_queue(dev
, skb
->len
);
2104 priv
->hw
->dma
->enable_dma_transmission(priv
->ioaddr
);
2106 spin_unlock(&priv
->tx_lock
);
2107 return NETDEV_TX_OK
;
2110 spin_unlock(&priv
->tx_lock
);
2111 dev_err(priv
->device
, "Tx dma map failed\n");
2113 priv
->dev
->stats
.tx_dropped
++;
2114 return NETDEV_TX_OK
;
2117 static void stmmac_rx_vlan(struct net_device
*dev
, struct sk_buff
*skb
)
2119 struct ethhdr
*ehdr
;
2122 if ((dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) ==
2123 NETIF_F_HW_VLAN_CTAG_RX
&&
2124 !__vlan_get_tag(skb
, &vlanid
)) {
2125 /* pop the vlan tag */
2126 ehdr
= (struct ethhdr
*)skb
->data
;
2127 memmove(skb
->data
+ VLAN_HLEN
, ehdr
, ETH_ALEN
* 2);
2128 skb_pull(skb
, VLAN_HLEN
);
2129 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vlanid
);
2134 static inline int stmmac_rx_threshold_count(struct stmmac_priv
*priv
)
2136 if (priv
->rx_zeroc_thresh
< STMMAC_RX_THRESH
)
2143 * stmmac_rx_refill - refill used skb preallocated buffers
2144 * @priv: driver private structure
2145 * Description : this is to reallocate the skb for the reception process
2146 * that is based on zero-copy.
2148 static inline void stmmac_rx_refill(struct stmmac_priv
*priv
)
2150 int bfsize
= priv
->dma_buf_sz
;
2151 unsigned int entry
= priv
->dirty_rx
;
2152 int dirty
= stmmac_rx_dirty(priv
);
2154 while (dirty
-- > 0) {
2157 if (priv
->extend_desc
)
2158 p
= (struct dma_desc
*)(priv
->dma_erx
+ entry
);
2160 p
= priv
->dma_rx
+ entry
;
2162 if (likely(priv
->rx_skbuff
[entry
] == NULL
)) {
2163 struct sk_buff
*skb
;
2165 skb
= netdev_alloc_skb_ip_align(priv
->dev
, bfsize
);
2166 if (unlikely(!skb
)) {
2167 /* so for a while no zero-copy! */
2168 priv
->rx_zeroc_thresh
= STMMAC_RX_THRESH
;
2169 if (unlikely(net_ratelimit()))
2170 dev_err(priv
->device
,
2171 "fail to alloc skb entry %d\n",
2176 priv
->rx_skbuff
[entry
] = skb
;
2177 priv
->rx_skbuff_dma
[entry
] =
2178 dma_map_single(priv
->device
, skb
->data
, bfsize
,
2180 if (dma_mapping_error(priv
->device
,
2181 priv
->rx_skbuff_dma
[entry
])) {
2182 dev_err(priv
->device
, "Rx dma map failed\n");
2186 p
->des2
= priv
->rx_skbuff_dma
[entry
];
2188 priv
->hw
->mode
->refill_desc3(priv
, p
);
2190 if (priv
->rx_zeroc_thresh
> 0)
2191 priv
->rx_zeroc_thresh
--;
2193 if (netif_msg_rx_status(priv
))
2194 pr_debug("\trefill entry #%d\n", entry
);
2198 priv
->hw
->desc
->set_rx_owner(p
);
2201 entry
= STMMAC_GET_ENTRY(entry
, DMA_RX_SIZE
);
2203 priv
->dirty_rx
= entry
;
2207 * stmmac_rx - manage the receive process
2208 * @priv: driver private structure
2209 * @limit: napi bugget.
2210 * Description : this the function called by the napi poll method.
2211 * It gets all the frames inside the ring.
2213 static int stmmac_rx(struct stmmac_priv
*priv
, int limit
)
2215 unsigned int entry
= priv
->cur_rx
;
2216 unsigned int next_entry
;
2217 unsigned int count
= 0;
2218 int coe
= priv
->hw
->rx_csum
;
2220 if (netif_msg_rx_status(priv
)) {
2221 pr_debug("%s: descriptor ring:\n", __func__
);
2222 if (priv
->extend_desc
)
2223 stmmac_display_ring((void *)priv
->dma_erx
,
2226 stmmac_display_ring((void *)priv
->dma_rx
,
2229 while (count
< limit
) {
2233 if (priv
->extend_desc
)
2234 p
= (struct dma_desc
*)(priv
->dma_erx
+ entry
);
2236 p
= priv
->dma_rx
+ entry
;
2238 /* read the status of the incoming frame */
2239 status
= priv
->hw
->desc
->rx_status(&priv
->dev
->stats
,
2241 /* check if managed by the DMA otherwise go ahead */
2242 if (unlikely(status
& dma_own
))
2247 priv
->cur_rx
= STMMAC_GET_ENTRY(priv
->cur_rx
, DMA_RX_SIZE
);
2248 next_entry
= priv
->cur_rx
;
2250 if (priv
->extend_desc
)
2251 prefetch(priv
->dma_erx
+ next_entry
);
2253 prefetch(priv
->dma_rx
+ next_entry
);
2255 if ((priv
->extend_desc
) && (priv
->hw
->desc
->rx_extended_status
))
2256 priv
->hw
->desc
->rx_extended_status(&priv
->dev
->stats
,
2260 if (unlikely(status
== discard_frame
)) {
2261 priv
->dev
->stats
.rx_errors
++;
2262 if (priv
->hwts_rx_en
&& !priv
->extend_desc
) {
2263 /* DESC2 & DESC3 will be overwitten by device
2264 * with timestamp value, hence reinitialize
2265 * them in stmmac_rx_refill() function so that
2266 * device can reuse it.
2268 priv
->rx_skbuff
[entry
] = NULL
;
2269 dma_unmap_single(priv
->device
,
2270 priv
->rx_skbuff_dma
[entry
],
2275 struct sk_buff
*skb
;
2278 frame_len
= priv
->hw
->desc
->get_rx_frame_len(p
, coe
);
2280 /* check if frame_len fits the preallocated memory */
2281 if (frame_len
> priv
->dma_buf_sz
) {
2282 priv
->dev
->stats
.rx_length_errors
++;
2286 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2287 * Type frames (LLC/LLC-SNAP)
2289 if (unlikely(status
!= llc_snap
))
2290 frame_len
-= ETH_FCS_LEN
;
2292 if (netif_msg_rx_status(priv
)) {
2293 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2295 if (frame_len
> ETH_FRAME_LEN
)
2296 pr_debug("\tframe size %d, COE: %d\n",
2300 if (unlikely((frame_len
< priv
->rx_copybreak
) ||
2301 stmmac_rx_threshold_count(priv
))) {
2302 skb
= netdev_alloc_skb_ip_align(priv
->dev
,
2304 if (unlikely(!skb
)) {
2305 if (net_ratelimit())
2306 dev_warn(priv
->device
,
2307 "packet dropped\n");
2308 priv
->dev
->stats
.rx_dropped
++;
2312 dma_sync_single_for_cpu(priv
->device
,
2316 skb_copy_to_linear_data(skb
,
2318 rx_skbuff
[entry
]->data
,
2321 skb_put(skb
, frame_len
);
2322 dma_sync_single_for_device(priv
->device
,
2327 skb
= priv
->rx_skbuff
[entry
];
2328 if (unlikely(!skb
)) {
2329 pr_err("%s: Inconsistent Rx chain\n",
2331 priv
->dev
->stats
.rx_dropped
++;
2334 prefetch(skb
->data
- NET_IP_ALIGN
);
2335 priv
->rx_skbuff
[entry
] = NULL
;
2336 priv
->rx_zeroc_thresh
++;
2338 skb_put(skb
, frame_len
);
2339 dma_unmap_single(priv
->device
,
2340 priv
->rx_skbuff_dma
[entry
],
2345 stmmac_get_rx_hwtstamp(priv
, entry
, skb
);
2347 if (netif_msg_pktdata(priv
)) {
2348 pr_debug("frame received (%dbytes)", frame_len
);
2349 print_pkt(skb
->data
, frame_len
);
2352 stmmac_rx_vlan(priv
->dev
, skb
);
2354 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
2357 skb_checksum_none_assert(skb
);
2359 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2361 napi_gro_receive(&priv
->napi
, skb
);
2363 priv
->dev
->stats
.rx_packets
++;
2364 priv
->dev
->stats
.rx_bytes
+= frame_len
;
2369 stmmac_rx_refill(priv
);
2371 priv
->xstats
.rx_pkt_n
+= count
;
2377 * stmmac_poll - stmmac poll method (NAPI)
2378 * @napi : pointer to the napi structure.
2379 * @budget : maximum number of packets that the current CPU can receive from
2382 * To look at the incoming frames and clear the tx resources.
2384 static int stmmac_poll(struct napi_struct
*napi
, int budget
)
2386 struct stmmac_priv
*priv
= container_of(napi
, struct stmmac_priv
, napi
);
2389 priv
->xstats
.napi_poll
++;
2390 stmmac_tx_clean(priv
);
2392 work_done
= stmmac_rx(priv
, budget
);
2393 if (work_done
< budget
) {
2394 napi_complete(napi
);
2395 stmmac_enable_dma_irq(priv
);
2402 * @dev : Pointer to net device structure
2403 * Description: this function is called when a packet transmission fails to
2404 * complete within a reasonable time. The driver will mark the error in the
2405 * netdev structure and arrange for the device to be reset to a sane state
2406 * in order to transmit a new packet.
2408 static void stmmac_tx_timeout(struct net_device
*dev
)
2410 struct stmmac_priv
*priv
= netdev_priv(dev
);
2412 /* Clear Tx resources and restart transmitting again */
2413 stmmac_tx_err(priv
);
2417 * stmmac_set_rx_mode - entry point for multicast addressing
2418 * @dev : pointer to the device structure
2420 * This function is a driver entry point which gets called by the kernel
2421 * whenever multicast addresses must be enabled/disabled.
2425 static void stmmac_set_rx_mode(struct net_device
*dev
)
2427 struct stmmac_priv
*priv
= netdev_priv(dev
);
2429 priv
->hw
->mac
->set_filter(priv
->hw
, dev
);
2433 * stmmac_change_mtu - entry point to change MTU size for the device.
2434 * @dev : device pointer.
2435 * @new_mtu : the new MTU size for the device.
2436 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2437 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2438 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2440 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2443 static int stmmac_change_mtu(struct net_device
*dev
, int new_mtu
)
2445 struct stmmac_priv
*priv
= netdev_priv(dev
);
2448 if (netif_running(dev
)) {
2449 pr_err("%s: must be stopped to change its MTU\n", dev
->name
);
2453 if (priv
->plat
->enh_desc
)
2454 max_mtu
= JUMBO_LEN
;
2456 max_mtu
= SKB_MAX_HEAD(NET_SKB_PAD
+ NET_IP_ALIGN
);
2458 if (priv
->plat
->maxmtu
< max_mtu
)
2459 max_mtu
= priv
->plat
->maxmtu
;
2461 if ((new_mtu
< 46) || (new_mtu
> max_mtu
)) {
2462 pr_err("%s: invalid MTU, max MTU is: %d\n", dev
->name
, max_mtu
);
2467 netdev_update_features(dev
);
2472 static netdev_features_t
stmmac_fix_features(struct net_device
*dev
,
2473 netdev_features_t features
)
2475 struct stmmac_priv
*priv
= netdev_priv(dev
);
2477 if (priv
->plat
->rx_coe
== STMMAC_RX_COE_NONE
)
2478 features
&= ~NETIF_F_RXCSUM
;
2480 if (!priv
->plat
->tx_coe
)
2481 features
&= ~NETIF_F_CSUM_MASK
;
2483 /* Some GMAC devices have a bugged Jumbo frame support that
2484 * needs to have the Tx COE disabled for oversized frames
2485 * (due to limited buffer sizes). In this case we disable
2486 * the TX csum insertionin the TDES and not use SF.
2488 if (priv
->plat
->bugged_jumbo
&& (dev
->mtu
> ETH_DATA_LEN
))
2489 features
&= ~NETIF_F_CSUM_MASK
;
2494 static int stmmac_set_features(struct net_device
*netdev
,
2495 netdev_features_t features
)
2497 struct stmmac_priv
*priv
= netdev_priv(netdev
);
2499 /* Keep the COE Type in case of csum is supporting */
2500 if (features
& NETIF_F_RXCSUM
)
2501 priv
->hw
->rx_csum
= priv
->plat
->rx_coe
;
2503 priv
->hw
->rx_csum
= 0;
2504 /* No check needed because rx_coe has been set before and it will be
2505 * fixed in case of issue.
2507 priv
->hw
->mac
->rx_ipc(priv
->hw
);
2513 * stmmac_interrupt - main ISR
2514 * @irq: interrupt number.
2515 * @dev_id: to pass the net device pointer.
2516 * Description: this is the main driver interrupt service routine.
2518 * o DMA service routine (to manage incoming frame reception and transmission
2520 * o Core interrupts to manage: remote wake-up, management counter, LPI
2523 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
)
2525 struct net_device
*dev
= (struct net_device
*)dev_id
;
2526 struct stmmac_priv
*priv
= netdev_priv(dev
);
2529 pm_wakeup_event(priv
->device
, 0);
2531 if (unlikely(!dev
)) {
2532 pr_err("%s: invalid dev pointer\n", __func__
);
2536 /* To handle GMAC own interrupts */
2537 if (priv
->plat
->has_gmac
) {
2538 int status
= priv
->hw
->mac
->host_irq_status(priv
->hw
,
2540 if (unlikely(status
)) {
2541 /* For LPI we need to save the tx status */
2542 if (status
& CORE_IRQ_TX_PATH_IN_LPI_MODE
)
2543 priv
->tx_path_in_lpi_mode
= true;
2544 if (status
& CORE_IRQ_TX_PATH_EXIT_LPI_MODE
)
2545 priv
->tx_path_in_lpi_mode
= false;
2549 /* To handle DMA interrupts */
2550 stmmac_dma_interrupt(priv
);
2555 #ifdef CONFIG_NET_POLL_CONTROLLER
2556 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2557 * to allow network I/O with interrupts disabled.
2559 static void stmmac_poll_controller(struct net_device
*dev
)
2561 disable_irq(dev
->irq
);
2562 stmmac_interrupt(dev
->irq
, dev
);
2563 enable_irq(dev
->irq
);
2568 * stmmac_ioctl - Entry point for the Ioctl
2569 * @dev: Device pointer.
2570 * @rq: An IOCTL specefic structure, that can contain a pointer to
2571 * a proprietary structure used to pass information to the driver.
2572 * @cmd: IOCTL command
2574 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2576 static int stmmac_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2578 struct stmmac_priv
*priv
= netdev_priv(dev
);
2579 int ret
= -EOPNOTSUPP
;
2581 if (!netif_running(dev
))
2590 ret
= phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
2593 ret
= stmmac_hwtstamp_ioctl(dev
, rq
);
2602 #ifdef CONFIG_DEBUG_FS
2603 static struct dentry
*stmmac_fs_dir
;
2605 static void sysfs_display_ring(void *head
, int size
, int extend_desc
,
2606 struct seq_file
*seq
)
2609 struct dma_extended_desc
*ep
= (struct dma_extended_desc
*)head
;
2610 struct dma_desc
*p
= (struct dma_desc
*)head
;
2612 for (i
= 0; i
< size
; i
++) {
2616 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2617 i
, (unsigned int)virt_to_phys(ep
),
2618 (unsigned int)x
, (unsigned int)(x
>> 32),
2619 ep
->basic
.des2
, ep
->basic
.des3
);
2623 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2624 i
, (unsigned int)virt_to_phys(ep
),
2625 (unsigned int)x
, (unsigned int)(x
>> 32),
2629 seq_printf(seq
, "\n");
2633 static int stmmac_sysfs_ring_read(struct seq_file
*seq
, void *v
)
2635 struct net_device
*dev
= seq
->private;
2636 struct stmmac_priv
*priv
= netdev_priv(dev
);
2638 if (priv
->extend_desc
) {
2639 seq_printf(seq
, "Extended RX descriptor ring:\n");
2640 sysfs_display_ring((void *)priv
->dma_erx
, DMA_RX_SIZE
, 1, seq
);
2641 seq_printf(seq
, "Extended TX descriptor ring:\n");
2642 sysfs_display_ring((void *)priv
->dma_etx
, DMA_TX_SIZE
, 1, seq
);
2644 seq_printf(seq
, "RX descriptor ring:\n");
2645 sysfs_display_ring((void *)priv
->dma_rx
, DMA_RX_SIZE
, 0, seq
);
2646 seq_printf(seq
, "TX descriptor ring:\n");
2647 sysfs_display_ring((void *)priv
->dma_tx
, DMA_TX_SIZE
, 0, seq
);
2653 static int stmmac_sysfs_ring_open(struct inode
*inode
, struct file
*file
)
2655 return single_open(file
, stmmac_sysfs_ring_read
, inode
->i_private
);
2658 static const struct file_operations stmmac_rings_status_fops
= {
2659 .owner
= THIS_MODULE
,
2660 .open
= stmmac_sysfs_ring_open
,
2662 .llseek
= seq_lseek
,
2663 .release
= single_release
,
2666 static int stmmac_sysfs_dma_cap_read(struct seq_file
*seq
, void *v
)
2668 struct net_device
*dev
= seq
->private;
2669 struct stmmac_priv
*priv
= netdev_priv(dev
);
2671 if (!priv
->hw_cap_support
) {
2672 seq_printf(seq
, "DMA HW features not supported\n");
2676 seq_printf(seq
, "==============================\n");
2677 seq_printf(seq
, "\tDMA HW features\n");
2678 seq_printf(seq
, "==============================\n");
2680 seq_printf(seq
, "\t10/100 Mbps %s\n",
2681 (priv
->dma_cap
.mbps_10_100
) ? "Y" : "N");
2682 seq_printf(seq
, "\t1000 Mbps %s\n",
2683 (priv
->dma_cap
.mbps_1000
) ? "Y" : "N");
2684 seq_printf(seq
, "\tHalf duple %s\n",
2685 (priv
->dma_cap
.half_duplex
) ? "Y" : "N");
2686 seq_printf(seq
, "\tHash Filter: %s\n",
2687 (priv
->dma_cap
.hash_filter
) ? "Y" : "N");
2688 seq_printf(seq
, "\tMultiple MAC address registers: %s\n",
2689 (priv
->dma_cap
.multi_addr
) ? "Y" : "N");
2690 seq_printf(seq
, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2691 (priv
->dma_cap
.pcs
) ? "Y" : "N");
2692 seq_printf(seq
, "\tSMA (MDIO) Interface: %s\n",
2693 (priv
->dma_cap
.sma_mdio
) ? "Y" : "N");
2694 seq_printf(seq
, "\tPMT Remote wake up: %s\n",
2695 (priv
->dma_cap
.pmt_remote_wake_up
) ? "Y" : "N");
2696 seq_printf(seq
, "\tPMT Magic Frame: %s\n",
2697 (priv
->dma_cap
.pmt_magic_frame
) ? "Y" : "N");
2698 seq_printf(seq
, "\tRMON module: %s\n",
2699 (priv
->dma_cap
.rmon
) ? "Y" : "N");
2700 seq_printf(seq
, "\tIEEE 1588-2002 Time Stamp: %s\n",
2701 (priv
->dma_cap
.time_stamp
) ? "Y" : "N");
2702 seq_printf(seq
, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2703 (priv
->dma_cap
.atime_stamp
) ? "Y" : "N");
2704 seq_printf(seq
, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2705 (priv
->dma_cap
.eee
) ? "Y" : "N");
2706 seq_printf(seq
, "\tAV features: %s\n", (priv
->dma_cap
.av
) ? "Y" : "N");
2707 seq_printf(seq
, "\tChecksum Offload in TX: %s\n",
2708 (priv
->dma_cap
.tx_coe
) ? "Y" : "N");
2709 seq_printf(seq
, "\tIP Checksum Offload (type1) in RX: %s\n",
2710 (priv
->dma_cap
.rx_coe_type1
) ? "Y" : "N");
2711 seq_printf(seq
, "\tIP Checksum Offload (type2) in RX: %s\n",
2712 (priv
->dma_cap
.rx_coe_type2
) ? "Y" : "N");
2713 seq_printf(seq
, "\tRXFIFO > 2048bytes: %s\n",
2714 (priv
->dma_cap
.rxfifo_over_2048
) ? "Y" : "N");
2715 seq_printf(seq
, "\tNumber of Additional RX channel: %d\n",
2716 priv
->dma_cap
.number_rx_channel
);
2717 seq_printf(seq
, "\tNumber of Additional TX channel: %d\n",
2718 priv
->dma_cap
.number_tx_channel
);
2719 seq_printf(seq
, "\tEnhanced descriptors: %s\n",
2720 (priv
->dma_cap
.enh_desc
) ? "Y" : "N");
2725 static int stmmac_sysfs_dma_cap_open(struct inode
*inode
, struct file
*file
)
2727 return single_open(file
, stmmac_sysfs_dma_cap_read
, inode
->i_private
);
2730 static const struct file_operations stmmac_dma_cap_fops
= {
2731 .owner
= THIS_MODULE
,
2732 .open
= stmmac_sysfs_dma_cap_open
,
2734 .llseek
= seq_lseek
,
2735 .release
= single_release
,
2738 static int stmmac_init_fs(struct net_device
*dev
)
2740 struct stmmac_priv
*priv
= netdev_priv(dev
);
2742 /* Create per netdev entries */
2743 priv
->dbgfs_dir
= debugfs_create_dir(dev
->name
, stmmac_fs_dir
);
2745 if (!priv
->dbgfs_dir
|| IS_ERR(priv
->dbgfs_dir
)) {
2746 pr_err("ERROR %s/%s, debugfs create directory failed\n",
2747 STMMAC_RESOURCE_NAME
, dev
->name
);
2752 /* Entry to report DMA RX/TX rings */
2753 priv
->dbgfs_rings_status
=
2754 debugfs_create_file("descriptors_status", S_IRUGO
,
2755 priv
->dbgfs_dir
, dev
,
2756 &stmmac_rings_status_fops
);
2758 if (!priv
->dbgfs_rings_status
|| IS_ERR(priv
->dbgfs_rings_status
)) {
2759 pr_info("ERROR creating stmmac ring debugfs file\n");
2760 debugfs_remove_recursive(priv
->dbgfs_dir
);
2765 /* Entry to report the DMA HW features */
2766 priv
->dbgfs_dma_cap
= debugfs_create_file("dma_cap", S_IRUGO
,
2768 dev
, &stmmac_dma_cap_fops
);
2770 if (!priv
->dbgfs_dma_cap
|| IS_ERR(priv
->dbgfs_dma_cap
)) {
2771 pr_info("ERROR creating stmmac MMC debugfs file\n");
2772 debugfs_remove_recursive(priv
->dbgfs_dir
);
2780 static void stmmac_exit_fs(struct net_device
*dev
)
2782 struct stmmac_priv
*priv
= netdev_priv(dev
);
2784 debugfs_remove_recursive(priv
->dbgfs_dir
);
2786 #endif /* CONFIG_DEBUG_FS */
2788 static const struct net_device_ops stmmac_netdev_ops
= {
2789 .ndo_open
= stmmac_open
,
2790 .ndo_start_xmit
= stmmac_xmit
,
2791 .ndo_stop
= stmmac_release
,
2792 .ndo_change_mtu
= stmmac_change_mtu
,
2793 .ndo_fix_features
= stmmac_fix_features
,
2794 .ndo_set_features
= stmmac_set_features
,
2795 .ndo_set_rx_mode
= stmmac_set_rx_mode
,
2796 .ndo_tx_timeout
= stmmac_tx_timeout
,
2797 .ndo_do_ioctl
= stmmac_ioctl
,
2798 #ifdef CONFIG_NET_POLL_CONTROLLER
2799 .ndo_poll_controller
= stmmac_poll_controller
,
2801 .ndo_set_mac_address
= eth_mac_addr
,
2805 * stmmac_hw_init - Init the MAC device
2806 * @priv: driver private structure
2807 * Description: this function is to configure the MAC device according to
2808 * some platform parameters or the HW capability register. It prepares the
2809 * driver to use either ring or chain modes and to setup either enhanced or
2810 * normal descriptors.
2812 static int stmmac_hw_init(struct stmmac_priv
*priv
)
2814 struct mac_device_info
*mac
;
2816 /* Identify the MAC HW device */
2817 if (priv
->plat
->has_gmac
) {
2818 priv
->dev
->priv_flags
|= IFF_UNICAST_FLT
;
2819 mac
= dwmac1000_setup(priv
->ioaddr
,
2820 priv
->plat
->multicast_filter_bins
,
2821 priv
->plat
->unicast_filter_entries
);
2823 mac
= dwmac100_setup(priv
->ioaddr
);
2830 /* Get and dump the chip ID */
2831 priv
->synopsys_id
= stmmac_get_synopsys_id(priv
);
2833 /* To use the chained or ring mode */
2835 priv
->hw
->mode
= &chain_mode_ops
;
2836 pr_info(" Chain mode enabled\n");
2837 priv
->mode
= STMMAC_CHAIN_MODE
;
2839 priv
->hw
->mode
= &ring_mode_ops
;
2840 pr_info(" Ring mode enabled\n");
2841 priv
->mode
= STMMAC_RING_MODE
;
2844 /* Get the HW capability (new GMAC newer than 3.50a) */
2845 priv
->hw_cap_support
= stmmac_get_hw_features(priv
);
2846 if (priv
->hw_cap_support
) {
2847 pr_info(" DMA HW capability register supported");
2849 /* We can override some gmac/dma configuration fields: e.g.
2850 * enh_desc, tx_coe (e.g. that are passed through the
2851 * platform) with the values from the HW capability
2852 * register (if supported).
2854 priv
->plat
->enh_desc
= priv
->dma_cap
.enh_desc
;
2855 priv
->plat
->pmt
= priv
->dma_cap
.pmt_remote_wake_up
;
2857 /* TXCOE doesn't work in thresh DMA mode */
2858 if (priv
->plat
->force_thresh_dma_mode
)
2859 priv
->plat
->tx_coe
= 0;
2861 priv
->plat
->tx_coe
= priv
->dma_cap
.tx_coe
;
2863 if (priv
->dma_cap
.rx_coe_type2
)
2864 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE2
;
2865 else if (priv
->dma_cap
.rx_coe_type1
)
2866 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE1
;
2869 pr_info(" No HW DMA feature register supported");
2871 /* To use alternate (extended) or normal descriptor structures */
2872 stmmac_selec_desc_mode(priv
);
2874 if (priv
->plat
->rx_coe
) {
2875 priv
->hw
->rx_csum
= priv
->plat
->rx_coe
;
2876 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2877 priv
->plat
->rx_coe
);
2879 if (priv
->plat
->tx_coe
)
2880 pr_info(" TX Checksum insertion supported\n");
2882 if (priv
->plat
->pmt
) {
2883 pr_info(" Wake-Up On Lan supported\n");
2884 device_set_wakeup_capable(priv
->device
, 1);
2892 * @device: device pointer
2893 * @plat_dat: platform data pointer
2894 * @res: stmmac resource pointer
2895 * Description: this is the main probe function used to
2896 * call the alloc_etherdev, allocate the priv structure.
2898 * returns 0 on success, otherwise errno.
2900 int stmmac_dvr_probe(struct device
*device
,
2901 struct plat_stmmacenet_data
*plat_dat
,
2902 struct stmmac_resources
*res
)
2905 struct net_device
*ndev
= NULL
;
2906 struct stmmac_priv
*priv
;
2908 ndev
= alloc_etherdev(sizeof(struct stmmac_priv
));
2912 SET_NETDEV_DEV(ndev
, device
);
2914 priv
= netdev_priv(ndev
);
2915 priv
->device
= device
;
2918 stmmac_set_ethtool_ops(ndev
);
2919 priv
->pause
= pause
;
2920 priv
->plat
= plat_dat
;
2921 priv
->ioaddr
= res
->addr
;
2922 priv
->dev
->base_addr
= (unsigned long)res
->addr
;
2924 priv
->dev
->irq
= res
->irq
;
2925 priv
->wol_irq
= res
->wol_irq
;
2926 priv
->lpi_irq
= res
->lpi_irq
;
2929 memcpy(priv
->dev
->dev_addr
, res
->mac
, ETH_ALEN
);
2931 dev_set_drvdata(device
, priv
->dev
);
2933 /* Verify driver arguments */
2934 stmmac_verify_args();
2936 /* Override with kernel parameters if supplied XXX CRS XXX
2937 * this needs to have multiple instances
2939 if ((phyaddr
>= 0) && (phyaddr
<= 31))
2940 priv
->plat
->phy_addr
= phyaddr
;
2942 priv
->stmmac_clk
= devm_clk_get(priv
->device
, STMMAC_RESOURCE_NAME
);
2943 if (IS_ERR(priv
->stmmac_clk
)) {
2944 dev_warn(priv
->device
, "%s: warning: cannot get CSR clock\n",
2946 /* If failed to obtain stmmac_clk and specific clk_csr value
2947 * is NOT passed from the platform, probe fail.
2949 if (!priv
->plat
->clk_csr
) {
2950 ret
= PTR_ERR(priv
->stmmac_clk
);
2953 priv
->stmmac_clk
= NULL
;
2956 clk_prepare_enable(priv
->stmmac_clk
);
2958 priv
->pclk
= devm_clk_get(priv
->device
, "pclk");
2959 if (IS_ERR(priv
->pclk
)) {
2960 if (PTR_ERR(priv
->pclk
) == -EPROBE_DEFER
) {
2961 ret
= -EPROBE_DEFER
;
2962 goto error_pclk_get
;
2966 clk_prepare_enable(priv
->pclk
);
2968 priv
->stmmac_rst
= devm_reset_control_get(priv
->device
,
2969 STMMAC_RESOURCE_NAME
);
2970 if (IS_ERR(priv
->stmmac_rst
)) {
2971 if (PTR_ERR(priv
->stmmac_rst
) == -EPROBE_DEFER
) {
2972 ret
= -EPROBE_DEFER
;
2975 dev_info(priv
->device
, "no reset control found\n");
2976 priv
->stmmac_rst
= NULL
;
2978 if (priv
->stmmac_rst
)
2979 reset_control_deassert(priv
->stmmac_rst
);
2981 /* Init MAC and get the capabilities */
2982 ret
= stmmac_hw_init(priv
);
2986 ndev
->netdev_ops
= &stmmac_netdev_ops
;
2988 ndev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
2990 ndev
->features
|= ndev
->hw_features
| NETIF_F_HIGHDMA
;
2991 ndev
->watchdog_timeo
= msecs_to_jiffies(watchdog
);
2992 #ifdef STMMAC_VLAN_TAG_USED
2993 /* Both mac100 and gmac support receive VLAN tag detection */
2994 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_RX
;
2996 priv
->msg_enable
= netif_msg_init(debug
, default_msg_level
);
2999 priv
->flow_ctrl
= FLOW_AUTO
; /* RX/TX pause on */
3001 /* Rx Watchdog is available in the COREs newer than the 3.40.
3002 * In some case, for example on bugged HW this feature
3003 * has to be disable and this can be done by passing the
3004 * riwt_off field from the platform.
3006 if ((priv
->synopsys_id
>= DWMAC_CORE_3_50
) && (!priv
->plat
->riwt_off
)) {
3008 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
3011 netif_napi_add(ndev
, &priv
->napi
, stmmac_poll
, 64);
3013 spin_lock_init(&priv
->lock
);
3014 spin_lock_init(&priv
->tx_lock
);
3016 ret
= register_netdev(ndev
);
3018 pr_err("%s: ERROR %i registering the device\n", __func__
, ret
);
3019 goto error_netdev_register
;
3022 /* If a specific clk_csr value is passed from the platform
3023 * this means that the CSR Clock Range selection cannot be
3024 * changed at run-time and it is fixed. Viceversa the driver'll try to
3025 * set the MDC clock dynamically according to the csr actual
3028 if (!priv
->plat
->clk_csr
)
3029 stmmac_clk_csr_set(priv
);
3031 priv
->clk_csr
= priv
->plat
->clk_csr
;
3033 stmmac_check_pcs_mode(priv
);
3035 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
3036 priv
->pcs
!= STMMAC_PCS_RTBI
) {
3037 /* MDIO bus Registration */
3038 ret
= stmmac_mdio_register(ndev
);
3040 pr_debug("%s: MDIO bus (id: %d) registration failed",
3041 __func__
, priv
->plat
->bus_id
);
3042 goto error_mdio_register
;
3048 error_mdio_register
:
3049 unregister_netdev(ndev
);
3050 error_netdev_register
:
3051 netif_napi_del(&priv
->napi
);
3053 clk_disable_unprepare(priv
->pclk
);
3055 clk_disable_unprepare(priv
->stmmac_clk
);
3061 EXPORT_SYMBOL_GPL(stmmac_dvr_probe
);
3065 * @ndev: net device pointer
3066 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3067 * changes the link status, releases the DMA descriptor rings.
3069 int stmmac_dvr_remove(struct net_device
*ndev
)
3071 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3073 pr_info("%s:\n\tremoving driver", __func__
);
3075 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
3076 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
3078 stmmac_set_mac(priv
->ioaddr
, false);
3079 netif_carrier_off(ndev
);
3080 unregister_netdev(ndev
);
3081 if (priv
->stmmac_rst
)
3082 reset_control_assert(priv
->stmmac_rst
);
3083 clk_disable_unprepare(priv
->pclk
);
3084 clk_disable_unprepare(priv
->stmmac_clk
);
3085 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
3086 priv
->pcs
!= STMMAC_PCS_RTBI
)
3087 stmmac_mdio_unregister(ndev
);
3092 EXPORT_SYMBOL_GPL(stmmac_dvr_remove
);
3095 * stmmac_suspend - suspend callback
3096 * @ndev: net device pointer
3097 * Description: this is the function to suspend the device and it is called
3098 * by the platform driver to stop the network queue, release the resources,
3099 * program the PMT register (for WoL), clean and release driver resources.
3101 int stmmac_suspend(struct net_device
*ndev
)
3103 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3104 unsigned long flags
;
3106 if (!ndev
|| !netif_running(ndev
))
3110 phy_stop(priv
->phydev
);
3112 spin_lock_irqsave(&priv
->lock
, flags
);
3114 netif_device_detach(ndev
);
3115 netif_stop_queue(ndev
);
3117 napi_disable(&priv
->napi
);
3119 /* Stop TX/RX DMA */
3120 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
3121 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
3123 /* Enable Power down mode by programming the PMT regs */
3124 if (device_may_wakeup(priv
->device
)) {
3125 priv
->hw
->mac
->pmt(priv
->hw
, priv
->wolopts
);
3128 stmmac_set_mac(priv
->ioaddr
, false);
3129 pinctrl_pm_select_sleep_state(priv
->device
);
3130 /* Disable clock in case of PWM is off */
3131 clk_disable(priv
->pclk
);
3132 clk_disable(priv
->stmmac_clk
);
3134 spin_unlock_irqrestore(&priv
->lock
, flags
);
3138 priv
->oldduplex
= -1;
3141 EXPORT_SYMBOL_GPL(stmmac_suspend
);
3144 * stmmac_resume - resume callback
3145 * @ndev: net device pointer
3146 * Description: when resume this function is invoked to setup the DMA and CORE
3147 * in a usable state.
3149 int stmmac_resume(struct net_device
*ndev
)
3151 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3152 unsigned long flags
;
3154 if (!netif_running(ndev
))
3157 spin_lock_irqsave(&priv
->lock
, flags
);
3159 /* Power Down bit, into the PM register, is cleared
3160 * automatically as soon as a magic packet or a Wake-up frame
3161 * is received. Anyway, it's better to manually clear
3162 * this bit because it can generate problems while resuming
3163 * from another devices (e.g. serial console).
3165 if (device_may_wakeup(priv
->device
)) {
3166 priv
->hw
->mac
->pmt(priv
->hw
, 0);
3169 pinctrl_pm_select_default_state(priv
->device
);
3170 /* enable the clk prevously disabled */
3171 clk_enable(priv
->stmmac_clk
);
3172 clk_enable(priv
->pclk
);
3173 /* reset the phy so that it's ready */
3175 stmmac_mdio_reset(priv
->mii
);
3178 netif_device_attach(ndev
);
3184 stmmac_clear_descriptors(priv
);
3186 stmmac_hw_setup(ndev
, false);
3187 stmmac_init_tx_coalesce(priv
);
3188 stmmac_set_rx_mode(ndev
);
3190 napi_enable(&priv
->napi
);
3192 netif_start_queue(ndev
);
3194 spin_unlock_irqrestore(&priv
->lock
, flags
);
3197 phy_start(priv
->phydev
);
3201 EXPORT_SYMBOL_GPL(stmmac_resume
);
3204 static int __init
stmmac_cmdline_opt(char *str
)
3210 while ((opt
= strsep(&str
, ",")) != NULL
) {
3211 if (!strncmp(opt
, "debug:", 6)) {
3212 if (kstrtoint(opt
+ 6, 0, &debug
))
3214 } else if (!strncmp(opt
, "phyaddr:", 8)) {
3215 if (kstrtoint(opt
+ 8, 0, &phyaddr
))
3217 } else if (!strncmp(opt
, "buf_sz:", 7)) {
3218 if (kstrtoint(opt
+ 7, 0, &buf_sz
))
3220 } else if (!strncmp(opt
, "tc:", 3)) {
3221 if (kstrtoint(opt
+ 3, 0, &tc
))
3223 } else if (!strncmp(opt
, "watchdog:", 9)) {
3224 if (kstrtoint(opt
+ 9, 0, &watchdog
))
3226 } else if (!strncmp(opt
, "flow_ctrl:", 10)) {
3227 if (kstrtoint(opt
+ 10, 0, &flow_ctrl
))
3229 } else if (!strncmp(opt
, "pause:", 6)) {
3230 if (kstrtoint(opt
+ 6, 0, &pause
))
3232 } else if (!strncmp(opt
, "eee_timer:", 10)) {
3233 if (kstrtoint(opt
+ 10, 0, &eee_timer
))
3235 } else if (!strncmp(opt
, "chain_mode:", 11)) {
3236 if (kstrtoint(opt
+ 11, 0, &chain_mode
))
3243 pr_err("%s: ERROR broken module parameter conversion", __func__
);
3247 __setup("stmmaceth=", stmmac_cmdline_opt
);
3250 static int __init
stmmac_init(void)
3252 #ifdef CONFIG_DEBUG_FS
3253 /* Create debugfs main directory if it doesn't exist yet */
3254 if (!stmmac_fs_dir
) {
3255 stmmac_fs_dir
= debugfs_create_dir(STMMAC_RESOURCE_NAME
, NULL
);
3257 if (!stmmac_fs_dir
|| IS_ERR(stmmac_fs_dir
)) {
3258 pr_err("ERROR %s, debugfs create directory failed\n",
3259 STMMAC_RESOURCE_NAME
);
3269 static void __exit
stmmac_exit(void)
3271 #ifdef CONFIG_DEBUG_FS
3272 debugfs_remove_recursive(stmmac_fs_dir
);
3276 module_init(stmmac_init
)
3277 module_exit(stmmac_exit
)
3279 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3280 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3281 MODULE_LICENSE("GPL");