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Merge branch 'x86-debug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / net / ethernet / sun / niu.c
1 /* niu.c: Neptune ethernet driver.
2 *
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/netdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/etherdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/delay.h>
18 #include <linux/bitops.h>
19 #include <linux/mii.h>
20 #include <linux/if.h>
21 #include <linux/if_ether.h>
22 #include <linux/if_vlan.h>
23 #include <linux/ip.h>
24 #include <linux/in.h>
25 #include <linux/ipv6.h>
26 #include <linux/log2.h>
27 #include <linux/jiffies.h>
28 #include <linux/crc32.h>
29 #include <linux/list.h>
30 #include <linux/slab.h>
31
32 #include <linux/io.h>
33 #include <linux/of_device.h>
34
35 #include "niu.h"
36
37 #define DRV_MODULE_NAME "niu"
38 #define DRV_MODULE_VERSION "1.1"
39 #define DRV_MODULE_RELDATE "Apr 22, 2010"
40
41 static char version[] __devinitdata =
42 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
43
44 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
45 MODULE_DESCRIPTION("NIU ethernet driver");
46 MODULE_LICENSE("GPL");
47 MODULE_VERSION(DRV_MODULE_VERSION);
48
49 #ifndef readq
50 static u64 readq(void __iomem *reg)
51 {
52 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
53 }
54
55 static void writeq(u64 val, void __iomem *reg)
56 {
57 writel(val & 0xffffffff, reg);
58 writel(val >> 32, reg + 0x4UL);
59 }
60 #endif
61
62 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
63 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
64 {}
65 };
66
67 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
68
69 #define NIU_TX_TIMEOUT (5 * HZ)
70
71 #define nr64(reg) readq(np->regs + (reg))
72 #define nw64(reg, val) writeq((val), np->regs + (reg))
73
74 #define nr64_mac(reg) readq(np->mac_regs + (reg))
75 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
76
77 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
78 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
79
80 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
81 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
82
83 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
84 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
85
86 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
87
88 static int niu_debug;
89 static int debug = -1;
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "NIU debug level");
92
93 #define niu_lock_parent(np, flags) \
94 spin_lock_irqsave(&np->parent->lock, flags)
95 #define niu_unlock_parent(np, flags) \
96 spin_unlock_irqrestore(&np->parent->lock, flags)
97
98 static int serdes_init_10g_serdes(struct niu *np);
99
100 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
101 u64 bits, int limit, int delay)
102 {
103 while (--limit >= 0) {
104 u64 val = nr64_mac(reg);
105
106 if (!(val & bits))
107 break;
108 udelay(delay);
109 }
110 if (limit < 0)
111 return -ENODEV;
112 return 0;
113 }
114
115 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
116 u64 bits, int limit, int delay,
117 const char *reg_name)
118 {
119 int err;
120
121 nw64_mac(reg, bits);
122 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
123 if (err)
124 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
125 (unsigned long long)bits, reg_name,
126 (unsigned long long)nr64_mac(reg));
127 return err;
128 }
129
130 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
131 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
132 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
133 })
134
135 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
136 u64 bits, int limit, int delay)
137 {
138 while (--limit >= 0) {
139 u64 val = nr64_ipp(reg);
140
141 if (!(val & bits))
142 break;
143 udelay(delay);
144 }
145 if (limit < 0)
146 return -ENODEV;
147 return 0;
148 }
149
150 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
151 u64 bits, int limit, int delay,
152 const char *reg_name)
153 {
154 int err;
155 u64 val;
156
157 val = nr64_ipp(reg);
158 val |= bits;
159 nw64_ipp(reg, val);
160
161 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
162 if (err)
163 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
164 (unsigned long long)bits, reg_name,
165 (unsigned long long)nr64_ipp(reg));
166 return err;
167 }
168
169 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
170 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
171 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
172 })
173
174 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
175 u64 bits, int limit, int delay)
176 {
177 while (--limit >= 0) {
178 u64 val = nr64(reg);
179
180 if (!(val & bits))
181 break;
182 udelay(delay);
183 }
184 if (limit < 0)
185 return -ENODEV;
186 return 0;
187 }
188
189 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
190 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
191 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
192 })
193
194 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
195 u64 bits, int limit, int delay,
196 const char *reg_name)
197 {
198 int err;
199
200 nw64(reg, bits);
201 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
202 if (err)
203 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
204 (unsigned long long)bits, reg_name,
205 (unsigned long long)nr64(reg));
206 return err;
207 }
208
209 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
210 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
211 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
212 })
213
214 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
215 {
216 u64 val = (u64) lp->timer;
217
218 if (on)
219 val |= LDG_IMGMT_ARM;
220
221 nw64(LDG_IMGMT(lp->ldg_num), val);
222 }
223
224 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
225 {
226 unsigned long mask_reg, bits;
227 u64 val;
228
229 if (ldn < 0 || ldn > LDN_MAX)
230 return -EINVAL;
231
232 if (ldn < 64) {
233 mask_reg = LD_IM0(ldn);
234 bits = LD_IM0_MASK;
235 } else {
236 mask_reg = LD_IM1(ldn - 64);
237 bits = LD_IM1_MASK;
238 }
239
240 val = nr64(mask_reg);
241 if (on)
242 val &= ~bits;
243 else
244 val |= bits;
245 nw64(mask_reg, val);
246
247 return 0;
248 }
249
250 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
251 {
252 struct niu_parent *parent = np->parent;
253 int i;
254
255 for (i = 0; i <= LDN_MAX; i++) {
256 int err;
257
258 if (parent->ldg_map[i] != lp->ldg_num)
259 continue;
260
261 err = niu_ldn_irq_enable(np, i, on);
262 if (err)
263 return err;
264 }
265 return 0;
266 }
267
268 static int niu_enable_interrupts(struct niu *np, int on)
269 {
270 int i;
271
272 for (i = 0; i < np->num_ldg; i++) {
273 struct niu_ldg *lp = &np->ldg[i];
274 int err;
275
276 err = niu_enable_ldn_in_ldg(np, lp, on);
277 if (err)
278 return err;
279 }
280 for (i = 0; i < np->num_ldg; i++)
281 niu_ldg_rearm(np, &np->ldg[i], on);
282
283 return 0;
284 }
285
286 static u32 phy_encode(u32 type, int port)
287 {
288 return type << (port * 2);
289 }
290
291 static u32 phy_decode(u32 val, int port)
292 {
293 return (val >> (port * 2)) & PORT_TYPE_MASK;
294 }
295
296 static int mdio_wait(struct niu *np)
297 {
298 int limit = 1000;
299 u64 val;
300
301 while (--limit > 0) {
302 val = nr64(MIF_FRAME_OUTPUT);
303 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
304 return val & MIF_FRAME_OUTPUT_DATA;
305
306 udelay(10);
307 }
308
309 return -ENODEV;
310 }
311
312 static int mdio_read(struct niu *np, int port, int dev, int reg)
313 {
314 int err;
315
316 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
317 err = mdio_wait(np);
318 if (err < 0)
319 return err;
320
321 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
322 return mdio_wait(np);
323 }
324
325 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
326 {
327 int err;
328
329 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
330 err = mdio_wait(np);
331 if (err < 0)
332 return err;
333
334 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
335 err = mdio_wait(np);
336 if (err < 0)
337 return err;
338
339 return 0;
340 }
341
342 static int mii_read(struct niu *np, int port, int reg)
343 {
344 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
345 return mdio_wait(np);
346 }
347
348 static int mii_write(struct niu *np, int port, int reg, int data)
349 {
350 int err;
351
352 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
353 err = mdio_wait(np);
354 if (err < 0)
355 return err;
356
357 return 0;
358 }
359
360 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
361 {
362 int err;
363
364 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
365 ESR2_TI_PLL_TX_CFG_L(channel),
366 val & 0xffff);
367 if (!err)
368 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
369 ESR2_TI_PLL_TX_CFG_H(channel),
370 val >> 16);
371 return err;
372 }
373
374 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
375 {
376 int err;
377
378 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
379 ESR2_TI_PLL_RX_CFG_L(channel),
380 val & 0xffff);
381 if (!err)
382 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
383 ESR2_TI_PLL_RX_CFG_H(channel),
384 val >> 16);
385 return err;
386 }
387
388 /* Mode is always 10G fiber. */
389 static int serdes_init_niu_10g_fiber(struct niu *np)
390 {
391 struct niu_link_config *lp = &np->link_config;
392 u32 tx_cfg, rx_cfg;
393 unsigned long i;
394
395 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
396 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
397 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
398 PLL_RX_CFG_EQ_LP_ADAPTIVE);
399
400 if (lp->loopback_mode == LOOPBACK_PHY) {
401 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
402
403 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
404 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
405
406 tx_cfg |= PLL_TX_CFG_ENTEST;
407 rx_cfg |= PLL_RX_CFG_ENTEST;
408 }
409
410 /* Initialize all 4 lanes of the SERDES. */
411 for (i = 0; i < 4; i++) {
412 int err = esr2_set_tx_cfg(np, i, tx_cfg);
413 if (err)
414 return err;
415 }
416
417 for (i = 0; i < 4; i++) {
418 int err = esr2_set_rx_cfg(np, i, rx_cfg);
419 if (err)
420 return err;
421 }
422
423 return 0;
424 }
425
426 static int serdes_init_niu_1g_serdes(struct niu *np)
427 {
428 struct niu_link_config *lp = &np->link_config;
429 u16 pll_cfg, pll_sts;
430 int max_retry = 100;
431 u64 uninitialized_var(sig), mask, val;
432 u32 tx_cfg, rx_cfg;
433 unsigned long i;
434 int err;
435
436 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
437 PLL_TX_CFG_RATE_HALF);
438 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
439 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
440 PLL_RX_CFG_RATE_HALF);
441
442 if (np->port == 0)
443 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
444
445 if (lp->loopback_mode == LOOPBACK_PHY) {
446 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
447
448 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
449 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
450
451 tx_cfg |= PLL_TX_CFG_ENTEST;
452 rx_cfg |= PLL_RX_CFG_ENTEST;
453 }
454
455 /* Initialize PLL for 1G */
456 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
457
458 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
459 ESR2_TI_PLL_CFG_L, pll_cfg);
460 if (err) {
461 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
462 np->port, __func__);
463 return err;
464 }
465
466 pll_sts = PLL_CFG_ENPLL;
467
468 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
469 ESR2_TI_PLL_STS_L, pll_sts);
470 if (err) {
471 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
472 np->port, __func__);
473 return err;
474 }
475
476 udelay(200);
477
478 /* Initialize all 4 lanes of the SERDES. */
479 for (i = 0; i < 4; i++) {
480 err = esr2_set_tx_cfg(np, i, tx_cfg);
481 if (err)
482 return err;
483 }
484
485 for (i = 0; i < 4; i++) {
486 err = esr2_set_rx_cfg(np, i, rx_cfg);
487 if (err)
488 return err;
489 }
490
491 switch (np->port) {
492 case 0:
493 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
494 mask = val;
495 break;
496
497 case 1:
498 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
499 mask = val;
500 break;
501
502 default:
503 return -EINVAL;
504 }
505
506 while (max_retry--) {
507 sig = nr64(ESR_INT_SIGNALS);
508 if ((sig & mask) == val)
509 break;
510
511 mdelay(500);
512 }
513
514 if ((sig & mask) != val) {
515 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
516 np->port, (int)(sig & mask), (int)val);
517 return -ENODEV;
518 }
519
520 return 0;
521 }
522
523 static int serdes_init_niu_10g_serdes(struct niu *np)
524 {
525 struct niu_link_config *lp = &np->link_config;
526 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
527 int max_retry = 100;
528 u64 uninitialized_var(sig), mask, val;
529 unsigned long i;
530 int err;
531
532 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
533 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
534 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
535 PLL_RX_CFG_EQ_LP_ADAPTIVE);
536
537 if (lp->loopback_mode == LOOPBACK_PHY) {
538 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
539
540 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
541 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
542
543 tx_cfg |= PLL_TX_CFG_ENTEST;
544 rx_cfg |= PLL_RX_CFG_ENTEST;
545 }
546
547 /* Initialize PLL for 10G */
548 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
549
550 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
551 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
552 if (err) {
553 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
554 np->port, __func__);
555 return err;
556 }
557
558 pll_sts = PLL_CFG_ENPLL;
559
560 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
561 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
562 if (err) {
563 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
564 np->port, __func__);
565 return err;
566 }
567
568 udelay(200);
569
570 /* Initialize all 4 lanes of the SERDES. */
571 for (i = 0; i < 4; i++) {
572 err = esr2_set_tx_cfg(np, i, tx_cfg);
573 if (err)
574 return err;
575 }
576
577 for (i = 0; i < 4; i++) {
578 err = esr2_set_rx_cfg(np, i, rx_cfg);
579 if (err)
580 return err;
581 }
582
583 /* check if serdes is ready */
584
585 switch (np->port) {
586 case 0:
587 mask = ESR_INT_SIGNALS_P0_BITS;
588 val = (ESR_INT_SRDY0_P0 |
589 ESR_INT_DET0_P0 |
590 ESR_INT_XSRDY_P0 |
591 ESR_INT_XDP_P0_CH3 |
592 ESR_INT_XDP_P0_CH2 |
593 ESR_INT_XDP_P0_CH1 |
594 ESR_INT_XDP_P0_CH0);
595 break;
596
597 case 1:
598 mask = ESR_INT_SIGNALS_P1_BITS;
599 val = (ESR_INT_SRDY0_P1 |
600 ESR_INT_DET0_P1 |
601 ESR_INT_XSRDY_P1 |
602 ESR_INT_XDP_P1_CH3 |
603 ESR_INT_XDP_P1_CH2 |
604 ESR_INT_XDP_P1_CH1 |
605 ESR_INT_XDP_P1_CH0);
606 break;
607
608 default:
609 return -EINVAL;
610 }
611
612 while (max_retry--) {
613 sig = nr64(ESR_INT_SIGNALS);
614 if ((sig & mask) == val)
615 break;
616
617 mdelay(500);
618 }
619
620 if ((sig & mask) != val) {
621 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
622 np->port, (int)(sig & mask), (int)val);
623
624 /* 10G failed, try initializing at 1G */
625 err = serdes_init_niu_1g_serdes(np);
626 if (!err) {
627 np->flags &= ~NIU_FLAGS_10G;
628 np->mac_xcvr = MAC_XCVR_PCS;
629 } else {
630 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
631 np->port);
632 return -ENODEV;
633 }
634 }
635 return 0;
636 }
637
638 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
639 {
640 int err;
641
642 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
643 if (err >= 0) {
644 *val = (err & 0xffff);
645 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
646 ESR_RXTX_CTRL_H(chan));
647 if (err >= 0)
648 *val |= ((err & 0xffff) << 16);
649 err = 0;
650 }
651 return err;
652 }
653
654 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
655 {
656 int err;
657
658 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
659 ESR_GLUE_CTRL0_L(chan));
660 if (err >= 0) {
661 *val = (err & 0xffff);
662 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
663 ESR_GLUE_CTRL0_H(chan));
664 if (err >= 0) {
665 *val |= ((err & 0xffff) << 16);
666 err = 0;
667 }
668 }
669 return err;
670 }
671
672 static int esr_read_reset(struct niu *np, u32 *val)
673 {
674 int err;
675
676 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
677 ESR_RXTX_RESET_CTRL_L);
678 if (err >= 0) {
679 *val = (err & 0xffff);
680 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
681 ESR_RXTX_RESET_CTRL_H);
682 if (err >= 0) {
683 *val |= ((err & 0xffff) << 16);
684 err = 0;
685 }
686 }
687 return err;
688 }
689
690 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
691 {
692 int err;
693
694 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
695 ESR_RXTX_CTRL_L(chan), val & 0xffff);
696 if (!err)
697 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
698 ESR_RXTX_CTRL_H(chan), (val >> 16));
699 return err;
700 }
701
702 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
703 {
704 int err;
705
706 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
707 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
708 if (!err)
709 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
710 ESR_GLUE_CTRL0_H(chan), (val >> 16));
711 return err;
712 }
713
714 static int esr_reset(struct niu *np)
715 {
716 u32 uninitialized_var(reset);
717 int err;
718
719 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
720 ESR_RXTX_RESET_CTRL_L, 0x0000);
721 if (err)
722 return err;
723 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
724 ESR_RXTX_RESET_CTRL_H, 0xffff);
725 if (err)
726 return err;
727 udelay(200);
728
729 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
730 ESR_RXTX_RESET_CTRL_L, 0xffff);
731 if (err)
732 return err;
733 udelay(200);
734
735 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
736 ESR_RXTX_RESET_CTRL_H, 0x0000);
737 if (err)
738 return err;
739 udelay(200);
740
741 err = esr_read_reset(np, &reset);
742 if (err)
743 return err;
744 if (reset != 0) {
745 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
746 np->port, reset);
747 return -ENODEV;
748 }
749
750 return 0;
751 }
752
753 static int serdes_init_10g(struct niu *np)
754 {
755 struct niu_link_config *lp = &np->link_config;
756 unsigned long ctrl_reg, test_cfg_reg, i;
757 u64 ctrl_val, test_cfg_val, sig, mask, val;
758 int err;
759
760 switch (np->port) {
761 case 0:
762 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
763 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
764 break;
765 case 1:
766 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
767 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
768 break;
769
770 default:
771 return -EINVAL;
772 }
773 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
774 ENET_SERDES_CTRL_SDET_1 |
775 ENET_SERDES_CTRL_SDET_2 |
776 ENET_SERDES_CTRL_SDET_3 |
777 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
778 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
779 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
780 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
781 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
783 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
784 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
785 test_cfg_val = 0;
786
787 if (lp->loopback_mode == LOOPBACK_PHY) {
788 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
789 ENET_SERDES_TEST_MD_0_SHIFT) |
790 (ENET_TEST_MD_PAD_LOOPBACK <<
791 ENET_SERDES_TEST_MD_1_SHIFT) |
792 (ENET_TEST_MD_PAD_LOOPBACK <<
793 ENET_SERDES_TEST_MD_2_SHIFT) |
794 (ENET_TEST_MD_PAD_LOOPBACK <<
795 ENET_SERDES_TEST_MD_3_SHIFT));
796 }
797
798 nw64(ctrl_reg, ctrl_val);
799 nw64(test_cfg_reg, test_cfg_val);
800
801 /* Initialize all 4 lanes of the SERDES. */
802 for (i = 0; i < 4; i++) {
803 u32 rxtx_ctrl, glue0;
804
805 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
806 if (err)
807 return err;
808 err = esr_read_glue0(np, i, &glue0);
809 if (err)
810 return err;
811
812 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
813 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
814 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
815
816 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
817 ESR_GLUE_CTRL0_THCNT |
818 ESR_GLUE_CTRL0_BLTIME);
819 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
820 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
821 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
822 (BLTIME_300_CYCLES <<
823 ESR_GLUE_CTRL0_BLTIME_SHIFT));
824
825 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
826 if (err)
827 return err;
828 err = esr_write_glue0(np, i, glue0);
829 if (err)
830 return err;
831 }
832
833 err = esr_reset(np);
834 if (err)
835 return err;
836
837 sig = nr64(ESR_INT_SIGNALS);
838 switch (np->port) {
839 case 0:
840 mask = ESR_INT_SIGNALS_P0_BITS;
841 val = (ESR_INT_SRDY0_P0 |
842 ESR_INT_DET0_P0 |
843 ESR_INT_XSRDY_P0 |
844 ESR_INT_XDP_P0_CH3 |
845 ESR_INT_XDP_P0_CH2 |
846 ESR_INT_XDP_P0_CH1 |
847 ESR_INT_XDP_P0_CH0);
848 break;
849
850 case 1:
851 mask = ESR_INT_SIGNALS_P1_BITS;
852 val = (ESR_INT_SRDY0_P1 |
853 ESR_INT_DET0_P1 |
854 ESR_INT_XSRDY_P1 |
855 ESR_INT_XDP_P1_CH3 |
856 ESR_INT_XDP_P1_CH2 |
857 ESR_INT_XDP_P1_CH1 |
858 ESR_INT_XDP_P1_CH0);
859 break;
860
861 default:
862 return -EINVAL;
863 }
864
865 if ((sig & mask) != val) {
866 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
867 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
868 return 0;
869 }
870 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
871 np->port, (int)(sig & mask), (int)val);
872 return -ENODEV;
873 }
874 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
875 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
876 return 0;
877 }
878
879 static int serdes_init_1g(struct niu *np)
880 {
881 u64 val;
882
883 val = nr64(ENET_SERDES_1_PLL_CFG);
884 val &= ~ENET_SERDES_PLL_FBDIV2;
885 switch (np->port) {
886 case 0:
887 val |= ENET_SERDES_PLL_HRATE0;
888 break;
889 case 1:
890 val |= ENET_SERDES_PLL_HRATE1;
891 break;
892 case 2:
893 val |= ENET_SERDES_PLL_HRATE2;
894 break;
895 case 3:
896 val |= ENET_SERDES_PLL_HRATE3;
897 break;
898 default:
899 return -EINVAL;
900 }
901 nw64(ENET_SERDES_1_PLL_CFG, val);
902
903 return 0;
904 }
905
906 static int serdes_init_1g_serdes(struct niu *np)
907 {
908 struct niu_link_config *lp = &np->link_config;
909 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
910 u64 ctrl_val, test_cfg_val, sig, mask, val;
911 int err;
912 u64 reset_val, val_rd;
913
914 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
915 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
916 ENET_SERDES_PLL_FBDIV0;
917 switch (np->port) {
918 case 0:
919 reset_val = ENET_SERDES_RESET_0;
920 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
921 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
922 pll_cfg = ENET_SERDES_0_PLL_CFG;
923 break;
924 case 1:
925 reset_val = ENET_SERDES_RESET_1;
926 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
927 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
928 pll_cfg = ENET_SERDES_1_PLL_CFG;
929 break;
930
931 default:
932 return -EINVAL;
933 }
934 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
935 ENET_SERDES_CTRL_SDET_1 |
936 ENET_SERDES_CTRL_SDET_2 |
937 ENET_SERDES_CTRL_SDET_3 |
938 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
939 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
940 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
941 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
942 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
944 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
945 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
946 test_cfg_val = 0;
947
948 if (lp->loopback_mode == LOOPBACK_PHY) {
949 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
950 ENET_SERDES_TEST_MD_0_SHIFT) |
951 (ENET_TEST_MD_PAD_LOOPBACK <<
952 ENET_SERDES_TEST_MD_1_SHIFT) |
953 (ENET_TEST_MD_PAD_LOOPBACK <<
954 ENET_SERDES_TEST_MD_2_SHIFT) |
955 (ENET_TEST_MD_PAD_LOOPBACK <<
956 ENET_SERDES_TEST_MD_3_SHIFT));
957 }
958
959 nw64(ENET_SERDES_RESET, reset_val);
960 mdelay(20);
961 val_rd = nr64(ENET_SERDES_RESET);
962 val_rd &= ~reset_val;
963 nw64(pll_cfg, val);
964 nw64(ctrl_reg, ctrl_val);
965 nw64(test_cfg_reg, test_cfg_val);
966 nw64(ENET_SERDES_RESET, val_rd);
967 mdelay(2000);
968
969 /* Initialize all 4 lanes of the SERDES. */
970 for (i = 0; i < 4; i++) {
971 u32 rxtx_ctrl, glue0;
972
973 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
974 if (err)
975 return err;
976 err = esr_read_glue0(np, i, &glue0);
977 if (err)
978 return err;
979
980 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
981 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
982 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
983
984 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
985 ESR_GLUE_CTRL0_THCNT |
986 ESR_GLUE_CTRL0_BLTIME);
987 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
988 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
989 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
990 (BLTIME_300_CYCLES <<
991 ESR_GLUE_CTRL0_BLTIME_SHIFT));
992
993 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
994 if (err)
995 return err;
996 err = esr_write_glue0(np, i, glue0);
997 if (err)
998 return err;
999 }
1000
1001
1002 sig = nr64(ESR_INT_SIGNALS);
1003 switch (np->port) {
1004 case 0:
1005 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1006 mask = val;
1007 break;
1008
1009 case 1:
1010 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1011 mask = val;
1012 break;
1013
1014 default:
1015 return -EINVAL;
1016 }
1017
1018 if ((sig & mask) != val) {
1019 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1020 np->port, (int)(sig & mask), (int)val);
1021 return -ENODEV;
1022 }
1023
1024 return 0;
1025 }
1026
1027 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1028 {
1029 struct niu_link_config *lp = &np->link_config;
1030 int link_up;
1031 u64 val;
1032 u16 current_speed;
1033 unsigned long flags;
1034 u8 current_duplex;
1035
1036 link_up = 0;
1037 current_speed = SPEED_INVALID;
1038 current_duplex = DUPLEX_INVALID;
1039
1040 spin_lock_irqsave(&np->lock, flags);
1041
1042 val = nr64_pcs(PCS_MII_STAT);
1043
1044 if (val & PCS_MII_STAT_LINK_STATUS) {
1045 link_up = 1;
1046 current_speed = SPEED_1000;
1047 current_duplex = DUPLEX_FULL;
1048 }
1049
1050 lp->active_speed = current_speed;
1051 lp->active_duplex = current_duplex;
1052 spin_unlock_irqrestore(&np->lock, flags);
1053
1054 *link_up_p = link_up;
1055 return 0;
1056 }
1057
1058 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1059 {
1060 unsigned long flags;
1061 struct niu_link_config *lp = &np->link_config;
1062 int link_up = 0;
1063 int link_ok = 1;
1064 u64 val, val2;
1065 u16 current_speed;
1066 u8 current_duplex;
1067
1068 if (!(np->flags & NIU_FLAGS_10G))
1069 return link_status_1g_serdes(np, link_up_p);
1070
1071 current_speed = SPEED_INVALID;
1072 current_duplex = DUPLEX_INVALID;
1073 spin_lock_irqsave(&np->lock, flags);
1074
1075 val = nr64_xpcs(XPCS_STATUS(0));
1076 val2 = nr64_mac(XMAC_INTER2);
1077 if (val2 & 0x01000000)
1078 link_ok = 0;
1079
1080 if ((val & 0x1000ULL) && link_ok) {
1081 link_up = 1;
1082 current_speed = SPEED_10000;
1083 current_duplex = DUPLEX_FULL;
1084 }
1085 lp->active_speed = current_speed;
1086 lp->active_duplex = current_duplex;
1087 spin_unlock_irqrestore(&np->lock, flags);
1088 *link_up_p = link_up;
1089 return 0;
1090 }
1091
1092 static int link_status_mii(struct niu *np, int *link_up_p)
1093 {
1094 struct niu_link_config *lp = &np->link_config;
1095 int err;
1096 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1097 int supported, advertising, active_speed, active_duplex;
1098
1099 err = mii_read(np, np->phy_addr, MII_BMCR);
1100 if (unlikely(err < 0))
1101 return err;
1102 bmcr = err;
1103
1104 err = mii_read(np, np->phy_addr, MII_BMSR);
1105 if (unlikely(err < 0))
1106 return err;
1107 bmsr = err;
1108
1109 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1110 if (unlikely(err < 0))
1111 return err;
1112 advert = err;
1113
1114 err = mii_read(np, np->phy_addr, MII_LPA);
1115 if (unlikely(err < 0))
1116 return err;
1117 lpa = err;
1118
1119 if (likely(bmsr & BMSR_ESTATEN)) {
1120 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1121 if (unlikely(err < 0))
1122 return err;
1123 estatus = err;
1124
1125 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1126 if (unlikely(err < 0))
1127 return err;
1128 ctrl1000 = err;
1129
1130 err = mii_read(np, np->phy_addr, MII_STAT1000);
1131 if (unlikely(err < 0))
1132 return err;
1133 stat1000 = err;
1134 } else
1135 estatus = ctrl1000 = stat1000 = 0;
1136
1137 supported = 0;
1138 if (bmsr & BMSR_ANEGCAPABLE)
1139 supported |= SUPPORTED_Autoneg;
1140 if (bmsr & BMSR_10HALF)
1141 supported |= SUPPORTED_10baseT_Half;
1142 if (bmsr & BMSR_10FULL)
1143 supported |= SUPPORTED_10baseT_Full;
1144 if (bmsr & BMSR_100HALF)
1145 supported |= SUPPORTED_100baseT_Half;
1146 if (bmsr & BMSR_100FULL)
1147 supported |= SUPPORTED_100baseT_Full;
1148 if (estatus & ESTATUS_1000_THALF)
1149 supported |= SUPPORTED_1000baseT_Half;
1150 if (estatus & ESTATUS_1000_TFULL)
1151 supported |= SUPPORTED_1000baseT_Full;
1152 lp->supported = supported;
1153
1154 advertising = mii_adv_to_ethtool_adv_t(advert);
1155 advertising |= mii_ctrl1000_to_ethtool_adv_t(ctrl1000);
1156
1157 if (bmcr & BMCR_ANENABLE) {
1158 int neg, neg1000;
1159
1160 lp->active_autoneg = 1;
1161 advertising |= ADVERTISED_Autoneg;
1162
1163 neg = advert & lpa;
1164 neg1000 = (ctrl1000 << 2) & stat1000;
1165
1166 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1167 active_speed = SPEED_1000;
1168 else if (neg & LPA_100)
1169 active_speed = SPEED_100;
1170 else if (neg & (LPA_10HALF | LPA_10FULL))
1171 active_speed = SPEED_10;
1172 else
1173 active_speed = SPEED_INVALID;
1174
1175 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1176 active_duplex = DUPLEX_FULL;
1177 else if (active_speed != SPEED_INVALID)
1178 active_duplex = DUPLEX_HALF;
1179 else
1180 active_duplex = DUPLEX_INVALID;
1181 } else {
1182 lp->active_autoneg = 0;
1183
1184 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1185 active_speed = SPEED_1000;
1186 else if (bmcr & BMCR_SPEED100)
1187 active_speed = SPEED_100;
1188 else
1189 active_speed = SPEED_10;
1190
1191 if (bmcr & BMCR_FULLDPLX)
1192 active_duplex = DUPLEX_FULL;
1193 else
1194 active_duplex = DUPLEX_HALF;
1195 }
1196
1197 lp->active_advertising = advertising;
1198 lp->active_speed = active_speed;
1199 lp->active_duplex = active_duplex;
1200 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1201
1202 return 0;
1203 }
1204
1205 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1206 {
1207 struct niu_link_config *lp = &np->link_config;
1208 u16 current_speed, bmsr;
1209 unsigned long flags;
1210 u8 current_duplex;
1211 int err, link_up;
1212
1213 link_up = 0;
1214 current_speed = SPEED_INVALID;
1215 current_duplex = DUPLEX_INVALID;
1216
1217 spin_lock_irqsave(&np->lock, flags);
1218
1219 err = -EINVAL;
1220
1221 err = mii_read(np, np->phy_addr, MII_BMSR);
1222 if (err < 0)
1223 goto out;
1224
1225 bmsr = err;
1226 if (bmsr & BMSR_LSTATUS) {
1227 u16 adv, lpa;
1228
1229 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1230 if (err < 0)
1231 goto out;
1232 adv = err;
1233
1234 err = mii_read(np, np->phy_addr, MII_LPA);
1235 if (err < 0)
1236 goto out;
1237 lpa = err;
1238
1239 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1240 if (err < 0)
1241 goto out;
1242 link_up = 1;
1243 current_speed = SPEED_1000;
1244 current_duplex = DUPLEX_FULL;
1245
1246 }
1247 lp->active_speed = current_speed;
1248 lp->active_duplex = current_duplex;
1249 err = 0;
1250
1251 out:
1252 spin_unlock_irqrestore(&np->lock, flags);
1253
1254 *link_up_p = link_up;
1255 return err;
1256 }
1257
1258 static int link_status_1g(struct niu *np, int *link_up_p)
1259 {
1260 struct niu_link_config *lp = &np->link_config;
1261 unsigned long flags;
1262 int err;
1263
1264 spin_lock_irqsave(&np->lock, flags);
1265
1266 err = link_status_mii(np, link_up_p);
1267 lp->supported |= SUPPORTED_TP;
1268 lp->active_advertising |= ADVERTISED_TP;
1269
1270 spin_unlock_irqrestore(&np->lock, flags);
1271 return err;
1272 }
1273
1274 static int bcm8704_reset(struct niu *np)
1275 {
1276 int err, limit;
1277
1278 err = mdio_read(np, np->phy_addr,
1279 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1280 if (err < 0 || err == 0xffff)
1281 return err;
1282 err |= BMCR_RESET;
1283 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1284 MII_BMCR, err);
1285 if (err)
1286 return err;
1287
1288 limit = 1000;
1289 while (--limit >= 0) {
1290 err = mdio_read(np, np->phy_addr,
1291 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1292 if (err < 0)
1293 return err;
1294 if (!(err & BMCR_RESET))
1295 break;
1296 }
1297 if (limit < 0) {
1298 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1299 np->port, (err & 0xffff));
1300 return -ENODEV;
1301 }
1302 return 0;
1303 }
1304
1305 /* When written, certain PHY registers need to be read back twice
1306 * in order for the bits to settle properly.
1307 */
1308 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1309 {
1310 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1311 if (err < 0)
1312 return err;
1313 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1314 if (err < 0)
1315 return err;
1316 return 0;
1317 }
1318
1319 static int bcm8706_init_user_dev3(struct niu *np)
1320 {
1321 int err;
1322
1323
1324 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1325 BCM8704_USER_OPT_DIGITAL_CTRL);
1326 if (err < 0)
1327 return err;
1328 err &= ~USER_ODIG_CTRL_GPIOS;
1329 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1330 err |= USER_ODIG_CTRL_RESV2;
1331 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1332 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1333 if (err)
1334 return err;
1335
1336 mdelay(1000);
1337
1338 return 0;
1339 }
1340
1341 static int bcm8704_init_user_dev3(struct niu *np)
1342 {
1343 int err;
1344
1345 err = mdio_write(np, np->phy_addr,
1346 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1347 (USER_CONTROL_OPTXRST_LVL |
1348 USER_CONTROL_OPBIASFLT_LVL |
1349 USER_CONTROL_OBTMPFLT_LVL |
1350 USER_CONTROL_OPPRFLT_LVL |
1351 USER_CONTROL_OPTXFLT_LVL |
1352 USER_CONTROL_OPRXLOS_LVL |
1353 USER_CONTROL_OPRXFLT_LVL |
1354 USER_CONTROL_OPTXON_LVL |
1355 (0x3f << USER_CONTROL_RES1_SHIFT)));
1356 if (err)
1357 return err;
1358
1359 err = mdio_write(np, np->phy_addr,
1360 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1361 (USER_PMD_TX_CTL_XFP_CLKEN |
1362 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1363 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1364 USER_PMD_TX_CTL_TSCK_LPWREN));
1365 if (err)
1366 return err;
1367
1368 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1369 if (err)
1370 return err;
1371 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1372 if (err)
1373 return err;
1374
1375 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1376 BCM8704_USER_OPT_DIGITAL_CTRL);
1377 if (err < 0)
1378 return err;
1379 err &= ~USER_ODIG_CTRL_GPIOS;
1380 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1381 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1382 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1383 if (err)
1384 return err;
1385
1386 mdelay(1000);
1387
1388 return 0;
1389 }
1390
1391 static int mrvl88x2011_act_led(struct niu *np, int val)
1392 {
1393 int err;
1394
1395 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1396 MRVL88X2011_LED_8_TO_11_CTL);
1397 if (err < 0)
1398 return err;
1399
1400 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1401 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1402
1403 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1404 MRVL88X2011_LED_8_TO_11_CTL, err);
1405 }
1406
1407 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1408 {
1409 int err;
1410
1411 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1412 MRVL88X2011_LED_BLINK_CTL);
1413 if (err >= 0) {
1414 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1415 err |= (rate << 4);
1416
1417 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1418 MRVL88X2011_LED_BLINK_CTL, err);
1419 }
1420
1421 return err;
1422 }
1423
1424 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1425 {
1426 int err;
1427
1428 /* Set LED functions */
1429 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1430 if (err)
1431 return err;
1432
1433 /* led activity */
1434 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1435 if (err)
1436 return err;
1437
1438 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1439 MRVL88X2011_GENERAL_CTL);
1440 if (err < 0)
1441 return err;
1442
1443 err |= MRVL88X2011_ENA_XFPREFCLK;
1444
1445 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1446 MRVL88X2011_GENERAL_CTL, err);
1447 if (err < 0)
1448 return err;
1449
1450 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1451 MRVL88X2011_PMA_PMD_CTL_1);
1452 if (err < 0)
1453 return err;
1454
1455 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1456 err |= MRVL88X2011_LOOPBACK;
1457 else
1458 err &= ~MRVL88X2011_LOOPBACK;
1459
1460 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1461 MRVL88X2011_PMA_PMD_CTL_1, err);
1462 if (err < 0)
1463 return err;
1464
1465 /* Enable PMD */
1466 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1467 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1468 }
1469
1470
1471 static int xcvr_diag_bcm870x(struct niu *np)
1472 {
1473 u16 analog_stat0, tx_alarm_status;
1474 int err = 0;
1475
1476 #if 1
1477 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1478 MII_STAT1000);
1479 if (err < 0)
1480 return err;
1481 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1482
1483 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1484 if (err < 0)
1485 return err;
1486 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1487
1488 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1489 MII_NWAYTEST);
1490 if (err < 0)
1491 return err;
1492 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1493 #endif
1494
1495 /* XXX dig this out it might not be so useful XXX */
1496 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1497 BCM8704_USER_ANALOG_STATUS0);
1498 if (err < 0)
1499 return err;
1500 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1501 BCM8704_USER_ANALOG_STATUS0);
1502 if (err < 0)
1503 return err;
1504 analog_stat0 = err;
1505
1506 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1507 BCM8704_USER_TX_ALARM_STATUS);
1508 if (err < 0)
1509 return err;
1510 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1511 BCM8704_USER_TX_ALARM_STATUS);
1512 if (err < 0)
1513 return err;
1514 tx_alarm_status = err;
1515
1516 if (analog_stat0 != 0x03fc) {
1517 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1518 pr_info("Port %u cable not connected or bad cable\n",
1519 np->port);
1520 } else if (analog_stat0 == 0x639c) {
1521 pr_info("Port %u optical module is bad or missing\n",
1522 np->port);
1523 }
1524 }
1525
1526 return 0;
1527 }
1528
1529 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1530 {
1531 struct niu_link_config *lp = &np->link_config;
1532 int err;
1533
1534 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1535 MII_BMCR);
1536 if (err < 0)
1537 return err;
1538
1539 err &= ~BMCR_LOOPBACK;
1540
1541 if (lp->loopback_mode == LOOPBACK_MAC)
1542 err |= BMCR_LOOPBACK;
1543
1544 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1545 MII_BMCR, err);
1546 if (err)
1547 return err;
1548
1549 return 0;
1550 }
1551
1552 static int xcvr_init_10g_bcm8706(struct niu *np)
1553 {
1554 int err = 0;
1555 u64 val;
1556
1557 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1558 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1559 return err;
1560
1561 val = nr64_mac(XMAC_CONFIG);
1562 val &= ~XMAC_CONFIG_LED_POLARITY;
1563 val |= XMAC_CONFIG_FORCE_LED_ON;
1564 nw64_mac(XMAC_CONFIG, val);
1565
1566 val = nr64(MIF_CONFIG);
1567 val |= MIF_CONFIG_INDIRECT_MODE;
1568 nw64(MIF_CONFIG, val);
1569
1570 err = bcm8704_reset(np);
1571 if (err)
1572 return err;
1573
1574 err = xcvr_10g_set_lb_bcm870x(np);
1575 if (err)
1576 return err;
1577
1578 err = bcm8706_init_user_dev3(np);
1579 if (err)
1580 return err;
1581
1582 err = xcvr_diag_bcm870x(np);
1583 if (err)
1584 return err;
1585
1586 return 0;
1587 }
1588
1589 static int xcvr_init_10g_bcm8704(struct niu *np)
1590 {
1591 int err;
1592
1593 err = bcm8704_reset(np);
1594 if (err)
1595 return err;
1596
1597 err = bcm8704_init_user_dev3(np);
1598 if (err)
1599 return err;
1600
1601 err = xcvr_10g_set_lb_bcm870x(np);
1602 if (err)
1603 return err;
1604
1605 err = xcvr_diag_bcm870x(np);
1606 if (err)
1607 return err;
1608
1609 return 0;
1610 }
1611
1612 static int xcvr_init_10g(struct niu *np)
1613 {
1614 int phy_id, err;
1615 u64 val;
1616
1617 val = nr64_mac(XMAC_CONFIG);
1618 val &= ~XMAC_CONFIG_LED_POLARITY;
1619 val |= XMAC_CONFIG_FORCE_LED_ON;
1620 nw64_mac(XMAC_CONFIG, val);
1621
1622 /* XXX shared resource, lock parent XXX */
1623 val = nr64(MIF_CONFIG);
1624 val |= MIF_CONFIG_INDIRECT_MODE;
1625 nw64(MIF_CONFIG, val);
1626
1627 phy_id = phy_decode(np->parent->port_phy, np->port);
1628 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1629
1630 /* handle different phy types */
1631 switch (phy_id & NIU_PHY_ID_MASK) {
1632 case NIU_PHY_ID_MRVL88X2011:
1633 err = xcvr_init_10g_mrvl88x2011(np);
1634 break;
1635
1636 default: /* bcom 8704 */
1637 err = xcvr_init_10g_bcm8704(np);
1638 break;
1639 }
1640
1641 return err;
1642 }
1643
1644 static int mii_reset(struct niu *np)
1645 {
1646 int limit, err;
1647
1648 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1649 if (err)
1650 return err;
1651
1652 limit = 1000;
1653 while (--limit >= 0) {
1654 udelay(500);
1655 err = mii_read(np, np->phy_addr, MII_BMCR);
1656 if (err < 0)
1657 return err;
1658 if (!(err & BMCR_RESET))
1659 break;
1660 }
1661 if (limit < 0) {
1662 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1663 np->port, err);
1664 return -ENODEV;
1665 }
1666
1667 return 0;
1668 }
1669
1670 static int xcvr_init_1g_rgmii(struct niu *np)
1671 {
1672 int err;
1673 u64 val;
1674 u16 bmcr, bmsr, estat;
1675
1676 val = nr64(MIF_CONFIG);
1677 val &= ~MIF_CONFIG_INDIRECT_MODE;
1678 nw64(MIF_CONFIG, val);
1679
1680 err = mii_reset(np);
1681 if (err)
1682 return err;
1683
1684 err = mii_read(np, np->phy_addr, MII_BMSR);
1685 if (err < 0)
1686 return err;
1687 bmsr = err;
1688
1689 estat = 0;
1690 if (bmsr & BMSR_ESTATEN) {
1691 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1692 if (err < 0)
1693 return err;
1694 estat = err;
1695 }
1696
1697 bmcr = 0;
1698 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1699 if (err)
1700 return err;
1701
1702 if (bmsr & BMSR_ESTATEN) {
1703 u16 ctrl1000 = 0;
1704
1705 if (estat & ESTATUS_1000_TFULL)
1706 ctrl1000 |= ADVERTISE_1000FULL;
1707 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1708 if (err)
1709 return err;
1710 }
1711
1712 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1713
1714 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1715 if (err)
1716 return err;
1717
1718 err = mii_read(np, np->phy_addr, MII_BMCR);
1719 if (err < 0)
1720 return err;
1721 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1722
1723 err = mii_read(np, np->phy_addr, MII_BMSR);
1724 if (err < 0)
1725 return err;
1726
1727 return 0;
1728 }
1729
1730 static int mii_init_common(struct niu *np)
1731 {
1732 struct niu_link_config *lp = &np->link_config;
1733 u16 bmcr, bmsr, adv, estat;
1734 int err;
1735
1736 err = mii_reset(np);
1737 if (err)
1738 return err;
1739
1740 err = mii_read(np, np->phy_addr, MII_BMSR);
1741 if (err < 0)
1742 return err;
1743 bmsr = err;
1744
1745 estat = 0;
1746 if (bmsr & BMSR_ESTATEN) {
1747 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1748 if (err < 0)
1749 return err;
1750 estat = err;
1751 }
1752
1753 bmcr = 0;
1754 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1755 if (err)
1756 return err;
1757
1758 if (lp->loopback_mode == LOOPBACK_MAC) {
1759 bmcr |= BMCR_LOOPBACK;
1760 if (lp->active_speed == SPEED_1000)
1761 bmcr |= BMCR_SPEED1000;
1762 if (lp->active_duplex == DUPLEX_FULL)
1763 bmcr |= BMCR_FULLDPLX;
1764 }
1765
1766 if (lp->loopback_mode == LOOPBACK_PHY) {
1767 u16 aux;
1768
1769 aux = (BCM5464R_AUX_CTL_EXT_LB |
1770 BCM5464R_AUX_CTL_WRITE_1);
1771 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1772 if (err)
1773 return err;
1774 }
1775
1776 if (lp->autoneg) {
1777 u16 ctrl1000;
1778
1779 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1780 if ((bmsr & BMSR_10HALF) &&
1781 (lp->advertising & ADVERTISED_10baseT_Half))
1782 adv |= ADVERTISE_10HALF;
1783 if ((bmsr & BMSR_10FULL) &&
1784 (lp->advertising & ADVERTISED_10baseT_Full))
1785 adv |= ADVERTISE_10FULL;
1786 if ((bmsr & BMSR_100HALF) &&
1787 (lp->advertising & ADVERTISED_100baseT_Half))
1788 adv |= ADVERTISE_100HALF;
1789 if ((bmsr & BMSR_100FULL) &&
1790 (lp->advertising & ADVERTISED_100baseT_Full))
1791 adv |= ADVERTISE_100FULL;
1792 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1793 if (err)
1794 return err;
1795
1796 if (likely(bmsr & BMSR_ESTATEN)) {
1797 ctrl1000 = 0;
1798 if ((estat & ESTATUS_1000_THALF) &&
1799 (lp->advertising & ADVERTISED_1000baseT_Half))
1800 ctrl1000 |= ADVERTISE_1000HALF;
1801 if ((estat & ESTATUS_1000_TFULL) &&
1802 (lp->advertising & ADVERTISED_1000baseT_Full))
1803 ctrl1000 |= ADVERTISE_1000FULL;
1804 err = mii_write(np, np->phy_addr,
1805 MII_CTRL1000, ctrl1000);
1806 if (err)
1807 return err;
1808 }
1809
1810 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1811 } else {
1812 /* !lp->autoneg */
1813 int fulldpx;
1814
1815 if (lp->duplex == DUPLEX_FULL) {
1816 bmcr |= BMCR_FULLDPLX;
1817 fulldpx = 1;
1818 } else if (lp->duplex == DUPLEX_HALF)
1819 fulldpx = 0;
1820 else
1821 return -EINVAL;
1822
1823 if (lp->speed == SPEED_1000) {
1824 /* if X-full requested while not supported, or
1825 X-half requested while not supported... */
1826 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1827 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1828 return -EINVAL;
1829 bmcr |= BMCR_SPEED1000;
1830 } else if (lp->speed == SPEED_100) {
1831 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1832 (!fulldpx && !(bmsr & BMSR_100HALF)))
1833 return -EINVAL;
1834 bmcr |= BMCR_SPEED100;
1835 } else if (lp->speed == SPEED_10) {
1836 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1837 (!fulldpx && !(bmsr & BMSR_10HALF)))
1838 return -EINVAL;
1839 } else
1840 return -EINVAL;
1841 }
1842
1843 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1844 if (err)
1845 return err;
1846
1847 #if 0
1848 err = mii_read(np, np->phy_addr, MII_BMCR);
1849 if (err < 0)
1850 return err;
1851 bmcr = err;
1852
1853 err = mii_read(np, np->phy_addr, MII_BMSR);
1854 if (err < 0)
1855 return err;
1856 bmsr = err;
1857
1858 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1859 np->port, bmcr, bmsr);
1860 #endif
1861
1862 return 0;
1863 }
1864
1865 static int xcvr_init_1g(struct niu *np)
1866 {
1867 u64 val;
1868
1869 /* XXX shared resource, lock parent XXX */
1870 val = nr64(MIF_CONFIG);
1871 val &= ~MIF_CONFIG_INDIRECT_MODE;
1872 nw64(MIF_CONFIG, val);
1873
1874 return mii_init_common(np);
1875 }
1876
1877 static int niu_xcvr_init(struct niu *np)
1878 {
1879 const struct niu_phy_ops *ops = np->phy_ops;
1880 int err;
1881
1882 err = 0;
1883 if (ops->xcvr_init)
1884 err = ops->xcvr_init(np);
1885
1886 return err;
1887 }
1888
1889 static int niu_serdes_init(struct niu *np)
1890 {
1891 const struct niu_phy_ops *ops = np->phy_ops;
1892 int err;
1893
1894 err = 0;
1895 if (ops->serdes_init)
1896 err = ops->serdes_init(np);
1897
1898 return err;
1899 }
1900
1901 static void niu_init_xif(struct niu *);
1902 static void niu_handle_led(struct niu *, int status);
1903
1904 static int niu_link_status_common(struct niu *np, int link_up)
1905 {
1906 struct niu_link_config *lp = &np->link_config;
1907 struct net_device *dev = np->dev;
1908 unsigned long flags;
1909
1910 if (!netif_carrier_ok(dev) && link_up) {
1911 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1912 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1913 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1914 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1915 "10Mbit/sec",
1916 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
1917
1918 spin_lock_irqsave(&np->lock, flags);
1919 niu_init_xif(np);
1920 niu_handle_led(np, 1);
1921 spin_unlock_irqrestore(&np->lock, flags);
1922
1923 netif_carrier_on(dev);
1924 } else if (netif_carrier_ok(dev) && !link_up) {
1925 netif_warn(np, link, dev, "Link is down\n");
1926 spin_lock_irqsave(&np->lock, flags);
1927 niu_handle_led(np, 0);
1928 spin_unlock_irqrestore(&np->lock, flags);
1929 netif_carrier_off(dev);
1930 }
1931
1932 return 0;
1933 }
1934
1935 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1936 {
1937 int err, link_up, pma_status, pcs_status;
1938
1939 link_up = 0;
1940
1941 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1942 MRVL88X2011_10G_PMD_STATUS_2);
1943 if (err < 0)
1944 goto out;
1945
1946 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1947 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1948 MRVL88X2011_PMA_PMD_STATUS_1);
1949 if (err < 0)
1950 goto out;
1951
1952 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1953
1954 /* Check PMC Register : 3.0001.2 == 1: read twice */
1955 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1956 MRVL88X2011_PMA_PMD_STATUS_1);
1957 if (err < 0)
1958 goto out;
1959
1960 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1961 MRVL88X2011_PMA_PMD_STATUS_1);
1962 if (err < 0)
1963 goto out;
1964
1965 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1966
1967 /* Check XGXS Register : 4.0018.[0-3,12] */
1968 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1969 MRVL88X2011_10G_XGXS_LANE_STAT);
1970 if (err < 0)
1971 goto out;
1972
1973 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1974 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1975 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1976 0x800))
1977 link_up = (pma_status && pcs_status) ? 1 : 0;
1978
1979 np->link_config.active_speed = SPEED_10000;
1980 np->link_config.active_duplex = DUPLEX_FULL;
1981 err = 0;
1982 out:
1983 mrvl88x2011_act_led(np, (link_up ?
1984 MRVL88X2011_LED_CTL_PCS_ACT :
1985 MRVL88X2011_LED_CTL_OFF));
1986
1987 *link_up_p = link_up;
1988 return err;
1989 }
1990
1991 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
1992 {
1993 int err, link_up;
1994 link_up = 0;
1995
1996 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1997 BCM8704_PMD_RCV_SIGDET);
1998 if (err < 0 || err == 0xffff)
1999 goto out;
2000 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2001 err = 0;
2002 goto out;
2003 }
2004
2005 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2006 BCM8704_PCS_10G_R_STATUS);
2007 if (err < 0)
2008 goto out;
2009
2010 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2011 err = 0;
2012 goto out;
2013 }
2014
2015 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2016 BCM8704_PHYXS_XGXS_LANE_STAT);
2017 if (err < 0)
2018 goto out;
2019 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2020 PHYXS_XGXS_LANE_STAT_MAGIC |
2021 PHYXS_XGXS_LANE_STAT_PATTEST |
2022 PHYXS_XGXS_LANE_STAT_LANE3 |
2023 PHYXS_XGXS_LANE_STAT_LANE2 |
2024 PHYXS_XGXS_LANE_STAT_LANE1 |
2025 PHYXS_XGXS_LANE_STAT_LANE0)) {
2026 err = 0;
2027 np->link_config.active_speed = SPEED_INVALID;
2028 np->link_config.active_duplex = DUPLEX_INVALID;
2029 goto out;
2030 }
2031
2032 link_up = 1;
2033 np->link_config.active_speed = SPEED_10000;
2034 np->link_config.active_duplex = DUPLEX_FULL;
2035 err = 0;
2036
2037 out:
2038 *link_up_p = link_up;
2039 return err;
2040 }
2041
2042 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2043 {
2044 int err, link_up;
2045
2046 link_up = 0;
2047
2048 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2049 BCM8704_PMD_RCV_SIGDET);
2050 if (err < 0)
2051 goto out;
2052 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2053 err = 0;
2054 goto out;
2055 }
2056
2057 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2058 BCM8704_PCS_10G_R_STATUS);
2059 if (err < 0)
2060 goto out;
2061 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2062 err = 0;
2063 goto out;
2064 }
2065
2066 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2067 BCM8704_PHYXS_XGXS_LANE_STAT);
2068 if (err < 0)
2069 goto out;
2070
2071 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2072 PHYXS_XGXS_LANE_STAT_MAGIC |
2073 PHYXS_XGXS_LANE_STAT_LANE3 |
2074 PHYXS_XGXS_LANE_STAT_LANE2 |
2075 PHYXS_XGXS_LANE_STAT_LANE1 |
2076 PHYXS_XGXS_LANE_STAT_LANE0)) {
2077 err = 0;
2078 goto out;
2079 }
2080
2081 link_up = 1;
2082 np->link_config.active_speed = SPEED_10000;
2083 np->link_config.active_duplex = DUPLEX_FULL;
2084 err = 0;
2085
2086 out:
2087 *link_up_p = link_up;
2088 return err;
2089 }
2090
2091 static int link_status_10g(struct niu *np, int *link_up_p)
2092 {
2093 unsigned long flags;
2094 int err = -EINVAL;
2095
2096 spin_lock_irqsave(&np->lock, flags);
2097
2098 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2099 int phy_id;
2100
2101 phy_id = phy_decode(np->parent->port_phy, np->port);
2102 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2103
2104 /* handle different phy types */
2105 switch (phy_id & NIU_PHY_ID_MASK) {
2106 case NIU_PHY_ID_MRVL88X2011:
2107 err = link_status_10g_mrvl(np, link_up_p);
2108 break;
2109
2110 default: /* bcom 8704 */
2111 err = link_status_10g_bcom(np, link_up_p);
2112 break;
2113 }
2114 }
2115
2116 spin_unlock_irqrestore(&np->lock, flags);
2117
2118 return err;
2119 }
2120
2121 static int niu_10g_phy_present(struct niu *np)
2122 {
2123 u64 sig, mask, val;
2124
2125 sig = nr64(ESR_INT_SIGNALS);
2126 switch (np->port) {
2127 case 0:
2128 mask = ESR_INT_SIGNALS_P0_BITS;
2129 val = (ESR_INT_SRDY0_P0 |
2130 ESR_INT_DET0_P0 |
2131 ESR_INT_XSRDY_P0 |
2132 ESR_INT_XDP_P0_CH3 |
2133 ESR_INT_XDP_P0_CH2 |
2134 ESR_INT_XDP_P0_CH1 |
2135 ESR_INT_XDP_P0_CH0);
2136 break;
2137
2138 case 1:
2139 mask = ESR_INT_SIGNALS_P1_BITS;
2140 val = (ESR_INT_SRDY0_P1 |
2141 ESR_INT_DET0_P1 |
2142 ESR_INT_XSRDY_P1 |
2143 ESR_INT_XDP_P1_CH3 |
2144 ESR_INT_XDP_P1_CH2 |
2145 ESR_INT_XDP_P1_CH1 |
2146 ESR_INT_XDP_P1_CH0);
2147 break;
2148
2149 default:
2150 return 0;
2151 }
2152
2153 if ((sig & mask) != val)
2154 return 0;
2155 return 1;
2156 }
2157
2158 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2159 {
2160 unsigned long flags;
2161 int err = 0;
2162 int phy_present;
2163 int phy_present_prev;
2164
2165 spin_lock_irqsave(&np->lock, flags);
2166
2167 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2168 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2169 1 : 0;
2170 phy_present = niu_10g_phy_present(np);
2171 if (phy_present != phy_present_prev) {
2172 /* state change */
2173 if (phy_present) {
2174 /* A NEM was just plugged in */
2175 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2176 if (np->phy_ops->xcvr_init)
2177 err = np->phy_ops->xcvr_init(np);
2178 if (err) {
2179 err = mdio_read(np, np->phy_addr,
2180 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2181 if (err == 0xffff) {
2182 /* No mdio, back-to-back XAUI */
2183 goto out;
2184 }
2185 /* debounce */
2186 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2187 }
2188 } else {
2189 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2190 *link_up_p = 0;
2191 netif_warn(np, link, np->dev,
2192 "Hotplug PHY Removed\n");
2193 }
2194 }
2195 out:
2196 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
2197 err = link_status_10g_bcm8706(np, link_up_p);
2198 if (err == 0xffff) {
2199 /* No mdio, back-to-back XAUI: it is C10NEM */
2200 *link_up_p = 1;
2201 np->link_config.active_speed = SPEED_10000;
2202 np->link_config.active_duplex = DUPLEX_FULL;
2203 }
2204 }
2205 }
2206
2207 spin_unlock_irqrestore(&np->lock, flags);
2208
2209 return 0;
2210 }
2211
2212 static int niu_link_status(struct niu *np, int *link_up_p)
2213 {
2214 const struct niu_phy_ops *ops = np->phy_ops;
2215 int err;
2216
2217 err = 0;
2218 if (ops->link_status)
2219 err = ops->link_status(np, link_up_p);
2220
2221 return err;
2222 }
2223
2224 static void niu_timer(unsigned long __opaque)
2225 {
2226 struct niu *np = (struct niu *) __opaque;
2227 unsigned long off;
2228 int err, link_up;
2229
2230 err = niu_link_status(np, &link_up);
2231 if (!err)
2232 niu_link_status_common(np, link_up);
2233
2234 if (netif_carrier_ok(np->dev))
2235 off = 5 * HZ;
2236 else
2237 off = 1 * HZ;
2238 np->timer.expires = jiffies + off;
2239
2240 add_timer(&np->timer);
2241 }
2242
2243 static const struct niu_phy_ops phy_ops_10g_serdes = {
2244 .serdes_init = serdes_init_10g_serdes,
2245 .link_status = link_status_10g_serdes,
2246 };
2247
2248 static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2249 .serdes_init = serdes_init_niu_10g_serdes,
2250 .link_status = link_status_10g_serdes,
2251 };
2252
2253 static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2254 .serdes_init = serdes_init_niu_1g_serdes,
2255 .link_status = link_status_1g_serdes,
2256 };
2257
2258 static const struct niu_phy_ops phy_ops_1g_rgmii = {
2259 .xcvr_init = xcvr_init_1g_rgmii,
2260 .link_status = link_status_1g_rgmii,
2261 };
2262
2263 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
2264 .serdes_init = serdes_init_niu_10g_fiber,
2265 .xcvr_init = xcvr_init_10g,
2266 .link_status = link_status_10g,
2267 };
2268
2269 static const struct niu_phy_ops phy_ops_10g_fiber = {
2270 .serdes_init = serdes_init_10g,
2271 .xcvr_init = xcvr_init_10g,
2272 .link_status = link_status_10g,
2273 };
2274
2275 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2276 .serdes_init = serdes_init_10g,
2277 .xcvr_init = xcvr_init_10g_bcm8706,
2278 .link_status = link_status_10g_hotplug,
2279 };
2280
2281 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2282 .serdes_init = serdes_init_niu_10g_fiber,
2283 .xcvr_init = xcvr_init_10g_bcm8706,
2284 .link_status = link_status_10g_hotplug,
2285 };
2286
2287 static const struct niu_phy_ops phy_ops_10g_copper = {
2288 .serdes_init = serdes_init_10g,
2289 .link_status = link_status_10g, /* XXX */
2290 };
2291
2292 static const struct niu_phy_ops phy_ops_1g_fiber = {
2293 .serdes_init = serdes_init_1g,
2294 .xcvr_init = xcvr_init_1g,
2295 .link_status = link_status_1g,
2296 };
2297
2298 static const struct niu_phy_ops phy_ops_1g_copper = {
2299 .xcvr_init = xcvr_init_1g,
2300 .link_status = link_status_1g,
2301 };
2302
2303 struct niu_phy_template {
2304 const struct niu_phy_ops *ops;
2305 u32 phy_addr_base;
2306 };
2307
2308 static const struct niu_phy_template phy_template_niu_10g_fiber = {
2309 .ops = &phy_ops_10g_fiber_niu,
2310 .phy_addr_base = 16,
2311 };
2312
2313 static const struct niu_phy_template phy_template_niu_10g_serdes = {
2314 .ops = &phy_ops_10g_serdes_niu,
2315 .phy_addr_base = 0,
2316 };
2317
2318 static const struct niu_phy_template phy_template_niu_1g_serdes = {
2319 .ops = &phy_ops_1g_serdes_niu,
2320 .phy_addr_base = 0,
2321 };
2322
2323 static const struct niu_phy_template phy_template_10g_fiber = {
2324 .ops = &phy_ops_10g_fiber,
2325 .phy_addr_base = 8,
2326 };
2327
2328 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2329 .ops = &phy_ops_10g_fiber_hotplug,
2330 .phy_addr_base = 8,
2331 };
2332
2333 static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2334 .ops = &phy_ops_niu_10g_hotplug,
2335 .phy_addr_base = 8,
2336 };
2337
2338 static const struct niu_phy_template phy_template_10g_copper = {
2339 .ops = &phy_ops_10g_copper,
2340 .phy_addr_base = 10,
2341 };
2342
2343 static const struct niu_phy_template phy_template_1g_fiber = {
2344 .ops = &phy_ops_1g_fiber,
2345 .phy_addr_base = 0,
2346 };
2347
2348 static const struct niu_phy_template phy_template_1g_copper = {
2349 .ops = &phy_ops_1g_copper,
2350 .phy_addr_base = 0,
2351 };
2352
2353 static const struct niu_phy_template phy_template_1g_rgmii = {
2354 .ops = &phy_ops_1g_rgmii,
2355 .phy_addr_base = 0,
2356 };
2357
2358 static const struct niu_phy_template phy_template_10g_serdes = {
2359 .ops = &phy_ops_10g_serdes,
2360 .phy_addr_base = 0,
2361 };
2362
2363 static int niu_atca_port_num[4] = {
2364 0, 0, 11, 10
2365 };
2366
2367 static int serdes_init_10g_serdes(struct niu *np)
2368 {
2369 struct niu_link_config *lp = &np->link_config;
2370 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2371 u64 ctrl_val, test_cfg_val, sig, mask, val;
2372
2373 switch (np->port) {
2374 case 0:
2375 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2376 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2377 pll_cfg = ENET_SERDES_0_PLL_CFG;
2378 break;
2379 case 1:
2380 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2381 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2382 pll_cfg = ENET_SERDES_1_PLL_CFG;
2383 break;
2384
2385 default:
2386 return -EINVAL;
2387 }
2388 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2389 ENET_SERDES_CTRL_SDET_1 |
2390 ENET_SERDES_CTRL_SDET_2 |
2391 ENET_SERDES_CTRL_SDET_3 |
2392 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2393 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2394 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2395 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2396 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2397 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2398 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2399 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2400 test_cfg_val = 0;
2401
2402 if (lp->loopback_mode == LOOPBACK_PHY) {
2403 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2404 ENET_SERDES_TEST_MD_0_SHIFT) |
2405 (ENET_TEST_MD_PAD_LOOPBACK <<
2406 ENET_SERDES_TEST_MD_1_SHIFT) |
2407 (ENET_TEST_MD_PAD_LOOPBACK <<
2408 ENET_SERDES_TEST_MD_2_SHIFT) |
2409 (ENET_TEST_MD_PAD_LOOPBACK <<
2410 ENET_SERDES_TEST_MD_3_SHIFT));
2411 }
2412
2413 esr_reset(np);
2414 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2415 nw64(ctrl_reg, ctrl_val);
2416 nw64(test_cfg_reg, test_cfg_val);
2417
2418 /* Initialize all 4 lanes of the SERDES. */
2419 for (i = 0; i < 4; i++) {
2420 u32 rxtx_ctrl, glue0;
2421 int err;
2422
2423 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2424 if (err)
2425 return err;
2426 err = esr_read_glue0(np, i, &glue0);
2427 if (err)
2428 return err;
2429
2430 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2431 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2432 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2433
2434 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2435 ESR_GLUE_CTRL0_THCNT |
2436 ESR_GLUE_CTRL0_BLTIME);
2437 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2438 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2439 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2440 (BLTIME_300_CYCLES <<
2441 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2442
2443 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2444 if (err)
2445 return err;
2446 err = esr_write_glue0(np, i, glue0);
2447 if (err)
2448 return err;
2449 }
2450
2451
2452 sig = nr64(ESR_INT_SIGNALS);
2453 switch (np->port) {
2454 case 0:
2455 mask = ESR_INT_SIGNALS_P0_BITS;
2456 val = (ESR_INT_SRDY0_P0 |
2457 ESR_INT_DET0_P0 |
2458 ESR_INT_XSRDY_P0 |
2459 ESR_INT_XDP_P0_CH3 |
2460 ESR_INT_XDP_P0_CH2 |
2461 ESR_INT_XDP_P0_CH1 |
2462 ESR_INT_XDP_P0_CH0);
2463 break;
2464
2465 case 1:
2466 mask = ESR_INT_SIGNALS_P1_BITS;
2467 val = (ESR_INT_SRDY0_P1 |
2468 ESR_INT_DET0_P1 |
2469 ESR_INT_XSRDY_P1 |
2470 ESR_INT_XDP_P1_CH3 |
2471 ESR_INT_XDP_P1_CH2 |
2472 ESR_INT_XDP_P1_CH1 |
2473 ESR_INT_XDP_P1_CH0);
2474 break;
2475
2476 default:
2477 return -EINVAL;
2478 }
2479
2480 if ((sig & mask) != val) {
2481 int err;
2482 err = serdes_init_1g_serdes(np);
2483 if (!err) {
2484 np->flags &= ~NIU_FLAGS_10G;
2485 np->mac_xcvr = MAC_XCVR_PCS;
2486 } else {
2487 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2488 np->port);
2489 return -ENODEV;
2490 }
2491 }
2492
2493 return 0;
2494 }
2495
2496 static int niu_determine_phy_disposition(struct niu *np)
2497 {
2498 struct niu_parent *parent = np->parent;
2499 u8 plat_type = parent->plat_type;
2500 const struct niu_phy_template *tp;
2501 u32 phy_addr_off = 0;
2502
2503 if (plat_type == PLAT_TYPE_NIU) {
2504 switch (np->flags &
2505 (NIU_FLAGS_10G |
2506 NIU_FLAGS_FIBER |
2507 NIU_FLAGS_XCVR_SERDES)) {
2508 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2509 /* 10G Serdes */
2510 tp = &phy_template_niu_10g_serdes;
2511 break;
2512 case NIU_FLAGS_XCVR_SERDES:
2513 /* 1G Serdes */
2514 tp = &phy_template_niu_1g_serdes;
2515 break;
2516 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2517 /* 10G Fiber */
2518 default:
2519 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2520 tp = &phy_template_niu_10g_hotplug;
2521 if (np->port == 0)
2522 phy_addr_off = 8;
2523 if (np->port == 1)
2524 phy_addr_off = 12;
2525 } else {
2526 tp = &phy_template_niu_10g_fiber;
2527 phy_addr_off += np->port;
2528 }
2529 break;
2530 }
2531 } else {
2532 switch (np->flags &
2533 (NIU_FLAGS_10G |
2534 NIU_FLAGS_FIBER |
2535 NIU_FLAGS_XCVR_SERDES)) {
2536 case 0:
2537 /* 1G copper */
2538 tp = &phy_template_1g_copper;
2539 if (plat_type == PLAT_TYPE_VF_P0)
2540 phy_addr_off = 10;
2541 else if (plat_type == PLAT_TYPE_VF_P1)
2542 phy_addr_off = 26;
2543
2544 phy_addr_off += (np->port ^ 0x3);
2545 break;
2546
2547 case NIU_FLAGS_10G:
2548 /* 10G copper */
2549 tp = &phy_template_10g_copper;
2550 break;
2551
2552 case NIU_FLAGS_FIBER:
2553 /* 1G fiber */
2554 tp = &phy_template_1g_fiber;
2555 break;
2556
2557 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2558 /* 10G fiber */
2559 tp = &phy_template_10g_fiber;
2560 if (plat_type == PLAT_TYPE_VF_P0 ||
2561 plat_type == PLAT_TYPE_VF_P1)
2562 phy_addr_off = 8;
2563 phy_addr_off += np->port;
2564 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2565 tp = &phy_template_10g_fiber_hotplug;
2566 if (np->port == 0)
2567 phy_addr_off = 8;
2568 if (np->port == 1)
2569 phy_addr_off = 12;
2570 }
2571 break;
2572
2573 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2574 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2575 case NIU_FLAGS_XCVR_SERDES:
2576 switch(np->port) {
2577 case 0:
2578 case 1:
2579 tp = &phy_template_10g_serdes;
2580 break;
2581 case 2:
2582 case 3:
2583 tp = &phy_template_1g_rgmii;
2584 break;
2585 default:
2586 return -EINVAL;
2587 break;
2588 }
2589 phy_addr_off = niu_atca_port_num[np->port];
2590 break;
2591
2592 default:
2593 return -EINVAL;
2594 }
2595 }
2596
2597 np->phy_ops = tp->ops;
2598 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2599
2600 return 0;
2601 }
2602
2603 static int niu_init_link(struct niu *np)
2604 {
2605 struct niu_parent *parent = np->parent;
2606 int err, ignore;
2607
2608 if (parent->plat_type == PLAT_TYPE_NIU) {
2609 err = niu_xcvr_init(np);
2610 if (err)
2611 return err;
2612 msleep(200);
2613 }
2614 err = niu_serdes_init(np);
2615 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2616 return err;
2617 msleep(200);
2618 err = niu_xcvr_init(np);
2619 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2620 niu_link_status(np, &ignore);
2621 return 0;
2622 }
2623
2624 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2625 {
2626 u16 reg0 = addr[4] << 8 | addr[5];
2627 u16 reg1 = addr[2] << 8 | addr[3];
2628 u16 reg2 = addr[0] << 8 | addr[1];
2629
2630 if (np->flags & NIU_FLAGS_XMAC) {
2631 nw64_mac(XMAC_ADDR0, reg0);
2632 nw64_mac(XMAC_ADDR1, reg1);
2633 nw64_mac(XMAC_ADDR2, reg2);
2634 } else {
2635 nw64_mac(BMAC_ADDR0, reg0);
2636 nw64_mac(BMAC_ADDR1, reg1);
2637 nw64_mac(BMAC_ADDR2, reg2);
2638 }
2639 }
2640
2641 static int niu_num_alt_addr(struct niu *np)
2642 {
2643 if (np->flags & NIU_FLAGS_XMAC)
2644 return XMAC_NUM_ALT_ADDR;
2645 else
2646 return BMAC_NUM_ALT_ADDR;
2647 }
2648
2649 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2650 {
2651 u16 reg0 = addr[4] << 8 | addr[5];
2652 u16 reg1 = addr[2] << 8 | addr[3];
2653 u16 reg2 = addr[0] << 8 | addr[1];
2654
2655 if (index >= niu_num_alt_addr(np))
2656 return -EINVAL;
2657
2658 if (np->flags & NIU_FLAGS_XMAC) {
2659 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2660 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2661 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2662 } else {
2663 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2664 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2665 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2666 }
2667
2668 return 0;
2669 }
2670
2671 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2672 {
2673 unsigned long reg;
2674 u64 val, mask;
2675
2676 if (index >= niu_num_alt_addr(np))
2677 return -EINVAL;
2678
2679 if (np->flags & NIU_FLAGS_XMAC) {
2680 reg = XMAC_ADDR_CMPEN;
2681 mask = 1 << index;
2682 } else {
2683 reg = BMAC_ADDR_CMPEN;
2684 mask = 1 << (index + 1);
2685 }
2686
2687 val = nr64_mac(reg);
2688 if (on)
2689 val |= mask;
2690 else
2691 val &= ~mask;
2692 nw64_mac(reg, val);
2693
2694 return 0;
2695 }
2696
2697 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2698 int num, int mac_pref)
2699 {
2700 u64 val = nr64_mac(reg);
2701 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2702 val |= num;
2703 if (mac_pref)
2704 val |= HOST_INFO_MPR;
2705 nw64_mac(reg, val);
2706 }
2707
2708 static int __set_rdc_table_num(struct niu *np,
2709 int xmac_index, int bmac_index,
2710 int rdc_table_num, int mac_pref)
2711 {
2712 unsigned long reg;
2713
2714 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2715 return -EINVAL;
2716 if (np->flags & NIU_FLAGS_XMAC)
2717 reg = XMAC_HOST_INFO(xmac_index);
2718 else
2719 reg = BMAC_HOST_INFO(bmac_index);
2720 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2721 return 0;
2722 }
2723
2724 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2725 int mac_pref)
2726 {
2727 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2728 }
2729
2730 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2731 int mac_pref)
2732 {
2733 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2734 }
2735
2736 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2737 int table_num, int mac_pref)
2738 {
2739 if (idx >= niu_num_alt_addr(np))
2740 return -EINVAL;
2741 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2742 }
2743
2744 static u64 vlan_entry_set_parity(u64 reg_val)
2745 {
2746 u64 port01_mask;
2747 u64 port23_mask;
2748
2749 port01_mask = 0x00ff;
2750 port23_mask = 0xff00;
2751
2752 if (hweight64(reg_val & port01_mask) & 1)
2753 reg_val |= ENET_VLAN_TBL_PARITY0;
2754 else
2755 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2756
2757 if (hweight64(reg_val & port23_mask) & 1)
2758 reg_val |= ENET_VLAN_TBL_PARITY1;
2759 else
2760 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2761
2762 return reg_val;
2763 }
2764
2765 static void vlan_tbl_write(struct niu *np, unsigned long index,
2766 int port, int vpr, int rdc_table)
2767 {
2768 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2769
2770 reg_val &= ~((ENET_VLAN_TBL_VPR |
2771 ENET_VLAN_TBL_VLANRDCTBLN) <<
2772 ENET_VLAN_TBL_SHIFT(port));
2773 if (vpr)
2774 reg_val |= (ENET_VLAN_TBL_VPR <<
2775 ENET_VLAN_TBL_SHIFT(port));
2776 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2777
2778 reg_val = vlan_entry_set_parity(reg_val);
2779
2780 nw64(ENET_VLAN_TBL(index), reg_val);
2781 }
2782
2783 static void vlan_tbl_clear(struct niu *np)
2784 {
2785 int i;
2786
2787 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2788 nw64(ENET_VLAN_TBL(i), 0);
2789 }
2790
2791 static int tcam_wait_bit(struct niu *np, u64 bit)
2792 {
2793 int limit = 1000;
2794
2795 while (--limit > 0) {
2796 if (nr64(TCAM_CTL) & bit)
2797 break;
2798 udelay(1);
2799 }
2800 if (limit <= 0)
2801 return -ENODEV;
2802
2803 return 0;
2804 }
2805
2806 static int tcam_flush(struct niu *np, int index)
2807 {
2808 nw64(TCAM_KEY_0, 0x00);
2809 nw64(TCAM_KEY_MASK_0, 0xff);
2810 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2811
2812 return tcam_wait_bit(np, TCAM_CTL_STAT);
2813 }
2814
2815 #if 0
2816 static int tcam_read(struct niu *np, int index,
2817 u64 *key, u64 *mask)
2818 {
2819 int err;
2820
2821 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2822 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2823 if (!err) {
2824 key[0] = nr64(TCAM_KEY_0);
2825 key[1] = nr64(TCAM_KEY_1);
2826 key[2] = nr64(TCAM_KEY_2);
2827 key[3] = nr64(TCAM_KEY_3);
2828 mask[0] = nr64(TCAM_KEY_MASK_0);
2829 mask[1] = nr64(TCAM_KEY_MASK_1);
2830 mask[2] = nr64(TCAM_KEY_MASK_2);
2831 mask[3] = nr64(TCAM_KEY_MASK_3);
2832 }
2833 return err;
2834 }
2835 #endif
2836
2837 static int tcam_write(struct niu *np, int index,
2838 u64 *key, u64 *mask)
2839 {
2840 nw64(TCAM_KEY_0, key[0]);
2841 nw64(TCAM_KEY_1, key[1]);
2842 nw64(TCAM_KEY_2, key[2]);
2843 nw64(TCAM_KEY_3, key[3]);
2844 nw64(TCAM_KEY_MASK_0, mask[0]);
2845 nw64(TCAM_KEY_MASK_1, mask[1]);
2846 nw64(TCAM_KEY_MASK_2, mask[2]);
2847 nw64(TCAM_KEY_MASK_3, mask[3]);
2848 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2849
2850 return tcam_wait_bit(np, TCAM_CTL_STAT);
2851 }
2852
2853 #if 0
2854 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2855 {
2856 int err;
2857
2858 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2859 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2860 if (!err)
2861 *data = nr64(TCAM_KEY_1);
2862
2863 return err;
2864 }
2865 #endif
2866
2867 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2868 {
2869 nw64(TCAM_KEY_1, assoc_data);
2870 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2871
2872 return tcam_wait_bit(np, TCAM_CTL_STAT);
2873 }
2874
2875 static void tcam_enable(struct niu *np, int on)
2876 {
2877 u64 val = nr64(FFLP_CFG_1);
2878
2879 if (on)
2880 val &= ~FFLP_CFG_1_TCAM_DIS;
2881 else
2882 val |= FFLP_CFG_1_TCAM_DIS;
2883 nw64(FFLP_CFG_1, val);
2884 }
2885
2886 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2887 {
2888 u64 val = nr64(FFLP_CFG_1);
2889
2890 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2891 FFLP_CFG_1_CAMLAT |
2892 FFLP_CFG_1_CAMRATIO);
2893 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2894 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2895 nw64(FFLP_CFG_1, val);
2896
2897 val = nr64(FFLP_CFG_1);
2898 val |= FFLP_CFG_1_FFLPINITDONE;
2899 nw64(FFLP_CFG_1, val);
2900 }
2901
2902 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2903 int on)
2904 {
2905 unsigned long reg;
2906 u64 val;
2907
2908 if (class < CLASS_CODE_ETHERTYPE1 ||
2909 class > CLASS_CODE_ETHERTYPE2)
2910 return -EINVAL;
2911
2912 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2913 val = nr64(reg);
2914 if (on)
2915 val |= L2_CLS_VLD;
2916 else
2917 val &= ~L2_CLS_VLD;
2918 nw64(reg, val);
2919
2920 return 0;
2921 }
2922
2923 #if 0
2924 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2925 u64 ether_type)
2926 {
2927 unsigned long reg;
2928 u64 val;
2929
2930 if (class < CLASS_CODE_ETHERTYPE1 ||
2931 class > CLASS_CODE_ETHERTYPE2 ||
2932 (ether_type & ~(u64)0xffff) != 0)
2933 return -EINVAL;
2934
2935 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2936 val = nr64(reg);
2937 val &= ~L2_CLS_ETYPE;
2938 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2939 nw64(reg, val);
2940
2941 return 0;
2942 }
2943 #endif
2944
2945 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2946 int on)
2947 {
2948 unsigned long reg;
2949 u64 val;
2950
2951 if (class < CLASS_CODE_USER_PROG1 ||
2952 class > CLASS_CODE_USER_PROG4)
2953 return -EINVAL;
2954
2955 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2956 val = nr64(reg);
2957 if (on)
2958 val |= L3_CLS_VALID;
2959 else
2960 val &= ~L3_CLS_VALID;
2961 nw64(reg, val);
2962
2963 return 0;
2964 }
2965
2966 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2967 int ipv6, u64 protocol_id,
2968 u64 tos_mask, u64 tos_val)
2969 {
2970 unsigned long reg;
2971 u64 val;
2972
2973 if (class < CLASS_CODE_USER_PROG1 ||
2974 class > CLASS_CODE_USER_PROG4 ||
2975 (protocol_id & ~(u64)0xff) != 0 ||
2976 (tos_mask & ~(u64)0xff) != 0 ||
2977 (tos_val & ~(u64)0xff) != 0)
2978 return -EINVAL;
2979
2980 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2981 val = nr64(reg);
2982 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2983 L3_CLS_TOSMASK | L3_CLS_TOS);
2984 if (ipv6)
2985 val |= L3_CLS_IPVER;
2986 val |= (protocol_id << L3_CLS_PID_SHIFT);
2987 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2988 val |= (tos_val << L3_CLS_TOS_SHIFT);
2989 nw64(reg, val);
2990
2991 return 0;
2992 }
2993
2994 static int tcam_early_init(struct niu *np)
2995 {
2996 unsigned long i;
2997 int err;
2998
2999 tcam_enable(np, 0);
3000 tcam_set_lat_and_ratio(np,
3001 DEFAULT_TCAM_LATENCY,
3002 DEFAULT_TCAM_ACCESS_RATIO);
3003 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3004 err = tcam_user_eth_class_enable(np, i, 0);
3005 if (err)
3006 return err;
3007 }
3008 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3009 err = tcam_user_ip_class_enable(np, i, 0);
3010 if (err)
3011 return err;
3012 }
3013
3014 return 0;
3015 }
3016
3017 static int tcam_flush_all(struct niu *np)
3018 {
3019 unsigned long i;
3020
3021 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3022 int err = tcam_flush(np, i);
3023 if (err)
3024 return err;
3025 }
3026 return 0;
3027 }
3028
3029 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3030 {
3031 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0);
3032 }
3033
3034 #if 0
3035 static int hash_read(struct niu *np, unsigned long partition,
3036 unsigned long index, unsigned long num_entries,
3037 u64 *data)
3038 {
3039 u64 val = hash_addr_regval(index, num_entries);
3040 unsigned long i;
3041
3042 if (partition >= FCRAM_NUM_PARTITIONS ||
3043 index + num_entries > FCRAM_SIZE)
3044 return -EINVAL;
3045
3046 nw64(HASH_TBL_ADDR(partition), val);
3047 for (i = 0; i < num_entries; i++)
3048 data[i] = nr64(HASH_TBL_DATA(partition));
3049
3050 return 0;
3051 }
3052 #endif
3053
3054 static int hash_write(struct niu *np, unsigned long partition,
3055 unsigned long index, unsigned long num_entries,
3056 u64 *data)
3057 {
3058 u64 val = hash_addr_regval(index, num_entries);
3059 unsigned long i;
3060
3061 if (partition >= FCRAM_NUM_PARTITIONS ||
3062 index + (num_entries * 8) > FCRAM_SIZE)
3063 return -EINVAL;
3064
3065 nw64(HASH_TBL_ADDR(partition), val);
3066 for (i = 0; i < num_entries; i++)
3067 nw64(HASH_TBL_DATA(partition), data[i]);
3068
3069 return 0;
3070 }
3071
3072 static void fflp_reset(struct niu *np)
3073 {
3074 u64 val;
3075
3076 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3077 udelay(10);
3078 nw64(FFLP_CFG_1, 0);
3079
3080 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3081 nw64(FFLP_CFG_1, val);
3082 }
3083
3084 static void fflp_set_timings(struct niu *np)
3085 {
3086 u64 val = nr64(FFLP_CFG_1);
3087
3088 val &= ~FFLP_CFG_1_FFLPINITDONE;
3089 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3090 nw64(FFLP_CFG_1, val);
3091
3092 val = nr64(FFLP_CFG_1);
3093 val |= FFLP_CFG_1_FFLPINITDONE;
3094 nw64(FFLP_CFG_1, val);
3095
3096 val = nr64(FCRAM_REF_TMR);
3097 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3098 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3099 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3100 nw64(FCRAM_REF_TMR, val);
3101 }
3102
3103 static int fflp_set_partition(struct niu *np, u64 partition,
3104 u64 mask, u64 base, int enable)
3105 {
3106 unsigned long reg;
3107 u64 val;
3108
3109 if (partition >= FCRAM_NUM_PARTITIONS ||
3110 (mask & ~(u64)0x1f) != 0 ||
3111 (base & ~(u64)0x1f) != 0)
3112 return -EINVAL;
3113
3114 reg = FLW_PRT_SEL(partition);
3115
3116 val = nr64(reg);
3117 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3118 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3119 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3120 if (enable)
3121 val |= FLW_PRT_SEL_EXT;
3122 nw64(reg, val);
3123
3124 return 0;
3125 }
3126
3127 static int fflp_disable_all_partitions(struct niu *np)
3128 {
3129 unsigned long i;
3130
3131 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3132 int err = fflp_set_partition(np, 0, 0, 0, 0);
3133 if (err)
3134 return err;
3135 }
3136 return 0;
3137 }
3138
3139 static void fflp_llcsnap_enable(struct niu *np, int on)
3140 {
3141 u64 val = nr64(FFLP_CFG_1);
3142
3143 if (on)
3144 val |= FFLP_CFG_1_LLCSNAP;
3145 else
3146 val &= ~FFLP_CFG_1_LLCSNAP;
3147 nw64(FFLP_CFG_1, val);
3148 }
3149
3150 static void fflp_errors_enable(struct niu *np, int on)
3151 {
3152 u64 val = nr64(FFLP_CFG_1);
3153
3154 if (on)
3155 val &= ~FFLP_CFG_1_ERRORDIS;
3156 else
3157 val |= FFLP_CFG_1_ERRORDIS;
3158 nw64(FFLP_CFG_1, val);
3159 }
3160
3161 static int fflp_hash_clear(struct niu *np)
3162 {
3163 struct fcram_hash_ipv4 ent;
3164 unsigned long i;
3165
3166 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3167 memset(&ent, 0, sizeof(ent));
3168 ent.header = HASH_HEADER_EXT;
3169
3170 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3171 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3172 if (err)
3173 return err;
3174 }
3175 return 0;
3176 }
3177
3178 static int fflp_early_init(struct niu *np)
3179 {
3180 struct niu_parent *parent;
3181 unsigned long flags;
3182 int err;
3183
3184 niu_lock_parent(np, flags);
3185
3186 parent = np->parent;
3187 err = 0;
3188 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3189 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3190 fflp_reset(np);
3191 fflp_set_timings(np);
3192 err = fflp_disable_all_partitions(np);
3193 if (err) {
3194 netif_printk(np, probe, KERN_DEBUG, np->dev,
3195 "fflp_disable_all_partitions failed, err=%d\n",
3196 err);
3197 goto out;
3198 }
3199 }
3200
3201 err = tcam_early_init(np);
3202 if (err) {
3203 netif_printk(np, probe, KERN_DEBUG, np->dev,
3204 "tcam_early_init failed, err=%d\n", err);
3205 goto out;
3206 }
3207 fflp_llcsnap_enable(np, 1);
3208 fflp_errors_enable(np, 0);
3209 nw64(H1POLY, 0);
3210 nw64(H2POLY, 0);
3211
3212 err = tcam_flush_all(np);
3213 if (err) {
3214 netif_printk(np, probe, KERN_DEBUG, np->dev,
3215 "tcam_flush_all failed, err=%d\n", err);
3216 goto out;
3217 }
3218 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3219 err = fflp_hash_clear(np);
3220 if (err) {
3221 netif_printk(np, probe, KERN_DEBUG, np->dev,
3222 "fflp_hash_clear failed, err=%d\n",
3223 err);
3224 goto out;
3225 }
3226 }
3227
3228 vlan_tbl_clear(np);
3229
3230 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3231 }
3232 out:
3233 niu_unlock_parent(np, flags);
3234 return err;
3235 }
3236
3237 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3238 {
3239 if (class_code < CLASS_CODE_USER_PROG1 ||
3240 class_code > CLASS_CODE_SCTP_IPV6)
3241 return -EINVAL;
3242
3243 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3244 return 0;
3245 }
3246
3247 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3248 {
3249 if (class_code < CLASS_CODE_USER_PROG1 ||
3250 class_code > CLASS_CODE_SCTP_IPV6)
3251 return -EINVAL;
3252
3253 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3254 return 0;
3255 }
3256
3257 /* Entries for the ports are interleaved in the TCAM */
3258 static u16 tcam_get_index(struct niu *np, u16 idx)
3259 {
3260 /* One entry reserved for IP fragment rule */
3261 if (idx >= (np->clas.tcam_sz - 1))
3262 idx = 0;
3263 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports);
3264 }
3265
3266 static u16 tcam_get_size(struct niu *np)
3267 {
3268 /* One entry reserved for IP fragment rule */
3269 return np->clas.tcam_sz - 1;
3270 }
3271
3272 static u16 tcam_get_valid_entry_cnt(struct niu *np)
3273 {
3274 /* One entry reserved for IP fragment rule */
3275 return np->clas.tcam_valid_entries - 1;
3276 }
3277
3278 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3279 u32 offset, u32 size, u32 truesize)
3280 {
3281 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, offset, size);
3282
3283 skb->len += size;
3284 skb->data_len += size;
3285 skb->truesize += truesize;
3286 }
3287
3288 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3289 {
3290 a >>= PAGE_SHIFT;
3291 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3292
3293 return a & (MAX_RBR_RING_SIZE - 1);
3294 }
3295
3296 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3297 struct page ***link)
3298 {
3299 unsigned int h = niu_hash_rxaddr(rp, addr);
3300 struct page *p, **pp;
3301
3302 addr &= PAGE_MASK;
3303 pp = &rp->rxhash[h];
3304 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3305 if (p->index == addr) {
3306 *link = pp;
3307 goto found;
3308 }
3309 }
3310 BUG();
3311
3312 found:
3313 return p;
3314 }
3315
3316 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3317 {
3318 unsigned int h = niu_hash_rxaddr(rp, base);
3319
3320 page->index = base;
3321 page->mapping = (struct address_space *) rp->rxhash[h];
3322 rp->rxhash[h] = page;
3323 }
3324
3325 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3326 gfp_t mask, int start_index)
3327 {
3328 struct page *page;
3329 u64 addr;
3330 int i;
3331
3332 page = alloc_page(mask);
3333 if (!page)
3334 return -ENOMEM;
3335
3336 addr = np->ops->map_page(np->device, page, 0,
3337 PAGE_SIZE, DMA_FROM_DEVICE);
3338
3339 niu_hash_page(rp, page, addr);
3340 if (rp->rbr_blocks_per_page > 1)
3341 atomic_add(rp->rbr_blocks_per_page - 1,
3342 &compound_head(page)->_count);
3343
3344 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3345 __le32 *rbr = &rp->rbr[start_index + i];
3346
3347 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3348 addr += rp->rbr_block_size;
3349 }
3350
3351 return 0;
3352 }
3353
3354 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3355 {
3356 int index = rp->rbr_index;
3357
3358 rp->rbr_pending++;
3359 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3360 int err = niu_rbr_add_page(np, rp, mask, index);
3361
3362 if (unlikely(err)) {
3363 rp->rbr_pending--;
3364 return;
3365 }
3366
3367 rp->rbr_index += rp->rbr_blocks_per_page;
3368 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3369 if (rp->rbr_index == rp->rbr_table_size)
3370 rp->rbr_index = 0;
3371
3372 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3373 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3374 rp->rbr_pending = 0;
3375 }
3376 }
3377 }
3378
3379 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3380 {
3381 unsigned int index = rp->rcr_index;
3382 int num_rcr = 0;
3383
3384 rp->rx_dropped++;
3385 while (1) {
3386 struct page *page, **link;
3387 u64 addr, val;
3388 u32 rcr_size;
3389
3390 num_rcr++;
3391
3392 val = le64_to_cpup(&rp->rcr[index]);
3393 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3394 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3395 page = niu_find_rxpage(rp, addr, &link);
3396
3397 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3398 RCR_ENTRY_PKTBUFSZ_SHIFT];
3399 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3400 *link = (struct page *) page->mapping;
3401 np->ops->unmap_page(np->device, page->index,
3402 PAGE_SIZE, DMA_FROM_DEVICE);
3403 page->index = 0;
3404 page->mapping = NULL;
3405 __free_page(page);
3406 rp->rbr_refill_pending++;
3407 }
3408
3409 index = NEXT_RCR(rp, index);
3410 if (!(val & RCR_ENTRY_MULTI))
3411 break;
3412
3413 }
3414 rp->rcr_index = index;
3415
3416 return num_rcr;
3417 }
3418
3419 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3420 struct rx_ring_info *rp)
3421 {
3422 unsigned int index = rp->rcr_index;
3423 struct rx_pkt_hdr1 *rh;
3424 struct sk_buff *skb;
3425 int len, num_rcr;
3426
3427 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3428 if (unlikely(!skb))
3429 return niu_rx_pkt_ignore(np, rp);
3430
3431 num_rcr = 0;
3432 while (1) {
3433 struct page *page, **link;
3434 u32 rcr_size, append_size;
3435 u64 addr, val, off;
3436
3437 num_rcr++;
3438
3439 val = le64_to_cpup(&rp->rcr[index]);
3440
3441 len = (val & RCR_ENTRY_L2_LEN) >>
3442 RCR_ENTRY_L2_LEN_SHIFT;
3443 len -= ETH_FCS_LEN;
3444
3445 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3446 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3447 page = niu_find_rxpage(rp, addr, &link);
3448
3449 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3450 RCR_ENTRY_PKTBUFSZ_SHIFT];
3451
3452 off = addr & ~PAGE_MASK;
3453 append_size = rcr_size;
3454 if (num_rcr == 1) {
3455 int ptype;
3456
3457 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3458 if ((ptype == RCR_PKT_TYPE_TCP ||
3459 ptype == RCR_PKT_TYPE_UDP) &&
3460 !(val & (RCR_ENTRY_NOPORT |
3461 RCR_ENTRY_ERROR)))
3462 skb->ip_summed = CHECKSUM_UNNECESSARY;
3463 else
3464 skb_checksum_none_assert(skb);
3465 } else if (!(val & RCR_ENTRY_MULTI))
3466 append_size = len - skb->len;
3467
3468 niu_rx_skb_append(skb, page, off, append_size, rcr_size);
3469 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3470 *link = (struct page *) page->mapping;
3471 np->ops->unmap_page(np->device, page->index,
3472 PAGE_SIZE, DMA_FROM_DEVICE);
3473 page->index = 0;
3474 page->mapping = NULL;
3475 rp->rbr_refill_pending++;
3476 } else
3477 get_page(page);
3478
3479 index = NEXT_RCR(rp, index);
3480 if (!(val & RCR_ENTRY_MULTI))
3481 break;
3482
3483 }
3484 rp->rcr_index = index;
3485
3486 len += sizeof(*rh);
3487 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3488 __pskb_pull_tail(skb, len);
3489
3490 rh = (struct rx_pkt_hdr1 *) skb->data;
3491 if (np->dev->features & NETIF_F_RXHASH)
3492 skb->rxhash = ((u32)rh->hashval2_0 << 24 |
3493 (u32)rh->hashval2_1 << 16 |
3494 (u32)rh->hashval1_1 << 8 |
3495 (u32)rh->hashval1_2 << 0);
3496 skb_pull(skb, sizeof(*rh));
3497
3498 rp->rx_packets++;
3499 rp->rx_bytes += skb->len;
3500
3501 skb->protocol = eth_type_trans(skb, np->dev);
3502 skb_record_rx_queue(skb, rp->rx_channel);
3503 napi_gro_receive(napi, skb);
3504
3505 return num_rcr;
3506 }
3507
3508 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3509 {
3510 int blocks_per_page = rp->rbr_blocks_per_page;
3511 int err, index = rp->rbr_index;
3512
3513 err = 0;
3514 while (index < (rp->rbr_table_size - blocks_per_page)) {
3515 err = niu_rbr_add_page(np, rp, mask, index);
3516 if (err)
3517 break;
3518
3519 index += blocks_per_page;
3520 }
3521
3522 rp->rbr_index = index;
3523 return err;
3524 }
3525
3526 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3527 {
3528 int i;
3529
3530 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3531 struct page *page;
3532
3533 page = rp->rxhash[i];
3534 while (page) {
3535 struct page *next = (struct page *) page->mapping;
3536 u64 base = page->index;
3537
3538 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3539 DMA_FROM_DEVICE);
3540 page->index = 0;
3541 page->mapping = NULL;
3542
3543 __free_page(page);
3544
3545 page = next;
3546 }
3547 }
3548
3549 for (i = 0; i < rp->rbr_table_size; i++)
3550 rp->rbr[i] = cpu_to_le32(0);
3551 rp->rbr_index = 0;
3552 }
3553
3554 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3555 {
3556 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3557 struct sk_buff *skb = tb->skb;
3558 struct tx_pkt_hdr *tp;
3559 u64 tx_flags;
3560 int i, len;
3561
3562 tp = (struct tx_pkt_hdr *) skb->data;
3563 tx_flags = le64_to_cpup(&tp->flags);
3564
3565 rp->tx_packets++;
3566 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3567 ((tx_flags & TXHDR_PAD) / 2));
3568
3569 len = skb_headlen(skb);
3570 np->ops->unmap_single(np->device, tb->mapping,
3571 len, DMA_TO_DEVICE);
3572
3573 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3574 rp->mark_pending--;
3575
3576 tb->skb = NULL;
3577 do {
3578 idx = NEXT_TX(rp, idx);
3579 len -= MAX_TX_DESC_LEN;
3580 } while (len > 0);
3581
3582 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3583 tb = &rp->tx_buffs[idx];
3584 BUG_ON(tb->skb != NULL);
3585 np->ops->unmap_page(np->device, tb->mapping,
3586 skb_frag_size(&skb_shinfo(skb)->frags[i]),
3587 DMA_TO_DEVICE);
3588 idx = NEXT_TX(rp, idx);
3589 }
3590
3591 dev_kfree_skb(skb);
3592
3593 return idx;
3594 }
3595
3596 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3597
3598 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3599 {
3600 struct netdev_queue *txq;
3601 unsigned int tx_bytes;
3602 u16 pkt_cnt, tmp;
3603 int cons, index;
3604 u64 cs;
3605
3606 index = (rp - np->tx_rings);
3607 txq = netdev_get_tx_queue(np->dev, index);
3608
3609 cs = rp->tx_cs;
3610 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3611 goto out;
3612
3613 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3614 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3615 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3616
3617 rp->last_pkt_cnt = tmp;
3618
3619 cons = rp->cons;
3620
3621 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3622 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
3623
3624 tx_bytes = 0;
3625 tmp = pkt_cnt;
3626 while (tmp--) {
3627 tx_bytes += rp->tx_buffs[cons].skb->len;
3628 cons = release_tx_packet(np, rp, cons);
3629 }
3630
3631 rp->cons = cons;
3632 smp_mb();
3633
3634 netdev_tx_completed_queue(txq, pkt_cnt, tx_bytes);
3635
3636 out:
3637 if (unlikely(netif_tx_queue_stopped(txq) &&
3638 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3639 __netif_tx_lock(txq, smp_processor_id());
3640 if (netif_tx_queue_stopped(txq) &&
3641 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3642 netif_tx_wake_queue(txq);
3643 __netif_tx_unlock(txq);
3644 }
3645 }
3646
3647 static inline void niu_sync_rx_discard_stats(struct niu *np,
3648 struct rx_ring_info *rp,
3649 const int limit)
3650 {
3651 /* This elaborate scheme is needed for reading the RX discard
3652 * counters, as they are only 16-bit and can overflow quickly,
3653 * and because the overflow indication bit is not usable as
3654 * the counter value does not wrap, but remains at max value
3655 * 0xFFFF.
3656 *
3657 * In theory and in practice counters can be lost in between
3658 * reading nr64() and clearing the counter nw64(). For this
3659 * reason, the number of counter clearings nw64() is
3660 * limited/reduced though the limit parameter.
3661 */
3662 int rx_channel = rp->rx_channel;
3663 u32 misc, wred;
3664
3665 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3666 * following discard events: IPP (Input Port Process),
3667 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3668 * Block Ring) prefetch buffer is empty.
3669 */
3670 misc = nr64(RXMISC(rx_channel));
3671 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3672 nw64(RXMISC(rx_channel), 0);
3673 rp->rx_errors += misc & RXMISC_COUNT;
3674
3675 if (unlikely(misc & RXMISC_OFLOW))
3676 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3677 rx_channel);
3678
3679 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3680 "rx-%d: MISC drop=%u over=%u\n",
3681 rx_channel, misc, misc-limit);
3682 }
3683
3684 /* WRED (Weighted Random Early Discard) by hardware */
3685 wred = nr64(RED_DIS_CNT(rx_channel));
3686 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3687 nw64(RED_DIS_CNT(rx_channel), 0);
3688 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3689
3690 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3691 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
3692
3693 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3694 "rx-%d: WRED drop=%u over=%u\n",
3695 rx_channel, wred, wred-limit);
3696 }
3697 }
3698
3699 static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3700 struct rx_ring_info *rp, int budget)
3701 {
3702 int qlen, rcr_done = 0, work_done = 0;
3703 struct rxdma_mailbox *mbox = rp->mbox;
3704 u64 stat;
3705
3706 #if 1
3707 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3708 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3709 #else
3710 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3711 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3712 #endif
3713 mbox->rx_dma_ctl_stat = 0;
3714 mbox->rcrstat_a = 0;
3715
3716 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3717 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3718 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
3719
3720 rcr_done = work_done = 0;
3721 qlen = min(qlen, budget);
3722 while (work_done < qlen) {
3723 rcr_done += niu_process_rx_pkt(napi, np, rp);
3724 work_done++;
3725 }
3726
3727 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3728 unsigned int i;
3729
3730 for (i = 0; i < rp->rbr_refill_pending; i++)
3731 niu_rbr_refill(np, rp, GFP_ATOMIC);
3732 rp->rbr_refill_pending = 0;
3733 }
3734
3735 stat = (RX_DMA_CTL_STAT_MEX |
3736 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3737 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3738
3739 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3740
3741 /* Only sync discards stats when qlen indicate potential for drops */
3742 if (qlen > 10)
3743 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
3744
3745 return work_done;
3746 }
3747
3748 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3749 {
3750 u64 v0 = lp->v0;
3751 u32 tx_vec = (v0 >> 32);
3752 u32 rx_vec = (v0 & 0xffffffff);
3753 int i, work_done = 0;
3754
3755 netif_printk(np, intr, KERN_DEBUG, np->dev,
3756 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
3757
3758 for (i = 0; i < np->num_tx_rings; i++) {
3759 struct tx_ring_info *rp = &np->tx_rings[i];
3760 if (tx_vec & (1 << rp->tx_channel))
3761 niu_tx_work(np, rp);
3762 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3763 }
3764
3765 for (i = 0; i < np->num_rx_rings; i++) {
3766 struct rx_ring_info *rp = &np->rx_rings[i];
3767
3768 if (rx_vec & (1 << rp->rx_channel)) {
3769 int this_work_done;
3770
3771 this_work_done = niu_rx_work(&lp->napi, np, rp,
3772 budget);
3773
3774 budget -= this_work_done;
3775 work_done += this_work_done;
3776 }
3777 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3778 }
3779
3780 return work_done;
3781 }
3782
3783 static int niu_poll(struct napi_struct *napi, int budget)
3784 {
3785 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3786 struct niu *np = lp->np;
3787 int work_done;
3788
3789 work_done = niu_poll_core(np, lp, budget);
3790
3791 if (work_done < budget) {
3792 napi_complete(napi);
3793 niu_ldg_rearm(np, lp, 1);
3794 }
3795 return work_done;
3796 }
3797
3798 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3799 u64 stat)
3800 {
3801 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
3802
3803 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3804 pr_cont("RBR_TMOUT ");
3805 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3806 pr_cont("RSP_CNT ");
3807 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3808 pr_cont("BYTE_EN_BUS ");
3809 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3810 pr_cont("RSP_DAT ");
3811 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3812 pr_cont("RCR_ACK ");
3813 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3814 pr_cont("RCR_SHA_PAR ");
3815 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3816 pr_cont("RBR_PRE_PAR ");
3817 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3818 pr_cont("CONFIG ");
3819 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3820 pr_cont("RCRINCON ");
3821 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3822 pr_cont("RCRFULL ");
3823 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3824 pr_cont("RBRFULL ");
3825 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3826 pr_cont("RBRLOGPAGE ");
3827 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3828 pr_cont("CFIGLOGPAGE ");
3829 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3830 pr_cont("DC_FIDO ");
3831
3832 pr_cont(")\n");
3833 }
3834
3835 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3836 {
3837 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3838 int err = 0;
3839
3840
3841 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3842 RX_DMA_CTL_STAT_PORT_FATAL))
3843 err = -EINVAL;
3844
3845 if (err) {
3846 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3847 rp->rx_channel,
3848 (unsigned long long) stat);
3849
3850 niu_log_rxchan_errors(np, rp, stat);
3851 }
3852
3853 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3854 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3855
3856 return err;
3857 }
3858
3859 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3860 u64 cs)
3861 {
3862 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
3863
3864 if (cs & TX_CS_MBOX_ERR)
3865 pr_cont("MBOX ");
3866 if (cs & TX_CS_PKT_SIZE_ERR)
3867 pr_cont("PKT_SIZE ");
3868 if (cs & TX_CS_TX_RING_OFLOW)
3869 pr_cont("TX_RING_OFLOW ");
3870 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3871 pr_cont("PREF_BUF_PAR ");
3872 if (cs & TX_CS_NACK_PREF)
3873 pr_cont("NACK_PREF ");
3874 if (cs & TX_CS_NACK_PKT_RD)
3875 pr_cont("NACK_PKT_RD ");
3876 if (cs & TX_CS_CONF_PART_ERR)
3877 pr_cont("CONF_PART ");
3878 if (cs & TX_CS_PKT_PRT_ERR)
3879 pr_cont("PKT_PTR ");
3880
3881 pr_cont(")\n");
3882 }
3883
3884 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3885 {
3886 u64 cs, logh, logl;
3887
3888 cs = nr64(TX_CS(rp->tx_channel));
3889 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3890 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3891
3892 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3893 rp->tx_channel,
3894 (unsigned long long)cs,
3895 (unsigned long long)logh,
3896 (unsigned long long)logl);
3897
3898 niu_log_txchan_errors(np, rp, cs);
3899
3900 return -ENODEV;
3901 }
3902
3903 static int niu_mif_interrupt(struct niu *np)
3904 {
3905 u64 mif_status = nr64(MIF_STATUS);
3906 int phy_mdint = 0;
3907
3908 if (np->flags & NIU_FLAGS_XMAC) {
3909 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3910
3911 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3912 phy_mdint = 1;
3913 }
3914
3915 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3916 (unsigned long long)mif_status, phy_mdint);
3917
3918 return -ENODEV;
3919 }
3920
3921 static void niu_xmac_interrupt(struct niu *np)
3922 {
3923 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3924 u64 val;
3925
3926 val = nr64_mac(XTXMAC_STATUS);
3927 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3928 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3929 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3930 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3931 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3932 mp->tx_fifo_errors++;
3933 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3934 mp->tx_overflow_errors++;
3935 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3936 mp->tx_max_pkt_size_errors++;
3937 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3938 mp->tx_underflow_errors++;
3939
3940 val = nr64_mac(XRXMAC_STATUS);
3941 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3942 mp->rx_local_faults++;
3943 if (val & XRXMAC_STATUS_RFLT_DET)
3944 mp->rx_remote_faults++;
3945 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3946 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3947 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3948 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3949 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3950 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3951 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3952 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3953 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3954 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3955 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3956 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3957 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3958 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3959 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3960 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3961 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3962 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3963 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3964 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3965 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3966 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3967 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3968 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3969 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3970 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3971 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3972 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3973 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3974 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3975 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3976 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3977 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3978 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3979 if (val & XRXMAC_STATUS_RXUFLOW)
3980 mp->rx_underflows++;
3981 if (val & XRXMAC_STATUS_RXOFLOW)
3982 mp->rx_overflows++;
3983
3984 val = nr64_mac(XMAC_FC_STAT);
3985 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3986 mp->pause_off_state++;
3987 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3988 mp->pause_on_state++;
3989 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3990 mp->pause_received++;
3991 }
3992
3993 static void niu_bmac_interrupt(struct niu *np)
3994 {
3995 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3996 u64 val;
3997
3998 val = nr64_mac(BTXMAC_STATUS);
3999 if (val & BTXMAC_STATUS_UNDERRUN)
4000 mp->tx_underflow_errors++;
4001 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4002 mp->tx_max_pkt_size_errors++;
4003 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4004 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4005 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4006 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4007
4008 val = nr64_mac(BRXMAC_STATUS);
4009 if (val & BRXMAC_STATUS_OVERFLOW)
4010 mp->rx_overflows++;
4011 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4012 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4013 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4014 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4015 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4016 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4017 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4018 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4019
4020 val = nr64_mac(BMAC_CTRL_STATUS);
4021 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4022 mp->pause_off_state++;
4023 if (val & BMAC_CTRL_STATUS_PAUSE)
4024 mp->pause_on_state++;
4025 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4026 mp->pause_received++;
4027 }
4028
4029 static int niu_mac_interrupt(struct niu *np)
4030 {
4031 if (np->flags & NIU_FLAGS_XMAC)
4032 niu_xmac_interrupt(np);
4033 else
4034 niu_bmac_interrupt(np);
4035
4036 return 0;
4037 }
4038
4039 static void niu_log_device_error(struct niu *np, u64 stat)
4040 {
4041 netdev_err(np->dev, "Core device errors ( ");
4042
4043 if (stat & SYS_ERR_MASK_META2)
4044 pr_cont("META2 ");
4045 if (stat & SYS_ERR_MASK_META1)
4046 pr_cont("META1 ");
4047 if (stat & SYS_ERR_MASK_PEU)
4048 pr_cont("PEU ");
4049 if (stat & SYS_ERR_MASK_TXC)
4050 pr_cont("TXC ");
4051 if (stat & SYS_ERR_MASK_RDMC)
4052 pr_cont("RDMC ");
4053 if (stat & SYS_ERR_MASK_TDMC)
4054 pr_cont("TDMC ");
4055 if (stat & SYS_ERR_MASK_ZCP)
4056 pr_cont("ZCP ");
4057 if (stat & SYS_ERR_MASK_FFLP)
4058 pr_cont("FFLP ");
4059 if (stat & SYS_ERR_MASK_IPP)
4060 pr_cont("IPP ");
4061 if (stat & SYS_ERR_MASK_MAC)
4062 pr_cont("MAC ");
4063 if (stat & SYS_ERR_MASK_SMX)
4064 pr_cont("SMX ");
4065
4066 pr_cont(")\n");
4067 }
4068
4069 static int niu_device_error(struct niu *np)
4070 {
4071 u64 stat = nr64(SYS_ERR_STAT);
4072
4073 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4074 (unsigned long long)stat);
4075
4076 niu_log_device_error(np, stat);
4077
4078 return -ENODEV;
4079 }
4080
4081 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4082 u64 v0, u64 v1, u64 v2)
4083 {
4084
4085 int i, err = 0;
4086
4087 lp->v0 = v0;
4088 lp->v1 = v1;
4089 lp->v2 = v2;
4090
4091 if (v1 & 0x00000000ffffffffULL) {
4092 u32 rx_vec = (v1 & 0xffffffff);
4093
4094 for (i = 0; i < np->num_rx_rings; i++) {
4095 struct rx_ring_info *rp = &np->rx_rings[i];
4096
4097 if (rx_vec & (1 << rp->rx_channel)) {
4098 int r = niu_rx_error(np, rp);
4099 if (r) {
4100 err = r;
4101 } else {
4102 if (!v0)
4103 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4104 RX_DMA_CTL_STAT_MEX);
4105 }
4106 }
4107 }
4108 }
4109 if (v1 & 0x7fffffff00000000ULL) {
4110 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4111
4112 for (i = 0; i < np->num_tx_rings; i++) {
4113 struct tx_ring_info *rp = &np->tx_rings[i];
4114
4115 if (tx_vec & (1 << rp->tx_channel)) {
4116 int r = niu_tx_error(np, rp);
4117 if (r)
4118 err = r;
4119 }
4120 }
4121 }
4122 if ((v0 | v1) & 0x8000000000000000ULL) {
4123 int r = niu_mif_interrupt(np);
4124 if (r)
4125 err = r;
4126 }
4127 if (v2) {
4128 if (v2 & 0x01ef) {
4129 int r = niu_mac_interrupt(np);
4130 if (r)
4131 err = r;
4132 }
4133 if (v2 & 0x0210) {
4134 int r = niu_device_error(np);
4135 if (r)
4136 err = r;
4137 }
4138 }
4139
4140 if (err)
4141 niu_enable_interrupts(np, 0);
4142
4143 return err;
4144 }
4145
4146 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4147 int ldn)
4148 {
4149 struct rxdma_mailbox *mbox = rp->mbox;
4150 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4151
4152 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4153 RX_DMA_CTL_STAT_RCRTO);
4154 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4155
4156 netif_printk(np, intr, KERN_DEBUG, np->dev,
4157 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
4158 }
4159
4160 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4161 int ldn)
4162 {
4163 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4164
4165 netif_printk(np, intr, KERN_DEBUG, np->dev,
4166 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
4167 }
4168
4169 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4170 {
4171 struct niu_parent *parent = np->parent;
4172 u32 rx_vec, tx_vec;
4173 int i;
4174
4175 tx_vec = (v0 >> 32);
4176 rx_vec = (v0 & 0xffffffff);
4177
4178 for (i = 0; i < np->num_rx_rings; i++) {
4179 struct rx_ring_info *rp = &np->rx_rings[i];
4180 int ldn = LDN_RXDMA(rp->rx_channel);
4181
4182 if (parent->ldg_map[ldn] != ldg)
4183 continue;
4184
4185 nw64(LD_IM0(ldn), LD_IM0_MASK);
4186 if (rx_vec & (1 << rp->rx_channel))
4187 niu_rxchan_intr(np, rp, ldn);
4188 }
4189
4190 for (i = 0; i < np->num_tx_rings; i++) {
4191 struct tx_ring_info *rp = &np->tx_rings[i];
4192 int ldn = LDN_TXDMA(rp->tx_channel);
4193
4194 if (parent->ldg_map[ldn] != ldg)
4195 continue;
4196
4197 nw64(LD_IM0(ldn), LD_IM0_MASK);
4198 if (tx_vec & (1 << rp->tx_channel))
4199 niu_txchan_intr(np, rp, ldn);
4200 }
4201 }
4202
4203 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4204 u64 v0, u64 v1, u64 v2)
4205 {
4206 if (likely(napi_schedule_prep(&lp->napi))) {
4207 lp->v0 = v0;
4208 lp->v1 = v1;
4209 lp->v2 = v2;
4210 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
4211 __napi_schedule(&lp->napi);
4212 }
4213 }
4214
4215 static irqreturn_t niu_interrupt(int irq, void *dev_id)
4216 {
4217 struct niu_ldg *lp = dev_id;
4218 struct niu *np = lp->np;
4219 int ldg = lp->ldg_num;
4220 unsigned long flags;
4221 u64 v0, v1, v2;
4222
4223 if (netif_msg_intr(np))
4224 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4225 __func__, lp, ldg);
4226
4227 spin_lock_irqsave(&np->lock, flags);
4228
4229 v0 = nr64(LDSV0(ldg));
4230 v1 = nr64(LDSV1(ldg));
4231 v2 = nr64(LDSV2(ldg));
4232
4233 if (netif_msg_intr(np))
4234 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4235 (unsigned long long) v0,
4236 (unsigned long long) v1,
4237 (unsigned long long) v2);
4238
4239 if (unlikely(!v0 && !v1 && !v2)) {
4240 spin_unlock_irqrestore(&np->lock, flags);
4241 return IRQ_NONE;
4242 }
4243
4244 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
4245 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4246 if (err)
4247 goto out;
4248 }
4249 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4250 niu_schedule_napi(np, lp, v0, v1, v2);
4251 else
4252 niu_ldg_rearm(np, lp, 1);
4253 out:
4254 spin_unlock_irqrestore(&np->lock, flags);
4255
4256 return IRQ_HANDLED;
4257 }
4258
4259 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4260 {
4261 if (rp->mbox) {
4262 np->ops->free_coherent(np->device,
4263 sizeof(struct rxdma_mailbox),
4264 rp->mbox, rp->mbox_dma);
4265 rp->mbox = NULL;
4266 }
4267 if (rp->rcr) {
4268 np->ops->free_coherent(np->device,
4269 MAX_RCR_RING_SIZE * sizeof(__le64),
4270 rp->rcr, rp->rcr_dma);
4271 rp->rcr = NULL;
4272 rp->rcr_table_size = 0;
4273 rp->rcr_index = 0;
4274 }
4275 if (rp->rbr) {
4276 niu_rbr_free(np, rp);
4277
4278 np->ops->free_coherent(np->device,
4279 MAX_RBR_RING_SIZE * sizeof(__le32),
4280 rp->rbr, rp->rbr_dma);
4281 rp->rbr = NULL;
4282 rp->rbr_table_size = 0;
4283 rp->rbr_index = 0;
4284 }
4285 kfree(rp->rxhash);
4286 rp->rxhash = NULL;
4287 }
4288
4289 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4290 {
4291 if (rp->mbox) {
4292 np->ops->free_coherent(np->device,
4293 sizeof(struct txdma_mailbox),
4294 rp->mbox, rp->mbox_dma);
4295 rp->mbox = NULL;
4296 }
4297 if (rp->descr) {
4298 int i;
4299
4300 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4301 if (rp->tx_buffs[i].skb)
4302 (void) release_tx_packet(np, rp, i);
4303 }
4304
4305 np->ops->free_coherent(np->device,
4306 MAX_TX_RING_SIZE * sizeof(__le64),
4307 rp->descr, rp->descr_dma);
4308 rp->descr = NULL;
4309 rp->pending = 0;
4310 rp->prod = 0;
4311 rp->cons = 0;
4312 rp->wrap_bit = 0;
4313 }
4314 }
4315
4316 static void niu_free_channels(struct niu *np)
4317 {
4318 int i;
4319
4320 if (np->rx_rings) {
4321 for (i = 0; i < np->num_rx_rings; i++) {
4322 struct rx_ring_info *rp = &np->rx_rings[i];
4323
4324 niu_free_rx_ring_info(np, rp);
4325 }
4326 kfree(np->rx_rings);
4327 np->rx_rings = NULL;
4328 np->num_rx_rings = 0;
4329 }
4330
4331 if (np->tx_rings) {
4332 for (i = 0; i < np->num_tx_rings; i++) {
4333 struct tx_ring_info *rp = &np->tx_rings[i];
4334
4335 niu_free_tx_ring_info(np, rp);
4336 netdev_tx_reset_queue(netdev_get_tx_queue(np->dev, i));
4337 }
4338 kfree(np->tx_rings);
4339 np->tx_rings = NULL;
4340 np->num_tx_rings = 0;
4341 }
4342 }
4343
4344 static int niu_alloc_rx_ring_info(struct niu *np,
4345 struct rx_ring_info *rp)
4346 {
4347 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4348
4349 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4350 GFP_KERNEL);
4351 if (!rp->rxhash)
4352 return -ENOMEM;
4353
4354 rp->mbox = np->ops->alloc_coherent(np->device,
4355 sizeof(struct rxdma_mailbox),
4356 &rp->mbox_dma, GFP_KERNEL);
4357 if (!rp->mbox)
4358 return -ENOMEM;
4359 if ((unsigned long)rp->mbox & (64UL - 1)) {
4360 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4361 rp->mbox);
4362 return -EINVAL;
4363 }
4364
4365 rp->rcr = np->ops->alloc_coherent(np->device,
4366 MAX_RCR_RING_SIZE * sizeof(__le64),
4367 &rp->rcr_dma, GFP_KERNEL);
4368 if (!rp->rcr)
4369 return -ENOMEM;
4370 if ((unsigned long)rp->rcr & (64UL - 1)) {
4371 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4372 rp->rcr);
4373 return -EINVAL;
4374 }
4375 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4376 rp->rcr_index = 0;
4377
4378 rp->rbr = np->ops->alloc_coherent(np->device,
4379 MAX_RBR_RING_SIZE * sizeof(__le32),
4380 &rp->rbr_dma, GFP_KERNEL);
4381 if (!rp->rbr)
4382 return -ENOMEM;
4383 if ((unsigned long)rp->rbr & (64UL - 1)) {
4384 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4385 rp->rbr);
4386 return -EINVAL;
4387 }
4388 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4389 rp->rbr_index = 0;
4390 rp->rbr_pending = 0;
4391
4392 return 0;
4393 }
4394
4395 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4396 {
4397 int mtu = np->dev->mtu;
4398
4399 /* These values are recommended by the HW designers for fair
4400 * utilization of DRR amongst the rings.
4401 */
4402 rp->max_burst = mtu + 32;
4403 if (rp->max_burst > 4096)
4404 rp->max_burst = 4096;
4405 }
4406
4407 static int niu_alloc_tx_ring_info(struct niu *np,
4408 struct tx_ring_info *rp)
4409 {
4410 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4411
4412 rp->mbox = np->ops->alloc_coherent(np->device,
4413 sizeof(struct txdma_mailbox),
4414 &rp->mbox_dma, GFP_KERNEL);
4415 if (!rp->mbox)
4416 return -ENOMEM;
4417 if ((unsigned long)rp->mbox & (64UL - 1)) {
4418 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4419 rp->mbox);
4420 return -EINVAL;
4421 }
4422
4423 rp->descr = np->ops->alloc_coherent(np->device,
4424 MAX_TX_RING_SIZE * sizeof(__le64),
4425 &rp->descr_dma, GFP_KERNEL);
4426 if (!rp->descr)
4427 return -ENOMEM;
4428 if ((unsigned long)rp->descr & (64UL - 1)) {
4429 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4430 rp->descr);
4431 return -EINVAL;
4432 }
4433
4434 rp->pending = MAX_TX_RING_SIZE;
4435 rp->prod = 0;
4436 rp->cons = 0;
4437 rp->wrap_bit = 0;
4438
4439 /* XXX make these configurable... XXX */
4440 rp->mark_freq = rp->pending / 4;
4441
4442 niu_set_max_burst(np, rp);
4443
4444 return 0;
4445 }
4446
4447 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4448 {
4449 u16 bss;
4450
4451 bss = min(PAGE_SHIFT, 15);
4452
4453 rp->rbr_block_size = 1 << bss;
4454 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4455
4456 rp->rbr_sizes[0] = 256;
4457 rp->rbr_sizes[1] = 1024;
4458 if (np->dev->mtu > ETH_DATA_LEN) {
4459 switch (PAGE_SIZE) {
4460 case 4 * 1024:
4461 rp->rbr_sizes[2] = 4096;
4462 break;
4463
4464 default:
4465 rp->rbr_sizes[2] = 8192;
4466 break;
4467 }
4468 } else {
4469 rp->rbr_sizes[2] = 2048;
4470 }
4471 rp->rbr_sizes[3] = rp->rbr_block_size;
4472 }
4473
4474 static int niu_alloc_channels(struct niu *np)
4475 {
4476 struct niu_parent *parent = np->parent;
4477 int first_rx_channel, first_tx_channel;
4478 int num_rx_rings, num_tx_rings;
4479 struct rx_ring_info *rx_rings;
4480 struct tx_ring_info *tx_rings;
4481 int i, port, err;
4482
4483 port = np->port;
4484 first_rx_channel = first_tx_channel = 0;
4485 for (i = 0; i < port; i++) {
4486 first_rx_channel += parent->rxchan_per_port[i];
4487 first_tx_channel += parent->txchan_per_port[i];
4488 }
4489
4490 num_rx_rings = parent->rxchan_per_port[port];
4491 num_tx_rings = parent->txchan_per_port[port];
4492
4493 rx_rings = kcalloc(num_rx_rings, sizeof(struct rx_ring_info),
4494 GFP_KERNEL);
4495 err = -ENOMEM;
4496 if (!rx_rings)
4497 goto out_err;
4498
4499 np->num_rx_rings = num_rx_rings;
4500 smp_wmb();
4501 np->rx_rings = rx_rings;
4502
4503 netif_set_real_num_rx_queues(np->dev, num_rx_rings);
4504
4505 for (i = 0; i < np->num_rx_rings; i++) {
4506 struct rx_ring_info *rp = &np->rx_rings[i];
4507
4508 rp->np = np;
4509 rp->rx_channel = first_rx_channel + i;
4510
4511 err = niu_alloc_rx_ring_info(np, rp);
4512 if (err)
4513 goto out_err;
4514
4515 niu_size_rbr(np, rp);
4516
4517 /* XXX better defaults, configurable, etc... XXX */
4518 rp->nonsyn_window = 64;
4519 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4520 rp->syn_window = 64;
4521 rp->syn_threshold = rp->rcr_table_size - 64;
4522 rp->rcr_pkt_threshold = 16;
4523 rp->rcr_timeout = 8;
4524 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4525 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4526 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4527
4528 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4529 if (err)
4530 return err;
4531 }
4532
4533 tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info),
4534 GFP_KERNEL);
4535 err = -ENOMEM;
4536 if (!tx_rings)
4537 goto out_err;
4538
4539 np->num_tx_rings = num_tx_rings;
4540 smp_wmb();
4541 np->tx_rings = tx_rings;
4542
4543 netif_set_real_num_tx_queues(np->dev, num_tx_rings);
4544
4545 for (i = 0; i < np->num_tx_rings; i++) {
4546 struct tx_ring_info *rp = &np->tx_rings[i];
4547
4548 rp->np = np;
4549 rp->tx_channel = first_tx_channel + i;
4550
4551 err = niu_alloc_tx_ring_info(np, rp);
4552 if (err)
4553 goto out_err;
4554 }
4555
4556 return 0;
4557
4558 out_err:
4559 niu_free_channels(np);
4560 return err;
4561 }
4562
4563 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4564 {
4565 int limit = 1000;
4566
4567 while (--limit > 0) {
4568 u64 val = nr64(TX_CS(channel));
4569 if (val & TX_CS_SNG_STATE)
4570 return 0;
4571 }
4572 return -ENODEV;
4573 }
4574
4575 static int niu_tx_channel_stop(struct niu *np, int channel)
4576 {
4577 u64 val = nr64(TX_CS(channel));
4578
4579 val |= TX_CS_STOP_N_GO;
4580 nw64(TX_CS(channel), val);
4581
4582 return niu_tx_cs_sng_poll(np, channel);
4583 }
4584
4585 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4586 {
4587 int limit = 1000;
4588
4589 while (--limit > 0) {
4590 u64 val = nr64(TX_CS(channel));
4591 if (!(val & TX_CS_RST))
4592 return 0;
4593 }
4594 return -ENODEV;
4595 }
4596
4597 static int niu_tx_channel_reset(struct niu *np, int channel)
4598 {
4599 u64 val = nr64(TX_CS(channel));
4600 int err;
4601
4602 val |= TX_CS_RST;
4603 nw64(TX_CS(channel), val);
4604
4605 err = niu_tx_cs_reset_poll(np, channel);
4606 if (!err)
4607 nw64(TX_RING_KICK(channel), 0);
4608
4609 return err;
4610 }
4611
4612 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4613 {
4614 u64 val;
4615
4616 nw64(TX_LOG_MASK1(channel), 0);
4617 nw64(TX_LOG_VAL1(channel), 0);
4618 nw64(TX_LOG_MASK2(channel), 0);
4619 nw64(TX_LOG_VAL2(channel), 0);
4620 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4621 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4622 nw64(TX_LOG_PAGE_HDL(channel), 0);
4623
4624 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4625 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4626 nw64(TX_LOG_PAGE_VLD(channel), val);
4627
4628 /* XXX TXDMA 32bit mode? XXX */
4629
4630 return 0;
4631 }
4632
4633 static void niu_txc_enable_port(struct niu *np, int on)
4634 {
4635 unsigned long flags;
4636 u64 val, mask;
4637
4638 niu_lock_parent(np, flags);
4639 val = nr64(TXC_CONTROL);
4640 mask = (u64)1 << np->port;
4641 if (on) {
4642 val |= TXC_CONTROL_ENABLE | mask;
4643 } else {
4644 val &= ~mask;
4645 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4646 val &= ~TXC_CONTROL_ENABLE;
4647 }
4648 nw64(TXC_CONTROL, val);
4649 niu_unlock_parent(np, flags);
4650 }
4651
4652 static void niu_txc_set_imask(struct niu *np, u64 imask)
4653 {
4654 unsigned long flags;
4655 u64 val;
4656
4657 niu_lock_parent(np, flags);
4658 val = nr64(TXC_INT_MASK);
4659 val &= ~TXC_INT_MASK_VAL(np->port);
4660 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4661 niu_unlock_parent(np, flags);
4662 }
4663
4664 static void niu_txc_port_dma_enable(struct niu *np, int on)
4665 {
4666 u64 val = 0;
4667
4668 if (on) {
4669 int i;
4670
4671 for (i = 0; i < np->num_tx_rings; i++)
4672 val |= (1 << np->tx_rings[i].tx_channel);
4673 }
4674 nw64(TXC_PORT_DMA(np->port), val);
4675 }
4676
4677 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4678 {
4679 int err, channel = rp->tx_channel;
4680 u64 val, ring_len;
4681
4682 err = niu_tx_channel_stop(np, channel);
4683 if (err)
4684 return err;
4685
4686 err = niu_tx_channel_reset(np, channel);
4687 if (err)
4688 return err;
4689
4690 err = niu_tx_channel_lpage_init(np, channel);
4691 if (err)
4692 return err;
4693
4694 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4695 nw64(TX_ENT_MSK(channel), 0);
4696
4697 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4698 TX_RNG_CFIG_STADDR)) {
4699 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4700 channel, (unsigned long long)rp->descr_dma);
4701 return -EINVAL;
4702 }
4703
4704 /* The length field in TX_RNG_CFIG is measured in 64-byte
4705 * blocks. rp->pending is the number of TX descriptors in
4706 * our ring, 8 bytes each, thus we divide by 8 bytes more
4707 * to get the proper value the chip wants.
4708 */
4709 ring_len = (rp->pending / 8);
4710
4711 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4712 rp->descr_dma);
4713 nw64(TX_RNG_CFIG(channel), val);
4714
4715 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4716 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4717 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4718 channel, (unsigned long long)rp->mbox_dma);
4719 return -EINVAL;
4720 }
4721 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4722 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4723
4724 nw64(TX_CS(channel), 0);
4725
4726 rp->last_pkt_cnt = 0;
4727
4728 return 0;
4729 }
4730
4731 static void niu_init_rdc_groups(struct niu *np)
4732 {
4733 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4734 int i, first_table_num = tp->first_table_num;
4735
4736 for (i = 0; i < tp->num_tables; i++) {
4737 struct rdc_table *tbl = &tp->tables[i];
4738 int this_table = first_table_num + i;
4739 int slot;
4740
4741 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4742 nw64(RDC_TBL(this_table, slot),
4743 tbl->rxdma_channel[slot]);
4744 }
4745
4746 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4747 }
4748
4749 static void niu_init_drr_weight(struct niu *np)
4750 {
4751 int type = phy_decode(np->parent->port_phy, np->port);
4752 u64 val;
4753
4754 switch (type) {
4755 case PORT_TYPE_10G:
4756 val = PT_DRR_WEIGHT_DEFAULT_10G;
4757 break;
4758
4759 case PORT_TYPE_1G:
4760 default:
4761 val = PT_DRR_WEIGHT_DEFAULT_1G;
4762 break;
4763 }
4764 nw64(PT_DRR_WT(np->port), val);
4765 }
4766
4767 static int niu_init_hostinfo(struct niu *np)
4768 {
4769 struct niu_parent *parent = np->parent;
4770 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4771 int i, err, num_alt = niu_num_alt_addr(np);
4772 int first_rdc_table = tp->first_table_num;
4773
4774 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4775 if (err)
4776 return err;
4777
4778 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4779 if (err)
4780 return err;
4781
4782 for (i = 0; i < num_alt; i++) {
4783 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4784 if (err)
4785 return err;
4786 }
4787
4788 return 0;
4789 }
4790
4791 static int niu_rx_channel_reset(struct niu *np, int channel)
4792 {
4793 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4794 RXDMA_CFIG1_RST, 1000, 10,
4795 "RXDMA_CFIG1");
4796 }
4797
4798 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4799 {
4800 u64 val;
4801
4802 nw64(RX_LOG_MASK1(channel), 0);
4803 nw64(RX_LOG_VAL1(channel), 0);
4804 nw64(RX_LOG_MASK2(channel), 0);
4805 nw64(RX_LOG_VAL2(channel), 0);
4806 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4807 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4808 nw64(RX_LOG_PAGE_HDL(channel), 0);
4809
4810 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4811 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4812 nw64(RX_LOG_PAGE_VLD(channel), val);
4813
4814 return 0;
4815 }
4816
4817 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4818 {
4819 u64 val;
4820
4821 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4822 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4823 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4824 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4825 nw64(RDC_RED_PARA(rp->rx_channel), val);
4826 }
4827
4828 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4829 {
4830 u64 val = 0;
4831
4832 *ret = 0;
4833 switch (rp->rbr_block_size) {
4834 case 4 * 1024:
4835 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4836 break;
4837 case 8 * 1024:
4838 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4839 break;
4840 case 16 * 1024:
4841 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4842 break;
4843 case 32 * 1024:
4844 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4845 break;
4846 default:
4847 return -EINVAL;
4848 }
4849 val |= RBR_CFIG_B_VLD2;
4850 switch (rp->rbr_sizes[2]) {
4851 case 2 * 1024:
4852 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4853 break;
4854 case 4 * 1024:
4855 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4856 break;
4857 case 8 * 1024:
4858 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4859 break;
4860 case 16 * 1024:
4861 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4862 break;
4863
4864 default:
4865 return -EINVAL;
4866 }
4867 val |= RBR_CFIG_B_VLD1;
4868 switch (rp->rbr_sizes[1]) {
4869 case 1 * 1024:
4870 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4871 break;
4872 case 2 * 1024:
4873 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4874 break;
4875 case 4 * 1024:
4876 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4877 break;
4878 case 8 * 1024:
4879 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4880 break;
4881
4882 default:
4883 return -EINVAL;
4884 }
4885 val |= RBR_CFIG_B_VLD0;
4886 switch (rp->rbr_sizes[0]) {
4887 case 256:
4888 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4889 break;
4890 case 512:
4891 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4892 break;
4893 case 1 * 1024:
4894 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4895 break;
4896 case 2 * 1024:
4897 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4898 break;
4899
4900 default:
4901 return -EINVAL;
4902 }
4903
4904 *ret = val;
4905 return 0;
4906 }
4907
4908 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4909 {
4910 u64 val = nr64(RXDMA_CFIG1(channel));
4911 int limit;
4912
4913 if (on)
4914 val |= RXDMA_CFIG1_EN;
4915 else
4916 val &= ~RXDMA_CFIG1_EN;
4917 nw64(RXDMA_CFIG1(channel), val);
4918
4919 limit = 1000;
4920 while (--limit > 0) {
4921 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4922 break;
4923 udelay(10);
4924 }
4925 if (limit <= 0)
4926 return -ENODEV;
4927 return 0;
4928 }
4929
4930 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4931 {
4932 int err, channel = rp->rx_channel;
4933 u64 val;
4934
4935 err = niu_rx_channel_reset(np, channel);
4936 if (err)
4937 return err;
4938
4939 err = niu_rx_channel_lpage_init(np, channel);
4940 if (err)
4941 return err;
4942
4943 niu_rx_channel_wred_init(np, rp);
4944
4945 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4946 nw64(RX_DMA_CTL_STAT(channel),
4947 (RX_DMA_CTL_STAT_MEX |
4948 RX_DMA_CTL_STAT_RCRTHRES |
4949 RX_DMA_CTL_STAT_RCRTO |
4950 RX_DMA_CTL_STAT_RBR_EMPTY));
4951 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4952 nw64(RXDMA_CFIG2(channel),
4953 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4954 RXDMA_CFIG2_FULL_HDR));
4955 nw64(RBR_CFIG_A(channel),
4956 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4957 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4958 err = niu_compute_rbr_cfig_b(rp, &val);
4959 if (err)
4960 return err;
4961 nw64(RBR_CFIG_B(channel), val);
4962 nw64(RCRCFIG_A(channel),
4963 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4964 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4965 nw64(RCRCFIG_B(channel),
4966 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4967 RCRCFIG_B_ENTOUT |
4968 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4969
4970 err = niu_enable_rx_channel(np, channel, 1);
4971 if (err)
4972 return err;
4973
4974 nw64(RBR_KICK(channel), rp->rbr_index);
4975
4976 val = nr64(RX_DMA_CTL_STAT(channel));
4977 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4978 nw64(RX_DMA_CTL_STAT(channel), val);
4979
4980 return 0;
4981 }
4982
4983 static int niu_init_rx_channels(struct niu *np)
4984 {
4985 unsigned long flags;
4986 u64 seed = jiffies_64;
4987 int err, i;
4988
4989 niu_lock_parent(np, flags);
4990 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4991 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4992 niu_unlock_parent(np, flags);
4993
4994 /* XXX RXDMA 32bit mode? XXX */
4995
4996 niu_init_rdc_groups(np);
4997 niu_init_drr_weight(np);
4998
4999 err = niu_init_hostinfo(np);
5000 if (err)
5001 return err;
5002
5003 for (i = 0; i < np->num_rx_rings; i++) {
5004 struct rx_ring_info *rp = &np->rx_rings[i];
5005
5006 err = niu_init_one_rx_channel(np, rp);
5007 if (err)
5008 return err;
5009 }
5010
5011 return 0;
5012 }
5013
5014 static int niu_set_ip_frag_rule(struct niu *np)
5015 {
5016 struct niu_parent *parent = np->parent;
5017 struct niu_classifier *cp = &np->clas;
5018 struct niu_tcam_entry *tp;
5019 int index, err;
5020
5021 index = cp->tcam_top;
5022 tp = &parent->tcam[index];
5023
5024 /* Note that the noport bit is the same in both ipv4 and
5025 * ipv6 format TCAM entries.
5026 */
5027 memset(tp, 0, sizeof(*tp));
5028 tp->key[1] = TCAM_V4KEY1_NOPORT;
5029 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5030 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5031 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5032 err = tcam_write(np, index, tp->key, tp->key_mask);
5033 if (err)
5034 return err;
5035 err = tcam_assoc_write(np, index, tp->assoc_data);
5036 if (err)
5037 return err;
5038 tp->valid = 1;
5039 cp->tcam_valid_entries++;
5040
5041 return 0;
5042 }
5043
5044 static int niu_init_classifier_hw(struct niu *np)
5045 {
5046 struct niu_parent *parent = np->parent;
5047 struct niu_classifier *cp = &np->clas;
5048 int i, err;
5049
5050 nw64(H1POLY, cp->h1_init);
5051 nw64(H2POLY, cp->h2_init);
5052
5053 err = niu_init_hostinfo(np);
5054 if (err)
5055 return err;
5056
5057 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5058 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5059
5060 vlan_tbl_write(np, i, np->port,
5061 vp->vlan_pref, vp->rdc_num);
5062 }
5063
5064 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5065 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5066
5067 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5068 ap->rdc_num, ap->mac_pref);
5069 if (err)
5070 return err;
5071 }
5072
5073 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5074 int index = i - CLASS_CODE_USER_PROG1;
5075
5076 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5077 if (err)
5078 return err;
5079 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5080 if (err)
5081 return err;
5082 }
5083
5084 err = niu_set_ip_frag_rule(np);
5085 if (err)
5086 return err;
5087
5088 tcam_enable(np, 1);
5089
5090 return 0;
5091 }
5092
5093 static int niu_zcp_write(struct niu *np, int index, u64 *data)
5094 {
5095 nw64(ZCP_RAM_DATA0, data[0]);
5096 nw64(ZCP_RAM_DATA1, data[1]);
5097 nw64(ZCP_RAM_DATA2, data[2]);
5098 nw64(ZCP_RAM_DATA3, data[3]);
5099 nw64(ZCP_RAM_DATA4, data[4]);
5100 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5101 nw64(ZCP_RAM_ACC,
5102 (ZCP_RAM_ACC_WRITE |
5103 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5104 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5105
5106 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5107 1000, 100);
5108 }
5109
5110 static int niu_zcp_read(struct niu *np, int index, u64 *data)
5111 {
5112 int err;
5113
5114 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5115 1000, 100);
5116 if (err) {
5117 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5118 (unsigned long long)nr64(ZCP_RAM_ACC));
5119 return err;
5120 }
5121
5122 nw64(ZCP_RAM_ACC,
5123 (ZCP_RAM_ACC_READ |
5124 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5125 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5126
5127 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5128 1000, 100);
5129 if (err) {
5130 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5131 (unsigned long long)nr64(ZCP_RAM_ACC));
5132 return err;
5133 }
5134
5135 data[0] = nr64(ZCP_RAM_DATA0);
5136 data[1] = nr64(ZCP_RAM_DATA1);
5137 data[2] = nr64(ZCP_RAM_DATA2);
5138 data[3] = nr64(ZCP_RAM_DATA3);
5139 data[4] = nr64(ZCP_RAM_DATA4);
5140
5141 return 0;
5142 }
5143
5144 static void niu_zcp_cfifo_reset(struct niu *np)
5145 {
5146 u64 val = nr64(RESET_CFIFO);
5147
5148 val |= RESET_CFIFO_RST(np->port);
5149 nw64(RESET_CFIFO, val);
5150 udelay(10);
5151
5152 val &= ~RESET_CFIFO_RST(np->port);
5153 nw64(RESET_CFIFO, val);
5154 }
5155
5156 static int niu_init_zcp(struct niu *np)
5157 {
5158 u64 data[5], rbuf[5];
5159 int i, max, err;
5160
5161 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5162 if (np->port == 0 || np->port == 1)
5163 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5164 else
5165 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5166 } else
5167 max = NIU_CFIFO_ENTRIES;
5168
5169 data[0] = 0;
5170 data[1] = 0;
5171 data[2] = 0;
5172 data[3] = 0;
5173 data[4] = 0;
5174
5175 for (i = 0; i < max; i++) {
5176 err = niu_zcp_write(np, i, data);
5177 if (err)
5178 return err;
5179 err = niu_zcp_read(np, i, rbuf);
5180 if (err)
5181 return err;
5182 }
5183
5184 niu_zcp_cfifo_reset(np);
5185 nw64(CFIFO_ECC(np->port), 0);
5186 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5187 (void) nr64(ZCP_INT_STAT);
5188 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5189
5190 return 0;
5191 }
5192
5193 static void niu_ipp_write(struct niu *np, int index, u64 *data)
5194 {
5195 u64 val = nr64_ipp(IPP_CFIG);
5196
5197 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5198 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5199 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5200 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5201 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5202 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5203 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5204 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5205 }
5206
5207 static void niu_ipp_read(struct niu *np, int index, u64 *data)
5208 {
5209 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5210 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5211 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5212 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5213 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5214 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5215 }
5216
5217 static int niu_ipp_reset(struct niu *np)
5218 {
5219 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5220 1000, 100, "IPP_CFIG");
5221 }
5222
5223 static int niu_init_ipp(struct niu *np)
5224 {
5225 u64 data[5], rbuf[5], val;
5226 int i, max, err;
5227
5228 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5229 if (np->port == 0 || np->port == 1)
5230 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5231 else
5232 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5233 } else
5234 max = NIU_DFIFO_ENTRIES;
5235
5236 data[0] = 0;
5237 data[1] = 0;
5238 data[2] = 0;
5239 data[3] = 0;
5240 data[4] = 0;
5241
5242 for (i = 0; i < max; i++) {
5243 niu_ipp_write(np, i, data);
5244 niu_ipp_read(np, i, rbuf);
5245 }
5246
5247 (void) nr64_ipp(IPP_INT_STAT);
5248 (void) nr64_ipp(IPP_INT_STAT);
5249
5250 err = niu_ipp_reset(np);
5251 if (err)
5252 return err;
5253
5254 (void) nr64_ipp(IPP_PKT_DIS);
5255 (void) nr64_ipp(IPP_BAD_CS_CNT);
5256 (void) nr64_ipp(IPP_ECC);
5257
5258 (void) nr64_ipp(IPP_INT_STAT);
5259
5260 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5261
5262 val = nr64_ipp(IPP_CFIG);
5263 val &= ~IPP_CFIG_IP_MAX_PKT;
5264 val |= (IPP_CFIG_IPP_ENABLE |
5265 IPP_CFIG_DFIFO_ECC_EN |
5266 IPP_CFIG_DROP_BAD_CRC |
5267 IPP_CFIG_CKSUM_EN |
5268 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5269 nw64_ipp(IPP_CFIG, val);
5270
5271 return 0;
5272 }
5273
5274 static void niu_handle_led(struct niu *np, int status)
5275 {
5276 u64 val;
5277 val = nr64_mac(XMAC_CONFIG);
5278
5279 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5280 (np->flags & NIU_FLAGS_FIBER) != 0) {
5281 if (status) {
5282 val |= XMAC_CONFIG_LED_POLARITY;
5283 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5284 } else {
5285 val |= XMAC_CONFIG_FORCE_LED_ON;
5286 val &= ~XMAC_CONFIG_LED_POLARITY;
5287 }
5288 }
5289
5290 nw64_mac(XMAC_CONFIG, val);
5291 }
5292
5293 static void niu_init_xif_xmac(struct niu *np)
5294 {
5295 struct niu_link_config *lp = &np->link_config;
5296 u64 val;
5297
5298 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5299 val = nr64(MIF_CONFIG);
5300 val |= MIF_CONFIG_ATCA_GE;
5301 nw64(MIF_CONFIG, val);
5302 }
5303
5304 val = nr64_mac(XMAC_CONFIG);
5305 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5306
5307 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5308
5309 if (lp->loopback_mode == LOOPBACK_MAC) {
5310 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5311 val |= XMAC_CONFIG_LOOPBACK;
5312 } else {
5313 val &= ~XMAC_CONFIG_LOOPBACK;
5314 }
5315
5316 if (np->flags & NIU_FLAGS_10G) {
5317 val &= ~XMAC_CONFIG_LFS_DISABLE;
5318 } else {
5319 val |= XMAC_CONFIG_LFS_DISABLE;
5320 if (!(np->flags & NIU_FLAGS_FIBER) &&
5321 !(np->flags & NIU_FLAGS_XCVR_SERDES))
5322 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5323 else
5324 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5325 }
5326
5327 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5328
5329 if (lp->active_speed == SPEED_100)
5330 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5331 else
5332 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5333
5334 nw64_mac(XMAC_CONFIG, val);
5335
5336 val = nr64_mac(XMAC_CONFIG);
5337 val &= ~XMAC_CONFIG_MODE_MASK;
5338 if (np->flags & NIU_FLAGS_10G) {
5339 val |= XMAC_CONFIG_MODE_XGMII;
5340 } else {
5341 if (lp->active_speed == SPEED_1000)
5342 val |= XMAC_CONFIG_MODE_GMII;
5343 else
5344 val |= XMAC_CONFIG_MODE_MII;
5345 }
5346
5347 nw64_mac(XMAC_CONFIG, val);
5348 }
5349
5350 static void niu_init_xif_bmac(struct niu *np)
5351 {
5352 struct niu_link_config *lp = &np->link_config;
5353 u64 val;
5354
5355 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5356
5357 if (lp->loopback_mode == LOOPBACK_MAC)
5358 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5359 else
5360 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5361
5362 if (lp->active_speed == SPEED_1000)
5363 val |= BMAC_XIF_CONFIG_GMII_MODE;
5364 else
5365 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5366
5367 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5368 BMAC_XIF_CONFIG_LED_POLARITY);
5369
5370 if (!(np->flags & NIU_FLAGS_10G) &&
5371 !(np->flags & NIU_FLAGS_FIBER) &&
5372 lp->active_speed == SPEED_100)
5373 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5374 else
5375 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5376
5377 nw64_mac(BMAC_XIF_CONFIG, val);
5378 }
5379
5380 static void niu_init_xif(struct niu *np)
5381 {
5382 if (np->flags & NIU_FLAGS_XMAC)
5383 niu_init_xif_xmac(np);
5384 else
5385 niu_init_xif_bmac(np);
5386 }
5387
5388 static void niu_pcs_mii_reset(struct niu *np)
5389 {
5390 int limit = 1000;
5391 u64 val = nr64_pcs(PCS_MII_CTL);
5392 val |= PCS_MII_CTL_RST;
5393 nw64_pcs(PCS_MII_CTL, val);
5394 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5395 udelay(100);
5396 val = nr64_pcs(PCS_MII_CTL);
5397 }
5398 }
5399
5400 static void niu_xpcs_reset(struct niu *np)
5401 {
5402 int limit = 1000;
5403 u64 val = nr64_xpcs(XPCS_CONTROL1);
5404 val |= XPCS_CONTROL1_RESET;
5405 nw64_xpcs(XPCS_CONTROL1, val);
5406 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5407 udelay(100);
5408 val = nr64_xpcs(XPCS_CONTROL1);
5409 }
5410 }
5411
5412 static int niu_init_pcs(struct niu *np)
5413 {
5414 struct niu_link_config *lp = &np->link_config;
5415 u64 val;
5416
5417 switch (np->flags & (NIU_FLAGS_10G |
5418 NIU_FLAGS_FIBER |
5419 NIU_FLAGS_XCVR_SERDES)) {
5420 case NIU_FLAGS_FIBER:
5421 /* 1G fiber */
5422 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5423 nw64_pcs(PCS_DPATH_MODE, 0);
5424 niu_pcs_mii_reset(np);
5425 break;
5426
5427 case NIU_FLAGS_10G:
5428 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5429 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5430 /* 10G SERDES */
5431 if (!(np->flags & NIU_FLAGS_XMAC))
5432 return -EINVAL;
5433
5434 /* 10G copper or fiber */
5435 val = nr64_mac(XMAC_CONFIG);
5436 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5437 nw64_mac(XMAC_CONFIG, val);
5438
5439 niu_xpcs_reset(np);
5440
5441 val = nr64_xpcs(XPCS_CONTROL1);
5442 if (lp->loopback_mode == LOOPBACK_PHY)
5443 val |= XPCS_CONTROL1_LOOPBACK;
5444 else
5445 val &= ~XPCS_CONTROL1_LOOPBACK;
5446 nw64_xpcs(XPCS_CONTROL1, val);
5447
5448 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5449 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5450 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5451 break;
5452
5453
5454 case NIU_FLAGS_XCVR_SERDES:
5455 /* 1G SERDES */
5456 niu_pcs_mii_reset(np);
5457 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5458 nw64_pcs(PCS_DPATH_MODE, 0);
5459 break;
5460
5461 case 0:
5462 /* 1G copper */
5463 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5464 /* 1G RGMII FIBER */
5465 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5466 niu_pcs_mii_reset(np);
5467 break;
5468
5469 default:
5470 return -EINVAL;
5471 }
5472
5473 return 0;
5474 }
5475
5476 static int niu_reset_tx_xmac(struct niu *np)
5477 {
5478 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5479 (XTXMAC_SW_RST_REG_RS |
5480 XTXMAC_SW_RST_SOFT_RST),
5481 1000, 100, "XTXMAC_SW_RST");
5482 }
5483
5484 static int niu_reset_tx_bmac(struct niu *np)
5485 {
5486 int limit;
5487
5488 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5489 limit = 1000;
5490 while (--limit >= 0) {
5491 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5492 break;
5493 udelay(100);
5494 }
5495 if (limit < 0) {
5496 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5497 np->port,
5498 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5499 return -ENODEV;
5500 }
5501
5502 return 0;
5503 }
5504
5505 static int niu_reset_tx_mac(struct niu *np)
5506 {
5507 if (np->flags & NIU_FLAGS_XMAC)
5508 return niu_reset_tx_xmac(np);
5509 else
5510 return niu_reset_tx_bmac(np);
5511 }
5512
5513 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5514 {
5515 u64 val;
5516
5517 val = nr64_mac(XMAC_MIN);
5518 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5519 XMAC_MIN_RX_MIN_PKT_SIZE);
5520 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5521 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5522 nw64_mac(XMAC_MIN, val);
5523
5524 nw64_mac(XMAC_MAX, max);
5525
5526 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5527
5528 val = nr64_mac(XMAC_IPG);
5529 if (np->flags & NIU_FLAGS_10G) {
5530 val &= ~XMAC_IPG_IPG_XGMII;
5531 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5532 } else {
5533 val &= ~XMAC_IPG_IPG_MII_GMII;
5534 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5535 }
5536 nw64_mac(XMAC_IPG, val);
5537
5538 val = nr64_mac(XMAC_CONFIG);
5539 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5540 XMAC_CONFIG_STRETCH_MODE |
5541 XMAC_CONFIG_VAR_MIN_IPG_EN |
5542 XMAC_CONFIG_TX_ENABLE);
5543 nw64_mac(XMAC_CONFIG, val);
5544
5545 nw64_mac(TXMAC_FRM_CNT, 0);
5546 nw64_mac(TXMAC_BYTE_CNT, 0);
5547 }
5548
5549 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5550 {
5551 u64 val;
5552
5553 nw64_mac(BMAC_MIN_FRAME, min);
5554 nw64_mac(BMAC_MAX_FRAME, max);
5555
5556 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5557 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5558 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5559
5560 val = nr64_mac(BTXMAC_CONFIG);
5561 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5562 BTXMAC_CONFIG_ENABLE);
5563 nw64_mac(BTXMAC_CONFIG, val);
5564 }
5565
5566 static void niu_init_tx_mac(struct niu *np)
5567 {
5568 u64 min, max;
5569
5570 min = 64;
5571 if (np->dev->mtu > ETH_DATA_LEN)
5572 max = 9216;
5573 else
5574 max = 1522;
5575
5576 /* The XMAC_MIN register only accepts values for TX min which
5577 * have the low 3 bits cleared.
5578 */
5579 BUG_ON(min & 0x7);
5580
5581 if (np->flags & NIU_FLAGS_XMAC)
5582 niu_init_tx_xmac(np, min, max);
5583 else
5584 niu_init_tx_bmac(np, min, max);
5585 }
5586
5587 static int niu_reset_rx_xmac(struct niu *np)
5588 {
5589 int limit;
5590
5591 nw64_mac(XRXMAC_SW_RST,
5592 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5593 limit = 1000;
5594 while (--limit >= 0) {
5595 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5596 XRXMAC_SW_RST_SOFT_RST)))
5597 break;
5598 udelay(100);
5599 }
5600 if (limit < 0) {
5601 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5602 np->port,
5603 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5604 return -ENODEV;
5605 }
5606
5607 return 0;
5608 }
5609
5610 static int niu_reset_rx_bmac(struct niu *np)
5611 {
5612 int limit;
5613
5614 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5615 limit = 1000;
5616 while (--limit >= 0) {
5617 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5618 break;
5619 udelay(100);
5620 }
5621 if (limit < 0) {
5622 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5623 np->port,
5624 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5625 return -ENODEV;
5626 }
5627
5628 return 0;
5629 }
5630
5631 static int niu_reset_rx_mac(struct niu *np)
5632 {
5633 if (np->flags & NIU_FLAGS_XMAC)
5634 return niu_reset_rx_xmac(np);
5635 else
5636 return niu_reset_rx_bmac(np);
5637 }
5638
5639 static void niu_init_rx_xmac(struct niu *np)
5640 {
5641 struct niu_parent *parent = np->parent;
5642 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5643 int first_rdc_table = tp->first_table_num;
5644 unsigned long i;
5645 u64 val;
5646
5647 nw64_mac(XMAC_ADD_FILT0, 0);
5648 nw64_mac(XMAC_ADD_FILT1, 0);
5649 nw64_mac(XMAC_ADD_FILT2, 0);
5650 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5651 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5652 for (i = 0; i < MAC_NUM_HASH; i++)
5653 nw64_mac(XMAC_HASH_TBL(i), 0);
5654 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5655 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5656 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5657
5658 val = nr64_mac(XMAC_CONFIG);
5659 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5660 XMAC_CONFIG_PROMISCUOUS |
5661 XMAC_CONFIG_PROMISC_GROUP |
5662 XMAC_CONFIG_ERR_CHK_DIS |
5663 XMAC_CONFIG_RX_CRC_CHK_DIS |
5664 XMAC_CONFIG_RESERVED_MULTICAST |
5665 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5666 XMAC_CONFIG_ADDR_FILTER_EN |
5667 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5668 XMAC_CONFIG_STRIP_CRC |
5669 XMAC_CONFIG_PASS_FLOW_CTRL |
5670 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5671 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5672 nw64_mac(XMAC_CONFIG, val);
5673
5674 nw64_mac(RXMAC_BT_CNT, 0);
5675 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5676 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5677 nw64_mac(RXMAC_FRAG_CNT, 0);
5678 nw64_mac(RXMAC_HIST_CNT1, 0);
5679 nw64_mac(RXMAC_HIST_CNT2, 0);
5680 nw64_mac(RXMAC_HIST_CNT3, 0);
5681 nw64_mac(RXMAC_HIST_CNT4, 0);
5682 nw64_mac(RXMAC_HIST_CNT5, 0);
5683 nw64_mac(RXMAC_HIST_CNT6, 0);
5684 nw64_mac(RXMAC_HIST_CNT7, 0);
5685 nw64_mac(RXMAC_MPSZER_CNT, 0);
5686 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5687 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5688 nw64_mac(LINK_FAULT_CNT, 0);
5689 }
5690
5691 static void niu_init_rx_bmac(struct niu *np)
5692 {
5693 struct niu_parent *parent = np->parent;
5694 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5695 int first_rdc_table = tp->first_table_num;
5696 unsigned long i;
5697 u64 val;
5698
5699 nw64_mac(BMAC_ADD_FILT0, 0);
5700 nw64_mac(BMAC_ADD_FILT1, 0);
5701 nw64_mac(BMAC_ADD_FILT2, 0);
5702 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5703 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5704 for (i = 0; i < MAC_NUM_HASH; i++)
5705 nw64_mac(BMAC_HASH_TBL(i), 0);
5706 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5707 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5708 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5709
5710 val = nr64_mac(BRXMAC_CONFIG);
5711 val &= ~(BRXMAC_CONFIG_ENABLE |
5712 BRXMAC_CONFIG_STRIP_PAD |
5713 BRXMAC_CONFIG_STRIP_FCS |
5714 BRXMAC_CONFIG_PROMISC |
5715 BRXMAC_CONFIG_PROMISC_GRP |
5716 BRXMAC_CONFIG_ADDR_FILT_EN |
5717 BRXMAC_CONFIG_DISCARD_DIS);
5718 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5719 nw64_mac(BRXMAC_CONFIG, val);
5720
5721 val = nr64_mac(BMAC_ADDR_CMPEN);
5722 val |= BMAC_ADDR_CMPEN_EN0;
5723 nw64_mac(BMAC_ADDR_CMPEN, val);
5724 }
5725
5726 static void niu_init_rx_mac(struct niu *np)
5727 {
5728 niu_set_primary_mac(np, np->dev->dev_addr);
5729
5730 if (np->flags & NIU_FLAGS_XMAC)
5731 niu_init_rx_xmac(np);
5732 else
5733 niu_init_rx_bmac(np);
5734 }
5735
5736 static void niu_enable_tx_xmac(struct niu *np, int on)
5737 {
5738 u64 val = nr64_mac(XMAC_CONFIG);
5739
5740 if (on)
5741 val |= XMAC_CONFIG_TX_ENABLE;
5742 else
5743 val &= ~XMAC_CONFIG_TX_ENABLE;
5744 nw64_mac(XMAC_CONFIG, val);
5745 }
5746
5747 static void niu_enable_tx_bmac(struct niu *np, int on)
5748 {
5749 u64 val = nr64_mac(BTXMAC_CONFIG);
5750
5751 if (on)
5752 val |= BTXMAC_CONFIG_ENABLE;
5753 else
5754 val &= ~BTXMAC_CONFIG_ENABLE;
5755 nw64_mac(BTXMAC_CONFIG, val);
5756 }
5757
5758 static void niu_enable_tx_mac(struct niu *np, int on)
5759 {
5760 if (np->flags & NIU_FLAGS_XMAC)
5761 niu_enable_tx_xmac(np, on);
5762 else
5763 niu_enable_tx_bmac(np, on);
5764 }
5765
5766 static void niu_enable_rx_xmac(struct niu *np, int on)
5767 {
5768 u64 val = nr64_mac(XMAC_CONFIG);
5769
5770 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5771 XMAC_CONFIG_PROMISCUOUS);
5772
5773 if (np->flags & NIU_FLAGS_MCAST)
5774 val |= XMAC_CONFIG_HASH_FILTER_EN;
5775 if (np->flags & NIU_FLAGS_PROMISC)
5776 val |= XMAC_CONFIG_PROMISCUOUS;
5777
5778 if (on)
5779 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5780 else
5781 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5782 nw64_mac(XMAC_CONFIG, val);
5783 }
5784
5785 static void niu_enable_rx_bmac(struct niu *np, int on)
5786 {
5787 u64 val = nr64_mac(BRXMAC_CONFIG);
5788
5789 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5790 BRXMAC_CONFIG_PROMISC);
5791
5792 if (np->flags & NIU_FLAGS_MCAST)
5793 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5794 if (np->flags & NIU_FLAGS_PROMISC)
5795 val |= BRXMAC_CONFIG_PROMISC;
5796
5797 if (on)
5798 val |= BRXMAC_CONFIG_ENABLE;
5799 else
5800 val &= ~BRXMAC_CONFIG_ENABLE;
5801 nw64_mac(BRXMAC_CONFIG, val);
5802 }
5803
5804 static void niu_enable_rx_mac(struct niu *np, int on)
5805 {
5806 if (np->flags & NIU_FLAGS_XMAC)
5807 niu_enable_rx_xmac(np, on);
5808 else
5809 niu_enable_rx_bmac(np, on);
5810 }
5811
5812 static int niu_init_mac(struct niu *np)
5813 {
5814 int err;
5815
5816 niu_init_xif(np);
5817 err = niu_init_pcs(np);
5818 if (err)
5819 return err;
5820
5821 err = niu_reset_tx_mac(np);
5822 if (err)
5823 return err;
5824 niu_init_tx_mac(np);
5825 err = niu_reset_rx_mac(np);
5826 if (err)
5827 return err;
5828 niu_init_rx_mac(np);
5829
5830 /* This looks hookey but the RX MAC reset we just did will
5831 * undo some of the state we setup in niu_init_tx_mac() so we
5832 * have to call it again. In particular, the RX MAC reset will
5833 * set the XMAC_MAX register back to it's default value.
5834 */
5835 niu_init_tx_mac(np);
5836 niu_enable_tx_mac(np, 1);
5837
5838 niu_enable_rx_mac(np, 1);
5839
5840 return 0;
5841 }
5842
5843 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5844 {
5845 (void) niu_tx_channel_stop(np, rp->tx_channel);
5846 }
5847
5848 static void niu_stop_tx_channels(struct niu *np)
5849 {
5850 int i;
5851
5852 for (i = 0; i < np->num_tx_rings; i++) {
5853 struct tx_ring_info *rp = &np->tx_rings[i];
5854
5855 niu_stop_one_tx_channel(np, rp);
5856 }
5857 }
5858
5859 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5860 {
5861 (void) niu_tx_channel_reset(np, rp->tx_channel);
5862 }
5863
5864 static void niu_reset_tx_channels(struct niu *np)
5865 {
5866 int i;
5867
5868 for (i = 0; i < np->num_tx_rings; i++) {
5869 struct tx_ring_info *rp = &np->tx_rings[i];
5870
5871 niu_reset_one_tx_channel(np, rp);
5872 }
5873 }
5874
5875 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5876 {
5877 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5878 }
5879
5880 static void niu_stop_rx_channels(struct niu *np)
5881 {
5882 int i;
5883
5884 for (i = 0; i < np->num_rx_rings; i++) {
5885 struct rx_ring_info *rp = &np->rx_rings[i];
5886
5887 niu_stop_one_rx_channel(np, rp);
5888 }
5889 }
5890
5891 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5892 {
5893 int channel = rp->rx_channel;
5894
5895 (void) niu_rx_channel_reset(np, channel);
5896 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5897 nw64(RX_DMA_CTL_STAT(channel), 0);
5898 (void) niu_enable_rx_channel(np, channel, 0);
5899 }
5900
5901 static void niu_reset_rx_channels(struct niu *np)
5902 {
5903 int i;
5904
5905 for (i = 0; i < np->num_rx_rings; i++) {
5906 struct rx_ring_info *rp = &np->rx_rings[i];
5907
5908 niu_reset_one_rx_channel(np, rp);
5909 }
5910 }
5911
5912 static void niu_disable_ipp(struct niu *np)
5913 {
5914 u64 rd, wr, val;
5915 int limit;
5916
5917 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5918 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5919 limit = 100;
5920 while (--limit >= 0 && (rd != wr)) {
5921 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5922 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5923 }
5924 if (limit < 0 &&
5925 (rd != 0 && wr != 1)) {
5926 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5927 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5928 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
5929 }
5930
5931 val = nr64_ipp(IPP_CFIG);
5932 val &= ~(IPP_CFIG_IPP_ENABLE |
5933 IPP_CFIG_DFIFO_ECC_EN |
5934 IPP_CFIG_DROP_BAD_CRC |
5935 IPP_CFIG_CKSUM_EN);
5936 nw64_ipp(IPP_CFIG, val);
5937
5938 (void) niu_ipp_reset(np);
5939 }
5940
5941 static int niu_init_hw(struct niu *np)
5942 {
5943 int i, err;
5944
5945 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
5946 niu_txc_enable_port(np, 1);
5947 niu_txc_port_dma_enable(np, 1);
5948 niu_txc_set_imask(np, 0);
5949
5950 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
5951 for (i = 0; i < np->num_tx_rings; i++) {
5952 struct tx_ring_info *rp = &np->tx_rings[i];
5953
5954 err = niu_init_one_tx_channel(np, rp);
5955 if (err)
5956 return err;
5957 }
5958
5959 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
5960 err = niu_init_rx_channels(np);
5961 if (err)
5962 goto out_uninit_tx_channels;
5963
5964 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
5965 err = niu_init_classifier_hw(np);
5966 if (err)
5967 goto out_uninit_rx_channels;
5968
5969 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
5970 err = niu_init_zcp(np);
5971 if (err)
5972 goto out_uninit_rx_channels;
5973
5974 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
5975 err = niu_init_ipp(np);
5976 if (err)
5977 goto out_uninit_rx_channels;
5978
5979 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
5980 err = niu_init_mac(np);
5981 if (err)
5982 goto out_uninit_ipp;
5983
5984 return 0;
5985
5986 out_uninit_ipp:
5987 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
5988 niu_disable_ipp(np);
5989
5990 out_uninit_rx_channels:
5991 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
5992 niu_stop_rx_channels(np);
5993 niu_reset_rx_channels(np);
5994
5995 out_uninit_tx_channels:
5996 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
5997 niu_stop_tx_channels(np);
5998 niu_reset_tx_channels(np);
5999
6000 return err;
6001 }
6002
6003 static void niu_stop_hw(struct niu *np)
6004 {
6005 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
6006 niu_enable_interrupts(np, 0);
6007
6008 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
6009 niu_enable_rx_mac(np, 0);
6010
6011 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
6012 niu_disable_ipp(np);
6013
6014 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
6015 niu_stop_tx_channels(np);
6016
6017 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
6018 niu_stop_rx_channels(np);
6019
6020 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
6021 niu_reset_tx_channels(np);
6022
6023 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
6024 niu_reset_rx_channels(np);
6025 }
6026
6027 static void niu_set_irq_name(struct niu *np)
6028 {
6029 int port = np->port;
6030 int i, j = 1;
6031
6032 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6033
6034 if (port == 0) {
6035 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6036 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6037 j = 3;
6038 }
6039
6040 for (i = 0; i < np->num_ldg - j; i++) {
6041 if (i < np->num_rx_rings)
6042 sprintf(np->irq_name[i+j], "%s-rx-%d",
6043 np->dev->name, i);
6044 else if (i < np->num_tx_rings + np->num_rx_rings)
6045 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6046 i - np->num_rx_rings);
6047 }
6048 }
6049
6050 static int niu_request_irq(struct niu *np)
6051 {
6052 int i, j, err;
6053
6054 niu_set_irq_name(np);
6055
6056 err = 0;
6057 for (i = 0; i < np->num_ldg; i++) {
6058 struct niu_ldg *lp = &np->ldg[i];
6059
6060 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED,
6061 np->irq_name[i], lp);
6062 if (err)
6063 goto out_free_irqs;
6064
6065 }
6066
6067 return 0;
6068
6069 out_free_irqs:
6070 for (j = 0; j < i; j++) {
6071 struct niu_ldg *lp = &np->ldg[j];
6072
6073 free_irq(lp->irq, lp);
6074 }
6075 return err;
6076 }
6077
6078 static void niu_free_irq(struct niu *np)
6079 {
6080 int i;
6081
6082 for (i = 0; i < np->num_ldg; i++) {
6083 struct niu_ldg *lp = &np->ldg[i];
6084
6085 free_irq(lp->irq, lp);
6086 }
6087 }
6088
6089 static void niu_enable_napi(struct niu *np)
6090 {
6091 int i;
6092
6093 for (i = 0; i < np->num_ldg; i++)
6094 napi_enable(&np->ldg[i].napi);
6095 }
6096
6097 static void niu_disable_napi(struct niu *np)
6098 {
6099 int i;
6100
6101 for (i = 0; i < np->num_ldg; i++)
6102 napi_disable(&np->ldg[i].napi);
6103 }
6104
6105 static int niu_open(struct net_device *dev)
6106 {
6107 struct niu *np = netdev_priv(dev);
6108 int err;
6109
6110 netif_carrier_off(dev);
6111
6112 err = niu_alloc_channels(np);
6113 if (err)
6114 goto out_err;
6115
6116 err = niu_enable_interrupts(np, 0);
6117 if (err)
6118 goto out_free_channels;
6119
6120 err = niu_request_irq(np);
6121 if (err)
6122 goto out_free_channels;
6123
6124 niu_enable_napi(np);
6125
6126 spin_lock_irq(&np->lock);
6127
6128 err = niu_init_hw(np);
6129 if (!err) {
6130 init_timer(&np->timer);
6131 np->timer.expires = jiffies + HZ;
6132 np->timer.data = (unsigned long) np;
6133 np->timer.function = niu_timer;
6134
6135 err = niu_enable_interrupts(np, 1);
6136 if (err)
6137 niu_stop_hw(np);
6138 }
6139
6140 spin_unlock_irq(&np->lock);
6141
6142 if (err) {
6143 niu_disable_napi(np);
6144 goto out_free_irq;
6145 }
6146
6147 netif_tx_start_all_queues(dev);
6148
6149 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6150 netif_carrier_on(dev);
6151
6152 add_timer(&np->timer);
6153
6154 return 0;
6155
6156 out_free_irq:
6157 niu_free_irq(np);
6158
6159 out_free_channels:
6160 niu_free_channels(np);
6161
6162 out_err:
6163 return err;
6164 }
6165
6166 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6167 {
6168 cancel_work_sync(&np->reset_task);
6169
6170 niu_disable_napi(np);
6171 netif_tx_stop_all_queues(dev);
6172
6173 del_timer_sync(&np->timer);
6174
6175 spin_lock_irq(&np->lock);
6176
6177 niu_stop_hw(np);
6178
6179 spin_unlock_irq(&np->lock);
6180 }
6181
6182 static int niu_close(struct net_device *dev)
6183 {
6184 struct niu *np = netdev_priv(dev);
6185
6186 niu_full_shutdown(np, dev);
6187
6188 niu_free_irq(np);
6189
6190 niu_free_channels(np);
6191
6192 niu_handle_led(np, 0);
6193
6194 return 0;
6195 }
6196
6197 static void niu_sync_xmac_stats(struct niu *np)
6198 {
6199 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6200
6201 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6202 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6203
6204 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6205 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6206 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6207 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6208 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6209 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6210 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6211 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6212 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6213 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6214 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6215 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6216 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6217 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6218 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6219 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6220 }
6221
6222 static void niu_sync_bmac_stats(struct niu *np)
6223 {
6224 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6225
6226 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6227 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6228
6229 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6230 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6231 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6232 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6233 }
6234
6235 static void niu_sync_mac_stats(struct niu *np)
6236 {
6237 if (np->flags & NIU_FLAGS_XMAC)
6238 niu_sync_xmac_stats(np);
6239 else
6240 niu_sync_bmac_stats(np);
6241 }
6242
6243 static void niu_get_rx_stats(struct niu *np,
6244 struct rtnl_link_stats64 *stats)
6245 {
6246 u64 pkts, dropped, errors, bytes;
6247 struct rx_ring_info *rx_rings;
6248 int i;
6249
6250 pkts = dropped = errors = bytes = 0;
6251
6252 rx_rings = ACCESS_ONCE(np->rx_rings);
6253 if (!rx_rings)
6254 goto no_rings;
6255
6256 for (i = 0; i < np->num_rx_rings; i++) {
6257 struct rx_ring_info *rp = &rx_rings[i];
6258
6259 niu_sync_rx_discard_stats(np, rp, 0);
6260
6261 pkts += rp->rx_packets;
6262 bytes += rp->rx_bytes;
6263 dropped += rp->rx_dropped;
6264 errors += rp->rx_errors;
6265 }
6266
6267 no_rings:
6268 stats->rx_packets = pkts;
6269 stats->rx_bytes = bytes;
6270 stats->rx_dropped = dropped;
6271 stats->rx_errors = errors;
6272 }
6273
6274 static void niu_get_tx_stats(struct niu *np,
6275 struct rtnl_link_stats64 *stats)
6276 {
6277 u64 pkts, errors, bytes;
6278 struct tx_ring_info *tx_rings;
6279 int i;
6280
6281 pkts = errors = bytes = 0;
6282
6283 tx_rings = ACCESS_ONCE(np->tx_rings);
6284 if (!tx_rings)
6285 goto no_rings;
6286
6287 for (i = 0; i < np->num_tx_rings; i++) {
6288 struct tx_ring_info *rp = &tx_rings[i];
6289
6290 pkts += rp->tx_packets;
6291 bytes += rp->tx_bytes;
6292 errors += rp->tx_errors;
6293 }
6294
6295 no_rings:
6296 stats->tx_packets = pkts;
6297 stats->tx_bytes = bytes;
6298 stats->tx_errors = errors;
6299 }
6300
6301 static struct rtnl_link_stats64 *niu_get_stats(struct net_device *dev,
6302 struct rtnl_link_stats64 *stats)
6303 {
6304 struct niu *np = netdev_priv(dev);
6305
6306 if (netif_running(dev)) {
6307 niu_get_rx_stats(np, stats);
6308 niu_get_tx_stats(np, stats);
6309 }
6310
6311 return stats;
6312 }
6313
6314 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6315 {
6316 int i;
6317
6318 for (i = 0; i < 16; i++)
6319 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6320 }
6321
6322 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6323 {
6324 int i;
6325
6326 for (i = 0; i < 16; i++)
6327 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6328 }
6329
6330 static void niu_load_hash(struct niu *np, u16 *hash)
6331 {
6332 if (np->flags & NIU_FLAGS_XMAC)
6333 niu_load_hash_xmac(np, hash);
6334 else
6335 niu_load_hash_bmac(np, hash);
6336 }
6337
6338 static void niu_set_rx_mode(struct net_device *dev)
6339 {
6340 struct niu *np = netdev_priv(dev);
6341 int i, alt_cnt, err;
6342 struct netdev_hw_addr *ha;
6343 unsigned long flags;
6344 u16 hash[16] = { 0, };
6345
6346 spin_lock_irqsave(&np->lock, flags);
6347 niu_enable_rx_mac(np, 0);
6348
6349 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6350 if (dev->flags & IFF_PROMISC)
6351 np->flags |= NIU_FLAGS_PROMISC;
6352 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
6353 np->flags |= NIU_FLAGS_MCAST;
6354
6355 alt_cnt = netdev_uc_count(dev);
6356 if (alt_cnt > niu_num_alt_addr(np)) {
6357 alt_cnt = 0;
6358 np->flags |= NIU_FLAGS_PROMISC;
6359 }
6360
6361 if (alt_cnt) {
6362 int index = 0;
6363
6364 netdev_for_each_uc_addr(ha, dev) {
6365 err = niu_set_alt_mac(np, index, ha->addr);
6366 if (err)
6367 netdev_warn(dev, "Error %d adding alt mac %d\n",
6368 err, index);
6369 err = niu_enable_alt_mac(np, index, 1);
6370 if (err)
6371 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6372 err, index);
6373
6374 index++;
6375 }
6376 } else {
6377 int alt_start;
6378 if (np->flags & NIU_FLAGS_XMAC)
6379 alt_start = 0;
6380 else
6381 alt_start = 1;
6382 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
6383 err = niu_enable_alt_mac(np, i, 0);
6384 if (err)
6385 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6386 err, i);
6387 }
6388 }
6389 if (dev->flags & IFF_ALLMULTI) {
6390 for (i = 0; i < 16; i++)
6391 hash[i] = 0xffff;
6392 } else if (!netdev_mc_empty(dev)) {
6393 netdev_for_each_mc_addr(ha, dev) {
6394 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
6395
6396 crc >>= 24;
6397 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6398 }
6399 }
6400
6401 if (np->flags & NIU_FLAGS_MCAST)
6402 niu_load_hash(np, hash);
6403
6404 niu_enable_rx_mac(np, 1);
6405 spin_unlock_irqrestore(&np->lock, flags);
6406 }
6407
6408 static int niu_set_mac_addr(struct net_device *dev, void *p)
6409 {
6410 struct niu *np = netdev_priv(dev);
6411 struct sockaddr *addr = p;
6412 unsigned long flags;
6413
6414 if (!is_valid_ether_addr(addr->sa_data))
6415 return -EINVAL;
6416
6417 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6418
6419 if (!netif_running(dev))
6420 return 0;
6421
6422 spin_lock_irqsave(&np->lock, flags);
6423 niu_enable_rx_mac(np, 0);
6424 niu_set_primary_mac(np, dev->dev_addr);
6425 niu_enable_rx_mac(np, 1);
6426 spin_unlock_irqrestore(&np->lock, flags);
6427
6428 return 0;
6429 }
6430
6431 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6432 {
6433 return -EOPNOTSUPP;
6434 }
6435
6436 static void niu_netif_stop(struct niu *np)
6437 {
6438 np->dev->trans_start = jiffies; /* prevent tx timeout */
6439
6440 niu_disable_napi(np);
6441
6442 netif_tx_disable(np->dev);
6443 }
6444
6445 static void niu_netif_start(struct niu *np)
6446 {
6447 /* NOTE: unconditional netif_wake_queue is only appropriate
6448 * so long as all callers are assured to have free tx slots
6449 * (such as after niu_init_hw).
6450 */
6451 netif_tx_wake_all_queues(np->dev);
6452
6453 niu_enable_napi(np);
6454
6455 niu_enable_interrupts(np, 1);
6456 }
6457
6458 static void niu_reset_buffers(struct niu *np)
6459 {
6460 int i, j, k, err;
6461
6462 if (np->rx_rings) {
6463 for (i = 0; i < np->num_rx_rings; i++) {
6464 struct rx_ring_info *rp = &np->rx_rings[i];
6465
6466 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6467 struct page *page;
6468
6469 page = rp->rxhash[j];
6470 while (page) {
6471 struct page *next =
6472 (struct page *) page->mapping;
6473 u64 base = page->index;
6474 base = base >> RBR_DESCR_ADDR_SHIFT;
6475 rp->rbr[k++] = cpu_to_le32(base);
6476 page = next;
6477 }
6478 }
6479 for (; k < MAX_RBR_RING_SIZE; k++) {
6480 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6481 if (unlikely(err))
6482 break;
6483 }
6484
6485 rp->rbr_index = rp->rbr_table_size - 1;
6486 rp->rcr_index = 0;
6487 rp->rbr_pending = 0;
6488 rp->rbr_refill_pending = 0;
6489 }
6490 }
6491 if (np->tx_rings) {
6492 for (i = 0; i < np->num_tx_rings; i++) {
6493 struct tx_ring_info *rp = &np->tx_rings[i];
6494
6495 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6496 if (rp->tx_buffs[j].skb)
6497 (void) release_tx_packet(np, rp, j);
6498 }
6499
6500 rp->pending = MAX_TX_RING_SIZE;
6501 rp->prod = 0;
6502 rp->cons = 0;
6503 rp->wrap_bit = 0;
6504 }
6505 }
6506 }
6507
6508 static void niu_reset_task(struct work_struct *work)
6509 {
6510 struct niu *np = container_of(work, struct niu, reset_task);
6511 unsigned long flags;
6512 int err;
6513
6514 spin_lock_irqsave(&np->lock, flags);
6515 if (!netif_running(np->dev)) {
6516 spin_unlock_irqrestore(&np->lock, flags);
6517 return;
6518 }
6519
6520 spin_unlock_irqrestore(&np->lock, flags);
6521
6522 del_timer_sync(&np->timer);
6523
6524 niu_netif_stop(np);
6525
6526 spin_lock_irqsave(&np->lock, flags);
6527
6528 niu_stop_hw(np);
6529
6530 spin_unlock_irqrestore(&np->lock, flags);
6531
6532 niu_reset_buffers(np);
6533
6534 spin_lock_irqsave(&np->lock, flags);
6535
6536 err = niu_init_hw(np);
6537 if (!err) {
6538 np->timer.expires = jiffies + HZ;
6539 add_timer(&np->timer);
6540 niu_netif_start(np);
6541 }
6542
6543 spin_unlock_irqrestore(&np->lock, flags);
6544 }
6545
6546 static void niu_tx_timeout(struct net_device *dev)
6547 {
6548 struct niu *np = netdev_priv(dev);
6549
6550 dev_err(np->device, "%s: Transmit timed out, resetting\n",
6551 dev->name);
6552
6553 schedule_work(&np->reset_task);
6554 }
6555
6556 static void niu_set_txd(struct tx_ring_info *rp, int index,
6557 u64 mapping, u64 len, u64 mark,
6558 u64 n_frags)
6559 {
6560 __le64 *desc = &rp->descr[index];
6561
6562 *desc = cpu_to_le64(mark |
6563 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6564 (len << TX_DESC_TR_LEN_SHIFT) |
6565 (mapping & TX_DESC_SAD));
6566 }
6567
6568 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6569 u64 pad_bytes, u64 len)
6570 {
6571 u16 eth_proto, eth_proto_inner;
6572 u64 csum_bits, l3off, ihl, ret;
6573 u8 ip_proto;
6574 int ipv6;
6575
6576 eth_proto = be16_to_cpu(ehdr->h_proto);
6577 eth_proto_inner = eth_proto;
6578 if (eth_proto == ETH_P_8021Q) {
6579 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6580 __be16 val = vp->h_vlan_encapsulated_proto;
6581
6582 eth_proto_inner = be16_to_cpu(val);
6583 }
6584
6585 ipv6 = ihl = 0;
6586 switch (skb->protocol) {
6587 case cpu_to_be16(ETH_P_IP):
6588 ip_proto = ip_hdr(skb)->protocol;
6589 ihl = ip_hdr(skb)->ihl;
6590 break;
6591 case cpu_to_be16(ETH_P_IPV6):
6592 ip_proto = ipv6_hdr(skb)->nexthdr;
6593 ihl = (40 >> 2);
6594 ipv6 = 1;
6595 break;
6596 default:
6597 ip_proto = ihl = 0;
6598 break;
6599 }
6600
6601 csum_bits = TXHDR_CSUM_NONE;
6602 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6603 u64 start, stuff;
6604
6605 csum_bits = (ip_proto == IPPROTO_TCP ?
6606 TXHDR_CSUM_TCP :
6607 (ip_proto == IPPROTO_UDP ?
6608 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6609
6610 start = skb_checksum_start_offset(skb) -
6611 (pad_bytes + sizeof(struct tx_pkt_hdr));
6612 stuff = start + skb->csum_offset;
6613
6614 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6615 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6616 }
6617
6618 l3off = skb_network_offset(skb) -
6619 (pad_bytes + sizeof(struct tx_pkt_hdr));
6620
6621 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6622 (len << TXHDR_LEN_SHIFT) |
6623 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6624 (ihl << TXHDR_IHL_SHIFT) |
6625 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6626 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6627 (ipv6 ? TXHDR_IP_VER : 0) |
6628 csum_bits);
6629
6630 return ret;
6631 }
6632
6633 static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6634 struct net_device *dev)
6635 {
6636 struct niu *np = netdev_priv(dev);
6637 unsigned long align, headroom;
6638 struct netdev_queue *txq;
6639 struct tx_ring_info *rp;
6640 struct tx_pkt_hdr *tp;
6641 unsigned int len, nfg;
6642 struct ethhdr *ehdr;
6643 int prod, i, tlen;
6644 u64 mapping, mrk;
6645
6646 i = skb_get_queue_mapping(skb);
6647 rp = &np->tx_rings[i];
6648 txq = netdev_get_tx_queue(dev, i);
6649
6650 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6651 netif_tx_stop_queue(txq);
6652 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
6653 rp->tx_errors++;
6654 return NETDEV_TX_BUSY;
6655 }
6656
6657 if (skb->len < ETH_ZLEN) {
6658 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6659
6660 if (skb_pad(skb, pad_bytes))
6661 goto out;
6662 skb_put(skb, pad_bytes);
6663 }
6664
6665 len = sizeof(struct tx_pkt_hdr) + 15;
6666 if (skb_headroom(skb) < len) {
6667 struct sk_buff *skb_new;
6668
6669 skb_new = skb_realloc_headroom(skb, len);
6670 if (!skb_new) {
6671 rp->tx_errors++;
6672 goto out_drop;
6673 }
6674 kfree_skb(skb);
6675 skb = skb_new;
6676 } else
6677 skb_orphan(skb);
6678
6679 align = ((unsigned long) skb->data & (16 - 1));
6680 headroom = align + sizeof(struct tx_pkt_hdr);
6681
6682 ehdr = (struct ethhdr *) skb->data;
6683 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6684
6685 len = skb->len - sizeof(struct tx_pkt_hdr);
6686 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6687 tp->resv = 0;
6688
6689 len = skb_headlen(skb);
6690 mapping = np->ops->map_single(np->device, skb->data,
6691 len, DMA_TO_DEVICE);
6692
6693 prod = rp->prod;
6694
6695 rp->tx_buffs[prod].skb = skb;
6696 rp->tx_buffs[prod].mapping = mapping;
6697
6698 mrk = TX_DESC_SOP;
6699 if (++rp->mark_counter == rp->mark_freq) {
6700 rp->mark_counter = 0;
6701 mrk |= TX_DESC_MARK;
6702 rp->mark_pending++;
6703 }
6704
6705 tlen = len;
6706 nfg = skb_shinfo(skb)->nr_frags;
6707 while (tlen > 0) {
6708 tlen -= MAX_TX_DESC_LEN;
6709 nfg++;
6710 }
6711
6712 while (len > 0) {
6713 unsigned int this_len = len;
6714
6715 if (this_len > MAX_TX_DESC_LEN)
6716 this_len = MAX_TX_DESC_LEN;
6717
6718 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6719 mrk = nfg = 0;
6720
6721 prod = NEXT_TX(rp, prod);
6722 mapping += this_len;
6723 len -= this_len;
6724 }
6725
6726 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6727 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6728
6729 len = skb_frag_size(frag);
6730 mapping = np->ops->map_page(np->device, skb_frag_page(frag),
6731 frag->page_offset, len,
6732 DMA_TO_DEVICE);
6733
6734 rp->tx_buffs[prod].skb = NULL;
6735 rp->tx_buffs[prod].mapping = mapping;
6736
6737 niu_set_txd(rp, prod, mapping, len, 0, 0);
6738
6739 prod = NEXT_TX(rp, prod);
6740 }
6741
6742 netdev_tx_sent_queue(txq, skb->len);
6743
6744 if (prod < rp->prod)
6745 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6746 rp->prod = prod;
6747
6748 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6749
6750 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6751 netif_tx_stop_queue(txq);
6752 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6753 netif_tx_wake_queue(txq);
6754 }
6755
6756 out:
6757 return NETDEV_TX_OK;
6758
6759 out_drop:
6760 rp->tx_errors++;
6761 kfree_skb(skb);
6762 goto out;
6763 }
6764
6765 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6766 {
6767 struct niu *np = netdev_priv(dev);
6768 int err, orig_jumbo, new_jumbo;
6769
6770 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6771 return -EINVAL;
6772
6773 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6774 new_jumbo = (new_mtu > ETH_DATA_LEN);
6775
6776 dev->mtu = new_mtu;
6777
6778 if (!netif_running(dev) ||
6779 (orig_jumbo == new_jumbo))
6780 return 0;
6781
6782 niu_full_shutdown(np, dev);
6783
6784 niu_free_channels(np);
6785
6786 niu_enable_napi(np);
6787
6788 err = niu_alloc_channels(np);
6789 if (err)
6790 return err;
6791
6792 spin_lock_irq(&np->lock);
6793
6794 err = niu_init_hw(np);
6795 if (!err) {
6796 init_timer(&np->timer);
6797 np->timer.expires = jiffies + HZ;
6798 np->timer.data = (unsigned long) np;
6799 np->timer.function = niu_timer;
6800
6801 err = niu_enable_interrupts(np, 1);
6802 if (err)
6803 niu_stop_hw(np);
6804 }
6805
6806 spin_unlock_irq(&np->lock);
6807
6808 if (!err) {
6809 netif_tx_start_all_queues(dev);
6810 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6811 netif_carrier_on(dev);
6812
6813 add_timer(&np->timer);
6814 }
6815
6816 return err;
6817 }
6818
6819 static void niu_get_drvinfo(struct net_device *dev,
6820 struct ethtool_drvinfo *info)
6821 {
6822 struct niu *np = netdev_priv(dev);
6823 struct niu_vpd *vpd = &np->vpd;
6824
6825 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
6826 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
6827 snprintf(info->fw_version, sizeof(info->fw_version), "%d.%d",
6828 vpd->fcode_major, vpd->fcode_minor);
6829 if (np->parent->plat_type != PLAT_TYPE_NIU)
6830 strlcpy(info->bus_info, pci_name(np->pdev),
6831 sizeof(info->bus_info));
6832 }
6833
6834 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6835 {
6836 struct niu *np = netdev_priv(dev);
6837 struct niu_link_config *lp;
6838
6839 lp = &np->link_config;
6840
6841 memset(cmd, 0, sizeof(*cmd));
6842 cmd->phy_address = np->phy_addr;
6843 cmd->supported = lp->supported;
6844 cmd->advertising = lp->active_advertising;
6845 cmd->autoneg = lp->active_autoneg;
6846 ethtool_cmd_speed_set(cmd, lp->active_speed);
6847 cmd->duplex = lp->active_duplex;
6848 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6849 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6850 XCVR_EXTERNAL : XCVR_INTERNAL;
6851
6852 return 0;
6853 }
6854
6855 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6856 {
6857 struct niu *np = netdev_priv(dev);
6858 struct niu_link_config *lp = &np->link_config;
6859
6860 lp->advertising = cmd->advertising;
6861 lp->speed = ethtool_cmd_speed(cmd);
6862 lp->duplex = cmd->duplex;
6863 lp->autoneg = cmd->autoneg;
6864 return niu_init_link(np);
6865 }
6866
6867 static u32 niu_get_msglevel(struct net_device *dev)
6868 {
6869 struct niu *np = netdev_priv(dev);
6870 return np->msg_enable;
6871 }
6872
6873 static void niu_set_msglevel(struct net_device *dev, u32 value)
6874 {
6875 struct niu *np = netdev_priv(dev);
6876 np->msg_enable = value;
6877 }
6878
6879 static int niu_nway_reset(struct net_device *dev)
6880 {
6881 struct niu *np = netdev_priv(dev);
6882
6883 if (np->link_config.autoneg)
6884 return niu_init_link(np);
6885
6886 return 0;
6887 }
6888
6889 static int niu_get_eeprom_len(struct net_device *dev)
6890 {
6891 struct niu *np = netdev_priv(dev);
6892
6893 return np->eeprom_len;
6894 }
6895
6896 static int niu_get_eeprom(struct net_device *dev,
6897 struct ethtool_eeprom *eeprom, u8 *data)
6898 {
6899 struct niu *np = netdev_priv(dev);
6900 u32 offset, len, val;
6901
6902 offset = eeprom->offset;
6903 len = eeprom->len;
6904
6905 if (offset + len < offset)
6906 return -EINVAL;
6907 if (offset >= np->eeprom_len)
6908 return -EINVAL;
6909 if (offset + len > np->eeprom_len)
6910 len = eeprom->len = np->eeprom_len - offset;
6911
6912 if (offset & 3) {
6913 u32 b_offset, b_count;
6914
6915 b_offset = offset & 3;
6916 b_count = 4 - b_offset;
6917 if (b_count > len)
6918 b_count = len;
6919
6920 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6921 memcpy(data, ((char *)&val) + b_offset, b_count);
6922 data += b_count;
6923 len -= b_count;
6924 offset += b_count;
6925 }
6926 while (len >= 4) {
6927 val = nr64(ESPC_NCR(offset / 4));
6928 memcpy(data, &val, 4);
6929 data += 4;
6930 len -= 4;
6931 offset += 4;
6932 }
6933 if (len) {
6934 val = nr64(ESPC_NCR(offset / 4));
6935 memcpy(data, &val, len);
6936 }
6937 return 0;
6938 }
6939
6940 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6941 {
6942 switch (flow_type) {
6943 case TCP_V4_FLOW:
6944 case TCP_V6_FLOW:
6945 *pid = IPPROTO_TCP;
6946 break;
6947 case UDP_V4_FLOW:
6948 case UDP_V6_FLOW:
6949 *pid = IPPROTO_UDP;
6950 break;
6951 case SCTP_V4_FLOW:
6952 case SCTP_V6_FLOW:
6953 *pid = IPPROTO_SCTP;
6954 break;
6955 case AH_V4_FLOW:
6956 case AH_V6_FLOW:
6957 *pid = IPPROTO_AH;
6958 break;
6959 case ESP_V4_FLOW:
6960 case ESP_V6_FLOW:
6961 *pid = IPPROTO_ESP;
6962 break;
6963 default:
6964 *pid = 0;
6965 break;
6966 }
6967 }
6968
6969 static int niu_class_to_ethflow(u64 class, int *flow_type)
6970 {
6971 switch (class) {
6972 case CLASS_CODE_TCP_IPV4:
6973 *flow_type = TCP_V4_FLOW;
6974 break;
6975 case CLASS_CODE_UDP_IPV4:
6976 *flow_type = UDP_V4_FLOW;
6977 break;
6978 case CLASS_CODE_AH_ESP_IPV4:
6979 *flow_type = AH_V4_FLOW;
6980 break;
6981 case CLASS_CODE_SCTP_IPV4:
6982 *flow_type = SCTP_V4_FLOW;
6983 break;
6984 case CLASS_CODE_TCP_IPV6:
6985 *flow_type = TCP_V6_FLOW;
6986 break;
6987 case CLASS_CODE_UDP_IPV6:
6988 *flow_type = UDP_V6_FLOW;
6989 break;
6990 case CLASS_CODE_AH_ESP_IPV6:
6991 *flow_type = AH_V6_FLOW;
6992 break;
6993 case CLASS_CODE_SCTP_IPV6:
6994 *flow_type = SCTP_V6_FLOW;
6995 break;
6996 case CLASS_CODE_USER_PROG1:
6997 case CLASS_CODE_USER_PROG2:
6998 case CLASS_CODE_USER_PROG3:
6999 case CLASS_CODE_USER_PROG4:
7000 *flow_type = IP_USER_FLOW;
7001 break;
7002 default:
7003 return 0;
7004 }
7005
7006 return 1;
7007 }
7008
7009 static int niu_ethflow_to_class(int flow_type, u64 *class)
7010 {
7011 switch (flow_type) {
7012 case TCP_V4_FLOW:
7013 *class = CLASS_CODE_TCP_IPV4;
7014 break;
7015 case UDP_V4_FLOW:
7016 *class = CLASS_CODE_UDP_IPV4;
7017 break;
7018 case AH_ESP_V4_FLOW:
7019 case AH_V4_FLOW:
7020 case ESP_V4_FLOW:
7021 *class = CLASS_CODE_AH_ESP_IPV4;
7022 break;
7023 case SCTP_V4_FLOW:
7024 *class = CLASS_CODE_SCTP_IPV4;
7025 break;
7026 case TCP_V6_FLOW:
7027 *class = CLASS_CODE_TCP_IPV6;
7028 break;
7029 case UDP_V6_FLOW:
7030 *class = CLASS_CODE_UDP_IPV6;
7031 break;
7032 case AH_ESP_V6_FLOW:
7033 case AH_V6_FLOW:
7034 case ESP_V6_FLOW:
7035 *class = CLASS_CODE_AH_ESP_IPV6;
7036 break;
7037 case SCTP_V6_FLOW:
7038 *class = CLASS_CODE_SCTP_IPV6;
7039 break;
7040 default:
7041 return 0;
7042 }
7043
7044 return 1;
7045 }
7046
7047 static u64 niu_flowkey_to_ethflow(u64 flow_key)
7048 {
7049 u64 ethflow = 0;
7050
7051 if (flow_key & FLOW_KEY_L2DA)
7052 ethflow |= RXH_L2DA;
7053 if (flow_key & FLOW_KEY_VLAN)
7054 ethflow |= RXH_VLAN;
7055 if (flow_key & FLOW_KEY_IPSA)
7056 ethflow |= RXH_IP_SRC;
7057 if (flow_key & FLOW_KEY_IPDA)
7058 ethflow |= RXH_IP_DST;
7059 if (flow_key & FLOW_KEY_PROTO)
7060 ethflow |= RXH_L3_PROTO;
7061 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7062 ethflow |= RXH_L4_B_0_1;
7063 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7064 ethflow |= RXH_L4_B_2_3;
7065
7066 return ethflow;
7067
7068 }
7069
7070 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7071 {
7072 u64 key = 0;
7073
7074 if (ethflow & RXH_L2DA)
7075 key |= FLOW_KEY_L2DA;
7076 if (ethflow & RXH_VLAN)
7077 key |= FLOW_KEY_VLAN;
7078 if (ethflow & RXH_IP_SRC)
7079 key |= FLOW_KEY_IPSA;
7080 if (ethflow & RXH_IP_DST)
7081 key |= FLOW_KEY_IPDA;
7082 if (ethflow & RXH_L3_PROTO)
7083 key |= FLOW_KEY_PROTO;
7084 if (ethflow & RXH_L4_B_0_1)
7085 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7086 if (ethflow & RXH_L4_B_2_3)
7087 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7088
7089 *flow_key = key;
7090
7091 return 1;
7092
7093 }
7094
7095 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7096 {
7097 u64 class;
7098
7099 nfc->data = 0;
7100
7101 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7102 return -EINVAL;
7103
7104 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7105 TCAM_KEY_DISC)
7106 nfc->data = RXH_DISCARD;
7107 else
7108 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
7109 CLASS_CODE_USER_PROG1]);
7110 return 0;
7111 }
7112
7113 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7114 struct ethtool_rx_flow_spec *fsp)
7115 {
7116 u32 tmp;
7117 u16 prt;
7118
7119 tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7120 fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7121
7122 tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7123 fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7124
7125 tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7126 fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7127
7128 tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7129 fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7130
7131 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7132 TCAM_V4KEY2_TOS_SHIFT;
7133 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7134 TCAM_V4KEY2_TOS_SHIFT;
7135
7136 switch (fsp->flow_type) {
7137 case TCP_V4_FLOW:
7138 case UDP_V4_FLOW:
7139 case SCTP_V4_FLOW:
7140 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7141 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7142 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7143
7144 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7145 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7146 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7147
7148 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7149 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7150 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7151
7152 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7153 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7154 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
7155 break;
7156 case AH_V4_FLOW:
7157 case ESP_V4_FLOW:
7158 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7159 TCAM_V4KEY2_PORT_SPI_SHIFT;
7160 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7161
7162 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7163 TCAM_V4KEY2_PORT_SPI_SHIFT;
7164 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
7165 break;
7166 case IP_USER_FLOW:
7167 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7168 TCAM_V4KEY2_PORT_SPI_SHIFT;
7169 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7170
7171 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7172 TCAM_V4KEY2_PORT_SPI_SHIFT;
7173 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
7174
7175 fsp->h_u.usr_ip4_spec.proto =
7176 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7177 TCAM_V4KEY2_PROTO_SHIFT;
7178 fsp->m_u.usr_ip4_spec.proto =
7179 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7180 TCAM_V4KEY2_PROTO_SHIFT;
7181
7182 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7183 break;
7184 default:
7185 break;
7186 }
7187 }
7188
7189 static int niu_get_ethtool_tcam_entry(struct niu *np,
7190 struct ethtool_rxnfc *nfc)
7191 {
7192 struct niu_parent *parent = np->parent;
7193 struct niu_tcam_entry *tp;
7194 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7195 u16 idx;
7196 u64 class;
7197 int ret = 0;
7198
7199 idx = tcam_get_index(np, (u16)nfc->fs.location);
7200
7201 tp = &parent->tcam[idx];
7202 if (!tp->valid) {
7203 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7204 parent->index, (u16)nfc->fs.location, idx);
7205 return -EINVAL;
7206 }
7207
7208 /* fill the flow spec entry */
7209 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7210 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7211 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7212
7213 if (ret < 0) {
7214 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7215 parent->index);
7216 ret = -EINVAL;
7217 goto out;
7218 }
7219
7220 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7221 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7222 TCAM_V4KEY2_PROTO_SHIFT;
7223 if (proto == IPPROTO_ESP) {
7224 if (fsp->flow_type == AH_V4_FLOW)
7225 fsp->flow_type = ESP_V4_FLOW;
7226 else
7227 fsp->flow_type = ESP_V6_FLOW;
7228 }
7229 }
7230
7231 switch (fsp->flow_type) {
7232 case TCP_V4_FLOW:
7233 case UDP_V4_FLOW:
7234 case SCTP_V4_FLOW:
7235 case AH_V4_FLOW:
7236 case ESP_V4_FLOW:
7237 niu_get_ip4fs_from_tcam_key(tp, fsp);
7238 break;
7239 case TCP_V6_FLOW:
7240 case UDP_V6_FLOW:
7241 case SCTP_V6_FLOW:
7242 case AH_V6_FLOW:
7243 case ESP_V6_FLOW:
7244 /* Not yet implemented */
7245 ret = -EINVAL;
7246 break;
7247 case IP_USER_FLOW:
7248 niu_get_ip4fs_from_tcam_key(tp, fsp);
7249 break;
7250 default:
7251 ret = -EINVAL;
7252 break;
7253 }
7254
7255 if (ret < 0)
7256 goto out;
7257
7258 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7259 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7260 else
7261 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7262 TCAM_ASSOCDATA_OFFSET_SHIFT;
7263
7264 /* put the tcam size here */
7265 nfc->data = tcam_get_size(np);
7266 out:
7267 return ret;
7268 }
7269
7270 static int niu_get_ethtool_tcam_all(struct niu *np,
7271 struct ethtool_rxnfc *nfc,
7272 u32 *rule_locs)
7273 {
7274 struct niu_parent *parent = np->parent;
7275 struct niu_tcam_entry *tp;
7276 int i, idx, cnt;
7277 unsigned long flags;
7278 int ret = 0;
7279
7280 /* put the tcam size here */
7281 nfc->data = tcam_get_size(np);
7282
7283 niu_lock_parent(np, flags);
7284 for (cnt = 0, i = 0; i < nfc->data; i++) {
7285 idx = tcam_get_index(np, i);
7286 tp = &parent->tcam[idx];
7287 if (!tp->valid)
7288 continue;
7289 if (cnt == nfc->rule_cnt) {
7290 ret = -EMSGSIZE;
7291 break;
7292 }
7293 rule_locs[cnt] = i;
7294 cnt++;
7295 }
7296 niu_unlock_parent(np, flags);
7297
7298 nfc->rule_cnt = cnt;
7299
7300 return ret;
7301 }
7302
7303 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7304 u32 *rule_locs)
7305 {
7306 struct niu *np = netdev_priv(dev);
7307 int ret = 0;
7308
7309 switch (cmd->cmd) {
7310 case ETHTOOL_GRXFH:
7311 ret = niu_get_hash_opts(np, cmd);
7312 break;
7313 case ETHTOOL_GRXRINGS:
7314 cmd->data = np->num_rx_rings;
7315 break;
7316 case ETHTOOL_GRXCLSRLCNT:
7317 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7318 break;
7319 case ETHTOOL_GRXCLSRULE:
7320 ret = niu_get_ethtool_tcam_entry(np, cmd);
7321 break;
7322 case ETHTOOL_GRXCLSRLALL:
7323 ret = niu_get_ethtool_tcam_all(np, cmd, rule_locs);
7324 break;
7325 default:
7326 ret = -EINVAL;
7327 break;
7328 }
7329
7330 return ret;
7331 }
7332
7333 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7334 {
7335 u64 class;
7336 u64 flow_key = 0;
7337 unsigned long flags;
7338
7339 if (!niu_ethflow_to_class(nfc->flow_type, &class))
7340 return -EINVAL;
7341
7342 if (class < CLASS_CODE_USER_PROG1 ||
7343 class > CLASS_CODE_SCTP_IPV6)
7344 return -EINVAL;
7345
7346 if (nfc->data & RXH_DISCARD) {
7347 niu_lock_parent(np, flags);
7348 flow_key = np->parent->tcam_key[class -
7349 CLASS_CODE_USER_PROG1];
7350 flow_key |= TCAM_KEY_DISC;
7351 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7352 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7353 niu_unlock_parent(np, flags);
7354 return 0;
7355 } else {
7356 /* Discard was set before, but is not set now */
7357 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7358 TCAM_KEY_DISC) {
7359 niu_lock_parent(np, flags);
7360 flow_key = np->parent->tcam_key[class -
7361 CLASS_CODE_USER_PROG1];
7362 flow_key &= ~TCAM_KEY_DISC;
7363 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7364 flow_key);
7365 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7366 flow_key;
7367 niu_unlock_parent(np, flags);
7368 }
7369 }
7370
7371 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
7372 return -EINVAL;
7373
7374 niu_lock_parent(np, flags);
7375 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7376 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7377 niu_unlock_parent(np, flags);
7378
7379 return 0;
7380 }
7381
7382 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7383 struct niu_tcam_entry *tp,
7384 int l2_rdc_tab, u64 class)
7385 {
7386 u8 pid = 0;
7387 u32 sip, dip, sipm, dipm, spi, spim;
7388 u16 sport, dport, spm, dpm;
7389
7390 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7391 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7392 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7393 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7394
7395 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7396 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7397 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7398 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7399
7400 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7401 tp->key[3] |= dip;
7402
7403 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7404 tp->key_mask[3] |= dipm;
7405
7406 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7407 TCAM_V4KEY2_TOS_SHIFT);
7408 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7409 TCAM_V4KEY2_TOS_SHIFT);
7410 switch (fsp->flow_type) {
7411 case TCP_V4_FLOW:
7412 case UDP_V4_FLOW:
7413 case SCTP_V4_FLOW:
7414 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7415 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7416 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7417 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7418
7419 tp->key[2] |= (((u64)sport << 16) | dport);
7420 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7421 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7422 break;
7423 case AH_V4_FLOW:
7424 case ESP_V4_FLOW:
7425 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7426 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7427
7428 tp->key[2] |= spi;
7429 tp->key_mask[2] |= spim;
7430 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7431 break;
7432 case IP_USER_FLOW:
7433 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7434 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7435
7436 tp->key[2] |= spi;
7437 tp->key_mask[2] |= spim;
7438 pid = fsp->h_u.usr_ip4_spec.proto;
7439 break;
7440 default:
7441 break;
7442 }
7443
7444 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7445 if (pid) {
7446 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7447 }
7448 }
7449
7450 static int niu_add_ethtool_tcam_entry(struct niu *np,
7451 struct ethtool_rxnfc *nfc)
7452 {
7453 struct niu_parent *parent = np->parent;
7454 struct niu_tcam_entry *tp;
7455 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7456 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7457 int l2_rdc_table = rdc_table->first_table_num;
7458 u16 idx;
7459 u64 class;
7460 unsigned long flags;
7461 int err, ret;
7462
7463 ret = 0;
7464
7465 idx = nfc->fs.location;
7466 if (idx >= tcam_get_size(np))
7467 return -EINVAL;
7468
7469 if (fsp->flow_type == IP_USER_FLOW) {
7470 int i;
7471 int add_usr_cls = 0;
7472 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7473 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7474
7475 if (uspec->ip_ver != ETH_RX_NFC_IP4)
7476 return -EINVAL;
7477
7478 niu_lock_parent(np, flags);
7479
7480 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7481 if (parent->l3_cls[i]) {
7482 if (uspec->proto == parent->l3_cls_pid[i]) {
7483 class = parent->l3_cls[i];
7484 parent->l3_cls_refcnt[i]++;
7485 add_usr_cls = 1;
7486 break;
7487 }
7488 } else {
7489 /* Program new user IP class */
7490 switch (i) {
7491 case 0:
7492 class = CLASS_CODE_USER_PROG1;
7493 break;
7494 case 1:
7495 class = CLASS_CODE_USER_PROG2;
7496 break;
7497 case 2:
7498 class = CLASS_CODE_USER_PROG3;
7499 break;
7500 case 3:
7501 class = CLASS_CODE_USER_PROG4;
7502 break;
7503 default:
7504 break;
7505 }
7506 ret = tcam_user_ip_class_set(np, class, 0,
7507 uspec->proto,
7508 uspec->tos,
7509 umask->tos);
7510 if (ret)
7511 goto out;
7512
7513 ret = tcam_user_ip_class_enable(np, class, 1);
7514 if (ret)
7515 goto out;
7516 parent->l3_cls[i] = class;
7517 parent->l3_cls_pid[i] = uspec->proto;
7518 parent->l3_cls_refcnt[i]++;
7519 add_usr_cls = 1;
7520 break;
7521 }
7522 }
7523 if (!add_usr_cls) {
7524 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7525 parent->index, __func__, uspec->proto);
7526 ret = -EINVAL;
7527 goto out;
7528 }
7529 niu_unlock_parent(np, flags);
7530 } else {
7531 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7532 return -EINVAL;
7533 }
7534 }
7535
7536 niu_lock_parent(np, flags);
7537
7538 idx = tcam_get_index(np, idx);
7539 tp = &parent->tcam[idx];
7540
7541 memset(tp, 0, sizeof(*tp));
7542
7543 /* fill in the tcam key and mask */
7544 switch (fsp->flow_type) {
7545 case TCP_V4_FLOW:
7546 case UDP_V4_FLOW:
7547 case SCTP_V4_FLOW:
7548 case AH_V4_FLOW:
7549 case ESP_V4_FLOW:
7550 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7551 break;
7552 case TCP_V6_FLOW:
7553 case UDP_V6_FLOW:
7554 case SCTP_V6_FLOW:
7555 case AH_V6_FLOW:
7556 case ESP_V6_FLOW:
7557 /* Not yet implemented */
7558 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7559 parent->index, __func__, fsp->flow_type);
7560 ret = -EINVAL;
7561 goto out;
7562 case IP_USER_FLOW:
7563 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7564 break;
7565 default:
7566 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7567 parent->index, __func__, fsp->flow_type);
7568 ret = -EINVAL;
7569 goto out;
7570 }
7571
7572 /* fill in the assoc data */
7573 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7574 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7575 } else {
7576 if (fsp->ring_cookie >= np->num_rx_rings) {
7577 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7578 parent->index, __func__,
7579 (long long)fsp->ring_cookie);
7580 ret = -EINVAL;
7581 goto out;
7582 }
7583 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7584 (fsp->ring_cookie <<
7585 TCAM_ASSOCDATA_OFFSET_SHIFT));
7586 }
7587
7588 err = tcam_write(np, idx, tp->key, tp->key_mask);
7589 if (err) {
7590 ret = -EINVAL;
7591 goto out;
7592 }
7593 err = tcam_assoc_write(np, idx, tp->assoc_data);
7594 if (err) {
7595 ret = -EINVAL;
7596 goto out;
7597 }
7598
7599 /* validate the entry */
7600 tp->valid = 1;
7601 np->clas.tcam_valid_entries++;
7602 out:
7603 niu_unlock_parent(np, flags);
7604
7605 return ret;
7606 }
7607
7608 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7609 {
7610 struct niu_parent *parent = np->parent;
7611 struct niu_tcam_entry *tp;
7612 u16 idx;
7613 unsigned long flags;
7614 u64 class;
7615 int ret = 0;
7616
7617 if (loc >= tcam_get_size(np))
7618 return -EINVAL;
7619
7620 niu_lock_parent(np, flags);
7621
7622 idx = tcam_get_index(np, loc);
7623 tp = &parent->tcam[idx];
7624
7625 /* if the entry is of a user defined class, then update*/
7626 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7627 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7628
7629 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7630 int i;
7631 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7632 if (parent->l3_cls[i] == class) {
7633 parent->l3_cls_refcnt[i]--;
7634 if (!parent->l3_cls_refcnt[i]) {
7635 /* disable class */
7636 ret = tcam_user_ip_class_enable(np,
7637 class,
7638 0);
7639 if (ret)
7640 goto out;
7641 parent->l3_cls[i] = 0;
7642 parent->l3_cls_pid[i] = 0;
7643 }
7644 break;
7645 }
7646 }
7647 if (i == NIU_L3_PROG_CLS) {
7648 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7649 parent->index, __func__,
7650 (unsigned long long)class);
7651 ret = -EINVAL;
7652 goto out;
7653 }
7654 }
7655
7656 ret = tcam_flush(np, idx);
7657 if (ret)
7658 goto out;
7659
7660 /* invalidate the entry */
7661 tp->valid = 0;
7662 np->clas.tcam_valid_entries--;
7663 out:
7664 niu_unlock_parent(np, flags);
7665
7666 return ret;
7667 }
7668
7669 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7670 {
7671 struct niu *np = netdev_priv(dev);
7672 int ret = 0;
7673
7674 switch (cmd->cmd) {
7675 case ETHTOOL_SRXFH:
7676 ret = niu_set_hash_opts(np, cmd);
7677 break;
7678 case ETHTOOL_SRXCLSRLINS:
7679 ret = niu_add_ethtool_tcam_entry(np, cmd);
7680 break;
7681 case ETHTOOL_SRXCLSRLDEL:
7682 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7683 break;
7684 default:
7685 ret = -EINVAL;
7686 break;
7687 }
7688
7689 return ret;
7690 }
7691
7692 static const struct {
7693 const char string[ETH_GSTRING_LEN];
7694 } niu_xmac_stat_keys[] = {
7695 { "tx_frames" },
7696 { "tx_bytes" },
7697 { "tx_fifo_errors" },
7698 { "tx_overflow_errors" },
7699 { "tx_max_pkt_size_errors" },
7700 { "tx_underflow_errors" },
7701 { "rx_local_faults" },
7702 { "rx_remote_faults" },
7703 { "rx_link_faults" },
7704 { "rx_align_errors" },
7705 { "rx_frags" },
7706 { "rx_mcasts" },
7707 { "rx_bcasts" },
7708 { "rx_hist_cnt1" },
7709 { "rx_hist_cnt2" },
7710 { "rx_hist_cnt3" },
7711 { "rx_hist_cnt4" },
7712 { "rx_hist_cnt5" },
7713 { "rx_hist_cnt6" },
7714 { "rx_hist_cnt7" },
7715 { "rx_octets" },
7716 { "rx_code_violations" },
7717 { "rx_len_errors" },
7718 { "rx_crc_errors" },
7719 { "rx_underflows" },
7720 { "rx_overflows" },
7721 { "pause_off_state" },
7722 { "pause_on_state" },
7723 { "pause_received" },
7724 };
7725
7726 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7727
7728 static const struct {
7729 const char string[ETH_GSTRING_LEN];
7730 } niu_bmac_stat_keys[] = {
7731 { "tx_underflow_errors" },
7732 { "tx_max_pkt_size_errors" },
7733 { "tx_bytes" },
7734 { "tx_frames" },
7735 { "rx_overflows" },
7736 { "rx_frames" },
7737 { "rx_align_errors" },
7738 { "rx_crc_errors" },
7739 { "rx_len_errors" },
7740 { "pause_off_state" },
7741 { "pause_on_state" },
7742 { "pause_received" },
7743 };
7744
7745 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7746
7747 static const struct {
7748 const char string[ETH_GSTRING_LEN];
7749 } niu_rxchan_stat_keys[] = {
7750 { "rx_channel" },
7751 { "rx_packets" },
7752 { "rx_bytes" },
7753 { "rx_dropped" },
7754 { "rx_errors" },
7755 };
7756
7757 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7758
7759 static const struct {
7760 const char string[ETH_GSTRING_LEN];
7761 } niu_txchan_stat_keys[] = {
7762 { "tx_channel" },
7763 { "tx_packets" },
7764 { "tx_bytes" },
7765 { "tx_errors" },
7766 };
7767
7768 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7769
7770 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7771 {
7772 struct niu *np = netdev_priv(dev);
7773 int i;
7774
7775 if (stringset != ETH_SS_STATS)
7776 return;
7777
7778 if (np->flags & NIU_FLAGS_XMAC) {
7779 memcpy(data, niu_xmac_stat_keys,
7780 sizeof(niu_xmac_stat_keys));
7781 data += sizeof(niu_xmac_stat_keys);
7782 } else {
7783 memcpy(data, niu_bmac_stat_keys,
7784 sizeof(niu_bmac_stat_keys));
7785 data += sizeof(niu_bmac_stat_keys);
7786 }
7787 for (i = 0; i < np->num_rx_rings; i++) {
7788 memcpy(data, niu_rxchan_stat_keys,
7789 sizeof(niu_rxchan_stat_keys));
7790 data += sizeof(niu_rxchan_stat_keys);
7791 }
7792 for (i = 0; i < np->num_tx_rings; i++) {
7793 memcpy(data, niu_txchan_stat_keys,
7794 sizeof(niu_txchan_stat_keys));
7795 data += sizeof(niu_txchan_stat_keys);
7796 }
7797 }
7798
7799 static int niu_get_sset_count(struct net_device *dev, int stringset)
7800 {
7801 struct niu *np = netdev_priv(dev);
7802
7803 if (stringset != ETH_SS_STATS)
7804 return -EINVAL;
7805
7806 return (np->flags & NIU_FLAGS_XMAC ?
7807 NUM_XMAC_STAT_KEYS :
7808 NUM_BMAC_STAT_KEYS) +
7809 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7810 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS);
7811 }
7812
7813 static void niu_get_ethtool_stats(struct net_device *dev,
7814 struct ethtool_stats *stats, u64 *data)
7815 {
7816 struct niu *np = netdev_priv(dev);
7817 int i;
7818
7819 niu_sync_mac_stats(np);
7820 if (np->flags & NIU_FLAGS_XMAC) {
7821 memcpy(data, &np->mac_stats.xmac,
7822 sizeof(struct niu_xmac_stats));
7823 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7824 } else {
7825 memcpy(data, &np->mac_stats.bmac,
7826 sizeof(struct niu_bmac_stats));
7827 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7828 }
7829 for (i = 0; i < np->num_rx_rings; i++) {
7830 struct rx_ring_info *rp = &np->rx_rings[i];
7831
7832 niu_sync_rx_discard_stats(np, rp, 0);
7833
7834 data[0] = rp->rx_channel;
7835 data[1] = rp->rx_packets;
7836 data[2] = rp->rx_bytes;
7837 data[3] = rp->rx_dropped;
7838 data[4] = rp->rx_errors;
7839 data += 5;
7840 }
7841 for (i = 0; i < np->num_tx_rings; i++) {
7842 struct tx_ring_info *rp = &np->tx_rings[i];
7843
7844 data[0] = rp->tx_channel;
7845 data[1] = rp->tx_packets;
7846 data[2] = rp->tx_bytes;
7847 data[3] = rp->tx_errors;
7848 data += 4;
7849 }
7850 }
7851
7852 static u64 niu_led_state_save(struct niu *np)
7853 {
7854 if (np->flags & NIU_FLAGS_XMAC)
7855 return nr64_mac(XMAC_CONFIG);
7856 else
7857 return nr64_mac(BMAC_XIF_CONFIG);
7858 }
7859
7860 static void niu_led_state_restore(struct niu *np, u64 val)
7861 {
7862 if (np->flags & NIU_FLAGS_XMAC)
7863 nw64_mac(XMAC_CONFIG, val);
7864 else
7865 nw64_mac(BMAC_XIF_CONFIG, val);
7866 }
7867
7868 static void niu_force_led(struct niu *np, int on)
7869 {
7870 u64 val, reg, bit;
7871
7872 if (np->flags & NIU_FLAGS_XMAC) {
7873 reg = XMAC_CONFIG;
7874 bit = XMAC_CONFIG_FORCE_LED_ON;
7875 } else {
7876 reg = BMAC_XIF_CONFIG;
7877 bit = BMAC_XIF_CONFIG_LINK_LED;
7878 }
7879
7880 val = nr64_mac(reg);
7881 if (on)
7882 val |= bit;
7883 else
7884 val &= ~bit;
7885 nw64_mac(reg, val);
7886 }
7887
7888 static int niu_set_phys_id(struct net_device *dev,
7889 enum ethtool_phys_id_state state)
7890
7891 {
7892 struct niu *np = netdev_priv(dev);
7893
7894 if (!netif_running(dev))
7895 return -EAGAIN;
7896
7897 switch (state) {
7898 case ETHTOOL_ID_ACTIVE:
7899 np->orig_led_state = niu_led_state_save(np);
7900 return 1; /* cycle on/off once per second */
7901
7902 case ETHTOOL_ID_ON:
7903 niu_force_led(np, 1);
7904 break;
7905
7906 case ETHTOOL_ID_OFF:
7907 niu_force_led(np, 0);
7908 break;
7909
7910 case ETHTOOL_ID_INACTIVE:
7911 niu_led_state_restore(np, np->orig_led_state);
7912 }
7913
7914 return 0;
7915 }
7916
7917 static const struct ethtool_ops niu_ethtool_ops = {
7918 .get_drvinfo = niu_get_drvinfo,
7919 .get_link = ethtool_op_get_link,
7920 .get_msglevel = niu_get_msglevel,
7921 .set_msglevel = niu_set_msglevel,
7922 .nway_reset = niu_nway_reset,
7923 .get_eeprom_len = niu_get_eeprom_len,
7924 .get_eeprom = niu_get_eeprom,
7925 .get_settings = niu_get_settings,
7926 .set_settings = niu_set_settings,
7927 .get_strings = niu_get_strings,
7928 .get_sset_count = niu_get_sset_count,
7929 .get_ethtool_stats = niu_get_ethtool_stats,
7930 .set_phys_id = niu_set_phys_id,
7931 .get_rxnfc = niu_get_nfc,
7932 .set_rxnfc = niu_set_nfc,
7933 };
7934
7935 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7936 int ldg, int ldn)
7937 {
7938 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7939 return -EINVAL;
7940 if (ldn < 0 || ldn > LDN_MAX)
7941 return -EINVAL;
7942
7943 parent->ldg_map[ldn] = ldg;
7944
7945 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7946 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7947 * the firmware, and we're not supposed to change them.
7948 * Validate the mapping, because if it's wrong we probably
7949 * won't get any interrupts and that's painful to debug.
7950 */
7951 if (nr64(LDG_NUM(ldn)) != ldg) {
7952 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7953 np->port, ldn, ldg,
7954 (unsigned long long) nr64(LDG_NUM(ldn)));
7955 return -EINVAL;
7956 }
7957 } else
7958 nw64(LDG_NUM(ldn), ldg);
7959
7960 return 0;
7961 }
7962
7963 static int niu_set_ldg_timer_res(struct niu *np, int res)
7964 {
7965 if (res < 0 || res > LDG_TIMER_RES_VAL)
7966 return -EINVAL;
7967
7968
7969 nw64(LDG_TIMER_RES, res);
7970
7971 return 0;
7972 }
7973
7974 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7975 {
7976 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7977 (func < 0 || func > 3) ||
7978 (vector < 0 || vector > 0x1f))
7979 return -EINVAL;
7980
7981 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7982
7983 return 0;
7984 }
7985
7986 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7987 {
7988 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7989 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7990 int limit;
7991
7992 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7993 return -EINVAL;
7994
7995 frame = frame_base;
7996 nw64(ESPC_PIO_STAT, frame);
7997 limit = 64;
7998 do {
7999 udelay(5);
8000 frame = nr64(ESPC_PIO_STAT);
8001 if (frame & ESPC_PIO_STAT_READ_END)
8002 break;
8003 } while (limit--);
8004 if (!(frame & ESPC_PIO_STAT_READ_END)) {
8005 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8006 (unsigned long long) frame);
8007 return -ENODEV;
8008 }
8009
8010 frame = frame_base;
8011 nw64(ESPC_PIO_STAT, frame);
8012 limit = 64;
8013 do {
8014 udelay(5);
8015 frame = nr64(ESPC_PIO_STAT);
8016 if (frame & ESPC_PIO_STAT_READ_END)
8017 break;
8018 } while (limit--);
8019 if (!(frame & ESPC_PIO_STAT_READ_END)) {
8020 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
8021 (unsigned long long) frame);
8022 return -ENODEV;
8023 }
8024
8025 frame = nr64(ESPC_PIO_STAT);
8026 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8027 }
8028
8029 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8030 {
8031 int err = niu_pci_eeprom_read(np, off);
8032 u16 val;
8033
8034 if (err < 0)
8035 return err;
8036 val = (err << 8);
8037 err = niu_pci_eeprom_read(np, off + 1);
8038 if (err < 0)
8039 return err;
8040 val |= (err & 0xff);
8041
8042 return val;
8043 }
8044
8045 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8046 {
8047 int err = niu_pci_eeprom_read(np, off);
8048 u16 val;
8049
8050 if (err < 0)
8051 return err;
8052
8053 val = (err & 0xff);
8054 err = niu_pci_eeprom_read(np, off + 1);
8055 if (err < 0)
8056 return err;
8057
8058 val |= (err & 0xff) << 8;
8059
8060 return val;
8061 }
8062
8063 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8064 u32 off,
8065 char *namebuf,
8066 int namebuf_len)
8067 {
8068 int i;
8069
8070 for (i = 0; i < namebuf_len; i++) {
8071 int err = niu_pci_eeprom_read(np, off + i);
8072 if (err < 0)
8073 return err;
8074 *namebuf++ = err;
8075 if (!err)
8076 break;
8077 }
8078 if (i >= namebuf_len)
8079 return -EINVAL;
8080
8081 return i + 1;
8082 }
8083
8084 static void __devinit niu_vpd_parse_version(struct niu *np)
8085 {
8086 struct niu_vpd *vpd = &np->vpd;
8087 int len = strlen(vpd->version) + 1;
8088 const char *s = vpd->version;
8089 int i;
8090
8091 for (i = 0; i < len - 5; i++) {
8092 if (!strncmp(s + i, "FCode ", 6))
8093 break;
8094 }
8095 if (i >= len - 5)
8096 return;
8097
8098 s += i + 5;
8099 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8100
8101 netif_printk(np, probe, KERN_DEBUG, np->dev,
8102 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8103 vpd->fcode_major, vpd->fcode_minor);
8104 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8105 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8106 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8107 np->flags |= NIU_FLAGS_VPD_VALID;
8108 }
8109
8110 /* ESPC_PIO_EN_ENABLE must be set */
8111 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8112 u32 start, u32 end)
8113 {
8114 unsigned int found_mask = 0;
8115 #define FOUND_MASK_MODEL 0x00000001
8116 #define FOUND_MASK_BMODEL 0x00000002
8117 #define FOUND_MASK_VERS 0x00000004
8118 #define FOUND_MASK_MAC 0x00000008
8119 #define FOUND_MASK_NMAC 0x00000010
8120 #define FOUND_MASK_PHY 0x00000020
8121 #define FOUND_MASK_ALL 0x0000003f
8122
8123 netif_printk(np, probe, KERN_DEBUG, np->dev,
8124 "VPD_SCAN: start[%x] end[%x]\n", start, end);
8125 while (start < end) {
8126 int len, err, prop_len;
8127 char namebuf[64];
8128 u8 *prop_buf;
8129 int max_len;
8130
8131 if (found_mask == FOUND_MASK_ALL) {
8132 niu_vpd_parse_version(np);
8133 return 1;
8134 }
8135
8136 err = niu_pci_eeprom_read(np, start + 2);
8137 if (err < 0)
8138 return err;
8139 len = err;
8140 start += 3;
8141
8142 prop_len = niu_pci_eeprom_read(np, start + 4);
8143 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8144 if (err < 0)
8145 return err;
8146
8147 prop_buf = NULL;
8148 max_len = 0;
8149 if (!strcmp(namebuf, "model")) {
8150 prop_buf = np->vpd.model;
8151 max_len = NIU_VPD_MODEL_MAX;
8152 found_mask |= FOUND_MASK_MODEL;
8153 } else if (!strcmp(namebuf, "board-model")) {
8154 prop_buf = np->vpd.board_model;
8155 max_len = NIU_VPD_BD_MODEL_MAX;
8156 found_mask |= FOUND_MASK_BMODEL;
8157 } else if (!strcmp(namebuf, "version")) {
8158 prop_buf = np->vpd.version;
8159 max_len = NIU_VPD_VERSION_MAX;
8160 found_mask |= FOUND_MASK_VERS;
8161 } else if (!strcmp(namebuf, "local-mac-address")) {
8162 prop_buf = np->vpd.local_mac;
8163 max_len = ETH_ALEN;
8164 found_mask |= FOUND_MASK_MAC;
8165 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8166 prop_buf = &np->vpd.mac_num;
8167 max_len = 1;
8168 found_mask |= FOUND_MASK_NMAC;
8169 } else if (!strcmp(namebuf, "phy-type")) {
8170 prop_buf = np->vpd.phy_type;
8171 max_len = NIU_VPD_PHY_TYPE_MAX;
8172 found_mask |= FOUND_MASK_PHY;
8173 }
8174
8175 if (max_len && prop_len > max_len) {
8176 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
8177 return -EINVAL;
8178 }
8179
8180 if (prop_buf) {
8181 u32 off = start + 5 + err;
8182 int i;
8183
8184 netif_printk(np, probe, KERN_DEBUG, np->dev,
8185 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8186 namebuf, prop_len);
8187 for (i = 0; i < prop_len; i++)
8188 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8189 }
8190
8191 start += len;
8192 }
8193
8194 return 0;
8195 }
8196
8197 /* ESPC_PIO_EN_ENABLE must be set */
8198 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8199 {
8200 u32 offset;
8201 int err;
8202
8203 err = niu_pci_eeprom_read16_swp(np, start + 1);
8204 if (err < 0)
8205 return;
8206
8207 offset = err + 3;
8208
8209 while (start + offset < ESPC_EEPROM_SIZE) {
8210 u32 here = start + offset;
8211 u32 end;
8212
8213 err = niu_pci_eeprom_read(np, here);
8214 if (err != 0x90)
8215 return;
8216
8217 err = niu_pci_eeprom_read16_swp(np, here + 1);
8218 if (err < 0)
8219 return;
8220
8221 here = start + offset + 3;
8222 end = start + offset + err;
8223
8224 offset += err;
8225
8226 err = niu_pci_vpd_scan_props(np, here, end);
8227 if (err < 0 || err == 1)
8228 return;
8229 }
8230 }
8231
8232 /* ESPC_PIO_EN_ENABLE must be set */
8233 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8234 {
8235 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8236 int err;
8237
8238 while (start < end) {
8239 ret = start;
8240
8241 /* ROM header signature? */
8242 err = niu_pci_eeprom_read16(np, start + 0);
8243 if (err != 0x55aa)
8244 return 0;
8245
8246 /* Apply offset to PCI data structure. */
8247 err = niu_pci_eeprom_read16(np, start + 23);
8248 if (err < 0)
8249 return 0;
8250 start += err;
8251
8252 /* Check for "PCIR" signature. */
8253 err = niu_pci_eeprom_read16(np, start + 0);
8254 if (err != 0x5043)
8255 return 0;
8256 err = niu_pci_eeprom_read16(np, start + 2);
8257 if (err != 0x4952)
8258 return 0;
8259
8260 /* Check for OBP image type. */
8261 err = niu_pci_eeprom_read(np, start + 20);
8262 if (err < 0)
8263 return 0;
8264 if (err != 0x01) {
8265 err = niu_pci_eeprom_read(np, ret + 2);
8266 if (err < 0)
8267 return 0;
8268
8269 start = ret + (err * 512);
8270 continue;
8271 }
8272
8273 err = niu_pci_eeprom_read16_swp(np, start + 8);
8274 if (err < 0)
8275 return err;
8276 ret += err;
8277
8278 err = niu_pci_eeprom_read(np, ret + 0);
8279 if (err != 0x82)
8280 return 0;
8281
8282 return ret;
8283 }
8284
8285 return 0;
8286 }
8287
8288 static int __devinit niu_phy_type_prop_decode(struct niu *np,
8289 const char *phy_prop)
8290 {
8291 if (!strcmp(phy_prop, "mif")) {
8292 /* 1G copper, MII */
8293 np->flags &= ~(NIU_FLAGS_FIBER |
8294 NIU_FLAGS_10G);
8295 np->mac_xcvr = MAC_XCVR_MII;
8296 } else if (!strcmp(phy_prop, "xgf")) {
8297 /* 10G fiber, XPCS */
8298 np->flags |= (NIU_FLAGS_10G |
8299 NIU_FLAGS_FIBER);
8300 np->mac_xcvr = MAC_XCVR_XPCS;
8301 } else if (!strcmp(phy_prop, "pcs")) {
8302 /* 1G fiber, PCS */
8303 np->flags &= ~NIU_FLAGS_10G;
8304 np->flags |= NIU_FLAGS_FIBER;
8305 np->mac_xcvr = MAC_XCVR_PCS;
8306 } else if (!strcmp(phy_prop, "xgc")) {
8307 /* 10G copper, XPCS */
8308 np->flags |= NIU_FLAGS_10G;
8309 np->flags &= ~NIU_FLAGS_FIBER;
8310 np->mac_xcvr = MAC_XCVR_XPCS;
8311 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8312 /* 10G Serdes or 1G Serdes, default to 10G */
8313 np->flags |= NIU_FLAGS_10G;
8314 np->flags &= ~NIU_FLAGS_FIBER;
8315 np->flags |= NIU_FLAGS_XCVR_SERDES;
8316 np->mac_xcvr = MAC_XCVR_XPCS;
8317 } else {
8318 return -EINVAL;
8319 }
8320 return 0;
8321 }
8322
8323 static int niu_pci_vpd_get_nports(struct niu *np)
8324 {
8325 int ports = 0;
8326
8327 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8328 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8329 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8330 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8331 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
8332 ports = 4;
8333 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8334 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8335 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8336 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
8337 ports = 2;
8338 }
8339
8340 return ports;
8341 }
8342
8343 static void __devinit niu_pci_vpd_validate(struct niu *np)
8344 {
8345 struct net_device *dev = np->dev;
8346 struct niu_vpd *vpd = &np->vpd;
8347 u8 val8;
8348
8349 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
8350 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
8351
8352 np->flags &= ~NIU_FLAGS_VPD_VALID;
8353 return;
8354 }
8355
8356 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8357 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8358 np->flags |= NIU_FLAGS_10G;
8359 np->flags &= ~NIU_FLAGS_FIBER;
8360 np->flags |= NIU_FLAGS_XCVR_SERDES;
8361 np->mac_xcvr = MAC_XCVR_PCS;
8362 if (np->port > 1) {
8363 np->flags |= NIU_FLAGS_FIBER;
8364 np->flags &= ~NIU_FLAGS_10G;
8365 }
8366 if (np->flags & NIU_FLAGS_10G)
8367 np->mac_xcvr = MAC_XCVR_XPCS;
8368 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8369 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8370 NIU_FLAGS_HOTPLUG_PHY);
8371 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8372 dev_err(np->device, "Illegal phy string [%s]\n",
8373 np->vpd.phy_type);
8374 dev_err(np->device, "Falling back to SPROM\n");
8375 np->flags &= ~NIU_FLAGS_VPD_VALID;
8376 return;
8377 }
8378
8379 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8380
8381 val8 = dev->perm_addr[5];
8382 dev->perm_addr[5] += np->port;
8383 if (dev->perm_addr[5] < val8)
8384 dev->perm_addr[4]++;
8385
8386 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8387 }
8388
8389 static int __devinit niu_pci_probe_sprom(struct niu *np)
8390 {
8391 struct net_device *dev = np->dev;
8392 int len, i;
8393 u64 val, sum;
8394 u8 val8;
8395
8396 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8397 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8398 len = val / 4;
8399
8400 np->eeprom_len = len;
8401
8402 netif_printk(np, probe, KERN_DEBUG, np->dev,
8403 "SPROM: Image size %llu\n", (unsigned long long)val);
8404
8405 sum = 0;
8406 for (i = 0; i < len; i++) {
8407 val = nr64(ESPC_NCR(i));
8408 sum += (val >> 0) & 0xff;
8409 sum += (val >> 8) & 0xff;
8410 sum += (val >> 16) & 0xff;
8411 sum += (val >> 24) & 0xff;
8412 }
8413 netif_printk(np, probe, KERN_DEBUG, np->dev,
8414 "SPROM: Checksum %x\n", (int)(sum & 0xff));
8415 if ((sum & 0xff) != 0xab) {
8416 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
8417 return -EINVAL;
8418 }
8419
8420 val = nr64(ESPC_PHY_TYPE);
8421 switch (np->port) {
8422 case 0:
8423 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8424 ESPC_PHY_TYPE_PORT0_SHIFT;
8425 break;
8426 case 1:
8427 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8428 ESPC_PHY_TYPE_PORT1_SHIFT;
8429 break;
8430 case 2:
8431 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8432 ESPC_PHY_TYPE_PORT2_SHIFT;
8433 break;
8434 case 3:
8435 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8436 ESPC_PHY_TYPE_PORT3_SHIFT;
8437 break;
8438 default:
8439 dev_err(np->device, "Bogus port number %u\n",
8440 np->port);
8441 return -EINVAL;
8442 }
8443 netif_printk(np, probe, KERN_DEBUG, np->dev,
8444 "SPROM: PHY type %x\n", val8);
8445
8446 switch (val8) {
8447 case ESPC_PHY_TYPE_1G_COPPER:
8448 /* 1G copper, MII */
8449 np->flags &= ~(NIU_FLAGS_FIBER |
8450 NIU_FLAGS_10G);
8451 np->mac_xcvr = MAC_XCVR_MII;
8452 break;
8453
8454 case ESPC_PHY_TYPE_1G_FIBER:
8455 /* 1G fiber, PCS */
8456 np->flags &= ~NIU_FLAGS_10G;
8457 np->flags |= NIU_FLAGS_FIBER;
8458 np->mac_xcvr = MAC_XCVR_PCS;
8459 break;
8460
8461 case ESPC_PHY_TYPE_10G_COPPER:
8462 /* 10G copper, XPCS */
8463 np->flags |= NIU_FLAGS_10G;
8464 np->flags &= ~NIU_FLAGS_FIBER;
8465 np->mac_xcvr = MAC_XCVR_XPCS;
8466 break;
8467
8468 case ESPC_PHY_TYPE_10G_FIBER:
8469 /* 10G fiber, XPCS */
8470 np->flags |= (NIU_FLAGS_10G |
8471 NIU_FLAGS_FIBER);
8472 np->mac_xcvr = MAC_XCVR_XPCS;
8473 break;
8474
8475 default:
8476 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
8477 return -EINVAL;
8478 }
8479
8480 val = nr64(ESPC_MAC_ADDR0);
8481 netif_printk(np, probe, KERN_DEBUG, np->dev,
8482 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8483 dev->perm_addr[0] = (val >> 0) & 0xff;
8484 dev->perm_addr[1] = (val >> 8) & 0xff;
8485 dev->perm_addr[2] = (val >> 16) & 0xff;
8486 dev->perm_addr[3] = (val >> 24) & 0xff;
8487
8488 val = nr64(ESPC_MAC_ADDR1);
8489 netif_printk(np, probe, KERN_DEBUG, np->dev,
8490 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8491 dev->perm_addr[4] = (val >> 0) & 0xff;
8492 dev->perm_addr[5] = (val >> 8) & 0xff;
8493
8494 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8495 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8496 dev->perm_addr);
8497 return -EINVAL;
8498 }
8499
8500 val8 = dev->perm_addr[5];
8501 dev->perm_addr[5] += np->port;
8502 if (dev->perm_addr[5] < val8)
8503 dev->perm_addr[4]++;
8504
8505 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8506
8507 val = nr64(ESPC_MOD_STR_LEN);
8508 netif_printk(np, probe, KERN_DEBUG, np->dev,
8509 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8510 if (val >= 8 * 4)
8511 return -EINVAL;
8512
8513 for (i = 0; i < val; i += 4) {
8514 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8515
8516 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8517 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8518 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8519 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8520 }
8521 np->vpd.model[val] = '\0';
8522
8523 val = nr64(ESPC_BD_MOD_STR_LEN);
8524 netif_printk(np, probe, KERN_DEBUG, np->dev,
8525 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8526 if (val >= 4 * 4)
8527 return -EINVAL;
8528
8529 for (i = 0; i < val; i += 4) {
8530 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8531
8532 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8533 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8534 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8535 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8536 }
8537 np->vpd.board_model[val] = '\0';
8538
8539 np->vpd.mac_num =
8540 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8541 netif_printk(np, probe, KERN_DEBUG, np->dev,
8542 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
8543
8544 return 0;
8545 }
8546
8547 static int __devinit niu_get_and_validate_port(struct niu *np)
8548 {
8549 struct niu_parent *parent = np->parent;
8550
8551 if (np->port <= 1)
8552 np->flags |= NIU_FLAGS_XMAC;
8553
8554 if (!parent->num_ports) {
8555 if (parent->plat_type == PLAT_TYPE_NIU) {
8556 parent->num_ports = 2;
8557 } else {
8558 parent->num_ports = niu_pci_vpd_get_nports(np);
8559 if (!parent->num_ports) {
8560 /* Fall back to SPROM as last resort.
8561 * This will fail on most cards.
8562 */
8563 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8564 ESPC_NUM_PORTS_MACS_VAL;
8565
8566 /* All of the current probing methods fail on
8567 * Maramba on-board parts.
8568 */
8569 if (!parent->num_ports)
8570 parent->num_ports = 4;
8571 }
8572 }
8573 }
8574
8575 if (np->port >= parent->num_ports)
8576 return -ENODEV;
8577
8578 return 0;
8579 }
8580
8581 static int __devinit phy_record(struct niu_parent *parent,
8582 struct phy_probe_info *p,
8583 int dev_id_1, int dev_id_2, u8 phy_port,
8584 int type)
8585 {
8586 u32 id = (dev_id_1 << 16) | dev_id_2;
8587 u8 idx;
8588
8589 if (dev_id_1 < 0 || dev_id_2 < 0)
8590 return 0;
8591 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
8592 /* Because of the NIU_PHY_ID_MASK being applied, the 8704
8593 * test covers the 8706 as well.
8594 */
8595 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
8596 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011))
8597 return 0;
8598 } else {
8599 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8600 return 0;
8601 }
8602
8603 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8604 parent->index, id,
8605 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8606 type == PHY_TYPE_PCS ? "PCS" : "MII",
8607 phy_port);
8608
8609 if (p->cur[type] >= NIU_MAX_PORTS) {
8610 pr_err("Too many PHY ports\n");
8611 return -EINVAL;
8612 }
8613 idx = p->cur[type];
8614 p->phy_id[type][idx] = id;
8615 p->phy_port[type][idx] = phy_port;
8616 p->cur[type] = idx + 1;
8617 return 0;
8618 }
8619
8620 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8621 {
8622 int i;
8623
8624 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8625 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8626 return 1;
8627 }
8628 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8629 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8630 return 1;
8631 }
8632
8633 return 0;
8634 }
8635
8636 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8637 {
8638 int port, cnt;
8639
8640 cnt = 0;
8641 *lowest = 32;
8642 for (port = 8; port < 32; port++) {
8643 if (port_has_10g(p, port)) {
8644 if (!cnt)
8645 *lowest = port;
8646 cnt++;
8647 }
8648 }
8649
8650 return cnt;
8651 }
8652
8653 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8654 {
8655 *lowest = 32;
8656 if (p->cur[PHY_TYPE_MII])
8657 *lowest = p->phy_port[PHY_TYPE_MII][0];
8658
8659 return p->cur[PHY_TYPE_MII];
8660 }
8661
8662 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8663 {
8664 int num_ports = parent->num_ports;
8665 int i;
8666
8667 for (i = 0; i < num_ports; i++) {
8668 parent->rxchan_per_port[i] = (16 / num_ports);
8669 parent->txchan_per_port[i] = (16 / num_ports);
8670
8671 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8672 parent->index, i,
8673 parent->rxchan_per_port[i],
8674 parent->txchan_per_port[i]);
8675 }
8676 }
8677
8678 static void __devinit niu_divide_channels(struct niu_parent *parent,
8679 int num_10g, int num_1g)
8680 {
8681 int num_ports = parent->num_ports;
8682 int rx_chans_per_10g, rx_chans_per_1g;
8683 int tx_chans_per_10g, tx_chans_per_1g;
8684 int i, tot_rx, tot_tx;
8685
8686 if (!num_10g || !num_1g) {
8687 rx_chans_per_10g = rx_chans_per_1g =
8688 (NIU_NUM_RXCHAN / num_ports);
8689 tx_chans_per_10g = tx_chans_per_1g =
8690 (NIU_NUM_TXCHAN / num_ports);
8691 } else {
8692 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8693 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8694 (rx_chans_per_1g * num_1g)) /
8695 num_10g;
8696
8697 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8698 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8699 (tx_chans_per_1g * num_1g)) /
8700 num_10g;
8701 }
8702
8703 tot_rx = tot_tx = 0;
8704 for (i = 0; i < num_ports; i++) {
8705 int type = phy_decode(parent->port_phy, i);
8706
8707 if (type == PORT_TYPE_10G) {
8708 parent->rxchan_per_port[i] = rx_chans_per_10g;
8709 parent->txchan_per_port[i] = tx_chans_per_10g;
8710 } else {
8711 parent->rxchan_per_port[i] = rx_chans_per_1g;
8712 parent->txchan_per_port[i] = tx_chans_per_1g;
8713 }
8714 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8715 parent->index, i,
8716 parent->rxchan_per_port[i],
8717 parent->txchan_per_port[i]);
8718 tot_rx += parent->rxchan_per_port[i];
8719 tot_tx += parent->txchan_per_port[i];
8720 }
8721
8722 if (tot_rx > NIU_NUM_RXCHAN) {
8723 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8724 parent->index, tot_rx);
8725 for (i = 0; i < num_ports; i++)
8726 parent->rxchan_per_port[i] = 1;
8727 }
8728 if (tot_tx > NIU_NUM_TXCHAN) {
8729 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8730 parent->index, tot_tx);
8731 for (i = 0; i < num_ports; i++)
8732 parent->txchan_per_port[i] = 1;
8733 }
8734 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
8735 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8736 parent->index, tot_rx, tot_tx);
8737 }
8738 }
8739
8740 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8741 int num_10g, int num_1g)
8742 {
8743 int i, num_ports = parent->num_ports;
8744 int rdc_group, rdc_groups_per_port;
8745 int rdc_channel_base;
8746
8747 rdc_group = 0;
8748 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8749
8750 rdc_channel_base = 0;
8751
8752 for (i = 0; i < num_ports; i++) {
8753 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8754 int grp, num_channels = parent->rxchan_per_port[i];
8755 int this_channel_offset;
8756
8757 tp->first_table_num = rdc_group;
8758 tp->num_tables = rdc_groups_per_port;
8759 this_channel_offset = 0;
8760 for (grp = 0; grp < tp->num_tables; grp++) {
8761 struct rdc_table *rt = &tp->tables[grp];
8762 int slot;
8763
8764 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8765 parent->index, i, tp->first_table_num + grp);
8766 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8767 rt->rxdma_channel[slot] =
8768 rdc_channel_base + this_channel_offset;
8769
8770 pr_cont("%d ", rt->rxdma_channel[slot]);
8771
8772 if (++this_channel_offset == num_channels)
8773 this_channel_offset = 0;
8774 }
8775 pr_cont("]\n");
8776 }
8777
8778 parent->rdc_default[i] = rdc_channel_base;
8779
8780 rdc_channel_base += num_channels;
8781 rdc_group += rdc_groups_per_port;
8782 }
8783 }
8784
8785 static int __devinit fill_phy_probe_info(struct niu *np,
8786 struct niu_parent *parent,
8787 struct phy_probe_info *info)
8788 {
8789 unsigned long flags;
8790 int port, err;
8791
8792 memset(info, 0, sizeof(*info));
8793
8794 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8795 niu_lock_parent(np, flags);
8796 err = 0;
8797 for (port = 8; port < 32; port++) {
8798 int dev_id_1, dev_id_2;
8799
8800 dev_id_1 = mdio_read(np, port,
8801 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8802 dev_id_2 = mdio_read(np, port,
8803 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8804 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8805 PHY_TYPE_PMA_PMD);
8806 if (err)
8807 break;
8808 dev_id_1 = mdio_read(np, port,
8809 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8810 dev_id_2 = mdio_read(np, port,
8811 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8812 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8813 PHY_TYPE_PCS);
8814 if (err)
8815 break;
8816 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8817 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8818 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8819 PHY_TYPE_MII);
8820 if (err)
8821 break;
8822 }
8823 niu_unlock_parent(np, flags);
8824
8825 return err;
8826 }
8827
8828 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8829 {
8830 struct phy_probe_info *info = &parent->phy_probe_info;
8831 int lowest_10g, lowest_1g;
8832 int num_10g, num_1g;
8833 u32 val;
8834 int err;
8835
8836 num_10g = num_1g = 0;
8837
8838 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8839 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
8840 num_10g = 0;
8841 num_1g = 2;
8842 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8843 parent->num_ports = 4;
8844 val = (phy_encode(PORT_TYPE_1G, 0) |
8845 phy_encode(PORT_TYPE_1G, 1) |
8846 phy_encode(PORT_TYPE_1G, 2) |
8847 phy_encode(PORT_TYPE_1G, 3));
8848 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
8849 num_10g = 2;
8850 num_1g = 0;
8851 parent->num_ports = 2;
8852 val = (phy_encode(PORT_TYPE_10G, 0) |
8853 phy_encode(PORT_TYPE_10G, 1));
8854 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8855 (parent->plat_type == PLAT_TYPE_NIU)) {
8856 /* this is the Monza case */
8857 if (np->flags & NIU_FLAGS_10G) {
8858 val = (phy_encode(PORT_TYPE_10G, 0) |
8859 phy_encode(PORT_TYPE_10G, 1));
8860 } else {
8861 val = (phy_encode(PORT_TYPE_1G, 0) |
8862 phy_encode(PORT_TYPE_1G, 1));
8863 }
8864 } else {
8865 err = fill_phy_probe_info(np, parent, info);
8866 if (err)
8867 return err;
8868
8869 num_10g = count_10g_ports(info, &lowest_10g);
8870 num_1g = count_1g_ports(info, &lowest_1g);
8871
8872 switch ((num_10g << 4) | num_1g) {
8873 case 0x24:
8874 if (lowest_1g == 10)
8875 parent->plat_type = PLAT_TYPE_VF_P0;
8876 else if (lowest_1g == 26)
8877 parent->plat_type = PLAT_TYPE_VF_P1;
8878 else
8879 goto unknown_vg_1g_port;
8880
8881 /* fallthru */
8882 case 0x22:
8883 val = (phy_encode(PORT_TYPE_10G, 0) |
8884 phy_encode(PORT_TYPE_10G, 1) |
8885 phy_encode(PORT_TYPE_1G, 2) |
8886 phy_encode(PORT_TYPE_1G, 3));
8887 break;
8888
8889 case 0x20:
8890 val = (phy_encode(PORT_TYPE_10G, 0) |
8891 phy_encode(PORT_TYPE_10G, 1));
8892 break;
8893
8894 case 0x10:
8895 val = phy_encode(PORT_TYPE_10G, np->port);
8896 break;
8897
8898 case 0x14:
8899 if (lowest_1g == 10)
8900 parent->plat_type = PLAT_TYPE_VF_P0;
8901 else if (lowest_1g == 26)
8902 parent->plat_type = PLAT_TYPE_VF_P1;
8903 else
8904 goto unknown_vg_1g_port;
8905
8906 /* fallthru */
8907 case 0x13:
8908 if ((lowest_10g & 0x7) == 0)
8909 val = (phy_encode(PORT_TYPE_10G, 0) |
8910 phy_encode(PORT_TYPE_1G, 1) |
8911 phy_encode(PORT_TYPE_1G, 2) |
8912 phy_encode(PORT_TYPE_1G, 3));
8913 else
8914 val = (phy_encode(PORT_TYPE_1G, 0) |
8915 phy_encode(PORT_TYPE_10G, 1) |
8916 phy_encode(PORT_TYPE_1G, 2) |
8917 phy_encode(PORT_TYPE_1G, 3));
8918 break;
8919
8920 case 0x04:
8921 if (lowest_1g == 10)
8922 parent->plat_type = PLAT_TYPE_VF_P0;
8923 else if (lowest_1g == 26)
8924 parent->plat_type = PLAT_TYPE_VF_P1;
8925 else
8926 goto unknown_vg_1g_port;
8927
8928 val = (phy_encode(PORT_TYPE_1G, 0) |
8929 phy_encode(PORT_TYPE_1G, 1) |
8930 phy_encode(PORT_TYPE_1G, 2) |
8931 phy_encode(PORT_TYPE_1G, 3));
8932 break;
8933
8934 default:
8935 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8936 num_10g, num_1g);
8937 return -EINVAL;
8938 }
8939 }
8940
8941 parent->port_phy = val;
8942
8943 if (parent->plat_type == PLAT_TYPE_NIU)
8944 niu_n2_divide_channels(parent);
8945 else
8946 niu_divide_channels(parent, num_10g, num_1g);
8947
8948 niu_divide_rdc_groups(parent, num_10g, num_1g);
8949
8950 return 0;
8951
8952 unknown_vg_1g_port:
8953 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
8954 return -EINVAL;
8955 }
8956
8957 static int __devinit niu_probe_ports(struct niu *np)
8958 {
8959 struct niu_parent *parent = np->parent;
8960 int err, i;
8961
8962 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8963 err = walk_phys(np, parent);
8964 if (err)
8965 return err;
8966
8967 niu_set_ldg_timer_res(np, 2);
8968 for (i = 0; i <= LDN_MAX; i++)
8969 niu_ldn_irq_enable(np, i, 0);
8970 }
8971
8972 if (parent->port_phy == PORT_PHY_INVALID)
8973 return -EINVAL;
8974
8975 return 0;
8976 }
8977
8978 static int __devinit niu_classifier_swstate_init(struct niu *np)
8979 {
8980 struct niu_classifier *cp = &np->clas;
8981
8982 cp->tcam_top = (u16) np->port;
8983 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
8984 cp->h1_init = 0xffffffff;
8985 cp->h2_init = 0xffff;
8986
8987 return fflp_early_init(np);
8988 }
8989
8990 static void __devinit niu_link_config_init(struct niu *np)
8991 {
8992 struct niu_link_config *lp = &np->link_config;
8993
8994 lp->advertising = (ADVERTISED_10baseT_Half |
8995 ADVERTISED_10baseT_Full |
8996 ADVERTISED_100baseT_Half |
8997 ADVERTISED_100baseT_Full |
8998 ADVERTISED_1000baseT_Half |
8999 ADVERTISED_1000baseT_Full |
9000 ADVERTISED_10000baseT_Full |
9001 ADVERTISED_Autoneg);
9002 lp->speed = lp->active_speed = SPEED_INVALID;
9003 lp->duplex = DUPLEX_FULL;
9004 lp->active_duplex = DUPLEX_INVALID;
9005 lp->autoneg = 1;
9006 #if 0
9007 lp->loopback_mode = LOOPBACK_MAC;
9008 lp->active_speed = SPEED_10000;
9009 lp->active_duplex = DUPLEX_FULL;
9010 #else
9011 lp->loopback_mode = LOOPBACK_DISABLED;
9012 #endif
9013 }
9014
9015 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
9016 {
9017 switch (np->port) {
9018 case 0:
9019 np->mac_regs = np->regs + XMAC_PORT0_OFF;
9020 np->ipp_off = 0x00000;
9021 np->pcs_off = 0x04000;
9022 np->xpcs_off = 0x02000;
9023 break;
9024
9025 case 1:
9026 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9027 np->ipp_off = 0x08000;
9028 np->pcs_off = 0x0a000;
9029 np->xpcs_off = 0x08000;
9030 break;
9031
9032 case 2:
9033 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9034 np->ipp_off = 0x04000;
9035 np->pcs_off = 0x0e000;
9036 np->xpcs_off = ~0UL;
9037 break;
9038
9039 case 3:
9040 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9041 np->ipp_off = 0x0c000;
9042 np->pcs_off = 0x12000;
9043 np->xpcs_off = ~0UL;
9044 break;
9045
9046 default:
9047 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9048 return -EINVAL;
9049 }
9050
9051 return 0;
9052 }
9053
9054 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9055 {
9056 struct msix_entry msi_vec[NIU_NUM_LDG];
9057 struct niu_parent *parent = np->parent;
9058 struct pci_dev *pdev = np->pdev;
9059 int i, num_irqs, err;
9060 u8 first_ldg;
9061
9062 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9063 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9064 ldg_num_map[i] = first_ldg + i;
9065
9066 num_irqs = (parent->rxchan_per_port[np->port] +
9067 parent->txchan_per_port[np->port] +
9068 (np->port == 0 ? 3 : 1));
9069 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9070
9071 retry:
9072 for (i = 0; i < num_irqs; i++) {
9073 msi_vec[i].vector = 0;
9074 msi_vec[i].entry = i;
9075 }
9076
9077 err = pci_enable_msix(pdev, msi_vec, num_irqs);
9078 if (err < 0) {
9079 np->flags &= ~NIU_FLAGS_MSIX;
9080 return;
9081 }
9082 if (err > 0) {
9083 num_irqs = err;
9084 goto retry;
9085 }
9086
9087 np->flags |= NIU_FLAGS_MSIX;
9088 for (i = 0; i < num_irqs; i++)
9089 np->ldg[i].irq = msi_vec[i].vector;
9090 np->num_ldg = num_irqs;
9091 }
9092
9093 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9094 {
9095 #ifdef CONFIG_SPARC64
9096 struct platform_device *op = np->op;
9097 const u32 *int_prop;
9098 int i;
9099
9100 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
9101 if (!int_prop)
9102 return -ENODEV;
9103
9104 for (i = 0; i < op->archdata.num_irqs; i++) {
9105 ldg_num_map[i] = int_prop[i];
9106 np->ldg[i].irq = op->archdata.irqs[i];
9107 }
9108
9109 np->num_ldg = op->archdata.num_irqs;
9110
9111 return 0;
9112 #else
9113 return -EINVAL;
9114 #endif
9115 }
9116
9117 static int __devinit niu_ldg_init(struct niu *np)
9118 {
9119 struct niu_parent *parent = np->parent;
9120 u8 ldg_num_map[NIU_NUM_LDG];
9121 int first_chan, num_chan;
9122 int i, err, ldg_rotor;
9123 u8 port;
9124
9125 np->num_ldg = 1;
9126 np->ldg[0].irq = np->dev->irq;
9127 if (parent->plat_type == PLAT_TYPE_NIU) {
9128 err = niu_n2_irq_init(np, ldg_num_map);
9129 if (err)
9130 return err;
9131 } else
9132 niu_try_msix(np, ldg_num_map);
9133
9134 port = np->port;
9135 for (i = 0; i < np->num_ldg; i++) {
9136 struct niu_ldg *lp = &np->ldg[i];
9137
9138 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9139
9140 lp->np = np;
9141 lp->ldg_num = ldg_num_map[i];
9142 lp->timer = 2; /* XXX */
9143
9144 /* On N2 NIU the firmware has setup the SID mappings so they go
9145 * to the correct values that will route the LDG to the proper
9146 * interrupt in the NCU interrupt table.
9147 */
9148 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9149 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9150 if (err)
9151 return err;
9152 }
9153 }
9154
9155 /* We adopt the LDG assignment ordering used by the N2 NIU
9156 * 'interrupt' properties because that simplifies a lot of
9157 * things. This ordering is:
9158 *
9159 * MAC
9160 * MIF (if port zero)
9161 * SYSERR (if port zero)
9162 * RX channels
9163 * TX channels
9164 */
9165
9166 ldg_rotor = 0;
9167
9168 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9169 LDN_MAC(port));
9170 if (err)
9171 return err;
9172
9173 ldg_rotor++;
9174 if (ldg_rotor == np->num_ldg)
9175 ldg_rotor = 0;
9176
9177 if (port == 0) {
9178 err = niu_ldg_assign_ldn(np, parent,
9179 ldg_num_map[ldg_rotor],
9180 LDN_MIF);
9181 if (err)
9182 return err;
9183
9184 ldg_rotor++;
9185 if (ldg_rotor == np->num_ldg)
9186 ldg_rotor = 0;
9187
9188 err = niu_ldg_assign_ldn(np, parent,
9189 ldg_num_map[ldg_rotor],
9190 LDN_DEVICE_ERROR);
9191 if (err)
9192 return err;
9193
9194 ldg_rotor++;
9195 if (ldg_rotor == np->num_ldg)
9196 ldg_rotor = 0;
9197
9198 }
9199
9200 first_chan = 0;
9201 for (i = 0; i < port; i++)
9202 first_chan += parent->rxchan_per_port[i];
9203 num_chan = parent->rxchan_per_port[port];
9204
9205 for (i = first_chan; i < (first_chan + num_chan); i++) {
9206 err = niu_ldg_assign_ldn(np, parent,
9207 ldg_num_map[ldg_rotor],
9208 LDN_RXDMA(i));
9209 if (err)
9210 return err;
9211 ldg_rotor++;
9212 if (ldg_rotor == np->num_ldg)
9213 ldg_rotor = 0;
9214 }
9215
9216 first_chan = 0;
9217 for (i = 0; i < port; i++)
9218 first_chan += parent->txchan_per_port[i];
9219 num_chan = parent->txchan_per_port[port];
9220 for (i = first_chan; i < (first_chan + num_chan); i++) {
9221 err = niu_ldg_assign_ldn(np, parent,
9222 ldg_num_map[ldg_rotor],
9223 LDN_TXDMA(i));
9224 if (err)
9225 return err;
9226 ldg_rotor++;
9227 if (ldg_rotor == np->num_ldg)
9228 ldg_rotor = 0;
9229 }
9230
9231 return 0;
9232 }
9233
9234 static void __devexit niu_ldg_free(struct niu *np)
9235 {
9236 if (np->flags & NIU_FLAGS_MSIX)
9237 pci_disable_msix(np->pdev);
9238 }
9239
9240 static int __devinit niu_get_of_props(struct niu *np)
9241 {
9242 #ifdef CONFIG_SPARC64
9243 struct net_device *dev = np->dev;
9244 struct device_node *dp;
9245 const char *phy_type;
9246 const u8 *mac_addr;
9247 const char *model;
9248 int prop_len;
9249
9250 if (np->parent->plat_type == PLAT_TYPE_NIU)
9251 dp = np->op->dev.of_node;
9252 else
9253 dp = pci_device_to_OF_node(np->pdev);
9254
9255 phy_type = of_get_property(dp, "phy-type", &prop_len);
9256 if (!phy_type) {
9257 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9258 dp->full_name);
9259 return -EINVAL;
9260 }
9261
9262 if (!strcmp(phy_type, "none"))
9263 return -ENODEV;
9264
9265 strcpy(np->vpd.phy_type, phy_type);
9266
9267 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
9268 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9269 dp->full_name, np->vpd.phy_type);
9270 return -EINVAL;
9271 }
9272
9273 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9274 if (!mac_addr) {
9275 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9276 dp->full_name);
9277 return -EINVAL;
9278 }
9279 if (prop_len != dev->addr_len) {
9280 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9281 dp->full_name, prop_len);
9282 }
9283 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9284 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
9285 netdev_err(dev, "%s: OF MAC address is invalid\n",
9286 dp->full_name);
9287 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
9288 return -EINVAL;
9289 }
9290
9291 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
9292
9293 model = of_get_property(dp, "model", &prop_len);
9294
9295 if (model)
9296 strcpy(np->vpd.model, model);
9297
9298 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9299 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9300 NIU_FLAGS_HOTPLUG_PHY);
9301 }
9302
9303 return 0;
9304 #else
9305 return -EINVAL;
9306 #endif
9307 }
9308
9309 static int __devinit niu_get_invariants(struct niu *np)
9310 {
9311 int err, have_props;
9312 u32 offset;
9313
9314 err = niu_get_of_props(np);
9315 if (err == -ENODEV)
9316 return err;
9317
9318 have_props = !err;
9319
9320 err = niu_init_mac_ipp_pcs_base(np);
9321 if (err)
9322 return err;
9323
9324 if (have_props) {
9325 err = niu_get_and_validate_port(np);
9326 if (err)
9327 return err;
9328
9329 } else {
9330 if (np->parent->plat_type == PLAT_TYPE_NIU)
9331 return -EINVAL;
9332
9333 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9334 offset = niu_pci_vpd_offset(np);
9335 netif_printk(np, probe, KERN_DEBUG, np->dev,
9336 "%s() VPD offset [%08x]\n", __func__, offset);
9337 if (offset)
9338 niu_pci_vpd_fetch(np, offset);
9339 nw64(ESPC_PIO_EN, 0);
9340
9341 if (np->flags & NIU_FLAGS_VPD_VALID) {
9342 niu_pci_vpd_validate(np);
9343 err = niu_get_and_validate_port(np);
9344 if (err)
9345 return err;
9346 }
9347
9348 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
9349 err = niu_get_and_validate_port(np);
9350 if (err)
9351 return err;
9352 err = niu_pci_probe_sprom(np);
9353 if (err)
9354 return err;
9355 }
9356 }
9357
9358 err = niu_probe_ports(np);
9359 if (err)
9360 return err;
9361
9362 niu_ldg_init(np);
9363
9364 niu_classifier_swstate_init(np);
9365 niu_link_config_init(np);
9366
9367 err = niu_determine_phy_disposition(np);
9368 if (!err)
9369 err = niu_init_link(np);
9370
9371 return err;
9372 }
9373
9374 static LIST_HEAD(niu_parent_list);
9375 static DEFINE_MUTEX(niu_parent_lock);
9376 static int niu_parent_index;
9377
9378 static ssize_t show_port_phy(struct device *dev,
9379 struct device_attribute *attr, char *buf)
9380 {
9381 struct platform_device *plat_dev = to_platform_device(dev);
9382 struct niu_parent *p = plat_dev->dev.platform_data;
9383 u32 port_phy = p->port_phy;
9384 char *orig_buf = buf;
9385 int i;
9386
9387 if (port_phy == PORT_PHY_UNKNOWN ||
9388 port_phy == PORT_PHY_INVALID)
9389 return 0;
9390
9391 for (i = 0; i < p->num_ports; i++) {
9392 const char *type_str;
9393 int type;
9394
9395 type = phy_decode(port_phy, i);
9396 if (type == PORT_TYPE_10G)
9397 type_str = "10G";
9398 else
9399 type_str = "1G";
9400 buf += sprintf(buf,
9401 (i == 0) ? "%s" : " %s",
9402 type_str);
9403 }
9404 buf += sprintf(buf, "\n");
9405 return buf - orig_buf;
9406 }
9407
9408 static ssize_t show_plat_type(struct device *dev,
9409 struct device_attribute *attr, char *buf)
9410 {
9411 struct platform_device *plat_dev = to_platform_device(dev);
9412 struct niu_parent *p = plat_dev->dev.platform_data;
9413 const char *type_str;
9414
9415 switch (p->plat_type) {
9416 case PLAT_TYPE_ATLAS:
9417 type_str = "atlas";
9418 break;
9419 case PLAT_TYPE_NIU:
9420 type_str = "niu";
9421 break;
9422 case PLAT_TYPE_VF_P0:
9423 type_str = "vf_p0";
9424 break;
9425 case PLAT_TYPE_VF_P1:
9426 type_str = "vf_p1";
9427 break;
9428 default:
9429 type_str = "unknown";
9430 break;
9431 }
9432
9433 return sprintf(buf, "%s\n", type_str);
9434 }
9435
9436 static ssize_t __show_chan_per_port(struct device *dev,
9437 struct device_attribute *attr, char *buf,
9438 int rx)
9439 {
9440 struct platform_device *plat_dev = to_platform_device(dev);
9441 struct niu_parent *p = plat_dev->dev.platform_data;
9442 char *orig_buf = buf;
9443 u8 *arr;
9444 int i;
9445
9446 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9447
9448 for (i = 0; i < p->num_ports; i++) {
9449 buf += sprintf(buf,
9450 (i == 0) ? "%d" : " %d",
9451 arr[i]);
9452 }
9453 buf += sprintf(buf, "\n");
9454
9455 return buf - orig_buf;
9456 }
9457
9458 static ssize_t show_rxchan_per_port(struct device *dev,
9459 struct device_attribute *attr, char *buf)
9460 {
9461 return __show_chan_per_port(dev, attr, buf, 1);
9462 }
9463
9464 static ssize_t show_txchan_per_port(struct device *dev,
9465 struct device_attribute *attr, char *buf)
9466 {
9467 return __show_chan_per_port(dev, attr, buf, 1);
9468 }
9469
9470 static ssize_t show_num_ports(struct device *dev,
9471 struct device_attribute *attr, char *buf)
9472 {
9473 struct platform_device *plat_dev = to_platform_device(dev);
9474 struct niu_parent *p = plat_dev->dev.platform_data;
9475
9476 return sprintf(buf, "%d\n", p->num_ports);
9477 }
9478
9479 static struct device_attribute niu_parent_attributes[] = {
9480 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9481 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9482 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9483 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9484 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9485 {}
9486 };
9487
9488 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9489 union niu_parent_id *id,
9490 u8 ptype)
9491 {
9492 struct platform_device *plat_dev;
9493 struct niu_parent *p;
9494 int i;
9495
9496 plat_dev = platform_device_register_simple("niu-board", niu_parent_index,
9497 NULL, 0);
9498 if (IS_ERR(plat_dev))
9499 return NULL;
9500
9501 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9502 int err = device_create_file(&plat_dev->dev,
9503 &niu_parent_attributes[i]);
9504 if (err)
9505 goto fail_unregister;
9506 }
9507
9508 p = kzalloc(sizeof(*p), GFP_KERNEL);
9509 if (!p)
9510 goto fail_unregister;
9511
9512 p->index = niu_parent_index++;
9513
9514 plat_dev->dev.platform_data = p;
9515 p->plat_dev = plat_dev;
9516
9517 memcpy(&p->id, id, sizeof(*id));
9518 p->plat_type = ptype;
9519 INIT_LIST_HEAD(&p->list);
9520 atomic_set(&p->refcnt, 0);
9521 list_add(&p->list, &niu_parent_list);
9522 spin_lock_init(&p->lock);
9523
9524 p->rxdma_clock_divider = 7500;
9525
9526 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9527 if (p->plat_type == PLAT_TYPE_NIU)
9528 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9529
9530 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9531 int index = i - CLASS_CODE_USER_PROG1;
9532
9533 p->tcam_key[index] = TCAM_KEY_TSEL;
9534 p->flow_key[index] = (FLOW_KEY_IPSA |
9535 FLOW_KEY_IPDA |
9536 FLOW_KEY_PROTO |
9537 (FLOW_KEY_L4_BYTE12 <<
9538 FLOW_KEY_L4_0_SHIFT) |
9539 (FLOW_KEY_L4_BYTE12 <<
9540 FLOW_KEY_L4_1_SHIFT));
9541 }
9542
9543 for (i = 0; i < LDN_MAX + 1; i++)
9544 p->ldg_map[i] = LDG_INVALID;
9545
9546 return p;
9547
9548 fail_unregister:
9549 platform_device_unregister(plat_dev);
9550 return NULL;
9551 }
9552
9553 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9554 union niu_parent_id *id,
9555 u8 ptype)
9556 {
9557 struct niu_parent *p, *tmp;
9558 int port = np->port;
9559
9560 mutex_lock(&niu_parent_lock);
9561 p = NULL;
9562 list_for_each_entry(tmp, &niu_parent_list, list) {
9563 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9564 p = tmp;
9565 break;
9566 }
9567 }
9568 if (!p)
9569 p = niu_new_parent(np, id, ptype);
9570
9571 if (p) {
9572 char port_name[6];
9573 int err;
9574
9575 sprintf(port_name, "port%d", port);
9576 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9577 &np->device->kobj,
9578 port_name);
9579 if (!err) {
9580 p->ports[port] = np;
9581 atomic_inc(&p->refcnt);
9582 }
9583 }
9584 mutex_unlock(&niu_parent_lock);
9585
9586 return p;
9587 }
9588
9589 static void niu_put_parent(struct niu *np)
9590 {
9591 struct niu_parent *p = np->parent;
9592 u8 port = np->port;
9593 char port_name[6];
9594
9595 BUG_ON(!p || p->ports[port] != np);
9596
9597 netif_printk(np, probe, KERN_DEBUG, np->dev,
9598 "%s() port[%u]\n", __func__, port);
9599
9600 sprintf(port_name, "port%d", port);
9601
9602 mutex_lock(&niu_parent_lock);
9603
9604 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9605
9606 p->ports[port] = NULL;
9607 np->parent = NULL;
9608
9609 if (atomic_dec_and_test(&p->refcnt)) {
9610 list_del(&p->list);
9611 platform_device_unregister(p->plat_dev);
9612 }
9613
9614 mutex_unlock(&niu_parent_lock);
9615 }
9616
9617 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9618 u64 *handle, gfp_t flag)
9619 {
9620 dma_addr_t dh;
9621 void *ret;
9622
9623 ret = dma_alloc_coherent(dev, size, &dh, flag);
9624 if (ret)
9625 *handle = dh;
9626 return ret;
9627 }
9628
9629 static void niu_pci_free_coherent(struct device *dev, size_t size,
9630 void *cpu_addr, u64 handle)
9631 {
9632 dma_free_coherent(dev, size, cpu_addr, handle);
9633 }
9634
9635 static u64 niu_pci_map_page(struct device *dev, struct page *page,
9636 unsigned long offset, size_t size,
9637 enum dma_data_direction direction)
9638 {
9639 return dma_map_page(dev, page, offset, size, direction);
9640 }
9641
9642 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9643 size_t size, enum dma_data_direction direction)
9644 {
9645 dma_unmap_page(dev, dma_address, size, direction);
9646 }
9647
9648 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9649 size_t size,
9650 enum dma_data_direction direction)
9651 {
9652 return dma_map_single(dev, cpu_addr, size, direction);
9653 }
9654
9655 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9656 size_t size,
9657 enum dma_data_direction direction)
9658 {
9659 dma_unmap_single(dev, dma_address, size, direction);
9660 }
9661
9662 static const struct niu_ops niu_pci_ops = {
9663 .alloc_coherent = niu_pci_alloc_coherent,
9664 .free_coherent = niu_pci_free_coherent,
9665 .map_page = niu_pci_map_page,
9666 .unmap_page = niu_pci_unmap_page,
9667 .map_single = niu_pci_map_single,
9668 .unmap_single = niu_pci_unmap_single,
9669 };
9670
9671 static void __devinit niu_driver_version(void)
9672 {
9673 static int niu_version_printed;
9674
9675 if (niu_version_printed++ == 0)
9676 pr_info("%s", version);
9677 }
9678
9679 static struct net_device * __devinit niu_alloc_and_init(
9680 struct device *gen_dev, struct pci_dev *pdev,
9681 struct platform_device *op, const struct niu_ops *ops,
9682 u8 port)
9683 {
9684 struct net_device *dev;
9685 struct niu *np;
9686
9687 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
9688 if (!dev) {
9689 dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
9690 return NULL;
9691 }
9692
9693 SET_NETDEV_DEV(dev, gen_dev);
9694
9695 np = netdev_priv(dev);
9696 np->dev = dev;
9697 np->pdev = pdev;
9698 np->op = op;
9699 np->device = gen_dev;
9700 np->ops = ops;
9701
9702 np->msg_enable = niu_debug;
9703
9704 spin_lock_init(&np->lock);
9705 INIT_WORK(&np->reset_task, niu_reset_task);
9706
9707 np->port = port;
9708
9709 return dev;
9710 }
9711
9712 static const struct net_device_ops niu_netdev_ops = {
9713 .ndo_open = niu_open,
9714 .ndo_stop = niu_close,
9715 .ndo_start_xmit = niu_start_xmit,
9716 .ndo_get_stats64 = niu_get_stats,
9717 .ndo_set_rx_mode = niu_set_rx_mode,
9718 .ndo_validate_addr = eth_validate_addr,
9719 .ndo_set_mac_address = niu_set_mac_addr,
9720 .ndo_do_ioctl = niu_ioctl,
9721 .ndo_tx_timeout = niu_tx_timeout,
9722 .ndo_change_mtu = niu_change_mtu,
9723 };
9724
9725 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9726 {
9727 dev->netdev_ops = &niu_netdev_ops;
9728 dev->ethtool_ops = &niu_ethtool_ops;
9729 dev->watchdog_timeo = NIU_TX_TIMEOUT;
9730 }
9731
9732 static void __devinit niu_device_announce(struct niu *np)
9733 {
9734 struct net_device *dev = np->dev;
9735
9736 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
9737
9738 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9739 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9740 dev->name,
9741 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9742 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9743 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9744 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9745 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9746 np->vpd.phy_type);
9747 } else {
9748 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9749 dev->name,
9750 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9751 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9752 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9753 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9754 "COPPER")),
9755 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9756 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9757 np->vpd.phy_type);
9758 }
9759 }
9760
9761 static void __devinit niu_set_basic_features(struct net_device *dev)
9762 {
9763 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH;
9764 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
9765 }
9766
9767 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9768 const struct pci_device_id *ent)
9769 {
9770 union niu_parent_id parent_id;
9771 struct net_device *dev;
9772 struct niu *np;
9773 int err, pos;
9774 u64 dma_mask;
9775 u16 val16;
9776
9777 niu_driver_version();
9778
9779 err = pci_enable_device(pdev);
9780 if (err) {
9781 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
9782 return err;
9783 }
9784
9785 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9786 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9787 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
9788 err = -ENODEV;
9789 goto err_out_disable_pdev;
9790 }
9791
9792 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9793 if (err) {
9794 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
9795 goto err_out_disable_pdev;
9796 }
9797
9798 pos = pci_pcie_cap(pdev);
9799 if (pos <= 0) {
9800 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
9801 goto err_out_free_res;
9802 }
9803
9804 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9805 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9806 if (!dev) {
9807 err = -ENOMEM;
9808 goto err_out_free_res;
9809 }
9810 np = netdev_priv(dev);
9811
9812 memset(&parent_id, 0, sizeof(parent_id));
9813 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9814 parent_id.pci.bus = pdev->bus->number;
9815 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9816
9817 np->parent = niu_get_parent(np, &parent_id,
9818 PLAT_TYPE_ATLAS);
9819 if (!np->parent) {
9820 err = -ENOMEM;
9821 goto err_out_free_dev;
9822 }
9823
9824 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9825 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9826 val16 |= (PCI_EXP_DEVCTL_CERE |
9827 PCI_EXP_DEVCTL_NFERE |
9828 PCI_EXP_DEVCTL_FERE |
9829 PCI_EXP_DEVCTL_URRE |
9830 PCI_EXP_DEVCTL_RELAX_EN);
9831 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9832
9833 dma_mask = DMA_BIT_MASK(44);
9834 err = pci_set_dma_mask(pdev, dma_mask);
9835 if (!err) {
9836 dev->features |= NETIF_F_HIGHDMA;
9837 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9838 if (err) {
9839 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9840 goto err_out_release_parent;
9841 }
9842 }
9843 if (err || dma_mask == DMA_BIT_MASK(32)) {
9844 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9845 if (err) {
9846 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
9847 goto err_out_release_parent;
9848 }
9849 }
9850
9851 niu_set_basic_features(dev);
9852
9853 dev->priv_flags |= IFF_UNICAST_FLT;
9854
9855 np->regs = pci_ioremap_bar(pdev, 0);
9856 if (!np->regs) {
9857 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
9858 err = -ENOMEM;
9859 goto err_out_release_parent;
9860 }
9861
9862 pci_set_master(pdev);
9863 pci_save_state(pdev);
9864
9865 dev->irq = pdev->irq;
9866
9867 niu_assign_netdev_ops(dev);
9868
9869 err = niu_get_invariants(np);
9870 if (err) {
9871 if (err != -ENODEV)
9872 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
9873 goto err_out_iounmap;
9874 }
9875
9876 err = register_netdev(dev);
9877 if (err) {
9878 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
9879 goto err_out_iounmap;
9880 }
9881
9882 pci_set_drvdata(pdev, dev);
9883
9884 niu_device_announce(np);
9885
9886 return 0;
9887
9888 err_out_iounmap:
9889 if (np->regs) {
9890 iounmap(np->regs);
9891 np->regs = NULL;
9892 }
9893
9894 err_out_release_parent:
9895 niu_put_parent(np);
9896
9897 err_out_free_dev:
9898 free_netdev(dev);
9899
9900 err_out_free_res:
9901 pci_release_regions(pdev);
9902
9903 err_out_disable_pdev:
9904 pci_disable_device(pdev);
9905 pci_set_drvdata(pdev, NULL);
9906
9907 return err;
9908 }
9909
9910 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9911 {
9912 struct net_device *dev = pci_get_drvdata(pdev);
9913
9914 if (dev) {
9915 struct niu *np = netdev_priv(dev);
9916
9917 unregister_netdev(dev);
9918 if (np->regs) {
9919 iounmap(np->regs);
9920 np->regs = NULL;
9921 }
9922
9923 niu_ldg_free(np);
9924
9925 niu_put_parent(np);
9926
9927 free_netdev(dev);
9928 pci_release_regions(pdev);
9929 pci_disable_device(pdev);
9930 pci_set_drvdata(pdev, NULL);
9931 }
9932 }
9933
9934 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9935 {
9936 struct net_device *dev = pci_get_drvdata(pdev);
9937 struct niu *np = netdev_priv(dev);
9938 unsigned long flags;
9939
9940 if (!netif_running(dev))
9941 return 0;
9942
9943 flush_work_sync(&np->reset_task);
9944 niu_netif_stop(np);
9945
9946 del_timer_sync(&np->timer);
9947
9948 spin_lock_irqsave(&np->lock, flags);
9949 niu_enable_interrupts(np, 0);
9950 spin_unlock_irqrestore(&np->lock, flags);
9951
9952 netif_device_detach(dev);
9953
9954 spin_lock_irqsave(&np->lock, flags);
9955 niu_stop_hw(np);
9956 spin_unlock_irqrestore(&np->lock, flags);
9957
9958 pci_save_state(pdev);
9959
9960 return 0;
9961 }
9962
9963 static int niu_resume(struct pci_dev *pdev)
9964 {
9965 struct net_device *dev = pci_get_drvdata(pdev);
9966 struct niu *np = netdev_priv(dev);
9967 unsigned long flags;
9968 int err;
9969
9970 if (!netif_running(dev))
9971 return 0;
9972
9973 pci_restore_state(pdev);
9974
9975 netif_device_attach(dev);
9976
9977 spin_lock_irqsave(&np->lock, flags);
9978
9979 err = niu_init_hw(np);
9980 if (!err) {
9981 np->timer.expires = jiffies + HZ;
9982 add_timer(&np->timer);
9983 niu_netif_start(np);
9984 }
9985
9986 spin_unlock_irqrestore(&np->lock, flags);
9987
9988 return err;
9989 }
9990
9991 static struct pci_driver niu_pci_driver = {
9992 .name = DRV_MODULE_NAME,
9993 .id_table = niu_pci_tbl,
9994 .probe = niu_pci_init_one,
9995 .remove = __devexit_p(niu_pci_remove_one),
9996 .suspend = niu_suspend,
9997 .resume = niu_resume,
9998 };
9999
10000 #ifdef CONFIG_SPARC64
10001 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
10002 u64 *dma_addr, gfp_t flag)
10003 {
10004 unsigned long order = get_order(size);
10005 unsigned long page = __get_free_pages(flag, order);
10006
10007 if (page == 0UL)
10008 return NULL;
10009 memset((char *)page, 0, PAGE_SIZE << order);
10010 *dma_addr = __pa(page);
10011
10012 return (void *) page;
10013 }
10014
10015 static void niu_phys_free_coherent(struct device *dev, size_t size,
10016 void *cpu_addr, u64 handle)
10017 {
10018 unsigned long order = get_order(size);
10019
10020 free_pages((unsigned long) cpu_addr, order);
10021 }
10022
10023 static u64 niu_phys_map_page(struct device *dev, struct page *page,
10024 unsigned long offset, size_t size,
10025 enum dma_data_direction direction)
10026 {
10027 return page_to_phys(page) + offset;
10028 }
10029
10030 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10031 size_t size, enum dma_data_direction direction)
10032 {
10033 /* Nothing to do. */
10034 }
10035
10036 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10037 size_t size,
10038 enum dma_data_direction direction)
10039 {
10040 return __pa(cpu_addr);
10041 }
10042
10043 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10044 size_t size,
10045 enum dma_data_direction direction)
10046 {
10047 /* Nothing to do. */
10048 }
10049
10050 static const struct niu_ops niu_phys_ops = {
10051 .alloc_coherent = niu_phys_alloc_coherent,
10052 .free_coherent = niu_phys_free_coherent,
10053 .map_page = niu_phys_map_page,
10054 .unmap_page = niu_phys_unmap_page,
10055 .map_single = niu_phys_map_single,
10056 .unmap_single = niu_phys_unmap_single,
10057 };
10058
10059 static int __devinit niu_of_probe(struct platform_device *op)
10060 {
10061 union niu_parent_id parent_id;
10062 struct net_device *dev;
10063 struct niu *np;
10064 const u32 *reg;
10065 int err;
10066
10067 niu_driver_version();
10068
10069 reg = of_get_property(op->dev.of_node, "reg", NULL);
10070 if (!reg) {
10071 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
10072 op->dev.of_node->full_name);
10073 return -ENODEV;
10074 }
10075
10076 dev = niu_alloc_and_init(&op->dev, NULL, op,
10077 &niu_phys_ops, reg[0] & 0x1);
10078 if (!dev) {
10079 err = -ENOMEM;
10080 goto err_out;
10081 }
10082 np = netdev_priv(dev);
10083
10084 memset(&parent_id, 0, sizeof(parent_id));
10085 parent_id.of = of_get_parent(op->dev.of_node);
10086
10087 np->parent = niu_get_parent(np, &parent_id,
10088 PLAT_TYPE_NIU);
10089 if (!np->parent) {
10090 err = -ENOMEM;
10091 goto err_out_free_dev;
10092 }
10093
10094 niu_set_basic_features(dev);
10095
10096 np->regs = of_ioremap(&op->resource[1], 0,
10097 resource_size(&op->resource[1]),
10098 "niu regs");
10099 if (!np->regs) {
10100 dev_err(&op->dev, "Cannot map device registers, aborting\n");
10101 err = -ENOMEM;
10102 goto err_out_release_parent;
10103 }
10104
10105 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
10106 resource_size(&op->resource[2]),
10107 "niu vregs-1");
10108 if (!np->vir_regs_1) {
10109 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
10110 err = -ENOMEM;
10111 goto err_out_iounmap;
10112 }
10113
10114 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
10115 resource_size(&op->resource[3]),
10116 "niu vregs-2");
10117 if (!np->vir_regs_2) {
10118 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
10119 err = -ENOMEM;
10120 goto err_out_iounmap;
10121 }
10122
10123 niu_assign_netdev_ops(dev);
10124
10125 err = niu_get_invariants(np);
10126 if (err) {
10127 if (err != -ENODEV)
10128 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
10129 goto err_out_iounmap;
10130 }
10131
10132 err = register_netdev(dev);
10133 if (err) {
10134 dev_err(&op->dev, "Cannot register net device, aborting\n");
10135 goto err_out_iounmap;
10136 }
10137
10138 dev_set_drvdata(&op->dev, dev);
10139
10140 niu_device_announce(np);
10141
10142 return 0;
10143
10144 err_out_iounmap:
10145 if (np->vir_regs_1) {
10146 of_iounmap(&op->resource[2], np->vir_regs_1,
10147 resource_size(&op->resource[2]));
10148 np->vir_regs_1 = NULL;
10149 }
10150
10151 if (np->vir_regs_2) {
10152 of_iounmap(&op->resource[3], np->vir_regs_2,
10153 resource_size(&op->resource[3]));
10154 np->vir_regs_2 = NULL;
10155 }
10156
10157 if (np->regs) {
10158 of_iounmap(&op->resource[1], np->regs,
10159 resource_size(&op->resource[1]));
10160 np->regs = NULL;
10161 }
10162
10163 err_out_release_parent:
10164 niu_put_parent(np);
10165
10166 err_out_free_dev:
10167 free_netdev(dev);
10168
10169 err_out:
10170 return err;
10171 }
10172
10173 static int __devexit niu_of_remove(struct platform_device *op)
10174 {
10175 struct net_device *dev = dev_get_drvdata(&op->dev);
10176
10177 if (dev) {
10178 struct niu *np = netdev_priv(dev);
10179
10180 unregister_netdev(dev);
10181
10182 if (np->vir_regs_1) {
10183 of_iounmap(&op->resource[2], np->vir_regs_1,
10184 resource_size(&op->resource[2]));
10185 np->vir_regs_1 = NULL;
10186 }
10187
10188 if (np->vir_regs_2) {
10189 of_iounmap(&op->resource[3], np->vir_regs_2,
10190 resource_size(&op->resource[3]));
10191 np->vir_regs_2 = NULL;
10192 }
10193
10194 if (np->regs) {
10195 of_iounmap(&op->resource[1], np->regs,
10196 resource_size(&op->resource[1]));
10197 np->regs = NULL;
10198 }
10199
10200 niu_ldg_free(np);
10201
10202 niu_put_parent(np);
10203
10204 free_netdev(dev);
10205 dev_set_drvdata(&op->dev, NULL);
10206 }
10207 return 0;
10208 }
10209
10210 static const struct of_device_id niu_match[] = {
10211 {
10212 .name = "network",
10213 .compatible = "SUNW,niusl",
10214 },
10215 {},
10216 };
10217 MODULE_DEVICE_TABLE(of, niu_match);
10218
10219 static struct platform_driver niu_of_driver = {
10220 .driver = {
10221 .name = "niu",
10222 .owner = THIS_MODULE,
10223 .of_match_table = niu_match,
10224 },
10225 .probe = niu_of_probe,
10226 .remove = __devexit_p(niu_of_remove),
10227 };
10228
10229 #endif /* CONFIG_SPARC64 */
10230
10231 static int __init niu_init(void)
10232 {
10233 int err = 0;
10234
10235 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
10236
10237 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10238
10239 #ifdef CONFIG_SPARC64
10240 err = platform_driver_register(&niu_of_driver);
10241 #endif
10242
10243 if (!err) {
10244 err = pci_register_driver(&niu_pci_driver);
10245 #ifdef CONFIG_SPARC64
10246 if (err)
10247 platform_driver_unregister(&niu_of_driver);
10248 #endif
10249 }
10250
10251 return err;
10252 }
10253
10254 static void __exit niu_exit(void)
10255 {
10256 pci_unregister_driver(&niu_pci_driver);
10257 #ifdef CONFIG_SPARC64
10258 platform_driver_unregister(&niu_of_driver);
10259 #endif
10260 }
10261
10262 module_init(niu_init);
10263 module_exit(niu_exit);
Linux kernel - Deliverables
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