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[deliverable/linux.git] / drivers / net / ethernet / ti / cpmac.c
1 /*
2 * Copyright (C) 2006, 2007 Eugene Konev
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/moduleparam.h>
22
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/types.h>
28 #include <linux/delay.h>
29
30 #include <linux/netdevice.h>
31 #include <linux/if_vlan.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/phy_fixed.h>
38 #include <linux/platform_device.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/clk.h>
41 #include <linux/gpio.h>
42 #include <linux/atomic.h>
43
44 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
45 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
46 MODULE_LICENSE("GPL");
47 MODULE_ALIAS("platform:cpmac");
48
49 static int debug_level = 8;
50 static int dumb_switch;
51
52 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
53 module_param(debug_level, int, 0444);
54 module_param(dumb_switch, int, 0444);
55
56 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
57 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
58
59 #define CPMAC_VERSION "0.5.2"
60 /* frame size + 802.1q tag + FCS size */
61 #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
62 #define CPMAC_QUEUES 8
63
64 /* Ethernet registers */
65 #define CPMAC_TX_CONTROL 0x0004
66 #define CPMAC_TX_TEARDOWN 0x0008
67 #define CPMAC_RX_CONTROL 0x0014
68 #define CPMAC_RX_TEARDOWN 0x0018
69 #define CPMAC_MBP 0x0100
70 #define MBP_RXPASSCRC 0x40000000
71 #define MBP_RXQOS 0x20000000
72 #define MBP_RXNOCHAIN 0x10000000
73 #define MBP_RXCMF 0x01000000
74 #define MBP_RXSHORT 0x00800000
75 #define MBP_RXCEF 0x00400000
76 #define MBP_RXPROMISC 0x00200000
77 #define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
78 #define MBP_RXBCAST 0x00002000
79 #define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
80 #define MBP_RXMCAST 0x00000020
81 #define MBP_MCASTCHAN(channel) ((channel) & 0x7)
82 #define CPMAC_UNICAST_ENABLE 0x0104
83 #define CPMAC_UNICAST_CLEAR 0x0108
84 #define CPMAC_MAX_LENGTH 0x010c
85 #define CPMAC_BUFFER_OFFSET 0x0110
86 #define CPMAC_MAC_CONTROL 0x0160
87 #define MAC_TXPTYPE 0x00000200
88 #define MAC_TXPACE 0x00000040
89 #define MAC_MII 0x00000020
90 #define MAC_TXFLOW 0x00000010
91 #define MAC_RXFLOW 0x00000008
92 #define MAC_MTEST 0x00000004
93 #define MAC_LOOPBACK 0x00000002
94 #define MAC_FDX 0x00000001
95 #define CPMAC_MAC_STATUS 0x0164
96 #define MAC_STATUS_QOS 0x00000004
97 #define MAC_STATUS_RXFLOW 0x00000002
98 #define MAC_STATUS_TXFLOW 0x00000001
99 #define CPMAC_TX_INT_ENABLE 0x0178
100 #define CPMAC_TX_INT_CLEAR 0x017c
101 #define CPMAC_MAC_INT_VECTOR 0x0180
102 #define MAC_INT_STATUS 0x00080000
103 #define MAC_INT_HOST 0x00040000
104 #define MAC_INT_RX 0x00020000
105 #define MAC_INT_TX 0x00010000
106 #define CPMAC_MAC_EOI_VECTOR 0x0184
107 #define CPMAC_RX_INT_ENABLE 0x0198
108 #define CPMAC_RX_INT_CLEAR 0x019c
109 #define CPMAC_MAC_INT_ENABLE 0x01a8
110 #define CPMAC_MAC_INT_CLEAR 0x01ac
111 #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
112 #define CPMAC_MAC_ADDR_MID 0x01d0
113 #define CPMAC_MAC_ADDR_HI 0x01d4
114 #define CPMAC_MAC_HASH_LO 0x01d8
115 #define CPMAC_MAC_HASH_HI 0x01dc
116 #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
117 #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
118 #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
119 #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
120 #define CPMAC_REG_END 0x0680
121 /*
122 * Rx/Tx statistics
123 * TODO: use some of them to fill stats in cpmac_stats()
124 */
125 #define CPMAC_STATS_RX_GOOD 0x0200
126 #define CPMAC_STATS_RX_BCAST 0x0204
127 #define CPMAC_STATS_RX_MCAST 0x0208
128 #define CPMAC_STATS_RX_PAUSE 0x020c
129 #define CPMAC_STATS_RX_CRC 0x0210
130 #define CPMAC_STATS_RX_ALIGN 0x0214
131 #define CPMAC_STATS_RX_OVER 0x0218
132 #define CPMAC_STATS_RX_JABBER 0x021c
133 #define CPMAC_STATS_RX_UNDER 0x0220
134 #define CPMAC_STATS_RX_FRAG 0x0224
135 #define CPMAC_STATS_RX_FILTER 0x0228
136 #define CPMAC_STATS_RX_QOSFILTER 0x022c
137 #define CPMAC_STATS_RX_OCTETS 0x0230
138
139 #define CPMAC_STATS_TX_GOOD 0x0234
140 #define CPMAC_STATS_TX_BCAST 0x0238
141 #define CPMAC_STATS_TX_MCAST 0x023c
142 #define CPMAC_STATS_TX_PAUSE 0x0240
143 #define CPMAC_STATS_TX_DEFER 0x0244
144 #define CPMAC_STATS_TX_COLLISION 0x0248
145 #define CPMAC_STATS_TX_SINGLECOLL 0x024c
146 #define CPMAC_STATS_TX_MULTICOLL 0x0250
147 #define CPMAC_STATS_TX_EXCESSCOLL 0x0254
148 #define CPMAC_STATS_TX_LATECOLL 0x0258
149 #define CPMAC_STATS_TX_UNDERRUN 0x025c
150 #define CPMAC_STATS_TX_CARRIERSENSE 0x0260
151 #define CPMAC_STATS_TX_OCTETS 0x0264
152
153 #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
154 #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
155 (reg)))
156
157 /* MDIO bus */
158 #define CPMAC_MDIO_VERSION 0x0000
159 #define CPMAC_MDIO_CONTROL 0x0004
160 #define MDIOC_IDLE 0x80000000
161 #define MDIOC_ENABLE 0x40000000
162 #define MDIOC_PREAMBLE 0x00100000
163 #define MDIOC_FAULT 0x00080000
164 #define MDIOC_FAULTDETECT 0x00040000
165 #define MDIOC_INTTEST 0x00020000
166 #define MDIOC_CLKDIV(div) ((div) & 0xff)
167 #define CPMAC_MDIO_ALIVE 0x0008
168 #define CPMAC_MDIO_LINK 0x000c
169 #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
170 #define MDIO_BUSY 0x80000000
171 #define MDIO_WRITE 0x40000000
172 #define MDIO_REG(reg) (((reg) & 0x1f) << 21)
173 #define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
174 #define MDIO_DATA(data) ((data) & 0xffff)
175 #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
176 #define PHYSEL_LINKSEL 0x00000040
177 #define PHYSEL_LINKINT 0x00000020
178
179 struct cpmac_desc {
180 u32 hw_next;
181 u32 hw_data;
182 u16 buflen;
183 u16 bufflags;
184 u16 datalen;
185 u16 dataflags;
186 #define CPMAC_SOP 0x8000
187 #define CPMAC_EOP 0x4000
188 #define CPMAC_OWN 0x2000
189 #define CPMAC_EOQ 0x1000
190 struct sk_buff *skb;
191 struct cpmac_desc *next;
192 struct cpmac_desc *prev;
193 dma_addr_t mapping;
194 dma_addr_t data_mapping;
195 };
196
197 struct cpmac_priv {
198 spinlock_t lock;
199 spinlock_t rx_lock;
200 struct cpmac_desc *rx_head;
201 int ring_size;
202 struct cpmac_desc *desc_ring;
203 dma_addr_t dma_ring;
204 void __iomem *regs;
205 struct mii_bus *mii_bus;
206 struct phy_device *phy;
207 char phy_name[MII_BUS_ID_SIZE + 3];
208 int oldlink, oldspeed, oldduplex;
209 u32 msg_enable;
210 struct net_device *dev;
211 struct work_struct reset_work;
212 struct platform_device *pdev;
213 struct napi_struct napi;
214 atomic_t reset_pending;
215 };
216
217 static irqreturn_t cpmac_irq(int, void *);
218 static void cpmac_hw_start(struct net_device *dev);
219 static void cpmac_hw_stop(struct net_device *dev);
220 static int cpmac_stop(struct net_device *dev);
221 static int cpmac_open(struct net_device *dev);
222
223 static void cpmac_dump_regs(struct net_device *dev)
224 {
225 int i;
226 struct cpmac_priv *priv = netdev_priv(dev);
227 for (i = 0; i < CPMAC_REG_END; i += 4) {
228 if (i % 16 == 0) {
229 if (i)
230 pr_cont("\n");
231 printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
232 priv->regs + i);
233 }
234 printk(" %08x", cpmac_read(priv->regs, i));
235 }
236 printk("\n");
237 }
238
239 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
240 {
241 int i;
242 printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
243 for (i = 0; i < sizeof(*desc) / 4; i++)
244 printk(" %08x", ((u32 *)desc)[i]);
245 printk("\n");
246 }
247
248 static void cpmac_dump_all_desc(struct net_device *dev)
249 {
250 struct cpmac_priv *priv = netdev_priv(dev);
251 struct cpmac_desc *dump = priv->rx_head;
252 do {
253 cpmac_dump_desc(dev, dump);
254 dump = dump->next;
255 } while (dump != priv->rx_head);
256 }
257
258 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
259 {
260 int i;
261 printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
262 for (i = 0; i < skb->len; i++) {
263 if (i % 16 == 0) {
264 if (i)
265 pr_cont("\n");
266 printk(KERN_DEBUG "%s: data[%p]:", dev->name,
267 skb->data + i);
268 }
269 printk(" %02x", ((u8 *)skb->data)[i]);
270 }
271 printk("\n");
272 }
273
274 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
275 {
276 u32 val;
277
278 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
279 cpu_relax();
280 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
281 MDIO_PHY(phy_id));
282 while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
283 cpu_relax();
284 return MDIO_DATA(val);
285 }
286
287 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
288 int reg, u16 val)
289 {
290 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
291 cpu_relax();
292 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
293 MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
294 return 0;
295 }
296
297 static int cpmac_mdio_reset(struct mii_bus *bus)
298 {
299 struct clk *cpmac_clk;
300
301 cpmac_clk = clk_get(&bus->dev, "cpmac");
302 if (IS_ERR(cpmac_clk)) {
303 printk(KERN_ERR "unable to get cpmac clock\n");
304 return -1;
305 }
306 ar7_device_reset(AR7_RESET_BIT_MDIO);
307 cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
308 MDIOC_CLKDIV(clk_get_rate(cpmac_clk) / 2200000 - 1));
309 return 0;
310 }
311
312 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
313
314 static struct mii_bus *cpmac_mii;
315
316 static void cpmac_set_multicast_list(struct net_device *dev)
317 {
318 struct netdev_hw_addr *ha;
319 u8 tmp;
320 u32 mbp, bit, hash[2] = { 0, };
321 struct cpmac_priv *priv = netdev_priv(dev);
322
323 mbp = cpmac_read(priv->regs, CPMAC_MBP);
324 if (dev->flags & IFF_PROMISC) {
325 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
326 MBP_RXPROMISC);
327 } else {
328 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
329 if (dev->flags & IFF_ALLMULTI) {
330 /* enable all multicast mode */
331 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
332 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
333 } else {
334 /*
335 * cpmac uses some strange mac address hashing
336 * (not crc32)
337 */
338 netdev_for_each_mc_addr(ha, dev) {
339 bit = 0;
340 tmp = ha->addr[0];
341 bit ^= (tmp >> 2) ^ (tmp << 4);
342 tmp = ha->addr[1];
343 bit ^= (tmp >> 4) ^ (tmp << 2);
344 tmp = ha->addr[2];
345 bit ^= (tmp >> 6) ^ tmp;
346 tmp = ha->addr[3];
347 bit ^= (tmp >> 2) ^ (tmp << 4);
348 tmp = ha->addr[4];
349 bit ^= (tmp >> 4) ^ (tmp << 2);
350 tmp = ha->addr[5];
351 bit ^= (tmp >> 6) ^ tmp;
352 bit &= 0x3f;
353 hash[bit / 32] |= 1 << (bit % 32);
354 }
355
356 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
357 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
358 }
359 }
360 }
361
362 static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
363 struct cpmac_desc *desc)
364 {
365 struct sk_buff *skb, *result = NULL;
366
367 if (unlikely(netif_msg_hw(priv)))
368 cpmac_dump_desc(priv->dev, desc);
369 cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
370 if (unlikely(!desc->datalen)) {
371 if (netif_msg_rx_err(priv) && net_ratelimit())
372 printk(KERN_WARNING "%s: rx: spurious interrupt\n",
373 priv->dev->name);
374 return NULL;
375 }
376
377 skb = netdev_alloc_skb_ip_align(priv->dev, CPMAC_SKB_SIZE);
378 if (likely(skb)) {
379 skb_put(desc->skb, desc->datalen);
380 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
381 skb_checksum_none_assert(desc->skb);
382 priv->dev->stats.rx_packets++;
383 priv->dev->stats.rx_bytes += desc->datalen;
384 result = desc->skb;
385 dma_unmap_single(&priv->dev->dev, desc->data_mapping,
386 CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
387 desc->skb = skb;
388 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
389 CPMAC_SKB_SIZE,
390 DMA_FROM_DEVICE);
391 desc->hw_data = (u32)desc->data_mapping;
392 if (unlikely(netif_msg_pktdata(priv))) {
393 printk(KERN_DEBUG "%s: received packet:\n",
394 priv->dev->name);
395 cpmac_dump_skb(priv->dev, result);
396 }
397 } else {
398 if (netif_msg_rx_err(priv) && net_ratelimit())
399 printk(KERN_WARNING
400 "%s: low on skbs, dropping packet\n",
401 priv->dev->name);
402 priv->dev->stats.rx_dropped++;
403 }
404
405 desc->buflen = CPMAC_SKB_SIZE;
406 desc->dataflags = CPMAC_OWN;
407
408 return result;
409 }
410
411 static int cpmac_poll(struct napi_struct *napi, int budget)
412 {
413 struct sk_buff *skb;
414 struct cpmac_desc *desc, *restart;
415 struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
416 int received = 0, processed = 0;
417
418 spin_lock(&priv->rx_lock);
419 if (unlikely(!priv->rx_head)) {
420 if (netif_msg_rx_err(priv) && net_ratelimit())
421 printk(KERN_WARNING "%s: rx: polling, but no queue\n",
422 priv->dev->name);
423 spin_unlock(&priv->rx_lock);
424 napi_complete(napi);
425 return 0;
426 }
427
428 desc = priv->rx_head;
429 restart = NULL;
430 while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
431 processed++;
432
433 if ((desc->dataflags & CPMAC_EOQ) != 0) {
434 /* The last update to eoq->hw_next didn't happen
435 * soon enough, and the receiver stopped here.
436 *Remember this descriptor so we can restart
437 * the receiver after freeing some space.
438 */
439 if (unlikely(restart)) {
440 if (netif_msg_rx_err(priv))
441 printk(KERN_ERR "%s: poll found a"
442 " duplicate EOQ: %p and %p\n",
443 priv->dev->name, restart, desc);
444 goto fatal_error;
445 }
446
447 restart = desc->next;
448 }
449
450 skb = cpmac_rx_one(priv, desc);
451 if (likely(skb)) {
452 netif_receive_skb(skb);
453 received++;
454 }
455 desc = desc->next;
456 }
457
458 if (desc != priv->rx_head) {
459 /* We freed some buffers, but not the whole ring,
460 * add what we did free to the rx list */
461 desc->prev->hw_next = (u32)0;
462 priv->rx_head->prev->hw_next = priv->rx_head->mapping;
463 }
464
465 /* Optimization: If we did not actually process an EOQ (perhaps because
466 * of quota limits), check to see if the tail of the queue has EOQ set.
467 * We should immediately restart in that case so that the receiver can
468 * restart and run in parallel with more packet processing.
469 * This lets us handle slightly larger bursts before running
470 * out of ring space (assuming dev->weight < ring_size) */
471
472 if (!restart &&
473 (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ))
474 == CPMAC_EOQ &&
475 (priv->rx_head->dataflags & CPMAC_OWN) != 0) {
476 /* reset EOQ so the poll loop (above) doesn't try to
477 * restart this when it eventually gets to this descriptor.
478 */
479 priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
480 restart = priv->rx_head;
481 }
482
483 if (restart) {
484 priv->dev->stats.rx_errors++;
485 priv->dev->stats.rx_fifo_errors++;
486 if (netif_msg_rx_err(priv) && net_ratelimit())
487 printk(KERN_WARNING "%s: rx dma ring overrun\n",
488 priv->dev->name);
489
490 if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
491 if (netif_msg_drv(priv))
492 printk(KERN_ERR "%s: cpmac_poll is trying to "
493 "restart rx from a descriptor that's "
494 "not free: %p\n",
495 priv->dev->name, restart);
496 goto fatal_error;
497 }
498
499 cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
500 }
501
502 priv->rx_head = desc;
503 spin_unlock(&priv->rx_lock);
504 if (unlikely(netif_msg_rx_status(priv)))
505 printk(KERN_DEBUG "%s: poll processed %d packets\n",
506 priv->dev->name, received);
507 if (processed == 0) {
508 /* we ran out of packets to read,
509 * revert to interrupt-driven mode */
510 napi_complete(napi);
511 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
512 return 0;
513 }
514
515 return 1;
516
517 fatal_error:
518 /* Something went horribly wrong.
519 * Reset hardware to try to recover rather than wedging. */
520
521 if (netif_msg_drv(priv)) {
522 printk(KERN_ERR "%s: cpmac_poll is confused. "
523 "Resetting hardware\n", priv->dev->name);
524 cpmac_dump_all_desc(priv->dev);
525 printk(KERN_DEBUG "%s: RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
526 priv->dev->name,
527 cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
528 cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
529 }
530
531 spin_unlock(&priv->rx_lock);
532 napi_complete(napi);
533 netif_tx_stop_all_queues(priv->dev);
534 napi_disable(&priv->napi);
535
536 atomic_inc(&priv->reset_pending);
537 cpmac_hw_stop(priv->dev);
538 if (!schedule_work(&priv->reset_work))
539 atomic_dec(&priv->reset_pending);
540 return 0;
541
542 }
543
544 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
545 {
546 int queue, len;
547 struct cpmac_desc *desc;
548 struct cpmac_priv *priv = netdev_priv(dev);
549
550 if (unlikely(atomic_read(&priv->reset_pending)))
551 return NETDEV_TX_BUSY;
552
553 if (unlikely(skb_padto(skb, ETH_ZLEN)))
554 return NETDEV_TX_OK;
555
556 len = max(skb->len, ETH_ZLEN);
557 queue = skb_get_queue_mapping(skb);
558 netif_stop_subqueue(dev, queue);
559
560 desc = &priv->desc_ring[queue];
561 if (unlikely(desc->dataflags & CPMAC_OWN)) {
562 if (netif_msg_tx_err(priv) && net_ratelimit())
563 printk(KERN_WARNING "%s: tx dma ring full\n",
564 dev->name);
565 return NETDEV_TX_BUSY;
566 }
567
568 spin_lock(&priv->lock);
569 spin_unlock(&priv->lock);
570 desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
571 desc->skb = skb;
572 desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
573 DMA_TO_DEVICE);
574 desc->hw_data = (u32)desc->data_mapping;
575 desc->datalen = len;
576 desc->buflen = len;
577 if (unlikely(netif_msg_tx_queued(priv)))
578 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
579 skb->len);
580 if (unlikely(netif_msg_hw(priv)))
581 cpmac_dump_desc(dev, desc);
582 if (unlikely(netif_msg_pktdata(priv)))
583 cpmac_dump_skb(dev, skb);
584 cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
585
586 return NETDEV_TX_OK;
587 }
588
589 static void cpmac_end_xmit(struct net_device *dev, int queue)
590 {
591 struct cpmac_desc *desc;
592 struct cpmac_priv *priv = netdev_priv(dev);
593
594 desc = &priv->desc_ring[queue];
595 cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
596 if (likely(desc->skb)) {
597 spin_lock(&priv->lock);
598 dev->stats.tx_packets++;
599 dev->stats.tx_bytes += desc->skb->len;
600 spin_unlock(&priv->lock);
601 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
602 DMA_TO_DEVICE);
603
604 if (unlikely(netif_msg_tx_done(priv)))
605 printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
606 desc->skb, desc->skb->len);
607
608 dev_kfree_skb_irq(desc->skb);
609 desc->skb = NULL;
610 if (__netif_subqueue_stopped(dev, queue))
611 netif_wake_subqueue(dev, queue);
612 } else {
613 if (netif_msg_tx_err(priv) && net_ratelimit())
614 printk(KERN_WARNING
615 "%s: end_xmit: spurious interrupt\n", dev->name);
616 if (__netif_subqueue_stopped(dev, queue))
617 netif_wake_subqueue(dev, queue);
618 }
619 }
620
621 static void cpmac_hw_stop(struct net_device *dev)
622 {
623 int i;
624 struct cpmac_priv *priv = netdev_priv(dev);
625 struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev);
626
627 ar7_device_reset(pdata->reset_bit);
628 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
629 cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
630 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
631 cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
632 for (i = 0; i < 8; i++) {
633 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
634 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
635 }
636 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
637 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
638 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
639 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
640 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
641 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
642 }
643
644 static void cpmac_hw_start(struct net_device *dev)
645 {
646 int i;
647 struct cpmac_priv *priv = netdev_priv(dev);
648 struct plat_cpmac_data *pdata = dev_get_platdata(&priv->pdev->dev);
649
650 ar7_device_reset(pdata->reset_bit);
651 for (i = 0; i < 8; i++) {
652 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
653 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
654 }
655 cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
656
657 cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
658 MBP_RXMCAST);
659 cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
660 for (i = 0; i < 8; i++)
661 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
662 cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
663 cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
664 (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
665 (dev->dev_addr[3] << 24));
666 cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
667 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
668 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
669 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
670 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
671 cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
672 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
673 cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
674 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
675
676 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
677 cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
678 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
679 cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
680 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
681 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
682 MAC_FDX);
683 }
684
685 static void cpmac_clear_rx(struct net_device *dev)
686 {
687 struct cpmac_priv *priv = netdev_priv(dev);
688 struct cpmac_desc *desc;
689 int i;
690 if (unlikely(!priv->rx_head))
691 return;
692 desc = priv->rx_head;
693 for (i = 0; i < priv->ring_size; i++) {
694 if ((desc->dataflags & CPMAC_OWN) == 0) {
695 if (netif_msg_rx_err(priv) && net_ratelimit())
696 printk(KERN_WARNING "%s: packet dropped\n",
697 dev->name);
698 if (unlikely(netif_msg_hw(priv)))
699 cpmac_dump_desc(dev, desc);
700 desc->dataflags = CPMAC_OWN;
701 dev->stats.rx_dropped++;
702 }
703 desc->hw_next = desc->next->mapping;
704 desc = desc->next;
705 }
706 priv->rx_head->prev->hw_next = 0;
707 }
708
709 static void cpmac_clear_tx(struct net_device *dev)
710 {
711 struct cpmac_priv *priv = netdev_priv(dev);
712 int i;
713 if (unlikely(!priv->desc_ring))
714 return;
715 for (i = 0; i < CPMAC_QUEUES; i++) {
716 priv->desc_ring[i].dataflags = 0;
717 if (priv->desc_ring[i].skb) {
718 dev_kfree_skb_any(priv->desc_ring[i].skb);
719 priv->desc_ring[i].skb = NULL;
720 }
721 }
722 }
723
724 static void cpmac_hw_error(struct work_struct *work)
725 {
726 struct cpmac_priv *priv =
727 container_of(work, struct cpmac_priv, reset_work);
728
729 spin_lock(&priv->rx_lock);
730 cpmac_clear_rx(priv->dev);
731 spin_unlock(&priv->rx_lock);
732 cpmac_clear_tx(priv->dev);
733 cpmac_hw_start(priv->dev);
734 barrier();
735 atomic_dec(&priv->reset_pending);
736
737 netif_tx_wake_all_queues(priv->dev);
738 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
739 }
740
741 static void cpmac_check_status(struct net_device *dev)
742 {
743 struct cpmac_priv *priv = netdev_priv(dev);
744
745 u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
746 int rx_channel = (macstatus >> 8) & 7;
747 int rx_code = (macstatus >> 12) & 15;
748 int tx_channel = (macstatus >> 16) & 7;
749 int tx_code = (macstatus >> 20) & 15;
750
751 if (rx_code || tx_code) {
752 if (netif_msg_drv(priv) && net_ratelimit()) {
753 /* Can't find any documentation on what these
754 *error codes actually are. So just log them and hope..
755 */
756 if (rx_code)
757 printk(KERN_WARNING "%s: host error %d on rx "
758 "channel %d (macstatus %08x), resetting\n",
759 dev->name, rx_code, rx_channel, macstatus);
760 if (tx_code)
761 printk(KERN_WARNING "%s: host error %d on tx "
762 "channel %d (macstatus %08x), resetting\n",
763 dev->name, tx_code, tx_channel, macstatus);
764 }
765
766 netif_tx_stop_all_queues(dev);
767 cpmac_hw_stop(dev);
768 if (schedule_work(&priv->reset_work))
769 atomic_inc(&priv->reset_pending);
770 if (unlikely(netif_msg_hw(priv)))
771 cpmac_dump_regs(dev);
772 }
773 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
774 }
775
776 static irqreturn_t cpmac_irq(int irq, void *dev_id)
777 {
778 struct net_device *dev = dev_id;
779 struct cpmac_priv *priv;
780 int queue;
781 u32 status;
782
783 priv = netdev_priv(dev);
784
785 status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
786
787 if (unlikely(netif_msg_intr(priv)))
788 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
789 status);
790
791 if (status & MAC_INT_TX)
792 cpmac_end_xmit(dev, (status & 7));
793
794 if (status & MAC_INT_RX) {
795 queue = (status >> 8) & 7;
796 if (napi_schedule_prep(&priv->napi)) {
797 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
798 __napi_schedule(&priv->napi);
799 }
800 }
801
802 cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
803
804 if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
805 cpmac_check_status(dev);
806
807 return IRQ_HANDLED;
808 }
809
810 static void cpmac_tx_timeout(struct net_device *dev)
811 {
812 struct cpmac_priv *priv = netdev_priv(dev);
813
814 spin_lock(&priv->lock);
815 dev->stats.tx_errors++;
816 spin_unlock(&priv->lock);
817 if (netif_msg_tx_err(priv) && net_ratelimit())
818 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
819
820 atomic_inc(&priv->reset_pending);
821 barrier();
822 cpmac_clear_tx(dev);
823 barrier();
824 atomic_dec(&priv->reset_pending);
825
826 netif_tx_wake_all_queues(priv->dev);
827 }
828
829 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
830 {
831 struct cpmac_priv *priv = netdev_priv(dev);
832 if (!(netif_running(dev)))
833 return -EINVAL;
834 if (!priv->phy)
835 return -EINVAL;
836
837 return phy_mii_ioctl(priv->phy, ifr, cmd);
838 }
839
840 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
841 {
842 struct cpmac_priv *priv = netdev_priv(dev);
843
844 if (priv->phy)
845 return phy_ethtool_gset(priv->phy, cmd);
846
847 return -EINVAL;
848 }
849
850 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
851 {
852 struct cpmac_priv *priv = netdev_priv(dev);
853
854 if (!capable(CAP_NET_ADMIN))
855 return -EPERM;
856
857 if (priv->phy)
858 return phy_ethtool_sset(priv->phy, cmd);
859
860 return -EINVAL;
861 }
862
863 static void cpmac_get_ringparam(struct net_device *dev,
864 struct ethtool_ringparam *ring)
865 {
866 struct cpmac_priv *priv = netdev_priv(dev);
867
868 ring->rx_max_pending = 1024;
869 ring->rx_mini_max_pending = 1;
870 ring->rx_jumbo_max_pending = 1;
871 ring->tx_max_pending = 1;
872
873 ring->rx_pending = priv->ring_size;
874 ring->rx_mini_pending = 1;
875 ring->rx_jumbo_pending = 1;
876 ring->tx_pending = 1;
877 }
878
879 static int cpmac_set_ringparam(struct net_device *dev,
880 struct ethtool_ringparam *ring)
881 {
882 struct cpmac_priv *priv = netdev_priv(dev);
883
884 if (netif_running(dev))
885 return -EBUSY;
886 priv->ring_size = ring->rx_pending;
887 return 0;
888 }
889
890 static void cpmac_get_drvinfo(struct net_device *dev,
891 struct ethtool_drvinfo *info)
892 {
893 strlcpy(info->driver, "cpmac", sizeof(info->driver));
894 strlcpy(info->version, CPMAC_VERSION, sizeof(info->version));
895 snprintf(info->bus_info, sizeof(info->bus_info), "%s", "cpmac");
896 info->regdump_len = 0;
897 }
898
899 static const struct ethtool_ops cpmac_ethtool_ops = {
900 .get_settings = cpmac_get_settings,
901 .set_settings = cpmac_set_settings,
902 .get_drvinfo = cpmac_get_drvinfo,
903 .get_link = ethtool_op_get_link,
904 .get_ringparam = cpmac_get_ringparam,
905 .set_ringparam = cpmac_set_ringparam,
906 };
907
908 static void cpmac_adjust_link(struct net_device *dev)
909 {
910 struct cpmac_priv *priv = netdev_priv(dev);
911 int new_state = 0;
912
913 spin_lock(&priv->lock);
914 if (priv->phy->link) {
915 netif_tx_start_all_queues(dev);
916 if (priv->phy->duplex != priv->oldduplex) {
917 new_state = 1;
918 priv->oldduplex = priv->phy->duplex;
919 }
920
921 if (priv->phy->speed != priv->oldspeed) {
922 new_state = 1;
923 priv->oldspeed = priv->phy->speed;
924 }
925
926 if (!priv->oldlink) {
927 new_state = 1;
928 priv->oldlink = 1;
929 }
930 } else if (priv->oldlink) {
931 new_state = 1;
932 priv->oldlink = 0;
933 priv->oldspeed = 0;
934 priv->oldduplex = -1;
935 }
936
937 if (new_state && netif_msg_link(priv) && net_ratelimit())
938 phy_print_status(priv->phy);
939
940 spin_unlock(&priv->lock);
941 }
942
943 static int cpmac_open(struct net_device *dev)
944 {
945 int i, size, res;
946 struct cpmac_priv *priv = netdev_priv(dev);
947 struct resource *mem;
948 struct cpmac_desc *desc;
949 struct sk_buff *skb;
950
951 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
952 if (!request_mem_region(mem->start, resource_size(mem), dev->name)) {
953 if (netif_msg_drv(priv))
954 printk(KERN_ERR "%s: failed to request registers\n",
955 dev->name);
956 res = -ENXIO;
957 goto fail_reserve;
958 }
959
960 priv->regs = ioremap(mem->start, resource_size(mem));
961 if (!priv->regs) {
962 if (netif_msg_drv(priv))
963 printk(KERN_ERR "%s: failed to remap registers\n",
964 dev->name);
965 res = -ENXIO;
966 goto fail_remap;
967 }
968
969 size = priv->ring_size + CPMAC_QUEUES;
970 priv->desc_ring = dma_alloc_coherent(&dev->dev,
971 sizeof(struct cpmac_desc) * size,
972 &priv->dma_ring,
973 GFP_KERNEL);
974 if (!priv->desc_ring) {
975 res = -ENOMEM;
976 goto fail_alloc;
977 }
978
979 for (i = 0; i < size; i++)
980 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
981
982 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
983 for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
984 skb = netdev_alloc_skb_ip_align(dev, CPMAC_SKB_SIZE);
985 if (unlikely(!skb)) {
986 res = -ENOMEM;
987 goto fail_desc;
988 }
989 desc->skb = skb;
990 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
991 CPMAC_SKB_SIZE,
992 DMA_FROM_DEVICE);
993 desc->hw_data = (u32)desc->data_mapping;
994 desc->buflen = CPMAC_SKB_SIZE;
995 desc->dataflags = CPMAC_OWN;
996 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
997 desc->next->prev = desc;
998 desc->hw_next = (u32)desc->next->mapping;
999 }
1000
1001 priv->rx_head->prev->hw_next = (u32)0;
1002
1003 res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED, dev->name, dev);
1004 if (res) {
1005 if (netif_msg_drv(priv))
1006 printk(KERN_ERR "%s: failed to obtain irq\n",
1007 dev->name);
1008 goto fail_irq;
1009 }
1010
1011 atomic_set(&priv->reset_pending, 0);
1012 INIT_WORK(&priv->reset_work, cpmac_hw_error);
1013 cpmac_hw_start(dev);
1014
1015 napi_enable(&priv->napi);
1016 priv->phy->state = PHY_CHANGELINK;
1017 phy_start(priv->phy);
1018
1019 return 0;
1020
1021 fail_irq:
1022 fail_desc:
1023 for (i = 0; i < priv->ring_size; i++) {
1024 if (priv->rx_head[i].skb) {
1025 dma_unmap_single(&dev->dev,
1026 priv->rx_head[i].data_mapping,
1027 CPMAC_SKB_SIZE,
1028 DMA_FROM_DEVICE);
1029 kfree_skb(priv->rx_head[i].skb);
1030 }
1031 }
1032 fail_alloc:
1033 kfree(priv->desc_ring);
1034 iounmap(priv->regs);
1035
1036 fail_remap:
1037 release_mem_region(mem->start, resource_size(mem));
1038
1039 fail_reserve:
1040 return res;
1041 }
1042
1043 static int cpmac_stop(struct net_device *dev)
1044 {
1045 int i;
1046 struct cpmac_priv *priv = netdev_priv(dev);
1047 struct resource *mem;
1048
1049 netif_tx_stop_all_queues(dev);
1050
1051 cancel_work_sync(&priv->reset_work);
1052 napi_disable(&priv->napi);
1053 phy_stop(priv->phy);
1054
1055 cpmac_hw_stop(dev);
1056
1057 for (i = 0; i < 8; i++)
1058 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
1059 cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
1060 cpmac_write(priv->regs, CPMAC_MBP, 0);
1061
1062 free_irq(dev->irq, dev);
1063 iounmap(priv->regs);
1064 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
1065 release_mem_region(mem->start, resource_size(mem));
1066 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1067 for (i = 0; i < priv->ring_size; i++) {
1068 if (priv->rx_head[i].skb) {
1069 dma_unmap_single(&dev->dev,
1070 priv->rx_head[i].data_mapping,
1071 CPMAC_SKB_SIZE,
1072 DMA_FROM_DEVICE);
1073 kfree_skb(priv->rx_head[i].skb);
1074 }
1075 }
1076
1077 dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
1078 (CPMAC_QUEUES + priv->ring_size),
1079 priv->desc_ring, priv->dma_ring);
1080 return 0;
1081 }
1082
1083 static const struct net_device_ops cpmac_netdev_ops = {
1084 .ndo_open = cpmac_open,
1085 .ndo_stop = cpmac_stop,
1086 .ndo_start_xmit = cpmac_start_xmit,
1087 .ndo_tx_timeout = cpmac_tx_timeout,
1088 .ndo_set_rx_mode = cpmac_set_multicast_list,
1089 .ndo_do_ioctl = cpmac_ioctl,
1090 .ndo_change_mtu = eth_change_mtu,
1091 .ndo_validate_addr = eth_validate_addr,
1092 .ndo_set_mac_address = eth_mac_addr,
1093 };
1094
1095 static int external_switch;
1096
1097 static int cpmac_probe(struct platform_device *pdev)
1098 {
1099 int rc, phy_id;
1100 char mdio_bus_id[MII_BUS_ID_SIZE];
1101 struct resource *mem;
1102 struct cpmac_priv *priv;
1103 struct net_device *dev;
1104 struct plat_cpmac_data *pdata;
1105
1106 pdata = dev_get_platdata(&pdev->dev);
1107
1108 if (external_switch || dumb_switch) {
1109 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */
1110 phy_id = pdev->id;
1111 } else {
1112 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1113 if (!(pdata->phy_mask & (1 << phy_id)))
1114 continue;
1115 if (!cpmac_mii->phy_map[phy_id])
1116 continue;
1117 strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
1118 break;
1119 }
1120 }
1121
1122 if (phy_id == PHY_MAX_ADDR) {
1123 dev_err(&pdev->dev, "no PHY present, falling back "
1124 "to switch on MDIO bus 0\n");
1125 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE); /* fixed phys bus */
1126 phy_id = pdev->id;
1127 }
1128
1129 dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1130 if (!dev)
1131 return -ENOMEM;
1132
1133 platform_set_drvdata(pdev, dev);
1134 priv = netdev_priv(dev);
1135
1136 priv->pdev = pdev;
1137 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1138 if (!mem) {
1139 rc = -ENODEV;
1140 goto fail;
1141 }
1142
1143 dev->irq = platform_get_irq_byname(pdev, "irq");
1144
1145 dev->netdev_ops = &cpmac_netdev_ops;
1146 dev->ethtool_ops = &cpmac_ethtool_ops;
1147
1148 netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1149
1150 spin_lock_init(&priv->lock);
1151 spin_lock_init(&priv->rx_lock);
1152 priv->dev = dev;
1153 priv->ring_size = 64;
1154 priv->msg_enable = netif_msg_init(debug_level, 0xff);
1155 memcpy(dev->dev_addr, pdata->dev_addr, sizeof(pdata->dev_addr));
1156
1157 snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
1158 mdio_bus_id, phy_id);
1159
1160 priv->phy = phy_connect(dev, priv->phy_name, cpmac_adjust_link,
1161 PHY_INTERFACE_MODE_MII);
1162
1163 if (IS_ERR(priv->phy)) {
1164 if (netif_msg_drv(priv))
1165 printk(KERN_ERR "%s: Could not attach to PHY\n",
1166 dev->name);
1167 rc = PTR_ERR(priv->phy);
1168 goto fail;
1169 }
1170
1171 rc = register_netdev(dev);
1172 if (rc) {
1173 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1174 dev->name);
1175 goto fail;
1176 }
1177
1178 if (netif_msg_probe(priv)) {
1179 printk(KERN_INFO
1180 "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
1181 "mac: %pM)\n", dev->name, (void *)mem->start, dev->irq,
1182 priv->phy_name, dev->dev_addr);
1183 }
1184 return 0;
1185
1186 fail:
1187 free_netdev(dev);
1188 return rc;
1189 }
1190
1191 static int cpmac_remove(struct platform_device *pdev)
1192 {
1193 struct net_device *dev = platform_get_drvdata(pdev);
1194 unregister_netdev(dev);
1195 free_netdev(dev);
1196 return 0;
1197 }
1198
1199 static struct platform_driver cpmac_driver = {
1200 .driver.name = "cpmac",
1201 .driver.owner = THIS_MODULE,
1202 .probe = cpmac_probe,
1203 .remove = cpmac_remove,
1204 };
1205
1206 int cpmac_init(void)
1207 {
1208 u32 mask;
1209 int i, res;
1210
1211 cpmac_mii = mdiobus_alloc();
1212 if (cpmac_mii == NULL)
1213 return -ENOMEM;
1214
1215 cpmac_mii->name = "cpmac-mii";
1216 cpmac_mii->read = cpmac_mdio_read;
1217 cpmac_mii->write = cpmac_mdio_write;
1218 cpmac_mii->reset = cpmac_mdio_reset;
1219 cpmac_mii->irq = mii_irqs;
1220
1221 cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256);
1222
1223 if (!cpmac_mii->priv) {
1224 printk(KERN_ERR "Can't ioremap mdio registers\n");
1225 res = -ENXIO;
1226 goto fail_alloc;
1227 }
1228
1229 #warning FIXME: unhardcode gpio&reset bits
1230 ar7_gpio_disable(26);
1231 ar7_gpio_disable(27);
1232 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1233 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1234 ar7_device_reset(AR7_RESET_BIT_EPHY);
1235
1236 cpmac_mii->reset(cpmac_mii);
1237
1238 for (i = 0; i < 300; i++) {
1239 mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE);
1240 if (mask)
1241 break;
1242 else
1243 msleep(10);
1244 }
1245
1246 mask &= 0x7fffffff;
1247 if (mask & (mask - 1)) {
1248 external_switch = 1;
1249 mask = 0;
1250 }
1251
1252 cpmac_mii->phy_mask = ~(mask | 0x80000000);
1253 snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "cpmac-1");
1254
1255 res = mdiobus_register(cpmac_mii);
1256 if (res)
1257 goto fail_mii;
1258
1259 res = platform_driver_register(&cpmac_driver);
1260 if (res)
1261 goto fail_cpmac;
1262
1263 return 0;
1264
1265 fail_cpmac:
1266 mdiobus_unregister(cpmac_mii);
1267
1268 fail_mii:
1269 iounmap(cpmac_mii->priv);
1270
1271 fail_alloc:
1272 mdiobus_free(cpmac_mii);
1273
1274 return res;
1275 }
1276
1277 void cpmac_exit(void)
1278 {
1279 platform_driver_unregister(&cpmac_driver);
1280 mdiobus_unregister(cpmac_mii);
1281 iounmap(cpmac_mii->priv);
1282 mdiobus_free(cpmac_mii);
1283 }
1284
1285 module_init(cpmac_init);
1286 module_exit(cpmac_exit);
Linux kernel - Deliverables
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