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[deliverable/linux.git] / drivers / net / ethernet / ti / cpsw.c
1 /*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/of.h>
33 #include <linux/of_net.h>
34 #include <linux/of_device.h>
35 #include <linux/if_vlan.h>
36
37 #include <linux/platform_data/cpsw.h>
38
39 #include "cpsw_ale.h"
40 #include "cpts.h"
41 #include "davinci_cpdma.h"
42
43 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
44 NETIF_MSG_DRV | NETIF_MSG_LINK | \
45 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
46 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
47 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
48 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
49 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
50 NETIF_MSG_RX_STATUS)
51
52 #define cpsw_info(priv, type, format, ...) \
53 do { \
54 if (netif_msg_##type(priv) && net_ratelimit()) \
55 dev_info(priv->dev, format, ## __VA_ARGS__); \
56 } while (0)
57
58 #define cpsw_err(priv, type, format, ...) \
59 do { \
60 if (netif_msg_##type(priv) && net_ratelimit()) \
61 dev_err(priv->dev, format, ## __VA_ARGS__); \
62 } while (0)
63
64 #define cpsw_dbg(priv, type, format, ...) \
65 do { \
66 if (netif_msg_##type(priv) && net_ratelimit()) \
67 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
68 } while (0)
69
70 #define cpsw_notice(priv, type, format, ...) \
71 do { \
72 if (netif_msg_##type(priv) && net_ratelimit()) \
73 dev_notice(priv->dev, format, ## __VA_ARGS__); \
74 } while (0)
75
76 #define ALE_ALL_PORTS 0x7
77
78 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
79 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
80 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
81
82 #define CPSW_VERSION_1 0x19010a
83 #define CPSW_VERSION_2 0x19010c
84
85 #define HOST_PORT_NUM 0
86 #define SLIVER_SIZE 0x40
87
88 #define CPSW1_HOST_PORT_OFFSET 0x028
89 #define CPSW1_SLAVE_OFFSET 0x050
90 #define CPSW1_SLAVE_SIZE 0x040
91 #define CPSW1_CPDMA_OFFSET 0x100
92 #define CPSW1_STATERAM_OFFSET 0x200
93 #define CPSW1_CPTS_OFFSET 0x500
94 #define CPSW1_ALE_OFFSET 0x600
95 #define CPSW1_SLIVER_OFFSET 0x700
96
97 #define CPSW2_HOST_PORT_OFFSET 0x108
98 #define CPSW2_SLAVE_OFFSET 0x200
99 #define CPSW2_SLAVE_SIZE 0x100
100 #define CPSW2_CPDMA_OFFSET 0x800
101 #define CPSW2_STATERAM_OFFSET 0xa00
102 #define CPSW2_CPTS_OFFSET 0xc00
103 #define CPSW2_ALE_OFFSET 0xd00
104 #define CPSW2_SLIVER_OFFSET 0xd80
105 #define CPSW2_BD_OFFSET 0x2000
106
107 #define CPDMA_RXTHRESH 0x0c0
108 #define CPDMA_RXFREE 0x0e0
109 #define CPDMA_TXHDP 0x00
110 #define CPDMA_RXHDP 0x20
111 #define CPDMA_TXCP 0x40
112 #define CPDMA_RXCP 0x60
113
114 #define CPSW_POLL_WEIGHT 64
115 #define CPSW_MIN_PACKET_SIZE 60
116 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
117
118 #define RX_PRIORITY_MAPPING 0x76543210
119 #define TX_PRIORITY_MAPPING 0x33221100
120 #define CPDMA_TX_PRIORITY_MAP 0x76543210
121
122 #define CPSW_VLAN_AWARE BIT(1)
123 #define CPSW_ALE_VLAN_AWARE 1
124
125 #define CPSW_FIFO_NORMAL_MODE (0 << 15)
126 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15)
127 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15)
128
129 #define CPSW_INTPACEEN (0x3f << 16)
130 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
131 #define CPSW_CMINTMAX_CNT 63
132 #define CPSW_CMINTMIN_CNT 2
133 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
134 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
135
136 #define cpsw_enable_irq(priv) \
137 do { \
138 u32 i; \
139 for (i = 0; i < priv->num_irqs; i++) \
140 enable_irq(priv->irqs_table[i]); \
141 } while (0);
142 #define cpsw_disable_irq(priv) \
143 do { \
144 u32 i; \
145 for (i = 0; i < priv->num_irqs; i++) \
146 disable_irq_nosync(priv->irqs_table[i]); \
147 } while (0);
148
149 #define cpsw_slave_index(priv) \
150 ((priv->data.dual_emac) ? priv->emac_port : \
151 priv->data.active_slave)
152
153 static int debug_level;
154 module_param(debug_level, int, 0);
155 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
156
157 static int ale_ageout = 10;
158 module_param(ale_ageout, int, 0);
159 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
160
161 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
162 module_param(rx_packet_max, int, 0);
163 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
164
165 struct cpsw_wr_regs {
166 u32 id_ver;
167 u32 soft_reset;
168 u32 control;
169 u32 int_control;
170 u32 rx_thresh_en;
171 u32 rx_en;
172 u32 tx_en;
173 u32 misc_en;
174 u32 mem_allign1[8];
175 u32 rx_thresh_stat;
176 u32 rx_stat;
177 u32 tx_stat;
178 u32 misc_stat;
179 u32 mem_allign2[8];
180 u32 rx_imax;
181 u32 tx_imax;
182
183 };
184
185 struct cpsw_ss_regs {
186 u32 id_ver;
187 u32 control;
188 u32 soft_reset;
189 u32 stat_port_en;
190 u32 ptype;
191 u32 soft_idle;
192 u32 thru_rate;
193 u32 gap_thresh;
194 u32 tx_start_wds;
195 u32 flow_control;
196 u32 vlan_ltype;
197 u32 ts_ltype;
198 u32 dlr_ltype;
199 };
200
201 /* CPSW_PORT_V1 */
202 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
203 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
204 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
205 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
206 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
207 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
208 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
209 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
210
211 /* CPSW_PORT_V2 */
212 #define CPSW2_CONTROL 0x00 /* Control Register */
213 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
214 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
215 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
216 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
217 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
218 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
219
220 /* CPSW_PORT_V1 and V2 */
221 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
222 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
223 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
224
225 /* CPSW_PORT_V2 only */
226 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
227 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
228 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
229 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
230 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
231 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
232 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
233 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
234
235 /* Bit definitions for the CPSW2_CONTROL register */
236 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
237 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
238 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
239 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
240 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
241 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
242 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
243 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
244 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
245 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
246 #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */
247 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
248 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
249 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
250 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
251 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
252
253 #define CTRL_TS_BITS \
254 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
255 TS_ANNEX_D_EN | TS_LTYPE1_EN)
256
257 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
258 #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN)
259 #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN)
260
261 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
262 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
263 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
264 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
265 #define TS_MSG_TYPE_EN_MASK (0xffff)
266
267 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
268 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
269
270 /* Bit definitions for the CPSW1_TS_CTL register */
271 #define CPSW_V1_TS_RX_EN BIT(0)
272 #define CPSW_V1_TS_TX_EN BIT(4)
273 #define CPSW_V1_MSG_TYPE_OFS 16
274
275 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
276 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
277
278 struct cpsw_host_regs {
279 u32 max_blks;
280 u32 blk_cnt;
281 u32 tx_in_ctl;
282 u32 port_vlan;
283 u32 tx_pri_map;
284 u32 cpdma_tx_pri_map;
285 u32 cpdma_rx_chan_map;
286 };
287
288 struct cpsw_sliver_regs {
289 u32 id_ver;
290 u32 mac_control;
291 u32 mac_status;
292 u32 soft_reset;
293 u32 rx_maxlen;
294 u32 __reserved_0;
295 u32 rx_pause;
296 u32 tx_pause;
297 u32 __reserved_1;
298 u32 rx_pri_map;
299 };
300
301 struct cpsw_slave {
302 void __iomem *regs;
303 struct cpsw_sliver_regs __iomem *sliver;
304 int slave_num;
305 u32 mac_control;
306 struct cpsw_slave_data *data;
307 struct phy_device *phy;
308 struct net_device *ndev;
309 u32 port_vlan;
310 u32 open_stat;
311 };
312
313 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
314 {
315 return __raw_readl(slave->regs + offset);
316 }
317
318 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
319 {
320 __raw_writel(val, slave->regs + offset);
321 }
322
323 struct cpsw_priv {
324 spinlock_t lock;
325 struct platform_device *pdev;
326 struct net_device *ndev;
327 struct resource *cpsw_res;
328 struct resource *cpsw_wr_res;
329 struct napi_struct napi;
330 struct device *dev;
331 struct cpsw_platform_data data;
332 struct cpsw_ss_regs __iomem *regs;
333 struct cpsw_wr_regs __iomem *wr_regs;
334 struct cpsw_host_regs __iomem *host_port_regs;
335 u32 msg_enable;
336 u32 version;
337 u32 coal_intvl;
338 u32 bus_freq_mhz;
339 struct net_device_stats stats;
340 int rx_packet_max;
341 int host_port;
342 struct clk *clk;
343 u8 mac_addr[ETH_ALEN];
344 struct cpsw_slave *slaves;
345 struct cpdma_ctlr *dma;
346 struct cpdma_chan *txch, *rxch;
347 struct cpsw_ale *ale;
348 /* snapshot of IRQ numbers */
349 u32 irqs_table[4];
350 u32 num_irqs;
351 struct cpts *cpts;
352 u32 emac_port;
353 };
354
355 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
356 #define for_each_slave(priv, func, arg...) \
357 do { \
358 int idx; \
359 if (priv->data.dual_emac) \
360 (func)((priv)->slaves + priv->emac_port, ##arg);\
361 else \
362 for (idx = 0; idx < (priv)->data.slaves; idx++) \
363 (func)((priv)->slaves + idx, ##arg); \
364 } while (0)
365 #define cpsw_get_slave_ndev(priv, __slave_no__) \
366 (priv->slaves[__slave_no__].ndev)
367 #define cpsw_get_slave_priv(priv, __slave_no__) \
368 ((priv->slaves[__slave_no__].ndev) ? \
369 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
370
371 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
372 do { \
373 if (!priv->data.dual_emac) \
374 break; \
375 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
376 ndev = cpsw_get_slave_ndev(priv, 0); \
377 priv = netdev_priv(ndev); \
378 skb->dev = ndev; \
379 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
380 ndev = cpsw_get_slave_ndev(priv, 1); \
381 priv = netdev_priv(ndev); \
382 skb->dev = ndev; \
383 } \
384 } while (0)
385 #define cpsw_add_mcast(priv, addr) \
386 do { \
387 if (priv->data.dual_emac) { \
388 struct cpsw_slave *slave = priv->slaves + \
389 priv->emac_port; \
390 int slave_port = cpsw_get_slave_port(priv, \
391 slave->slave_num); \
392 cpsw_ale_add_mcast(priv->ale, addr, \
393 1 << slave_port | 1 << priv->host_port, \
394 ALE_VLAN, slave->port_vlan, 0); \
395 } else { \
396 cpsw_ale_add_mcast(priv->ale, addr, \
397 ALE_ALL_PORTS << priv->host_port, \
398 0, 0, 0); \
399 } \
400 } while (0)
401
402 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
403 {
404 if (priv->host_port == 0)
405 return slave_num + 1;
406 else
407 return slave_num;
408 }
409
410 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
411 {
412 struct cpsw_priv *priv = netdev_priv(ndev);
413
414 if (ndev->flags & IFF_PROMISC) {
415 /* Enable promiscuous mode */
416 dev_err(priv->dev, "Ignoring Promiscuous mode\n");
417 return;
418 }
419
420 /* Clear all mcast from ALE */
421 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
422
423 if (!netdev_mc_empty(ndev)) {
424 struct netdev_hw_addr *ha;
425
426 /* program multicast address list into ALE register */
427 netdev_for_each_mc_addr(ha, ndev) {
428 cpsw_add_mcast(priv, (u8 *)ha->addr);
429 }
430 }
431 }
432
433 static void cpsw_intr_enable(struct cpsw_priv *priv)
434 {
435 __raw_writel(0xFF, &priv->wr_regs->tx_en);
436 __raw_writel(0xFF, &priv->wr_regs->rx_en);
437
438 cpdma_ctlr_int_ctrl(priv->dma, true);
439 return;
440 }
441
442 static void cpsw_intr_disable(struct cpsw_priv *priv)
443 {
444 __raw_writel(0, &priv->wr_regs->tx_en);
445 __raw_writel(0, &priv->wr_regs->rx_en);
446
447 cpdma_ctlr_int_ctrl(priv->dma, false);
448 return;
449 }
450
451 void cpsw_tx_handler(void *token, int len, int status)
452 {
453 struct sk_buff *skb = token;
454 struct net_device *ndev = skb->dev;
455 struct cpsw_priv *priv = netdev_priv(ndev);
456
457 /* Check whether the queue is stopped due to stalled tx dma, if the
458 * queue is stopped then start the queue as we have free desc for tx
459 */
460 if (unlikely(netif_queue_stopped(ndev)))
461 netif_wake_queue(ndev);
462 cpts_tx_timestamp(priv->cpts, skb);
463 priv->stats.tx_packets++;
464 priv->stats.tx_bytes += len;
465 dev_kfree_skb_any(skb);
466 }
467
468 void cpsw_rx_handler(void *token, int len, int status)
469 {
470 struct sk_buff *skb = token;
471 struct net_device *ndev = skb->dev;
472 struct cpsw_priv *priv = netdev_priv(ndev);
473 int ret = 0;
474
475 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
476
477 /* free and bail if we are shutting down */
478 if (unlikely(!netif_running(ndev)) ||
479 unlikely(!netif_carrier_ok(ndev))) {
480 dev_kfree_skb_any(skb);
481 return;
482 }
483 if (likely(status >= 0)) {
484 skb_put(skb, len);
485 cpts_rx_timestamp(priv->cpts, skb);
486 skb->protocol = eth_type_trans(skb, ndev);
487 netif_receive_skb(skb);
488 priv->stats.rx_bytes += len;
489 priv->stats.rx_packets++;
490 skb = NULL;
491 }
492
493 if (unlikely(!netif_running(ndev))) {
494 if (skb)
495 dev_kfree_skb_any(skb);
496 return;
497 }
498
499 if (likely(!skb)) {
500 skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
501 if (WARN_ON(!skb))
502 return;
503
504 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
505 skb_tailroom(skb), 0, GFP_KERNEL);
506 }
507 WARN_ON(ret < 0);
508 }
509
510 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
511 {
512 struct cpsw_priv *priv = dev_id;
513
514 if (likely(netif_running(priv->ndev))) {
515 cpsw_intr_disable(priv);
516 cpsw_disable_irq(priv);
517 napi_schedule(&priv->napi);
518 } else {
519 priv = cpsw_get_slave_priv(priv, 1);
520 if (likely(priv) && likely(netif_running(priv->ndev))) {
521 cpsw_intr_disable(priv);
522 cpsw_disable_irq(priv);
523 napi_schedule(&priv->napi);
524 }
525 }
526 return IRQ_HANDLED;
527 }
528
529 static int cpsw_poll(struct napi_struct *napi, int budget)
530 {
531 struct cpsw_priv *priv = napi_to_priv(napi);
532 int num_tx, num_rx;
533
534 num_tx = cpdma_chan_process(priv->txch, 128);
535 if (num_tx)
536 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
537
538 num_rx = cpdma_chan_process(priv->rxch, budget);
539 if (num_rx < budget) {
540 napi_complete(napi);
541 cpsw_intr_enable(priv);
542 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
543 cpsw_enable_irq(priv);
544 }
545
546 if (num_rx || num_tx)
547 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
548 num_rx, num_tx);
549
550 return num_rx;
551 }
552
553 static inline void soft_reset(const char *module, void __iomem *reg)
554 {
555 unsigned long timeout = jiffies + HZ;
556
557 __raw_writel(1, reg);
558 do {
559 cpu_relax();
560 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
561
562 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
563 }
564
565 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
566 ((mac)[2] << 16) | ((mac)[3] << 24))
567 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
568
569 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
570 struct cpsw_priv *priv)
571 {
572 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
573 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
574 }
575
576 static void _cpsw_adjust_link(struct cpsw_slave *slave,
577 struct cpsw_priv *priv, bool *link)
578 {
579 struct phy_device *phy = slave->phy;
580 u32 mac_control = 0;
581 u32 slave_port;
582
583 if (!phy)
584 return;
585
586 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
587
588 if (phy->link) {
589 mac_control = priv->data.mac_control;
590
591 /* enable forwarding */
592 cpsw_ale_control_set(priv->ale, slave_port,
593 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
594
595 if (phy->speed == 1000)
596 mac_control |= BIT(7); /* GIGABITEN */
597 if (phy->duplex)
598 mac_control |= BIT(0); /* FULLDUPLEXEN */
599
600 /* set speed_in input in case RMII mode is used in 100Mbps */
601 if (phy->speed == 100)
602 mac_control |= BIT(15);
603
604 *link = true;
605 } else {
606 mac_control = 0;
607 /* disable forwarding */
608 cpsw_ale_control_set(priv->ale, slave_port,
609 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
610 }
611
612 if (mac_control != slave->mac_control) {
613 phy_print_status(phy);
614 __raw_writel(mac_control, &slave->sliver->mac_control);
615 }
616
617 slave->mac_control = mac_control;
618 }
619
620 static void cpsw_adjust_link(struct net_device *ndev)
621 {
622 struct cpsw_priv *priv = netdev_priv(ndev);
623 bool link = false;
624
625 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
626
627 if (link) {
628 netif_carrier_on(ndev);
629 if (netif_running(ndev))
630 netif_wake_queue(ndev);
631 } else {
632 netif_carrier_off(ndev);
633 netif_stop_queue(ndev);
634 }
635 }
636
637 static int cpsw_get_coalesce(struct net_device *ndev,
638 struct ethtool_coalesce *coal)
639 {
640 struct cpsw_priv *priv = netdev_priv(ndev);
641
642 coal->rx_coalesce_usecs = priv->coal_intvl;
643 return 0;
644 }
645
646 static int cpsw_set_coalesce(struct net_device *ndev,
647 struct ethtool_coalesce *coal)
648 {
649 struct cpsw_priv *priv = netdev_priv(ndev);
650 u32 int_ctrl;
651 u32 num_interrupts = 0;
652 u32 prescale = 0;
653 u32 addnl_dvdr = 1;
654 u32 coal_intvl = 0;
655
656 if (!coal->rx_coalesce_usecs)
657 return -EINVAL;
658
659 coal_intvl = coal->rx_coalesce_usecs;
660
661 int_ctrl = readl(&priv->wr_regs->int_control);
662 prescale = priv->bus_freq_mhz * 4;
663
664 if (coal_intvl < CPSW_CMINTMIN_INTVL)
665 coal_intvl = CPSW_CMINTMIN_INTVL;
666
667 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
668 /* Interrupt pacer works with 4us Pulse, we can
669 * throttle further by dilating the 4us pulse.
670 */
671 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
672
673 if (addnl_dvdr > 1) {
674 prescale *= addnl_dvdr;
675 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
676 coal_intvl = (CPSW_CMINTMAX_INTVL
677 * addnl_dvdr);
678 } else {
679 addnl_dvdr = 1;
680 coal_intvl = CPSW_CMINTMAX_INTVL;
681 }
682 }
683
684 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
685 writel(num_interrupts, &priv->wr_regs->rx_imax);
686 writel(num_interrupts, &priv->wr_regs->tx_imax);
687
688 int_ctrl |= CPSW_INTPACEEN;
689 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
690 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
691 writel(int_ctrl, &priv->wr_regs->int_control);
692
693 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
694 if (priv->data.dual_emac) {
695 int i;
696
697 for (i = 0; i < priv->data.slaves; i++) {
698 priv = netdev_priv(priv->slaves[i].ndev);
699 priv->coal_intvl = coal_intvl;
700 }
701 } else {
702 priv->coal_intvl = coal_intvl;
703 }
704
705 return 0;
706 }
707
708 static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
709 {
710 static char *leader = "........................................";
711
712 if (!val)
713 return 0;
714 else
715 return snprintf(buf, maxlen, "%s %s %10d\n", name,
716 leader + strlen(name), val);
717 }
718
719 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
720 {
721 u32 i;
722 u32 usage_count = 0;
723
724 if (!priv->data.dual_emac)
725 return 0;
726
727 for (i = 0; i < priv->data.slaves; i++)
728 if (priv->slaves[i].open_stat)
729 usage_count++;
730
731 return usage_count;
732 }
733
734 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
735 struct cpsw_priv *priv, struct sk_buff *skb)
736 {
737 if (!priv->data.dual_emac)
738 return cpdma_chan_submit(priv->txch, skb, skb->data,
739 skb->len, 0, GFP_KERNEL);
740
741 if (ndev == cpsw_get_slave_ndev(priv, 0))
742 return cpdma_chan_submit(priv->txch, skb, skb->data,
743 skb->len, 1, GFP_KERNEL);
744 else
745 return cpdma_chan_submit(priv->txch, skb, skb->data,
746 skb->len, 2, GFP_KERNEL);
747 }
748
749 static inline void cpsw_add_dual_emac_def_ale_entries(
750 struct cpsw_priv *priv, struct cpsw_slave *slave,
751 u32 slave_port)
752 {
753 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
754
755 if (priv->version == CPSW_VERSION_1)
756 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
757 else
758 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
759 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
760 port_mask, port_mask, 0);
761 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
762 port_mask, ALE_VLAN, slave->port_vlan, 0);
763 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
764 priv->host_port, ALE_VLAN, slave->port_vlan);
765 }
766
767 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
768 {
769 char name[32];
770 u32 slave_port;
771
772 sprintf(name, "slave-%d", slave->slave_num);
773
774 soft_reset(name, &slave->sliver->soft_reset);
775
776 /* setup priority mapping */
777 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
778
779 switch (priv->version) {
780 case CPSW_VERSION_1:
781 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
782 break;
783 case CPSW_VERSION_2:
784 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
785 break;
786 }
787
788 /* setup max packet size, and mac address */
789 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
790 cpsw_set_slave_mac(slave, priv);
791
792 slave->mac_control = 0; /* no link yet */
793
794 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
795
796 if (priv->data.dual_emac)
797 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
798 else
799 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
800 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
801
802 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
803 &cpsw_adjust_link, slave->data->phy_if);
804 if (IS_ERR(slave->phy)) {
805 dev_err(priv->dev, "phy %s not found on slave %d\n",
806 slave->data->phy_id, slave->slave_num);
807 slave->phy = NULL;
808 } else {
809 dev_info(priv->dev, "phy found : id is : 0x%x\n",
810 slave->phy->phy_id);
811 phy_start(slave->phy);
812 }
813 }
814
815 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
816 {
817 const int vlan = priv->data.default_vlan;
818 const int port = priv->host_port;
819 u32 reg;
820 int i;
821
822 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
823 CPSW2_PORT_VLAN;
824
825 writel(vlan, &priv->host_port_regs->port_vlan);
826
827 for (i = 0; i < priv->data.slaves; i++)
828 slave_write(priv->slaves + i, vlan, reg);
829
830 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
831 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
832 (ALE_PORT_1 | ALE_PORT_2) << port);
833 }
834
835 static void cpsw_init_host_port(struct cpsw_priv *priv)
836 {
837 u32 control_reg;
838 u32 fifo_mode;
839
840 /* soft reset the controller and initialize ale */
841 soft_reset("cpsw", &priv->regs->soft_reset);
842 cpsw_ale_start(priv->ale);
843
844 /* switch to vlan unaware mode */
845 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
846 CPSW_ALE_VLAN_AWARE);
847 control_reg = readl(&priv->regs->control);
848 control_reg |= CPSW_VLAN_AWARE;
849 writel(control_reg, &priv->regs->control);
850 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
851 CPSW_FIFO_NORMAL_MODE;
852 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
853
854 /* setup host port priority mapping */
855 __raw_writel(CPDMA_TX_PRIORITY_MAP,
856 &priv->host_port_regs->cpdma_tx_pri_map);
857 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
858
859 cpsw_ale_control_set(priv->ale, priv->host_port,
860 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
861
862 if (!priv->data.dual_emac) {
863 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
864 0, 0);
865 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
866 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
867 }
868 }
869
870 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
871 {
872 if (!slave->phy)
873 return;
874 phy_stop(slave->phy);
875 phy_disconnect(slave->phy);
876 slave->phy = NULL;
877 }
878
879 static int cpsw_ndo_open(struct net_device *ndev)
880 {
881 struct cpsw_priv *priv = netdev_priv(ndev);
882 int i, ret;
883 u32 reg;
884
885 if (!cpsw_common_res_usage_state(priv))
886 cpsw_intr_disable(priv);
887 netif_carrier_off(ndev);
888
889 pm_runtime_get_sync(&priv->pdev->dev);
890
891 reg = priv->version;
892
893 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
894 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
895 CPSW_RTL_VERSION(reg));
896
897 /* initialize host and slave ports */
898 if (!cpsw_common_res_usage_state(priv))
899 cpsw_init_host_port(priv);
900 for_each_slave(priv, cpsw_slave_open, priv);
901
902 /* Add default VLAN */
903 if (!priv->data.dual_emac)
904 cpsw_add_default_vlan(priv);
905
906 if (!cpsw_common_res_usage_state(priv)) {
907 /* setup tx dma to fixed prio and zero offset */
908 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
909 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
910
911 /* disable priority elevation */
912 __raw_writel(0, &priv->regs->ptype);
913
914 /* enable statistics collection only on all ports */
915 __raw_writel(0x7, &priv->regs->stat_port_en);
916
917 if (WARN_ON(!priv->data.rx_descs))
918 priv->data.rx_descs = 128;
919
920 for (i = 0; i < priv->data.rx_descs; i++) {
921 struct sk_buff *skb;
922
923 ret = -ENOMEM;
924 skb = __netdev_alloc_skb_ip_align(priv->ndev,
925 priv->rx_packet_max, GFP_KERNEL);
926 if (!skb)
927 goto err_cleanup;
928 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
929 skb_tailroom(skb), 0, GFP_KERNEL);
930 if (ret < 0) {
931 kfree_skb(skb);
932 goto err_cleanup;
933 }
934 }
935 /* continue even if we didn't manage to submit all
936 * receive descs
937 */
938 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
939 }
940
941 /* Enable Interrupt pacing if configured */
942 if (priv->coal_intvl != 0) {
943 struct ethtool_coalesce coal;
944
945 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
946 cpsw_set_coalesce(ndev, &coal);
947 }
948
949 cpdma_ctlr_start(priv->dma);
950 cpsw_intr_enable(priv);
951 napi_enable(&priv->napi);
952 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
953 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
954
955 if (priv->data.dual_emac)
956 priv->slaves[priv->emac_port].open_stat = true;
957 return 0;
958
959 err_cleanup:
960 cpdma_ctlr_stop(priv->dma);
961 for_each_slave(priv, cpsw_slave_stop, priv);
962 pm_runtime_put_sync(&priv->pdev->dev);
963 netif_carrier_off(priv->ndev);
964 return ret;
965 }
966
967 static int cpsw_ndo_stop(struct net_device *ndev)
968 {
969 struct cpsw_priv *priv = netdev_priv(ndev);
970
971 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
972 netif_stop_queue(priv->ndev);
973 napi_disable(&priv->napi);
974 netif_carrier_off(priv->ndev);
975
976 if (cpsw_common_res_usage_state(priv) <= 1) {
977 cpsw_intr_disable(priv);
978 cpdma_ctlr_int_ctrl(priv->dma, false);
979 cpdma_ctlr_stop(priv->dma);
980 cpsw_ale_stop(priv->ale);
981 }
982 for_each_slave(priv, cpsw_slave_stop, priv);
983 pm_runtime_put_sync(&priv->pdev->dev);
984 if (priv->data.dual_emac)
985 priv->slaves[priv->emac_port].open_stat = false;
986 return 0;
987 }
988
989 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
990 struct net_device *ndev)
991 {
992 struct cpsw_priv *priv = netdev_priv(ndev);
993 int ret;
994
995 ndev->trans_start = jiffies;
996
997 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
998 cpsw_err(priv, tx_err, "packet pad failed\n");
999 priv->stats.tx_dropped++;
1000 return NETDEV_TX_OK;
1001 }
1002
1003 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1004 priv->cpts->tx_enable)
1005 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1006
1007 skb_tx_timestamp(skb);
1008
1009 ret = cpsw_tx_packet_submit(ndev, priv, skb);
1010 if (unlikely(ret != 0)) {
1011 cpsw_err(priv, tx_err, "desc submit failed\n");
1012 goto fail;
1013 }
1014
1015 /* If there is no more tx desc left free then we need to
1016 * tell the kernel to stop sending us tx frames.
1017 */
1018 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1019 netif_stop_queue(ndev);
1020
1021 return NETDEV_TX_OK;
1022 fail:
1023 priv->stats.tx_dropped++;
1024 netif_stop_queue(ndev);
1025 return NETDEV_TX_BUSY;
1026 }
1027
1028 static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
1029 {
1030 /*
1031 * The switch cannot operate in promiscuous mode without substantial
1032 * headache. For promiscuous mode to work, we would need to put the
1033 * ALE in bypass mode and route all traffic to the host port.
1034 * Subsequently, the host will need to operate as a "bridge", learn,
1035 * and flood as needed. For now, we simply complain here and
1036 * do nothing about it :-)
1037 */
1038 if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
1039 dev_err(&ndev->dev, "promiscuity ignored!\n");
1040
1041 /*
1042 * The switch cannot filter multicast traffic unless it is configured
1043 * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a
1044 * whole bunch of additional logic that this driver does not implement
1045 * at present.
1046 */
1047 if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
1048 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
1049 }
1050
1051 #ifdef CONFIG_TI_CPTS
1052
1053 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1054 {
1055 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1056 u32 ts_en, seq_id;
1057
1058 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1059 slave_write(slave, 0, CPSW1_TS_CTL);
1060 return;
1061 }
1062
1063 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1064 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1065
1066 if (priv->cpts->tx_enable)
1067 ts_en |= CPSW_V1_TS_TX_EN;
1068
1069 if (priv->cpts->rx_enable)
1070 ts_en |= CPSW_V1_TS_RX_EN;
1071
1072 slave_write(slave, ts_en, CPSW1_TS_CTL);
1073 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1074 }
1075
1076 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1077 {
1078 struct cpsw_slave *slave;
1079 u32 ctrl, mtype;
1080
1081 if (priv->data.dual_emac)
1082 slave = &priv->slaves[priv->emac_port];
1083 else
1084 slave = &priv->slaves[priv->data.active_slave];
1085
1086 ctrl = slave_read(slave, CPSW2_CONTROL);
1087 ctrl &= ~CTRL_ALL_TS_MASK;
1088
1089 if (priv->cpts->tx_enable)
1090 ctrl |= CTRL_TX_TS_BITS;
1091
1092 if (priv->cpts->rx_enable)
1093 ctrl |= CTRL_RX_TS_BITS;
1094
1095 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1096
1097 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1098 slave_write(slave, ctrl, CPSW2_CONTROL);
1099 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1100 }
1101
1102 static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
1103 {
1104 struct cpsw_priv *priv = netdev_priv(dev);
1105 struct cpts *cpts = priv->cpts;
1106 struct hwtstamp_config cfg;
1107
1108 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1109 return -EFAULT;
1110
1111 /* reserved for future extensions */
1112 if (cfg.flags)
1113 return -EINVAL;
1114
1115 switch (cfg.tx_type) {
1116 case HWTSTAMP_TX_OFF:
1117 cpts->tx_enable = 0;
1118 break;
1119 case HWTSTAMP_TX_ON:
1120 cpts->tx_enable = 1;
1121 break;
1122 default:
1123 return -ERANGE;
1124 }
1125
1126 switch (cfg.rx_filter) {
1127 case HWTSTAMP_FILTER_NONE:
1128 cpts->rx_enable = 0;
1129 break;
1130 case HWTSTAMP_FILTER_ALL:
1131 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1132 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1133 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1134 return -ERANGE;
1135 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1136 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1137 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1138 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1139 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1140 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1141 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1142 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1143 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1144 cpts->rx_enable = 1;
1145 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1146 break;
1147 default:
1148 return -ERANGE;
1149 }
1150
1151 switch (priv->version) {
1152 case CPSW_VERSION_1:
1153 cpsw_hwtstamp_v1(priv);
1154 break;
1155 case CPSW_VERSION_2:
1156 cpsw_hwtstamp_v2(priv);
1157 break;
1158 default:
1159 return -ENOTSUPP;
1160 }
1161
1162 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1163 }
1164
1165 #endif /*CONFIG_TI_CPTS*/
1166
1167 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1168 {
1169 struct cpsw_priv *priv = netdev_priv(dev);
1170 struct mii_ioctl_data *data = if_mii(req);
1171 int slave_no = cpsw_slave_index(priv);
1172
1173 if (!netif_running(dev))
1174 return -EINVAL;
1175
1176 switch (cmd) {
1177 #ifdef CONFIG_TI_CPTS
1178 case SIOCSHWTSTAMP:
1179 return cpsw_hwtstamp_ioctl(dev, req);
1180 #endif
1181 case SIOCGMIIPHY:
1182 data->phy_id = priv->slaves[slave_no].phy->addr;
1183 break;
1184 default:
1185 return -ENOTSUPP;
1186 }
1187
1188 return 0;
1189 }
1190
1191 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1192 {
1193 struct cpsw_priv *priv = netdev_priv(ndev);
1194
1195 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1196 priv->stats.tx_errors++;
1197 cpsw_intr_disable(priv);
1198 cpdma_ctlr_int_ctrl(priv->dma, false);
1199 cpdma_chan_stop(priv->txch);
1200 cpdma_chan_start(priv->txch);
1201 cpdma_ctlr_int_ctrl(priv->dma, true);
1202 cpsw_intr_enable(priv);
1203 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1204 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1205
1206 }
1207
1208 static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
1209 {
1210 struct cpsw_priv *priv = netdev_priv(ndev);
1211 return &priv->stats;
1212 }
1213
1214 #ifdef CONFIG_NET_POLL_CONTROLLER
1215 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1216 {
1217 struct cpsw_priv *priv = netdev_priv(ndev);
1218
1219 cpsw_intr_disable(priv);
1220 cpdma_ctlr_int_ctrl(priv->dma, false);
1221 cpsw_interrupt(ndev->irq, priv);
1222 cpdma_ctlr_int_ctrl(priv->dma, true);
1223 cpsw_intr_enable(priv);
1224 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1225 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1226
1227 }
1228 #endif
1229
1230 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1231 unsigned short vid)
1232 {
1233 int ret;
1234
1235 ret = cpsw_ale_add_vlan(priv->ale, vid,
1236 ALE_ALL_PORTS << priv->host_port,
1237 0, ALE_ALL_PORTS << priv->host_port,
1238 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
1239 if (ret != 0)
1240 return ret;
1241
1242 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1243 priv->host_port, ALE_VLAN, vid);
1244 if (ret != 0)
1245 goto clean_vid;
1246
1247 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1248 ALE_ALL_PORTS << priv->host_port,
1249 ALE_VLAN, vid, 0);
1250 if (ret != 0)
1251 goto clean_vlan_ucast;
1252 return 0;
1253
1254 clean_vlan_ucast:
1255 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1256 priv->host_port, ALE_VLAN, vid);
1257 clean_vid:
1258 cpsw_ale_del_vlan(priv->ale, vid, 0);
1259 return ret;
1260 }
1261
1262 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1263 __be16 proto, u16 vid)
1264 {
1265 struct cpsw_priv *priv = netdev_priv(ndev);
1266
1267 if (vid == priv->data.default_vlan)
1268 return 0;
1269
1270 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1271 return cpsw_add_vlan_ale_entry(priv, vid);
1272 }
1273
1274 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1275 __be16 proto, u16 vid)
1276 {
1277 struct cpsw_priv *priv = netdev_priv(ndev);
1278 int ret;
1279
1280 if (vid == priv->data.default_vlan)
1281 return 0;
1282
1283 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1284 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1285 if (ret != 0)
1286 return ret;
1287
1288 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1289 priv->host_port, ALE_VLAN, vid);
1290 if (ret != 0)
1291 return ret;
1292
1293 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1294 0, ALE_VLAN, vid);
1295 }
1296
1297 static const struct net_device_ops cpsw_netdev_ops = {
1298 .ndo_open = cpsw_ndo_open,
1299 .ndo_stop = cpsw_ndo_stop,
1300 .ndo_start_xmit = cpsw_ndo_start_xmit,
1301 .ndo_change_rx_flags = cpsw_ndo_change_rx_flags,
1302 .ndo_do_ioctl = cpsw_ndo_ioctl,
1303 .ndo_validate_addr = eth_validate_addr,
1304 .ndo_change_mtu = eth_change_mtu,
1305 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
1306 .ndo_get_stats = cpsw_ndo_get_stats,
1307 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
1308 #ifdef CONFIG_NET_POLL_CONTROLLER
1309 .ndo_poll_controller = cpsw_ndo_poll_controller,
1310 #endif
1311 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1312 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
1313 };
1314
1315 static void cpsw_get_drvinfo(struct net_device *ndev,
1316 struct ethtool_drvinfo *info)
1317 {
1318 struct cpsw_priv *priv = netdev_priv(ndev);
1319
1320 strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver));
1321 strlcpy(info->version, "1.0", sizeof(info->version));
1322 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1323 }
1324
1325 static u32 cpsw_get_msglevel(struct net_device *ndev)
1326 {
1327 struct cpsw_priv *priv = netdev_priv(ndev);
1328 return priv->msg_enable;
1329 }
1330
1331 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1332 {
1333 struct cpsw_priv *priv = netdev_priv(ndev);
1334 priv->msg_enable = value;
1335 }
1336
1337 static int cpsw_get_ts_info(struct net_device *ndev,
1338 struct ethtool_ts_info *info)
1339 {
1340 #ifdef CONFIG_TI_CPTS
1341 struct cpsw_priv *priv = netdev_priv(ndev);
1342
1343 info->so_timestamping =
1344 SOF_TIMESTAMPING_TX_HARDWARE |
1345 SOF_TIMESTAMPING_TX_SOFTWARE |
1346 SOF_TIMESTAMPING_RX_HARDWARE |
1347 SOF_TIMESTAMPING_RX_SOFTWARE |
1348 SOF_TIMESTAMPING_SOFTWARE |
1349 SOF_TIMESTAMPING_RAW_HARDWARE;
1350 info->phc_index = priv->cpts->phc_index;
1351 info->tx_types =
1352 (1 << HWTSTAMP_TX_OFF) |
1353 (1 << HWTSTAMP_TX_ON);
1354 info->rx_filters =
1355 (1 << HWTSTAMP_FILTER_NONE) |
1356 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1357 #else
1358 info->so_timestamping =
1359 SOF_TIMESTAMPING_TX_SOFTWARE |
1360 SOF_TIMESTAMPING_RX_SOFTWARE |
1361 SOF_TIMESTAMPING_SOFTWARE;
1362 info->phc_index = -1;
1363 info->tx_types = 0;
1364 info->rx_filters = 0;
1365 #endif
1366 return 0;
1367 }
1368
1369 static int cpsw_get_settings(struct net_device *ndev,
1370 struct ethtool_cmd *ecmd)
1371 {
1372 struct cpsw_priv *priv = netdev_priv(ndev);
1373 int slave_no = cpsw_slave_index(priv);
1374
1375 if (priv->slaves[slave_no].phy)
1376 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1377 else
1378 return -EOPNOTSUPP;
1379 }
1380
1381 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1382 {
1383 struct cpsw_priv *priv = netdev_priv(ndev);
1384 int slave_no = cpsw_slave_index(priv);
1385
1386 if (priv->slaves[slave_no].phy)
1387 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1388 else
1389 return -EOPNOTSUPP;
1390 }
1391
1392 static const struct ethtool_ops cpsw_ethtool_ops = {
1393 .get_drvinfo = cpsw_get_drvinfo,
1394 .get_msglevel = cpsw_get_msglevel,
1395 .set_msglevel = cpsw_set_msglevel,
1396 .get_link = ethtool_op_get_link,
1397 .get_ts_info = cpsw_get_ts_info,
1398 .get_settings = cpsw_get_settings,
1399 .set_settings = cpsw_set_settings,
1400 .get_coalesce = cpsw_get_coalesce,
1401 .set_coalesce = cpsw_set_coalesce,
1402 };
1403
1404 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1405 u32 slave_reg_ofs, u32 sliver_reg_ofs)
1406 {
1407 void __iomem *regs = priv->regs;
1408 int slave_num = slave->slave_num;
1409 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1410
1411 slave->data = data;
1412 slave->regs = regs + slave_reg_ofs;
1413 slave->sliver = regs + sliver_reg_ofs;
1414 slave->port_vlan = data->dual_emac_res_vlan;
1415 }
1416
1417 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1418 struct platform_device *pdev)
1419 {
1420 struct device_node *node = pdev->dev.of_node;
1421 struct device_node *slave_node;
1422 int i = 0, ret;
1423 u32 prop;
1424
1425 if (!node)
1426 return -EINVAL;
1427
1428 if (of_property_read_u32(node, "slaves", &prop)) {
1429 pr_err("Missing slaves property in the DT.\n");
1430 return -EINVAL;
1431 }
1432 data->slaves = prop;
1433
1434 if (of_property_read_u32(node, "active_slave", &prop)) {
1435 pr_err("Missing active_slave property in the DT.\n");
1436 ret = -EINVAL;
1437 goto error_ret;
1438 }
1439 data->active_slave = prop;
1440
1441 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1442 pr_err("Missing cpts_clock_mult property in the DT.\n");
1443 ret = -EINVAL;
1444 goto error_ret;
1445 }
1446 data->cpts_clock_mult = prop;
1447
1448 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1449 pr_err("Missing cpts_clock_shift property in the DT.\n");
1450 ret = -EINVAL;
1451 goto error_ret;
1452 }
1453 data->cpts_clock_shift = prop;
1454
1455 data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data),
1456 GFP_KERNEL);
1457 if (!data->slave_data)
1458 return -EINVAL;
1459
1460 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1461 pr_err("Missing cpdma_channels property in the DT.\n");
1462 ret = -EINVAL;
1463 goto error_ret;
1464 }
1465 data->channels = prop;
1466
1467 if (of_property_read_u32(node, "ale_entries", &prop)) {
1468 pr_err("Missing ale_entries property in the DT.\n");
1469 ret = -EINVAL;
1470 goto error_ret;
1471 }
1472 data->ale_entries = prop;
1473
1474 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1475 pr_err("Missing bd_ram_size property in the DT.\n");
1476 ret = -EINVAL;
1477 goto error_ret;
1478 }
1479 data->bd_ram_size = prop;
1480
1481 if (of_property_read_u32(node, "rx_descs", &prop)) {
1482 pr_err("Missing rx_descs property in the DT.\n");
1483 ret = -EINVAL;
1484 goto error_ret;
1485 }
1486 data->rx_descs = prop;
1487
1488 if (of_property_read_u32(node, "mac_control", &prop)) {
1489 pr_err("Missing mac_control property in the DT.\n");
1490 ret = -EINVAL;
1491 goto error_ret;
1492 }
1493 data->mac_control = prop;
1494
1495 if (!of_property_read_u32(node, "dual_emac", &prop))
1496 data->dual_emac = prop;
1497
1498 /*
1499 * Populate all the child nodes here...
1500 */
1501 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1502 /* We do not want to force this, as in some cases may not have child */
1503 if (ret)
1504 pr_warn("Doesn't have any child node\n");
1505
1506 for_each_node_by_name(slave_node, "slave") {
1507 struct cpsw_slave_data *slave_data = data->slave_data + i;
1508 const void *mac_addr = NULL;
1509 u32 phyid;
1510 int lenp;
1511 const __be32 *parp;
1512 struct device_node *mdio_node;
1513 struct platform_device *mdio;
1514
1515 parp = of_get_property(slave_node, "phy_id", &lenp);
1516 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
1517 pr_err("Missing slave[%d] phy_id property\n", i);
1518 ret = -EINVAL;
1519 goto error_ret;
1520 }
1521 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1522 phyid = be32_to_cpup(parp+1);
1523 mdio = of_find_device_by_node(mdio_node);
1524 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1525 PHY_ID_FMT, mdio->name, phyid);
1526
1527 mac_addr = of_get_mac_address(slave_node);
1528 if (mac_addr)
1529 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1530
1531 if (data->dual_emac) {
1532 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
1533 &prop)) {
1534 pr_err("Missing dual_emac_res_vlan in DT.\n");
1535 slave_data->dual_emac_res_vlan = i+1;
1536 pr_err("Using %d as Reserved VLAN for %d slave\n",
1537 slave_data->dual_emac_res_vlan, i);
1538 } else {
1539 slave_data->dual_emac_res_vlan = prop;
1540 }
1541 }
1542
1543 i++;
1544 }
1545
1546 return 0;
1547
1548 error_ret:
1549 kfree(data->slave_data);
1550 return ret;
1551 }
1552
1553 static int cpsw_probe_dual_emac(struct platform_device *pdev,
1554 struct cpsw_priv *priv)
1555 {
1556 struct cpsw_platform_data *data = &priv->data;
1557 struct net_device *ndev;
1558 struct cpsw_priv *priv_sl2;
1559 int ret = 0, i;
1560
1561 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1562 if (!ndev) {
1563 pr_err("cpsw: error allocating net_device\n");
1564 return -ENOMEM;
1565 }
1566
1567 priv_sl2 = netdev_priv(ndev);
1568 spin_lock_init(&priv_sl2->lock);
1569 priv_sl2->data = *data;
1570 priv_sl2->pdev = pdev;
1571 priv_sl2->ndev = ndev;
1572 priv_sl2->dev = &ndev->dev;
1573 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1574 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
1575
1576 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
1577 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
1578 ETH_ALEN);
1579 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
1580 } else {
1581 random_ether_addr(priv_sl2->mac_addr);
1582 pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
1583 }
1584 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
1585
1586 priv_sl2->slaves = priv->slaves;
1587 priv_sl2->clk = priv->clk;
1588
1589 priv_sl2->coal_intvl = 0;
1590 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
1591
1592 priv_sl2->cpsw_res = priv->cpsw_res;
1593 priv_sl2->regs = priv->regs;
1594 priv_sl2->host_port = priv->host_port;
1595 priv_sl2->host_port_regs = priv->host_port_regs;
1596 priv_sl2->wr_regs = priv->wr_regs;
1597 priv_sl2->dma = priv->dma;
1598 priv_sl2->txch = priv->txch;
1599 priv_sl2->rxch = priv->rxch;
1600 priv_sl2->ale = priv->ale;
1601 priv_sl2->emac_port = 1;
1602 priv->slaves[1].ndev = ndev;
1603 priv_sl2->cpts = priv->cpts;
1604 priv_sl2->version = priv->version;
1605
1606 for (i = 0; i < priv->num_irqs; i++) {
1607 priv_sl2->irqs_table[i] = priv->irqs_table[i];
1608 priv_sl2->num_irqs = priv->num_irqs;
1609 }
1610
1611 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1612
1613 ndev->netdev_ops = &cpsw_netdev_ops;
1614 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1615 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1616
1617 /* register the network device */
1618 SET_NETDEV_DEV(ndev, &pdev->dev);
1619 ret = register_netdev(ndev);
1620 if (ret) {
1621 pr_err("cpsw: error registering net device\n");
1622 free_netdev(ndev);
1623 ret = -ENODEV;
1624 }
1625
1626 return ret;
1627 }
1628
1629 static int cpsw_probe(struct platform_device *pdev)
1630 {
1631 struct cpsw_platform_data *data = pdev->dev.platform_data;
1632 struct net_device *ndev;
1633 struct cpsw_priv *priv;
1634 struct cpdma_params dma_params;
1635 struct cpsw_ale_params ale_params;
1636 void __iomem *ss_regs, *wr_regs;
1637 struct resource *res;
1638 u32 slave_offset, sliver_offset, slave_size;
1639 int ret = 0, i, k = 0;
1640
1641 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1642 if (!ndev) {
1643 pr_err("error allocating net_device\n");
1644 return -ENOMEM;
1645 }
1646
1647 platform_set_drvdata(pdev, ndev);
1648 priv = netdev_priv(ndev);
1649 spin_lock_init(&priv->lock);
1650 priv->pdev = pdev;
1651 priv->ndev = ndev;
1652 priv->dev = &ndev->dev;
1653 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1654 priv->rx_packet_max = max(rx_packet_max, 128);
1655 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
1656 if (!ndev) {
1657 pr_err("error allocating cpts\n");
1658 goto clean_ndev_ret;
1659 }
1660
1661 /*
1662 * This may be required here for child devices.
1663 */
1664 pm_runtime_enable(&pdev->dev);
1665
1666 if (cpsw_probe_dt(&priv->data, pdev)) {
1667 pr_err("cpsw: platform data missing\n");
1668 ret = -ENODEV;
1669 goto clean_ndev_ret;
1670 }
1671 data = &priv->data;
1672
1673 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
1674 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
1675 pr_info("Detected MACID = %pM", priv->mac_addr);
1676 } else {
1677 eth_random_addr(priv->mac_addr);
1678 pr_info("Random MACID = %pM", priv->mac_addr);
1679 }
1680
1681 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1682
1683 priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
1684 GFP_KERNEL);
1685 if (!priv->slaves) {
1686 ret = -EBUSY;
1687 goto clean_ndev_ret;
1688 }
1689 for (i = 0; i < data->slaves; i++)
1690 priv->slaves[i].slave_num = i;
1691
1692 priv->slaves[0].ndev = ndev;
1693 priv->emac_port = 0;
1694
1695 priv->clk = clk_get(&pdev->dev, "fck");
1696 if (IS_ERR(priv->clk)) {
1697 dev_err(&pdev->dev, "fck is not found\n");
1698 ret = -ENODEV;
1699 goto clean_slave_ret;
1700 }
1701 priv->coal_intvl = 0;
1702 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
1703
1704 priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1705 if (!priv->cpsw_res) {
1706 dev_err(priv->dev, "error getting i/o resource\n");
1707 ret = -ENOENT;
1708 goto clean_clk_ret;
1709 }
1710 if (!request_mem_region(priv->cpsw_res->start,
1711 resource_size(priv->cpsw_res), ndev->name)) {
1712 dev_err(priv->dev, "failed request i/o region\n");
1713 ret = -ENXIO;
1714 goto clean_clk_ret;
1715 }
1716 ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
1717 if (!ss_regs) {
1718 dev_err(priv->dev, "unable to map i/o region\n");
1719 goto clean_cpsw_iores_ret;
1720 }
1721 priv->regs = ss_regs;
1722 priv->version = __raw_readl(&priv->regs->id_ver);
1723 priv->host_port = HOST_PORT_NUM;
1724
1725 priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1726 if (!priv->cpsw_wr_res) {
1727 dev_err(priv->dev, "error getting i/o resource\n");
1728 ret = -ENOENT;
1729 goto clean_iomap_ret;
1730 }
1731 if (!request_mem_region(priv->cpsw_wr_res->start,
1732 resource_size(priv->cpsw_wr_res), ndev->name)) {
1733 dev_err(priv->dev, "failed request i/o region\n");
1734 ret = -ENXIO;
1735 goto clean_iomap_ret;
1736 }
1737 wr_regs = ioremap(priv->cpsw_wr_res->start,
1738 resource_size(priv->cpsw_wr_res));
1739 if (!wr_regs) {
1740 dev_err(priv->dev, "unable to map i/o region\n");
1741 goto clean_cpsw_wr_iores_ret;
1742 }
1743 priv->wr_regs = wr_regs;
1744
1745 memset(&dma_params, 0, sizeof(dma_params));
1746 memset(&ale_params, 0, sizeof(ale_params));
1747
1748 switch (priv->version) {
1749 case CPSW_VERSION_1:
1750 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
1751 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
1752 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
1753 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
1754 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
1755 slave_offset = CPSW1_SLAVE_OFFSET;
1756 slave_size = CPSW1_SLAVE_SIZE;
1757 sliver_offset = CPSW1_SLIVER_OFFSET;
1758 dma_params.desc_mem_phys = 0;
1759 break;
1760 case CPSW_VERSION_2:
1761 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
1762 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
1763 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
1764 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
1765 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
1766 slave_offset = CPSW2_SLAVE_OFFSET;
1767 slave_size = CPSW2_SLAVE_SIZE;
1768 sliver_offset = CPSW2_SLIVER_OFFSET;
1769 dma_params.desc_mem_phys =
1770 (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET;
1771 break;
1772 default:
1773 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
1774 ret = -ENODEV;
1775 goto clean_cpsw_wr_iores_ret;
1776 }
1777 for (i = 0; i < priv->data.slaves; i++) {
1778 struct cpsw_slave *slave = &priv->slaves[i];
1779 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
1780 slave_offset += slave_size;
1781 sliver_offset += SLIVER_SIZE;
1782 }
1783
1784 dma_params.dev = &pdev->dev;
1785 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
1786 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
1787 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
1788 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
1789 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
1790
1791 dma_params.num_chan = data->channels;
1792 dma_params.has_soft_reset = true;
1793 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
1794 dma_params.desc_mem_size = data->bd_ram_size;
1795 dma_params.desc_align = 16;
1796 dma_params.has_ext_regs = true;
1797 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
1798
1799 priv->dma = cpdma_ctlr_create(&dma_params);
1800 if (!priv->dma) {
1801 dev_err(priv->dev, "error initializing dma\n");
1802 ret = -ENOMEM;
1803 goto clean_wr_iomap_ret;
1804 }
1805
1806 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
1807 cpsw_tx_handler);
1808 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
1809 cpsw_rx_handler);
1810
1811 if (WARN_ON(!priv->txch || !priv->rxch)) {
1812 dev_err(priv->dev, "error initializing dma channels\n");
1813 ret = -ENOMEM;
1814 goto clean_dma_ret;
1815 }
1816
1817 ale_params.dev = &ndev->dev;
1818 ale_params.ale_ageout = ale_ageout;
1819 ale_params.ale_entries = data->ale_entries;
1820 ale_params.ale_ports = data->slaves;
1821
1822 priv->ale = cpsw_ale_create(&ale_params);
1823 if (!priv->ale) {
1824 dev_err(priv->dev, "error initializing ale engine\n");
1825 ret = -ENODEV;
1826 goto clean_dma_ret;
1827 }
1828
1829 ndev->irq = platform_get_irq(pdev, 0);
1830 if (ndev->irq < 0) {
1831 dev_err(priv->dev, "error getting irq resource\n");
1832 ret = -ENOENT;
1833 goto clean_ale_ret;
1834 }
1835
1836 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1837 for (i = res->start; i <= res->end; i++) {
1838 if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
1839 dev_name(&pdev->dev), priv)) {
1840 dev_err(priv->dev, "error attaching irq\n");
1841 goto clean_ale_ret;
1842 }
1843 priv->irqs_table[k] = i;
1844 priv->num_irqs = k;
1845 }
1846 k++;
1847 }
1848
1849 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1850
1851 ndev->netdev_ops = &cpsw_netdev_ops;
1852 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1853 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1854
1855 /* register the network device */
1856 SET_NETDEV_DEV(ndev, &pdev->dev);
1857 ret = register_netdev(ndev);
1858 if (ret) {
1859 dev_err(priv->dev, "error registering net device\n");
1860 ret = -ENODEV;
1861 goto clean_irq_ret;
1862 }
1863
1864 if (cpts_register(&pdev->dev, priv->cpts,
1865 data->cpts_clock_mult, data->cpts_clock_shift))
1866 dev_err(priv->dev, "error registering cpts device\n");
1867
1868 cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
1869 priv->cpsw_res->start, ndev->irq);
1870
1871 if (priv->data.dual_emac) {
1872 ret = cpsw_probe_dual_emac(pdev, priv);
1873 if (ret) {
1874 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
1875 goto clean_irq_ret;
1876 }
1877 }
1878
1879 return 0;
1880
1881 clean_irq_ret:
1882 free_irq(ndev->irq, priv);
1883 clean_ale_ret:
1884 cpsw_ale_destroy(priv->ale);
1885 clean_dma_ret:
1886 cpdma_chan_destroy(priv->txch);
1887 cpdma_chan_destroy(priv->rxch);
1888 cpdma_ctlr_destroy(priv->dma);
1889 clean_wr_iomap_ret:
1890 iounmap(priv->wr_regs);
1891 clean_cpsw_wr_iores_ret:
1892 release_mem_region(priv->cpsw_wr_res->start,
1893 resource_size(priv->cpsw_wr_res));
1894 clean_iomap_ret:
1895 iounmap(priv->regs);
1896 clean_cpsw_iores_ret:
1897 release_mem_region(priv->cpsw_res->start,
1898 resource_size(priv->cpsw_res));
1899 clean_clk_ret:
1900 clk_put(priv->clk);
1901 clean_slave_ret:
1902 pm_runtime_disable(&pdev->dev);
1903 kfree(priv->slaves);
1904 clean_ndev_ret:
1905 free_netdev(ndev);
1906 return ret;
1907 }
1908
1909 static int cpsw_remove(struct platform_device *pdev)
1910 {
1911 struct net_device *ndev = platform_get_drvdata(pdev);
1912 struct cpsw_priv *priv = netdev_priv(ndev);
1913
1914 pr_info("removing device");
1915 platform_set_drvdata(pdev, NULL);
1916
1917 cpts_unregister(priv->cpts);
1918 free_irq(ndev->irq, priv);
1919 cpsw_ale_destroy(priv->ale);
1920 cpdma_chan_destroy(priv->txch);
1921 cpdma_chan_destroy(priv->rxch);
1922 cpdma_ctlr_destroy(priv->dma);
1923 iounmap(priv->regs);
1924 release_mem_region(priv->cpsw_res->start,
1925 resource_size(priv->cpsw_res));
1926 iounmap(priv->wr_regs);
1927 release_mem_region(priv->cpsw_wr_res->start,
1928 resource_size(priv->cpsw_wr_res));
1929 pm_runtime_disable(&pdev->dev);
1930 clk_put(priv->clk);
1931 kfree(priv->slaves);
1932 free_netdev(ndev);
1933
1934 return 0;
1935 }
1936
1937 static int cpsw_suspend(struct device *dev)
1938 {
1939 struct platform_device *pdev = to_platform_device(dev);
1940 struct net_device *ndev = platform_get_drvdata(pdev);
1941
1942 if (netif_running(ndev))
1943 cpsw_ndo_stop(ndev);
1944 pm_runtime_put_sync(&pdev->dev);
1945
1946 return 0;
1947 }
1948
1949 static int cpsw_resume(struct device *dev)
1950 {
1951 struct platform_device *pdev = to_platform_device(dev);
1952 struct net_device *ndev = platform_get_drvdata(pdev);
1953
1954 pm_runtime_get_sync(&pdev->dev);
1955 if (netif_running(ndev))
1956 cpsw_ndo_open(ndev);
1957 return 0;
1958 }
1959
1960 static const struct dev_pm_ops cpsw_pm_ops = {
1961 .suspend = cpsw_suspend,
1962 .resume = cpsw_resume,
1963 };
1964
1965 static const struct of_device_id cpsw_of_mtable[] = {
1966 { .compatible = "ti,cpsw", },
1967 { /* sentinel */ },
1968 };
1969
1970 static struct platform_driver cpsw_driver = {
1971 .driver = {
1972 .name = "cpsw",
1973 .owner = THIS_MODULE,
1974 .pm = &cpsw_pm_ops,
1975 .of_match_table = of_match_ptr(cpsw_of_mtable),
1976 },
1977 .probe = cpsw_probe,
1978 .remove = cpsw_remove,
1979 };
1980
1981 static int __init cpsw_init(void)
1982 {
1983 return platform_driver_register(&cpsw_driver);
1984 }
1985 late_initcall(cpsw_init);
1986
1987 static void __exit cpsw_exit(void)
1988 {
1989 platform_driver_unregister(&cpsw_driver);
1990 }
1991 module_exit(cpsw_exit);
1992
1993 MODULE_LICENSE("GPL");
1994 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
1995 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
1996 MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux kernel - Deliverables
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