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Merge branch 'for-1111' of git://gitorious.org/smack-next/kernel into for-linus
[deliverable/linux.git] / drivers / net / ethernet / xilinx / ll_temac_main.c
1 /*
2 * Driver for Xilinx TEMAC Ethernet device
3 *
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 *
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
10 *
11 * Notes:
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
21 *
22 * TODO:
23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
27 *
28 */
29
30 #include <linux/delay.h>
31 #include <linux/etherdevice.h>
32 #include <linux/init.h>
33 #include <linux/mii.h>
34 #include <linux/module.h>
35 #include <linux/mutex.h>
36 #include <linux/netdevice.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39 #include <linux/of_mdio.h>
40 #include <linux/of_platform.h>
41 #include <linux/of_address.h>
42 #include <linux/skbuff.h>
43 #include <linux/spinlock.h>
44 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */
45 #include <linux/udp.h> /* needed for sizeof(udphdr) */
46 #include <linux/phy.h>
47 #include <linux/in.h>
48 #include <linux/io.h>
49 #include <linux/ip.h>
50 #include <linux/slab.h>
51 #include <linux/interrupt.h>
52 #include <linux/dma-mapping.h>
53
54 #include "ll_temac.h"
55
56 #define TX_BD_NUM 64
57 #define RX_BD_NUM 128
58
59 /* ---------------------------------------------------------------------
60 * Low level register access functions
61 */
62
63 u32 temac_ior(struct temac_local *lp, int offset)
64 {
65 return in_be32((u32 *)(lp->regs + offset));
66 }
67
68 void temac_iow(struct temac_local *lp, int offset, u32 value)
69 {
70 out_be32((u32 *) (lp->regs + offset), value);
71 }
72
73 int temac_indirect_busywait(struct temac_local *lp)
74 {
75 long end = jiffies + 2;
76
77 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
78 if (end - jiffies <= 0) {
79 WARN_ON(1);
80 return -ETIMEDOUT;
81 }
82 msleep(1);
83 }
84 return 0;
85 }
86
87 /**
88 * temac_indirect_in32
89 *
90 * lp->indirect_mutex must be held when calling this function
91 */
92 u32 temac_indirect_in32(struct temac_local *lp, int reg)
93 {
94 u32 val;
95
96 if (temac_indirect_busywait(lp))
97 return -ETIMEDOUT;
98 temac_iow(lp, XTE_CTL0_OFFSET, reg);
99 if (temac_indirect_busywait(lp))
100 return -ETIMEDOUT;
101 val = temac_ior(lp, XTE_LSW0_OFFSET);
102
103 return val;
104 }
105
106 /**
107 * temac_indirect_out32
108 *
109 * lp->indirect_mutex must be held when calling this function
110 */
111 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
112 {
113 if (temac_indirect_busywait(lp))
114 return;
115 temac_iow(lp, XTE_LSW0_OFFSET, value);
116 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
117 }
118
119 /**
120 * temac_dma_in32 - Memory mapped DMA read, this function expects a
121 * register input that is based on DCR word addresses which
122 * are then converted to memory mapped byte addresses
123 */
124 static u32 temac_dma_in32(struct temac_local *lp, int reg)
125 {
126 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
127 }
128
129 /**
130 * temac_dma_out32 - Memory mapped DMA read, this function expects a
131 * register input that is based on DCR word addresses which
132 * are then converted to memory mapped byte addresses
133 */
134 static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
135 {
136 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
137 }
138
139 /* DMA register access functions can be DCR based or memory mapped.
140 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
141 * memory mapped.
142 */
143 #ifdef CONFIG_PPC_DCR
144
145 /**
146 * temac_dma_dcr_in32 - DCR based DMA read
147 */
148 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
149 {
150 return dcr_read(lp->sdma_dcrs, reg);
151 }
152
153 /**
154 * temac_dma_dcr_out32 - DCR based DMA write
155 */
156 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
157 {
158 dcr_write(lp->sdma_dcrs, reg, value);
159 }
160
161 /**
162 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
163 * I/O functions
164 */
165 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
166 struct device_node *np)
167 {
168 unsigned int dcrs;
169
170 /* setup the dcr address mapping if it's in the device tree */
171
172 dcrs = dcr_resource_start(np, 0);
173 if (dcrs != 0) {
174 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
175 lp->dma_in = temac_dma_dcr_in;
176 lp->dma_out = temac_dma_dcr_out;
177 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
178 return 0;
179 }
180 /* no DCR in the device tree, indicate a failure */
181 return -1;
182 }
183
184 #else
185
186 /*
187 * temac_dcr_setup - This is a stub for when DCR is not supported,
188 * such as with MicroBlaze
189 */
190 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
191 struct device_node *np)
192 {
193 return -1;
194 }
195
196 #endif
197
198 /**
199 * * temac_dma_bd_release - Release buffer descriptor rings
200 */
201 static void temac_dma_bd_release(struct net_device *ndev)
202 {
203 struct temac_local *lp = netdev_priv(ndev);
204 int i;
205
206 for (i = 0; i < RX_BD_NUM; i++) {
207 if (!lp->rx_skb[i])
208 break;
209 else {
210 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
211 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
212 dev_kfree_skb(lp->rx_skb[i]);
213 }
214 }
215 if (lp->rx_bd_v)
216 dma_free_coherent(ndev->dev.parent,
217 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
218 lp->rx_bd_v, lp->rx_bd_p);
219 if (lp->tx_bd_v)
220 dma_free_coherent(ndev->dev.parent,
221 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
222 lp->tx_bd_v, lp->tx_bd_p);
223 if (lp->rx_skb)
224 kfree(lp->rx_skb);
225 }
226
227 /**
228 * temac_dma_bd_init - Setup buffer descriptor rings
229 */
230 static int temac_dma_bd_init(struct net_device *ndev)
231 {
232 struct temac_local *lp = netdev_priv(ndev);
233 struct sk_buff *skb;
234 int i;
235
236 lp->rx_skb = kzalloc(sizeof(*lp->rx_skb) * RX_BD_NUM, GFP_KERNEL);
237 if (!lp->rx_skb) {
238 dev_err(&ndev->dev,
239 "can't allocate memory for DMA RX buffer\n");
240 goto out;
241 }
242 /* allocate the tx and rx ring buffer descriptors. */
243 /* returns a virtual address and a physical address. */
244 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
245 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
246 &lp->tx_bd_p, GFP_KERNEL);
247 if (!lp->tx_bd_v) {
248 dev_err(&ndev->dev,
249 "unable to allocate DMA TX buffer descriptors");
250 goto out;
251 }
252 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
253 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
254 &lp->rx_bd_p, GFP_KERNEL);
255 if (!lp->rx_bd_v) {
256 dev_err(&ndev->dev,
257 "unable to allocate DMA RX buffer descriptors");
258 goto out;
259 }
260
261 memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
262 for (i = 0; i < TX_BD_NUM; i++) {
263 lp->tx_bd_v[i].next = lp->tx_bd_p +
264 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
265 }
266
267 memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
268 for (i = 0; i < RX_BD_NUM; i++) {
269 lp->rx_bd_v[i].next = lp->rx_bd_p +
270 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
271
272 skb = netdev_alloc_skb_ip_align(ndev,
273 XTE_MAX_JUMBO_FRAME_SIZE);
274
275 if (skb == 0) {
276 dev_err(&ndev->dev, "alloc_skb error %d\n", i);
277 goto out;
278 }
279 lp->rx_skb[i] = skb;
280 /* returns physical address of skb->data */
281 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
282 skb->data,
283 XTE_MAX_JUMBO_FRAME_SIZE,
284 DMA_FROM_DEVICE);
285 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
286 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
287 }
288
289 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
290 CHNL_CTRL_IRQ_EN |
291 CHNL_CTRL_IRQ_DLY_EN |
292 CHNL_CTRL_IRQ_COAL_EN);
293 /* 0x10220483 */
294 /* 0x00100483 */
295 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
296 CHNL_CTRL_IRQ_EN |
297 CHNL_CTRL_IRQ_DLY_EN |
298 CHNL_CTRL_IRQ_COAL_EN |
299 CHNL_CTRL_IRQ_IOE);
300 /* 0xff010283 */
301
302 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
303 lp->dma_out(lp, RX_TAILDESC_PTR,
304 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
305 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
306
307 return 0;
308
309 out:
310 temac_dma_bd_release(ndev);
311 return -ENOMEM;
312 }
313
314 /* ---------------------------------------------------------------------
315 * net_device_ops
316 */
317
318 static int temac_set_mac_address(struct net_device *ndev, void *address)
319 {
320 struct temac_local *lp = netdev_priv(ndev);
321
322 if (address)
323 memcpy(ndev->dev_addr, address, ETH_ALEN);
324
325 if (!is_valid_ether_addr(ndev->dev_addr))
326 random_ether_addr(ndev->dev_addr);
327
328 /* set up unicast MAC address filter set its mac address */
329 mutex_lock(&lp->indirect_mutex);
330 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
331 (ndev->dev_addr[0]) |
332 (ndev->dev_addr[1] << 8) |
333 (ndev->dev_addr[2] << 16) |
334 (ndev->dev_addr[3] << 24));
335 /* There are reserved bits in EUAW1
336 * so don't affect them Set MAC bits [47:32] in EUAW1 */
337 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
338 (ndev->dev_addr[4] & 0x000000ff) |
339 (ndev->dev_addr[5] << 8));
340 mutex_unlock(&lp->indirect_mutex);
341
342 return 0;
343 }
344
345 static int netdev_set_mac_address(struct net_device *ndev, void *p)
346 {
347 struct sockaddr *addr = p;
348
349 return temac_set_mac_address(ndev, addr->sa_data);
350 }
351
352 static void temac_set_multicast_list(struct net_device *ndev)
353 {
354 struct temac_local *lp = netdev_priv(ndev);
355 u32 multi_addr_msw, multi_addr_lsw, val;
356 int i;
357
358 mutex_lock(&lp->indirect_mutex);
359 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
360 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
361 /*
362 * We must make the kernel realise we had to move
363 * into promisc mode or we start all out war on
364 * the cable. If it was a promisc request the
365 * flag is already set. If not we assert it.
366 */
367 ndev->flags |= IFF_PROMISC;
368 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
369 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
370 } else if (!netdev_mc_empty(ndev)) {
371 struct netdev_hw_addr *ha;
372
373 i = 0;
374 netdev_for_each_mc_addr(ha, ndev) {
375 if (i >= MULTICAST_CAM_TABLE_NUM)
376 break;
377 multi_addr_msw = ((ha->addr[3] << 24) |
378 (ha->addr[2] << 16) |
379 (ha->addr[1] << 8) |
380 (ha->addr[0]));
381 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
382 multi_addr_msw);
383 multi_addr_lsw = ((ha->addr[5] << 8) |
384 (ha->addr[4]) | (i << 16));
385 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
386 multi_addr_lsw);
387 i++;
388 }
389 } else {
390 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
391 temac_indirect_out32(lp, XTE_AFM_OFFSET,
392 val & ~XTE_AFM_EPPRM_MASK);
393 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
394 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
395 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
396 }
397 mutex_unlock(&lp->indirect_mutex);
398 }
399
400 struct temac_option {
401 int flg;
402 u32 opt;
403 u32 reg;
404 u32 m_or;
405 u32 m_and;
406 } temac_options[] = {
407 /* Turn on jumbo packet support for both Rx and Tx */
408 {
409 .opt = XTE_OPTION_JUMBO,
410 .reg = XTE_TXC_OFFSET,
411 .m_or = XTE_TXC_TXJMBO_MASK,
412 },
413 {
414 .opt = XTE_OPTION_JUMBO,
415 .reg = XTE_RXC1_OFFSET,
416 .m_or =XTE_RXC1_RXJMBO_MASK,
417 },
418 /* Turn on VLAN packet support for both Rx and Tx */
419 {
420 .opt = XTE_OPTION_VLAN,
421 .reg = XTE_TXC_OFFSET,
422 .m_or =XTE_TXC_TXVLAN_MASK,
423 },
424 {
425 .opt = XTE_OPTION_VLAN,
426 .reg = XTE_RXC1_OFFSET,
427 .m_or =XTE_RXC1_RXVLAN_MASK,
428 },
429 /* Turn on FCS stripping on receive packets */
430 {
431 .opt = XTE_OPTION_FCS_STRIP,
432 .reg = XTE_RXC1_OFFSET,
433 .m_or =XTE_RXC1_RXFCS_MASK,
434 },
435 /* Turn on FCS insertion on transmit packets */
436 {
437 .opt = XTE_OPTION_FCS_INSERT,
438 .reg = XTE_TXC_OFFSET,
439 .m_or =XTE_TXC_TXFCS_MASK,
440 },
441 /* Turn on length/type field checking on receive packets */
442 {
443 .opt = XTE_OPTION_LENTYPE_ERR,
444 .reg = XTE_RXC1_OFFSET,
445 .m_or =XTE_RXC1_RXLT_MASK,
446 },
447 /* Turn on flow control */
448 {
449 .opt = XTE_OPTION_FLOW_CONTROL,
450 .reg = XTE_FCC_OFFSET,
451 .m_or =XTE_FCC_RXFLO_MASK,
452 },
453 /* Turn on flow control */
454 {
455 .opt = XTE_OPTION_FLOW_CONTROL,
456 .reg = XTE_FCC_OFFSET,
457 .m_or =XTE_FCC_TXFLO_MASK,
458 },
459 /* Turn on promiscuous frame filtering (all frames are received ) */
460 {
461 .opt = XTE_OPTION_PROMISC,
462 .reg = XTE_AFM_OFFSET,
463 .m_or =XTE_AFM_EPPRM_MASK,
464 },
465 /* Enable transmitter if not already enabled */
466 {
467 .opt = XTE_OPTION_TXEN,
468 .reg = XTE_TXC_OFFSET,
469 .m_or =XTE_TXC_TXEN_MASK,
470 },
471 /* Enable receiver? */
472 {
473 .opt = XTE_OPTION_RXEN,
474 .reg = XTE_RXC1_OFFSET,
475 .m_or =XTE_RXC1_RXEN_MASK,
476 },
477 {}
478 };
479
480 /**
481 * temac_setoptions
482 */
483 static u32 temac_setoptions(struct net_device *ndev, u32 options)
484 {
485 struct temac_local *lp = netdev_priv(ndev);
486 struct temac_option *tp = &temac_options[0];
487 int reg;
488
489 mutex_lock(&lp->indirect_mutex);
490 while (tp->opt) {
491 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
492 if (options & tp->opt)
493 reg |= tp->m_or;
494 temac_indirect_out32(lp, tp->reg, reg);
495 tp++;
496 }
497 lp->options |= options;
498 mutex_unlock(&lp->indirect_mutex);
499
500 return 0;
501 }
502
503 /* Initialize temac */
504 static void temac_device_reset(struct net_device *ndev)
505 {
506 struct temac_local *lp = netdev_priv(ndev);
507 u32 timeout;
508 u32 val;
509
510 /* Perform a software reset */
511
512 /* 0x300 host enable bit ? */
513 /* reset PHY through control register ?:1 */
514
515 dev_dbg(&ndev->dev, "%s()\n", __func__);
516
517 mutex_lock(&lp->indirect_mutex);
518 /* Reset the receiver and wait for it to finish reset */
519 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
520 timeout = 1000;
521 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
522 udelay(1);
523 if (--timeout == 0) {
524 dev_err(&ndev->dev,
525 "temac_device_reset RX reset timeout!!\n");
526 break;
527 }
528 }
529
530 /* Reset the transmitter and wait for it to finish reset */
531 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
532 timeout = 1000;
533 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
534 udelay(1);
535 if (--timeout == 0) {
536 dev_err(&ndev->dev,
537 "temac_device_reset TX reset timeout!!\n");
538 break;
539 }
540 }
541
542 /* Disable the receiver */
543 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
544 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
545
546 /* Reset Local Link (DMA) */
547 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
548 timeout = 1000;
549 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
550 udelay(1);
551 if (--timeout == 0) {
552 dev_err(&ndev->dev,
553 "temac_device_reset DMA reset timeout!!\n");
554 break;
555 }
556 }
557 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
558
559 if (temac_dma_bd_init(ndev)) {
560 dev_err(&ndev->dev,
561 "temac_device_reset descriptor allocation failed\n");
562 }
563
564 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
565 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
566 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
567 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
568
569 mutex_unlock(&lp->indirect_mutex);
570
571 /* Sync default options with HW
572 * but leave receiver and transmitter disabled. */
573 temac_setoptions(ndev,
574 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
575
576 temac_set_mac_address(ndev, NULL);
577
578 /* Set address filter table */
579 temac_set_multicast_list(ndev);
580 if (temac_setoptions(ndev, lp->options))
581 dev_err(&ndev->dev, "Error setting TEMAC options\n");
582
583 /* Init Driver variable */
584 ndev->trans_start = jiffies; /* prevent tx timeout */
585 }
586
587 void temac_adjust_link(struct net_device *ndev)
588 {
589 struct temac_local *lp = netdev_priv(ndev);
590 struct phy_device *phy = lp->phy_dev;
591 u32 mii_speed;
592 int link_state;
593
594 /* hash together the state values to decide if something has changed */
595 link_state = phy->speed | (phy->duplex << 1) | phy->link;
596
597 mutex_lock(&lp->indirect_mutex);
598 if (lp->last_link != link_state) {
599 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
600 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
601
602 switch (phy->speed) {
603 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
604 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
605 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
606 }
607
608 /* Write new speed setting out to TEMAC */
609 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
610 lp->last_link = link_state;
611 phy_print_status(phy);
612 }
613 mutex_unlock(&lp->indirect_mutex);
614 }
615
616 static void temac_start_xmit_done(struct net_device *ndev)
617 {
618 struct temac_local *lp = netdev_priv(ndev);
619 struct cdmac_bd *cur_p;
620 unsigned int stat = 0;
621
622 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
623 stat = cur_p->app0;
624
625 while (stat & STS_CTRL_APP0_CMPLT) {
626 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
627 DMA_TO_DEVICE);
628 if (cur_p->app4)
629 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
630 cur_p->app0 = 0;
631 cur_p->app1 = 0;
632 cur_p->app2 = 0;
633 cur_p->app3 = 0;
634 cur_p->app4 = 0;
635
636 ndev->stats.tx_packets++;
637 ndev->stats.tx_bytes += cur_p->len;
638
639 lp->tx_bd_ci++;
640 if (lp->tx_bd_ci >= TX_BD_NUM)
641 lp->tx_bd_ci = 0;
642
643 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
644 stat = cur_p->app0;
645 }
646
647 netif_wake_queue(ndev);
648 }
649
650 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
651 {
652 struct cdmac_bd *cur_p;
653 int tail;
654
655 tail = lp->tx_bd_tail;
656 cur_p = &lp->tx_bd_v[tail];
657
658 do {
659 if (cur_p->app0)
660 return NETDEV_TX_BUSY;
661
662 tail++;
663 if (tail >= TX_BD_NUM)
664 tail = 0;
665
666 cur_p = &lp->tx_bd_v[tail];
667 num_frag--;
668 } while (num_frag >= 0);
669
670 return 0;
671 }
672
673 static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
674 {
675 struct temac_local *lp = netdev_priv(ndev);
676 struct cdmac_bd *cur_p;
677 dma_addr_t start_p, tail_p;
678 int ii;
679 unsigned long num_frag;
680 skb_frag_t *frag;
681
682 num_frag = skb_shinfo(skb)->nr_frags;
683 frag = &skb_shinfo(skb)->frags[0];
684 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
685 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
686
687 if (temac_check_tx_bd_space(lp, num_frag)) {
688 if (!netif_queue_stopped(ndev)) {
689 netif_stop_queue(ndev);
690 return NETDEV_TX_BUSY;
691 }
692 return NETDEV_TX_BUSY;
693 }
694
695 cur_p->app0 = 0;
696 if (skb->ip_summed == CHECKSUM_PARTIAL) {
697 unsigned int csum_start_off = skb_checksum_start_offset(skb);
698 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
699
700 cur_p->app0 |= 1; /* TX Checksum Enabled */
701 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
702 cur_p->app2 = 0; /* initial checksum seed */
703 }
704
705 cur_p->app0 |= STS_CTRL_APP0_SOP;
706 cur_p->len = skb_headlen(skb);
707 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
708 DMA_TO_DEVICE);
709 cur_p->app4 = (unsigned long)skb;
710
711 for (ii = 0; ii < num_frag; ii++) {
712 lp->tx_bd_tail++;
713 if (lp->tx_bd_tail >= TX_BD_NUM)
714 lp->tx_bd_tail = 0;
715
716 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
717 cur_p->phys = dma_map_single(ndev->dev.parent,
718 skb_frag_address(frag),
719 skb_frag_size(frag), DMA_TO_DEVICE);
720 cur_p->len = skb_frag_size(frag);
721 cur_p->app0 = 0;
722 frag++;
723 }
724 cur_p->app0 |= STS_CTRL_APP0_EOP;
725
726 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
727 lp->tx_bd_tail++;
728 if (lp->tx_bd_tail >= TX_BD_NUM)
729 lp->tx_bd_tail = 0;
730
731 skb_tx_timestamp(skb);
732
733 /* Kick off the transfer */
734 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
735
736 return NETDEV_TX_OK;
737 }
738
739
740 static void ll_temac_recv(struct net_device *ndev)
741 {
742 struct temac_local *lp = netdev_priv(ndev);
743 struct sk_buff *skb, *new_skb;
744 unsigned int bdstat;
745 struct cdmac_bd *cur_p;
746 dma_addr_t tail_p;
747 int length;
748 unsigned long flags;
749
750 spin_lock_irqsave(&lp->rx_lock, flags);
751
752 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
753 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
754
755 bdstat = cur_p->app0;
756 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
757
758 skb = lp->rx_skb[lp->rx_bd_ci];
759 length = cur_p->app4 & 0x3FFF;
760
761 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
762 DMA_FROM_DEVICE);
763
764 skb_put(skb, length);
765 skb->dev = ndev;
766 skb->protocol = eth_type_trans(skb, ndev);
767 skb_checksum_none_assert(skb);
768
769 /* if we're doing rx csum offload, set it up */
770 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
771 (skb->protocol == __constant_htons(ETH_P_IP)) &&
772 (skb->len > 64)) {
773
774 skb->csum = cur_p->app3 & 0xFFFF;
775 skb->ip_summed = CHECKSUM_COMPLETE;
776 }
777
778 if (!skb_defer_rx_timestamp(skb))
779 netif_rx(skb);
780
781 ndev->stats.rx_packets++;
782 ndev->stats.rx_bytes += length;
783
784 new_skb = netdev_alloc_skb_ip_align(ndev,
785 XTE_MAX_JUMBO_FRAME_SIZE);
786
787 if (new_skb == 0) {
788 dev_err(&ndev->dev, "no memory for new sk_buff\n");
789 spin_unlock_irqrestore(&lp->rx_lock, flags);
790 return;
791 }
792
793 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
794 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
795 XTE_MAX_JUMBO_FRAME_SIZE,
796 DMA_FROM_DEVICE);
797 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
798 lp->rx_skb[lp->rx_bd_ci] = new_skb;
799
800 lp->rx_bd_ci++;
801 if (lp->rx_bd_ci >= RX_BD_NUM)
802 lp->rx_bd_ci = 0;
803
804 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
805 bdstat = cur_p->app0;
806 }
807 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
808
809 spin_unlock_irqrestore(&lp->rx_lock, flags);
810 }
811
812 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
813 {
814 struct net_device *ndev = _ndev;
815 struct temac_local *lp = netdev_priv(ndev);
816 unsigned int status;
817
818 status = lp->dma_in(lp, TX_IRQ_REG);
819 lp->dma_out(lp, TX_IRQ_REG, status);
820
821 if (status & (IRQ_COAL | IRQ_DLY))
822 temac_start_xmit_done(lp->ndev);
823 if (status & 0x080)
824 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
825
826 return IRQ_HANDLED;
827 }
828
829 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
830 {
831 struct net_device *ndev = _ndev;
832 struct temac_local *lp = netdev_priv(ndev);
833 unsigned int status;
834
835 /* Read and clear the status registers */
836 status = lp->dma_in(lp, RX_IRQ_REG);
837 lp->dma_out(lp, RX_IRQ_REG, status);
838
839 if (status & (IRQ_COAL | IRQ_DLY))
840 ll_temac_recv(lp->ndev);
841
842 return IRQ_HANDLED;
843 }
844
845 static int temac_open(struct net_device *ndev)
846 {
847 struct temac_local *lp = netdev_priv(ndev);
848 int rc;
849
850 dev_dbg(&ndev->dev, "temac_open()\n");
851
852 if (lp->phy_node) {
853 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
854 temac_adjust_link, 0, 0);
855 if (!lp->phy_dev) {
856 dev_err(lp->dev, "of_phy_connect() failed\n");
857 return -ENODEV;
858 }
859
860 phy_start(lp->phy_dev);
861 }
862
863 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
864 if (rc)
865 goto err_tx_irq;
866 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
867 if (rc)
868 goto err_rx_irq;
869
870 temac_device_reset(ndev);
871 return 0;
872
873 err_rx_irq:
874 free_irq(lp->tx_irq, ndev);
875 err_tx_irq:
876 if (lp->phy_dev)
877 phy_disconnect(lp->phy_dev);
878 lp->phy_dev = NULL;
879 dev_err(lp->dev, "request_irq() failed\n");
880 return rc;
881 }
882
883 static int temac_stop(struct net_device *ndev)
884 {
885 struct temac_local *lp = netdev_priv(ndev);
886
887 dev_dbg(&ndev->dev, "temac_close()\n");
888
889 free_irq(lp->tx_irq, ndev);
890 free_irq(lp->rx_irq, ndev);
891
892 if (lp->phy_dev)
893 phy_disconnect(lp->phy_dev);
894 lp->phy_dev = NULL;
895
896 temac_dma_bd_release(ndev);
897
898 return 0;
899 }
900
901 #ifdef CONFIG_NET_POLL_CONTROLLER
902 static void
903 temac_poll_controller(struct net_device *ndev)
904 {
905 struct temac_local *lp = netdev_priv(ndev);
906
907 disable_irq(lp->tx_irq);
908 disable_irq(lp->rx_irq);
909
910 ll_temac_rx_irq(lp->tx_irq, ndev);
911 ll_temac_tx_irq(lp->rx_irq, ndev);
912
913 enable_irq(lp->tx_irq);
914 enable_irq(lp->rx_irq);
915 }
916 #endif
917
918 static const struct net_device_ops temac_netdev_ops = {
919 .ndo_open = temac_open,
920 .ndo_stop = temac_stop,
921 .ndo_start_xmit = temac_start_xmit,
922 .ndo_set_mac_address = netdev_set_mac_address,
923 .ndo_validate_addr = eth_validate_addr,
924 #ifdef CONFIG_NET_POLL_CONTROLLER
925 .ndo_poll_controller = temac_poll_controller,
926 #endif
927 };
928
929 /* ---------------------------------------------------------------------
930 * SYSFS device attributes
931 */
932 static ssize_t temac_show_llink_regs(struct device *dev,
933 struct device_attribute *attr, char *buf)
934 {
935 struct net_device *ndev = dev_get_drvdata(dev);
936 struct temac_local *lp = netdev_priv(ndev);
937 int i, len = 0;
938
939 for (i = 0; i < 0x11; i++)
940 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
941 (i % 8) == 7 ? "\n" : " ");
942 len += sprintf(buf + len, "\n");
943
944 return len;
945 }
946
947 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
948
949 static struct attribute *temac_device_attrs[] = {
950 &dev_attr_llink_regs.attr,
951 NULL,
952 };
953
954 static const struct attribute_group temac_attr_group = {
955 .attrs = temac_device_attrs,
956 };
957
958 /* ethtool support */
959 static int temac_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
960 {
961 struct temac_local *lp = netdev_priv(ndev);
962 return phy_ethtool_gset(lp->phy_dev, cmd);
963 }
964
965 static int temac_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
966 {
967 struct temac_local *lp = netdev_priv(ndev);
968 return phy_ethtool_sset(lp->phy_dev, cmd);
969 }
970
971 static int temac_nway_reset(struct net_device *ndev)
972 {
973 struct temac_local *lp = netdev_priv(ndev);
974 return phy_start_aneg(lp->phy_dev);
975 }
976
977 static const struct ethtool_ops temac_ethtool_ops = {
978 .get_settings = temac_get_settings,
979 .set_settings = temac_set_settings,
980 .nway_reset = temac_nway_reset,
981 .get_link = ethtool_op_get_link,
982 };
983
984 static int __devinit temac_of_probe(struct platform_device *op)
985 {
986 struct device_node *np;
987 struct temac_local *lp;
988 struct net_device *ndev;
989 const void *addr;
990 __be32 *p;
991 int size, rc = 0;
992
993 /* Init network device structure */
994 ndev = alloc_etherdev(sizeof(*lp));
995 if (!ndev) {
996 dev_err(&op->dev, "could not allocate device.\n");
997 return -ENOMEM;
998 }
999 ether_setup(ndev);
1000 dev_set_drvdata(&op->dev, ndev);
1001 SET_NETDEV_DEV(ndev, &op->dev);
1002 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1003 ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
1004 ndev->netdev_ops = &temac_netdev_ops;
1005 ndev->ethtool_ops = &temac_ethtool_ops;
1006 #if 0
1007 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1008 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1009 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1010 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1011 ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */
1012 ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */
1013 ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */
1014 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1015 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1016 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1017 ndev->features |= NETIF_F_LRO; /* large receive offload */
1018 #endif
1019
1020 /* setup temac private info structure */
1021 lp = netdev_priv(ndev);
1022 lp->ndev = ndev;
1023 lp->dev = &op->dev;
1024 lp->options = XTE_OPTION_DEFAULTS;
1025 spin_lock_init(&lp->rx_lock);
1026 mutex_init(&lp->indirect_mutex);
1027
1028 /* map device registers */
1029 lp->regs = of_iomap(op->dev.of_node, 0);
1030 if (!lp->regs) {
1031 dev_err(&op->dev, "could not map temac regs.\n");
1032 goto nodev;
1033 }
1034
1035 /* Setup checksum offload, but default to off if not specified */
1036 lp->temac_features = 0;
1037 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1038 if (p && be32_to_cpu(*p)) {
1039 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1040 /* Can checksum TCP/UDP over IPv4. */
1041 ndev->features |= NETIF_F_IP_CSUM;
1042 }
1043 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1044 if (p && be32_to_cpu(*p))
1045 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1046
1047 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1048 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
1049 if (!np) {
1050 dev_err(&op->dev, "could not find DMA node\n");
1051 goto err_iounmap;
1052 }
1053
1054 /* Setup the DMA register accesses, could be DCR or memory mapped */
1055 if (temac_dcr_setup(lp, op, np)) {
1056
1057 /* no DCR in the device tree, try non-DCR */
1058 lp->sdma_regs = of_iomap(np, 0);
1059 if (lp->sdma_regs) {
1060 lp->dma_in = temac_dma_in32;
1061 lp->dma_out = temac_dma_out32;
1062 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1063 } else {
1064 dev_err(&op->dev, "unable to map DMA registers\n");
1065 of_node_put(np);
1066 goto err_iounmap;
1067 }
1068 }
1069
1070 lp->rx_irq = irq_of_parse_and_map(np, 0);
1071 lp->tx_irq = irq_of_parse_and_map(np, 1);
1072
1073 of_node_put(np); /* Finished with the DMA node; drop the reference */
1074
1075 if ((lp->rx_irq == NO_IRQ) || (lp->tx_irq == NO_IRQ)) {
1076 dev_err(&op->dev, "could not determine irqs\n");
1077 rc = -ENOMEM;
1078 goto err_iounmap_2;
1079 }
1080
1081
1082 /* Retrieve the MAC address */
1083 addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
1084 if ((!addr) || (size != 6)) {
1085 dev_err(&op->dev, "could not find MAC address\n");
1086 rc = -ENODEV;
1087 goto err_iounmap_2;
1088 }
1089 temac_set_mac_address(ndev, (void *)addr);
1090
1091 rc = temac_mdio_setup(lp, op->dev.of_node);
1092 if (rc)
1093 dev_warn(&op->dev, "error registering MDIO bus\n");
1094
1095 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
1096 if (lp->phy_node)
1097 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1098
1099 /* Add the device attributes */
1100 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1101 if (rc) {
1102 dev_err(lp->dev, "Error creating sysfs files\n");
1103 goto err_iounmap_2;
1104 }
1105
1106 rc = register_netdev(lp->ndev);
1107 if (rc) {
1108 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1109 goto err_register_ndev;
1110 }
1111
1112 return 0;
1113
1114 err_register_ndev:
1115 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1116 err_iounmap_2:
1117 if (lp->sdma_regs)
1118 iounmap(lp->sdma_regs);
1119 err_iounmap:
1120 iounmap(lp->regs);
1121 nodev:
1122 free_netdev(ndev);
1123 ndev = NULL;
1124 return rc;
1125 }
1126
1127 static int __devexit temac_of_remove(struct platform_device *op)
1128 {
1129 struct net_device *ndev = dev_get_drvdata(&op->dev);
1130 struct temac_local *lp = netdev_priv(ndev);
1131
1132 temac_mdio_teardown(lp);
1133 unregister_netdev(ndev);
1134 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1135 if (lp->phy_node)
1136 of_node_put(lp->phy_node);
1137 lp->phy_node = NULL;
1138 dev_set_drvdata(&op->dev, NULL);
1139 iounmap(lp->regs);
1140 if (lp->sdma_regs)
1141 iounmap(lp->sdma_regs);
1142 free_netdev(ndev);
1143 return 0;
1144 }
1145
1146 static struct of_device_id temac_of_match[] __devinitdata = {
1147 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1148 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1149 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1150 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1151 {},
1152 };
1153 MODULE_DEVICE_TABLE(of, temac_of_match);
1154
1155 static struct platform_driver temac_of_driver = {
1156 .probe = temac_of_probe,
1157 .remove = __devexit_p(temac_of_remove),
1158 .driver = {
1159 .owner = THIS_MODULE,
1160 .name = "xilinx_temac",
1161 .of_match_table = temac_of_match,
1162 },
1163 };
1164
1165 static int __init temac_init(void)
1166 {
1167 return platform_driver_register(&temac_of_driver);
1168 }
1169 module_init(temac_init);
1170
1171 static void __exit temac_exit(void)
1172 {
1173 platform_driver_unregister(&temac_of_driver);
1174 }
1175 module_exit(temac_exit);
1176
1177 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1178 MODULE_AUTHOR("Yoshio Kashiwagi");
1179 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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