2 * linux/drivers/net/ethoc.c
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
14 #include <linux/etherdevice.h>
15 #include <linux/crc32.h>
17 #include <linux/mii.h>
18 #include <linux/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/sched.h>
21 #include <net/ethoc.h>
23 static int buffer_size
= 0x8000; /* 32 KBytes */
24 module_param(buffer_size
, int, 0);
25 MODULE_PARM_DESC(buffer_size
, "DMA buffer allocation size");
27 /* register offsets */
29 #define INT_SOURCE 0x04
34 #define PACKETLEN 0x18
36 #define TX_BD_NUM 0x20
37 #define CTRLMODER 0x24
39 #define MIICOMMAND 0x2c
40 #define MIIADDRESS 0x30
41 #define MIITX_DATA 0x34
42 #define MIIRX_DATA 0x38
43 #define MIISTATUS 0x3c
44 #define MAC_ADDR0 0x40
45 #define MAC_ADDR1 0x44
46 #define ETH_HASH0 0x48
47 #define ETH_HASH1 0x4c
48 #define ETH_TXCTRL 0x50
51 #define MODER_RXEN (1 << 0) /* receive enable */
52 #define MODER_TXEN (1 << 1) /* transmit enable */
53 #define MODER_NOPRE (1 << 2) /* no preamble */
54 #define MODER_BRO (1 << 3) /* broadcast address */
55 #define MODER_IAM (1 << 4) /* individual address mode */
56 #define MODER_PRO (1 << 5) /* promiscuous mode */
57 #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
58 #define MODER_LOOP (1 << 7) /* loopback */
59 #define MODER_NBO (1 << 8) /* no back-off */
60 #define MODER_EDE (1 << 9) /* excess defer enable */
61 #define MODER_FULLD (1 << 10) /* full duplex */
62 #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
63 #define MODER_DCRC (1 << 12) /* delayed CRC enable */
64 #define MODER_CRC (1 << 13) /* CRC enable */
65 #define MODER_HUGE (1 << 14) /* huge packets enable */
66 #define MODER_PAD (1 << 15) /* padding enabled */
67 #define MODER_RSM (1 << 16) /* receive small packets */
69 /* interrupt source and mask registers */
70 #define INT_MASK_TXF (1 << 0) /* transmit frame */
71 #define INT_MASK_TXE (1 << 1) /* transmit error */
72 #define INT_MASK_RXF (1 << 2) /* receive frame */
73 #define INT_MASK_RXE (1 << 3) /* receive error */
74 #define INT_MASK_BUSY (1 << 4)
75 #define INT_MASK_TXC (1 << 5) /* transmit control frame */
76 #define INT_MASK_RXC (1 << 6) /* receive control frame */
78 #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
79 #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
81 #define INT_MASK_ALL ( \
82 INT_MASK_TXF | INT_MASK_TXE | \
83 INT_MASK_RXF | INT_MASK_RXE | \
84 INT_MASK_TXC | INT_MASK_RXC | \
88 /* packet length register */
89 #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
90 #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
91 #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
94 /* transmit buffer number register */
95 #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
97 /* control module mode register */
98 #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
99 #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
100 #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
102 /* MII mode register */
103 #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
104 #define MIIMODER_NOPRE (1 << 8) /* no preamble */
106 /* MII command register */
107 #define MIICOMMAND_SCAN (1 << 0) /* scan status */
108 #define MIICOMMAND_READ (1 << 1) /* read status */
109 #define MIICOMMAND_WRITE (1 << 2) /* write control data */
111 /* MII address register */
112 #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
113 #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
114 #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
115 MIIADDRESS_RGAD(reg))
117 /* MII transmit data register */
118 #define MIITX_DATA_VAL(x) ((x) & 0xffff)
120 /* MII receive data register */
121 #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
123 /* MII status register */
124 #define MIISTATUS_LINKFAIL (1 << 0)
125 #define MIISTATUS_BUSY (1 << 1)
126 #define MIISTATUS_INVALID (1 << 2)
128 /* TX buffer descriptor */
129 #define TX_BD_CS (1 << 0) /* carrier sense lost */
130 #define TX_BD_DF (1 << 1) /* defer indication */
131 #define TX_BD_LC (1 << 2) /* late collision */
132 #define TX_BD_RL (1 << 3) /* retransmission limit */
133 #define TX_BD_RETRY_MASK (0x00f0)
134 #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
135 #define TX_BD_UR (1 << 8) /* transmitter underrun */
136 #define TX_BD_CRC (1 << 11) /* TX CRC enable */
137 #define TX_BD_PAD (1 << 12) /* pad enable for short packets */
138 #define TX_BD_WRAP (1 << 13)
139 #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
140 #define TX_BD_READY (1 << 15) /* TX buffer ready */
141 #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
142 #define TX_BD_LEN_MASK (0xffff << 16)
144 #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
145 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
147 /* RX buffer descriptor */
148 #define RX_BD_LC (1 << 0) /* late collision */
149 #define RX_BD_CRC (1 << 1) /* RX CRC error */
150 #define RX_BD_SF (1 << 2) /* short frame */
151 #define RX_BD_TL (1 << 3) /* too long */
152 #define RX_BD_DN (1 << 4) /* dribble nibble */
153 #define RX_BD_IS (1 << 5) /* invalid symbol */
154 #define RX_BD_OR (1 << 6) /* receiver overrun */
155 #define RX_BD_MISS (1 << 7)
156 #define RX_BD_CF (1 << 8) /* control frame */
157 #define RX_BD_WRAP (1 << 13)
158 #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
159 #define RX_BD_EMPTY (1 << 15)
160 #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
162 #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
163 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
165 #define ETHOC_BUFSIZ 1536
166 #define ETHOC_ZLEN 64
167 #define ETHOC_BD_BASE 0x400
168 #define ETHOC_TIMEOUT (HZ / 2)
169 #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
172 * struct ethoc - driver-private device structure
173 * @iobase: pointer to I/O memory region
174 * @membase: pointer to buffer memory region
175 * @dma_alloc: dma allocated buffer size
176 * @num_tx: number of send buffers
177 * @cur_tx: last send buffer written
178 * @dty_tx: last buffer actually sent
179 * @num_rx: number of receive buffers
180 * @cur_rx: current receive buffer
181 * @netdev: pointer to network device structure
182 * @napi: NAPI structure
183 * @stats: network device statistics
184 * @msg_enable: device state flags
185 * @rx_lock: receive lock
188 * @mdio: MDIO bus for PHY access
189 * @phy_id: address of attached PHY
192 void __iomem
*iobase
;
193 void __iomem
*membase
;
203 struct net_device
*netdev
;
204 struct napi_struct napi
;
205 struct net_device_stats stats
;
211 struct phy_device
*phy
;
212 struct mii_bus
*mdio
;
217 * struct ethoc_bd - buffer descriptor
218 * @stat: buffer statistics
219 * @addr: physical memory address
226 static inline u32
ethoc_read(struct ethoc
*dev
, loff_t offset
)
228 return ioread32(dev
->iobase
+ offset
);
231 static inline void ethoc_write(struct ethoc
*dev
, loff_t offset
, u32 data
)
233 iowrite32(data
, dev
->iobase
+ offset
);
236 static inline void ethoc_read_bd(struct ethoc
*dev
, int index
,
239 loff_t offset
= ETHOC_BD_BASE
+ (index
* sizeof(struct ethoc_bd
));
240 bd
->stat
= ethoc_read(dev
, offset
+ 0);
241 bd
->addr
= ethoc_read(dev
, offset
+ 4);
244 static inline void ethoc_write_bd(struct ethoc
*dev
, int index
,
245 const struct ethoc_bd
*bd
)
247 loff_t offset
= ETHOC_BD_BASE
+ (index
* sizeof(struct ethoc_bd
));
248 ethoc_write(dev
, offset
+ 0, bd
->stat
);
249 ethoc_write(dev
, offset
+ 4, bd
->addr
);
252 static inline void ethoc_enable_irq(struct ethoc
*dev
, u32 mask
)
254 u32 imask
= ethoc_read(dev
, INT_MASK
);
256 ethoc_write(dev
, INT_MASK
, imask
);
259 static inline void ethoc_disable_irq(struct ethoc
*dev
, u32 mask
)
261 u32 imask
= ethoc_read(dev
, INT_MASK
);
263 ethoc_write(dev
, INT_MASK
, imask
);
266 static inline void ethoc_ack_irq(struct ethoc
*dev
, u32 mask
)
268 ethoc_write(dev
, INT_SOURCE
, mask
);
271 static inline void ethoc_enable_rx_and_tx(struct ethoc
*dev
)
273 u32 mode
= ethoc_read(dev
, MODER
);
274 mode
|= MODER_RXEN
| MODER_TXEN
;
275 ethoc_write(dev
, MODER
, mode
);
278 static inline void ethoc_disable_rx_and_tx(struct ethoc
*dev
)
280 u32 mode
= ethoc_read(dev
, MODER
);
281 mode
&= ~(MODER_RXEN
| MODER_TXEN
);
282 ethoc_write(dev
, MODER
, mode
);
285 static int ethoc_init_ring(struct ethoc
*dev
)
294 /* setup transmission buffers */
295 bd
.addr
= virt_to_phys(dev
->membase
);
296 bd
.stat
= TX_BD_IRQ
| TX_BD_CRC
;
298 for (i
= 0; i
< dev
->num_tx
; i
++) {
299 if (i
== dev
->num_tx
- 1)
300 bd
.stat
|= TX_BD_WRAP
;
302 ethoc_write_bd(dev
, i
, &bd
);
303 bd
.addr
+= ETHOC_BUFSIZ
;
306 bd
.stat
= RX_BD_EMPTY
| RX_BD_IRQ
;
308 for (i
= 0; i
< dev
->num_rx
; i
++) {
309 if (i
== dev
->num_rx
- 1)
310 bd
.stat
|= RX_BD_WRAP
;
312 ethoc_write_bd(dev
, dev
->num_tx
+ i
, &bd
);
313 bd
.addr
+= ETHOC_BUFSIZ
;
319 static int ethoc_reset(struct ethoc
*dev
)
323 /* TODO: reset controller? */
325 ethoc_disable_rx_and_tx(dev
);
327 /* TODO: setup registers */
329 /* enable FCS generation and automatic padding */
330 mode
= ethoc_read(dev
, MODER
);
331 mode
|= MODER_CRC
| MODER_PAD
;
332 ethoc_write(dev
, MODER
, mode
);
334 /* set full-duplex mode */
335 mode
= ethoc_read(dev
, MODER
);
337 ethoc_write(dev
, MODER
, mode
);
338 ethoc_write(dev
, IPGT
, 0x15);
340 ethoc_ack_irq(dev
, INT_MASK_ALL
);
341 ethoc_enable_irq(dev
, INT_MASK_ALL
);
342 ethoc_enable_rx_and_tx(dev
);
346 static unsigned int ethoc_update_rx_stats(struct ethoc
*dev
,
349 struct net_device
*netdev
= dev
->netdev
;
350 unsigned int ret
= 0;
352 if (bd
->stat
& RX_BD_TL
) {
353 dev_err(&netdev
->dev
, "RX: frame too long\n");
354 dev
->stats
.rx_length_errors
++;
358 if (bd
->stat
& RX_BD_SF
) {
359 dev_err(&netdev
->dev
, "RX: frame too short\n");
360 dev
->stats
.rx_length_errors
++;
364 if (bd
->stat
& RX_BD_DN
) {
365 dev_err(&netdev
->dev
, "RX: dribble nibble\n");
366 dev
->stats
.rx_frame_errors
++;
369 if (bd
->stat
& RX_BD_CRC
) {
370 dev_err(&netdev
->dev
, "RX: wrong CRC\n");
371 dev
->stats
.rx_crc_errors
++;
375 if (bd
->stat
& RX_BD_OR
) {
376 dev_err(&netdev
->dev
, "RX: overrun\n");
377 dev
->stats
.rx_over_errors
++;
381 if (bd
->stat
& RX_BD_MISS
)
382 dev
->stats
.rx_missed_errors
++;
384 if (bd
->stat
& RX_BD_LC
) {
385 dev_err(&netdev
->dev
, "RX: late collision\n");
386 dev
->stats
.collisions
++;
393 static int ethoc_rx(struct net_device
*dev
, int limit
)
395 struct ethoc
*priv
= netdev_priv(dev
);
398 for (count
= 0; count
< limit
; ++count
) {
402 entry
= priv
->num_tx
+ (priv
->cur_rx
% priv
->num_rx
);
403 ethoc_read_bd(priv
, entry
, &bd
);
404 if (bd
.stat
& RX_BD_EMPTY
)
407 if (ethoc_update_rx_stats(priv
, &bd
) == 0) {
408 int size
= bd
.stat
>> 16;
411 size
-= 4; /* strip the CRC */
412 skb
= netdev_alloc_skb_ip_align(dev
, size
);
415 void *src
= phys_to_virt(bd
.addr
);
416 memcpy_fromio(skb_put(skb
, size
), src
, size
);
417 skb
->protocol
= eth_type_trans(skb
, dev
);
418 priv
->stats
.rx_packets
++;
419 priv
->stats
.rx_bytes
+= size
;
420 netif_receive_skb(skb
);
423 dev_warn(&dev
->dev
, "low on memory - "
426 priv
->stats
.rx_dropped
++;
431 /* clear the buffer descriptor so it can be reused */
432 bd
.stat
&= ~RX_BD_STATS
;
433 bd
.stat
|= RX_BD_EMPTY
;
434 ethoc_write_bd(priv
, entry
, &bd
);
441 static int ethoc_update_tx_stats(struct ethoc
*dev
, struct ethoc_bd
*bd
)
443 struct net_device
*netdev
= dev
->netdev
;
445 if (bd
->stat
& TX_BD_LC
) {
446 dev_err(&netdev
->dev
, "TX: late collision\n");
447 dev
->stats
.tx_window_errors
++;
450 if (bd
->stat
& TX_BD_RL
) {
451 dev_err(&netdev
->dev
, "TX: retransmit limit\n");
452 dev
->stats
.tx_aborted_errors
++;
455 if (bd
->stat
& TX_BD_UR
) {
456 dev_err(&netdev
->dev
, "TX: underrun\n");
457 dev
->stats
.tx_fifo_errors
++;
460 if (bd
->stat
& TX_BD_CS
) {
461 dev_err(&netdev
->dev
, "TX: carrier sense lost\n");
462 dev
->stats
.tx_carrier_errors
++;
465 if (bd
->stat
& TX_BD_STATS
)
466 dev
->stats
.tx_errors
++;
468 dev
->stats
.collisions
+= (bd
->stat
>> 4) & 0xf;
469 dev
->stats
.tx_bytes
+= bd
->stat
>> 16;
470 dev
->stats
.tx_packets
++;
474 static void ethoc_tx(struct net_device
*dev
)
476 struct ethoc
*priv
= netdev_priv(dev
);
478 spin_lock(&priv
->lock
);
480 while (priv
->dty_tx
!= priv
->cur_tx
) {
481 unsigned int entry
= priv
->dty_tx
% priv
->num_tx
;
484 ethoc_read_bd(priv
, entry
, &bd
);
485 if (bd
.stat
& TX_BD_READY
)
488 entry
= (++priv
->dty_tx
) % priv
->num_tx
;
489 (void)ethoc_update_tx_stats(priv
, &bd
);
492 if ((priv
->cur_tx
- priv
->dty_tx
) <= (priv
->num_tx
/ 2))
493 netif_wake_queue(dev
);
495 ethoc_ack_irq(priv
, INT_MASK_TX
);
496 spin_unlock(&priv
->lock
);
499 static irqreturn_t
ethoc_interrupt(int irq
, void *dev_id
)
501 struct net_device
*dev
= (struct net_device
*)dev_id
;
502 struct ethoc
*priv
= netdev_priv(dev
);
505 ethoc_disable_irq(priv
, INT_MASK_ALL
);
506 pending
= ethoc_read(priv
, INT_SOURCE
);
507 if (unlikely(pending
== 0)) {
508 ethoc_enable_irq(priv
, INT_MASK_ALL
);
512 ethoc_ack_irq(priv
, pending
);
514 if (pending
& INT_MASK_BUSY
) {
515 dev_err(&dev
->dev
, "packet dropped\n");
516 priv
->stats
.rx_dropped
++;
519 if (pending
& INT_MASK_RX
) {
520 if (napi_schedule_prep(&priv
->napi
))
521 __napi_schedule(&priv
->napi
);
523 ethoc_enable_irq(priv
, INT_MASK_RX
);
526 if (pending
& INT_MASK_TX
)
529 ethoc_enable_irq(priv
, INT_MASK_ALL
& ~INT_MASK_RX
);
533 static int ethoc_get_mac_address(struct net_device
*dev
, void *addr
)
535 struct ethoc
*priv
= netdev_priv(dev
);
536 u8
*mac
= (u8
*)addr
;
539 reg
= ethoc_read(priv
, MAC_ADDR0
);
540 mac
[2] = (reg
>> 24) & 0xff;
541 mac
[3] = (reg
>> 16) & 0xff;
542 mac
[4] = (reg
>> 8) & 0xff;
543 mac
[5] = (reg
>> 0) & 0xff;
545 reg
= ethoc_read(priv
, MAC_ADDR1
);
546 mac
[0] = (reg
>> 8) & 0xff;
547 mac
[1] = (reg
>> 0) & 0xff;
552 static int ethoc_poll(struct napi_struct
*napi
, int budget
)
554 struct ethoc
*priv
= container_of(napi
, struct ethoc
, napi
);
557 work_done
= ethoc_rx(priv
->netdev
, budget
);
558 if (work_done
< budget
) {
559 ethoc_enable_irq(priv
, INT_MASK_RX
);
566 static int ethoc_mdio_read(struct mii_bus
*bus
, int phy
, int reg
)
568 unsigned long timeout
= jiffies
+ ETHOC_MII_TIMEOUT
;
569 struct ethoc
*priv
= bus
->priv
;
571 ethoc_write(priv
, MIIADDRESS
, MIIADDRESS_ADDR(phy
, reg
));
572 ethoc_write(priv
, MIICOMMAND
, MIICOMMAND_READ
);
574 while (time_before(jiffies
, timeout
)) {
575 u32 status
= ethoc_read(priv
, MIISTATUS
);
576 if (!(status
& MIISTATUS_BUSY
)) {
577 u32 data
= ethoc_read(priv
, MIIRX_DATA
);
578 /* reset MII command register */
579 ethoc_write(priv
, MIICOMMAND
, 0);
589 static int ethoc_mdio_write(struct mii_bus
*bus
, int phy
, int reg
, u16 val
)
591 unsigned long timeout
= jiffies
+ ETHOC_MII_TIMEOUT
;
592 struct ethoc
*priv
= bus
->priv
;
594 ethoc_write(priv
, MIIADDRESS
, MIIADDRESS_ADDR(phy
, reg
));
595 ethoc_write(priv
, MIITX_DATA
, val
);
596 ethoc_write(priv
, MIICOMMAND
, MIICOMMAND_WRITE
);
598 while (time_before(jiffies
, timeout
)) {
599 u32 stat
= ethoc_read(priv
, MIISTATUS
);
600 if (!(stat
& MIISTATUS_BUSY
))
609 static int ethoc_mdio_reset(struct mii_bus
*bus
)
614 static void ethoc_mdio_poll(struct net_device
*dev
)
618 static int ethoc_mdio_probe(struct net_device
*dev
)
620 struct ethoc
*priv
= netdev_priv(dev
);
621 struct phy_device
*phy
;
624 for (i
= 0; i
< PHY_MAX_ADDR
; i
++) {
625 phy
= priv
->mdio
->phy_map
[i
];
627 if (priv
->phy_id
!= -1) {
628 /* attach to specified PHY */
629 if (priv
->phy_id
== phy
->addr
)
632 /* autoselect PHY if none was specified */
640 dev_err(&dev
->dev
, "no PHY found\n");
644 phy
= phy_connect(dev
, dev_name(&phy
->dev
), ethoc_mdio_poll
, 0,
645 PHY_INTERFACE_MODE_GMII
);
647 dev_err(&dev
->dev
, "could not attach to PHY\n");
655 static int ethoc_open(struct net_device
*dev
)
657 struct ethoc
*priv
= netdev_priv(dev
);
658 unsigned int min_tx
= 2;
662 ret
= request_irq(dev
->irq
, ethoc_interrupt
, IRQF_SHARED
,
667 /* calculate the number of TX/RX buffers, maximum 128 supported */
668 num_bd
= min_t(unsigned int,
669 128, (dev
->mem_end
- dev
->mem_start
+ 1) / ETHOC_BUFSIZ
);
670 priv
->num_tx
= max(min_tx
, num_bd
/ 4);
671 priv
->num_rx
= num_bd
- priv
->num_tx
;
672 ethoc_write(priv
, TX_BD_NUM
, priv
->num_tx
);
674 ethoc_init_ring(priv
);
677 if (netif_queue_stopped(dev
)) {
678 dev_dbg(&dev
->dev
, " resuming queue\n");
679 netif_wake_queue(dev
);
681 dev_dbg(&dev
->dev
, " starting queue\n");
682 netif_start_queue(dev
);
685 phy_start(priv
->phy
);
686 napi_enable(&priv
->napi
);
688 if (netif_msg_ifup(priv
)) {
689 dev_info(&dev
->dev
, "I/O: %08lx Memory: %08lx-%08lx\n",
690 dev
->base_addr
, dev
->mem_start
, dev
->mem_end
);
696 static int ethoc_stop(struct net_device
*dev
)
698 struct ethoc
*priv
= netdev_priv(dev
);
700 napi_disable(&priv
->napi
);
705 ethoc_disable_rx_and_tx(priv
);
706 free_irq(dev
->irq
, dev
);
708 if (!netif_queue_stopped(dev
))
709 netif_stop_queue(dev
);
714 static int ethoc_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
716 struct ethoc
*priv
= netdev_priv(dev
);
717 struct mii_ioctl_data
*mdio
= if_mii(ifr
);
718 struct phy_device
*phy
= NULL
;
720 if (!netif_running(dev
))
723 if (cmd
!= SIOCGMIIPHY
) {
724 if (mdio
->phy_id
>= PHY_MAX_ADDR
)
727 phy
= priv
->mdio
->phy_map
[mdio
->phy_id
];
734 return phy_mii_ioctl(phy
, mdio
, cmd
);
737 static int ethoc_config(struct net_device
*dev
, struct ifmap
*map
)
742 static int ethoc_set_mac_address(struct net_device
*dev
, void *addr
)
744 struct ethoc
*priv
= netdev_priv(dev
);
745 u8
*mac
= (u8
*)addr
;
747 ethoc_write(priv
, MAC_ADDR0
, (mac
[2] << 24) | (mac
[3] << 16) |
748 (mac
[4] << 8) | (mac
[5] << 0));
749 ethoc_write(priv
, MAC_ADDR1
, (mac
[0] << 8) | (mac
[1] << 0));
754 static void ethoc_set_multicast_list(struct net_device
*dev
)
756 struct ethoc
*priv
= netdev_priv(dev
);
757 u32 mode
= ethoc_read(priv
, MODER
);
758 struct dev_mc_list
*mc
= NULL
;
759 u32 hash
[2] = { 0, 0 };
761 /* set loopback mode if requested */
762 if (dev
->flags
& IFF_LOOPBACK
)
767 /* receive broadcast frames if requested */
768 if (dev
->flags
& IFF_BROADCAST
)
773 /* enable promiscuous mode if requested */
774 if (dev
->flags
& IFF_PROMISC
)
779 ethoc_write(priv
, MODER
, mode
);
781 /* receive multicast frames */
782 if (dev
->flags
& IFF_ALLMULTI
) {
783 hash
[0] = 0xffffffff;
784 hash
[1] = 0xffffffff;
786 for (mc
= dev
->mc_list
; mc
; mc
= mc
->next
) {
787 u32 crc
= ether_crc(mc
->dmi_addrlen
, mc
->dmi_addr
);
788 int bit
= (crc
>> 26) & 0x3f;
789 hash
[bit
>> 5] |= 1 << (bit
& 0x1f);
793 ethoc_write(priv
, ETH_HASH0
, hash
[0]);
794 ethoc_write(priv
, ETH_HASH1
, hash
[1]);
797 static int ethoc_change_mtu(struct net_device
*dev
, int new_mtu
)
802 static void ethoc_tx_timeout(struct net_device
*dev
)
804 struct ethoc
*priv
= netdev_priv(dev
);
805 u32 pending
= ethoc_read(priv
, INT_SOURCE
);
807 ethoc_interrupt(dev
->irq
, dev
);
810 static struct net_device_stats
*ethoc_stats(struct net_device
*dev
)
812 struct ethoc
*priv
= netdev_priv(dev
);
816 static netdev_tx_t
ethoc_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
818 struct ethoc
*priv
= netdev_priv(dev
);
823 if (unlikely(skb
->len
> ETHOC_BUFSIZ
)) {
824 priv
->stats
.tx_errors
++;
828 entry
= priv
->cur_tx
% priv
->num_tx
;
829 spin_lock_irq(&priv
->lock
);
832 ethoc_read_bd(priv
, entry
, &bd
);
833 if (unlikely(skb
->len
< ETHOC_ZLEN
))
834 bd
.stat
|= TX_BD_PAD
;
836 bd
.stat
&= ~TX_BD_PAD
;
838 dest
= phys_to_virt(bd
.addr
);
839 memcpy_toio(dest
, skb
->data
, skb
->len
);
841 bd
.stat
&= ~(TX_BD_STATS
| TX_BD_LEN_MASK
);
842 bd
.stat
|= TX_BD_LEN(skb
->len
);
843 ethoc_write_bd(priv
, entry
, &bd
);
845 bd
.stat
|= TX_BD_READY
;
846 ethoc_write_bd(priv
, entry
, &bd
);
848 if (priv
->cur_tx
== (priv
->dty_tx
+ priv
->num_tx
)) {
849 dev_dbg(&dev
->dev
, "stopping queue\n");
850 netif_stop_queue(dev
);
853 dev
->trans_start
= jiffies
;
854 spin_unlock_irq(&priv
->lock
);
860 static const struct net_device_ops ethoc_netdev_ops
= {
861 .ndo_open
= ethoc_open
,
862 .ndo_stop
= ethoc_stop
,
863 .ndo_do_ioctl
= ethoc_ioctl
,
864 .ndo_set_config
= ethoc_config
,
865 .ndo_set_mac_address
= ethoc_set_mac_address
,
866 .ndo_set_multicast_list
= ethoc_set_multicast_list
,
867 .ndo_change_mtu
= ethoc_change_mtu
,
868 .ndo_tx_timeout
= ethoc_tx_timeout
,
869 .ndo_get_stats
= ethoc_stats
,
870 .ndo_start_xmit
= ethoc_start_xmit
,
874 * ethoc_probe() - initialize OpenCores ethernet MAC
875 * pdev: platform device
877 static int ethoc_probe(struct platform_device
*pdev
)
879 struct net_device
*netdev
= NULL
;
880 struct resource
*res
= NULL
;
881 struct resource
*mmio
= NULL
;
882 struct resource
*mem
= NULL
;
883 struct ethoc
*priv
= NULL
;
887 /* allocate networking device */
888 netdev
= alloc_etherdev(sizeof(struct ethoc
));
890 dev_err(&pdev
->dev
, "cannot allocate network device\n");
895 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
896 platform_set_drvdata(pdev
, netdev
);
898 /* obtain I/O memory space */
899 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
901 dev_err(&pdev
->dev
, "cannot obtain I/O memory space\n");
906 mmio
= devm_request_mem_region(&pdev
->dev
, res
->start
,
907 resource_size(res
), res
->name
);
909 dev_err(&pdev
->dev
, "cannot request I/O memory space\n");
914 netdev
->base_addr
= mmio
->start
;
916 /* obtain buffer memory space */
917 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
919 mem
= devm_request_mem_region(&pdev
->dev
, res
->start
,
920 resource_size(res
), res
->name
);
922 dev_err(&pdev
->dev
, "cannot request memory space\n");
927 netdev
->mem_start
= mem
->start
;
928 netdev
->mem_end
= mem
->end
;
932 /* obtain device IRQ number */
933 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
935 dev_err(&pdev
->dev
, "cannot obtain IRQ\n");
940 netdev
->irq
= res
->start
;
942 /* setup driver-private data */
943 priv
= netdev_priv(netdev
);
944 priv
->netdev
= netdev
;
947 priv
->iobase
= devm_ioremap_nocache(&pdev
->dev
, netdev
->base_addr
,
948 resource_size(mmio
));
950 dev_err(&pdev
->dev
, "cannot remap I/O memory space\n");
955 if (netdev
->mem_end
) {
956 priv
->membase
= devm_ioremap_nocache(&pdev
->dev
,
957 netdev
->mem_start
, resource_size(mem
));
958 if (!priv
->membase
) {
959 dev_err(&pdev
->dev
, "cannot remap memory space\n");
964 /* Allocate buffer memory */
965 priv
->membase
= dma_alloc_coherent(NULL
,
966 buffer_size
, (void *)&netdev
->mem_start
,
968 if (!priv
->membase
) {
969 dev_err(&pdev
->dev
, "cannot allocate %dB buffer\n",
974 netdev
->mem_end
= netdev
->mem_start
+ buffer_size
;
975 priv
->dma_alloc
= buffer_size
;
978 /* Allow the platform setup code to pass in a MAC address. */
979 if (pdev
->dev
.platform_data
) {
980 struct ethoc_platform_data
*pdata
=
981 (struct ethoc_platform_data
*)pdev
->dev
.platform_data
;
982 memcpy(netdev
->dev_addr
, pdata
->hwaddr
, IFHWADDRLEN
);
983 priv
->phy_id
= pdata
->phy_id
;
986 /* Check that the given MAC address is valid. If it isn't, read the
987 * current MAC from the controller. */
988 if (!is_valid_ether_addr(netdev
->dev_addr
))
989 ethoc_get_mac_address(netdev
, netdev
->dev_addr
);
991 /* Check the MAC again for validity, if it still isn't choose and
992 * program a random one. */
993 if (!is_valid_ether_addr(netdev
->dev_addr
))
994 random_ether_addr(netdev
->dev_addr
);
996 ethoc_set_mac_address(netdev
, netdev
->dev_addr
);
998 /* register MII bus */
999 priv
->mdio
= mdiobus_alloc();
1005 priv
->mdio
->name
= "ethoc-mdio";
1006 snprintf(priv
->mdio
->id
, MII_BUS_ID_SIZE
, "%s-%d",
1007 priv
->mdio
->name
, pdev
->id
);
1008 priv
->mdio
->read
= ethoc_mdio_read
;
1009 priv
->mdio
->write
= ethoc_mdio_write
;
1010 priv
->mdio
->reset
= ethoc_mdio_reset
;
1011 priv
->mdio
->priv
= priv
;
1013 priv
->mdio
->irq
= kmalloc(sizeof(int) * PHY_MAX_ADDR
, GFP_KERNEL
);
1014 if (!priv
->mdio
->irq
) {
1019 for (phy
= 0; phy
< PHY_MAX_ADDR
; phy
++)
1020 priv
->mdio
->irq
[phy
] = PHY_POLL
;
1022 ret
= mdiobus_register(priv
->mdio
);
1024 dev_err(&netdev
->dev
, "failed to register MDIO bus\n");
1028 ret
= ethoc_mdio_probe(netdev
);
1030 dev_err(&netdev
->dev
, "failed to probe MDIO bus\n");
1034 ether_setup(netdev
);
1036 /* setup the net_device structure */
1037 netdev
->netdev_ops
= ðoc_netdev_ops
;
1038 netdev
->watchdog_timeo
= ETHOC_TIMEOUT
;
1039 netdev
->features
|= 0;
1042 memset(&priv
->napi
, 0, sizeof(priv
->napi
));
1043 netif_napi_add(netdev
, &priv
->napi
, ethoc_poll
, 64);
1045 spin_lock_init(&priv
->rx_lock
);
1046 spin_lock_init(&priv
->lock
);
1048 ret
= register_netdev(netdev
);
1050 dev_err(&netdev
->dev
, "failed to register interface\n");
1057 mdiobus_unregister(priv
->mdio
);
1059 kfree(priv
->mdio
->irq
);
1060 mdiobus_free(priv
->mdio
);
1062 if (priv
->dma_alloc
)
1063 dma_free_coherent(NULL
, priv
->dma_alloc
, priv
->membase
,
1065 free_netdev(netdev
);
1071 * ethoc_remove() - shutdown OpenCores ethernet MAC
1072 * @pdev: platform device
1074 static int ethoc_remove(struct platform_device
*pdev
)
1076 struct net_device
*netdev
= platform_get_drvdata(pdev
);
1077 struct ethoc
*priv
= netdev_priv(netdev
);
1079 platform_set_drvdata(pdev
, NULL
);
1082 phy_disconnect(priv
->phy
);
1086 mdiobus_unregister(priv
->mdio
);
1087 kfree(priv
->mdio
->irq
);
1088 mdiobus_free(priv
->mdio
);
1090 if (priv
->dma_alloc
)
1091 dma_free_coherent(NULL
, priv
->dma_alloc
, priv
->membase
,
1093 unregister_netdev(netdev
);
1094 free_netdev(netdev
);
1101 static int ethoc_suspend(struct platform_device
*pdev
, pm_message_t state
)
1106 static int ethoc_resume(struct platform_device
*pdev
)
1111 # define ethoc_suspend NULL
1112 # define ethoc_resume NULL
1115 static struct platform_driver ethoc_driver
= {
1116 .probe
= ethoc_probe
,
1117 .remove
= ethoc_remove
,
1118 .suspend
= ethoc_suspend
,
1119 .resume
= ethoc_resume
,
1125 static int __init
ethoc_init(void)
1127 return platform_driver_register(ðoc_driver
);
1130 static void __exit
ethoc_exit(void)
1132 platform_driver_unregister(ðoc_driver
);
1135 module_init(ethoc_init
);
1136 module_exit(ethoc_exit
);
1138 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1139 MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1140 MODULE_LICENSE("GPL v2");