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Merge branch 'perf/nmi' into perf/core
[deliverable/linux.git] / drivers / net / fec.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/workqueue.h>
38 #include <linux/bitops.h>
39 #include <linux/io.h>
40 #include <linux/irq.h>
41 #include <linux/clk.h>
42 #include <linux/platform_device.h>
43 #include <linux/phy.h>
44 #include <linux/fec.h>
45
46 #include <asm/cacheflush.h>
47
48 #ifndef CONFIG_ARCH_MXC
49 #include <asm/coldfire.h>
50 #include <asm/mcfsim.h>
51 #endif
52
53 #include "fec.h"
54
55 #ifdef CONFIG_ARCH_MXC
56 #include <mach/hardware.h>
57 #define FEC_ALIGNMENT 0xf
58 #else
59 #define FEC_ALIGNMENT 0x3
60 #endif
61
62 /*
63 * Define the fixed address of the FEC hardware.
64 */
65 #if defined(CONFIG_M5272)
66
67 static unsigned char fec_mac_default[] = {
68 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
69 };
70
71 /*
72 * Some hardware gets it MAC address out of local flash memory.
73 * if this is non-zero then assume it is the address to get MAC from.
74 */
75 #if defined(CONFIG_NETtel)
76 #define FEC_FLASHMAC 0xf0006006
77 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
78 #define FEC_FLASHMAC 0xf0006000
79 #elif defined(CONFIG_CANCam)
80 #define FEC_FLASHMAC 0xf0020000
81 #elif defined (CONFIG_M5272C3)
82 #define FEC_FLASHMAC (0xffe04000 + 4)
83 #elif defined(CONFIG_MOD5272)
84 #define FEC_FLASHMAC 0xffc0406b
85 #else
86 #define FEC_FLASHMAC 0
87 #endif
88 #endif /* CONFIG_M5272 */
89
90 /* The number of Tx and Rx buffers. These are allocated from the page
91 * pool. The code may assume these are power of two, so it it best
92 * to keep them that size.
93 * We don't need to allocate pages for the transmitter. We just use
94 * the skbuffer directly.
95 */
96 #define FEC_ENET_RX_PAGES 8
97 #define FEC_ENET_RX_FRSIZE 2048
98 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
99 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
100 #define FEC_ENET_TX_FRSIZE 2048
101 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
102 #define TX_RING_SIZE 16 /* Must be power of two */
103 #define TX_RING_MOD_MASK 15 /* for this to work */
104
105 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
106 #error "FEC: descriptor ring size constants too large"
107 #endif
108
109 /* Interrupt events/masks. */
110 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
111 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
112 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
113 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
114 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
115 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
116 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
117 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
118 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
119 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
120
121 /* The FEC stores dest/src/type, data, and checksum for receive packets.
122 */
123 #define PKT_MAXBUF_SIZE 1518
124 #define PKT_MINBUF_SIZE 64
125 #define PKT_MAXBLR_SIZE 1520
126
127
128 /*
129 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
130 * size bits. Other FEC hardware does not, so we need to take that into
131 * account when setting it.
132 */
133 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
134 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
135 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
136 #else
137 #define OPT_FRAME_SIZE 0
138 #endif
139
140 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
141 * tx_bd_base always point to the base of the buffer descriptors. The
142 * cur_rx and cur_tx point to the currently available buffer.
143 * The dirty_tx tracks the current buffer that is being sent by the
144 * controller. The cur_tx and dirty_tx are equal under both completely
145 * empty and completely full conditions. The empty/ready indicator in
146 * the buffer descriptor determines the actual condition.
147 */
148 struct fec_enet_private {
149 /* Hardware registers of the FEC device */
150 void __iomem *hwp;
151
152 struct net_device *netdev;
153
154 struct clk *clk;
155
156 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
157 unsigned char *tx_bounce[TX_RING_SIZE];
158 struct sk_buff* tx_skbuff[TX_RING_SIZE];
159 struct sk_buff* rx_skbuff[RX_RING_SIZE];
160 ushort skb_cur;
161 ushort skb_dirty;
162
163 /* CPM dual port RAM relative addresses */
164 dma_addr_t bd_dma;
165 /* Address of Rx and Tx buffers */
166 struct bufdesc *rx_bd_base;
167 struct bufdesc *tx_bd_base;
168 /* The next free ring entry */
169 struct bufdesc *cur_rx, *cur_tx;
170 /* The ring entries to be free()ed */
171 struct bufdesc *dirty_tx;
172
173 uint tx_full;
174 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
175 spinlock_t hw_lock;
176
177 struct platform_device *pdev;
178
179 int opened;
180
181 /* Phylib and MDIO interface */
182 struct mii_bus *mii_bus;
183 struct phy_device *phy_dev;
184 int mii_timeout;
185 uint phy_speed;
186 phy_interface_t phy_interface;
187 int index;
188 int link;
189 int full_duplex;
190 };
191
192 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
193 static void fec_enet_tx(struct net_device *dev);
194 static void fec_enet_rx(struct net_device *dev);
195 static int fec_enet_close(struct net_device *dev);
196 static void fec_restart(struct net_device *dev, int duplex);
197 static void fec_stop(struct net_device *dev);
198
199 /* FEC MII MMFR bits definition */
200 #define FEC_MMFR_ST (1 << 30)
201 #define FEC_MMFR_OP_READ (2 << 28)
202 #define FEC_MMFR_OP_WRITE (1 << 28)
203 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
204 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
205 #define FEC_MMFR_TA (2 << 16)
206 #define FEC_MMFR_DATA(v) (v & 0xffff)
207
208 #define FEC_MII_TIMEOUT 10000
209
210 /* Transmitter timeout */
211 #define TX_TIMEOUT (2 * HZ)
212
213 static int
214 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
215 {
216 struct fec_enet_private *fep = netdev_priv(dev);
217 struct bufdesc *bdp;
218 void *bufaddr;
219 unsigned short status;
220 unsigned long flags;
221
222 if (!fep->link) {
223 /* Link is down or autonegotiation is in progress. */
224 return NETDEV_TX_BUSY;
225 }
226
227 spin_lock_irqsave(&fep->hw_lock, flags);
228 /* Fill in a Tx ring entry */
229 bdp = fep->cur_tx;
230
231 status = bdp->cbd_sc;
232
233 if (status & BD_ENET_TX_READY) {
234 /* Ooops. All transmit buffers are full. Bail out.
235 * This should not happen, since dev->tbusy should be set.
236 */
237 printk("%s: tx queue full!.\n", dev->name);
238 spin_unlock_irqrestore(&fep->hw_lock, flags);
239 return NETDEV_TX_BUSY;
240 }
241
242 /* Clear all of the status flags */
243 status &= ~BD_ENET_TX_STATS;
244
245 /* Set buffer length and buffer pointer */
246 bufaddr = skb->data;
247 bdp->cbd_datlen = skb->len;
248
249 /*
250 * On some FEC implementations data must be aligned on
251 * 4-byte boundaries. Use bounce buffers to copy data
252 * and get it aligned. Ugh.
253 */
254 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
255 unsigned int index;
256 index = bdp - fep->tx_bd_base;
257 memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len);
258 bufaddr = fep->tx_bounce[index];
259 }
260
261 /* Save skb pointer */
262 fep->tx_skbuff[fep->skb_cur] = skb;
263
264 dev->stats.tx_bytes += skb->len;
265 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
266
267 /* Push the data cache so the CPM does not get stale memory
268 * data.
269 */
270 bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr,
271 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
272
273 /* Send it on its way. Tell FEC it's ready, interrupt when done,
274 * it's the last BD of the frame, and to put the CRC on the end.
275 */
276 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
277 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
278 bdp->cbd_sc = status;
279
280 /* Trigger transmission start */
281 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
282
283 /* If this was the last BD in the ring, start at the beginning again. */
284 if (status & BD_ENET_TX_WRAP)
285 bdp = fep->tx_bd_base;
286 else
287 bdp++;
288
289 if (bdp == fep->dirty_tx) {
290 fep->tx_full = 1;
291 netif_stop_queue(dev);
292 }
293
294 fep->cur_tx = bdp;
295
296 spin_unlock_irqrestore(&fep->hw_lock, flags);
297
298 return NETDEV_TX_OK;
299 }
300
301 static void
302 fec_timeout(struct net_device *dev)
303 {
304 struct fec_enet_private *fep = netdev_priv(dev);
305
306 dev->stats.tx_errors++;
307
308 fec_restart(dev, fep->full_duplex);
309 netif_wake_queue(dev);
310 }
311
312 static irqreturn_t
313 fec_enet_interrupt(int irq, void * dev_id)
314 {
315 struct net_device *dev = dev_id;
316 struct fec_enet_private *fep = netdev_priv(dev);
317 uint int_events;
318 irqreturn_t ret = IRQ_NONE;
319
320 do {
321 int_events = readl(fep->hwp + FEC_IEVENT);
322 writel(int_events, fep->hwp + FEC_IEVENT);
323
324 if (int_events & FEC_ENET_RXF) {
325 ret = IRQ_HANDLED;
326 fec_enet_rx(dev);
327 }
328
329 /* Transmit OK, or non-fatal error. Update the buffer
330 * descriptors. FEC handles all errors, we just discover
331 * them as part of the transmit process.
332 */
333 if (int_events & FEC_ENET_TXF) {
334 ret = IRQ_HANDLED;
335 fec_enet_tx(dev);
336 }
337 } while (int_events);
338
339 return ret;
340 }
341
342
343 static void
344 fec_enet_tx(struct net_device *dev)
345 {
346 struct fec_enet_private *fep;
347 struct bufdesc *bdp;
348 unsigned short status;
349 struct sk_buff *skb;
350
351 fep = netdev_priv(dev);
352 spin_lock(&fep->hw_lock);
353 bdp = fep->dirty_tx;
354
355 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
356 if (bdp == fep->cur_tx && fep->tx_full == 0)
357 break;
358
359 dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
360 bdp->cbd_bufaddr = 0;
361
362 skb = fep->tx_skbuff[fep->skb_dirty];
363 /* Check for errors. */
364 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
365 BD_ENET_TX_RL | BD_ENET_TX_UN |
366 BD_ENET_TX_CSL)) {
367 dev->stats.tx_errors++;
368 if (status & BD_ENET_TX_HB) /* No heartbeat */
369 dev->stats.tx_heartbeat_errors++;
370 if (status & BD_ENET_TX_LC) /* Late collision */
371 dev->stats.tx_window_errors++;
372 if (status & BD_ENET_TX_RL) /* Retrans limit */
373 dev->stats.tx_aborted_errors++;
374 if (status & BD_ENET_TX_UN) /* Underrun */
375 dev->stats.tx_fifo_errors++;
376 if (status & BD_ENET_TX_CSL) /* Carrier lost */
377 dev->stats.tx_carrier_errors++;
378 } else {
379 dev->stats.tx_packets++;
380 }
381
382 if (status & BD_ENET_TX_READY)
383 printk("HEY! Enet xmit interrupt and TX_READY.\n");
384
385 /* Deferred means some collisions occurred during transmit,
386 * but we eventually sent the packet OK.
387 */
388 if (status & BD_ENET_TX_DEF)
389 dev->stats.collisions++;
390
391 /* Free the sk buffer associated with this last transmit */
392 dev_kfree_skb_any(skb);
393 fep->tx_skbuff[fep->skb_dirty] = NULL;
394 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
395
396 /* Update pointer to next buffer descriptor to be transmitted */
397 if (status & BD_ENET_TX_WRAP)
398 bdp = fep->tx_bd_base;
399 else
400 bdp++;
401
402 /* Since we have freed up a buffer, the ring is no longer full
403 */
404 if (fep->tx_full) {
405 fep->tx_full = 0;
406 if (netif_queue_stopped(dev))
407 netif_wake_queue(dev);
408 }
409 }
410 fep->dirty_tx = bdp;
411 spin_unlock(&fep->hw_lock);
412 }
413
414
415 /* During a receive, the cur_rx points to the current incoming buffer.
416 * When we update through the ring, if the next incoming buffer has
417 * not been given to the system, we just set the empty indicator,
418 * effectively tossing the packet.
419 */
420 static void
421 fec_enet_rx(struct net_device *dev)
422 {
423 struct fec_enet_private *fep = netdev_priv(dev);
424 struct bufdesc *bdp;
425 unsigned short status;
426 struct sk_buff *skb;
427 ushort pkt_len;
428 __u8 *data;
429
430 #ifdef CONFIG_M532x
431 flush_cache_all();
432 #endif
433
434 spin_lock(&fep->hw_lock);
435
436 /* First, grab all of the stats for the incoming packet.
437 * These get messed up if we get called due to a busy condition.
438 */
439 bdp = fep->cur_rx;
440
441 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
442
443 /* Since we have allocated space to hold a complete frame,
444 * the last indicator should be set.
445 */
446 if ((status & BD_ENET_RX_LAST) == 0)
447 printk("FEC ENET: rcv is not +last\n");
448
449 if (!fep->opened)
450 goto rx_processing_done;
451
452 /* Check for errors. */
453 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
454 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
455 dev->stats.rx_errors++;
456 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
457 /* Frame too long or too short. */
458 dev->stats.rx_length_errors++;
459 }
460 if (status & BD_ENET_RX_NO) /* Frame alignment */
461 dev->stats.rx_frame_errors++;
462 if (status & BD_ENET_RX_CR) /* CRC Error */
463 dev->stats.rx_crc_errors++;
464 if (status & BD_ENET_RX_OV) /* FIFO overrun */
465 dev->stats.rx_fifo_errors++;
466 }
467
468 /* Report late collisions as a frame error.
469 * On this error, the BD is closed, but we don't know what we
470 * have in the buffer. So, just drop this frame on the floor.
471 */
472 if (status & BD_ENET_RX_CL) {
473 dev->stats.rx_errors++;
474 dev->stats.rx_frame_errors++;
475 goto rx_processing_done;
476 }
477
478 /* Process the incoming frame. */
479 dev->stats.rx_packets++;
480 pkt_len = bdp->cbd_datlen;
481 dev->stats.rx_bytes += pkt_len;
482 data = (__u8*)__va(bdp->cbd_bufaddr);
483
484 dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
485 DMA_FROM_DEVICE);
486
487 /* This does 16 byte alignment, exactly what we need.
488 * The packet length includes FCS, but we don't want to
489 * include that when passing upstream as it messes up
490 * bridging applications.
491 */
492 skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
493
494 if (unlikely(!skb)) {
495 printk("%s: Memory squeeze, dropping packet.\n",
496 dev->name);
497 dev->stats.rx_dropped++;
498 } else {
499 skb_reserve(skb, NET_IP_ALIGN);
500 skb_put(skb, pkt_len - 4); /* Make room */
501 skb_copy_to_linear_data(skb, data, pkt_len - 4);
502 skb->protocol = eth_type_trans(skb, dev);
503 netif_rx(skb);
504 }
505
506 bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen,
507 DMA_FROM_DEVICE);
508 rx_processing_done:
509 /* Clear the status flags for this buffer */
510 status &= ~BD_ENET_RX_STATS;
511
512 /* Mark the buffer empty */
513 status |= BD_ENET_RX_EMPTY;
514 bdp->cbd_sc = status;
515
516 /* Update BD pointer to next entry */
517 if (status & BD_ENET_RX_WRAP)
518 bdp = fep->rx_bd_base;
519 else
520 bdp++;
521 /* Doing this here will keep the FEC running while we process
522 * incoming frames. On a heavily loaded network, we should be
523 * able to keep up at the expense of system resources.
524 */
525 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
526 }
527 fep->cur_rx = bdp;
528
529 spin_unlock(&fep->hw_lock);
530 }
531
532 /* ------------------------------------------------------------------------- */
533 #ifdef CONFIG_M5272
534 static void __inline__ fec_get_mac(struct net_device *dev)
535 {
536 struct fec_enet_private *fep = netdev_priv(dev);
537 unsigned char *iap, tmpaddr[ETH_ALEN];
538
539 if (FEC_FLASHMAC) {
540 /*
541 * Get MAC address from FLASH.
542 * If it is all 1's or 0's, use the default.
543 */
544 iap = (unsigned char *)FEC_FLASHMAC;
545 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
546 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
547 iap = fec_mac_default;
548 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
549 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
550 iap = fec_mac_default;
551 } else {
552 *((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW);
553 *((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
554 iap = &tmpaddr[0];
555 }
556
557 memcpy(dev->dev_addr, iap, ETH_ALEN);
558
559 /* Adjust MAC if using default MAC address */
560 if (iap == fec_mac_default)
561 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
562 }
563 #endif
564
565 /* ------------------------------------------------------------------------- */
566
567 /*
568 * Phy section
569 */
570 static void fec_enet_adjust_link(struct net_device *dev)
571 {
572 struct fec_enet_private *fep = netdev_priv(dev);
573 struct phy_device *phy_dev = fep->phy_dev;
574 unsigned long flags;
575
576 int status_change = 0;
577
578 spin_lock_irqsave(&fep->hw_lock, flags);
579
580 /* Prevent a state halted on mii error */
581 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
582 phy_dev->state = PHY_RESUMING;
583 goto spin_unlock;
584 }
585
586 /* Duplex link change */
587 if (phy_dev->link) {
588 if (fep->full_duplex != phy_dev->duplex) {
589 fec_restart(dev, phy_dev->duplex);
590 status_change = 1;
591 }
592 }
593
594 /* Link on or off change */
595 if (phy_dev->link != fep->link) {
596 fep->link = phy_dev->link;
597 if (phy_dev->link)
598 fec_restart(dev, phy_dev->duplex);
599 else
600 fec_stop(dev);
601 status_change = 1;
602 }
603
604 spin_unlock:
605 spin_unlock_irqrestore(&fep->hw_lock, flags);
606
607 if (status_change)
608 phy_print_status(phy_dev);
609 }
610
611 /*
612 * NOTE: a MII transaction is during around 25 us, so polling it...
613 */
614 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
615 {
616 struct fec_enet_private *fep = bus->priv;
617 int timeout = FEC_MII_TIMEOUT;
618
619 fep->mii_timeout = 0;
620
621 /* clear MII end of transfer bit*/
622 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
623
624 /* start a read op */
625 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
626 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
627 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
628
629 /* wait for end of transfer */
630 while (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_MII)) {
631 cpu_relax();
632 if (timeout-- < 0) {
633 fep->mii_timeout = 1;
634 printk(KERN_ERR "FEC: MDIO read timeout\n");
635 return -ETIMEDOUT;
636 }
637 }
638
639 /* return value */
640 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
641 }
642
643 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
644 u16 value)
645 {
646 struct fec_enet_private *fep = bus->priv;
647 int timeout = FEC_MII_TIMEOUT;
648
649 fep->mii_timeout = 0;
650
651 /* clear MII end of transfer bit*/
652 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
653
654 /* start a read op */
655 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
656 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
657 FEC_MMFR_TA | FEC_MMFR_DATA(value),
658 fep->hwp + FEC_MII_DATA);
659
660 /* wait for end of transfer */
661 while (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_MII)) {
662 cpu_relax();
663 if (timeout-- < 0) {
664 fep->mii_timeout = 1;
665 printk(KERN_ERR "FEC: MDIO write timeout\n");
666 return -ETIMEDOUT;
667 }
668 }
669
670 return 0;
671 }
672
673 static int fec_enet_mdio_reset(struct mii_bus *bus)
674 {
675 return 0;
676 }
677
678 static int fec_enet_mii_probe(struct net_device *dev)
679 {
680 struct fec_enet_private *fep = netdev_priv(dev);
681 struct phy_device *phy_dev = NULL;
682 int phy_addr;
683
684 fep->phy_dev = NULL;
685
686 /* find the first phy */
687 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
688 if (fep->mii_bus->phy_map[phy_addr]) {
689 phy_dev = fep->mii_bus->phy_map[phy_addr];
690 break;
691 }
692 }
693
694 if (!phy_dev) {
695 printk(KERN_ERR "%s: no PHY found\n", dev->name);
696 return -ENODEV;
697 }
698
699 /* attach the mac to the phy */
700 phy_dev = phy_connect(dev, dev_name(&phy_dev->dev),
701 &fec_enet_adjust_link, 0,
702 PHY_INTERFACE_MODE_MII);
703 if (IS_ERR(phy_dev)) {
704 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
705 return PTR_ERR(phy_dev);
706 }
707
708 /* mask with MAC supported features */
709 phy_dev->supported &= PHY_BASIC_FEATURES;
710 phy_dev->advertising = phy_dev->supported;
711
712 fep->phy_dev = phy_dev;
713 fep->link = 0;
714 fep->full_duplex = 0;
715
716 printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] "
717 "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name,
718 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
719 fep->phy_dev->irq);
720
721 return 0;
722 }
723
724 static int fec_enet_mii_init(struct platform_device *pdev)
725 {
726 struct net_device *dev = platform_get_drvdata(pdev);
727 struct fec_enet_private *fep = netdev_priv(dev);
728 int err = -ENXIO, i;
729
730 fep->mii_timeout = 0;
731
732 /*
733 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
734 */
735 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
736 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
737
738 fep->mii_bus = mdiobus_alloc();
739 if (fep->mii_bus == NULL) {
740 err = -ENOMEM;
741 goto err_out;
742 }
743
744 fep->mii_bus->name = "fec_enet_mii_bus";
745 fep->mii_bus->read = fec_enet_mdio_read;
746 fep->mii_bus->write = fec_enet_mdio_write;
747 fep->mii_bus->reset = fec_enet_mdio_reset;
748 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
749 fep->mii_bus->priv = fep;
750 fep->mii_bus->parent = &pdev->dev;
751
752 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
753 if (!fep->mii_bus->irq) {
754 err = -ENOMEM;
755 goto err_out_free_mdiobus;
756 }
757
758 for (i = 0; i < PHY_MAX_ADDR; i++)
759 fep->mii_bus->irq[i] = PHY_POLL;
760
761 platform_set_drvdata(dev, fep->mii_bus);
762
763 if (mdiobus_register(fep->mii_bus))
764 goto err_out_free_mdio_irq;
765
766 return 0;
767
768 err_out_free_mdio_irq:
769 kfree(fep->mii_bus->irq);
770 err_out_free_mdiobus:
771 mdiobus_free(fep->mii_bus);
772 err_out:
773 return err;
774 }
775
776 static void fec_enet_mii_remove(struct fec_enet_private *fep)
777 {
778 if (fep->phy_dev)
779 phy_disconnect(fep->phy_dev);
780 mdiobus_unregister(fep->mii_bus);
781 kfree(fep->mii_bus->irq);
782 mdiobus_free(fep->mii_bus);
783 }
784
785 static int fec_enet_get_settings(struct net_device *dev,
786 struct ethtool_cmd *cmd)
787 {
788 struct fec_enet_private *fep = netdev_priv(dev);
789 struct phy_device *phydev = fep->phy_dev;
790
791 if (!phydev)
792 return -ENODEV;
793
794 return phy_ethtool_gset(phydev, cmd);
795 }
796
797 static int fec_enet_set_settings(struct net_device *dev,
798 struct ethtool_cmd *cmd)
799 {
800 struct fec_enet_private *fep = netdev_priv(dev);
801 struct phy_device *phydev = fep->phy_dev;
802
803 if (!phydev)
804 return -ENODEV;
805
806 return phy_ethtool_sset(phydev, cmd);
807 }
808
809 static void fec_enet_get_drvinfo(struct net_device *dev,
810 struct ethtool_drvinfo *info)
811 {
812 struct fec_enet_private *fep = netdev_priv(dev);
813
814 strcpy(info->driver, fep->pdev->dev.driver->name);
815 strcpy(info->version, "Revision: 1.0");
816 strcpy(info->bus_info, dev_name(&dev->dev));
817 }
818
819 static struct ethtool_ops fec_enet_ethtool_ops = {
820 .get_settings = fec_enet_get_settings,
821 .set_settings = fec_enet_set_settings,
822 .get_drvinfo = fec_enet_get_drvinfo,
823 .get_link = ethtool_op_get_link,
824 };
825
826 static int fec_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
827 {
828 struct fec_enet_private *fep = netdev_priv(dev);
829 struct phy_device *phydev = fep->phy_dev;
830
831 if (!netif_running(dev))
832 return -EINVAL;
833
834 if (!phydev)
835 return -ENODEV;
836
837 return phy_mii_ioctl(phydev, if_mii(rq), cmd);
838 }
839
840 static void fec_enet_free_buffers(struct net_device *dev)
841 {
842 struct fec_enet_private *fep = netdev_priv(dev);
843 int i;
844 struct sk_buff *skb;
845 struct bufdesc *bdp;
846
847 bdp = fep->rx_bd_base;
848 for (i = 0; i < RX_RING_SIZE; i++) {
849 skb = fep->rx_skbuff[i];
850
851 if (bdp->cbd_bufaddr)
852 dma_unmap_single(&dev->dev, bdp->cbd_bufaddr,
853 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
854 if (skb)
855 dev_kfree_skb(skb);
856 bdp++;
857 }
858
859 bdp = fep->tx_bd_base;
860 for (i = 0; i < TX_RING_SIZE; i++)
861 kfree(fep->tx_bounce[i]);
862 }
863
864 static int fec_enet_alloc_buffers(struct net_device *dev)
865 {
866 struct fec_enet_private *fep = netdev_priv(dev);
867 int i;
868 struct sk_buff *skb;
869 struct bufdesc *bdp;
870
871 bdp = fep->rx_bd_base;
872 for (i = 0; i < RX_RING_SIZE; i++) {
873 skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE);
874 if (!skb) {
875 fec_enet_free_buffers(dev);
876 return -ENOMEM;
877 }
878 fep->rx_skbuff[i] = skb;
879
880 bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data,
881 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
882 bdp->cbd_sc = BD_ENET_RX_EMPTY;
883 bdp++;
884 }
885
886 /* Set the last buffer to wrap. */
887 bdp--;
888 bdp->cbd_sc |= BD_SC_WRAP;
889
890 bdp = fep->tx_bd_base;
891 for (i = 0; i < TX_RING_SIZE; i++) {
892 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
893
894 bdp->cbd_sc = 0;
895 bdp->cbd_bufaddr = 0;
896 bdp++;
897 }
898
899 /* Set the last buffer to wrap. */
900 bdp--;
901 bdp->cbd_sc |= BD_SC_WRAP;
902
903 return 0;
904 }
905
906 static int
907 fec_enet_open(struct net_device *dev)
908 {
909 struct fec_enet_private *fep = netdev_priv(dev);
910 int ret;
911
912 /* I should reset the ring buffers here, but I don't yet know
913 * a simple way to do that.
914 */
915
916 ret = fec_enet_alloc_buffers(dev);
917 if (ret)
918 return ret;
919
920 /* Probe and connect to PHY when open the interface */
921 ret = fec_enet_mii_probe(dev);
922 if (ret) {
923 fec_enet_free_buffers(dev);
924 return ret;
925 }
926 phy_start(fep->phy_dev);
927 netif_start_queue(dev);
928 fep->opened = 1;
929 return 0;
930 }
931
932 static int
933 fec_enet_close(struct net_device *dev)
934 {
935 struct fec_enet_private *fep = netdev_priv(dev);
936
937 /* Don't know what to do yet. */
938 fep->opened = 0;
939 netif_stop_queue(dev);
940 fec_stop(dev);
941
942 if (fep->phy_dev)
943 phy_disconnect(fep->phy_dev);
944
945 fec_enet_free_buffers(dev);
946
947 return 0;
948 }
949
950 /* Set or clear the multicast filter for this adaptor.
951 * Skeleton taken from sunlance driver.
952 * The CPM Ethernet implementation allows Multicast as well as individual
953 * MAC address filtering. Some of the drivers check to make sure it is
954 * a group multicast address, and discard those that are not. I guess I
955 * will do the same for now, but just remove the test if you want
956 * individual filtering as well (do the upper net layers want or support
957 * this kind of feature?).
958 */
959
960 #define HASH_BITS 6 /* #bits in hash */
961 #define CRC32_POLY 0xEDB88320
962
963 static void set_multicast_list(struct net_device *dev)
964 {
965 struct fec_enet_private *fep = netdev_priv(dev);
966 struct netdev_hw_addr *ha;
967 unsigned int i, bit, data, crc, tmp;
968 unsigned char hash;
969
970 if (dev->flags & IFF_PROMISC) {
971 tmp = readl(fep->hwp + FEC_R_CNTRL);
972 tmp |= 0x8;
973 writel(tmp, fep->hwp + FEC_R_CNTRL);
974 return;
975 }
976
977 tmp = readl(fep->hwp + FEC_R_CNTRL);
978 tmp &= ~0x8;
979 writel(tmp, fep->hwp + FEC_R_CNTRL);
980
981 if (dev->flags & IFF_ALLMULTI) {
982 /* Catch all multicast addresses, so set the
983 * filter to all 1's
984 */
985 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
986 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
987
988 return;
989 }
990
991 /* Clear filter and add the addresses in hash register
992 */
993 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
994 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
995
996 netdev_for_each_mc_addr(ha, dev) {
997 /* Only support group multicast for now */
998 if (!(ha->addr[0] & 1))
999 continue;
1000
1001 /* calculate crc32 value of mac address */
1002 crc = 0xffffffff;
1003
1004 for (i = 0; i < dev->addr_len; i++) {
1005 data = ha->addr[i];
1006 for (bit = 0; bit < 8; bit++, data >>= 1) {
1007 crc = (crc >> 1) ^
1008 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1009 }
1010 }
1011
1012 /* only upper 6 bits (HASH_BITS) are used
1013 * which point to specific bit in he hash registers
1014 */
1015 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1016
1017 if (hash > 31) {
1018 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1019 tmp |= 1 << (hash - 32);
1020 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1021 } else {
1022 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1023 tmp |= 1 << hash;
1024 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1025 }
1026 }
1027 }
1028
1029 /* Set a MAC change in hardware. */
1030 static int
1031 fec_set_mac_address(struct net_device *dev, void *p)
1032 {
1033 struct fec_enet_private *fep = netdev_priv(dev);
1034 struct sockaddr *addr = p;
1035
1036 if (!is_valid_ether_addr(addr->sa_data))
1037 return -EADDRNOTAVAIL;
1038
1039 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1040
1041 writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
1042 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
1043 fep->hwp + FEC_ADDR_LOW);
1044 writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24),
1045 fep->hwp + FEC_ADDR_HIGH);
1046 return 0;
1047 }
1048
1049 static const struct net_device_ops fec_netdev_ops = {
1050 .ndo_open = fec_enet_open,
1051 .ndo_stop = fec_enet_close,
1052 .ndo_start_xmit = fec_enet_start_xmit,
1053 .ndo_set_multicast_list = set_multicast_list,
1054 .ndo_change_mtu = eth_change_mtu,
1055 .ndo_validate_addr = eth_validate_addr,
1056 .ndo_tx_timeout = fec_timeout,
1057 .ndo_set_mac_address = fec_set_mac_address,
1058 .ndo_do_ioctl = fec_enet_ioctl,
1059 };
1060
1061 /*
1062 * XXX: We need to clean up on failure exits here.
1063 *
1064 * index is only used in legacy code
1065 */
1066 static int fec_enet_init(struct net_device *dev, int index)
1067 {
1068 struct fec_enet_private *fep = netdev_priv(dev);
1069 struct bufdesc *cbd_base;
1070 struct bufdesc *bdp;
1071 int i;
1072
1073 /* Allocate memory for buffer descriptors. */
1074 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1075 GFP_KERNEL);
1076 if (!cbd_base) {
1077 printk("FEC: allocate descriptor memory failed?\n");
1078 return -ENOMEM;
1079 }
1080
1081 spin_lock_init(&fep->hw_lock);
1082
1083 fep->index = index;
1084 fep->hwp = (void __iomem *)dev->base_addr;
1085 fep->netdev = dev;
1086
1087 /* Set the Ethernet address */
1088 #ifdef CONFIG_M5272
1089 fec_get_mac(dev);
1090 #else
1091 {
1092 unsigned long l;
1093 l = readl(fep->hwp + FEC_ADDR_LOW);
1094 dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24);
1095 dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16);
1096 dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8);
1097 dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0);
1098 l = readl(fep->hwp + FEC_ADDR_HIGH);
1099 dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24);
1100 dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16);
1101 }
1102 #endif
1103
1104 /* Set receive and transmit descriptor base. */
1105 fep->rx_bd_base = cbd_base;
1106 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1107
1108 /* The FEC Ethernet specific entries in the device structure */
1109 dev->watchdog_timeo = TX_TIMEOUT;
1110 dev->netdev_ops = &fec_netdev_ops;
1111 dev->ethtool_ops = &fec_enet_ethtool_ops;
1112
1113 /* Initialize the receive buffer descriptors. */
1114 bdp = fep->rx_bd_base;
1115 for (i = 0; i < RX_RING_SIZE; i++) {
1116
1117 /* Initialize the BD for every fragment in the page. */
1118 bdp->cbd_sc = 0;
1119 bdp++;
1120 }
1121
1122 /* Set the last buffer to wrap */
1123 bdp--;
1124 bdp->cbd_sc |= BD_SC_WRAP;
1125
1126 /* ...and the same for transmit */
1127 bdp = fep->tx_bd_base;
1128 for (i = 0; i < TX_RING_SIZE; i++) {
1129
1130 /* Initialize the BD for every fragment in the page. */
1131 bdp->cbd_sc = 0;
1132 bdp->cbd_bufaddr = 0;
1133 bdp++;
1134 }
1135
1136 /* Set the last buffer to wrap */
1137 bdp--;
1138 bdp->cbd_sc |= BD_SC_WRAP;
1139
1140 fec_restart(dev, 0);
1141
1142 return 0;
1143 }
1144
1145 /* This function is called to start or restart the FEC during a link
1146 * change. This only happens when switching between half and full
1147 * duplex.
1148 */
1149 static void
1150 fec_restart(struct net_device *dev, int duplex)
1151 {
1152 struct fec_enet_private *fep = netdev_priv(dev);
1153 int i;
1154
1155 /* Whack a reset. We should wait for this. */
1156 writel(1, fep->hwp + FEC_ECNTRL);
1157 udelay(10);
1158
1159 /* Clear any outstanding interrupt. */
1160 writel(0xffc00000, fep->hwp + FEC_IEVENT);
1161
1162 /* Reset all multicast. */
1163 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1164 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1165 #ifndef CONFIG_M5272
1166 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1167 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1168 #endif
1169
1170 /* Set maximum receive buffer size. */
1171 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
1172
1173 /* Set receive and transmit descriptor base. */
1174 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
1175 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
1176 fep->hwp + FEC_X_DES_START);
1177
1178 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1179 fep->cur_rx = fep->rx_bd_base;
1180
1181 /* Reset SKB transmit buffers. */
1182 fep->skb_cur = fep->skb_dirty = 0;
1183 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
1184 if (fep->tx_skbuff[i]) {
1185 dev_kfree_skb_any(fep->tx_skbuff[i]);
1186 fep->tx_skbuff[i] = NULL;
1187 }
1188 }
1189
1190 /* Enable MII mode */
1191 if (duplex) {
1192 /* MII enable / FD enable */
1193 writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
1194 writel(0x04, fep->hwp + FEC_X_CNTRL);
1195 } else {
1196 /* MII enable / No Rcv on Xmit */
1197 writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
1198 writel(0x0, fep->hwp + FEC_X_CNTRL);
1199 }
1200 fep->full_duplex = duplex;
1201
1202 /* Set MII speed */
1203 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1204
1205 #ifdef FEC_MIIGSK_ENR
1206 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
1207 /* disable the gasket and wait */
1208 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1209 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1210 udelay(1);
1211
1212 /* configure the gasket: RMII, 50 MHz, no loopback, no echo */
1213 writel(1, fep->hwp + FEC_MIIGSK_CFGR);
1214
1215 /* re-enable the gasket */
1216 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1217 }
1218 #endif
1219
1220 /* And last, enable the transmit and receive processing */
1221 writel(2, fep->hwp + FEC_ECNTRL);
1222 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1223
1224 /* Enable interrupts we wish to service */
1225 writel(FEC_ENET_TXF | FEC_ENET_RXF, fep->hwp + FEC_IMASK);
1226 }
1227
1228 static void
1229 fec_stop(struct net_device *dev)
1230 {
1231 struct fec_enet_private *fep = netdev_priv(dev);
1232
1233 /* We cannot expect a graceful transmit stop without link !!! */
1234 if (fep->link) {
1235 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1236 udelay(10);
1237 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1238 printk("fec_stop : Graceful transmit stop did not complete !\n");
1239 }
1240
1241 /* Whack a reset. We should wait for this. */
1242 writel(1, fep->hwp + FEC_ECNTRL);
1243 udelay(10);
1244
1245 /* Clear outstanding MII command interrupts. */
1246 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
1247
1248 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1249 }
1250
1251 static int __devinit
1252 fec_probe(struct platform_device *pdev)
1253 {
1254 struct fec_enet_private *fep;
1255 struct fec_platform_data *pdata;
1256 struct net_device *ndev;
1257 int i, irq, ret = 0;
1258 struct resource *r;
1259
1260 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1261 if (!r)
1262 return -ENXIO;
1263
1264 r = request_mem_region(r->start, resource_size(r), pdev->name);
1265 if (!r)
1266 return -EBUSY;
1267
1268 /* Init network device */
1269 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1270 if (!ndev)
1271 return -ENOMEM;
1272
1273 SET_NETDEV_DEV(ndev, &pdev->dev);
1274
1275 /* setup board info structure */
1276 fep = netdev_priv(ndev);
1277 memset(fep, 0, sizeof(*fep));
1278
1279 ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r));
1280 fep->pdev = pdev;
1281
1282 if (!ndev->base_addr) {
1283 ret = -ENOMEM;
1284 goto failed_ioremap;
1285 }
1286
1287 platform_set_drvdata(pdev, ndev);
1288
1289 pdata = pdev->dev.platform_data;
1290 if (pdata)
1291 fep->phy_interface = pdata->phy;
1292
1293 /* This device has up to three irqs on some platforms */
1294 for (i = 0; i < 3; i++) {
1295 irq = platform_get_irq(pdev, i);
1296 if (i && irq < 0)
1297 break;
1298 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1299 if (ret) {
1300 while (i >= 0) {
1301 irq = platform_get_irq(pdev, i);
1302 free_irq(irq, ndev);
1303 i--;
1304 }
1305 goto failed_irq;
1306 }
1307 }
1308
1309 fep->clk = clk_get(&pdev->dev, "fec_clk");
1310 if (IS_ERR(fep->clk)) {
1311 ret = PTR_ERR(fep->clk);
1312 goto failed_clk;
1313 }
1314 clk_enable(fep->clk);
1315
1316 ret = fec_enet_init(ndev, 0);
1317 if (ret)
1318 goto failed_init;
1319
1320 ret = fec_enet_mii_init(pdev);
1321 if (ret)
1322 goto failed_mii_init;
1323
1324 ret = register_netdev(ndev);
1325 if (ret)
1326 goto failed_register;
1327
1328 return 0;
1329
1330 failed_register:
1331 fec_enet_mii_remove(fep);
1332 failed_mii_init:
1333 failed_init:
1334 clk_disable(fep->clk);
1335 clk_put(fep->clk);
1336 failed_clk:
1337 for (i = 0; i < 3; i++) {
1338 irq = platform_get_irq(pdev, i);
1339 if (irq > 0)
1340 free_irq(irq, ndev);
1341 }
1342 failed_irq:
1343 iounmap((void __iomem *)ndev->base_addr);
1344 failed_ioremap:
1345 free_netdev(ndev);
1346
1347 return ret;
1348 }
1349
1350 static int __devexit
1351 fec_drv_remove(struct platform_device *pdev)
1352 {
1353 struct net_device *ndev = platform_get_drvdata(pdev);
1354 struct fec_enet_private *fep = netdev_priv(ndev);
1355
1356 platform_set_drvdata(pdev, NULL);
1357
1358 fec_stop(ndev);
1359 fec_enet_mii_remove(fep);
1360 clk_disable(fep->clk);
1361 clk_put(fep->clk);
1362 iounmap((void __iomem *)ndev->base_addr);
1363 unregister_netdev(ndev);
1364 free_netdev(ndev);
1365 return 0;
1366 }
1367
1368 static int
1369 fec_suspend(struct platform_device *dev, pm_message_t state)
1370 {
1371 struct net_device *ndev = platform_get_drvdata(dev);
1372 struct fec_enet_private *fep;
1373
1374 if (ndev) {
1375 fep = netdev_priv(ndev);
1376 if (netif_running(ndev))
1377 fec_enet_close(ndev);
1378 clk_disable(fep->clk);
1379 }
1380 return 0;
1381 }
1382
1383 static int
1384 fec_resume(struct platform_device *dev)
1385 {
1386 struct net_device *ndev = platform_get_drvdata(dev);
1387 struct fec_enet_private *fep;
1388
1389 if (ndev) {
1390 fep = netdev_priv(ndev);
1391 clk_enable(fep->clk);
1392 if (netif_running(ndev))
1393 fec_enet_open(ndev);
1394 }
1395 return 0;
1396 }
1397
1398 static struct platform_driver fec_driver = {
1399 .driver = {
1400 .name = "fec",
1401 .owner = THIS_MODULE,
1402 },
1403 .probe = fec_probe,
1404 .remove = __devexit_p(fec_drv_remove),
1405 .suspend = fec_suspend,
1406 .resume = fec_resume,
1407 };
1408
1409 static int __init
1410 fec_enet_module_init(void)
1411 {
1412 printk(KERN_INFO "FEC Ethernet Driver\n");
1413
1414 return platform_driver_register(&fec_driver);
1415 }
1416
1417 static void __exit
1418 fec_enet_cleanup(void)
1419 {
1420 platform_driver_unregister(&fec_driver);
1421 }
1422
1423 module_exit(fec_enet_cleanup);
1424 module_init(fec_enet_module_init);
1425
1426 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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