1 /****************************************************************************/
4 * fec.h -- Fast Ethernet Controller for Motorola ColdFire 5230,
5 * 5231, 5232, 5234, 5235, 5270, 5271, 5272, 5274, 5275,
8 * (C) Copyright 2000-2003, Greg Ungerer (gerg@snapgear.com)
9 * (C) Copyright 2000-2001, Lineo (www.lineo.com)
12 /****************************************************************************/
15 /****************************************************************************/
17 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
19 * Just figures, Motorola would have to change the offsets for
20 * registers in the same peripheral device on different models
24 unsigned long fec_reserved0
;
25 unsigned long fec_ievent
; /* Interrupt event reg */
26 unsigned long fec_imask
; /* Interrupt mask reg */
27 unsigned long fec_reserved1
;
28 unsigned long fec_r_des_active
; /* Receive descriptor reg */
29 unsigned long fec_x_des_active
; /* Transmit descriptor reg */
30 unsigned long fec_reserved2
[3];
31 unsigned long fec_ecntrl
; /* Ethernet control reg */
32 unsigned long fec_reserved3
[6];
33 unsigned long fec_mii_data
; /* MII manage frame reg */
34 unsigned long fec_mii_speed
; /* MII speed control reg */
35 unsigned long fec_reserved4
[7];
36 unsigned long fec_mib_ctrlstat
; /* MIB control/status reg */
37 unsigned long fec_reserved5
[7];
38 unsigned long fec_r_cntrl
; /* Receive control reg */
39 unsigned long fec_reserved6
[15];
40 unsigned long fec_x_cntrl
; /* Transmit Control reg */
41 unsigned long fec_reserved7
[7];
42 unsigned long fec_addr_low
; /* Low 32bits MAC address */
43 unsigned long fec_addr_high
; /* High 16bits MAC address */
44 unsigned long fec_opd
; /* Opcode + Pause duration */
45 unsigned long fec_reserved8
[10];
46 unsigned long fec_hash_table_high
; /* High 32bits hash table */
47 unsigned long fec_hash_table_low
; /* Low 32bits hash table */
48 unsigned long fec_grp_hash_table_high
;/* High 32bits hash table */
49 unsigned long fec_grp_hash_table_low
; /* Low 32bits hash table */
50 unsigned long fec_reserved9
[7];
51 unsigned long fec_x_wmrk
; /* FIFO transmit water mark */
52 unsigned long fec_reserved10
;
53 unsigned long fec_r_bound
; /* FIFO receive bound reg */
54 unsigned long fec_r_fstart
; /* FIFO receive start reg */
55 unsigned long fec_reserved11
[11];
56 unsigned long fec_r_des_start
; /* Receive descriptor ring */
57 unsigned long fec_x_des_start
; /* Transmit descriptor ring */
58 unsigned long fec_r_buff_size
; /* Maximum receive buff size */
64 * Define device register set address map.
67 unsigned long fec_ecntrl
; /* Ethernet control reg */
68 unsigned long fec_ievent
; /* Interrupt even reg */
69 unsigned long fec_imask
; /* Interrupt mask reg */
70 unsigned long fec_ivec
; /* Interrupt vec status reg */
71 unsigned long fec_r_des_active
; /* Receive descriptor reg */
72 unsigned long fec_x_des_active
; /* Transmit descriptor reg */
73 unsigned long fec_reserved1
[10];
74 unsigned long fec_mii_data
; /* MII manage frame reg */
75 unsigned long fec_mii_speed
; /* MII speed control reg */
76 unsigned long fec_reserved2
[17];
77 unsigned long fec_r_bound
; /* FIFO receive bound reg */
78 unsigned long fec_r_fstart
; /* FIFO receive start reg */
79 unsigned long fec_reserved3
[4];
80 unsigned long fec_x_wmrk
; /* FIFO transmit water mark */
81 unsigned long fec_reserved4
;
82 unsigned long fec_x_fstart
; /* FIFO transmit start reg */
83 unsigned long fec_reserved5
[21];
84 unsigned long fec_r_cntrl
; /* Receive control reg */
85 unsigned long fec_max_frm_len
; /* Maximum frame length reg */
86 unsigned long fec_reserved6
[14];
87 unsigned long fec_x_cntrl
; /* Transmit Control reg */
88 unsigned long fec_reserved7
[158];
89 unsigned long fec_addr_low
; /* Low 32bits MAC address */
90 unsigned long fec_addr_high
; /* High 16bits MAC address */
91 unsigned long fec_hash_table_high
; /* High 32bits hash table */
92 unsigned long fec_hash_table_low
; /* Low 32bits hash table */
93 unsigned long fec_r_des_start
; /* Receive descriptor ring */
94 unsigned long fec_x_des_start
; /* Transmit descriptor ring */
95 unsigned long fec_r_buff_size
; /* Maximum receive buff size */
96 unsigned long reserved8
[9];
97 unsigned long fec_fifo_ram
[112]; /* FIFO RAM buffer */
100 #endif /* CONFIG_M5272 */
104 * Define the buffer descriptor structure.
106 typedef struct bufdesc
{
107 unsigned short cbd_sc
; /* Control and status info */
108 unsigned short cbd_datlen
; /* Data length */
109 unsigned long cbd_bufaddr
; /* Buffer address */
114 * The following definitions courtesy of commproc.h, which where
115 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
117 #define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
118 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
119 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
120 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
121 #define BD_SC_CM ((ushort)0x0200) /* Continous mode */
122 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
123 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */
124 #define BD_SC_BR ((ushort)0x0020) /* Break received */
125 #define BD_SC_FR ((ushort)0x0010) /* Framing error */
126 #define BD_SC_PR ((ushort)0x0008) /* Parity error */
127 #define BD_SC_OV ((ushort)0x0002) /* Overrun */
128 #define BD_SC_CD ((ushort)0x0001) /* ?? */
130 /* Buffer descriptor control/status used by Ethernet receive.
132 #define BD_ENET_RX_EMPTY ((ushort)0x8000)
133 #define BD_ENET_RX_WRAP ((ushort)0x2000)
134 #define BD_ENET_RX_INTR ((ushort)0x1000)
135 #define BD_ENET_RX_LAST ((ushort)0x0800)
136 #define BD_ENET_RX_FIRST ((ushort)0x0400)
137 #define BD_ENET_RX_MISS ((ushort)0x0100)
138 #define BD_ENET_RX_LG ((ushort)0x0020)
139 #define BD_ENET_RX_NO ((ushort)0x0010)
140 #define BD_ENET_RX_SH ((ushort)0x0008)
141 #define BD_ENET_RX_CR ((ushort)0x0004)
142 #define BD_ENET_RX_OV ((ushort)0x0002)
143 #define BD_ENET_RX_CL ((ushort)0x0001)
144 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
146 /* Buffer descriptor control/status used by Ethernet transmit.
148 #define BD_ENET_TX_READY ((ushort)0x8000)
149 #define BD_ENET_TX_PAD ((ushort)0x4000)
150 #define BD_ENET_TX_WRAP ((ushort)0x2000)
151 #define BD_ENET_TX_INTR ((ushort)0x1000)
152 #define BD_ENET_TX_LAST ((ushort)0x0800)
153 #define BD_ENET_TX_TC ((ushort)0x0400)
154 #define BD_ENET_TX_DEF ((ushort)0x0200)
155 #define BD_ENET_TX_HB ((ushort)0x0100)
156 #define BD_ENET_TX_LC ((ushort)0x0080)
157 #define BD_ENET_TX_RL ((ushort)0x0040)
158 #define BD_ENET_TX_RCMASK ((ushort)0x003c)
159 #define BD_ENET_TX_UN ((ushort)0x0002)
160 #define BD_ENET_TX_CSL ((ushort)0x0001)
161 #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
164 /****************************************************************************/
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