[PATCH] remove many unneeded #includes of sched.h
[deliverable/linux.git] / drivers / net / fs_enet / mii-bitbang.c
1 /*
2 * Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
3 *
4 * Copyright (c) 2003 Intracom S.A.
5 * by Pantelis Antoniou <panto@intracom.gr>
6 *
7 * 2005 (c) MontaVista Software, Inc.
8 * Vitaly Bordug <vbordug@ru.mvista.com>
9 *
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
13 */
14
15
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <linux/ptrace.h>
21 #include <linux/errno.h>
22 #include <linux/ioport.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/pci.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/skbuff.h>
31 #include <linux/spinlock.h>
32 #include <linux/mii.h>
33 #include <linux/ethtool.h>
34 #include <linux/bitops.h>
35 #include <linux/platform_device.h>
36
37 #include <asm/pgtable.h>
38 #include <asm/irq.h>
39 #include <asm/uaccess.h>
40
41 #include "fs_enet.h"
42
43 static int bitbang_prep_bit(u8 **datp, u8 *mskp,
44 struct fs_mii_bit *mii_bit)
45 {
46 void *dat;
47 int adv;
48 u8 msk;
49
50 dat = (void*) mii_bit->offset;
51
52 adv = mii_bit->bit >> 3;
53 dat = (char *)dat + adv;
54
55 msk = 1 << (7 - (mii_bit->bit & 7));
56
57 *datp = dat;
58 *mskp = msk;
59
60 return 0;
61 }
62
63 static inline void bb_set(u8 *p, u8 m)
64 {
65 out_8(p, in_8(p) | m);
66 }
67
68 static inline void bb_clr(u8 *p, u8 m)
69 {
70 out_8(p, in_8(p) & ~m);
71 }
72
73 static inline int bb_read(u8 *p, u8 m)
74 {
75 return (in_8(p) & m) != 0;
76 }
77
78 static inline void mdio_active(struct bb_info *bitbang)
79 {
80 bb_set(bitbang->mdio_dir, bitbang->mdio_dir_msk);
81 }
82
83 static inline void mdio_tristate(struct bb_info *bitbang )
84 {
85 bb_clr(bitbang->mdio_dir, bitbang->mdio_dir_msk);
86 }
87
88 static inline int mdio_read(struct bb_info *bitbang )
89 {
90 return bb_read(bitbang->mdio_dat, bitbang->mdio_dat_msk);
91 }
92
93 static inline void mdio(struct bb_info *bitbang , int what)
94 {
95 if (what)
96 bb_set(bitbang->mdio_dat, bitbang->mdio_dat_msk);
97 else
98 bb_clr(bitbang->mdio_dat, bitbang->mdio_dat_msk);
99 }
100
101 static inline void mdc(struct bb_info *bitbang , int what)
102 {
103 if (what)
104 bb_set(bitbang->mdc_dat, bitbang->mdc_msk);
105 else
106 bb_clr(bitbang->mdc_dat, bitbang->mdc_msk);
107 }
108
109 static inline void mii_delay(struct bb_info *bitbang )
110 {
111 udelay(bitbang->delay);
112 }
113
114 /* Utility to send the preamble, address, and register (common to read and write). */
115 static void bitbang_pre(struct bb_info *bitbang , int read, u8 addr, u8 reg)
116 {
117 int j;
118
119 /*
120 * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
121 * The IEEE spec says this is a PHY optional requirement. The AMD
122 * 79C874 requires one after power up and one after a MII communications
123 * error. This means that we are doing more preambles than we need,
124 * but it is safer and will be much more robust.
125 */
126
127 mdio_active(bitbang);
128 mdio(bitbang, 1);
129 for (j = 0; j < 32; j++) {
130 mdc(bitbang, 0);
131 mii_delay(bitbang);
132 mdc(bitbang, 1);
133 mii_delay(bitbang);
134 }
135
136 /* send the start bit (01) and the read opcode (10) or write (10) */
137 mdc(bitbang, 0);
138 mdio(bitbang, 0);
139 mii_delay(bitbang);
140 mdc(bitbang, 1);
141 mii_delay(bitbang);
142 mdc(bitbang, 0);
143 mdio(bitbang, 1);
144 mii_delay(bitbang);
145 mdc(bitbang, 1);
146 mii_delay(bitbang);
147 mdc(bitbang, 0);
148 mdio(bitbang, read);
149 mii_delay(bitbang);
150 mdc(bitbang, 1);
151 mii_delay(bitbang);
152 mdc(bitbang, 0);
153 mdio(bitbang, !read);
154 mii_delay(bitbang);
155 mdc(bitbang, 1);
156 mii_delay(bitbang);
157
158 /* send the PHY address */
159 for (j = 0; j < 5; j++) {
160 mdc(bitbang, 0);
161 mdio(bitbang, (addr & 0x10) != 0);
162 mii_delay(bitbang);
163 mdc(bitbang, 1);
164 mii_delay(bitbang);
165 addr <<= 1;
166 }
167
168 /* send the register address */
169 for (j = 0; j < 5; j++) {
170 mdc(bitbang, 0);
171 mdio(bitbang, (reg & 0x10) != 0);
172 mii_delay(bitbang);
173 mdc(bitbang, 1);
174 mii_delay(bitbang);
175 reg <<= 1;
176 }
177 }
178
179 static int fs_enet_mii_bb_read(struct mii_bus *bus , int phy_id, int location)
180 {
181 u16 rdreg;
182 int ret, j;
183 u8 addr = phy_id & 0xff;
184 u8 reg = location & 0xff;
185 struct bb_info* bitbang = bus->priv;
186
187 bitbang_pre(bitbang, 1, addr, reg);
188
189 /* tri-state our MDIO I/O pin so we can read */
190 mdc(bitbang, 0);
191 mdio_tristate(bitbang);
192 mii_delay(bitbang);
193 mdc(bitbang, 1);
194 mii_delay(bitbang);
195
196 /* check the turnaround bit: the PHY should be driving it to zero */
197 if (mdio_read(bitbang) != 0) {
198 /* PHY didn't drive TA low */
199 for (j = 0; j < 32; j++) {
200 mdc(bitbang, 0);
201 mii_delay(bitbang);
202 mdc(bitbang, 1);
203 mii_delay(bitbang);
204 }
205 ret = -1;
206 goto out;
207 }
208
209 mdc(bitbang, 0);
210 mii_delay(bitbang);
211
212 /* read 16 bits of register data, MSB first */
213 rdreg = 0;
214 for (j = 0; j < 16; j++) {
215 mdc(bitbang, 1);
216 mii_delay(bitbang);
217 rdreg <<= 1;
218 rdreg |= mdio_read(bitbang);
219 mdc(bitbang, 0);
220 mii_delay(bitbang);
221 }
222
223 mdc(bitbang, 1);
224 mii_delay(bitbang);
225 mdc(bitbang, 0);
226 mii_delay(bitbang);
227 mdc(bitbang, 1);
228 mii_delay(bitbang);
229
230 ret = rdreg;
231 out:
232 return ret;
233 }
234
235 static int fs_enet_mii_bb_write(struct mii_bus *bus, int phy_id, int location, u16 val)
236 {
237 int j;
238 struct bb_info* bitbang = bus->priv;
239
240 u8 addr = phy_id & 0xff;
241 u8 reg = location & 0xff;
242 u16 value = val & 0xffff;
243
244 bitbang_pre(bitbang, 0, addr, reg);
245
246 /* send the turnaround (10) */
247 mdc(bitbang, 0);
248 mdio(bitbang, 1);
249 mii_delay(bitbang);
250 mdc(bitbang, 1);
251 mii_delay(bitbang);
252 mdc(bitbang, 0);
253 mdio(bitbang, 0);
254 mii_delay(bitbang);
255 mdc(bitbang, 1);
256 mii_delay(bitbang);
257
258 /* write 16 bits of register data, MSB first */
259 for (j = 0; j < 16; j++) {
260 mdc(bitbang, 0);
261 mdio(bitbang, (value & 0x8000) != 0);
262 mii_delay(bitbang);
263 mdc(bitbang, 1);
264 mii_delay(bitbang);
265 value <<= 1;
266 }
267
268 /*
269 * Tri-state the MDIO line.
270 */
271 mdio_tristate(bitbang);
272 mdc(bitbang, 0);
273 mii_delay(bitbang);
274 mdc(bitbang, 1);
275 mii_delay(bitbang);
276 return 0;
277 }
278
279 static int fs_enet_mii_bb_reset(struct mii_bus *bus)
280 {
281 /*nothing here - dunno how to reset it*/
282 return 0;
283 }
284
285 static int fs_mii_bitbang_init(struct bb_info *bitbang, struct fs_mii_bb_platform_info* fmpi)
286 {
287 int r;
288
289 bitbang->delay = fmpi->delay;
290
291 r = bitbang_prep_bit(&bitbang->mdio_dir,
292 &bitbang->mdio_dir_msk,
293 &fmpi->mdio_dir);
294 if (r != 0)
295 return r;
296
297 r = bitbang_prep_bit(&bitbang->mdio_dat,
298 &bitbang->mdio_dat_msk,
299 &fmpi->mdio_dat);
300 if (r != 0)
301 return r;
302
303 r = bitbang_prep_bit(&bitbang->mdc_dat,
304 &bitbang->mdc_msk,
305 &fmpi->mdc_dat);
306 if (r != 0)
307 return r;
308
309 return 0;
310 }
311
312
313 static int __devinit fs_enet_mdio_probe(struct device *dev)
314 {
315 struct platform_device *pdev = to_platform_device(dev);
316 struct fs_mii_bb_platform_info *pdata;
317 struct mii_bus *new_bus;
318 struct bb_info *bitbang;
319 int err = 0;
320
321 if (NULL == dev)
322 return -EINVAL;
323
324 new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
325
326 if (NULL == new_bus)
327 return -ENOMEM;
328
329 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
330
331 if (NULL == bitbang)
332 return -ENOMEM;
333
334 new_bus->name = "BB MII Bus",
335 new_bus->read = &fs_enet_mii_bb_read,
336 new_bus->write = &fs_enet_mii_bb_write,
337 new_bus->reset = &fs_enet_mii_bb_reset,
338 new_bus->id = pdev->id;
339
340 new_bus->phy_mask = ~0x9;
341 pdata = (struct fs_mii_bb_platform_info *)pdev->dev.platform_data;
342
343 if (NULL == pdata) {
344 printk(KERN_ERR "gfar mdio %d: Missing platform data!\n", pdev->id);
345 return -ENODEV;
346 }
347
348 /*set up workspace*/
349 fs_mii_bitbang_init(bitbang, pdata);
350
351 new_bus->priv = bitbang;
352
353 new_bus->irq = pdata->irq;
354
355 new_bus->dev = dev;
356 dev_set_drvdata(dev, new_bus);
357
358 err = mdiobus_register(new_bus);
359
360 if (0 != err) {
361 printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
362 new_bus->name);
363 goto bus_register_fail;
364 }
365
366 return 0;
367
368 bus_register_fail:
369 kfree(bitbang);
370 kfree(new_bus);
371
372 return err;
373 }
374
375
376 static int fs_enet_mdio_remove(struct device *dev)
377 {
378 struct mii_bus *bus = dev_get_drvdata(dev);
379
380 mdiobus_unregister(bus);
381
382 dev_set_drvdata(dev, NULL);
383
384 iounmap((void *) (&bus->priv));
385 bus->priv = NULL;
386 kfree(bus);
387
388 return 0;
389 }
390
391 static struct device_driver fs_enet_bb_mdio_driver = {
392 .name = "fsl-bb-mdio",
393 .bus = &platform_bus_type,
394 .probe = fs_enet_mdio_probe,
395 .remove = fs_enet_mdio_remove,
396 };
397
398 int fs_enet_mdio_bb_init(void)
399 {
400 return driver_register(&fs_enet_bb_mdio_driver);
401 }
402
403 void fs_enet_mdio_bb_exit(void)
404 {
405 driver_unregister(&fs_enet_bb_mdio_driver);
406 }
407
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