2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
78 #include <linux/of_platform.h>
80 #include <linux/tcp.h>
81 #include <linux/udp.h>
86 #include <asm/uaccess.h>
87 #include <linux/module.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/crc32.h>
90 #include <linux/mii.h>
91 #include <linux/phy.h>
92 #include <linux/phy_fixed.h>
96 #include "fsl_pq_mdio.h"
98 #define TX_TIMEOUT (1*HZ)
99 #undef BRIEF_GFAR_ERRORS
100 #undef VERBOSE_GFAR_ERRORS
102 const char gfar_driver_name
[] = "Gianfar Ethernet";
103 const char gfar_driver_version
[] = "1.3";
105 static int gfar_enet_open(struct net_device
*dev
);
106 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
107 static void gfar_reset_task(struct work_struct
*work
);
108 static void gfar_timeout(struct net_device
*dev
);
109 static int gfar_close(struct net_device
*dev
);
110 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
111 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
112 struct sk_buff
*skb
);
113 static int gfar_set_mac_address(struct net_device
*dev
);
114 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
115 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
116 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
117 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
118 static void adjust_link(struct net_device
*dev
);
119 static void init_registers(struct net_device
*dev
);
120 static int init_phy(struct net_device
*dev
);
121 static int gfar_probe(struct of_device
*ofdev
,
122 const struct of_device_id
*match
);
123 static int gfar_remove(struct of_device
*ofdev
);
124 static void free_skb_resources(struct gfar_private
*priv
);
125 static void gfar_set_multi(struct net_device
*dev
);
126 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
127 static void gfar_configure_serdes(struct net_device
*dev
);
128 static int gfar_poll(struct napi_struct
*napi
, int budget
);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device
*dev
);
132 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
);
133 static int gfar_clean_tx_ring(struct net_device
*dev
);
134 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
136 static void gfar_vlan_rx_register(struct net_device
*netdev
,
137 struct vlan_group
*grp
);
138 void gfar_halt(struct net_device
*dev
);
139 static void gfar_halt_nodisable(struct net_device
*dev
);
140 void gfar_start(struct net_device
*dev
);
141 static void gfar_clear_exact_match(struct net_device
*dev
);
142 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
144 MODULE_AUTHOR("Freescale Semiconductor, Inc");
145 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
146 MODULE_LICENSE("GPL");
148 /* Returns 1 if incoming frames use an FCB */
149 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
151 return priv
->vlgrp
|| priv
->rx_csum_enable
;
154 static int gfar_of_init(struct net_device
*dev
)
156 struct device_node
*phy
, *mdio
;
157 const unsigned int *id
;
160 const void *mac_addr
;
164 struct gfar_private
*priv
= netdev_priv(dev
);
165 struct device_node
*np
= priv
->node
;
166 char bus_name
[MII_BUS_ID_SIZE
];
168 if (!np
|| !of_device_is_available(np
))
171 /* get a pointer to the register memory */
172 addr
= of_translate_address(np
, of_get_address(np
, 0, &size
, NULL
));
173 priv
->regs
= ioremap(addr
, size
);
175 if (priv
->regs
== NULL
)
178 priv
->interruptTransmit
= irq_of_parse_and_map(np
, 0);
180 model
= of_get_property(np
, "model", NULL
);
182 /* If we aren't the FEC we have multiple interrupts */
183 if (model
&& strcasecmp(model
, "FEC")) {
184 priv
->interruptReceive
= irq_of_parse_and_map(np
, 1);
186 priv
->interruptError
= irq_of_parse_and_map(np
, 2);
188 if (priv
->interruptTransmit
< 0 ||
189 priv
->interruptReceive
< 0 ||
190 priv
->interruptError
< 0) {
196 mac_addr
= of_get_mac_address(np
);
198 memcpy(dev
->dev_addr
, mac_addr
, MAC_ADDR_LEN
);
200 if (model
&& !strcasecmp(model
, "TSEC"))
202 FSL_GIANFAR_DEV_HAS_GIGABIT
|
203 FSL_GIANFAR_DEV_HAS_COALESCE
|
204 FSL_GIANFAR_DEV_HAS_RMON
|
205 FSL_GIANFAR_DEV_HAS_MULTI_INTR
;
206 if (model
&& !strcasecmp(model
, "eTSEC"))
208 FSL_GIANFAR_DEV_HAS_GIGABIT
|
209 FSL_GIANFAR_DEV_HAS_COALESCE
|
210 FSL_GIANFAR_DEV_HAS_RMON
|
211 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
212 FSL_GIANFAR_DEV_HAS_PADDING
|
213 FSL_GIANFAR_DEV_HAS_CSUM
|
214 FSL_GIANFAR_DEV_HAS_VLAN
|
215 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
|
216 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
;
218 ctype
= of_get_property(np
, "phy-connection-type", NULL
);
220 /* We only care about rgmii-id. The rest are autodetected */
221 if (ctype
&& !strcmp(ctype
, "rgmii-id"))
222 priv
->interface
= PHY_INTERFACE_MODE_RGMII_ID
;
224 priv
->interface
= PHY_INTERFACE_MODE_MII
;
226 if (of_get_property(np
, "fsl,magic-packet", NULL
))
227 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
;
229 ph
= of_get_property(np
, "phy-handle", NULL
);
233 fixed_link
= (u32
*)of_get_property(np
, "fixed-link", NULL
);
239 snprintf(priv
->phy_bus_id
, sizeof(priv
->phy_bus_id
),
240 PHY_ID_FMT
, "0", fixed_link
[0]);
242 phy
= of_find_node_by_phandle(*ph
);
249 mdio
= of_get_parent(phy
);
251 id
= of_get_property(phy
, "reg", NULL
);
256 fsl_pq_mdio_bus_name(bus_name
, mdio
);
257 snprintf(priv
->phy_bus_id
, sizeof(priv
->phy_bus_id
), "%s:%02x",
261 /* Find the TBI PHY. If it's not there, we don't support SGMII */
262 ph
= of_get_property(np
, "tbi-handle", NULL
);
264 struct device_node
*tbi
= of_find_node_by_phandle(*ph
);
265 struct of_device
*ofdev
;
271 mdio
= of_get_parent(tbi
);
275 ofdev
= of_find_device_by_node(mdio
);
279 id
= of_get_property(tbi
, "reg", NULL
);
285 bus
= dev_get_drvdata(&ofdev
->dev
);
287 priv
->tbiphy
= bus
->phy_map
[*id
];
297 /* Ioctl MII Interface */
298 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
300 struct gfar_private
*priv
= netdev_priv(dev
);
302 if (!netif_running(dev
))
308 return phy_mii_ioctl(priv
->phydev
, if_mii(rq
), cmd
);
311 /* Set up the ethernet device structure, private data,
312 * and anything else we need before we start */
313 static int gfar_probe(struct of_device
*ofdev
,
314 const struct of_device_id
*match
)
317 struct net_device
*dev
= NULL
;
318 struct gfar_private
*priv
= NULL
;
319 DECLARE_MAC_BUF(mac
);
323 /* Create an ethernet device instance */
324 dev
= alloc_etherdev(sizeof (*priv
));
329 priv
= netdev_priv(dev
);
331 priv
->node
= ofdev
->node
;
333 err
= gfar_of_init(dev
);
338 spin_lock_init(&priv
->txlock
);
339 spin_lock_init(&priv
->rxlock
);
340 spin_lock_init(&priv
->bflock
);
341 INIT_WORK(&priv
->reset_task
, gfar_reset_task
);
343 dev_set_drvdata(&ofdev
->dev
, priv
);
345 /* Stop the DMA engine now, in case it was running before */
346 /* (The firmware could have used it, and left it running). */
349 /* Reset MAC layer */
350 gfar_write(&priv
->regs
->maccfg1
, MACCFG1_SOFT_RESET
);
352 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
353 gfar_write(&priv
->regs
->maccfg1
, tempval
);
355 /* Initialize MACCFG2. */
356 gfar_write(&priv
->regs
->maccfg2
, MACCFG2_INIT_SETTINGS
);
358 /* Initialize ECNTRL */
359 gfar_write(&priv
->regs
->ecntrl
, ECNTRL_INIT_SETTINGS
);
361 /* Set the dev->base_addr to the gfar reg region */
362 dev
->base_addr
= (unsigned long) (priv
->regs
);
364 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
366 /* Fill in the dev structure */
367 dev
->open
= gfar_enet_open
;
368 dev
->hard_start_xmit
= gfar_start_xmit
;
369 dev
->tx_timeout
= gfar_timeout
;
370 dev
->watchdog_timeo
= TX_TIMEOUT
;
371 netif_napi_add(dev
, &priv
->napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
372 #ifdef CONFIG_NET_POLL_CONTROLLER
373 dev
->poll_controller
= gfar_netpoll
;
375 dev
->stop
= gfar_close
;
376 dev
->change_mtu
= gfar_change_mtu
;
378 dev
->set_multicast_list
= gfar_set_multi
;
380 dev
->ethtool_ops
= &gfar_ethtool_ops
;
381 dev
->do_ioctl
= gfar_ioctl
;
383 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
384 priv
->rx_csum_enable
= 1;
385 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_HIGHDMA
;
387 priv
->rx_csum_enable
= 0;
391 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
392 dev
->vlan_rx_register
= gfar_vlan_rx_register
;
394 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
397 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
398 priv
->extended_hash
= 1;
399 priv
->hash_width
= 9;
401 priv
->hash_regs
[0] = &priv
->regs
->igaddr0
;
402 priv
->hash_regs
[1] = &priv
->regs
->igaddr1
;
403 priv
->hash_regs
[2] = &priv
->regs
->igaddr2
;
404 priv
->hash_regs
[3] = &priv
->regs
->igaddr3
;
405 priv
->hash_regs
[4] = &priv
->regs
->igaddr4
;
406 priv
->hash_regs
[5] = &priv
->regs
->igaddr5
;
407 priv
->hash_regs
[6] = &priv
->regs
->igaddr6
;
408 priv
->hash_regs
[7] = &priv
->regs
->igaddr7
;
409 priv
->hash_regs
[8] = &priv
->regs
->gaddr0
;
410 priv
->hash_regs
[9] = &priv
->regs
->gaddr1
;
411 priv
->hash_regs
[10] = &priv
->regs
->gaddr2
;
412 priv
->hash_regs
[11] = &priv
->regs
->gaddr3
;
413 priv
->hash_regs
[12] = &priv
->regs
->gaddr4
;
414 priv
->hash_regs
[13] = &priv
->regs
->gaddr5
;
415 priv
->hash_regs
[14] = &priv
->regs
->gaddr6
;
416 priv
->hash_regs
[15] = &priv
->regs
->gaddr7
;
419 priv
->extended_hash
= 0;
420 priv
->hash_width
= 8;
422 priv
->hash_regs
[0] = &priv
->regs
->gaddr0
;
423 priv
->hash_regs
[1] = &priv
->regs
->gaddr1
;
424 priv
->hash_regs
[2] = &priv
->regs
->gaddr2
;
425 priv
->hash_regs
[3] = &priv
->regs
->gaddr3
;
426 priv
->hash_regs
[4] = &priv
->regs
->gaddr4
;
427 priv
->hash_regs
[5] = &priv
->regs
->gaddr5
;
428 priv
->hash_regs
[6] = &priv
->regs
->gaddr6
;
429 priv
->hash_regs
[7] = &priv
->regs
->gaddr7
;
432 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
433 priv
->padding
= DEFAULT_PADDING
;
437 if (dev
->features
& NETIF_F_IP_CSUM
)
438 dev
->hard_header_len
+= GMAC_FCB_LEN
;
440 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
441 priv
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
442 priv
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
443 priv
->num_txbdfree
= DEFAULT_TX_RING_SIZE
;
445 priv
->txcoalescing
= DEFAULT_TX_COALESCE
;
446 priv
->txic
= DEFAULT_TXIC
;
447 priv
->rxcoalescing
= DEFAULT_RX_COALESCE
;
448 priv
->rxic
= DEFAULT_RXIC
;
450 /* Enable most messages by default */
451 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
453 /* Carrier starts down, phylib will bring it up */
454 netif_carrier_off(dev
);
456 err
= register_netdev(dev
);
459 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
464 device_init_wakeup(&dev
->dev
,
465 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
467 /* fill out IRQ number and name fields */
468 len_devname
= strlen(dev
->name
);
469 strncpy(&priv
->int_name_tx
[0], dev
->name
, len_devname
);
470 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
471 strncpy(&priv
->int_name_tx
[len_devname
],
472 "_tx", sizeof("_tx") + 1);
474 strncpy(&priv
->int_name_rx
[0], dev
->name
, len_devname
);
475 strncpy(&priv
->int_name_rx
[len_devname
],
476 "_rx", sizeof("_rx") + 1);
478 strncpy(&priv
->int_name_er
[0], dev
->name
, len_devname
);
479 strncpy(&priv
->int_name_er
[len_devname
],
480 "_er", sizeof("_er") + 1);
482 priv
->int_name_tx
[len_devname
] = '\0';
484 /* Create all the sysfs files */
485 gfar_init_sysfs(dev
);
487 /* Print out the device info */
488 printk(KERN_INFO DEVICE_NAME
"%pM\n", dev
->name
, dev
->dev_addr
);
490 /* Even more device info helps when determining which kernel */
491 /* provided which set of benchmarks. */
492 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
493 printk(KERN_INFO
"%s: %d/%d RX/TX BD ring size\n",
494 dev
->name
, priv
->rx_ring_size
, priv
->tx_ring_size
);
505 static int gfar_remove(struct of_device
*ofdev
)
507 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
509 dev_set_drvdata(&ofdev
->dev
, NULL
);
512 free_netdev(priv
->dev
);
518 static int gfar_suspend(struct of_device
*ofdev
, pm_message_t state
)
520 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
521 struct net_device
*dev
= priv
->dev
;
525 int magic_packet
= priv
->wol_en
&&
526 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
528 netif_device_detach(dev
);
530 if (netif_running(dev
)) {
531 spin_lock_irqsave(&priv
->txlock
, flags
);
532 spin_lock(&priv
->rxlock
);
534 gfar_halt_nodisable(dev
);
536 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
537 tempval
= gfar_read(&priv
->regs
->maccfg1
);
539 tempval
&= ~MACCFG1_TX_EN
;
542 tempval
&= ~MACCFG1_RX_EN
;
544 gfar_write(&priv
->regs
->maccfg1
, tempval
);
546 spin_unlock(&priv
->rxlock
);
547 spin_unlock_irqrestore(&priv
->txlock
, flags
);
549 napi_disable(&priv
->napi
);
552 /* Enable interrupt on Magic Packet */
553 gfar_write(&priv
->regs
->imask
, IMASK_MAG
);
555 /* Enable Magic Packet mode */
556 tempval
= gfar_read(&priv
->regs
->maccfg2
);
557 tempval
|= MACCFG2_MPEN
;
558 gfar_write(&priv
->regs
->maccfg2
, tempval
);
560 phy_stop(priv
->phydev
);
567 static int gfar_resume(struct of_device
*ofdev
)
569 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
570 struct net_device
*dev
= priv
->dev
;
573 int magic_packet
= priv
->wol_en
&&
574 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
576 if (!netif_running(dev
)) {
577 netif_device_attach(dev
);
581 if (!magic_packet
&& priv
->phydev
)
582 phy_start(priv
->phydev
);
584 /* Disable Magic Packet mode, in case something
588 spin_lock_irqsave(&priv
->txlock
, flags
);
589 spin_lock(&priv
->rxlock
);
591 tempval
= gfar_read(&priv
->regs
->maccfg2
);
592 tempval
&= ~MACCFG2_MPEN
;
593 gfar_write(&priv
->regs
->maccfg2
, tempval
);
597 spin_unlock(&priv
->rxlock
);
598 spin_unlock_irqrestore(&priv
->txlock
, flags
);
600 netif_device_attach(dev
);
602 napi_enable(&priv
->napi
);
607 #define gfar_suspend NULL
608 #define gfar_resume NULL
611 /* Reads the controller's registers to determine what interface
612 * connects it to the PHY.
614 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
616 struct gfar_private
*priv
= netdev_priv(dev
);
617 u32 ecntrl
= gfar_read(&priv
->regs
->ecntrl
);
619 if (ecntrl
& ECNTRL_SGMII_MODE
)
620 return PHY_INTERFACE_MODE_SGMII
;
622 if (ecntrl
& ECNTRL_TBI_MODE
) {
623 if (ecntrl
& ECNTRL_REDUCED_MODE
)
624 return PHY_INTERFACE_MODE_RTBI
;
626 return PHY_INTERFACE_MODE_TBI
;
629 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
630 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
631 return PHY_INTERFACE_MODE_RMII
;
633 phy_interface_t interface
= priv
->interface
;
636 * This isn't autodetected right now, so it must
637 * be set by the device tree or platform code.
639 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
640 return PHY_INTERFACE_MODE_RGMII_ID
;
642 return PHY_INTERFACE_MODE_RGMII
;
646 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
647 return PHY_INTERFACE_MODE_GMII
;
649 return PHY_INTERFACE_MODE_MII
;
653 /* Initializes driver's PHY state, and attaches to the PHY.
654 * Returns 0 on success.
656 static int init_phy(struct net_device
*dev
)
658 struct gfar_private
*priv
= netdev_priv(dev
);
659 uint gigabit_support
=
660 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
661 SUPPORTED_1000baseT_Full
: 0;
662 struct phy_device
*phydev
;
663 phy_interface_t interface
;
667 priv
->oldduplex
= -1;
669 interface
= gfar_get_interface(dev
);
671 phydev
= phy_connect(dev
, priv
->phy_bus_id
, &adjust_link
, 0, interface
);
673 if (interface
== PHY_INTERFACE_MODE_SGMII
)
674 gfar_configure_serdes(dev
);
676 if (IS_ERR(phydev
)) {
677 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
678 return PTR_ERR(phydev
);
681 /* Remove any features not supported by the controller */
682 phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
683 phydev
->advertising
= phydev
->supported
;
685 priv
->phydev
= phydev
;
691 * Initialize TBI PHY interface for communicating with the
692 * SERDES lynx PHY on the chip. We communicate with this PHY
693 * through the MDIO bus on each controller, treating it as a
694 * "normal" PHY at the address found in the TBIPA register. We assume
695 * that the TBIPA register is valid. Either the MDIO bus code will set
696 * it to a value that doesn't conflict with other PHYs on the bus, or the
697 * value doesn't matter, as there are no other PHYs on the bus.
699 static void gfar_configure_serdes(struct net_device
*dev
)
701 struct gfar_private
*priv
= netdev_priv(dev
);
704 printk(KERN_WARNING
"SGMII mode requires that the device "
705 "tree specify a tbi-handle\n");
710 * If the link is already up, we must already be ok, and don't need to
711 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
712 * everything for us? Resetting it takes the link down and requires
713 * several seconds for it to come back.
715 if (phy_read(priv
->tbiphy
, MII_BMSR
) & BMSR_LSTATUS
)
718 /* Single clk mode, mii mode off(for serdes communication) */
719 phy_write(priv
->tbiphy
, MII_TBICON
, TBICON_CLK_SELECT
);
721 phy_write(priv
->tbiphy
, MII_ADVERTISE
,
722 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
723 ADVERTISE_1000XPSE_ASYM
);
725 phy_write(priv
->tbiphy
, MII_BMCR
, BMCR_ANENABLE
|
726 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
729 static void init_registers(struct net_device
*dev
)
731 struct gfar_private
*priv
= netdev_priv(dev
);
734 gfar_write(&priv
->regs
->ievent
, IEVENT_INIT_CLEAR
);
736 /* Initialize IMASK */
737 gfar_write(&priv
->regs
->imask
, IMASK_INIT_CLEAR
);
739 /* Init hash registers to zero */
740 gfar_write(&priv
->regs
->igaddr0
, 0);
741 gfar_write(&priv
->regs
->igaddr1
, 0);
742 gfar_write(&priv
->regs
->igaddr2
, 0);
743 gfar_write(&priv
->regs
->igaddr3
, 0);
744 gfar_write(&priv
->regs
->igaddr4
, 0);
745 gfar_write(&priv
->regs
->igaddr5
, 0);
746 gfar_write(&priv
->regs
->igaddr6
, 0);
747 gfar_write(&priv
->regs
->igaddr7
, 0);
749 gfar_write(&priv
->regs
->gaddr0
, 0);
750 gfar_write(&priv
->regs
->gaddr1
, 0);
751 gfar_write(&priv
->regs
->gaddr2
, 0);
752 gfar_write(&priv
->regs
->gaddr3
, 0);
753 gfar_write(&priv
->regs
->gaddr4
, 0);
754 gfar_write(&priv
->regs
->gaddr5
, 0);
755 gfar_write(&priv
->regs
->gaddr6
, 0);
756 gfar_write(&priv
->regs
->gaddr7
, 0);
758 /* Zero out the rmon mib registers if it has them */
759 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
760 memset_io(&(priv
->regs
->rmon
), 0, sizeof (struct rmon_mib
));
762 /* Mask off the CAM interrupts */
763 gfar_write(&priv
->regs
->rmon
.cam1
, 0xffffffff);
764 gfar_write(&priv
->regs
->rmon
.cam2
, 0xffffffff);
767 /* Initialize the max receive buffer length */
768 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
770 /* Initialize the Minimum Frame Length Register */
771 gfar_write(&priv
->regs
->minflr
, MINFLR_INIT_SETTINGS
);
775 /* Halt the receive and transmit queues */
776 static void gfar_halt_nodisable(struct net_device
*dev
)
778 struct gfar_private
*priv
= netdev_priv(dev
);
779 struct gfar __iomem
*regs
= priv
->regs
;
782 /* Mask all interrupts */
783 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
785 /* Clear all interrupts */
786 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
788 /* Stop the DMA, and wait for it to stop */
789 tempval
= gfar_read(&priv
->regs
->dmactrl
);
790 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
791 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
792 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
793 gfar_write(&priv
->regs
->dmactrl
, tempval
);
795 while (!(gfar_read(&priv
->regs
->ievent
) &
796 (IEVENT_GRSC
| IEVENT_GTSC
)))
801 /* Halt the receive and transmit queues */
802 void gfar_halt(struct net_device
*dev
)
804 struct gfar_private
*priv
= netdev_priv(dev
);
805 struct gfar __iomem
*regs
= priv
->regs
;
808 gfar_halt_nodisable(dev
);
810 /* Disable Rx and Tx */
811 tempval
= gfar_read(®s
->maccfg1
);
812 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
813 gfar_write(®s
->maccfg1
, tempval
);
816 void stop_gfar(struct net_device
*dev
)
818 struct gfar_private
*priv
= netdev_priv(dev
);
819 struct gfar __iomem
*regs
= priv
->regs
;
822 phy_stop(priv
->phydev
);
825 spin_lock_irqsave(&priv
->txlock
, flags
);
826 spin_lock(&priv
->rxlock
);
830 spin_unlock(&priv
->rxlock
);
831 spin_unlock_irqrestore(&priv
->txlock
, flags
);
834 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
835 free_irq(priv
->interruptError
, dev
);
836 free_irq(priv
->interruptTransmit
, dev
);
837 free_irq(priv
->interruptReceive
, dev
);
839 free_irq(priv
->interruptTransmit
, dev
);
842 free_skb_resources(priv
);
844 dma_free_coherent(&dev
->dev
,
845 sizeof(struct txbd8
)*priv
->tx_ring_size
846 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
848 gfar_read(®s
->tbase0
));
851 /* If there are any tx skbs or rx skbs still around, free them.
852 * Then free tx_skbuff and rx_skbuff */
853 static void free_skb_resources(struct gfar_private
*priv
)
859 /* Go through all the buffer descriptors and free their data buffers */
860 txbdp
= priv
->tx_bd_base
;
862 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
863 if (!priv
->tx_skbuff
[i
])
866 dma_unmap_single(&priv
->dev
->dev
, txbdp
->bufPtr
,
867 txbdp
->length
, DMA_TO_DEVICE
);
869 for (j
= 0; j
< skb_shinfo(priv
->tx_skbuff
[i
])->nr_frags
; j
++) {
871 dma_unmap_page(&priv
->dev
->dev
, txbdp
->bufPtr
,
872 txbdp
->length
, DMA_TO_DEVICE
);
875 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
876 priv
->tx_skbuff
[i
] = NULL
;
879 kfree(priv
->tx_skbuff
);
881 rxbdp
= priv
->rx_bd_base
;
883 /* rx_skbuff is not guaranteed to be allocated, so only
884 * free it and its contents if it is allocated */
885 if(priv
->rx_skbuff
!= NULL
) {
886 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
887 if (priv
->rx_skbuff
[i
]) {
888 dma_unmap_single(&priv
->dev
->dev
, rxbdp
->bufPtr
,
889 priv
->rx_buffer_size
,
892 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
893 priv
->rx_skbuff
[i
] = NULL
;
902 kfree(priv
->rx_skbuff
);
906 void gfar_start(struct net_device
*dev
)
908 struct gfar_private
*priv
= netdev_priv(dev
);
909 struct gfar __iomem
*regs
= priv
->regs
;
912 /* Enable Rx and Tx in MACCFG1 */
913 tempval
= gfar_read(®s
->maccfg1
);
914 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
915 gfar_write(®s
->maccfg1
, tempval
);
917 /* Initialize DMACTRL to have WWR and WOP */
918 tempval
= gfar_read(&priv
->regs
->dmactrl
);
919 tempval
|= DMACTRL_INIT_SETTINGS
;
920 gfar_write(&priv
->regs
->dmactrl
, tempval
);
922 /* Make sure we aren't stopped */
923 tempval
= gfar_read(&priv
->regs
->dmactrl
);
924 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
925 gfar_write(&priv
->regs
->dmactrl
, tempval
);
927 /* Clear THLT/RHLT, so that the DMA starts polling now */
928 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
);
929 gfar_write(®s
->rstat
, RSTAT_CLEAR_RHALT
);
931 /* Unmask the interrupts we look for */
932 gfar_write(®s
->imask
, IMASK_DEFAULT
);
934 dev
->trans_start
= jiffies
;
937 /* Bring the controller up and running */
938 int startup_gfar(struct net_device
*dev
)
945 struct gfar_private
*priv
= netdev_priv(dev
);
946 struct gfar __iomem
*regs
= priv
->regs
;
951 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
953 /* Allocate memory for the buffer descriptors */
954 vaddr
= (unsigned long) dma_alloc_coherent(&dev
->dev
,
955 sizeof (struct txbd8
) * priv
->tx_ring_size
+
956 sizeof (struct rxbd8
) * priv
->rx_ring_size
,
960 if (netif_msg_ifup(priv
))
961 printk(KERN_ERR
"%s: Could not allocate buffer descriptors!\n",
966 priv
->tx_bd_base
= (struct txbd8
*) vaddr
;
968 /* enet DMA only understands physical addresses */
969 gfar_write(®s
->tbase0
, addr
);
971 /* Start the rx descriptor ring where the tx ring leaves off */
972 addr
= addr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
973 vaddr
= vaddr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
974 priv
->rx_bd_base
= (struct rxbd8
*) vaddr
;
975 gfar_write(®s
->rbase0
, addr
);
977 /* Setup the skbuff rings */
979 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
980 priv
->tx_ring_size
, GFP_KERNEL
);
982 if (NULL
== priv
->tx_skbuff
) {
983 if (netif_msg_ifup(priv
))
984 printk(KERN_ERR
"%s: Could not allocate tx_skbuff\n",
990 for (i
= 0; i
< priv
->tx_ring_size
; i
++)
991 priv
->tx_skbuff
[i
] = NULL
;
994 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
995 priv
->rx_ring_size
, GFP_KERNEL
);
997 if (NULL
== priv
->rx_skbuff
) {
998 if (netif_msg_ifup(priv
))
999 printk(KERN_ERR
"%s: Could not allocate rx_skbuff\n",
1005 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
1006 priv
->rx_skbuff
[i
] = NULL
;
1008 /* Initialize some variables in our dev structure */
1009 priv
->num_txbdfree
= priv
->tx_ring_size
;
1010 priv
->dirty_tx
= priv
->cur_tx
= priv
->tx_bd_base
;
1011 priv
->cur_rx
= priv
->rx_bd_base
;
1012 priv
->skb_curtx
= priv
->skb_dirtytx
= 0;
1013 priv
->skb_currx
= 0;
1015 /* Initialize Transmit Descriptor Ring */
1016 txbdp
= priv
->tx_bd_base
;
1017 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
1023 /* Set the last descriptor in the ring to indicate wrap */
1025 txbdp
->status
|= TXBD_WRAP
;
1027 rxbdp
= priv
->rx_bd_base
;
1028 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
1029 struct sk_buff
*skb
;
1031 skb
= gfar_new_skb(dev
);
1034 printk(KERN_ERR
"%s: Can't allocate RX buffers\n",
1037 goto err_rxalloc_fail
;
1040 priv
->rx_skbuff
[i
] = skb
;
1042 gfar_new_rxbdp(dev
, rxbdp
, skb
);
1047 /* Set the last descriptor in the ring to wrap */
1049 rxbdp
->status
|= RXBD_WRAP
;
1051 /* If the device has multiple interrupts, register for
1052 * them. Otherwise, only register for the one */
1053 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1054 /* Install our interrupt handlers for Error,
1055 * Transmit, and Receive */
1056 if (request_irq(priv
->interruptError
, gfar_error
,
1057 0, priv
->int_name_er
, dev
) < 0) {
1058 if (netif_msg_intr(priv
))
1059 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1060 dev
->name
, priv
->interruptError
);
1066 if (request_irq(priv
->interruptTransmit
, gfar_transmit
,
1067 0, priv
->int_name_tx
, dev
) < 0) {
1068 if (netif_msg_intr(priv
))
1069 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1070 dev
->name
, priv
->interruptTransmit
);
1077 if (request_irq(priv
->interruptReceive
, gfar_receive
,
1078 0, priv
->int_name_rx
, dev
) < 0) {
1079 if (netif_msg_intr(priv
))
1080 printk(KERN_ERR
"%s: Can't get IRQ %d (receive0)\n",
1081 dev
->name
, priv
->interruptReceive
);
1087 if (request_irq(priv
->interruptTransmit
, gfar_interrupt
,
1088 0, priv
->int_name_tx
, dev
) < 0) {
1089 if (netif_msg_intr(priv
))
1090 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1091 dev
->name
, priv
->interruptTransmit
);
1098 phy_start(priv
->phydev
);
1100 /* Configure the coalescing support */
1101 gfar_write(®s
->txic
, 0);
1102 if (priv
->txcoalescing
)
1103 gfar_write(®s
->txic
, priv
->txic
);
1105 gfar_write(®s
->rxic
, 0);
1106 if (priv
->rxcoalescing
)
1107 gfar_write(®s
->rxic
, priv
->rxic
);
1109 if (priv
->rx_csum_enable
)
1110 rctrl
|= RCTRL_CHECKSUMMING
;
1112 if (priv
->extended_hash
) {
1113 rctrl
|= RCTRL_EXTHASH
;
1115 gfar_clear_exact_match(dev
);
1116 rctrl
|= RCTRL_EMEN
;
1119 if (priv
->padding
) {
1120 rctrl
&= ~RCTRL_PAL_MASK
;
1121 rctrl
|= RCTRL_PADDING(priv
->padding
);
1124 /* Init rctrl based on our settings */
1125 gfar_write(&priv
->regs
->rctrl
, rctrl
);
1127 if (dev
->features
& NETIF_F_IP_CSUM
)
1128 gfar_write(&priv
->regs
->tctrl
, TCTRL_INIT_CSUM
);
1130 /* Set the extraction length and index */
1131 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
1132 ATTRELI_EI(priv
->rx_stash_index
);
1134 gfar_write(&priv
->regs
->attreli
, attrs
);
1136 /* Start with defaults, and add stashing or locking
1137 * depending on the approprate variables */
1138 attrs
= ATTR_INIT_SETTINGS
;
1140 if (priv
->bd_stash_en
)
1141 attrs
|= ATTR_BDSTASH
;
1143 if (priv
->rx_stash_size
!= 0)
1144 attrs
|= ATTR_BUFSTASH
;
1146 gfar_write(&priv
->regs
->attr
, attrs
);
1148 gfar_write(&priv
->regs
->fifo_tx_thr
, priv
->fifo_threshold
);
1149 gfar_write(&priv
->regs
->fifo_tx_starve
, priv
->fifo_starve
);
1150 gfar_write(&priv
->regs
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
1152 /* Start the controller */
1158 free_irq(priv
->interruptTransmit
, dev
);
1160 free_irq(priv
->interruptError
, dev
);
1164 free_skb_resources(priv
);
1166 dma_free_coherent(&dev
->dev
,
1167 sizeof(struct txbd8
)*priv
->tx_ring_size
1168 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
1170 gfar_read(®s
->tbase0
));
1175 /* Called when something needs to use the ethernet device */
1176 /* Returns 0 for success. */
1177 static int gfar_enet_open(struct net_device
*dev
)
1179 struct gfar_private
*priv
= netdev_priv(dev
);
1182 napi_enable(&priv
->napi
);
1184 skb_queue_head_init(&priv
->rx_recycle
);
1186 /* Initialize a bunch of registers */
1187 init_registers(dev
);
1189 gfar_set_mac_address(dev
);
1191 err
= init_phy(dev
);
1194 napi_disable(&priv
->napi
);
1198 err
= startup_gfar(dev
);
1200 napi_disable(&priv
->napi
);
1204 netif_start_queue(dev
);
1206 device_set_wakeup_enable(&dev
->dev
, priv
->wol_en
);
1211 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
)
1213 struct txfcb
*fcb
= (struct txfcb
*)skb_push (skb
, GMAC_FCB_LEN
);
1215 cacheable_memzero(fcb
, GMAC_FCB_LEN
);
1220 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
1224 /* If we're here, it's a IP packet with a TCP or UDP
1225 * payload. We set it to checksum, using a pseudo-header
1228 flags
= TXFCB_DEFAULT
;
1230 /* Tell the controller what the protocol is */
1231 /* And provide the already calculated phcs */
1232 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
1234 fcb
->phcs
= udp_hdr(skb
)->check
;
1236 fcb
->phcs
= tcp_hdr(skb
)->check
;
1238 /* l3os is the distance between the start of the
1239 * frame (skb->data) and the start of the IP hdr.
1240 * l4os is the distance between the start of the
1241 * l3 hdr and the l4 hdr */
1242 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
1243 fcb
->l4os
= skb_network_header_len(skb
);
1248 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
1250 fcb
->flags
|= TXFCB_VLN
;
1251 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1254 static inline struct txbd8
*skip_txbd(struct txbd8
*bdp
, int stride
,
1255 struct txbd8
*base
, int ring_size
)
1257 struct txbd8
*new_bd
= bdp
+ stride
;
1259 return (new_bd
>= (base
+ ring_size
)) ? (new_bd
- ring_size
) : new_bd
;
1262 static inline struct txbd8
*next_txbd(struct txbd8
*bdp
, struct txbd8
*base
,
1265 return skip_txbd(bdp
, 1, base
, ring_size
);
1268 /* This is called by the kernel when a frame is ready for transmission. */
1269 /* It is pointed to by the dev->hard_start_xmit function pointer */
1270 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1272 struct gfar_private
*priv
= netdev_priv(dev
);
1273 struct txfcb
*fcb
= NULL
;
1274 struct txbd8
*txbdp
, *txbdp_start
, *base
;
1278 unsigned long flags
;
1279 unsigned int nr_frags
, length
;
1281 base
= priv
->tx_bd_base
;
1283 /* total number of fragments in the SKB */
1284 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1286 spin_lock_irqsave(&priv
->txlock
, flags
);
1288 /* check if there is space to queue this packet */
1289 if (nr_frags
> priv
->num_txbdfree
) {
1290 /* no space, stop the queue */
1291 netif_stop_queue(dev
);
1292 dev
->stats
.tx_fifo_errors
++;
1293 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1294 return NETDEV_TX_BUSY
;
1297 /* Update transmit stats */
1298 dev
->stats
.tx_bytes
+= skb
->len
;
1300 txbdp
= txbdp_start
= priv
->cur_tx
;
1302 if (nr_frags
== 0) {
1303 lstatus
= txbdp
->lstatus
| BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
1305 /* Place the fragment addresses and lengths into the TxBDs */
1306 for (i
= 0; i
< nr_frags
; i
++) {
1307 /* Point at the next BD, wrapping as needed */
1308 txbdp
= next_txbd(txbdp
, base
, priv
->tx_ring_size
);
1310 length
= skb_shinfo(skb
)->frags
[i
].size
;
1312 lstatus
= txbdp
->lstatus
| length
|
1313 BD_LFLAG(TXBD_READY
);
1315 /* Handle the last BD specially */
1316 if (i
== nr_frags
- 1)
1317 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
1319 bufaddr
= dma_map_page(&dev
->dev
,
1320 skb_shinfo(skb
)->frags
[i
].page
,
1321 skb_shinfo(skb
)->frags
[i
].page_offset
,
1325 /* set the TxBD length and buffer pointer */
1326 txbdp
->bufPtr
= bufaddr
;
1327 txbdp
->lstatus
= lstatus
;
1330 lstatus
= txbdp_start
->lstatus
;
1333 /* Set up checksumming */
1334 if (CHECKSUM_PARTIAL
== skb
->ip_summed
) {
1335 fcb
= gfar_add_fcb(skb
);
1336 lstatus
|= BD_LFLAG(TXBD_TOE
);
1337 gfar_tx_checksum(skb
, fcb
);
1340 if (priv
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1341 if (unlikely(NULL
== fcb
)) {
1342 fcb
= gfar_add_fcb(skb
);
1343 lstatus
|= BD_LFLAG(TXBD_TOE
);
1346 gfar_tx_vlan(skb
, fcb
);
1349 /* setup the TxBD length and buffer pointer for the first BD */
1350 priv
->tx_skbuff
[priv
->skb_curtx
] = skb
;
1351 txbdp_start
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1352 skb_headlen(skb
), DMA_TO_DEVICE
);
1354 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | skb_headlen(skb
);
1357 * The powerpc-specific eieio() is used, as wmb() has too strong
1358 * semantics (it requires synchronization between cacheable and
1359 * uncacheable mappings, which eieio doesn't provide and which we
1360 * don't need), thus requiring a more expensive sync instruction. At
1361 * some point, the set of architecture-independent barrier functions
1362 * should be expanded to include weaker barriers.
1366 txbdp_start
->lstatus
= lstatus
;
1368 /* Update the current skb pointer to the next entry we will use
1369 * (wrapping if necessary) */
1370 priv
->skb_curtx
= (priv
->skb_curtx
+ 1) &
1371 TX_RING_MOD_MASK(priv
->tx_ring_size
);
1373 priv
->cur_tx
= next_txbd(txbdp
, base
, priv
->tx_ring_size
);
1375 /* reduce TxBD free count */
1376 priv
->num_txbdfree
-= (nr_frags
+ 1);
1378 dev
->trans_start
= jiffies
;
1380 /* If the next BD still needs to be cleaned up, then the bds
1381 are full. We need to tell the kernel to stop sending us stuff. */
1382 if (!priv
->num_txbdfree
) {
1383 netif_stop_queue(dev
);
1385 dev
->stats
.tx_fifo_errors
++;
1388 /* Tell the DMA to go go go */
1389 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1392 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1397 /* Stops the kernel queue, and halts the controller */
1398 static int gfar_close(struct net_device
*dev
)
1400 struct gfar_private
*priv
= netdev_priv(dev
);
1402 napi_disable(&priv
->napi
);
1404 skb_queue_purge(&priv
->rx_recycle
);
1405 cancel_work_sync(&priv
->reset_task
);
1408 /* Disconnect from the PHY */
1409 phy_disconnect(priv
->phydev
);
1410 priv
->phydev
= NULL
;
1412 netif_stop_queue(dev
);
1417 /* Changes the mac address if the controller is not running. */
1418 static int gfar_set_mac_address(struct net_device
*dev
)
1420 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
1426 /* Enables and disables VLAN insertion/extraction */
1427 static void gfar_vlan_rx_register(struct net_device
*dev
,
1428 struct vlan_group
*grp
)
1430 struct gfar_private
*priv
= netdev_priv(dev
);
1431 unsigned long flags
;
1434 spin_lock_irqsave(&priv
->rxlock
, flags
);
1439 /* Enable VLAN tag insertion */
1440 tempval
= gfar_read(&priv
->regs
->tctrl
);
1441 tempval
|= TCTRL_VLINS
;
1443 gfar_write(&priv
->regs
->tctrl
, tempval
);
1445 /* Enable VLAN tag extraction */
1446 tempval
= gfar_read(&priv
->regs
->rctrl
);
1447 tempval
|= RCTRL_VLEX
;
1448 tempval
|= (RCTRL_VLEX
| RCTRL_PRSDEP_INIT
);
1449 gfar_write(&priv
->regs
->rctrl
, tempval
);
1451 /* Disable VLAN tag insertion */
1452 tempval
= gfar_read(&priv
->regs
->tctrl
);
1453 tempval
&= ~TCTRL_VLINS
;
1454 gfar_write(&priv
->regs
->tctrl
, tempval
);
1456 /* Disable VLAN tag extraction */
1457 tempval
= gfar_read(&priv
->regs
->rctrl
);
1458 tempval
&= ~RCTRL_VLEX
;
1459 /* If parse is no longer required, then disable parser */
1460 if (tempval
& RCTRL_REQ_PARSER
)
1461 tempval
|= RCTRL_PRSDEP_INIT
;
1463 tempval
&= ~RCTRL_PRSDEP_INIT
;
1464 gfar_write(&priv
->regs
->rctrl
, tempval
);
1467 gfar_change_mtu(dev
, dev
->mtu
);
1469 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1472 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
1474 int tempsize
, tempval
;
1475 struct gfar_private
*priv
= netdev_priv(dev
);
1476 int oldsize
= priv
->rx_buffer_size
;
1477 int frame_size
= new_mtu
+ ETH_HLEN
;
1480 frame_size
+= VLAN_HLEN
;
1482 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
1483 if (netif_msg_drv(priv
))
1484 printk(KERN_ERR
"%s: Invalid MTU setting\n",
1489 if (gfar_uses_fcb(priv
))
1490 frame_size
+= GMAC_FCB_LEN
;
1492 frame_size
+= priv
->padding
;
1495 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
1496 INCREMENTAL_BUFFER_SIZE
;
1498 /* Only stop and start the controller if it isn't already
1499 * stopped, and we changed something */
1500 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1503 priv
->rx_buffer_size
= tempsize
;
1507 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
1508 gfar_write(&priv
->regs
->maxfrm
, priv
->rx_buffer_size
);
1510 /* If the mtu is larger than the max size for standard
1511 * ethernet frames (ie, a jumbo frame), then set maccfg2
1512 * to allow huge frames, and to check the length */
1513 tempval
= gfar_read(&priv
->regs
->maccfg2
);
1515 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
1516 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1518 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1520 gfar_write(&priv
->regs
->maccfg2
, tempval
);
1522 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1528 /* gfar_reset_task gets scheduled when a packet has not been
1529 * transmitted after a set amount of time.
1530 * For now, assume that clearing out all the structures, and
1531 * starting over will fix the problem.
1533 static void gfar_reset_task(struct work_struct
*work
)
1535 struct gfar_private
*priv
= container_of(work
, struct gfar_private
,
1537 struct net_device
*dev
= priv
->dev
;
1539 if (dev
->flags
& IFF_UP
) {
1544 netif_tx_schedule_all(dev
);
1547 static void gfar_timeout(struct net_device
*dev
)
1549 struct gfar_private
*priv
= netdev_priv(dev
);
1551 dev
->stats
.tx_errors
++;
1552 schedule_work(&priv
->reset_task
);
1555 /* Interrupt Handler for Transmit complete */
1556 static int gfar_clean_tx_ring(struct net_device
*dev
)
1558 struct gfar_private
*priv
= netdev_priv(dev
);
1560 struct txbd8
*lbdp
= NULL
;
1561 struct txbd8
*base
= priv
->tx_bd_base
;
1562 struct sk_buff
*skb
;
1564 int tx_ring_size
= priv
->tx_ring_size
;
1570 bdp
= priv
->dirty_tx
;
1571 skb_dirtytx
= priv
->skb_dirtytx
;
1573 while ((skb
= priv
->tx_skbuff
[skb_dirtytx
])) {
1574 frags
= skb_shinfo(skb
)->nr_frags
;
1575 lbdp
= skip_txbd(bdp
, frags
, base
, tx_ring_size
);
1577 lstatus
= lbdp
->lstatus
;
1579 /* Only clean completed frames */
1580 if ((lstatus
& BD_LFLAG(TXBD_READY
)) &&
1581 (lstatus
& BD_LENGTH_MASK
))
1584 dma_unmap_single(&dev
->dev
,
1589 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
1590 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
1592 for (i
= 0; i
< frags
; i
++) {
1593 dma_unmap_page(&dev
->dev
,
1597 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
1598 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
1602 * If there's room in the queue (limit it to rx_buffer_size)
1603 * we add this skb back into the pool, if it's the right size
1605 if (skb_queue_len(&priv
->rx_recycle
) < priv
->rx_ring_size
&&
1606 skb_recycle_check(skb
, priv
->rx_buffer_size
+
1608 __skb_queue_head(&priv
->rx_recycle
, skb
);
1610 dev_kfree_skb_any(skb
);
1612 priv
->tx_skbuff
[skb_dirtytx
] = NULL
;
1614 skb_dirtytx
= (skb_dirtytx
+ 1) &
1615 TX_RING_MOD_MASK(tx_ring_size
);
1618 priv
->num_txbdfree
+= frags
+ 1;
1621 /* If we freed a buffer, we can restart transmission, if necessary */
1622 if (netif_queue_stopped(dev
) && priv
->num_txbdfree
)
1623 netif_wake_queue(dev
);
1625 /* Update dirty indicators */
1626 priv
->skb_dirtytx
= skb_dirtytx
;
1627 priv
->dirty_tx
= bdp
;
1629 dev
->stats
.tx_packets
+= howmany
;
1634 static void gfar_schedule_cleanup(struct net_device
*dev
)
1636 struct gfar_private
*priv
= netdev_priv(dev
);
1637 unsigned long flags
;
1639 spin_lock_irqsave(&priv
->txlock
, flags
);
1640 spin_lock(&priv
->rxlock
);
1642 if (napi_schedule_prep(&priv
->napi
)) {
1643 gfar_write(&priv
->regs
->imask
, IMASK_RTX_DISABLED
);
1644 __napi_schedule(&priv
->napi
);
1647 spin_unlock(&priv
->rxlock
);
1648 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1651 /* Interrupt Handler for Transmit complete */
1652 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
)
1654 gfar_schedule_cleanup((struct net_device
*)dev_id
);
1658 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
1659 struct sk_buff
*skb
)
1661 struct gfar_private
*priv
= netdev_priv(dev
);
1664 bdp
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1665 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1667 lstatus
= BD_LFLAG(RXBD_EMPTY
| RXBD_INTERRUPT
);
1669 if (bdp
== priv
->rx_bd_base
+ priv
->rx_ring_size
- 1)
1670 lstatus
|= BD_LFLAG(RXBD_WRAP
);
1674 bdp
->lstatus
= lstatus
;
1678 struct sk_buff
* gfar_new_skb(struct net_device
*dev
)
1680 unsigned int alignamount
;
1681 struct gfar_private
*priv
= netdev_priv(dev
);
1682 struct sk_buff
*skb
= NULL
;
1684 skb
= __skb_dequeue(&priv
->rx_recycle
);
1686 skb
= netdev_alloc_skb(dev
,
1687 priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
1692 alignamount
= RXBUF_ALIGNMENT
-
1693 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
1695 /* We need the data buffer to be aligned properly. We will reserve
1696 * as many bytes as needed to align the data properly
1698 skb_reserve(skb
, alignamount
);
1703 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
1705 struct gfar_private
*priv
= netdev_priv(dev
);
1706 struct net_device_stats
*stats
= &dev
->stats
;
1707 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
1709 /* If the packet was truncated, none of the other errors
1711 if (status
& RXBD_TRUNCATED
) {
1712 stats
->rx_length_errors
++;
1718 /* Count the errors, if there were any */
1719 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
1720 stats
->rx_length_errors
++;
1722 if (status
& RXBD_LARGE
)
1727 if (status
& RXBD_NONOCTET
) {
1728 stats
->rx_frame_errors
++;
1729 estats
->rx_nonoctet
++;
1731 if (status
& RXBD_CRCERR
) {
1732 estats
->rx_crcerr
++;
1733 stats
->rx_crc_errors
++;
1735 if (status
& RXBD_OVERRUN
) {
1736 estats
->rx_overrun
++;
1737 stats
->rx_crc_errors
++;
1741 irqreturn_t
gfar_receive(int irq
, void *dev_id
)
1743 gfar_schedule_cleanup((struct net_device
*)dev_id
);
1747 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
1749 /* If valid headers were found, and valid sums
1750 * were verified, then we tell the kernel that no
1751 * checksumming is necessary. Otherwise, it is */
1752 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
1753 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1755 skb
->ip_summed
= CHECKSUM_NONE
;
1759 /* gfar_process_frame() -- handle one incoming packet if skb
1761 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
1764 struct gfar_private
*priv
= netdev_priv(dev
);
1765 struct rxfcb
*fcb
= NULL
;
1769 /* fcb is at the beginning if exists */
1770 fcb
= (struct rxfcb
*)skb
->data
;
1772 /* Remove the FCB from the skb */
1773 /* Remove the padded bytes, if there are any */
1775 skb_pull(skb
, amount_pull
);
1777 if (priv
->rx_csum_enable
)
1778 gfar_rx_checksum(skb
, fcb
);
1780 /* Tell the skb what kind of packet this is */
1781 skb
->protocol
= eth_type_trans(skb
, dev
);
1783 /* Send the packet up the stack */
1784 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
)))
1785 ret
= vlan_hwaccel_receive_skb(skb
, priv
->vlgrp
, fcb
->vlctl
);
1787 ret
= netif_receive_skb(skb
);
1789 if (NET_RX_DROP
== ret
)
1790 priv
->extra_stats
.kernel_dropped
++;
1795 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1796 * until the budget/quota has been reached. Returns the number
1799 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
)
1801 struct rxbd8
*bdp
, *base
;
1802 struct sk_buff
*skb
;
1806 struct gfar_private
*priv
= netdev_priv(dev
);
1808 /* Get the first full descriptor */
1810 base
= priv
->rx_bd_base
;
1812 amount_pull
= (gfar_uses_fcb(priv
) ? GMAC_FCB_LEN
: 0) +
1815 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
1816 struct sk_buff
*newskb
;
1819 /* Add another skb for the future */
1820 newskb
= gfar_new_skb(dev
);
1822 skb
= priv
->rx_skbuff
[priv
->skb_currx
];
1824 dma_unmap_single(&priv
->dev
->dev
, bdp
->bufPtr
,
1825 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1827 /* We drop the frame if we failed to allocate a new buffer */
1828 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
1829 bdp
->status
& RXBD_ERR
)) {
1830 count_errors(bdp
->status
, dev
);
1832 if (unlikely(!newskb
))
1835 __skb_queue_head(&priv
->rx_recycle
, skb
);
1837 /* Increment the number of packets */
1838 dev
->stats
.rx_packets
++;
1842 pkt_len
= bdp
->length
- ETH_FCS_LEN
;
1843 /* Remove the FCS from the packet length */
1844 skb_put(skb
, pkt_len
);
1845 dev
->stats
.rx_bytes
+= pkt_len
;
1847 if (in_irq() || irqs_disabled())
1848 printk("Interrupt problem!\n");
1849 gfar_process_frame(dev
, skb
, amount_pull
);
1852 if (netif_msg_rx_err(priv
))
1854 "%s: Missing skb!\n", dev
->name
);
1855 dev
->stats
.rx_dropped
++;
1856 priv
->extra_stats
.rx_skbmissing
++;
1861 priv
->rx_skbuff
[priv
->skb_currx
] = newskb
;
1863 /* Setup the new bdp */
1864 gfar_new_rxbdp(dev
, bdp
, newskb
);
1866 /* Update to the next pointer */
1867 bdp
= next_bd(bdp
, base
, priv
->rx_ring_size
);
1869 /* update to point at the next skb */
1871 (priv
->skb_currx
+ 1) &
1872 RX_RING_MOD_MASK(priv
->rx_ring_size
);
1875 /* Update the current rxbd pointer to be the next one */
1881 static int gfar_poll(struct napi_struct
*napi
, int budget
)
1883 struct gfar_private
*priv
= container_of(napi
, struct gfar_private
, napi
);
1884 struct net_device
*dev
= priv
->dev
;
1887 unsigned long flags
;
1889 /* Clear IEVENT, so interrupts aren't called again
1890 * because of the packets that have already arrived */
1891 gfar_write(&priv
->regs
->ievent
, IEVENT_RTX_MASK
);
1893 /* If we fail to get the lock, don't bother with the TX BDs */
1894 if (spin_trylock_irqsave(&priv
->txlock
, flags
)) {
1895 tx_cleaned
= gfar_clean_tx_ring(dev
);
1896 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1899 rx_cleaned
= gfar_clean_rx_ring(dev
, budget
);
1904 if (rx_cleaned
< budget
) {
1905 napi_complete(napi
);
1907 /* Clear the halt bit in RSTAT */
1908 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1910 gfar_write(&priv
->regs
->imask
, IMASK_DEFAULT
);
1912 /* If we are coalescing interrupts, update the timer */
1913 /* Otherwise, clear it */
1914 if (likely(priv
->rxcoalescing
)) {
1915 gfar_write(&priv
->regs
->rxic
, 0);
1916 gfar_write(&priv
->regs
->rxic
, priv
->rxic
);
1918 if (likely(priv
->txcoalescing
)) {
1919 gfar_write(&priv
->regs
->txic
, 0);
1920 gfar_write(&priv
->regs
->txic
, priv
->txic
);
1927 #ifdef CONFIG_NET_POLL_CONTROLLER
1929 * Polling 'interrupt' - used by things like netconsole to send skbs
1930 * without having to re-enable interrupts. It's not called while
1931 * the interrupt routine is executing.
1933 static void gfar_netpoll(struct net_device
*dev
)
1935 struct gfar_private
*priv
= netdev_priv(dev
);
1937 /* If the device has multiple interrupts, run tx/rx */
1938 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1939 disable_irq(priv
->interruptTransmit
);
1940 disable_irq(priv
->interruptReceive
);
1941 disable_irq(priv
->interruptError
);
1942 gfar_interrupt(priv
->interruptTransmit
, dev
);
1943 enable_irq(priv
->interruptError
);
1944 enable_irq(priv
->interruptReceive
);
1945 enable_irq(priv
->interruptTransmit
);
1947 disable_irq(priv
->interruptTransmit
);
1948 gfar_interrupt(priv
->interruptTransmit
, dev
);
1949 enable_irq(priv
->interruptTransmit
);
1954 /* The interrupt handler for devices with one interrupt */
1955 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
)
1957 struct net_device
*dev
= dev_id
;
1958 struct gfar_private
*priv
= netdev_priv(dev
);
1960 /* Save ievent for future reference */
1961 u32 events
= gfar_read(&priv
->regs
->ievent
);
1963 /* Check for reception */
1964 if (events
& IEVENT_RX_MASK
)
1965 gfar_receive(irq
, dev_id
);
1967 /* Check for transmit completion */
1968 if (events
& IEVENT_TX_MASK
)
1969 gfar_transmit(irq
, dev_id
);
1971 /* Check for errors */
1972 if (events
& IEVENT_ERR_MASK
)
1973 gfar_error(irq
, dev_id
);
1978 /* Called every time the controller might need to be made
1979 * aware of new link state. The PHY code conveys this
1980 * information through variables in the phydev structure, and this
1981 * function converts those variables into the appropriate
1982 * register values, and can bring down the device if needed.
1984 static void adjust_link(struct net_device
*dev
)
1986 struct gfar_private
*priv
= netdev_priv(dev
);
1987 struct gfar __iomem
*regs
= priv
->regs
;
1988 unsigned long flags
;
1989 struct phy_device
*phydev
= priv
->phydev
;
1992 spin_lock_irqsave(&priv
->txlock
, flags
);
1994 u32 tempval
= gfar_read(®s
->maccfg2
);
1995 u32 ecntrl
= gfar_read(®s
->ecntrl
);
1997 /* Now we make sure that we can be in full duplex mode.
1998 * If not, we operate in half-duplex mode. */
1999 if (phydev
->duplex
!= priv
->oldduplex
) {
2001 if (!(phydev
->duplex
))
2002 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
2004 tempval
|= MACCFG2_FULL_DUPLEX
;
2006 priv
->oldduplex
= phydev
->duplex
;
2009 if (phydev
->speed
!= priv
->oldspeed
) {
2011 switch (phydev
->speed
) {
2014 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
2016 ecntrl
&= ~(ECNTRL_R100
);
2021 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
2023 /* Reduced mode distinguishes
2024 * between 10 and 100 */
2025 if (phydev
->speed
== SPEED_100
)
2026 ecntrl
|= ECNTRL_R100
;
2028 ecntrl
&= ~(ECNTRL_R100
);
2031 if (netif_msg_link(priv
))
2033 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2034 dev
->name
, phydev
->speed
);
2038 priv
->oldspeed
= phydev
->speed
;
2041 gfar_write(®s
->maccfg2
, tempval
);
2042 gfar_write(®s
->ecntrl
, ecntrl
);
2044 if (!priv
->oldlink
) {
2048 } else if (priv
->oldlink
) {
2052 priv
->oldduplex
= -1;
2055 if (new_state
&& netif_msg_link(priv
))
2056 phy_print_status(phydev
);
2058 spin_unlock_irqrestore(&priv
->txlock
, flags
);
2061 /* Update the hash table based on the current list of multicast
2062 * addresses we subscribe to. Also, change the promiscuity of
2063 * the device based on the flags (this function is called
2064 * whenever dev->flags is changed */
2065 static void gfar_set_multi(struct net_device
*dev
)
2067 struct dev_mc_list
*mc_ptr
;
2068 struct gfar_private
*priv
= netdev_priv(dev
);
2069 struct gfar __iomem
*regs
= priv
->regs
;
2072 if(dev
->flags
& IFF_PROMISC
) {
2073 /* Set RCTRL to PROM */
2074 tempval
= gfar_read(®s
->rctrl
);
2075 tempval
|= RCTRL_PROM
;
2076 gfar_write(®s
->rctrl
, tempval
);
2078 /* Set RCTRL to not PROM */
2079 tempval
= gfar_read(®s
->rctrl
);
2080 tempval
&= ~(RCTRL_PROM
);
2081 gfar_write(®s
->rctrl
, tempval
);
2084 if(dev
->flags
& IFF_ALLMULTI
) {
2085 /* Set the hash to rx all multicast frames */
2086 gfar_write(®s
->igaddr0
, 0xffffffff);
2087 gfar_write(®s
->igaddr1
, 0xffffffff);
2088 gfar_write(®s
->igaddr2
, 0xffffffff);
2089 gfar_write(®s
->igaddr3
, 0xffffffff);
2090 gfar_write(®s
->igaddr4
, 0xffffffff);
2091 gfar_write(®s
->igaddr5
, 0xffffffff);
2092 gfar_write(®s
->igaddr6
, 0xffffffff);
2093 gfar_write(®s
->igaddr7
, 0xffffffff);
2094 gfar_write(®s
->gaddr0
, 0xffffffff);
2095 gfar_write(®s
->gaddr1
, 0xffffffff);
2096 gfar_write(®s
->gaddr2
, 0xffffffff);
2097 gfar_write(®s
->gaddr3
, 0xffffffff);
2098 gfar_write(®s
->gaddr4
, 0xffffffff);
2099 gfar_write(®s
->gaddr5
, 0xffffffff);
2100 gfar_write(®s
->gaddr6
, 0xffffffff);
2101 gfar_write(®s
->gaddr7
, 0xffffffff);
2106 /* zero out the hash */
2107 gfar_write(®s
->igaddr0
, 0x0);
2108 gfar_write(®s
->igaddr1
, 0x0);
2109 gfar_write(®s
->igaddr2
, 0x0);
2110 gfar_write(®s
->igaddr3
, 0x0);
2111 gfar_write(®s
->igaddr4
, 0x0);
2112 gfar_write(®s
->igaddr5
, 0x0);
2113 gfar_write(®s
->igaddr6
, 0x0);
2114 gfar_write(®s
->igaddr7
, 0x0);
2115 gfar_write(®s
->gaddr0
, 0x0);
2116 gfar_write(®s
->gaddr1
, 0x0);
2117 gfar_write(®s
->gaddr2
, 0x0);
2118 gfar_write(®s
->gaddr3
, 0x0);
2119 gfar_write(®s
->gaddr4
, 0x0);
2120 gfar_write(®s
->gaddr5
, 0x0);
2121 gfar_write(®s
->gaddr6
, 0x0);
2122 gfar_write(®s
->gaddr7
, 0x0);
2124 /* If we have extended hash tables, we need to
2125 * clear the exact match registers to prepare for
2127 if (priv
->extended_hash
) {
2128 em_num
= GFAR_EM_NUM
+ 1;
2129 gfar_clear_exact_match(dev
);
2136 if(dev
->mc_count
== 0)
2139 /* Parse the list, and set the appropriate bits */
2140 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
2142 gfar_set_mac_for_addr(dev
, idx
,
2146 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
2154 /* Clears each of the exact match registers to zero, so they
2155 * don't interfere with normal reception */
2156 static void gfar_clear_exact_match(struct net_device
*dev
)
2159 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
2161 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
2162 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
2165 /* Set the appropriate hash bit for the given addr */
2166 /* The algorithm works like so:
2167 * 1) Take the Destination Address (ie the multicast address), and
2168 * do a CRC on it (little endian), and reverse the bits of the
2170 * 2) Use the 8 most significant bits as a hash into a 256-entry
2171 * table. The table is controlled through 8 32-bit registers:
2172 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2173 * gaddr7. This means that the 3 most significant bits in the
2174 * hash index which gaddr register to use, and the 5 other bits
2175 * indicate which bit (assuming an IBM numbering scheme, which
2176 * for PowerPC (tm) is usually the case) in the register holds
2178 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
2181 struct gfar_private
*priv
= netdev_priv(dev
);
2182 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
2183 int width
= priv
->hash_width
;
2184 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
2185 u8 whichreg
= result
>> (32 - width
+ 5);
2186 u32 value
= (1 << (31-whichbit
));
2188 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
2190 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
2196 /* There are multiple MAC Address register pairs on some controllers
2197 * This function sets the numth pair to a given address
2199 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
2201 struct gfar_private
*priv
= netdev_priv(dev
);
2203 char tmpbuf
[MAC_ADDR_LEN
];
2205 u32 __iomem
*macptr
= &priv
->regs
->macstnaddr1
;
2209 /* Now copy it into the mac registers backwards, cuz */
2210 /* little endian is silly */
2211 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
2212 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
2214 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
2216 tempval
= *((u32
*) (tmpbuf
+ 4));
2218 gfar_write(macptr
+1, tempval
);
2221 /* GFAR error interrupt handler */
2222 static irqreturn_t
gfar_error(int irq
, void *dev_id
)
2224 struct net_device
*dev
= dev_id
;
2225 struct gfar_private
*priv
= netdev_priv(dev
);
2227 /* Save ievent for future reference */
2228 u32 events
= gfar_read(&priv
->regs
->ievent
);
2231 gfar_write(&priv
->regs
->ievent
, events
& IEVENT_ERR_MASK
);
2233 /* Magic Packet is not an error. */
2234 if ((priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
) &&
2235 (events
& IEVENT_MAG
))
2236 events
&= ~IEVENT_MAG
;
2239 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
2240 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2241 dev
->name
, events
, gfar_read(&priv
->regs
->imask
));
2243 /* Update the error counters */
2244 if (events
& IEVENT_TXE
) {
2245 dev
->stats
.tx_errors
++;
2247 if (events
& IEVENT_LC
)
2248 dev
->stats
.tx_window_errors
++;
2249 if (events
& IEVENT_CRL
)
2250 dev
->stats
.tx_aborted_errors
++;
2251 if (events
& IEVENT_XFUN
) {
2252 if (netif_msg_tx_err(priv
))
2253 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
2254 "packet dropped.\n", dev
->name
);
2255 dev
->stats
.tx_dropped
++;
2256 priv
->extra_stats
.tx_underrun
++;
2258 /* Reactivate the Tx Queues */
2259 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
2261 if (netif_msg_tx_err(priv
))
2262 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
2264 if (events
& IEVENT_BSY
) {
2265 dev
->stats
.rx_errors
++;
2266 priv
->extra_stats
.rx_bsy
++;
2268 gfar_receive(irq
, dev_id
);
2270 if (netif_msg_rx_err(priv
))
2271 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
2272 dev
->name
, gfar_read(&priv
->regs
->rstat
));
2274 if (events
& IEVENT_BABR
) {
2275 dev
->stats
.rx_errors
++;
2276 priv
->extra_stats
.rx_babr
++;
2278 if (netif_msg_rx_err(priv
))
2279 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
2281 if (events
& IEVENT_EBERR
) {
2282 priv
->extra_stats
.eberr
++;
2283 if (netif_msg_rx_err(priv
))
2284 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
2286 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
2287 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
2289 if (events
& IEVENT_BABT
) {
2290 priv
->extra_stats
.tx_babt
++;
2291 if (netif_msg_tx_err(priv
))
2292 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
2297 /* work with hotplug and coldplug */
2298 MODULE_ALIAS("platform:fsl-gianfar");
2300 static struct of_device_id gfar_match
[] =
2304 .compatible
= "gianfar",
2309 /* Structure for a device driver */
2310 static struct of_platform_driver gfar_driver
= {
2311 .name
= "fsl-gianfar",
2312 .match_table
= gfar_match
,
2314 .probe
= gfar_probe
,
2315 .remove
= gfar_remove
,
2316 .suspend
= gfar_suspend
,
2317 .resume
= gfar_resume
,
2320 static int __init
gfar_init(void)
2322 return of_register_platform_driver(&gfar_driver
);
2325 static void __exit
gfar_exit(void)
2327 of_unregister_platform_driver(&gfar_driver
);
2330 module_init(gfar_init
);
2331 module_exit(gfar_exit
);