2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through platform_device. Structures which
29 * define the configuration needed by the board are defined in a
30 * board structure in arch/ppc/platforms (though I do not
31 * discount the possibility that other architectures could one
34 * The Gianfar Ethernet Controller uses a ring of buffer
35 * descriptors. The beginning is indicated by a register
36 * pointing to the physical address of the start of the ring.
37 * The end is determined by a "wrap" bit being set in the
38 * last descriptor of the ring.
40 * When a packet is received, the RXF bit in the
41 * IEVENT register is set, triggering an interrupt when the
42 * corresponding bit in the IMASK register is also set (if
43 * interrupt coalescing is active, then the interrupt may not
44 * happen immediately, but will wait until either a set number
45 * of frames or amount of time have passed). In NAPI, the
46 * interrupt handler will signal there is work to be done, and
47 * exit. Without NAPI, the packet(s) will be handled
48 * immediately. Both methods will start at the last known empty
49 * descriptor, and process every subsequent descriptor until there
50 * are none left with data (NAPI will stop after a set number of
51 * packets to give time to other tasks, but will eventually
52 * process all the packets). The data arrives inside a
53 * pre-allocated skb, and so after the skb is passed up to the
54 * stack, a new skb must be allocated, and the address field in
55 * the buffer descriptor must be updated to indicate this new
58 * When the kernel requests that a packet be transmitted, the
59 * driver starts where it left off last time, and points the
60 * descriptor at the buffer which was passed in. The driver
61 * then informs the DMA engine that there are packets ready to
62 * be transmitted. Once the controller is finished transmitting
63 * the packet, an interrupt may be triggered (under the same
64 * conditions as for reception, but depending on the TXF bit).
65 * The driver then cleans up the buffer.
68 #include <linux/kernel.h>
69 #include <linux/string.h>
70 #include <linux/errno.h>
71 #include <linux/unistd.h>
72 #include <linux/slab.h>
73 #include <linux/interrupt.h>
74 #include <linux/init.h>
75 #include <linux/delay.h>
76 #include <linux/netdevice.h>
77 #include <linux/etherdevice.h>
78 #include <linux/skbuff.h>
79 #include <linux/if_vlan.h>
80 #include <linux/spinlock.h>
82 #include <linux/platform_device.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
90 #include <asm/uaccess.h>
91 #include <linux/module.h>
92 #include <linux/dma-mapping.h>
93 #include <linux/crc32.h>
94 #include <linux/mii.h>
95 #include <linux/phy.h>
98 #include "gianfar_mii.h"
100 #define TX_TIMEOUT (1*HZ)
101 #define SKB_ALLOC_TIMEOUT 1000000
102 #undef BRIEF_GFAR_ERRORS
103 #undef VERBOSE_GFAR_ERRORS
105 #ifdef CONFIG_GFAR_NAPI
106 #define RECEIVE(x) netif_receive_skb(x)
108 #define RECEIVE(x) netif_rx(x)
111 const char gfar_driver_name
[] = "Gianfar Ethernet";
112 const char gfar_driver_version
[] = "1.3";
114 static int gfar_enet_open(struct net_device
*dev
);
115 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
116 static void gfar_timeout(struct net_device
*dev
);
117 static int gfar_close(struct net_device
*dev
);
118 struct sk_buff
*gfar_new_skb(struct net_device
*dev
, struct rxbd8
*bdp
);
119 static struct net_device_stats
*gfar_get_stats(struct net_device
*dev
);
120 static int gfar_set_mac_address(struct net_device
*dev
);
121 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
122 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
123 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
124 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
125 static void adjust_link(struct net_device
*dev
);
126 static void init_registers(struct net_device
*dev
);
127 static int init_phy(struct net_device
*dev
);
128 static int gfar_probe(struct platform_device
*pdev
);
129 static int gfar_remove(struct platform_device
*pdev
);
130 static void free_skb_resources(struct gfar_private
*priv
);
131 static void gfar_set_multi(struct net_device
*dev
);
132 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
133 static void gfar_configure_serdes(struct net_device
*dev
);
134 extern int gfar_local_mdio_write(struct gfar_mii
*regs
, int mii_id
, int regnum
, u16 value
);
135 extern int gfar_local_mdio_read(struct gfar_mii
*regs
, int mii_id
, int regnum
);
136 #ifdef CONFIG_GFAR_NAPI
137 static int gfar_poll(struct napi_struct
*napi
, int budget
);
139 #ifdef CONFIG_NET_POLL_CONTROLLER
140 static void gfar_netpoll(struct net_device
*dev
);
142 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
);
143 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
, int length
);
144 static void gfar_vlan_rx_register(struct net_device
*netdev
,
145 struct vlan_group
*grp
);
146 void gfar_halt(struct net_device
*dev
);
147 void gfar_start(struct net_device
*dev
);
148 static void gfar_clear_exact_match(struct net_device
*dev
);
149 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
151 extern const struct ethtool_ops gfar_ethtool_ops
;
153 MODULE_AUTHOR("Freescale Semiconductor, Inc");
154 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
155 MODULE_LICENSE("GPL");
157 /* Returns 1 if incoming frames use an FCB */
158 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
160 return (priv
->vlan_enable
|| priv
->rx_csum_enable
);
163 /* Set up the ethernet device structure, private data,
164 * and anything else we need before we start */
165 static int gfar_probe(struct platform_device
*pdev
)
168 struct net_device
*dev
= NULL
;
169 struct gfar_private
*priv
= NULL
;
170 struct gianfar_platform_data
*einfo
;
175 einfo
= (struct gianfar_platform_data
*) pdev
->dev
.platform_data
;
178 printk(KERN_ERR
"gfar %d: Missing additional data!\n",
184 /* Create an ethernet device instance */
185 dev
= alloc_etherdev(sizeof (*priv
));
190 priv
= netdev_priv(dev
);
193 /* Set the info in the priv to the current info */
196 /* fill out IRQ fields */
197 if (einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
198 priv
->interruptTransmit
= platform_get_irq_byname(pdev
, "tx");
199 priv
->interruptReceive
= platform_get_irq_byname(pdev
, "rx");
200 priv
->interruptError
= platform_get_irq_byname(pdev
, "error");
201 if (priv
->interruptTransmit
< 0 || priv
->interruptReceive
< 0 || priv
->interruptError
< 0)
204 priv
->interruptTransmit
= platform_get_irq(pdev
, 0);
205 if (priv
->interruptTransmit
< 0)
209 /* get a pointer to the register memory */
210 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
211 priv
->regs
= ioremap(r
->start
, sizeof (struct gfar
));
213 if (NULL
== priv
->regs
) {
218 spin_lock_init(&priv
->txlock
);
219 spin_lock_init(&priv
->rxlock
);
221 platform_set_drvdata(pdev
, dev
);
223 /* Stop the DMA engine now, in case it was running before */
224 /* (The firmware could have used it, and left it running). */
225 /* To do this, we write Graceful Receive Stop and Graceful */
226 /* Transmit Stop, and then wait until the corresponding bits */
227 /* in IEVENT indicate the stops have completed. */
228 tempval
= gfar_read(&priv
->regs
->dmactrl
);
229 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
230 gfar_write(&priv
->regs
->dmactrl
, tempval
);
232 tempval
= gfar_read(&priv
->regs
->dmactrl
);
233 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
234 gfar_write(&priv
->regs
->dmactrl
, tempval
);
236 while (!(gfar_read(&priv
->regs
->ievent
) & (IEVENT_GRSC
| IEVENT_GTSC
)))
239 /* Reset MAC layer */
240 gfar_write(&priv
->regs
->maccfg1
, MACCFG1_SOFT_RESET
);
242 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
243 gfar_write(&priv
->regs
->maccfg1
, tempval
);
245 /* Initialize MACCFG2. */
246 gfar_write(&priv
->regs
->maccfg2
, MACCFG2_INIT_SETTINGS
);
248 /* Initialize ECNTRL */
249 gfar_write(&priv
->regs
->ecntrl
, ECNTRL_INIT_SETTINGS
);
251 /* Copy the station address into the dev structure, */
252 memcpy(dev
->dev_addr
, einfo
->mac_addr
, MAC_ADDR_LEN
);
254 /* Set the dev->base_addr to the gfar reg region */
255 dev
->base_addr
= (unsigned long) (priv
->regs
);
257 SET_MODULE_OWNER(dev
);
258 SET_NETDEV_DEV(dev
, &pdev
->dev
);
260 /* Fill in the dev structure */
261 dev
->open
= gfar_enet_open
;
262 dev
->hard_start_xmit
= gfar_start_xmit
;
263 dev
->tx_timeout
= gfar_timeout
;
264 dev
->watchdog_timeo
= TX_TIMEOUT
;
265 netif_napi_add(dev
, &priv
->napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
266 #ifdef CONFIG_NET_POLL_CONTROLLER
267 dev
->poll_controller
= gfar_netpoll
;
269 dev
->stop
= gfar_close
;
270 dev
->get_stats
= gfar_get_stats
;
271 dev
->change_mtu
= gfar_change_mtu
;
273 dev
->set_multicast_list
= gfar_set_multi
;
275 dev
->ethtool_ops
= &gfar_ethtool_ops
;
277 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
278 priv
->rx_csum_enable
= 1;
279 dev
->features
|= NETIF_F_IP_CSUM
;
281 priv
->rx_csum_enable
= 0;
285 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
286 dev
->vlan_rx_register
= gfar_vlan_rx_register
;
288 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
290 priv
->vlan_enable
= 1;
293 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
294 priv
->extended_hash
= 1;
295 priv
->hash_width
= 9;
297 priv
->hash_regs
[0] = &priv
->regs
->igaddr0
;
298 priv
->hash_regs
[1] = &priv
->regs
->igaddr1
;
299 priv
->hash_regs
[2] = &priv
->regs
->igaddr2
;
300 priv
->hash_regs
[3] = &priv
->regs
->igaddr3
;
301 priv
->hash_regs
[4] = &priv
->regs
->igaddr4
;
302 priv
->hash_regs
[5] = &priv
->regs
->igaddr5
;
303 priv
->hash_regs
[6] = &priv
->regs
->igaddr6
;
304 priv
->hash_regs
[7] = &priv
->regs
->igaddr7
;
305 priv
->hash_regs
[8] = &priv
->regs
->gaddr0
;
306 priv
->hash_regs
[9] = &priv
->regs
->gaddr1
;
307 priv
->hash_regs
[10] = &priv
->regs
->gaddr2
;
308 priv
->hash_regs
[11] = &priv
->regs
->gaddr3
;
309 priv
->hash_regs
[12] = &priv
->regs
->gaddr4
;
310 priv
->hash_regs
[13] = &priv
->regs
->gaddr5
;
311 priv
->hash_regs
[14] = &priv
->regs
->gaddr6
;
312 priv
->hash_regs
[15] = &priv
->regs
->gaddr7
;
315 priv
->extended_hash
= 0;
316 priv
->hash_width
= 8;
318 priv
->hash_regs
[0] = &priv
->regs
->gaddr0
;
319 priv
->hash_regs
[1] = &priv
->regs
->gaddr1
;
320 priv
->hash_regs
[2] = &priv
->regs
->gaddr2
;
321 priv
->hash_regs
[3] = &priv
->regs
->gaddr3
;
322 priv
->hash_regs
[4] = &priv
->regs
->gaddr4
;
323 priv
->hash_regs
[5] = &priv
->regs
->gaddr5
;
324 priv
->hash_regs
[6] = &priv
->regs
->gaddr6
;
325 priv
->hash_regs
[7] = &priv
->regs
->gaddr7
;
328 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
329 priv
->padding
= DEFAULT_PADDING
;
333 if (dev
->features
& NETIF_F_IP_CSUM
)
334 dev
->hard_header_len
+= GMAC_FCB_LEN
;
336 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
337 priv
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
338 priv
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
340 priv
->txcoalescing
= DEFAULT_TX_COALESCE
;
341 priv
->txcount
= DEFAULT_TXCOUNT
;
342 priv
->txtime
= DEFAULT_TXTIME
;
343 priv
->rxcoalescing
= DEFAULT_RX_COALESCE
;
344 priv
->rxcount
= DEFAULT_RXCOUNT
;
345 priv
->rxtime
= DEFAULT_RXTIME
;
347 /* Enable most messages by default */
348 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
350 err
= register_netdev(dev
);
353 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
358 /* Create all the sysfs files */
359 gfar_init_sysfs(dev
);
361 /* Print out the device info */
362 printk(KERN_INFO DEVICE_NAME
, dev
->name
);
363 for (idx
= 0; idx
< 6; idx
++)
364 printk("%2.2x%c", dev
->dev_addr
[idx
], idx
== 5 ? ' ' : ':');
367 /* Even more device info helps when determining which kernel */
368 /* provided which set of benchmarks. */
369 #ifdef CONFIG_GFAR_NAPI
370 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
372 printk(KERN_INFO
"%s: Running with NAPI disabled\n", dev
->name
);
374 printk(KERN_INFO
"%s: %d/%d RX/TX BD ring size\n",
375 dev
->name
, priv
->rx_ring_size
, priv
->tx_ring_size
);
386 static int gfar_remove(struct platform_device
*pdev
)
388 struct net_device
*dev
= platform_get_drvdata(pdev
);
389 struct gfar_private
*priv
= netdev_priv(dev
);
391 platform_set_drvdata(pdev
, NULL
);
400 /* Reads the controller's registers to determine what interface
401 * connects it to the PHY.
403 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
405 struct gfar_private
*priv
= netdev_priv(dev
);
406 u32 ecntrl
= gfar_read(&priv
->regs
->ecntrl
);
408 if (ecntrl
& ECNTRL_SGMII_MODE
)
409 return PHY_INTERFACE_MODE_SGMII
;
411 if (ecntrl
& ECNTRL_TBI_MODE
) {
412 if (ecntrl
& ECNTRL_REDUCED_MODE
)
413 return PHY_INTERFACE_MODE_RTBI
;
415 return PHY_INTERFACE_MODE_TBI
;
418 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
419 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
420 return PHY_INTERFACE_MODE_RMII
;
422 phy_interface_t interface
= priv
->einfo
->interface
;
425 * This isn't autodetected right now, so it must
426 * be set by the device tree or platform code.
428 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
429 return PHY_INTERFACE_MODE_RGMII_ID
;
431 return PHY_INTERFACE_MODE_RGMII
;
435 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
436 return PHY_INTERFACE_MODE_GMII
;
438 return PHY_INTERFACE_MODE_MII
;
442 /* Initializes driver's PHY state, and attaches to the PHY.
443 * Returns 0 on success.
445 static int init_phy(struct net_device
*dev
)
447 struct gfar_private
*priv
= netdev_priv(dev
);
448 uint gigabit_support
=
449 priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
450 SUPPORTED_1000baseT_Full
: 0;
451 struct phy_device
*phydev
;
452 char phy_id
[BUS_ID_SIZE
];
453 phy_interface_t interface
;
457 priv
->oldduplex
= -1;
459 snprintf(phy_id
, BUS_ID_SIZE
, PHY_ID_FMT
, priv
->einfo
->bus_id
, priv
->einfo
->phy_id
);
461 interface
= gfar_get_interface(dev
);
463 phydev
= phy_connect(dev
, phy_id
, &adjust_link
, 0, interface
);
465 if (interface
== PHY_INTERFACE_MODE_SGMII
)
466 gfar_configure_serdes(dev
);
468 if (IS_ERR(phydev
)) {
469 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
470 return PTR_ERR(phydev
);
473 /* Remove any features not supported by the controller */
474 phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
475 phydev
->advertising
= phydev
->supported
;
477 priv
->phydev
= phydev
;
482 static void gfar_configure_serdes(struct net_device
*dev
)
484 struct gfar_private
*priv
= netdev_priv(dev
);
485 struct gfar_mii __iomem
*regs
=
486 (void __iomem
*)&priv
->regs
->gfar_mii_regs
;
488 /* Initialise TBI i/f to communicate with serdes (lynx phy) */
490 /* Single clk mode, mii mode off(for aerdes communication) */
491 gfar_local_mdio_write(regs
, TBIPA_VALUE
, MII_TBICON
, TBICON_CLK_SELECT
);
493 /* Supported pause and full-duplex, no half-duplex */
494 gfar_local_mdio_write(regs
, TBIPA_VALUE
, MII_ADVERTISE
,
495 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
496 ADVERTISE_1000XPSE_ASYM
);
498 /* ANEG enable, restart ANEG, full duplex mode, speed[1] set */
499 gfar_local_mdio_write(regs
, TBIPA_VALUE
, MII_BMCR
, BMCR_ANENABLE
|
500 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
503 static void init_registers(struct net_device
*dev
)
505 struct gfar_private
*priv
= netdev_priv(dev
);
508 gfar_write(&priv
->regs
->ievent
, IEVENT_INIT_CLEAR
);
510 /* Initialize IMASK */
511 gfar_write(&priv
->regs
->imask
, IMASK_INIT_CLEAR
);
513 /* Init hash registers to zero */
514 gfar_write(&priv
->regs
->igaddr0
, 0);
515 gfar_write(&priv
->regs
->igaddr1
, 0);
516 gfar_write(&priv
->regs
->igaddr2
, 0);
517 gfar_write(&priv
->regs
->igaddr3
, 0);
518 gfar_write(&priv
->regs
->igaddr4
, 0);
519 gfar_write(&priv
->regs
->igaddr5
, 0);
520 gfar_write(&priv
->regs
->igaddr6
, 0);
521 gfar_write(&priv
->regs
->igaddr7
, 0);
523 gfar_write(&priv
->regs
->gaddr0
, 0);
524 gfar_write(&priv
->regs
->gaddr1
, 0);
525 gfar_write(&priv
->regs
->gaddr2
, 0);
526 gfar_write(&priv
->regs
->gaddr3
, 0);
527 gfar_write(&priv
->regs
->gaddr4
, 0);
528 gfar_write(&priv
->regs
->gaddr5
, 0);
529 gfar_write(&priv
->regs
->gaddr6
, 0);
530 gfar_write(&priv
->regs
->gaddr7
, 0);
532 /* Zero out the rmon mib registers if it has them */
533 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
534 memset_io(&(priv
->regs
->rmon
), 0, sizeof (struct rmon_mib
));
536 /* Mask off the CAM interrupts */
537 gfar_write(&priv
->regs
->rmon
.cam1
, 0xffffffff);
538 gfar_write(&priv
->regs
->rmon
.cam2
, 0xffffffff);
541 /* Initialize the max receive buffer length */
542 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
544 /* Initialize the Minimum Frame Length Register */
545 gfar_write(&priv
->regs
->minflr
, MINFLR_INIT_SETTINGS
);
547 /* Assign the TBI an address which won't conflict with the PHYs */
548 gfar_write(&priv
->regs
->tbipa
, TBIPA_VALUE
);
552 /* Halt the receive and transmit queues */
553 void gfar_halt(struct net_device
*dev
)
555 struct gfar_private
*priv
= netdev_priv(dev
);
556 struct gfar __iomem
*regs
= priv
->regs
;
559 /* Mask all interrupts */
560 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
562 /* Clear all interrupts */
563 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
565 /* Stop the DMA, and wait for it to stop */
566 tempval
= gfar_read(&priv
->regs
->dmactrl
);
567 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
568 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
569 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
570 gfar_write(&priv
->regs
->dmactrl
, tempval
);
572 while (!(gfar_read(&priv
->regs
->ievent
) &
573 (IEVENT_GRSC
| IEVENT_GTSC
)))
577 /* Disable Rx and Tx */
578 tempval
= gfar_read(®s
->maccfg1
);
579 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
580 gfar_write(®s
->maccfg1
, tempval
);
583 void stop_gfar(struct net_device
*dev
)
585 struct gfar_private
*priv
= netdev_priv(dev
);
586 struct gfar __iomem
*regs
= priv
->regs
;
589 phy_stop(priv
->phydev
);
592 spin_lock_irqsave(&priv
->txlock
, flags
);
593 spin_lock(&priv
->rxlock
);
597 spin_unlock(&priv
->rxlock
);
598 spin_unlock_irqrestore(&priv
->txlock
, flags
);
601 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
602 free_irq(priv
->interruptError
, dev
);
603 free_irq(priv
->interruptTransmit
, dev
);
604 free_irq(priv
->interruptReceive
, dev
);
606 free_irq(priv
->interruptTransmit
, dev
);
609 free_skb_resources(priv
);
611 dma_free_coherent(NULL
,
612 sizeof(struct txbd8
)*priv
->tx_ring_size
613 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
615 gfar_read(®s
->tbase0
));
618 /* If there are any tx skbs or rx skbs still around, free them.
619 * Then free tx_skbuff and rx_skbuff */
620 static void free_skb_resources(struct gfar_private
*priv
)
626 /* Go through all the buffer descriptors and free their data buffers */
627 txbdp
= priv
->tx_bd_base
;
629 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
631 if (priv
->tx_skbuff
[i
]) {
632 dma_unmap_single(NULL
, txbdp
->bufPtr
,
635 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
636 priv
->tx_skbuff
[i
] = NULL
;
640 kfree(priv
->tx_skbuff
);
642 rxbdp
= priv
->rx_bd_base
;
644 /* rx_skbuff is not guaranteed to be allocated, so only
645 * free it and its contents if it is allocated */
646 if(priv
->rx_skbuff
!= NULL
) {
647 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
648 if (priv
->rx_skbuff
[i
]) {
649 dma_unmap_single(NULL
, rxbdp
->bufPtr
,
650 priv
->rx_buffer_size
,
653 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
654 priv
->rx_skbuff
[i
] = NULL
;
664 kfree(priv
->rx_skbuff
);
668 void gfar_start(struct net_device
*dev
)
670 struct gfar_private
*priv
= netdev_priv(dev
);
671 struct gfar __iomem
*regs
= priv
->regs
;
674 /* Enable Rx and Tx in MACCFG1 */
675 tempval
= gfar_read(®s
->maccfg1
);
676 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
677 gfar_write(®s
->maccfg1
, tempval
);
679 /* Initialize DMACTRL to have WWR and WOP */
680 tempval
= gfar_read(&priv
->regs
->dmactrl
);
681 tempval
|= DMACTRL_INIT_SETTINGS
;
682 gfar_write(&priv
->regs
->dmactrl
, tempval
);
684 /* Make sure we aren't stopped */
685 tempval
= gfar_read(&priv
->regs
->dmactrl
);
686 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
687 gfar_write(&priv
->regs
->dmactrl
, tempval
);
689 /* Clear THLT/RHLT, so that the DMA starts polling now */
690 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
);
691 gfar_write(®s
->rstat
, RSTAT_CLEAR_RHALT
);
693 /* Unmask the interrupts we look for */
694 gfar_write(®s
->imask
, IMASK_DEFAULT
);
697 /* Bring the controller up and running */
698 int startup_gfar(struct net_device
*dev
)
705 struct gfar_private
*priv
= netdev_priv(dev
);
706 struct gfar __iomem
*regs
= priv
->regs
;
711 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
713 /* Allocate memory for the buffer descriptors */
714 vaddr
= (unsigned long) dma_alloc_coherent(NULL
,
715 sizeof (struct txbd8
) * priv
->tx_ring_size
+
716 sizeof (struct rxbd8
) * priv
->rx_ring_size
,
720 if (netif_msg_ifup(priv
))
721 printk(KERN_ERR
"%s: Could not allocate buffer descriptors!\n",
726 priv
->tx_bd_base
= (struct txbd8
*) vaddr
;
728 /* enet DMA only understands physical addresses */
729 gfar_write(®s
->tbase0
, addr
);
731 /* Start the rx descriptor ring where the tx ring leaves off */
732 addr
= addr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
733 vaddr
= vaddr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
734 priv
->rx_bd_base
= (struct rxbd8
*) vaddr
;
735 gfar_write(®s
->rbase0
, addr
);
737 /* Setup the skbuff rings */
739 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
740 priv
->tx_ring_size
, GFP_KERNEL
);
742 if (NULL
== priv
->tx_skbuff
) {
743 if (netif_msg_ifup(priv
))
744 printk(KERN_ERR
"%s: Could not allocate tx_skbuff\n",
750 for (i
= 0; i
< priv
->tx_ring_size
; i
++)
751 priv
->tx_skbuff
[i
] = NULL
;
754 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
755 priv
->rx_ring_size
, GFP_KERNEL
);
757 if (NULL
== priv
->rx_skbuff
) {
758 if (netif_msg_ifup(priv
))
759 printk(KERN_ERR
"%s: Could not allocate rx_skbuff\n",
765 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
766 priv
->rx_skbuff
[i
] = NULL
;
768 /* Initialize some variables in our dev structure */
769 priv
->dirty_tx
= priv
->cur_tx
= priv
->tx_bd_base
;
770 priv
->cur_rx
= priv
->rx_bd_base
;
771 priv
->skb_curtx
= priv
->skb_dirtytx
= 0;
774 /* Initialize Transmit Descriptor Ring */
775 txbdp
= priv
->tx_bd_base
;
776 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
783 /* Set the last descriptor in the ring to indicate wrap */
785 txbdp
->status
|= TXBD_WRAP
;
787 rxbdp
= priv
->rx_bd_base
;
788 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
789 struct sk_buff
*skb
= NULL
;
793 skb
= gfar_new_skb(dev
, rxbdp
);
795 priv
->rx_skbuff
[i
] = skb
;
800 /* Set the last descriptor in the ring to wrap */
802 rxbdp
->status
|= RXBD_WRAP
;
804 /* If the device has multiple interrupts, register for
805 * them. Otherwise, only register for the one */
806 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
807 /* Install our interrupt handlers for Error,
808 * Transmit, and Receive */
809 if (request_irq(priv
->interruptError
, gfar_error
,
810 0, "enet_error", dev
) < 0) {
811 if (netif_msg_intr(priv
))
812 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
813 dev
->name
, priv
->interruptError
);
819 if (request_irq(priv
->interruptTransmit
, gfar_transmit
,
820 0, "enet_tx", dev
) < 0) {
821 if (netif_msg_intr(priv
))
822 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
823 dev
->name
, priv
->interruptTransmit
);
830 if (request_irq(priv
->interruptReceive
, gfar_receive
,
831 0, "enet_rx", dev
) < 0) {
832 if (netif_msg_intr(priv
))
833 printk(KERN_ERR
"%s: Can't get IRQ %d (receive0)\n",
834 dev
->name
, priv
->interruptReceive
);
840 if (request_irq(priv
->interruptTransmit
, gfar_interrupt
,
841 0, "gfar_interrupt", dev
) < 0) {
842 if (netif_msg_intr(priv
))
843 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
844 dev
->name
, priv
->interruptError
);
851 phy_start(priv
->phydev
);
853 /* Configure the coalescing support */
854 if (priv
->txcoalescing
)
855 gfar_write(®s
->txic
,
856 mk_ic_value(priv
->txcount
, priv
->txtime
));
858 gfar_write(®s
->txic
, 0);
860 if (priv
->rxcoalescing
)
861 gfar_write(®s
->rxic
,
862 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
864 gfar_write(®s
->rxic
, 0);
866 if (priv
->rx_csum_enable
)
867 rctrl
|= RCTRL_CHECKSUMMING
;
869 if (priv
->extended_hash
) {
870 rctrl
|= RCTRL_EXTHASH
;
872 gfar_clear_exact_match(dev
);
876 if (priv
->vlan_enable
)
880 rctrl
&= ~RCTRL_PAL_MASK
;
881 rctrl
|= RCTRL_PADDING(priv
->padding
);
884 /* Init rctrl based on our settings */
885 gfar_write(&priv
->regs
->rctrl
, rctrl
);
887 if (dev
->features
& NETIF_F_IP_CSUM
)
888 gfar_write(&priv
->regs
->tctrl
, TCTRL_INIT_CSUM
);
890 /* Set the extraction length and index */
891 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
892 ATTRELI_EI(priv
->rx_stash_index
);
894 gfar_write(&priv
->regs
->attreli
, attrs
);
896 /* Start with defaults, and add stashing or locking
897 * depending on the approprate variables */
898 attrs
= ATTR_INIT_SETTINGS
;
900 if (priv
->bd_stash_en
)
901 attrs
|= ATTR_BDSTASH
;
903 if (priv
->rx_stash_size
!= 0)
904 attrs
|= ATTR_BUFSTASH
;
906 gfar_write(&priv
->regs
->attr
, attrs
);
908 gfar_write(&priv
->regs
->fifo_tx_thr
, priv
->fifo_threshold
);
909 gfar_write(&priv
->regs
->fifo_tx_starve
, priv
->fifo_starve
);
910 gfar_write(&priv
->regs
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
912 /* Start the controller */
918 free_irq(priv
->interruptTransmit
, dev
);
920 free_irq(priv
->interruptError
, dev
);
923 free_skb_resources(priv
);
925 dma_free_coherent(NULL
,
926 sizeof(struct txbd8
)*priv
->tx_ring_size
927 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
929 gfar_read(®s
->tbase0
));
934 /* Called when something needs to use the ethernet device */
935 /* Returns 0 for success. */
936 static int gfar_enet_open(struct net_device
*dev
)
940 napi_enable(&priv
->napi
);
942 /* Initialize a bunch of registers */
945 gfar_set_mac_address(dev
);
950 napi_disable(&priv
->napi
);
954 err
= startup_gfar(dev
);
956 napi_disable(&priv
->napi
);
958 netif_start_queue(dev
);
963 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
, struct txbd8
*bdp
)
965 struct txfcb
*fcb
= (struct txfcb
*)skb_push (skb
, GMAC_FCB_LEN
);
967 memset(fcb
, 0, GMAC_FCB_LEN
);
972 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
976 /* If we're here, it's a IP packet with a TCP or UDP
977 * payload. We set it to checksum, using a pseudo-header
980 flags
= TXFCB_DEFAULT
;
982 /* Tell the controller what the protocol is */
983 /* And provide the already calculated phcs */
984 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
986 fcb
->phcs
= udp_hdr(skb
)->check
;
988 fcb
->phcs
= tcp_hdr(skb
)->check
;
990 /* l3os is the distance between the start of the
991 * frame (skb->data) and the start of the IP hdr.
992 * l4os is the distance between the start of the
993 * l3 hdr and the l4 hdr */
994 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
995 fcb
->l4os
= skb_network_header_len(skb
);
1000 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
1002 fcb
->flags
|= TXFCB_VLN
;
1003 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1006 /* This is called by the kernel when a frame is ready for transmission. */
1007 /* It is pointed to by the dev->hard_start_xmit function pointer */
1008 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1010 struct gfar_private
*priv
= netdev_priv(dev
);
1011 struct txfcb
*fcb
= NULL
;
1012 struct txbd8
*txbdp
;
1014 unsigned long flags
;
1016 /* Update transmit stats */
1017 priv
->stats
.tx_bytes
+= skb
->len
;
1020 spin_lock_irqsave(&priv
->txlock
, flags
);
1022 /* Point at the first free tx descriptor */
1023 txbdp
= priv
->cur_tx
;
1025 /* Clear all but the WRAP status flags */
1026 status
= txbdp
->status
& TXBD_WRAP
;
1028 /* Set up checksumming */
1029 if (likely((dev
->features
& NETIF_F_IP_CSUM
)
1030 && (CHECKSUM_PARTIAL
== skb
->ip_summed
))) {
1031 fcb
= gfar_add_fcb(skb
, txbdp
);
1033 gfar_tx_checksum(skb
, fcb
);
1036 if (priv
->vlan_enable
&&
1037 unlikely(priv
->vlgrp
&& vlan_tx_tag_present(skb
))) {
1038 if (unlikely(NULL
== fcb
)) {
1039 fcb
= gfar_add_fcb(skb
, txbdp
);
1043 gfar_tx_vlan(skb
, fcb
);
1046 /* Set buffer length and pointer */
1047 txbdp
->length
= skb
->len
;
1048 txbdp
->bufPtr
= dma_map_single(NULL
, skb
->data
,
1049 skb
->len
, DMA_TO_DEVICE
);
1051 /* Save the skb pointer so we can free it later */
1052 priv
->tx_skbuff
[priv
->skb_curtx
] = skb
;
1054 /* Update the current skb pointer (wrapping if this was the last) */
1056 (priv
->skb_curtx
+ 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1058 /* Flag the BD as interrupt-causing */
1059 status
|= TXBD_INTERRUPT
;
1061 /* Flag the BD as ready to go, last in frame, and */
1062 /* in need of CRC */
1063 status
|= (TXBD_READY
| TXBD_LAST
| TXBD_CRC
);
1065 dev
->trans_start
= jiffies
;
1067 /* The powerpc-specific eieio() is used, as wmb() has too strong
1068 * semantics (it requires synchronization between cacheable and
1069 * uncacheable mappings, which eieio doesn't provide and which we
1070 * don't need), thus requiring a more expensive sync instruction. At
1071 * some point, the set of architecture-independent barrier functions
1072 * should be expanded to include weaker barriers.
1076 txbdp
->status
= status
;
1078 /* If this was the last BD in the ring, the next one */
1079 /* is at the beginning of the ring */
1080 if (txbdp
->status
& TXBD_WRAP
)
1081 txbdp
= priv
->tx_bd_base
;
1085 /* If the next BD still needs to be cleaned up, then the bds
1086 are full. We need to tell the kernel to stop sending us stuff. */
1087 if (txbdp
== priv
->dirty_tx
) {
1088 netif_stop_queue(dev
);
1090 priv
->stats
.tx_fifo_errors
++;
1093 /* Update the current txbd to the next one */
1094 priv
->cur_tx
= txbdp
;
1096 /* Tell the DMA to go go go */
1097 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1100 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1105 /* Stops the kernel queue, and halts the controller */
1106 static int gfar_close(struct net_device
*dev
)
1108 struct gfar_private
*priv
= netdev_priv(dev
);
1110 napi_disable(&priv
->napi
);
1114 /* Disconnect from the PHY */
1115 phy_disconnect(priv
->phydev
);
1116 priv
->phydev
= NULL
;
1118 netif_stop_queue(dev
);
1123 /* returns a net_device_stats structure pointer */
1124 static struct net_device_stats
* gfar_get_stats(struct net_device
*dev
)
1126 struct gfar_private
*priv
= netdev_priv(dev
);
1128 return &(priv
->stats
);
1131 /* Changes the mac address if the controller is not running. */
1132 int gfar_set_mac_address(struct net_device
*dev
)
1134 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
1140 /* Enables and disables VLAN insertion/extraction */
1141 static void gfar_vlan_rx_register(struct net_device
*dev
,
1142 struct vlan_group
*grp
)
1144 struct gfar_private
*priv
= netdev_priv(dev
);
1145 unsigned long flags
;
1148 spin_lock_irqsave(&priv
->rxlock
, flags
);
1153 /* Enable VLAN tag insertion */
1154 tempval
= gfar_read(&priv
->regs
->tctrl
);
1155 tempval
|= TCTRL_VLINS
;
1157 gfar_write(&priv
->regs
->tctrl
, tempval
);
1159 /* Enable VLAN tag extraction */
1160 tempval
= gfar_read(&priv
->regs
->rctrl
);
1161 tempval
|= RCTRL_VLEX
;
1162 gfar_write(&priv
->regs
->rctrl
, tempval
);
1164 /* Disable VLAN tag insertion */
1165 tempval
= gfar_read(&priv
->regs
->tctrl
);
1166 tempval
&= ~TCTRL_VLINS
;
1167 gfar_write(&priv
->regs
->tctrl
, tempval
);
1169 /* Disable VLAN tag extraction */
1170 tempval
= gfar_read(&priv
->regs
->rctrl
);
1171 tempval
&= ~RCTRL_VLEX
;
1172 gfar_write(&priv
->regs
->rctrl
, tempval
);
1175 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1178 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
1180 int tempsize
, tempval
;
1181 struct gfar_private
*priv
= netdev_priv(dev
);
1182 int oldsize
= priv
->rx_buffer_size
;
1183 int frame_size
= new_mtu
+ ETH_HLEN
;
1185 if (priv
->vlan_enable
)
1186 frame_size
+= VLAN_ETH_HLEN
;
1188 if (gfar_uses_fcb(priv
))
1189 frame_size
+= GMAC_FCB_LEN
;
1191 frame_size
+= priv
->padding
;
1193 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
1194 if (netif_msg_drv(priv
))
1195 printk(KERN_ERR
"%s: Invalid MTU setting\n",
1201 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
1202 INCREMENTAL_BUFFER_SIZE
;
1204 /* Only stop and start the controller if it isn't already
1205 * stopped, and we changed something */
1206 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1209 priv
->rx_buffer_size
= tempsize
;
1213 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
1214 gfar_write(&priv
->regs
->maxfrm
, priv
->rx_buffer_size
);
1216 /* If the mtu is larger than the max size for standard
1217 * ethernet frames (ie, a jumbo frame), then set maccfg2
1218 * to allow huge frames, and to check the length */
1219 tempval
= gfar_read(&priv
->regs
->maccfg2
);
1221 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
1222 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1224 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1226 gfar_write(&priv
->regs
->maccfg2
, tempval
);
1228 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1234 /* gfar_timeout gets called when a packet has not been
1235 * transmitted after a set amount of time.
1236 * For now, assume that clearing out all the structures, and
1237 * starting over will fix the problem. */
1238 static void gfar_timeout(struct net_device
*dev
)
1240 struct gfar_private
*priv
= netdev_priv(dev
);
1242 priv
->stats
.tx_errors
++;
1244 if (dev
->flags
& IFF_UP
) {
1249 netif_schedule(dev
);
1252 /* Interrupt Handler for Transmit complete */
1253 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
)
1255 struct net_device
*dev
= (struct net_device
*) dev_id
;
1256 struct gfar_private
*priv
= netdev_priv(dev
);
1260 gfar_write(&priv
->regs
->ievent
, IEVENT_TX_MASK
);
1263 spin_lock(&priv
->txlock
);
1264 bdp
= priv
->dirty_tx
;
1265 while ((bdp
->status
& TXBD_READY
) == 0) {
1266 /* If dirty_tx and cur_tx are the same, then either the */
1267 /* ring is empty or full now (it could only be full in the beginning, */
1268 /* obviously). If it is empty, we are done. */
1269 if ((bdp
== priv
->cur_tx
) && (netif_queue_stopped(dev
) == 0))
1272 priv
->stats
.tx_packets
++;
1274 /* Deferred means some collisions occurred during transmit, */
1275 /* but we eventually sent the packet. */
1276 if (bdp
->status
& TXBD_DEF
)
1277 priv
->stats
.collisions
++;
1279 /* Free the sk buffer associated with this TxBD */
1280 dev_kfree_skb_irq(priv
->tx_skbuff
[priv
->skb_dirtytx
]);
1281 priv
->tx_skbuff
[priv
->skb_dirtytx
] = NULL
;
1283 (priv
->skb_dirtytx
+
1284 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1286 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1287 if (bdp
->status
& TXBD_WRAP
)
1288 bdp
= priv
->tx_bd_base
;
1292 /* Move dirty_tx to be the next bd */
1293 priv
->dirty_tx
= bdp
;
1295 /* We freed a buffer, so now we can restart transmission */
1296 if (netif_queue_stopped(dev
))
1297 netif_wake_queue(dev
);
1298 } /* while ((bdp->status & TXBD_READY) == 0) */
1300 /* If we are coalescing the interrupts, reset the timer */
1301 /* Otherwise, clear it */
1302 if (priv
->txcoalescing
)
1303 gfar_write(&priv
->regs
->txic
,
1304 mk_ic_value(priv
->txcount
, priv
->txtime
));
1306 gfar_write(&priv
->regs
->txic
, 0);
1308 spin_unlock(&priv
->txlock
);
1313 struct sk_buff
* gfar_new_skb(struct net_device
*dev
, struct rxbd8
*bdp
)
1315 unsigned int alignamount
;
1316 struct gfar_private
*priv
= netdev_priv(dev
);
1317 struct sk_buff
*skb
= NULL
;
1318 unsigned int timeout
= SKB_ALLOC_TIMEOUT
;
1320 /* We have to allocate the skb, so keep trying till we succeed */
1321 while ((!skb
) && timeout
--)
1322 skb
= dev_alloc_skb(priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
1327 alignamount
= RXBUF_ALIGNMENT
-
1328 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
1330 /* We need the data buffer to be aligned properly. We will reserve
1331 * as many bytes as needed to align the data properly
1333 skb_reserve(skb
, alignamount
);
1335 bdp
->bufPtr
= dma_map_single(NULL
, skb
->data
,
1336 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1340 /* Mark the buffer empty */
1342 bdp
->status
|= (RXBD_EMPTY
| RXBD_INTERRUPT
);
1347 static inline void count_errors(unsigned short status
, struct gfar_private
*priv
)
1349 struct net_device_stats
*stats
= &priv
->stats
;
1350 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
1352 /* If the packet was truncated, none of the other errors
1354 if (status
& RXBD_TRUNCATED
) {
1355 stats
->rx_length_errors
++;
1361 /* Count the errors, if there were any */
1362 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
1363 stats
->rx_length_errors
++;
1365 if (status
& RXBD_LARGE
)
1370 if (status
& RXBD_NONOCTET
) {
1371 stats
->rx_frame_errors
++;
1372 estats
->rx_nonoctet
++;
1374 if (status
& RXBD_CRCERR
) {
1375 estats
->rx_crcerr
++;
1376 stats
->rx_crc_errors
++;
1378 if (status
& RXBD_OVERRUN
) {
1379 estats
->rx_overrun
++;
1380 stats
->rx_crc_errors
++;
1384 irqreturn_t
gfar_receive(int irq
, void *dev_id
)
1386 struct net_device
*dev
= (struct net_device
*) dev_id
;
1387 struct gfar_private
*priv
= netdev_priv(dev
);
1388 #ifdef CONFIG_GFAR_NAPI
1391 unsigned long flags
;
1394 /* Clear IEVENT, so rx interrupt isn't called again
1395 * because of this interrupt */
1396 gfar_write(&priv
->regs
->ievent
, IEVENT_RX_MASK
);
1399 #ifdef CONFIG_GFAR_NAPI
1400 if (netif_rx_schedule_prep(dev
, &priv
->napi
)) {
1401 tempval
= gfar_read(&priv
->regs
->imask
);
1402 tempval
&= IMASK_RX_DISABLED
;
1403 gfar_write(&priv
->regs
->imask
, tempval
);
1405 __netif_rx_schedule(dev
, &priv
->napi
);
1407 if (netif_msg_rx_err(priv
))
1408 printk(KERN_DEBUG
"%s: receive called twice (%x)[%x]\n",
1409 dev
->name
, gfar_read(&priv
->regs
->ievent
),
1410 gfar_read(&priv
->regs
->imask
));
1414 spin_lock_irqsave(&priv
->rxlock
, flags
);
1415 gfar_clean_rx_ring(dev
, priv
->rx_ring_size
);
1417 /* If we are coalescing interrupts, update the timer */
1418 /* Otherwise, clear it */
1419 if (priv
->rxcoalescing
)
1420 gfar_write(&priv
->regs
->rxic
,
1421 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
1423 gfar_write(&priv
->regs
->rxic
, 0);
1425 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1431 static inline int gfar_rx_vlan(struct sk_buff
*skb
,
1432 struct vlan_group
*vlgrp
, unsigned short vlctl
)
1434 #ifdef CONFIG_GFAR_NAPI
1435 return vlan_hwaccel_receive_skb(skb
, vlgrp
, vlctl
);
1437 return vlan_hwaccel_rx(skb
, vlgrp
, vlctl
);
1441 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
1443 /* If valid headers were found, and valid sums
1444 * were verified, then we tell the kernel that no
1445 * checksumming is necessary. Otherwise, it is */
1446 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
1447 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1449 skb
->ip_summed
= CHECKSUM_NONE
;
1453 static inline struct rxfcb
*gfar_get_fcb(struct sk_buff
*skb
)
1455 struct rxfcb
*fcb
= (struct rxfcb
*)skb
->data
;
1457 /* Remove the FCB from the skb */
1458 skb_pull(skb
, GMAC_FCB_LEN
);
1463 /* gfar_process_frame() -- handle one incoming packet if skb
1465 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
1468 struct gfar_private
*priv
= netdev_priv(dev
);
1469 struct rxfcb
*fcb
= NULL
;
1472 if (netif_msg_rx_err(priv
))
1473 printk(KERN_WARNING
"%s: Missing skb!!.\n", dev
->name
);
1474 priv
->stats
.rx_dropped
++;
1475 priv
->extra_stats
.rx_skbmissing
++;
1479 /* Prep the skb for the packet */
1480 skb_put(skb
, length
);
1482 /* Grab the FCB if there is one */
1483 if (gfar_uses_fcb(priv
))
1484 fcb
= gfar_get_fcb(skb
);
1486 /* Remove the padded bytes, if there are any */
1488 skb_pull(skb
, priv
->padding
);
1490 if (priv
->rx_csum_enable
)
1491 gfar_rx_checksum(skb
, fcb
);
1493 /* Tell the skb what kind of packet this is */
1494 skb
->protocol
= eth_type_trans(skb
, dev
);
1496 /* Send the packet up the stack */
1497 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
)))
1498 ret
= gfar_rx_vlan(skb
, priv
->vlgrp
, fcb
->vlctl
);
1502 if (NET_RX_DROP
== ret
)
1503 priv
->extra_stats
.kernel_dropped
++;
1509 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1510 * until the budget/quota has been reached. Returns the number
1513 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
)
1516 struct sk_buff
*skb
;
1519 struct gfar_private
*priv
= netdev_priv(dev
);
1521 /* Get the first full descriptor */
1524 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
1526 skb
= priv
->rx_skbuff
[priv
->skb_currx
];
1529 (RXBD_LARGE
| RXBD_SHORT
| RXBD_NONOCTET
1530 | RXBD_CRCERR
| RXBD_OVERRUN
| RXBD_TRUNCATED
))) {
1531 /* Increment the number of packets */
1532 priv
->stats
.rx_packets
++;
1535 /* Remove the FCS from the packet length */
1536 pkt_len
= bdp
->length
- 4;
1538 gfar_process_frame(dev
, skb
, pkt_len
);
1540 priv
->stats
.rx_bytes
+= pkt_len
;
1542 count_errors(bdp
->status
, priv
);
1545 dev_kfree_skb_any(skb
);
1547 priv
->rx_skbuff
[priv
->skb_currx
] = NULL
;
1550 dev
->last_rx
= jiffies
;
1552 /* Clear the status flags for this buffer */
1553 bdp
->status
&= ~RXBD_STATS
;
1555 /* Add another skb for the future */
1556 skb
= gfar_new_skb(dev
, bdp
);
1557 priv
->rx_skbuff
[priv
->skb_currx
] = skb
;
1559 /* Update to the next pointer */
1560 if (bdp
->status
& RXBD_WRAP
)
1561 bdp
= priv
->rx_bd_base
;
1565 /* update to point at the next skb */
1568 1) & RX_RING_MOD_MASK(priv
->rx_ring_size
);
1572 /* Update the current rxbd pointer to be the next one */
1578 #ifdef CONFIG_GFAR_NAPI
1579 static int gfar_poll(struct napi_struct
*napi
, int budget
)
1581 struct gfar_private
*priv
= container_of(napi
, struct gfar_private
, napi
);
1582 struct net_device
*dev
= priv
->dev
;
1585 howmany
= gfar_clean_rx_ring(dev
, budget
);
1587 if (howmany
< budget
) {
1588 netif_rx_complete(dev
, napi
);
1590 /* Clear the halt bit in RSTAT */
1591 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1593 gfar_write(&priv
->regs
->imask
, IMASK_DEFAULT
);
1595 /* If we are coalescing interrupts, update the timer */
1596 /* Otherwise, clear it */
1597 if (priv
->rxcoalescing
)
1598 gfar_write(&priv
->regs
->rxic
,
1599 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
1601 gfar_write(&priv
->regs
->rxic
, 0);
1608 #ifdef CONFIG_NET_POLL_CONTROLLER
1610 * Polling 'interrupt' - used by things like netconsole to send skbs
1611 * without having to re-enable interrupts. It's not called while
1612 * the interrupt routine is executing.
1614 static void gfar_netpoll(struct net_device
*dev
)
1616 struct gfar_private
*priv
= netdev_priv(dev
);
1618 /* If the device has multiple interrupts, run tx/rx */
1619 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1620 disable_irq(priv
->interruptTransmit
);
1621 disable_irq(priv
->interruptReceive
);
1622 disable_irq(priv
->interruptError
);
1623 gfar_interrupt(priv
->interruptTransmit
, dev
);
1624 enable_irq(priv
->interruptError
);
1625 enable_irq(priv
->interruptReceive
);
1626 enable_irq(priv
->interruptTransmit
);
1628 disable_irq(priv
->interruptTransmit
);
1629 gfar_interrupt(priv
->interruptTransmit
, dev
);
1630 enable_irq(priv
->interruptTransmit
);
1635 /* The interrupt handler for devices with one interrupt */
1636 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
)
1638 struct net_device
*dev
= dev_id
;
1639 struct gfar_private
*priv
= netdev_priv(dev
);
1641 /* Save ievent for future reference */
1642 u32 events
= gfar_read(&priv
->regs
->ievent
);
1644 /* Check for reception */
1645 if (events
& IEVENT_RX_MASK
)
1646 gfar_receive(irq
, dev_id
);
1648 /* Check for transmit completion */
1649 if (events
& IEVENT_TX_MASK
)
1650 gfar_transmit(irq
, dev_id
);
1652 /* Check for errors */
1653 if (events
& IEVENT_ERR_MASK
)
1654 gfar_error(irq
, dev_id
);
1659 /* Called every time the controller might need to be made
1660 * aware of new link state. The PHY code conveys this
1661 * information through variables in the phydev structure, and this
1662 * function converts those variables into the appropriate
1663 * register values, and can bring down the device if needed.
1665 static void adjust_link(struct net_device
*dev
)
1667 struct gfar_private
*priv
= netdev_priv(dev
);
1668 struct gfar __iomem
*regs
= priv
->regs
;
1669 unsigned long flags
;
1670 struct phy_device
*phydev
= priv
->phydev
;
1673 spin_lock_irqsave(&priv
->txlock
, flags
);
1675 u32 tempval
= gfar_read(®s
->maccfg2
);
1676 u32 ecntrl
= gfar_read(®s
->ecntrl
);
1678 /* Now we make sure that we can be in full duplex mode.
1679 * If not, we operate in half-duplex mode. */
1680 if (phydev
->duplex
!= priv
->oldduplex
) {
1682 if (!(phydev
->duplex
))
1683 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
1685 tempval
|= MACCFG2_FULL_DUPLEX
;
1687 priv
->oldduplex
= phydev
->duplex
;
1690 if (phydev
->speed
!= priv
->oldspeed
) {
1692 switch (phydev
->speed
) {
1695 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
1700 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
1702 /* Reduced mode distinguishes
1703 * between 10 and 100 */
1704 if (phydev
->speed
== SPEED_100
)
1705 ecntrl
|= ECNTRL_R100
;
1707 ecntrl
&= ~(ECNTRL_R100
);
1710 if (netif_msg_link(priv
))
1712 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1713 dev
->name
, phydev
->speed
);
1717 priv
->oldspeed
= phydev
->speed
;
1720 gfar_write(®s
->maccfg2
, tempval
);
1721 gfar_write(®s
->ecntrl
, ecntrl
);
1723 if (!priv
->oldlink
) {
1726 netif_schedule(dev
);
1728 } else if (priv
->oldlink
) {
1732 priv
->oldduplex
= -1;
1735 if (new_state
&& netif_msg_link(priv
))
1736 phy_print_status(phydev
);
1738 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1741 /* Update the hash table based on the current list of multicast
1742 * addresses we subscribe to. Also, change the promiscuity of
1743 * the device based on the flags (this function is called
1744 * whenever dev->flags is changed */
1745 static void gfar_set_multi(struct net_device
*dev
)
1747 struct dev_mc_list
*mc_ptr
;
1748 struct gfar_private
*priv
= netdev_priv(dev
);
1749 struct gfar __iomem
*regs
= priv
->regs
;
1752 if(dev
->flags
& IFF_PROMISC
) {
1753 /* Set RCTRL to PROM */
1754 tempval
= gfar_read(®s
->rctrl
);
1755 tempval
|= RCTRL_PROM
;
1756 gfar_write(®s
->rctrl
, tempval
);
1758 /* Set RCTRL to not PROM */
1759 tempval
= gfar_read(®s
->rctrl
);
1760 tempval
&= ~(RCTRL_PROM
);
1761 gfar_write(®s
->rctrl
, tempval
);
1764 if(dev
->flags
& IFF_ALLMULTI
) {
1765 /* Set the hash to rx all multicast frames */
1766 gfar_write(®s
->igaddr0
, 0xffffffff);
1767 gfar_write(®s
->igaddr1
, 0xffffffff);
1768 gfar_write(®s
->igaddr2
, 0xffffffff);
1769 gfar_write(®s
->igaddr3
, 0xffffffff);
1770 gfar_write(®s
->igaddr4
, 0xffffffff);
1771 gfar_write(®s
->igaddr5
, 0xffffffff);
1772 gfar_write(®s
->igaddr6
, 0xffffffff);
1773 gfar_write(®s
->igaddr7
, 0xffffffff);
1774 gfar_write(®s
->gaddr0
, 0xffffffff);
1775 gfar_write(®s
->gaddr1
, 0xffffffff);
1776 gfar_write(®s
->gaddr2
, 0xffffffff);
1777 gfar_write(®s
->gaddr3
, 0xffffffff);
1778 gfar_write(®s
->gaddr4
, 0xffffffff);
1779 gfar_write(®s
->gaddr5
, 0xffffffff);
1780 gfar_write(®s
->gaddr6
, 0xffffffff);
1781 gfar_write(®s
->gaddr7
, 0xffffffff);
1786 /* zero out the hash */
1787 gfar_write(®s
->igaddr0
, 0x0);
1788 gfar_write(®s
->igaddr1
, 0x0);
1789 gfar_write(®s
->igaddr2
, 0x0);
1790 gfar_write(®s
->igaddr3
, 0x0);
1791 gfar_write(®s
->igaddr4
, 0x0);
1792 gfar_write(®s
->igaddr5
, 0x0);
1793 gfar_write(®s
->igaddr6
, 0x0);
1794 gfar_write(®s
->igaddr7
, 0x0);
1795 gfar_write(®s
->gaddr0
, 0x0);
1796 gfar_write(®s
->gaddr1
, 0x0);
1797 gfar_write(®s
->gaddr2
, 0x0);
1798 gfar_write(®s
->gaddr3
, 0x0);
1799 gfar_write(®s
->gaddr4
, 0x0);
1800 gfar_write(®s
->gaddr5
, 0x0);
1801 gfar_write(®s
->gaddr6
, 0x0);
1802 gfar_write(®s
->gaddr7
, 0x0);
1804 /* If we have extended hash tables, we need to
1805 * clear the exact match registers to prepare for
1807 if (priv
->extended_hash
) {
1808 em_num
= GFAR_EM_NUM
+ 1;
1809 gfar_clear_exact_match(dev
);
1816 if(dev
->mc_count
== 0)
1819 /* Parse the list, and set the appropriate bits */
1820 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
1822 gfar_set_mac_for_addr(dev
, idx
,
1826 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
1834 /* Clears each of the exact match registers to zero, so they
1835 * don't interfere with normal reception */
1836 static void gfar_clear_exact_match(struct net_device
*dev
)
1839 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
1841 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
1842 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
1845 /* Set the appropriate hash bit for the given addr */
1846 /* The algorithm works like so:
1847 * 1) Take the Destination Address (ie the multicast address), and
1848 * do a CRC on it (little endian), and reverse the bits of the
1850 * 2) Use the 8 most significant bits as a hash into a 256-entry
1851 * table. The table is controlled through 8 32-bit registers:
1852 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1853 * gaddr7. This means that the 3 most significant bits in the
1854 * hash index which gaddr register to use, and the 5 other bits
1855 * indicate which bit (assuming an IBM numbering scheme, which
1856 * for PowerPC (tm) is usually the case) in the register holds
1858 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
1861 struct gfar_private
*priv
= netdev_priv(dev
);
1862 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
1863 int width
= priv
->hash_width
;
1864 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
1865 u8 whichreg
= result
>> (32 - width
+ 5);
1866 u32 value
= (1 << (31-whichbit
));
1868 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
1870 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
1876 /* There are multiple MAC Address register pairs on some controllers
1877 * This function sets the numth pair to a given address
1879 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
1881 struct gfar_private
*priv
= netdev_priv(dev
);
1883 char tmpbuf
[MAC_ADDR_LEN
];
1885 u32 __iomem
*macptr
= &priv
->regs
->macstnaddr1
;
1889 /* Now copy it into the mac registers backwards, cuz */
1890 /* little endian is silly */
1891 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
1892 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
1894 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
1896 tempval
= *((u32
*) (tmpbuf
+ 4));
1898 gfar_write(macptr
+1, tempval
);
1901 /* GFAR error interrupt handler */
1902 static irqreturn_t
gfar_error(int irq
, void *dev_id
)
1904 struct net_device
*dev
= dev_id
;
1905 struct gfar_private
*priv
= netdev_priv(dev
);
1907 /* Save ievent for future reference */
1908 u32 events
= gfar_read(&priv
->regs
->ievent
);
1911 gfar_write(&priv
->regs
->ievent
, IEVENT_ERR_MASK
);
1914 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
1915 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1916 dev
->name
, events
, gfar_read(&priv
->regs
->imask
));
1918 /* Update the error counters */
1919 if (events
& IEVENT_TXE
) {
1920 priv
->stats
.tx_errors
++;
1922 if (events
& IEVENT_LC
)
1923 priv
->stats
.tx_window_errors
++;
1924 if (events
& IEVENT_CRL
)
1925 priv
->stats
.tx_aborted_errors
++;
1926 if (events
& IEVENT_XFUN
) {
1927 if (netif_msg_tx_err(priv
))
1928 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
1929 "packet dropped.\n", dev
->name
);
1930 priv
->stats
.tx_dropped
++;
1931 priv
->extra_stats
.tx_underrun
++;
1933 /* Reactivate the Tx Queues */
1934 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1936 if (netif_msg_tx_err(priv
))
1937 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
1939 if (events
& IEVENT_BSY
) {
1940 priv
->stats
.rx_errors
++;
1941 priv
->extra_stats
.rx_bsy
++;
1943 gfar_receive(irq
, dev_id
);
1945 #ifndef CONFIG_GFAR_NAPI
1946 /* Clear the halt bit in RSTAT */
1947 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1950 if (netif_msg_rx_err(priv
))
1951 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
1952 dev
->name
, gfar_read(&priv
->regs
->rstat
));
1954 if (events
& IEVENT_BABR
) {
1955 priv
->stats
.rx_errors
++;
1956 priv
->extra_stats
.rx_babr
++;
1958 if (netif_msg_rx_err(priv
))
1959 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
1961 if (events
& IEVENT_EBERR
) {
1962 priv
->extra_stats
.eberr
++;
1963 if (netif_msg_rx_err(priv
))
1964 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
1966 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
1967 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
1969 if (events
& IEVENT_BABT
) {
1970 priv
->extra_stats
.tx_babt
++;
1971 if (netif_msg_tx_err(priv
))
1972 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
1977 /* Structure for a device driver */
1978 static struct platform_driver gfar_driver
= {
1979 .probe
= gfar_probe
,
1980 .remove
= gfar_remove
,
1982 .name
= "fsl-gianfar",
1986 static int __init
gfar_init(void)
1988 int err
= gfar_mdio_init();
1993 err
= platform_driver_register(&gfar_driver
);
2001 static void __exit
gfar_exit(void)
2003 platform_driver_unregister(&gfar_driver
);
2007 module_init(gfar_init
);
2008 module_exit(gfar_exit
);