2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
78 #include <linux/of_platform.h>
80 #include <linux/tcp.h>
81 #include <linux/udp.h>
86 #include <asm/uaccess.h>
87 #include <linux/module.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/crc32.h>
90 #include <linux/mii.h>
91 #include <linux/phy.h>
92 #include <linux/phy_fixed.h>
96 #include "gianfar_mii.h"
98 #define TX_TIMEOUT (1*HZ)
99 #undef BRIEF_GFAR_ERRORS
100 #undef VERBOSE_GFAR_ERRORS
102 const char gfar_driver_name
[] = "Gianfar Ethernet";
103 const char gfar_driver_version
[] = "1.3";
105 static int gfar_enet_open(struct net_device
*dev
);
106 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
107 static void gfar_reset_task(struct work_struct
*work
);
108 static void gfar_timeout(struct net_device
*dev
);
109 static int gfar_close(struct net_device
*dev
);
110 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
111 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
112 struct sk_buff
*skb
);
113 static int gfar_set_mac_address(struct net_device
*dev
);
114 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
115 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
116 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
117 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
118 static void adjust_link(struct net_device
*dev
);
119 static void init_registers(struct net_device
*dev
);
120 static int init_phy(struct net_device
*dev
);
121 static int gfar_probe(struct of_device
*ofdev
,
122 const struct of_device_id
*match
);
123 static int gfar_remove(struct of_device
*ofdev
);
124 static void free_skb_resources(struct gfar_private
*priv
);
125 static void gfar_set_multi(struct net_device
*dev
);
126 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
127 static void gfar_configure_serdes(struct net_device
*dev
);
128 static int gfar_poll(struct napi_struct
*napi
, int budget
);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device
*dev
);
132 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
);
133 static int gfar_clean_tx_ring(struct net_device
*dev
);
134 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
136 static void gfar_vlan_rx_register(struct net_device
*netdev
,
137 struct vlan_group
*grp
);
138 void gfar_halt(struct net_device
*dev
);
139 static void gfar_halt_nodisable(struct net_device
*dev
);
140 void gfar_start(struct net_device
*dev
);
141 static void gfar_clear_exact_match(struct net_device
*dev
);
142 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
144 extern const struct ethtool_ops gfar_ethtool_ops
;
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 /* Returns 1 if incoming frames use an FCB */
151 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
153 return priv
->vlgrp
|| priv
->rx_csum_enable
;
156 static int gfar_of_init(struct net_device
*dev
)
158 struct device_node
*phy
, *mdio
;
159 const unsigned int *id
;
162 const void *mac_addr
;
166 struct gfar_private
*priv
= netdev_priv(dev
);
167 struct device_node
*np
= priv
->node
;
168 char bus_name
[MII_BUS_ID_SIZE
];
170 if (!np
|| !of_device_is_available(np
))
173 /* get a pointer to the register memory */
174 addr
= of_translate_address(np
, of_get_address(np
, 0, &size
, NULL
));
175 priv
->regs
= ioremap(addr
, size
);
177 if (priv
->regs
== NULL
)
180 priv
->interruptTransmit
= irq_of_parse_and_map(np
, 0);
182 model
= of_get_property(np
, "model", NULL
);
184 /* If we aren't the FEC we have multiple interrupts */
185 if (model
&& strcasecmp(model
, "FEC")) {
186 priv
->interruptReceive
= irq_of_parse_and_map(np
, 1);
188 priv
->interruptError
= irq_of_parse_and_map(np
, 2);
190 if (priv
->interruptTransmit
< 0 ||
191 priv
->interruptReceive
< 0 ||
192 priv
->interruptError
< 0) {
198 mac_addr
= of_get_mac_address(np
);
200 memcpy(dev
->dev_addr
, mac_addr
, MAC_ADDR_LEN
);
202 if (model
&& !strcasecmp(model
, "TSEC"))
204 FSL_GIANFAR_DEV_HAS_GIGABIT
|
205 FSL_GIANFAR_DEV_HAS_COALESCE
|
206 FSL_GIANFAR_DEV_HAS_RMON
|
207 FSL_GIANFAR_DEV_HAS_MULTI_INTR
;
208 if (model
&& !strcasecmp(model
, "eTSEC"))
210 FSL_GIANFAR_DEV_HAS_GIGABIT
|
211 FSL_GIANFAR_DEV_HAS_COALESCE
|
212 FSL_GIANFAR_DEV_HAS_RMON
|
213 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
214 FSL_GIANFAR_DEV_HAS_PADDING
|
215 FSL_GIANFAR_DEV_HAS_CSUM
|
216 FSL_GIANFAR_DEV_HAS_VLAN
|
217 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
|
218 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
;
220 ctype
= of_get_property(np
, "phy-connection-type", NULL
);
222 /* We only care about rgmii-id. The rest are autodetected */
223 if (ctype
&& !strcmp(ctype
, "rgmii-id"))
224 priv
->interface
= PHY_INTERFACE_MODE_RGMII_ID
;
226 priv
->interface
= PHY_INTERFACE_MODE_MII
;
228 if (of_get_property(np
, "fsl,magic-packet", NULL
))
229 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
;
231 ph
= of_get_property(np
, "phy-handle", NULL
);
235 fixed_link
= (u32
*)of_get_property(np
, "fixed-link", NULL
);
241 snprintf(priv
->phy_bus_id
, sizeof(priv
->phy_bus_id
),
242 PHY_ID_FMT
, "0", fixed_link
[0]);
244 phy
= of_find_node_by_phandle(*ph
);
251 mdio
= of_get_parent(phy
);
253 id
= of_get_property(phy
, "reg", NULL
);
258 gfar_mdio_bus_name(bus_name
, mdio
);
259 snprintf(priv
->phy_bus_id
, sizeof(priv
->phy_bus_id
), "%s:%02x",
263 /* Find the TBI PHY. If it's not there, we don't support SGMII */
264 ph
= of_get_property(np
, "tbi-handle", NULL
);
266 struct device_node
*tbi
= of_find_node_by_phandle(*ph
);
267 struct of_device
*ofdev
;
273 mdio
= of_get_parent(tbi
);
277 ofdev
= of_find_device_by_node(mdio
);
281 id
= of_get_property(tbi
, "reg", NULL
);
287 bus
= dev_get_drvdata(&ofdev
->dev
);
289 priv
->tbiphy
= bus
->phy_map
[*id
];
299 /* Ioctl MII Interface */
300 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
302 struct gfar_private
*priv
= netdev_priv(dev
);
304 if (!netif_running(dev
))
310 return phy_mii_ioctl(priv
->phydev
, if_mii(rq
), cmd
);
313 /* Set up the ethernet device structure, private data,
314 * and anything else we need before we start */
315 static int gfar_probe(struct of_device
*ofdev
,
316 const struct of_device_id
*match
)
319 struct net_device
*dev
= NULL
;
320 struct gfar_private
*priv
= NULL
;
321 DECLARE_MAC_BUF(mac
);
325 /* Create an ethernet device instance */
326 dev
= alloc_etherdev(sizeof (*priv
));
331 priv
= netdev_priv(dev
);
333 priv
->node
= ofdev
->node
;
335 err
= gfar_of_init(dev
);
340 spin_lock_init(&priv
->txlock
);
341 spin_lock_init(&priv
->rxlock
);
342 spin_lock_init(&priv
->bflock
);
343 INIT_WORK(&priv
->reset_task
, gfar_reset_task
);
345 dev_set_drvdata(&ofdev
->dev
, priv
);
347 /* Stop the DMA engine now, in case it was running before */
348 /* (The firmware could have used it, and left it running). */
351 /* Reset MAC layer */
352 gfar_write(&priv
->regs
->maccfg1
, MACCFG1_SOFT_RESET
);
354 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
355 gfar_write(&priv
->regs
->maccfg1
, tempval
);
357 /* Initialize MACCFG2. */
358 gfar_write(&priv
->regs
->maccfg2
, MACCFG2_INIT_SETTINGS
);
360 /* Initialize ECNTRL */
361 gfar_write(&priv
->regs
->ecntrl
, ECNTRL_INIT_SETTINGS
);
363 /* Set the dev->base_addr to the gfar reg region */
364 dev
->base_addr
= (unsigned long) (priv
->regs
);
366 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
368 /* Fill in the dev structure */
369 dev
->open
= gfar_enet_open
;
370 dev
->hard_start_xmit
= gfar_start_xmit
;
371 dev
->tx_timeout
= gfar_timeout
;
372 dev
->watchdog_timeo
= TX_TIMEOUT
;
373 netif_napi_add(dev
, &priv
->napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
374 #ifdef CONFIG_NET_POLL_CONTROLLER
375 dev
->poll_controller
= gfar_netpoll
;
377 dev
->stop
= gfar_close
;
378 dev
->change_mtu
= gfar_change_mtu
;
380 dev
->set_multicast_list
= gfar_set_multi
;
382 dev
->ethtool_ops
= &gfar_ethtool_ops
;
383 dev
->do_ioctl
= gfar_ioctl
;
385 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
386 priv
->rx_csum_enable
= 1;
387 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_HIGHDMA
;
389 priv
->rx_csum_enable
= 0;
393 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
394 dev
->vlan_rx_register
= gfar_vlan_rx_register
;
396 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
399 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
400 priv
->extended_hash
= 1;
401 priv
->hash_width
= 9;
403 priv
->hash_regs
[0] = &priv
->regs
->igaddr0
;
404 priv
->hash_regs
[1] = &priv
->regs
->igaddr1
;
405 priv
->hash_regs
[2] = &priv
->regs
->igaddr2
;
406 priv
->hash_regs
[3] = &priv
->regs
->igaddr3
;
407 priv
->hash_regs
[4] = &priv
->regs
->igaddr4
;
408 priv
->hash_regs
[5] = &priv
->regs
->igaddr5
;
409 priv
->hash_regs
[6] = &priv
->regs
->igaddr6
;
410 priv
->hash_regs
[7] = &priv
->regs
->igaddr7
;
411 priv
->hash_regs
[8] = &priv
->regs
->gaddr0
;
412 priv
->hash_regs
[9] = &priv
->regs
->gaddr1
;
413 priv
->hash_regs
[10] = &priv
->regs
->gaddr2
;
414 priv
->hash_regs
[11] = &priv
->regs
->gaddr3
;
415 priv
->hash_regs
[12] = &priv
->regs
->gaddr4
;
416 priv
->hash_regs
[13] = &priv
->regs
->gaddr5
;
417 priv
->hash_regs
[14] = &priv
->regs
->gaddr6
;
418 priv
->hash_regs
[15] = &priv
->regs
->gaddr7
;
421 priv
->extended_hash
= 0;
422 priv
->hash_width
= 8;
424 priv
->hash_regs
[0] = &priv
->regs
->gaddr0
;
425 priv
->hash_regs
[1] = &priv
->regs
->gaddr1
;
426 priv
->hash_regs
[2] = &priv
->regs
->gaddr2
;
427 priv
->hash_regs
[3] = &priv
->regs
->gaddr3
;
428 priv
->hash_regs
[4] = &priv
->regs
->gaddr4
;
429 priv
->hash_regs
[5] = &priv
->regs
->gaddr5
;
430 priv
->hash_regs
[6] = &priv
->regs
->gaddr6
;
431 priv
->hash_regs
[7] = &priv
->regs
->gaddr7
;
434 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
435 priv
->padding
= DEFAULT_PADDING
;
439 if (dev
->features
& NETIF_F_IP_CSUM
)
440 dev
->hard_header_len
+= GMAC_FCB_LEN
;
442 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
443 priv
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
444 priv
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
445 priv
->num_txbdfree
= DEFAULT_TX_RING_SIZE
;
447 priv
->txcoalescing
= DEFAULT_TX_COALESCE
;
448 priv
->txic
= DEFAULT_TXIC
;
449 priv
->rxcoalescing
= DEFAULT_RX_COALESCE
;
450 priv
->rxic
= DEFAULT_RXIC
;
452 /* Enable most messages by default */
453 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
455 /* Carrier starts down, phylib will bring it up */
456 netif_carrier_off(dev
);
458 err
= register_netdev(dev
);
461 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
466 /* fill out IRQ number and name fields */
467 len_devname
= strlen(dev
->name
);
468 strncpy(&priv
->int_name_tx
[0], dev
->name
, len_devname
);
469 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
470 strncpy(&priv
->int_name_tx
[len_devname
],
471 "_tx", sizeof("_tx") + 1);
473 strncpy(&priv
->int_name_rx
[0], dev
->name
, len_devname
);
474 strncpy(&priv
->int_name_rx
[len_devname
],
475 "_rx", sizeof("_rx") + 1);
477 strncpy(&priv
->int_name_er
[0], dev
->name
, len_devname
);
478 strncpy(&priv
->int_name_er
[len_devname
],
479 "_er", sizeof("_er") + 1);
481 priv
->int_name_tx
[len_devname
] = '\0';
483 /* Create all the sysfs files */
484 gfar_init_sysfs(dev
);
486 /* Print out the device info */
487 printk(KERN_INFO DEVICE_NAME
"%pM\n", dev
->name
, dev
->dev_addr
);
489 /* Even more device info helps when determining which kernel */
490 /* provided which set of benchmarks. */
491 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
492 printk(KERN_INFO
"%s: %d/%d RX/TX BD ring size\n",
493 dev
->name
, priv
->rx_ring_size
, priv
->tx_ring_size
);
504 static int gfar_remove(struct of_device
*ofdev
)
506 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
508 dev_set_drvdata(&ofdev
->dev
, NULL
);
511 free_netdev(priv
->dev
);
517 static int gfar_suspend(struct of_device
*ofdev
, pm_message_t state
)
519 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
520 struct net_device
*dev
= priv
->dev
;
524 int magic_packet
= priv
->wol_en
&&
525 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
527 netif_device_detach(dev
);
529 if (netif_running(dev
)) {
530 spin_lock_irqsave(&priv
->txlock
, flags
);
531 spin_lock(&priv
->rxlock
);
533 gfar_halt_nodisable(dev
);
535 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
536 tempval
= gfar_read(&priv
->regs
->maccfg1
);
538 tempval
&= ~MACCFG1_TX_EN
;
541 tempval
&= ~MACCFG1_RX_EN
;
543 gfar_write(&priv
->regs
->maccfg1
, tempval
);
545 spin_unlock(&priv
->rxlock
);
546 spin_unlock_irqrestore(&priv
->txlock
, flags
);
548 napi_disable(&priv
->napi
);
551 /* Enable interrupt on Magic Packet */
552 gfar_write(&priv
->regs
->imask
, IMASK_MAG
);
554 /* Enable Magic Packet mode */
555 tempval
= gfar_read(&priv
->regs
->maccfg2
);
556 tempval
|= MACCFG2_MPEN
;
557 gfar_write(&priv
->regs
->maccfg2
, tempval
);
559 phy_stop(priv
->phydev
);
566 static int gfar_resume(struct of_device
*ofdev
)
568 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
569 struct net_device
*dev
= priv
->dev
;
572 int magic_packet
= priv
->wol_en
&&
573 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
575 if (!netif_running(dev
)) {
576 netif_device_attach(dev
);
580 if (!magic_packet
&& priv
->phydev
)
581 phy_start(priv
->phydev
);
583 /* Disable Magic Packet mode, in case something
587 spin_lock_irqsave(&priv
->txlock
, flags
);
588 spin_lock(&priv
->rxlock
);
590 tempval
= gfar_read(&priv
->regs
->maccfg2
);
591 tempval
&= ~MACCFG2_MPEN
;
592 gfar_write(&priv
->regs
->maccfg2
, tempval
);
596 spin_unlock(&priv
->rxlock
);
597 spin_unlock_irqrestore(&priv
->txlock
, flags
);
599 netif_device_attach(dev
);
601 napi_enable(&priv
->napi
);
606 #define gfar_suspend NULL
607 #define gfar_resume NULL
610 /* Reads the controller's registers to determine what interface
611 * connects it to the PHY.
613 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
615 struct gfar_private
*priv
= netdev_priv(dev
);
616 u32 ecntrl
= gfar_read(&priv
->regs
->ecntrl
);
618 if (ecntrl
& ECNTRL_SGMII_MODE
)
619 return PHY_INTERFACE_MODE_SGMII
;
621 if (ecntrl
& ECNTRL_TBI_MODE
) {
622 if (ecntrl
& ECNTRL_REDUCED_MODE
)
623 return PHY_INTERFACE_MODE_RTBI
;
625 return PHY_INTERFACE_MODE_TBI
;
628 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
629 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
630 return PHY_INTERFACE_MODE_RMII
;
632 phy_interface_t interface
= priv
->interface
;
635 * This isn't autodetected right now, so it must
636 * be set by the device tree or platform code.
638 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
639 return PHY_INTERFACE_MODE_RGMII_ID
;
641 return PHY_INTERFACE_MODE_RGMII
;
645 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
646 return PHY_INTERFACE_MODE_GMII
;
648 return PHY_INTERFACE_MODE_MII
;
652 /* Initializes driver's PHY state, and attaches to the PHY.
653 * Returns 0 on success.
655 static int init_phy(struct net_device
*dev
)
657 struct gfar_private
*priv
= netdev_priv(dev
);
658 uint gigabit_support
=
659 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
660 SUPPORTED_1000baseT_Full
: 0;
661 struct phy_device
*phydev
;
662 phy_interface_t interface
;
666 priv
->oldduplex
= -1;
668 interface
= gfar_get_interface(dev
);
670 phydev
= phy_connect(dev
, priv
->phy_bus_id
, &adjust_link
, 0, interface
);
672 if (interface
== PHY_INTERFACE_MODE_SGMII
)
673 gfar_configure_serdes(dev
);
675 if (IS_ERR(phydev
)) {
676 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
677 return PTR_ERR(phydev
);
680 /* Remove any features not supported by the controller */
681 phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
682 phydev
->advertising
= phydev
->supported
;
684 priv
->phydev
= phydev
;
690 * Initialize TBI PHY interface for communicating with the
691 * SERDES lynx PHY on the chip. We communicate with this PHY
692 * through the MDIO bus on each controller, treating it as a
693 * "normal" PHY at the address found in the TBIPA register. We assume
694 * that the TBIPA register is valid. Either the MDIO bus code will set
695 * it to a value that doesn't conflict with other PHYs on the bus, or the
696 * value doesn't matter, as there are no other PHYs on the bus.
698 static void gfar_configure_serdes(struct net_device
*dev
)
700 struct gfar_private
*priv
= netdev_priv(dev
);
703 printk(KERN_WARNING
"SGMII mode requires that the device "
704 "tree specify a tbi-handle\n");
709 * If the link is already up, we must already be ok, and don't need to
710 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
711 * everything for us? Resetting it takes the link down and requires
712 * several seconds for it to come back.
714 if (phy_read(priv
->tbiphy
, MII_BMSR
) & BMSR_LSTATUS
)
717 /* Single clk mode, mii mode off(for serdes communication) */
718 phy_write(priv
->tbiphy
, MII_TBICON
, TBICON_CLK_SELECT
);
720 phy_write(priv
->tbiphy
, MII_ADVERTISE
,
721 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
722 ADVERTISE_1000XPSE_ASYM
);
724 phy_write(priv
->tbiphy
, MII_BMCR
, BMCR_ANENABLE
|
725 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
728 static void init_registers(struct net_device
*dev
)
730 struct gfar_private
*priv
= netdev_priv(dev
);
733 gfar_write(&priv
->regs
->ievent
, IEVENT_INIT_CLEAR
);
735 /* Initialize IMASK */
736 gfar_write(&priv
->regs
->imask
, IMASK_INIT_CLEAR
);
738 /* Init hash registers to zero */
739 gfar_write(&priv
->regs
->igaddr0
, 0);
740 gfar_write(&priv
->regs
->igaddr1
, 0);
741 gfar_write(&priv
->regs
->igaddr2
, 0);
742 gfar_write(&priv
->regs
->igaddr3
, 0);
743 gfar_write(&priv
->regs
->igaddr4
, 0);
744 gfar_write(&priv
->regs
->igaddr5
, 0);
745 gfar_write(&priv
->regs
->igaddr6
, 0);
746 gfar_write(&priv
->regs
->igaddr7
, 0);
748 gfar_write(&priv
->regs
->gaddr0
, 0);
749 gfar_write(&priv
->regs
->gaddr1
, 0);
750 gfar_write(&priv
->regs
->gaddr2
, 0);
751 gfar_write(&priv
->regs
->gaddr3
, 0);
752 gfar_write(&priv
->regs
->gaddr4
, 0);
753 gfar_write(&priv
->regs
->gaddr5
, 0);
754 gfar_write(&priv
->regs
->gaddr6
, 0);
755 gfar_write(&priv
->regs
->gaddr7
, 0);
757 /* Zero out the rmon mib registers if it has them */
758 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
759 memset_io(&(priv
->regs
->rmon
), 0, sizeof (struct rmon_mib
));
761 /* Mask off the CAM interrupts */
762 gfar_write(&priv
->regs
->rmon
.cam1
, 0xffffffff);
763 gfar_write(&priv
->regs
->rmon
.cam2
, 0xffffffff);
766 /* Initialize the max receive buffer length */
767 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
769 /* Initialize the Minimum Frame Length Register */
770 gfar_write(&priv
->regs
->minflr
, MINFLR_INIT_SETTINGS
);
774 /* Halt the receive and transmit queues */
775 static void gfar_halt_nodisable(struct net_device
*dev
)
777 struct gfar_private
*priv
= netdev_priv(dev
);
778 struct gfar __iomem
*regs
= priv
->regs
;
781 /* Mask all interrupts */
782 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
784 /* Clear all interrupts */
785 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
787 /* Stop the DMA, and wait for it to stop */
788 tempval
= gfar_read(&priv
->regs
->dmactrl
);
789 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
790 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
791 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
792 gfar_write(&priv
->regs
->dmactrl
, tempval
);
794 while (!(gfar_read(&priv
->regs
->ievent
) &
795 (IEVENT_GRSC
| IEVENT_GTSC
)))
800 /* Halt the receive and transmit queues */
801 void gfar_halt(struct net_device
*dev
)
803 struct gfar_private
*priv
= netdev_priv(dev
);
804 struct gfar __iomem
*regs
= priv
->regs
;
807 gfar_halt_nodisable(dev
);
809 /* Disable Rx and Tx */
810 tempval
= gfar_read(®s
->maccfg1
);
811 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
812 gfar_write(®s
->maccfg1
, tempval
);
815 void stop_gfar(struct net_device
*dev
)
817 struct gfar_private
*priv
= netdev_priv(dev
);
818 struct gfar __iomem
*regs
= priv
->regs
;
821 phy_stop(priv
->phydev
);
824 spin_lock_irqsave(&priv
->txlock
, flags
);
825 spin_lock(&priv
->rxlock
);
829 spin_unlock(&priv
->rxlock
);
830 spin_unlock_irqrestore(&priv
->txlock
, flags
);
833 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
834 free_irq(priv
->interruptError
, dev
);
835 free_irq(priv
->interruptTransmit
, dev
);
836 free_irq(priv
->interruptReceive
, dev
);
838 free_irq(priv
->interruptTransmit
, dev
);
841 free_skb_resources(priv
);
843 dma_free_coherent(&dev
->dev
,
844 sizeof(struct txbd8
)*priv
->tx_ring_size
845 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
847 gfar_read(®s
->tbase0
));
850 /* If there are any tx skbs or rx skbs still around, free them.
851 * Then free tx_skbuff and rx_skbuff */
852 static void free_skb_resources(struct gfar_private
*priv
)
858 /* Go through all the buffer descriptors and free their data buffers */
859 txbdp
= priv
->tx_bd_base
;
861 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
862 if (!priv
->tx_skbuff
[i
])
865 dma_unmap_single(&priv
->dev
->dev
, txbdp
->bufPtr
,
866 txbdp
->length
, DMA_TO_DEVICE
);
868 for (j
= 0; j
< skb_shinfo(priv
->tx_skbuff
[i
])->nr_frags
; j
++) {
870 dma_unmap_page(&priv
->dev
->dev
, txbdp
->bufPtr
,
871 txbdp
->length
, DMA_TO_DEVICE
);
874 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
875 priv
->tx_skbuff
[i
] = NULL
;
878 kfree(priv
->tx_skbuff
);
880 rxbdp
= priv
->rx_bd_base
;
882 /* rx_skbuff is not guaranteed to be allocated, so only
883 * free it and its contents if it is allocated */
884 if(priv
->rx_skbuff
!= NULL
) {
885 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
886 if (priv
->rx_skbuff
[i
]) {
887 dma_unmap_single(&priv
->dev
->dev
, rxbdp
->bufPtr
,
888 priv
->rx_buffer_size
,
891 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
892 priv
->rx_skbuff
[i
] = NULL
;
901 kfree(priv
->rx_skbuff
);
905 void gfar_start(struct net_device
*dev
)
907 struct gfar_private
*priv
= netdev_priv(dev
);
908 struct gfar __iomem
*regs
= priv
->regs
;
911 /* Enable Rx and Tx in MACCFG1 */
912 tempval
= gfar_read(®s
->maccfg1
);
913 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
914 gfar_write(®s
->maccfg1
, tempval
);
916 /* Initialize DMACTRL to have WWR and WOP */
917 tempval
= gfar_read(&priv
->regs
->dmactrl
);
918 tempval
|= DMACTRL_INIT_SETTINGS
;
919 gfar_write(&priv
->regs
->dmactrl
, tempval
);
921 /* Make sure we aren't stopped */
922 tempval
= gfar_read(&priv
->regs
->dmactrl
);
923 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
924 gfar_write(&priv
->regs
->dmactrl
, tempval
);
926 /* Clear THLT/RHLT, so that the DMA starts polling now */
927 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
);
928 gfar_write(®s
->rstat
, RSTAT_CLEAR_RHALT
);
930 /* Unmask the interrupts we look for */
931 gfar_write(®s
->imask
, IMASK_DEFAULT
);
933 dev
->trans_start
= jiffies
;
936 /* Bring the controller up and running */
937 int startup_gfar(struct net_device
*dev
)
944 struct gfar_private
*priv
= netdev_priv(dev
);
945 struct gfar __iomem
*regs
= priv
->regs
;
950 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
952 /* Allocate memory for the buffer descriptors */
953 vaddr
= (unsigned long) dma_alloc_coherent(&dev
->dev
,
954 sizeof (struct txbd8
) * priv
->tx_ring_size
+
955 sizeof (struct rxbd8
) * priv
->rx_ring_size
,
959 if (netif_msg_ifup(priv
))
960 printk(KERN_ERR
"%s: Could not allocate buffer descriptors!\n",
965 priv
->tx_bd_base
= (struct txbd8
*) vaddr
;
967 /* enet DMA only understands physical addresses */
968 gfar_write(®s
->tbase0
, addr
);
970 /* Start the rx descriptor ring where the tx ring leaves off */
971 addr
= addr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
972 vaddr
= vaddr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
973 priv
->rx_bd_base
= (struct rxbd8
*) vaddr
;
974 gfar_write(®s
->rbase0
, addr
);
976 /* Setup the skbuff rings */
978 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
979 priv
->tx_ring_size
, GFP_KERNEL
);
981 if (NULL
== priv
->tx_skbuff
) {
982 if (netif_msg_ifup(priv
))
983 printk(KERN_ERR
"%s: Could not allocate tx_skbuff\n",
989 for (i
= 0; i
< priv
->tx_ring_size
; i
++)
990 priv
->tx_skbuff
[i
] = NULL
;
993 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
994 priv
->rx_ring_size
, GFP_KERNEL
);
996 if (NULL
== priv
->rx_skbuff
) {
997 if (netif_msg_ifup(priv
))
998 printk(KERN_ERR
"%s: Could not allocate rx_skbuff\n",
1004 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
1005 priv
->rx_skbuff
[i
] = NULL
;
1007 /* Initialize some variables in our dev structure */
1008 priv
->num_txbdfree
= priv
->tx_ring_size
;
1009 priv
->dirty_tx
= priv
->cur_tx
= priv
->tx_bd_base
;
1010 priv
->cur_rx
= priv
->rx_bd_base
;
1011 priv
->skb_curtx
= priv
->skb_dirtytx
= 0;
1012 priv
->skb_currx
= 0;
1014 /* Initialize Transmit Descriptor Ring */
1015 txbdp
= priv
->tx_bd_base
;
1016 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
1022 /* Set the last descriptor in the ring to indicate wrap */
1024 txbdp
->status
|= TXBD_WRAP
;
1026 rxbdp
= priv
->rx_bd_base
;
1027 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
1028 struct sk_buff
*skb
;
1030 skb
= gfar_new_skb(dev
);
1033 printk(KERN_ERR
"%s: Can't allocate RX buffers\n",
1036 goto err_rxalloc_fail
;
1039 priv
->rx_skbuff
[i
] = skb
;
1041 gfar_new_rxbdp(dev
, rxbdp
, skb
);
1046 /* Set the last descriptor in the ring to wrap */
1048 rxbdp
->status
|= RXBD_WRAP
;
1050 /* If the device has multiple interrupts, register for
1051 * them. Otherwise, only register for the one */
1052 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1053 /* Install our interrupt handlers for Error,
1054 * Transmit, and Receive */
1055 if (request_irq(priv
->interruptError
, gfar_error
,
1056 0, priv
->int_name_er
, dev
) < 0) {
1057 if (netif_msg_intr(priv
))
1058 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1059 dev
->name
, priv
->interruptError
);
1065 if (request_irq(priv
->interruptTransmit
, gfar_transmit
,
1066 0, priv
->int_name_tx
, dev
) < 0) {
1067 if (netif_msg_intr(priv
))
1068 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1069 dev
->name
, priv
->interruptTransmit
);
1076 if (request_irq(priv
->interruptReceive
, gfar_receive
,
1077 0, priv
->int_name_rx
, dev
) < 0) {
1078 if (netif_msg_intr(priv
))
1079 printk(KERN_ERR
"%s: Can't get IRQ %d (receive0)\n",
1080 dev
->name
, priv
->interruptReceive
);
1086 if (request_irq(priv
->interruptTransmit
, gfar_interrupt
,
1087 0, priv
->int_name_tx
, dev
) < 0) {
1088 if (netif_msg_intr(priv
))
1089 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1090 dev
->name
, priv
->interruptTransmit
);
1097 phy_start(priv
->phydev
);
1099 /* Configure the coalescing support */
1100 gfar_write(®s
->txic
, 0);
1101 if (priv
->txcoalescing
)
1102 gfar_write(®s
->txic
, priv
->txic
);
1104 gfar_write(®s
->rxic
, 0);
1105 if (priv
->rxcoalescing
)
1106 gfar_write(®s
->rxic
, priv
->rxic
);
1108 if (priv
->rx_csum_enable
)
1109 rctrl
|= RCTRL_CHECKSUMMING
;
1111 if (priv
->extended_hash
) {
1112 rctrl
|= RCTRL_EXTHASH
;
1114 gfar_clear_exact_match(dev
);
1115 rctrl
|= RCTRL_EMEN
;
1118 if (priv
->padding
) {
1119 rctrl
&= ~RCTRL_PAL_MASK
;
1120 rctrl
|= RCTRL_PADDING(priv
->padding
);
1123 /* Init rctrl based on our settings */
1124 gfar_write(&priv
->regs
->rctrl
, rctrl
);
1126 if (dev
->features
& NETIF_F_IP_CSUM
)
1127 gfar_write(&priv
->regs
->tctrl
, TCTRL_INIT_CSUM
);
1129 /* Set the extraction length and index */
1130 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
1131 ATTRELI_EI(priv
->rx_stash_index
);
1133 gfar_write(&priv
->regs
->attreli
, attrs
);
1135 /* Start with defaults, and add stashing or locking
1136 * depending on the approprate variables */
1137 attrs
= ATTR_INIT_SETTINGS
;
1139 if (priv
->bd_stash_en
)
1140 attrs
|= ATTR_BDSTASH
;
1142 if (priv
->rx_stash_size
!= 0)
1143 attrs
|= ATTR_BUFSTASH
;
1145 gfar_write(&priv
->regs
->attr
, attrs
);
1147 gfar_write(&priv
->regs
->fifo_tx_thr
, priv
->fifo_threshold
);
1148 gfar_write(&priv
->regs
->fifo_tx_starve
, priv
->fifo_starve
);
1149 gfar_write(&priv
->regs
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
1151 /* Start the controller */
1157 free_irq(priv
->interruptTransmit
, dev
);
1159 free_irq(priv
->interruptError
, dev
);
1163 free_skb_resources(priv
);
1165 dma_free_coherent(&dev
->dev
,
1166 sizeof(struct txbd8
)*priv
->tx_ring_size
1167 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
1169 gfar_read(®s
->tbase0
));
1174 /* Called when something needs to use the ethernet device */
1175 /* Returns 0 for success. */
1176 static int gfar_enet_open(struct net_device
*dev
)
1178 struct gfar_private
*priv
= netdev_priv(dev
);
1181 napi_enable(&priv
->napi
);
1183 /* Initialize a bunch of registers */
1184 init_registers(dev
);
1186 gfar_set_mac_address(dev
);
1188 err
= init_phy(dev
);
1191 napi_disable(&priv
->napi
);
1195 err
= startup_gfar(dev
);
1197 napi_disable(&priv
->napi
);
1201 netif_start_queue(dev
);
1206 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
)
1208 struct txfcb
*fcb
= (struct txfcb
*)skb_push (skb
, GMAC_FCB_LEN
);
1210 cacheable_memzero(fcb
, GMAC_FCB_LEN
);
1215 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
1219 /* If we're here, it's a IP packet with a TCP or UDP
1220 * payload. We set it to checksum, using a pseudo-header
1223 flags
= TXFCB_DEFAULT
;
1225 /* Tell the controller what the protocol is */
1226 /* And provide the already calculated phcs */
1227 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
1229 fcb
->phcs
= udp_hdr(skb
)->check
;
1231 fcb
->phcs
= tcp_hdr(skb
)->check
;
1233 /* l3os is the distance between the start of the
1234 * frame (skb->data) and the start of the IP hdr.
1235 * l4os is the distance between the start of the
1236 * l3 hdr and the l4 hdr */
1237 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
1238 fcb
->l4os
= skb_network_header_len(skb
);
1243 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
1245 fcb
->flags
|= TXFCB_VLN
;
1246 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1249 static inline struct txbd8
*skip_txbd(struct txbd8
*bdp
, int stride
,
1250 struct txbd8
*base
, int ring_size
)
1252 struct txbd8
*new_bd
= bdp
+ stride
;
1254 return (new_bd
>= (base
+ ring_size
)) ? (new_bd
- ring_size
) : new_bd
;
1257 static inline struct txbd8
*next_txbd(struct txbd8
*bdp
, struct txbd8
*base
,
1260 return skip_txbd(bdp
, 1, base
, ring_size
);
1263 /* This is called by the kernel when a frame is ready for transmission. */
1264 /* It is pointed to by the dev->hard_start_xmit function pointer */
1265 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1267 struct gfar_private
*priv
= netdev_priv(dev
);
1268 struct txfcb
*fcb
= NULL
;
1269 struct txbd8
*txbdp
, *txbdp_start
, *base
;
1273 unsigned long flags
;
1274 unsigned int nr_frags
, length
;
1276 base
= priv
->tx_bd_base
;
1278 /* total number of fragments in the SKB */
1279 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1281 spin_lock_irqsave(&priv
->txlock
, flags
);
1283 /* check if there is space to queue this packet */
1284 if (nr_frags
> priv
->num_txbdfree
) {
1285 /* no space, stop the queue */
1286 netif_stop_queue(dev
);
1287 dev
->stats
.tx_fifo_errors
++;
1288 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1289 return NETDEV_TX_BUSY
;
1292 /* Update transmit stats */
1293 dev
->stats
.tx_bytes
+= skb
->len
;
1295 txbdp
= txbdp_start
= priv
->cur_tx
;
1297 if (nr_frags
== 0) {
1298 lstatus
= txbdp
->lstatus
| BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
1300 /* Place the fragment addresses and lengths into the TxBDs */
1301 for (i
= 0; i
< nr_frags
; i
++) {
1302 /* Point at the next BD, wrapping as needed */
1303 txbdp
= next_txbd(txbdp
, base
, priv
->tx_ring_size
);
1305 length
= skb_shinfo(skb
)->frags
[i
].size
;
1307 lstatus
= txbdp
->lstatus
| length
|
1308 BD_LFLAG(TXBD_READY
);
1310 /* Handle the last BD specially */
1311 if (i
== nr_frags
- 1)
1312 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
1314 bufaddr
= dma_map_page(&dev
->dev
,
1315 skb_shinfo(skb
)->frags
[i
].page
,
1316 skb_shinfo(skb
)->frags
[i
].page_offset
,
1320 /* set the TxBD length and buffer pointer */
1321 txbdp
->bufPtr
= bufaddr
;
1322 txbdp
->lstatus
= lstatus
;
1325 lstatus
= txbdp_start
->lstatus
;
1328 /* Set up checksumming */
1329 if (CHECKSUM_PARTIAL
== skb
->ip_summed
) {
1330 fcb
= gfar_add_fcb(skb
);
1331 lstatus
|= BD_LFLAG(TXBD_TOE
);
1332 gfar_tx_checksum(skb
, fcb
);
1335 if (priv
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1336 if (unlikely(NULL
== fcb
)) {
1337 fcb
= gfar_add_fcb(skb
);
1338 lstatus
|= BD_LFLAG(TXBD_TOE
);
1341 gfar_tx_vlan(skb
, fcb
);
1344 /* setup the TxBD length and buffer pointer for the first BD */
1345 priv
->tx_skbuff
[priv
->skb_curtx
] = skb
;
1346 txbdp_start
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1347 skb_headlen(skb
), DMA_TO_DEVICE
);
1349 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | skb_headlen(skb
);
1352 * The powerpc-specific eieio() is used, as wmb() has too strong
1353 * semantics (it requires synchronization between cacheable and
1354 * uncacheable mappings, which eieio doesn't provide and which we
1355 * don't need), thus requiring a more expensive sync instruction. At
1356 * some point, the set of architecture-independent barrier functions
1357 * should be expanded to include weaker barriers.
1361 txbdp_start
->lstatus
= lstatus
;
1363 /* Update the current skb pointer to the next entry we will use
1364 * (wrapping if necessary) */
1365 priv
->skb_curtx
= (priv
->skb_curtx
+ 1) &
1366 TX_RING_MOD_MASK(priv
->tx_ring_size
);
1368 priv
->cur_tx
= next_txbd(txbdp
, base
, priv
->tx_ring_size
);
1370 /* reduce TxBD free count */
1371 priv
->num_txbdfree
-= (nr_frags
+ 1);
1373 dev
->trans_start
= jiffies
;
1375 /* If the next BD still needs to be cleaned up, then the bds
1376 are full. We need to tell the kernel to stop sending us stuff. */
1377 if (!priv
->num_txbdfree
) {
1378 netif_stop_queue(dev
);
1380 dev
->stats
.tx_fifo_errors
++;
1383 /* Tell the DMA to go go go */
1384 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1387 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1392 /* Stops the kernel queue, and halts the controller */
1393 static int gfar_close(struct net_device
*dev
)
1395 struct gfar_private
*priv
= netdev_priv(dev
);
1397 napi_disable(&priv
->napi
);
1399 cancel_work_sync(&priv
->reset_task
);
1402 /* Disconnect from the PHY */
1403 phy_disconnect(priv
->phydev
);
1404 priv
->phydev
= NULL
;
1406 netif_stop_queue(dev
);
1411 /* Changes the mac address if the controller is not running. */
1412 static int gfar_set_mac_address(struct net_device
*dev
)
1414 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
1420 /* Enables and disables VLAN insertion/extraction */
1421 static void gfar_vlan_rx_register(struct net_device
*dev
,
1422 struct vlan_group
*grp
)
1424 struct gfar_private
*priv
= netdev_priv(dev
);
1425 unsigned long flags
;
1426 struct vlan_group
*old_grp
;
1429 spin_lock_irqsave(&priv
->rxlock
, flags
);
1431 old_grp
= priv
->vlgrp
;
1437 /* Enable VLAN tag insertion */
1438 tempval
= gfar_read(&priv
->regs
->tctrl
);
1439 tempval
|= TCTRL_VLINS
;
1441 gfar_write(&priv
->regs
->tctrl
, tempval
);
1443 /* Enable VLAN tag extraction */
1444 tempval
= gfar_read(&priv
->regs
->rctrl
);
1445 tempval
|= RCTRL_VLEX
;
1446 tempval
|= (RCTRL_VLEX
| RCTRL_PRSDEP_INIT
);
1447 gfar_write(&priv
->regs
->rctrl
, tempval
);
1449 /* Disable VLAN tag insertion */
1450 tempval
= gfar_read(&priv
->regs
->tctrl
);
1451 tempval
&= ~TCTRL_VLINS
;
1452 gfar_write(&priv
->regs
->tctrl
, tempval
);
1454 /* Disable VLAN tag extraction */
1455 tempval
= gfar_read(&priv
->regs
->rctrl
);
1456 tempval
&= ~RCTRL_VLEX
;
1457 /* If parse is no longer required, then disable parser */
1458 if (tempval
& RCTRL_REQ_PARSER
)
1459 tempval
|= RCTRL_PRSDEP_INIT
;
1461 tempval
&= ~RCTRL_PRSDEP_INIT
;
1462 gfar_write(&priv
->regs
->rctrl
, tempval
);
1465 gfar_change_mtu(dev
, dev
->mtu
);
1467 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1470 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
1472 int tempsize
, tempval
;
1473 struct gfar_private
*priv
= netdev_priv(dev
);
1474 int oldsize
= priv
->rx_buffer_size
;
1475 int frame_size
= new_mtu
+ ETH_HLEN
;
1478 frame_size
+= VLAN_HLEN
;
1480 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
1481 if (netif_msg_drv(priv
))
1482 printk(KERN_ERR
"%s: Invalid MTU setting\n",
1487 if (gfar_uses_fcb(priv
))
1488 frame_size
+= GMAC_FCB_LEN
;
1490 frame_size
+= priv
->padding
;
1493 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
1494 INCREMENTAL_BUFFER_SIZE
;
1496 /* Only stop and start the controller if it isn't already
1497 * stopped, and we changed something */
1498 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1501 priv
->rx_buffer_size
= tempsize
;
1505 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
1506 gfar_write(&priv
->regs
->maxfrm
, priv
->rx_buffer_size
);
1508 /* If the mtu is larger than the max size for standard
1509 * ethernet frames (ie, a jumbo frame), then set maccfg2
1510 * to allow huge frames, and to check the length */
1511 tempval
= gfar_read(&priv
->regs
->maccfg2
);
1513 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
1514 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1516 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1518 gfar_write(&priv
->regs
->maccfg2
, tempval
);
1520 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1526 /* gfar_reset_task gets scheduled when a packet has not been
1527 * transmitted after a set amount of time.
1528 * For now, assume that clearing out all the structures, and
1529 * starting over will fix the problem.
1531 static void gfar_reset_task(struct work_struct
*work
)
1533 struct gfar_private
*priv
= container_of(work
, struct gfar_private
,
1535 struct net_device
*dev
= priv
->dev
;
1537 if (dev
->flags
& IFF_UP
) {
1542 netif_tx_schedule_all(dev
);
1545 static void gfar_timeout(struct net_device
*dev
)
1547 struct gfar_private
*priv
= netdev_priv(dev
);
1549 dev
->stats
.tx_errors
++;
1550 schedule_work(&priv
->reset_task
);
1553 /* Interrupt Handler for Transmit complete */
1554 static int gfar_clean_tx_ring(struct net_device
*dev
)
1556 struct gfar_private
*priv
= netdev_priv(dev
);
1558 struct txbd8
*lbdp
= NULL
;
1559 struct txbd8
*base
= priv
->tx_bd_base
;
1560 struct sk_buff
*skb
;
1562 int tx_ring_size
= priv
->tx_ring_size
;
1568 bdp
= priv
->dirty_tx
;
1569 skb_dirtytx
= priv
->skb_dirtytx
;
1571 while ((skb
= priv
->tx_skbuff
[skb_dirtytx
])) {
1572 frags
= skb_shinfo(skb
)->nr_frags
;
1573 lbdp
= skip_txbd(bdp
, frags
, base
, tx_ring_size
);
1575 lstatus
= lbdp
->lstatus
;
1577 /* Only clean completed frames */
1578 if ((lstatus
& BD_LFLAG(TXBD_READY
)) &&
1579 (lstatus
& BD_LENGTH_MASK
))
1582 dma_unmap_single(&dev
->dev
,
1587 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
1588 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
1590 for (i
= 0; i
< frags
; i
++) {
1591 dma_unmap_page(&dev
->dev
,
1595 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
1596 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
1599 dev_kfree_skb_any(skb
);
1600 priv
->tx_skbuff
[skb_dirtytx
] = NULL
;
1602 skb_dirtytx
= (skb_dirtytx
+ 1) &
1603 TX_RING_MOD_MASK(tx_ring_size
);
1606 priv
->num_txbdfree
+= frags
+ 1;
1609 /* If we freed a buffer, we can restart transmission, if necessary */
1610 if (netif_queue_stopped(dev
) && priv
->num_txbdfree
)
1611 netif_wake_queue(dev
);
1613 /* Update dirty indicators */
1614 priv
->skb_dirtytx
= skb_dirtytx
;
1615 priv
->dirty_tx
= bdp
;
1617 dev
->stats
.tx_packets
+= howmany
;
1622 static void gfar_schedule_cleanup(struct net_device
*dev
)
1624 struct gfar_private
*priv
= netdev_priv(dev
);
1625 if (netif_rx_schedule_prep(&priv
->napi
)) {
1626 gfar_write(&priv
->regs
->imask
, IMASK_RTX_DISABLED
);
1627 __netif_rx_schedule(&priv
->napi
);
1631 /* Interrupt Handler for Transmit complete */
1632 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
)
1634 gfar_schedule_cleanup((struct net_device
*)dev_id
);
1638 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
1639 struct sk_buff
*skb
)
1641 struct gfar_private
*priv
= netdev_priv(dev
);
1644 bdp
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1645 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1647 lstatus
= BD_LFLAG(RXBD_EMPTY
| RXBD_INTERRUPT
);
1649 if (bdp
== priv
->rx_bd_base
+ priv
->rx_ring_size
- 1)
1650 lstatus
|= BD_LFLAG(RXBD_WRAP
);
1654 bdp
->lstatus
= lstatus
;
1658 struct sk_buff
* gfar_new_skb(struct net_device
*dev
)
1660 unsigned int alignamount
;
1661 struct gfar_private
*priv
= netdev_priv(dev
);
1662 struct sk_buff
*skb
= NULL
;
1664 /* We have to allocate the skb, so keep trying till we succeed */
1665 skb
= netdev_alloc_skb(dev
, priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
1670 alignamount
= RXBUF_ALIGNMENT
-
1671 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
1673 /* We need the data buffer to be aligned properly. We will reserve
1674 * as many bytes as needed to align the data properly
1676 skb_reserve(skb
, alignamount
);
1681 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
1683 struct gfar_private
*priv
= netdev_priv(dev
);
1684 struct net_device_stats
*stats
= &dev
->stats
;
1685 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
1687 /* If the packet was truncated, none of the other errors
1689 if (status
& RXBD_TRUNCATED
) {
1690 stats
->rx_length_errors
++;
1696 /* Count the errors, if there were any */
1697 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
1698 stats
->rx_length_errors
++;
1700 if (status
& RXBD_LARGE
)
1705 if (status
& RXBD_NONOCTET
) {
1706 stats
->rx_frame_errors
++;
1707 estats
->rx_nonoctet
++;
1709 if (status
& RXBD_CRCERR
) {
1710 estats
->rx_crcerr
++;
1711 stats
->rx_crc_errors
++;
1713 if (status
& RXBD_OVERRUN
) {
1714 estats
->rx_overrun
++;
1715 stats
->rx_crc_errors
++;
1719 irqreturn_t
gfar_receive(int irq
, void *dev_id
)
1721 gfar_schedule_cleanup((struct net_device
*)dev_id
);
1725 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
1727 /* If valid headers were found, and valid sums
1728 * were verified, then we tell the kernel that no
1729 * checksumming is necessary. Otherwise, it is */
1730 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
1731 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1733 skb
->ip_summed
= CHECKSUM_NONE
;
1737 /* gfar_process_frame() -- handle one incoming packet if skb
1739 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
1742 struct gfar_private
*priv
= netdev_priv(dev
);
1743 struct rxfcb
*fcb
= NULL
;
1747 /* fcb is at the beginning if exists */
1748 fcb
= (struct rxfcb
*)skb
->data
;
1750 /* Remove the FCB from the skb */
1751 /* Remove the padded bytes, if there are any */
1753 skb_pull(skb
, amount_pull
);
1755 if (priv
->rx_csum_enable
)
1756 gfar_rx_checksum(skb
, fcb
);
1758 /* Tell the skb what kind of packet this is */
1759 skb
->protocol
= eth_type_trans(skb
, dev
);
1761 /* Send the packet up the stack */
1762 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
)))
1763 ret
= vlan_hwaccel_receive_skb(skb
, priv
->vlgrp
, fcb
->vlctl
);
1765 ret
= netif_receive_skb(skb
);
1767 if (NET_RX_DROP
== ret
)
1768 priv
->extra_stats
.kernel_dropped
++;
1773 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1774 * until the budget/quota has been reached. Returns the number
1777 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
)
1779 struct rxbd8
*bdp
, *base
;
1780 struct sk_buff
*skb
;
1784 struct gfar_private
*priv
= netdev_priv(dev
);
1786 /* Get the first full descriptor */
1788 base
= priv
->rx_bd_base
;
1790 amount_pull
= (gfar_uses_fcb(priv
) ? GMAC_FCB_LEN
: 0) +
1793 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
1794 struct sk_buff
*newskb
;
1797 /* Add another skb for the future */
1798 newskb
= gfar_new_skb(dev
);
1800 skb
= priv
->rx_skbuff
[priv
->skb_currx
];
1802 dma_unmap_single(&priv
->dev
->dev
, bdp
->bufPtr
,
1803 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1805 /* We drop the frame if we failed to allocate a new buffer */
1806 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
1807 bdp
->status
& RXBD_ERR
)) {
1808 count_errors(bdp
->status
, dev
);
1810 if (unlikely(!newskb
))
1813 dev_kfree_skb_any(skb
);
1815 /* Increment the number of packets */
1816 dev
->stats
.rx_packets
++;
1820 pkt_len
= bdp
->length
- ETH_FCS_LEN
;
1821 /* Remove the FCS from the packet length */
1822 skb_put(skb
, pkt_len
);
1823 dev
->stats
.rx_bytes
+= pkt_len
;
1825 gfar_process_frame(dev
, skb
, amount_pull
);
1828 if (netif_msg_rx_err(priv
))
1830 "%s: Missing skb!\n", dev
->name
);
1831 dev
->stats
.rx_dropped
++;
1832 priv
->extra_stats
.rx_skbmissing
++;
1837 priv
->rx_skbuff
[priv
->skb_currx
] = newskb
;
1839 /* Setup the new bdp */
1840 gfar_new_rxbdp(dev
, bdp
, newskb
);
1842 /* Update to the next pointer */
1843 bdp
= next_bd(bdp
, base
, priv
->rx_ring_size
);
1845 /* update to point at the next skb */
1847 (priv
->skb_currx
+ 1) &
1848 RX_RING_MOD_MASK(priv
->rx_ring_size
);
1851 /* Update the current rxbd pointer to be the next one */
1857 static int gfar_poll(struct napi_struct
*napi
, int budget
)
1859 struct gfar_private
*priv
= container_of(napi
, struct gfar_private
, napi
);
1860 struct net_device
*dev
= priv
->dev
;
1863 unsigned long flags
;
1865 /* Clear IEVENT, so interrupts aren't called again
1866 * because of the packets that have already arrived */
1867 gfar_write(&priv
->regs
->ievent
, IEVENT_RTX_MASK
);
1869 /* If we fail to get the lock, don't bother with the TX BDs */
1870 if (spin_trylock_irqsave(&priv
->txlock
, flags
)) {
1871 tx_cleaned
= gfar_clean_tx_ring(dev
);
1872 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1875 rx_cleaned
= gfar_clean_rx_ring(dev
, budget
);
1880 if (rx_cleaned
< budget
) {
1881 netif_rx_complete(napi
);
1883 /* Clear the halt bit in RSTAT */
1884 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1886 gfar_write(&priv
->regs
->imask
, IMASK_DEFAULT
);
1888 /* If we are coalescing interrupts, update the timer */
1889 /* Otherwise, clear it */
1890 if (likely(priv
->rxcoalescing
)) {
1891 gfar_write(&priv
->regs
->rxic
, 0);
1892 gfar_write(&priv
->regs
->rxic
, priv
->rxic
);
1894 if (likely(priv
->txcoalescing
)) {
1895 gfar_write(&priv
->regs
->txic
, 0);
1896 gfar_write(&priv
->regs
->txic
, priv
->txic
);
1903 #ifdef CONFIG_NET_POLL_CONTROLLER
1905 * Polling 'interrupt' - used by things like netconsole to send skbs
1906 * without having to re-enable interrupts. It's not called while
1907 * the interrupt routine is executing.
1909 static void gfar_netpoll(struct net_device
*dev
)
1911 struct gfar_private
*priv
= netdev_priv(dev
);
1913 /* If the device has multiple interrupts, run tx/rx */
1914 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1915 disable_irq(priv
->interruptTransmit
);
1916 disable_irq(priv
->interruptReceive
);
1917 disable_irq(priv
->interruptError
);
1918 gfar_interrupt(priv
->interruptTransmit
, dev
);
1919 enable_irq(priv
->interruptError
);
1920 enable_irq(priv
->interruptReceive
);
1921 enable_irq(priv
->interruptTransmit
);
1923 disable_irq(priv
->interruptTransmit
);
1924 gfar_interrupt(priv
->interruptTransmit
, dev
);
1925 enable_irq(priv
->interruptTransmit
);
1930 /* The interrupt handler for devices with one interrupt */
1931 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
)
1933 struct net_device
*dev
= dev_id
;
1934 struct gfar_private
*priv
= netdev_priv(dev
);
1936 /* Save ievent for future reference */
1937 u32 events
= gfar_read(&priv
->regs
->ievent
);
1939 /* Check for reception */
1940 if (events
& IEVENT_RX_MASK
)
1941 gfar_receive(irq
, dev_id
);
1943 /* Check for transmit completion */
1944 if (events
& IEVENT_TX_MASK
)
1945 gfar_transmit(irq
, dev_id
);
1947 /* Check for errors */
1948 if (events
& IEVENT_ERR_MASK
)
1949 gfar_error(irq
, dev_id
);
1954 /* Called every time the controller might need to be made
1955 * aware of new link state. The PHY code conveys this
1956 * information through variables in the phydev structure, and this
1957 * function converts those variables into the appropriate
1958 * register values, and can bring down the device if needed.
1960 static void adjust_link(struct net_device
*dev
)
1962 struct gfar_private
*priv
= netdev_priv(dev
);
1963 struct gfar __iomem
*regs
= priv
->regs
;
1964 unsigned long flags
;
1965 struct phy_device
*phydev
= priv
->phydev
;
1968 spin_lock_irqsave(&priv
->txlock
, flags
);
1970 u32 tempval
= gfar_read(®s
->maccfg2
);
1971 u32 ecntrl
= gfar_read(®s
->ecntrl
);
1973 /* Now we make sure that we can be in full duplex mode.
1974 * If not, we operate in half-duplex mode. */
1975 if (phydev
->duplex
!= priv
->oldduplex
) {
1977 if (!(phydev
->duplex
))
1978 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
1980 tempval
|= MACCFG2_FULL_DUPLEX
;
1982 priv
->oldduplex
= phydev
->duplex
;
1985 if (phydev
->speed
!= priv
->oldspeed
) {
1987 switch (phydev
->speed
) {
1990 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
1992 ecntrl
&= ~(ECNTRL_R100
);
1997 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
1999 /* Reduced mode distinguishes
2000 * between 10 and 100 */
2001 if (phydev
->speed
== SPEED_100
)
2002 ecntrl
|= ECNTRL_R100
;
2004 ecntrl
&= ~(ECNTRL_R100
);
2007 if (netif_msg_link(priv
))
2009 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2010 dev
->name
, phydev
->speed
);
2014 priv
->oldspeed
= phydev
->speed
;
2017 gfar_write(®s
->maccfg2
, tempval
);
2018 gfar_write(®s
->ecntrl
, ecntrl
);
2020 if (!priv
->oldlink
) {
2024 } else if (priv
->oldlink
) {
2028 priv
->oldduplex
= -1;
2031 if (new_state
&& netif_msg_link(priv
))
2032 phy_print_status(phydev
);
2034 spin_unlock_irqrestore(&priv
->txlock
, flags
);
2037 /* Update the hash table based on the current list of multicast
2038 * addresses we subscribe to. Also, change the promiscuity of
2039 * the device based on the flags (this function is called
2040 * whenever dev->flags is changed */
2041 static void gfar_set_multi(struct net_device
*dev
)
2043 struct dev_mc_list
*mc_ptr
;
2044 struct gfar_private
*priv
= netdev_priv(dev
);
2045 struct gfar __iomem
*regs
= priv
->regs
;
2048 if(dev
->flags
& IFF_PROMISC
) {
2049 /* Set RCTRL to PROM */
2050 tempval
= gfar_read(®s
->rctrl
);
2051 tempval
|= RCTRL_PROM
;
2052 gfar_write(®s
->rctrl
, tempval
);
2054 /* Set RCTRL to not PROM */
2055 tempval
= gfar_read(®s
->rctrl
);
2056 tempval
&= ~(RCTRL_PROM
);
2057 gfar_write(®s
->rctrl
, tempval
);
2060 if(dev
->flags
& IFF_ALLMULTI
) {
2061 /* Set the hash to rx all multicast frames */
2062 gfar_write(®s
->igaddr0
, 0xffffffff);
2063 gfar_write(®s
->igaddr1
, 0xffffffff);
2064 gfar_write(®s
->igaddr2
, 0xffffffff);
2065 gfar_write(®s
->igaddr3
, 0xffffffff);
2066 gfar_write(®s
->igaddr4
, 0xffffffff);
2067 gfar_write(®s
->igaddr5
, 0xffffffff);
2068 gfar_write(®s
->igaddr6
, 0xffffffff);
2069 gfar_write(®s
->igaddr7
, 0xffffffff);
2070 gfar_write(®s
->gaddr0
, 0xffffffff);
2071 gfar_write(®s
->gaddr1
, 0xffffffff);
2072 gfar_write(®s
->gaddr2
, 0xffffffff);
2073 gfar_write(®s
->gaddr3
, 0xffffffff);
2074 gfar_write(®s
->gaddr4
, 0xffffffff);
2075 gfar_write(®s
->gaddr5
, 0xffffffff);
2076 gfar_write(®s
->gaddr6
, 0xffffffff);
2077 gfar_write(®s
->gaddr7
, 0xffffffff);
2082 /* zero out the hash */
2083 gfar_write(®s
->igaddr0
, 0x0);
2084 gfar_write(®s
->igaddr1
, 0x0);
2085 gfar_write(®s
->igaddr2
, 0x0);
2086 gfar_write(®s
->igaddr3
, 0x0);
2087 gfar_write(®s
->igaddr4
, 0x0);
2088 gfar_write(®s
->igaddr5
, 0x0);
2089 gfar_write(®s
->igaddr6
, 0x0);
2090 gfar_write(®s
->igaddr7
, 0x0);
2091 gfar_write(®s
->gaddr0
, 0x0);
2092 gfar_write(®s
->gaddr1
, 0x0);
2093 gfar_write(®s
->gaddr2
, 0x0);
2094 gfar_write(®s
->gaddr3
, 0x0);
2095 gfar_write(®s
->gaddr4
, 0x0);
2096 gfar_write(®s
->gaddr5
, 0x0);
2097 gfar_write(®s
->gaddr6
, 0x0);
2098 gfar_write(®s
->gaddr7
, 0x0);
2100 /* If we have extended hash tables, we need to
2101 * clear the exact match registers to prepare for
2103 if (priv
->extended_hash
) {
2104 em_num
= GFAR_EM_NUM
+ 1;
2105 gfar_clear_exact_match(dev
);
2112 if(dev
->mc_count
== 0)
2115 /* Parse the list, and set the appropriate bits */
2116 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
2118 gfar_set_mac_for_addr(dev
, idx
,
2122 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
2130 /* Clears each of the exact match registers to zero, so they
2131 * don't interfere with normal reception */
2132 static void gfar_clear_exact_match(struct net_device
*dev
)
2135 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
2137 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
2138 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
2141 /* Set the appropriate hash bit for the given addr */
2142 /* The algorithm works like so:
2143 * 1) Take the Destination Address (ie the multicast address), and
2144 * do a CRC on it (little endian), and reverse the bits of the
2146 * 2) Use the 8 most significant bits as a hash into a 256-entry
2147 * table. The table is controlled through 8 32-bit registers:
2148 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2149 * gaddr7. This means that the 3 most significant bits in the
2150 * hash index which gaddr register to use, and the 5 other bits
2151 * indicate which bit (assuming an IBM numbering scheme, which
2152 * for PowerPC (tm) is usually the case) in the register holds
2154 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
2157 struct gfar_private
*priv
= netdev_priv(dev
);
2158 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
2159 int width
= priv
->hash_width
;
2160 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
2161 u8 whichreg
= result
>> (32 - width
+ 5);
2162 u32 value
= (1 << (31-whichbit
));
2164 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
2166 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
2172 /* There are multiple MAC Address register pairs on some controllers
2173 * This function sets the numth pair to a given address
2175 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
2177 struct gfar_private
*priv
= netdev_priv(dev
);
2179 char tmpbuf
[MAC_ADDR_LEN
];
2181 u32 __iomem
*macptr
= &priv
->regs
->macstnaddr1
;
2185 /* Now copy it into the mac registers backwards, cuz */
2186 /* little endian is silly */
2187 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
2188 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
2190 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
2192 tempval
= *((u32
*) (tmpbuf
+ 4));
2194 gfar_write(macptr
+1, tempval
);
2197 /* GFAR error interrupt handler */
2198 static irqreturn_t
gfar_error(int irq
, void *dev_id
)
2200 struct net_device
*dev
= dev_id
;
2201 struct gfar_private
*priv
= netdev_priv(dev
);
2203 /* Save ievent for future reference */
2204 u32 events
= gfar_read(&priv
->regs
->ievent
);
2207 gfar_write(&priv
->regs
->ievent
, events
& IEVENT_ERR_MASK
);
2209 /* Magic Packet is not an error. */
2210 if ((priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
) &&
2211 (events
& IEVENT_MAG
))
2212 events
&= ~IEVENT_MAG
;
2215 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
2216 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2217 dev
->name
, events
, gfar_read(&priv
->regs
->imask
));
2219 /* Update the error counters */
2220 if (events
& IEVENT_TXE
) {
2221 dev
->stats
.tx_errors
++;
2223 if (events
& IEVENT_LC
)
2224 dev
->stats
.tx_window_errors
++;
2225 if (events
& IEVENT_CRL
)
2226 dev
->stats
.tx_aborted_errors
++;
2227 if (events
& IEVENT_XFUN
) {
2228 if (netif_msg_tx_err(priv
))
2229 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
2230 "packet dropped.\n", dev
->name
);
2231 dev
->stats
.tx_dropped
++;
2232 priv
->extra_stats
.tx_underrun
++;
2234 /* Reactivate the Tx Queues */
2235 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
2237 if (netif_msg_tx_err(priv
))
2238 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
2240 if (events
& IEVENT_BSY
) {
2241 dev
->stats
.rx_errors
++;
2242 priv
->extra_stats
.rx_bsy
++;
2244 gfar_receive(irq
, dev_id
);
2246 if (netif_msg_rx_err(priv
))
2247 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
2248 dev
->name
, gfar_read(&priv
->regs
->rstat
));
2250 if (events
& IEVENT_BABR
) {
2251 dev
->stats
.rx_errors
++;
2252 priv
->extra_stats
.rx_babr
++;
2254 if (netif_msg_rx_err(priv
))
2255 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
2257 if (events
& IEVENT_EBERR
) {
2258 priv
->extra_stats
.eberr
++;
2259 if (netif_msg_rx_err(priv
))
2260 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
2262 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
2263 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
2265 if (events
& IEVENT_BABT
) {
2266 priv
->extra_stats
.tx_babt
++;
2267 if (netif_msg_tx_err(priv
))
2268 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
2273 /* work with hotplug and coldplug */
2274 MODULE_ALIAS("platform:fsl-gianfar");
2276 static struct of_device_id gfar_match
[] =
2280 .compatible
= "gianfar",
2285 /* Structure for a device driver */
2286 static struct of_platform_driver gfar_driver
= {
2287 .name
= "fsl-gianfar",
2288 .match_table
= gfar_match
,
2290 .probe
= gfar_probe
,
2291 .remove
= gfar_remove
,
2292 .suspend
= gfar_suspend
,
2293 .resume
= gfar_resume
,
2296 static int __init
gfar_init(void)
2298 int err
= gfar_mdio_init();
2303 err
= of_register_platform_driver(&gfar_driver
);
2311 static void __exit
gfar_exit(void)
2313 of_unregister_platform_driver(&gfar_driver
);
2317 module_init(gfar_init
);
2318 module_exit(gfar_exit
);