2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through platform_device. Structures which
29 * define the configuration needed by the board are defined in a
30 * board structure in arch/ppc/platforms (though I do not
31 * discount the possibility that other architectures could one
34 * The Gianfar Ethernet Controller uses a ring of buffer
35 * descriptors. The beginning is indicated by a register
36 * pointing to the physical address of the start of the ring.
37 * The end is determined by a "wrap" bit being set in the
38 * last descriptor of the ring.
40 * When a packet is received, the RXF bit in the
41 * IEVENT register is set, triggering an interrupt when the
42 * corresponding bit in the IMASK register is also set (if
43 * interrupt coalescing is active, then the interrupt may not
44 * happen immediately, but will wait until either a set number
45 * of frames or amount of time have passed). In NAPI, the
46 * interrupt handler will signal there is work to be done, and
47 * exit. Without NAPI, the packet(s) will be handled
48 * immediately. Both methods will start at the last known empty
49 * descriptor, and process every subsequent descriptor until there
50 * are none left with data (NAPI will stop after a set number of
51 * packets to give time to other tasks, but will eventually
52 * process all the packets). The data arrives inside a
53 * pre-allocated skb, and so after the skb is passed up to the
54 * stack, a new skb must be allocated, and the address field in
55 * the buffer descriptor must be updated to indicate this new
58 * When the kernel requests that a packet be transmitted, the
59 * driver starts where it left off last time, and points the
60 * descriptor at the buffer which was passed in. The driver
61 * then informs the DMA engine that there are packets ready to
62 * be transmitted. Once the controller is finished transmitting
63 * the packet, an interrupt may be triggered (under the same
64 * conditions as for reception, but depending on the TXF bit).
65 * The driver then cleans up the buffer.
68 #include <linux/kernel.h>
69 #include <linux/string.h>
70 #include <linux/errno.h>
71 #include <linux/unistd.h>
72 #include <linux/slab.h>
73 #include <linux/interrupt.h>
74 #include <linux/init.h>
75 #include <linux/delay.h>
76 #include <linux/netdevice.h>
77 #include <linux/etherdevice.h>
78 #include <linux/skbuff.h>
79 #include <linux/if_vlan.h>
80 #include <linux/spinlock.h>
82 #include <linux/platform_device.h>
84 #include <linux/tcp.h>
85 #include <linux/udp.h>
90 #include <asm/uaccess.h>
91 #include <linux/module.h>
92 #include <linux/dma-mapping.h>
93 #include <linux/crc32.h>
94 #include <linux/mii.h>
95 #include <linux/phy.h>
98 #include "gianfar_mii.h"
100 #define TX_TIMEOUT (1*HZ)
101 #define SKB_ALLOC_TIMEOUT 1000000
102 #undef BRIEF_GFAR_ERRORS
103 #undef VERBOSE_GFAR_ERRORS
105 #ifdef CONFIG_GFAR_NAPI
106 #define RECEIVE(x) netif_receive_skb(x)
108 #define RECEIVE(x) netif_rx(x)
111 const char gfar_driver_name
[] = "Gianfar Ethernet";
112 const char gfar_driver_version
[] = "1.3";
114 static int gfar_enet_open(struct net_device
*dev
);
115 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
116 static void gfar_timeout(struct net_device
*dev
);
117 static int gfar_close(struct net_device
*dev
);
118 struct sk_buff
*gfar_new_skb(struct net_device
*dev
, struct rxbd8
*bdp
);
119 static int gfar_set_mac_address(struct net_device
*dev
);
120 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
121 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
122 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
123 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
124 static void adjust_link(struct net_device
*dev
);
125 static void init_registers(struct net_device
*dev
);
126 static int init_phy(struct net_device
*dev
);
127 static int gfar_probe(struct platform_device
*pdev
);
128 static int gfar_remove(struct platform_device
*pdev
);
129 static void free_skb_resources(struct gfar_private
*priv
);
130 static void gfar_set_multi(struct net_device
*dev
);
131 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
132 static void gfar_configure_serdes(struct net_device
*dev
);
133 extern int gfar_local_mdio_write(struct gfar_mii
*regs
, int mii_id
, int regnum
, u16 value
);
134 extern int gfar_local_mdio_read(struct gfar_mii
*regs
, int mii_id
, int regnum
);
135 #ifdef CONFIG_GFAR_NAPI
136 static int gfar_poll(struct napi_struct
*napi
, int budget
);
138 #ifdef CONFIG_NET_POLL_CONTROLLER
139 static void gfar_netpoll(struct net_device
*dev
);
141 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
);
142 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
, int length
);
143 static void gfar_vlan_rx_register(struct net_device
*netdev
,
144 struct vlan_group
*grp
);
145 void gfar_halt(struct net_device
*dev
);
146 void gfar_start(struct net_device
*dev
);
147 static void gfar_clear_exact_match(struct net_device
*dev
);
148 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
150 extern const struct ethtool_ops gfar_ethtool_ops
;
152 MODULE_AUTHOR("Freescale Semiconductor, Inc");
153 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
154 MODULE_LICENSE("GPL");
156 /* Returns 1 if incoming frames use an FCB */
157 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
159 return (priv
->vlan_enable
|| priv
->rx_csum_enable
);
162 /* Set up the ethernet device structure, private data,
163 * and anything else we need before we start */
164 static int gfar_probe(struct platform_device
*pdev
)
167 struct net_device
*dev
= NULL
;
168 struct gfar_private
*priv
= NULL
;
169 struct gianfar_platform_data
*einfo
;
173 DECLARE_MAC_BUF(mac
);
175 einfo
= (struct gianfar_platform_data
*) pdev
->dev
.platform_data
;
178 printk(KERN_ERR
"gfar %d: Missing additional data!\n",
184 /* Create an ethernet device instance */
185 dev
= alloc_etherdev(sizeof (*priv
));
190 priv
= netdev_priv(dev
);
193 /* Set the info in the priv to the current info */
196 /* fill out IRQ fields */
197 if (einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
198 priv
->interruptTransmit
= platform_get_irq_byname(pdev
, "tx");
199 priv
->interruptReceive
= platform_get_irq_byname(pdev
, "rx");
200 priv
->interruptError
= platform_get_irq_byname(pdev
, "error");
201 if (priv
->interruptTransmit
< 0 || priv
->interruptReceive
< 0 || priv
->interruptError
< 0)
204 priv
->interruptTransmit
= platform_get_irq(pdev
, 0);
205 if (priv
->interruptTransmit
< 0)
209 /* get a pointer to the register memory */
210 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
211 priv
->regs
= ioremap(r
->start
, sizeof (struct gfar
));
213 if (NULL
== priv
->regs
) {
218 spin_lock_init(&priv
->txlock
);
219 spin_lock_init(&priv
->rxlock
);
221 platform_set_drvdata(pdev
, dev
);
223 /* Stop the DMA engine now, in case it was running before */
224 /* (The firmware could have used it, and left it running). */
225 /* To do this, we write Graceful Receive Stop and Graceful */
226 /* Transmit Stop, and then wait until the corresponding bits */
227 /* in IEVENT indicate the stops have completed. */
228 tempval
= gfar_read(&priv
->regs
->dmactrl
);
229 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
230 gfar_write(&priv
->regs
->dmactrl
, tempval
);
232 tempval
= gfar_read(&priv
->regs
->dmactrl
);
233 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
234 gfar_write(&priv
->regs
->dmactrl
, tempval
);
236 while (!(gfar_read(&priv
->regs
->ievent
) & (IEVENT_GRSC
| IEVENT_GTSC
)))
239 /* Reset MAC layer */
240 gfar_write(&priv
->regs
->maccfg1
, MACCFG1_SOFT_RESET
);
242 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
243 gfar_write(&priv
->regs
->maccfg1
, tempval
);
245 /* Initialize MACCFG2. */
246 gfar_write(&priv
->regs
->maccfg2
, MACCFG2_INIT_SETTINGS
);
248 /* Initialize ECNTRL */
249 gfar_write(&priv
->regs
->ecntrl
, ECNTRL_INIT_SETTINGS
);
251 /* Copy the station address into the dev structure, */
252 memcpy(dev
->dev_addr
, einfo
->mac_addr
, MAC_ADDR_LEN
);
254 /* Set the dev->base_addr to the gfar reg region */
255 dev
->base_addr
= (unsigned long) (priv
->regs
);
257 SET_NETDEV_DEV(dev
, &pdev
->dev
);
259 /* Fill in the dev structure */
260 dev
->open
= gfar_enet_open
;
261 dev
->hard_start_xmit
= gfar_start_xmit
;
262 dev
->tx_timeout
= gfar_timeout
;
263 dev
->watchdog_timeo
= TX_TIMEOUT
;
264 netif_napi_add(dev
, &priv
->napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
265 #ifdef CONFIG_NET_POLL_CONTROLLER
266 dev
->poll_controller
= gfar_netpoll
;
268 dev
->stop
= gfar_close
;
269 dev
->change_mtu
= gfar_change_mtu
;
271 dev
->set_multicast_list
= gfar_set_multi
;
273 dev
->ethtool_ops
= &gfar_ethtool_ops
;
275 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
276 priv
->rx_csum_enable
= 1;
277 dev
->features
|= NETIF_F_IP_CSUM
;
279 priv
->rx_csum_enable
= 0;
283 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
284 dev
->vlan_rx_register
= gfar_vlan_rx_register
;
286 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
288 priv
->vlan_enable
= 1;
291 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
292 priv
->extended_hash
= 1;
293 priv
->hash_width
= 9;
295 priv
->hash_regs
[0] = &priv
->regs
->igaddr0
;
296 priv
->hash_regs
[1] = &priv
->regs
->igaddr1
;
297 priv
->hash_regs
[2] = &priv
->regs
->igaddr2
;
298 priv
->hash_regs
[3] = &priv
->regs
->igaddr3
;
299 priv
->hash_regs
[4] = &priv
->regs
->igaddr4
;
300 priv
->hash_regs
[5] = &priv
->regs
->igaddr5
;
301 priv
->hash_regs
[6] = &priv
->regs
->igaddr6
;
302 priv
->hash_regs
[7] = &priv
->regs
->igaddr7
;
303 priv
->hash_regs
[8] = &priv
->regs
->gaddr0
;
304 priv
->hash_regs
[9] = &priv
->regs
->gaddr1
;
305 priv
->hash_regs
[10] = &priv
->regs
->gaddr2
;
306 priv
->hash_regs
[11] = &priv
->regs
->gaddr3
;
307 priv
->hash_regs
[12] = &priv
->regs
->gaddr4
;
308 priv
->hash_regs
[13] = &priv
->regs
->gaddr5
;
309 priv
->hash_regs
[14] = &priv
->regs
->gaddr6
;
310 priv
->hash_regs
[15] = &priv
->regs
->gaddr7
;
313 priv
->extended_hash
= 0;
314 priv
->hash_width
= 8;
316 priv
->hash_regs
[0] = &priv
->regs
->gaddr0
;
317 priv
->hash_regs
[1] = &priv
->regs
->gaddr1
;
318 priv
->hash_regs
[2] = &priv
->regs
->gaddr2
;
319 priv
->hash_regs
[3] = &priv
->regs
->gaddr3
;
320 priv
->hash_regs
[4] = &priv
->regs
->gaddr4
;
321 priv
->hash_regs
[5] = &priv
->regs
->gaddr5
;
322 priv
->hash_regs
[6] = &priv
->regs
->gaddr6
;
323 priv
->hash_regs
[7] = &priv
->regs
->gaddr7
;
326 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
327 priv
->padding
= DEFAULT_PADDING
;
331 if (dev
->features
& NETIF_F_IP_CSUM
)
332 dev
->hard_header_len
+= GMAC_FCB_LEN
;
334 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
335 priv
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
336 priv
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
338 priv
->txcoalescing
= DEFAULT_TX_COALESCE
;
339 priv
->txcount
= DEFAULT_TXCOUNT
;
340 priv
->txtime
= DEFAULT_TXTIME
;
341 priv
->rxcoalescing
= DEFAULT_RX_COALESCE
;
342 priv
->rxcount
= DEFAULT_RXCOUNT
;
343 priv
->rxtime
= DEFAULT_RXTIME
;
345 /* Enable most messages by default */
346 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
348 err
= register_netdev(dev
);
351 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
356 /* Create all the sysfs files */
357 gfar_init_sysfs(dev
);
359 /* Print out the device info */
360 printk(KERN_INFO DEVICE_NAME
"%s\n",
361 dev
->name
, print_mac(mac
, dev
->dev_addr
));
363 /* Even more device info helps when determining which kernel */
364 /* provided which set of benchmarks. */
365 #ifdef CONFIG_GFAR_NAPI
366 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
368 printk(KERN_INFO
"%s: Running with NAPI disabled\n", dev
->name
);
370 printk(KERN_INFO
"%s: %d/%d RX/TX BD ring size\n",
371 dev
->name
, priv
->rx_ring_size
, priv
->tx_ring_size
);
382 static int gfar_remove(struct platform_device
*pdev
)
384 struct net_device
*dev
= platform_get_drvdata(pdev
);
385 struct gfar_private
*priv
= netdev_priv(dev
);
387 platform_set_drvdata(pdev
, NULL
);
396 /* Reads the controller's registers to determine what interface
397 * connects it to the PHY.
399 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
401 struct gfar_private
*priv
= netdev_priv(dev
);
402 u32 ecntrl
= gfar_read(&priv
->regs
->ecntrl
);
404 if (ecntrl
& ECNTRL_SGMII_MODE
)
405 return PHY_INTERFACE_MODE_SGMII
;
407 if (ecntrl
& ECNTRL_TBI_MODE
) {
408 if (ecntrl
& ECNTRL_REDUCED_MODE
)
409 return PHY_INTERFACE_MODE_RTBI
;
411 return PHY_INTERFACE_MODE_TBI
;
414 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
415 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
416 return PHY_INTERFACE_MODE_RMII
;
418 phy_interface_t interface
= priv
->einfo
->interface
;
421 * This isn't autodetected right now, so it must
422 * be set by the device tree or platform code.
424 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
425 return PHY_INTERFACE_MODE_RGMII_ID
;
427 return PHY_INTERFACE_MODE_RGMII
;
431 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
432 return PHY_INTERFACE_MODE_GMII
;
434 return PHY_INTERFACE_MODE_MII
;
438 /* Initializes driver's PHY state, and attaches to the PHY.
439 * Returns 0 on success.
441 static int init_phy(struct net_device
*dev
)
443 struct gfar_private
*priv
= netdev_priv(dev
);
444 uint gigabit_support
=
445 priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
446 SUPPORTED_1000baseT_Full
: 0;
447 struct phy_device
*phydev
;
448 char phy_id
[BUS_ID_SIZE
];
449 phy_interface_t interface
;
453 priv
->oldduplex
= -1;
455 snprintf(phy_id
, BUS_ID_SIZE
, PHY_ID_FMT
, priv
->einfo
->bus_id
, priv
->einfo
->phy_id
);
457 interface
= gfar_get_interface(dev
);
459 phydev
= phy_connect(dev
, phy_id
, &adjust_link
, 0, interface
);
461 if (interface
== PHY_INTERFACE_MODE_SGMII
)
462 gfar_configure_serdes(dev
);
464 if (IS_ERR(phydev
)) {
465 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
466 return PTR_ERR(phydev
);
469 /* Remove any features not supported by the controller */
470 phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
471 phydev
->advertising
= phydev
->supported
;
473 priv
->phydev
= phydev
;
478 static void gfar_configure_serdes(struct net_device
*dev
)
480 struct gfar_private
*priv
= netdev_priv(dev
);
481 struct gfar_mii __iomem
*regs
=
482 (void __iomem
*)&priv
->regs
->gfar_mii_regs
;
484 /* Initialise TBI i/f to communicate with serdes (lynx phy) */
486 /* Single clk mode, mii mode off(for aerdes communication) */
487 gfar_local_mdio_write(regs
, TBIPA_VALUE
, MII_TBICON
, TBICON_CLK_SELECT
);
489 /* Supported pause and full-duplex, no half-duplex */
490 gfar_local_mdio_write(regs
, TBIPA_VALUE
, MII_ADVERTISE
,
491 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
492 ADVERTISE_1000XPSE_ASYM
);
494 /* ANEG enable, restart ANEG, full duplex mode, speed[1] set */
495 gfar_local_mdio_write(regs
, TBIPA_VALUE
, MII_BMCR
, BMCR_ANENABLE
|
496 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
499 static void init_registers(struct net_device
*dev
)
501 struct gfar_private
*priv
= netdev_priv(dev
);
504 gfar_write(&priv
->regs
->ievent
, IEVENT_INIT_CLEAR
);
506 /* Initialize IMASK */
507 gfar_write(&priv
->regs
->imask
, IMASK_INIT_CLEAR
);
509 /* Init hash registers to zero */
510 gfar_write(&priv
->regs
->igaddr0
, 0);
511 gfar_write(&priv
->regs
->igaddr1
, 0);
512 gfar_write(&priv
->regs
->igaddr2
, 0);
513 gfar_write(&priv
->regs
->igaddr3
, 0);
514 gfar_write(&priv
->regs
->igaddr4
, 0);
515 gfar_write(&priv
->regs
->igaddr5
, 0);
516 gfar_write(&priv
->regs
->igaddr6
, 0);
517 gfar_write(&priv
->regs
->igaddr7
, 0);
519 gfar_write(&priv
->regs
->gaddr0
, 0);
520 gfar_write(&priv
->regs
->gaddr1
, 0);
521 gfar_write(&priv
->regs
->gaddr2
, 0);
522 gfar_write(&priv
->regs
->gaddr3
, 0);
523 gfar_write(&priv
->regs
->gaddr4
, 0);
524 gfar_write(&priv
->regs
->gaddr5
, 0);
525 gfar_write(&priv
->regs
->gaddr6
, 0);
526 gfar_write(&priv
->regs
->gaddr7
, 0);
528 /* Zero out the rmon mib registers if it has them */
529 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
530 memset_io(&(priv
->regs
->rmon
), 0, sizeof (struct rmon_mib
));
532 /* Mask off the CAM interrupts */
533 gfar_write(&priv
->regs
->rmon
.cam1
, 0xffffffff);
534 gfar_write(&priv
->regs
->rmon
.cam2
, 0xffffffff);
537 /* Initialize the max receive buffer length */
538 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
540 /* Initialize the Minimum Frame Length Register */
541 gfar_write(&priv
->regs
->minflr
, MINFLR_INIT_SETTINGS
);
543 /* Assign the TBI an address which won't conflict with the PHYs */
544 gfar_write(&priv
->regs
->tbipa
, TBIPA_VALUE
);
548 /* Halt the receive and transmit queues */
549 void gfar_halt(struct net_device
*dev
)
551 struct gfar_private
*priv
= netdev_priv(dev
);
552 struct gfar __iomem
*regs
= priv
->regs
;
555 /* Mask all interrupts */
556 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
558 /* Clear all interrupts */
559 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
561 /* Stop the DMA, and wait for it to stop */
562 tempval
= gfar_read(&priv
->regs
->dmactrl
);
563 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
564 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
565 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
566 gfar_write(&priv
->regs
->dmactrl
, tempval
);
568 while (!(gfar_read(&priv
->regs
->ievent
) &
569 (IEVENT_GRSC
| IEVENT_GTSC
)))
573 /* Disable Rx and Tx */
574 tempval
= gfar_read(®s
->maccfg1
);
575 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
576 gfar_write(®s
->maccfg1
, tempval
);
579 void stop_gfar(struct net_device
*dev
)
581 struct gfar_private
*priv
= netdev_priv(dev
);
582 struct gfar __iomem
*regs
= priv
->regs
;
585 phy_stop(priv
->phydev
);
588 spin_lock_irqsave(&priv
->txlock
, flags
);
589 spin_lock(&priv
->rxlock
);
593 spin_unlock(&priv
->rxlock
);
594 spin_unlock_irqrestore(&priv
->txlock
, flags
);
597 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
598 free_irq(priv
->interruptError
, dev
);
599 free_irq(priv
->interruptTransmit
, dev
);
600 free_irq(priv
->interruptReceive
, dev
);
602 free_irq(priv
->interruptTransmit
, dev
);
605 free_skb_resources(priv
);
607 dma_free_coherent(NULL
,
608 sizeof(struct txbd8
)*priv
->tx_ring_size
609 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
611 gfar_read(®s
->tbase0
));
614 /* If there are any tx skbs or rx skbs still around, free them.
615 * Then free tx_skbuff and rx_skbuff */
616 static void free_skb_resources(struct gfar_private
*priv
)
622 /* Go through all the buffer descriptors and free their data buffers */
623 txbdp
= priv
->tx_bd_base
;
625 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
627 if (priv
->tx_skbuff
[i
]) {
628 dma_unmap_single(NULL
, txbdp
->bufPtr
,
631 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
632 priv
->tx_skbuff
[i
] = NULL
;
636 kfree(priv
->tx_skbuff
);
638 rxbdp
= priv
->rx_bd_base
;
640 /* rx_skbuff is not guaranteed to be allocated, so only
641 * free it and its contents if it is allocated */
642 if(priv
->rx_skbuff
!= NULL
) {
643 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
644 if (priv
->rx_skbuff
[i
]) {
645 dma_unmap_single(NULL
, rxbdp
->bufPtr
,
646 priv
->rx_buffer_size
,
649 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
650 priv
->rx_skbuff
[i
] = NULL
;
660 kfree(priv
->rx_skbuff
);
664 void gfar_start(struct net_device
*dev
)
666 struct gfar_private
*priv
= netdev_priv(dev
);
667 struct gfar __iomem
*regs
= priv
->regs
;
670 /* Enable Rx and Tx in MACCFG1 */
671 tempval
= gfar_read(®s
->maccfg1
);
672 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
673 gfar_write(®s
->maccfg1
, tempval
);
675 /* Initialize DMACTRL to have WWR and WOP */
676 tempval
= gfar_read(&priv
->regs
->dmactrl
);
677 tempval
|= DMACTRL_INIT_SETTINGS
;
678 gfar_write(&priv
->regs
->dmactrl
, tempval
);
680 /* Make sure we aren't stopped */
681 tempval
= gfar_read(&priv
->regs
->dmactrl
);
682 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
683 gfar_write(&priv
->regs
->dmactrl
, tempval
);
685 /* Clear THLT/RHLT, so that the DMA starts polling now */
686 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
);
687 gfar_write(®s
->rstat
, RSTAT_CLEAR_RHALT
);
689 /* Unmask the interrupts we look for */
690 gfar_write(®s
->imask
, IMASK_DEFAULT
);
693 /* Bring the controller up and running */
694 int startup_gfar(struct net_device
*dev
)
701 struct gfar_private
*priv
= netdev_priv(dev
);
702 struct gfar __iomem
*regs
= priv
->regs
;
707 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
709 /* Allocate memory for the buffer descriptors */
710 vaddr
= (unsigned long) dma_alloc_coherent(NULL
,
711 sizeof (struct txbd8
) * priv
->tx_ring_size
+
712 sizeof (struct rxbd8
) * priv
->rx_ring_size
,
716 if (netif_msg_ifup(priv
))
717 printk(KERN_ERR
"%s: Could not allocate buffer descriptors!\n",
722 priv
->tx_bd_base
= (struct txbd8
*) vaddr
;
724 /* enet DMA only understands physical addresses */
725 gfar_write(®s
->tbase0
, addr
);
727 /* Start the rx descriptor ring where the tx ring leaves off */
728 addr
= addr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
729 vaddr
= vaddr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
730 priv
->rx_bd_base
= (struct rxbd8
*) vaddr
;
731 gfar_write(®s
->rbase0
, addr
);
733 /* Setup the skbuff rings */
735 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
736 priv
->tx_ring_size
, GFP_KERNEL
);
738 if (NULL
== priv
->tx_skbuff
) {
739 if (netif_msg_ifup(priv
))
740 printk(KERN_ERR
"%s: Could not allocate tx_skbuff\n",
746 for (i
= 0; i
< priv
->tx_ring_size
; i
++)
747 priv
->tx_skbuff
[i
] = NULL
;
750 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
751 priv
->rx_ring_size
, GFP_KERNEL
);
753 if (NULL
== priv
->rx_skbuff
) {
754 if (netif_msg_ifup(priv
))
755 printk(KERN_ERR
"%s: Could not allocate rx_skbuff\n",
761 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
762 priv
->rx_skbuff
[i
] = NULL
;
764 /* Initialize some variables in our dev structure */
765 priv
->dirty_tx
= priv
->cur_tx
= priv
->tx_bd_base
;
766 priv
->cur_rx
= priv
->rx_bd_base
;
767 priv
->skb_curtx
= priv
->skb_dirtytx
= 0;
770 /* Initialize Transmit Descriptor Ring */
771 txbdp
= priv
->tx_bd_base
;
772 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
779 /* Set the last descriptor in the ring to indicate wrap */
781 txbdp
->status
|= TXBD_WRAP
;
783 rxbdp
= priv
->rx_bd_base
;
784 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
785 struct sk_buff
*skb
= NULL
;
789 skb
= gfar_new_skb(dev
, rxbdp
);
791 priv
->rx_skbuff
[i
] = skb
;
796 /* Set the last descriptor in the ring to wrap */
798 rxbdp
->status
|= RXBD_WRAP
;
800 /* If the device has multiple interrupts, register for
801 * them. Otherwise, only register for the one */
802 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
803 /* Install our interrupt handlers for Error,
804 * Transmit, and Receive */
805 if (request_irq(priv
->interruptError
, gfar_error
,
806 0, "enet_error", dev
) < 0) {
807 if (netif_msg_intr(priv
))
808 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
809 dev
->name
, priv
->interruptError
);
815 if (request_irq(priv
->interruptTransmit
, gfar_transmit
,
816 0, "enet_tx", dev
) < 0) {
817 if (netif_msg_intr(priv
))
818 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
819 dev
->name
, priv
->interruptTransmit
);
826 if (request_irq(priv
->interruptReceive
, gfar_receive
,
827 0, "enet_rx", dev
) < 0) {
828 if (netif_msg_intr(priv
))
829 printk(KERN_ERR
"%s: Can't get IRQ %d (receive0)\n",
830 dev
->name
, priv
->interruptReceive
);
836 if (request_irq(priv
->interruptTransmit
, gfar_interrupt
,
837 0, "gfar_interrupt", dev
) < 0) {
838 if (netif_msg_intr(priv
))
839 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
840 dev
->name
, priv
->interruptError
);
847 phy_start(priv
->phydev
);
849 /* Configure the coalescing support */
850 if (priv
->txcoalescing
)
851 gfar_write(®s
->txic
,
852 mk_ic_value(priv
->txcount
, priv
->txtime
));
854 gfar_write(®s
->txic
, 0);
856 if (priv
->rxcoalescing
)
857 gfar_write(®s
->rxic
,
858 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
860 gfar_write(®s
->rxic
, 0);
862 if (priv
->rx_csum_enable
)
863 rctrl
|= RCTRL_CHECKSUMMING
;
865 if (priv
->extended_hash
) {
866 rctrl
|= RCTRL_EXTHASH
;
868 gfar_clear_exact_match(dev
);
872 if (priv
->vlan_enable
)
876 rctrl
&= ~RCTRL_PAL_MASK
;
877 rctrl
|= RCTRL_PADDING(priv
->padding
);
880 /* Init rctrl based on our settings */
881 gfar_write(&priv
->regs
->rctrl
, rctrl
);
883 if (dev
->features
& NETIF_F_IP_CSUM
)
884 gfar_write(&priv
->regs
->tctrl
, TCTRL_INIT_CSUM
);
886 /* Set the extraction length and index */
887 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
888 ATTRELI_EI(priv
->rx_stash_index
);
890 gfar_write(&priv
->regs
->attreli
, attrs
);
892 /* Start with defaults, and add stashing or locking
893 * depending on the approprate variables */
894 attrs
= ATTR_INIT_SETTINGS
;
896 if (priv
->bd_stash_en
)
897 attrs
|= ATTR_BDSTASH
;
899 if (priv
->rx_stash_size
!= 0)
900 attrs
|= ATTR_BUFSTASH
;
902 gfar_write(&priv
->regs
->attr
, attrs
);
904 gfar_write(&priv
->regs
->fifo_tx_thr
, priv
->fifo_threshold
);
905 gfar_write(&priv
->regs
->fifo_tx_starve
, priv
->fifo_starve
);
906 gfar_write(&priv
->regs
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
908 /* Start the controller */
914 free_irq(priv
->interruptTransmit
, dev
);
916 free_irq(priv
->interruptError
, dev
);
919 free_skb_resources(priv
);
921 dma_free_coherent(NULL
,
922 sizeof(struct txbd8
)*priv
->tx_ring_size
923 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
925 gfar_read(®s
->tbase0
));
930 /* Called when something needs to use the ethernet device */
931 /* Returns 0 for success. */
932 static int gfar_enet_open(struct net_device
*dev
)
936 napi_enable(&priv
->napi
);
938 /* Initialize a bunch of registers */
941 gfar_set_mac_address(dev
);
946 napi_disable(&priv
->napi
);
950 err
= startup_gfar(dev
);
952 napi_disable(&priv
->napi
);
954 netif_start_queue(dev
);
959 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
, struct txbd8
*bdp
)
961 struct txfcb
*fcb
= (struct txfcb
*)skb_push (skb
, GMAC_FCB_LEN
);
963 memset(fcb
, 0, GMAC_FCB_LEN
);
968 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
972 /* If we're here, it's a IP packet with a TCP or UDP
973 * payload. We set it to checksum, using a pseudo-header
976 flags
= TXFCB_DEFAULT
;
978 /* Tell the controller what the protocol is */
979 /* And provide the already calculated phcs */
980 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
982 fcb
->phcs
= udp_hdr(skb
)->check
;
984 fcb
->phcs
= tcp_hdr(skb
)->check
;
986 /* l3os is the distance between the start of the
987 * frame (skb->data) and the start of the IP hdr.
988 * l4os is the distance between the start of the
989 * l3 hdr and the l4 hdr */
990 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
991 fcb
->l4os
= skb_network_header_len(skb
);
996 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
998 fcb
->flags
|= TXFCB_VLN
;
999 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1002 /* This is called by the kernel when a frame is ready for transmission. */
1003 /* It is pointed to by the dev->hard_start_xmit function pointer */
1004 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1006 struct gfar_private
*priv
= netdev_priv(dev
);
1007 struct txfcb
*fcb
= NULL
;
1008 struct txbd8
*txbdp
;
1010 unsigned long flags
;
1012 /* Update transmit stats */
1013 dev
->stats
.tx_bytes
+= skb
->len
;
1016 spin_lock_irqsave(&priv
->txlock
, flags
);
1018 /* Point at the first free tx descriptor */
1019 txbdp
= priv
->cur_tx
;
1021 /* Clear all but the WRAP status flags */
1022 status
= txbdp
->status
& TXBD_WRAP
;
1024 /* Set up checksumming */
1025 if (likely((dev
->features
& NETIF_F_IP_CSUM
)
1026 && (CHECKSUM_PARTIAL
== skb
->ip_summed
))) {
1027 fcb
= gfar_add_fcb(skb
, txbdp
);
1029 gfar_tx_checksum(skb
, fcb
);
1032 if (priv
->vlan_enable
&&
1033 unlikely(priv
->vlgrp
&& vlan_tx_tag_present(skb
))) {
1034 if (unlikely(NULL
== fcb
)) {
1035 fcb
= gfar_add_fcb(skb
, txbdp
);
1039 gfar_tx_vlan(skb
, fcb
);
1042 /* Set buffer length and pointer */
1043 txbdp
->length
= skb
->len
;
1044 txbdp
->bufPtr
= dma_map_single(NULL
, skb
->data
,
1045 skb
->len
, DMA_TO_DEVICE
);
1047 /* Save the skb pointer so we can free it later */
1048 priv
->tx_skbuff
[priv
->skb_curtx
] = skb
;
1050 /* Update the current skb pointer (wrapping if this was the last) */
1052 (priv
->skb_curtx
+ 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1054 /* Flag the BD as interrupt-causing */
1055 status
|= TXBD_INTERRUPT
;
1057 /* Flag the BD as ready to go, last in frame, and */
1058 /* in need of CRC */
1059 status
|= (TXBD_READY
| TXBD_LAST
| TXBD_CRC
);
1061 dev
->trans_start
= jiffies
;
1063 /* The powerpc-specific eieio() is used, as wmb() has too strong
1064 * semantics (it requires synchronization between cacheable and
1065 * uncacheable mappings, which eieio doesn't provide and which we
1066 * don't need), thus requiring a more expensive sync instruction. At
1067 * some point, the set of architecture-independent barrier functions
1068 * should be expanded to include weaker barriers.
1072 txbdp
->status
= status
;
1074 /* If this was the last BD in the ring, the next one */
1075 /* is at the beginning of the ring */
1076 if (txbdp
->status
& TXBD_WRAP
)
1077 txbdp
= priv
->tx_bd_base
;
1081 /* If the next BD still needs to be cleaned up, then the bds
1082 are full. We need to tell the kernel to stop sending us stuff. */
1083 if (txbdp
== priv
->dirty_tx
) {
1084 netif_stop_queue(dev
);
1086 dev
->stats
.tx_fifo_errors
++;
1089 /* Update the current txbd to the next one */
1090 priv
->cur_tx
= txbdp
;
1092 /* Tell the DMA to go go go */
1093 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1096 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1101 /* Stops the kernel queue, and halts the controller */
1102 static int gfar_close(struct net_device
*dev
)
1104 struct gfar_private
*priv
= netdev_priv(dev
);
1106 napi_disable(&priv
->napi
);
1110 /* Disconnect from the PHY */
1111 phy_disconnect(priv
->phydev
);
1112 priv
->phydev
= NULL
;
1114 netif_stop_queue(dev
);
1119 /* Changes the mac address if the controller is not running. */
1120 int gfar_set_mac_address(struct net_device
*dev
)
1122 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
1128 /* Enables and disables VLAN insertion/extraction */
1129 static void gfar_vlan_rx_register(struct net_device
*dev
,
1130 struct vlan_group
*grp
)
1132 struct gfar_private
*priv
= netdev_priv(dev
);
1133 unsigned long flags
;
1136 spin_lock_irqsave(&priv
->rxlock
, flags
);
1141 /* Enable VLAN tag insertion */
1142 tempval
= gfar_read(&priv
->regs
->tctrl
);
1143 tempval
|= TCTRL_VLINS
;
1145 gfar_write(&priv
->regs
->tctrl
, tempval
);
1147 /* Enable VLAN tag extraction */
1148 tempval
= gfar_read(&priv
->regs
->rctrl
);
1149 tempval
|= RCTRL_VLEX
;
1150 gfar_write(&priv
->regs
->rctrl
, tempval
);
1152 /* Disable VLAN tag insertion */
1153 tempval
= gfar_read(&priv
->regs
->tctrl
);
1154 tempval
&= ~TCTRL_VLINS
;
1155 gfar_write(&priv
->regs
->tctrl
, tempval
);
1157 /* Disable VLAN tag extraction */
1158 tempval
= gfar_read(&priv
->regs
->rctrl
);
1159 tempval
&= ~RCTRL_VLEX
;
1160 gfar_write(&priv
->regs
->rctrl
, tempval
);
1163 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1166 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
1168 int tempsize
, tempval
;
1169 struct gfar_private
*priv
= netdev_priv(dev
);
1170 int oldsize
= priv
->rx_buffer_size
;
1171 int frame_size
= new_mtu
+ ETH_HLEN
;
1173 if (priv
->vlan_enable
)
1174 frame_size
+= VLAN_ETH_HLEN
;
1176 if (gfar_uses_fcb(priv
))
1177 frame_size
+= GMAC_FCB_LEN
;
1179 frame_size
+= priv
->padding
;
1181 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
1182 if (netif_msg_drv(priv
))
1183 printk(KERN_ERR
"%s: Invalid MTU setting\n",
1189 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
1190 INCREMENTAL_BUFFER_SIZE
;
1192 /* Only stop and start the controller if it isn't already
1193 * stopped, and we changed something */
1194 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1197 priv
->rx_buffer_size
= tempsize
;
1201 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
1202 gfar_write(&priv
->regs
->maxfrm
, priv
->rx_buffer_size
);
1204 /* If the mtu is larger than the max size for standard
1205 * ethernet frames (ie, a jumbo frame), then set maccfg2
1206 * to allow huge frames, and to check the length */
1207 tempval
= gfar_read(&priv
->regs
->maccfg2
);
1209 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
1210 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1212 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1214 gfar_write(&priv
->regs
->maccfg2
, tempval
);
1216 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1222 /* gfar_timeout gets called when a packet has not been
1223 * transmitted after a set amount of time.
1224 * For now, assume that clearing out all the structures, and
1225 * starting over will fix the problem. */
1226 static void gfar_timeout(struct net_device
*dev
)
1228 struct gfar_private
*priv
= netdev_priv(dev
);
1230 dev
->stats
.tx_errors
++;
1232 if (dev
->flags
& IFF_UP
) {
1237 netif_schedule(dev
);
1240 /* Interrupt Handler for Transmit complete */
1241 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
)
1243 struct net_device
*dev
= (struct net_device
*) dev_id
;
1244 struct gfar_private
*priv
= netdev_priv(dev
);
1248 gfar_write(&priv
->regs
->ievent
, IEVENT_TX_MASK
);
1251 spin_lock(&priv
->txlock
);
1252 bdp
= priv
->dirty_tx
;
1253 while ((bdp
->status
& TXBD_READY
) == 0) {
1254 /* If dirty_tx and cur_tx are the same, then either the */
1255 /* ring is empty or full now (it could only be full in the beginning, */
1256 /* obviously). If it is empty, we are done. */
1257 if ((bdp
== priv
->cur_tx
) && (netif_queue_stopped(dev
) == 0))
1260 dev
->stats
.tx_packets
++;
1262 /* Deferred means some collisions occurred during transmit, */
1263 /* but we eventually sent the packet. */
1264 if (bdp
->status
& TXBD_DEF
)
1265 dev
->stats
.collisions
++;
1267 /* Free the sk buffer associated with this TxBD */
1268 dev_kfree_skb_irq(priv
->tx_skbuff
[priv
->skb_dirtytx
]);
1269 priv
->tx_skbuff
[priv
->skb_dirtytx
] = NULL
;
1271 (priv
->skb_dirtytx
+
1272 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1274 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1275 if (bdp
->status
& TXBD_WRAP
)
1276 bdp
= priv
->tx_bd_base
;
1280 /* Move dirty_tx to be the next bd */
1281 priv
->dirty_tx
= bdp
;
1283 /* We freed a buffer, so now we can restart transmission */
1284 if (netif_queue_stopped(dev
))
1285 netif_wake_queue(dev
);
1286 } /* while ((bdp->status & TXBD_READY) == 0) */
1288 /* If we are coalescing the interrupts, reset the timer */
1289 /* Otherwise, clear it */
1290 if (priv
->txcoalescing
)
1291 gfar_write(&priv
->regs
->txic
,
1292 mk_ic_value(priv
->txcount
, priv
->txtime
));
1294 gfar_write(&priv
->regs
->txic
, 0);
1296 spin_unlock(&priv
->txlock
);
1301 struct sk_buff
* gfar_new_skb(struct net_device
*dev
, struct rxbd8
*bdp
)
1303 unsigned int alignamount
;
1304 struct gfar_private
*priv
= netdev_priv(dev
);
1305 struct sk_buff
*skb
= NULL
;
1306 unsigned int timeout
= SKB_ALLOC_TIMEOUT
;
1308 /* We have to allocate the skb, so keep trying till we succeed */
1309 while ((!skb
) && timeout
--)
1310 skb
= dev_alloc_skb(priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
1315 alignamount
= RXBUF_ALIGNMENT
-
1316 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
1318 /* We need the data buffer to be aligned properly. We will reserve
1319 * as many bytes as needed to align the data properly
1321 skb_reserve(skb
, alignamount
);
1323 bdp
->bufPtr
= dma_map_single(NULL
, skb
->data
,
1324 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1328 /* Mark the buffer empty */
1330 bdp
->status
|= (RXBD_EMPTY
| RXBD_INTERRUPT
);
1335 static inline void count_errors(unsigned short status
, struct gfar_private
*priv
)
1337 struct net_device_stats
*stats
= &dev
->stats
;
1338 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
1340 /* If the packet was truncated, none of the other errors
1342 if (status
& RXBD_TRUNCATED
) {
1343 stats
->rx_length_errors
++;
1349 /* Count the errors, if there were any */
1350 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
1351 stats
->rx_length_errors
++;
1353 if (status
& RXBD_LARGE
)
1358 if (status
& RXBD_NONOCTET
) {
1359 stats
->rx_frame_errors
++;
1360 estats
->rx_nonoctet
++;
1362 if (status
& RXBD_CRCERR
) {
1363 estats
->rx_crcerr
++;
1364 stats
->rx_crc_errors
++;
1366 if (status
& RXBD_OVERRUN
) {
1367 estats
->rx_overrun
++;
1368 stats
->rx_crc_errors
++;
1372 irqreturn_t
gfar_receive(int irq
, void *dev_id
)
1374 struct net_device
*dev
= (struct net_device
*) dev_id
;
1375 struct gfar_private
*priv
= netdev_priv(dev
);
1376 #ifdef CONFIG_GFAR_NAPI
1379 unsigned long flags
;
1382 /* Clear IEVENT, so rx interrupt isn't called again
1383 * because of this interrupt */
1384 gfar_write(&priv
->regs
->ievent
, IEVENT_RX_MASK
);
1387 #ifdef CONFIG_GFAR_NAPI
1388 if (netif_rx_schedule_prep(dev
, &priv
->napi
)) {
1389 tempval
= gfar_read(&priv
->regs
->imask
);
1390 tempval
&= IMASK_RX_DISABLED
;
1391 gfar_write(&priv
->regs
->imask
, tempval
);
1393 __netif_rx_schedule(dev
, &priv
->napi
);
1395 if (netif_msg_rx_err(priv
))
1396 printk(KERN_DEBUG
"%s: receive called twice (%x)[%x]\n",
1397 dev
->name
, gfar_read(&priv
->regs
->ievent
),
1398 gfar_read(&priv
->regs
->imask
));
1402 spin_lock_irqsave(&priv
->rxlock
, flags
);
1403 gfar_clean_rx_ring(dev
, priv
->rx_ring_size
);
1405 /* If we are coalescing interrupts, update the timer */
1406 /* Otherwise, clear it */
1407 if (priv
->rxcoalescing
)
1408 gfar_write(&priv
->regs
->rxic
,
1409 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
1411 gfar_write(&priv
->regs
->rxic
, 0);
1413 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1419 static inline int gfar_rx_vlan(struct sk_buff
*skb
,
1420 struct vlan_group
*vlgrp
, unsigned short vlctl
)
1422 #ifdef CONFIG_GFAR_NAPI
1423 return vlan_hwaccel_receive_skb(skb
, vlgrp
, vlctl
);
1425 return vlan_hwaccel_rx(skb
, vlgrp
, vlctl
);
1429 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
1431 /* If valid headers were found, and valid sums
1432 * were verified, then we tell the kernel that no
1433 * checksumming is necessary. Otherwise, it is */
1434 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
1435 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1437 skb
->ip_summed
= CHECKSUM_NONE
;
1441 static inline struct rxfcb
*gfar_get_fcb(struct sk_buff
*skb
)
1443 struct rxfcb
*fcb
= (struct rxfcb
*)skb
->data
;
1445 /* Remove the FCB from the skb */
1446 skb_pull(skb
, GMAC_FCB_LEN
);
1451 /* gfar_process_frame() -- handle one incoming packet if skb
1453 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
1456 struct gfar_private
*priv
= netdev_priv(dev
);
1457 struct rxfcb
*fcb
= NULL
;
1460 if (netif_msg_rx_err(priv
))
1461 printk(KERN_WARNING
"%s: Missing skb!!.\n", dev
->name
);
1462 dev
->stats
.rx_dropped
++;
1463 priv
->extra_stats
.rx_skbmissing
++;
1467 /* Prep the skb for the packet */
1468 skb_put(skb
, length
);
1470 /* Grab the FCB if there is one */
1471 if (gfar_uses_fcb(priv
))
1472 fcb
= gfar_get_fcb(skb
);
1474 /* Remove the padded bytes, if there are any */
1476 skb_pull(skb
, priv
->padding
);
1478 if (priv
->rx_csum_enable
)
1479 gfar_rx_checksum(skb
, fcb
);
1481 /* Tell the skb what kind of packet this is */
1482 skb
->protocol
= eth_type_trans(skb
, dev
);
1484 /* Send the packet up the stack */
1485 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
)))
1486 ret
= gfar_rx_vlan(skb
, priv
->vlgrp
, fcb
->vlctl
);
1490 if (NET_RX_DROP
== ret
)
1491 priv
->extra_stats
.kernel_dropped
++;
1497 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1498 * until the budget/quota has been reached. Returns the number
1501 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
)
1504 struct sk_buff
*skb
;
1507 struct gfar_private
*priv
= netdev_priv(dev
);
1509 /* Get the first full descriptor */
1512 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
1514 skb
= priv
->rx_skbuff
[priv
->skb_currx
];
1517 (RXBD_LARGE
| RXBD_SHORT
| RXBD_NONOCTET
1518 | RXBD_CRCERR
| RXBD_OVERRUN
| RXBD_TRUNCATED
))) {
1519 /* Increment the number of packets */
1520 dev
->stats
.rx_packets
++;
1523 /* Remove the FCS from the packet length */
1524 pkt_len
= bdp
->length
- 4;
1526 gfar_process_frame(dev
, skb
, pkt_len
);
1528 dev
->stats
.rx_bytes
+= pkt_len
;
1530 count_errors(bdp
->status
, priv
);
1533 dev_kfree_skb_any(skb
);
1535 priv
->rx_skbuff
[priv
->skb_currx
] = NULL
;
1538 dev
->last_rx
= jiffies
;
1540 /* Clear the status flags for this buffer */
1541 bdp
->status
&= ~RXBD_STATS
;
1543 /* Add another skb for the future */
1544 skb
= gfar_new_skb(dev
, bdp
);
1545 priv
->rx_skbuff
[priv
->skb_currx
] = skb
;
1547 /* Update to the next pointer */
1548 if (bdp
->status
& RXBD_WRAP
)
1549 bdp
= priv
->rx_bd_base
;
1553 /* update to point at the next skb */
1556 1) & RX_RING_MOD_MASK(priv
->rx_ring_size
);
1560 /* Update the current rxbd pointer to be the next one */
1566 #ifdef CONFIG_GFAR_NAPI
1567 static int gfar_poll(struct napi_struct
*napi
, int budget
)
1569 struct gfar_private
*priv
= container_of(napi
, struct gfar_private
, napi
);
1570 struct net_device
*dev
= priv
->dev
;
1573 howmany
= gfar_clean_rx_ring(dev
, budget
);
1575 if (howmany
< budget
) {
1576 netif_rx_complete(dev
, napi
);
1578 /* Clear the halt bit in RSTAT */
1579 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1581 gfar_write(&priv
->regs
->imask
, IMASK_DEFAULT
);
1583 /* If we are coalescing interrupts, update the timer */
1584 /* Otherwise, clear it */
1585 if (priv
->rxcoalescing
)
1586 gfar_write(&priv
->regs
->rxic
,
1587 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
1589 gfar_write(&priv
->regs
->rxic
, 0);
1596 #ifdef CONFIG_NET_POLL_CONTROLLER
1598 * Polling 'interrupt' - used by things like netconsole to send skbs
1599 * without having to re-enable interrupts. It's not called while
1600 * the interrupt routine is executing.
1602 static void gfar_netpoll(struct net_device
*dev
)
1604 struct gfar_private
*priv
= netdev_priv(dev
);
1606 /* If the device has multiple interrupts, run tx/rx */
1607 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1608 disable_irq(priv
->interruptTransmit
);
1609 disable_irq(priv
->interruptReceive
);
1610 disable_irq(priv
->interruptError
);
1611 gfar_interrupt(priv
->interruptTransmit
, dev
);
1612 enable_irq(priv
->interruptError
);
1613 enable_irq(priv
->interruptReceive
);
1614 enable_irq(priv
->interruptTransmit
);
1616 disable_irq(priv
->interruptTransmit
);
1617 gfar_interrupt(priv
->interruptTransmit
, dev
);
1618 enable_irq(priv
->interruptTransmit
);
1623 /* The interrupt handler for devices with one interrupt */
1624 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
)
1626 struct net_device
*dev
= dev_id
;
1627 struct gfar_private
*priv
= netdev_priv(dev
);
1629 /* Save ievent for future reference */
1630 u32 events
= gfar_read(&priv
->regs
->ievent
);
1632 /* Check for reception */
1633 if (events
& IEVENT_RX_MASK
)
1634 gfar_receive(irq
, dev_id
);
1636 /* Check for transmit completion */
1637 if (events
& IEVENT_TX_MASK
)
1638 gfar_transmit(irq
, dev_id
);
1640 /* Check for errors */
1641 if (events
& IEVENT_ERR_MASK
)
1642 gfar_error(irq
, dev_id
);
1647 /* Called every time the controller might need to be made
1648 * aware of new link state. The PHY code conveys this
1649 * information through variables in the phydev structure, and this
1650 * function converts those variables into the appropriate
1651 * register values, and can bring down the device if needed.
1653 static void adjust_link(struct net_device
*dev
)
1655 struct gfar_private
*priv
= netdev_priv(dev
);
1656 struct gfar __iomem
*regs
= priv
->regs
;
1657 unsigned long flags
;
1658 struct phy_device
*phydev
= priv
->phydev
;
1661 spin_lock_irqsave(&priv
->txlock
, flags
);
1663 u32 tempval
= gfar_read(®s
->maccfg2
);
1664 u32 ecntrl
= gfar_read(®s
->ecntrl
);
1666 /* Now we make sure that we can be in full duplex mode.
1667 * If not, we operate in half-duplex mode. */
1668 if (phydev
->duplex
!= priv
->oldduplex
) {
1670 if (!(phydev
->duplex
))
1671 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
1673 tempval
|= MACCFG2_FULL_DUPLEX
;
1675 priv
->oldduplex
= phydev
->duplex
;
1678 if (phydev
->speed
!= priv
->oldspeed
) {
1680 switch (phydev
->speed
) {
1683 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
1688 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
1690 /* Reduced mode distinguishes
1691 * between 10 and 100 */
1692 if (phydev
->speed
== SPEED_100
)
1693 ecntrl
|= ECNTRL_R100
;
1695 ecntrl
&= ~(ECNTRL_R100
);
1698 if (netif_msg_link(priv
))
1700 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1701 dev
->name
, phydev
->speed
);
1705 priv
->oldspeed
= phydev
->speed
;
1708 gfar_write(®s
->maccfg2
, tempval
);
1709 gfar_write(®s
->ecntrl
, ecntrl
);
1711 if (!priv
->oldlink
) {
1714 netif_schedule(dev
);
1716 } else if (priv
->oldlink
) {
1720 priv
->oldduplex
= -1;
1723 if (new_state
&& netif_msg_link(priv
))
1724 phy_print_status(phydev
);
1726 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1729 /* Update the hash table based on the current list of multicast
1730 * addresses we subscribe to. Also, change the promiscuity of
1731 * the device based on the flags (this function is called
1732 * whenever dev->flags is changed */
1733 static void gfar_set_multi(struct net_device
*dev
)
1735 struct dev_mc_list
*mc_ptr
;
1736 struct gfar_private
*priv
= netdev_priv(dev
);
1737 struct gfar __iomem
*regs
= priv
->regs
;
1740 if(dev
->flags
& IFF_PROMISC
) {
1741 /* Set RCTRL to PROM */
1742 tempval
= gfar_read(®s
->rctrl
);
1743 tempval
|= RCTRL_PROM
;
1744 gfar_write(®s
->rctrl
, tempval
);
1746 /* Set RCTRL to not PROM */
1747 tempval
= gfar_read(®s
->rctrl
);
1748 tempval
&= ~(RCTRL_PROM
);
1749 gfar_write(®s
->rctrl
, tempval
);
1752 if(dev
->flags
& IFF_ALLMULTI
) {
1753 /* Set the hash to rx all multicast frames */
1754 gfar_write(®s
->igaddr0
, 0xffffffff);
1755 gfar_write(®s
->igaddr1
, 0xffffffff);
1756 gfar_write(®s
->igaddr2
, 0xffffffff);
1757 gfar_write(®s
->igaddr3
, 0xffffffff);
1758 gfar_write(®s
->igaddr4
, 0xffffffff);
1759 gfar_write(®s
->igaddr5
, 0xffffffff);
1760 gfar_write(®s
->igaddr6
, 0xffffffff);
1761 gfar_write(®s
->igaddr7
, 0xffffffff);
1762 gfar_write(®s
->gaddr0
, 0xffffffff);
1763 gfar_write(®s
->gaddr1
, 0xffffffff);
1764 gfar_write(®s
->gaddr2
, 0xffffffff);
1765 gfar_write(®s
->gaddr3
, 0xffffffff);
1766 gfar_write(®s
->gaddr4
, 0xffffffff);
1767 gfar_write(®s
->gaddr5
, 0xffffffff);
1768 gfar_write(®s
->gaddr6
, 0xffffffff);
1769 gfar_write(®s
->gaddr7
, 0xffffffff);
1774 /* zero out the hash */
1775 gfar_write(®s
->igaddr0
, 0x0);
1776 gfar_write(®s
->igaddr1
, 0x0);
1777 gfar_write(®s
->igaddr2
, 0x0);
1778 gfar_write(®s
->igaddr3
, 0x0);
1779 gfar_write(®s
->igaddr4
, 0x0);
1780 gfar_write(®s
->igaddr5
, 0x0);
1781 gfar_write(®s
->igaddr6
, 0x0);
1782 gfar_write(®s
->igaddr7
, 0x0);
1783 gfar_write(®s
->gaddr0
, 0x0);
1784 gfar_write(®s
->gaddr1
, 0x0);
1785 gfar_write(®s
->gaddr2
, 0x0);
1786 gfar_write(®s
->gaddr3
, 0x0);
1787 gfar_write(®s
->gaddr4
, 0x0);
1788 gfar_write(®s
->gaddr5
, 0x0);
1789 gfar_write(®s
->gaddr6
, 0x0);
1790 gfar_write(®s
->gaddr7
, 0x0);
1792 /* If we have extended hash tables, we need to
1793 * clear the exact match registers to prepare for
1795 if (priv
->extended_hash
) {
1796 em_num
= GFAR_EM_NUM
+ 1;
1797 gfar_clear_exact_match(dev
);
1804 if(dev
->mc_count
== 0)
1807 /* Parse the list, and set the appropriate bits */
1808 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
1810 gfar_set_mac_for_addr(dev
, idx
,
1814 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
1822 /* Clears each of the exact match registers to zero, so they
1823 * don't interfere with normal reception */
1824 static void gfar_clear_exact_match(struct net_device
*dev
)
1827 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
1829 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
1830 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
1833 /* Set the appropriate hash bit for the given addr */
1834 /* The algorithm works like so:
1835 * 1) Take the Destination Address (ie the multicast address), and
1836 * do a CRC on it (little endian), and reverse the bits of the
1838 * 2) Use the 8 most significant bits as a hash into a 256-entry
1839 * table. The table is controlled through 8 32-bit registers:
1840 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1841 * gaddr7. This means that the 3 most significant bits in the
1842 * hash index which gaddr register to use, and the 5 other bits
1843 * indicate which bit (assuming an IBM numbering scheme, which
1844 * for PowerPC (tm) is usually the case) in the register holds
1846 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
1849 struct gfar_private
*priv
= netdev_priv(dev
);
1850 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
1851 int width
= priv
->hash_width
;
1852 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
1853 u8 whichreg
= result
>> (32 - width
+ 5);
1854 u32 value
= (1 << (31-whichbit
));
1856 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
1858 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
1864 /* There are multiple MAC Address register pairs on some controllers
1865 * This function sets the numth pair to a given address
1867 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
1869 struct gfar_private
*priv
= netdev_priv(dev
);
1871 char tmpbuf
[MAC_ADDR_LEN
];
1873 u32 __iomem
*macptr
= &priv
->regs
->macstnaddr1
;
1877 /* Now copy it into the mac registers backwards, cuz */
1878 /* little endian is silly */
1879 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
1880 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
1882 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
1884 tempval
= *((u32
*) (tmpbuf
+ 4));
1886 gfar_write(macptr
+1, tempval
);
1889 /* GFAR error interrupt handler */
1890 static irqreturn_t
gfar_error(int irq
, void *dev_id
)
1892 struct net_device
*dev
= dev_id
;
1893 struct gfar_private
*priv
= netdev_priv(dev
);
1895 /* Save ievent for future reference */
1896 u32 events
= gfar_read(&priv
->regs
->ievent
);
1899 gfar_write(&priv
->regs
->ievent
, IEVENT_ERR_MASK
);
1902 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
1903 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1904 dev
->name
, events
, gfar_read(&priv
->regs
->imask
));
1906 /* Update the error counters */
1907 if (events
& IEVENT_TXE
) {
1908 dev
->stats
.tx_errors
++;
1910 if (events
& IEVENT_LC
)
1911 dev
->stats
.tx_window_errors
++;
1912 if (events
& IEVENT_CRL
)
1913 dev
->stats
.tx_aborted_errors
++;
1914 if (events
& IEVENT_XFUN
) {
1915 if (netif_msg_tx_err(priv
))
1916 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
1917 "packet dropped.\n", dev
->name
);
1918 dev
->stats
.tx_dropped
++;
1919 priv
->extra_stats
.tx_underrun
++;
1921 /* Reactivate the Tx Queues */
1922 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1924 if (netif_msg_tx_err(priv
))
1925 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
1927 if (events
& IEVENT_BSY
) {
1928 dev
->stats
.rx_errors
++;
1929 priv
->extra_stats
.rx_bsy
++;
1931 gfar_receive(irq
, dev_id
);
1933 #ifndef CONFIG_GFAR_NAPI
1934 /* Clear the halt bit in RSTAT */
1935 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1938 if (netif_msg_rx_err(priv
))
1939 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
1940 dev
->name
, gfar_read(&priv
->regs
->rstat
));
1942 if (events
& IEVENT_BABR
) {
1943 dev
->stats
.rx_errors
++;
1944 priv
->extra_stats
.rx_babr
++;
1946 if (netif_msg_rx_err(priv
))
1947 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
1949 if (events
& IEVENT_EBERR
) {
1950 priv
->extra_stats
.eberr
++;
1951 if (netif_msg_rx_err(priv
))
1952 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
1954 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
1955 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
1957 if (events
& IEVENT_BABT
) {
1958 priv
->extra_stats
.tx_babt
++;
1959 if (netif_msg_tx_err(priv
))
1960 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
1965 /* Structure for a device driver */
1966 static struct platform_driver gfar_driver
= {
1967 .probe
= gfar_probe
,
1968 .remove
= gfar_remove
,
1970 .name
= "fsl-gianfar",
1974 static int __init
gfar_init(void)
1976 int err
= gfar_mdio_init();
1981 err
= platform_driver_register(&gfar_driver
);
1989 static void __exit
gfar_exit(void)
1991 platform_driver_unregister(&gfar_driver
);
1995 module_init(gfar_init
);
1996 module_exit(gfar_exit
);