drivers/net/ieee802154/mrf24j40.c

   1 /*
   2  * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
   3  *
   4  * Copyright (C) 2012 Alan Ott <alan@signal11.us>
   5  *                    Signal 11 Software
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/spi/spi.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <net/wpan-phy.h>
  27 #include <net/mac802154.h>
  28 #include <net/ieee802154.h>
  29
  30 /* MRF24J40 Short Address Registers */
  31 #define REG_RXMCR    0x00  /* Receive MAC control */
  32 #define REG_PANIDL   0x01  /* PAN ID (low) */
  33 #define REG_PANIDH   0x02  /* PAN ID (high) */
  34 #define REG_SADRL    0x03  /* Short address (low) */
  35 #define REG_SADRH    0x04  /* Short address (high) */
  36 #define REG_EADR0    0x05  /* Long address (low) (high is EADR7) */
  37 #define REG_TXMCR    0x11  /* Transmit MAC control */
  38 #define REG_PACON0   0x16  /* Power Amplifier Control */
  39 #define REG_PACON1   0x17  /* Power Amplifier Control */
  40 #define REG_PACON2   0x18  /* Power Amplifier Control */
  41 #define REG_TXNCON   0x1B  /* Transmit Normal FIFO Control */
  42 #define REG_TXSTAT   0x24  /* TX MAC Status Register */
  43 #define REG_SOFTRST  0x2A  /* Soft Reset */
  44 #define REG_TXSTBL   0x2E  /* TX Stabilization */
  45 #define REG_INTSTAT  0x31  /* Interrupt Status */
  46 #define REG_INTCON   0x32  /* Interrupt Control */
  47 #define REG_RFCTL    0x36  /* RF Control Mode Register */
  48 #define REG_BBREG1   0x39  /* Baseband Registers */
  49 #define REG_BBREG2   0x3A  /* */
  50 #define REG_BBREG6   0x3E  /* */
  51 #define REG_CCAEDTH  0x3F  /* Energy Detection Threshold */
  52
  53 /* MRF24J40 Long Address Registers */
  54 #define REG_RFCON0     0x200  /* RF Control Registers */
  55 #define REG_RFCON1     0x201
  56 #define REG_RFCON2     0x202
  57 #define REG_RFCON3     0x203
  58 #define REG_RFCON5     0x205
  59 #define REG_RFCON6     0x206
  60 #define REG_RFCON7     0x207
  61 #define REG_RFCON8     0x208
  62 #define REG_RSSI       0x210
  63 #define REG_SLPCON0    0x211  /* Sleep Clock Control Registers */
  64 #define REG_SLPCON1    0x220
  65 #define REG_WAKETIMEL  0x222  /* Wake-up Time Match Value Low */
  66 #define REG_WAKETIMEH  0x223  /* Wake-up Time Match Value High */
  67 #define REG_RX_FIFO    0x300  /* Receive FIFO */
  68
  69 /* Device configuration: Only channels 11-26 on page 0 are supported. */
  70 #define MRF24J40_CHAN_MIN 11
  71 #define MRF24J40_CHAN_MAX 26
  72 #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
  73                       - ((u32)1 << MRF24J40_CHAN_MIN))
  74
  75 #define TX_FIFO_SIZE 128 /* From datasheet */
  76 #define RX_FIFO_SIZE 144 /* From datasheet */
  77 #define SET_CHANNEL_DELAY_US 192 /* From datasheet */
  78
  79 /* Device Private Data */
  80 struct mrf24j40 {
  81         struct spi_device *spi;
  82         struct ieee802154_dev *dev;
  83
  84         struct mutex buffer_mutex; /* only used to protect buf */
  85         struct completion tx_complete;
  86         struct work_struct irqwork;
  87         u8 *buf; /* 3 bytes. Used for SPI single-register transfers. */
  88 };
  89
  90 /* Read/Write SPI Commands for Short and Long Address registers. */
  91 #define MRF24J40_READSHORT(reg) ((reg) << 1)
  92 #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
  93 #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
  94 #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
  95
  96 /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
  97 #define MAX_SPI_SPEED_HZ 10000000
  98
  99 #define printdev(X) (&X->spi->dev)
 100
 101 static int write_short_reg(struct mrf24j40 *devrec, u8 reg, u8 value)
 102 {
 103         int ret;
 104         struct spi_message msg;
 105         struct spi_transfer xfer = {
 106                 .len = 2,
 107                 .tx_buf = devrec->buf,
 108                 .rx_buf = devrec->buf,
 109         };
 110
 111         spi_message_init(&msg);
 112         spi_message_add_tail(&xfer, &msg);
 113
 114         mutex_lock(&devrec->buffer_mutex);
 115         devrec->buf[0] = MRF24J40_WRITESHORT(reg);
 116         devrec->buf[1] = value;
 117
 118         ret = spi_sync(devrec->spi, &msg);
 119         if (ret)
 120                 dev_err(printdev(devrec),
 121                         "SPI write Failed for short register 0x%hhx\n", reg);
 122
 123         mutex_unlock(&devrec->buffer_mutex);
 124         return ret;
 125 }
 126
 127 static int read_short_reg(struct mrf24j40 *devrec, u8 reg, u8 *val)
 128 {
 129         int ret = -1;
 130         struct spi_message msg;
 131         struct spi_transfer xfer = {
 132                 .len = 2,
 133                 .tx_buf = devrec->buf,
 134                 .rx_buf = devrec->buf,
 135         };
 136
 137         spi_message_init(&msg);
 138         spi_message_add_tail(&xfer, &msg);
 139
 140         mutex_lock(&devrec->buffer_mutex);
 141         devrec->buf[0] = MRF24J40_READSHORT(reg);
 142         devrec->buf[1] = 0;
 143
 144         ret = spi_sync(devrec->spi, &msg);
 145         if (ret)
 146                 dev_err(printdev(devrec),
 147                         "SPI read Failed for short register 0x%hhx\n", reg);
 148         else
 149                 *val = devrec->buf[1];
 150
 151         mutex_unlock(&devrec->buffer_mutex);
 152         return ret;
 153 }
 154
 155 static int read_long_reg(struct mrf24j40 *devrec, u16 reg, u8 *value)
 156 {
 157         int ret;
 158         u16 cmd;
 159         struct spi_message msg;
 160         struct spi_transfer xfer = {
 161                 .len = 3,
 162                 .tx_buf = devrec->buf,
 163                 .rx_buf = devrec->buf,
 164         };
 165
 166         spi_message_init(&msg);
 167         spi_message_add_tail(&xfer, &msg);
 168
 169         cmd = MRF24J40_READLONG(reg);
 170         mutex_lock(&devrec->buffer_mutex);
 171         devrec->buf[0] = cmd >> 8 & 0xff;
 172         devrec->buf[1] = cmd & 0xff;
 173         devrec->buf[2] = 0;
 174
 175         ret = spi_sync(devrec->spi, &msg);
 176         if (ret)
 177                 dev_err(printdev(devrec),
 178                         "SPI read Failed for long register 0x%hx\n", reg);
 179         else
 180                 *value = devrec->buf[2];
 181
 182         mutex_unlock(&devrec->buffer_mutex);
 183         return ret;
 184 }
 185
 186 static int write_long_reg(struct mrf24j40 *devrec, u16 reg, u8 val)
 187 {
 188         int ret;
 189         u16 cmd;
 190         struct spi_message msg;
 191         struct spi_transfer xfer = {
 192                 .len = 3,
 193                 .tx_buf = devrec->buf,
 194                 .rx_buf = devrec->buf,
 195         };
 196
 197         spi_message_init(&msg);
 198         spi_message_add_tail(&xfer, &msg);
 199
 200         cmd = MRF24J40_WRITELONG(reg);
 201         mutex_lock(&devrec->buffer_mutex);
 202         devrec->buf[0] = cmd >> 8 & 0xff;
 203         devrec->buf[1] = cmd & 0xff;
 204         devrec->buf[2] = val;
 205
 206         ret = spi_sync(devrec->spi, &msg);
 207         if (ret)
 208                 dev_err(printdev(devrec),
 209                         "SPI write Failed for long register 0x%hx\n", reg);
 210
 211         mutex_unlock(&devrec->buffer_mutex);
 212         return ret;
 213 }
 214
 215 /* This function relies on an undocumented write method. Once a write command
 216    and address is set, as many bytes of data as desired can be clocked into
 217    the device. The datasheet only shows setting one byte at a time. */
 218 static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
 219                         const u8 *data, size_t length)
 220 {
 221         int ret;
 222         u16 cmd;
 223         u8 lengths[2];
 224         struct spi_message msg;
 225         struct spi_transfer addr_xfer = {
 226                 .len = 2,
 227                 .tx_buf = devrec->buf,
 228         };
 229         struct spi_transfer lengths_xfer = {
 230                 .len = 2,
 231                 .tx_buf = &lengths, /* TODO: Is DMA really required for SPI? */
 232         };
 233         struct spi_transfer data_xfer = {
 234                 .len = length,
 235                 .tx_buf = data,
 236         };
 237
 238         /* Range check the length. 2 bytes are used for the length fields.*/
 239         if (length > TX_FIFO_SIZE-2) {
 240                 dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
 241                 length = TX_FIFO_SIZE-2;
 242         }
 243
 244         spi_message_init(&msg);
 245         spi_message_add_tail(&addr_xfer, &msg);
 246         spi_message_add_tail(&lengths_xfer, &msg);
 247         spi_message_add_tail(&data_xfer, &msg);
 248
 249         cmd = MRF24J40_WRITELONG(reg);
 250         mutex_lock(&devrec->buffer_mutex);
 251         devrec->buf[0] = cmd >> 8 & 0xff;
 252         devrec->buf[1] = cmd & 0xff;
 253         lengths[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
 254         lengths[1] = length; /* Total length */
 255
 256         ret = spi_sync(devrec->spi, &msg);
 257         if (ret)
 258                 dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
 259
 260         mutex_unlock(&devrec->buffer_mutex);
 261         return ret;
 262 }
 263
 264 static int mrf24j40_read_rx_buf(struct mrf24j40 *devrec,
 265                                 u8 *data, u8 *len, u8 *lqi)
 266 {
 267         u8 rx_len;
 268         u8 addr[2];
 269         u8 lqi_rssi[2];
 270         u16 cmd;
 271         int ret;
 272         struct spi_message msg;
 273         struct spi_transfer addr_xfer = {
 274                 .len = 2,
 275                 .tx_buf = &addr,
 276         };
 277         struct spi_transfer data_xfer = {
 278                 .len = 0x0, /* set below */
 279                 .rx_buf = data,
 280         };
 281         struct spi_transfer status_xfer = {
 282                 .len = 2,
 283                 .rx_buf = &lqi_rssi,
 284         };
 285
 286         /* Get the length of the data in the RX FIFO. The length in this
 287          * register exclues the 1-byte length field at the beginning. */
 288         ret = read_long_reg(devrec, REG_RX_FIFO, &rx_len);
 289         if (ret)
 290                 goto out;
 291
 292         /* Range check the RX FIFO length, accounting for the one-byte
 293          * length field at the begining. */
 294         if (rx_len > RX_FIFO_SIZE-1) {
 295                 dev_err(printdev(devrec), "Invalid length read from device. Performing short read.\n");
 296                 rx_len = RX_FIFO_SIZE-1;
 297         }
 298
 299         if (rx_len > *len) {
 300                 /* Passed in buffer wasn't big enough. Should never happen. */
 301                 dev_err(printdev(devrec), "Buffer not big enough. Performing short read\n");
 302                 rx_len = *len;
 303         }
 304
 305         /* Set up the commands to read the data. */
 306         cmd = MRF24J40_READLONG(REG_RX_FIFO+1);
 307         addr[0] = cmd >> 8 & 0xff;
 308         addr[1] = cmd & 0xff;
 309         data_xfer.len = rx_len;
 310
 311         spi_message_init(&msg);
 312         spi_message_add_tail(&addr_xfer, &msg);
 313         spi_message_add_tail(&data_xfer, &msg);
 314         spi_message_add_tail(&status_xfer, &msg);
 315
 316         ret = spi_sync(devrec->spi, &msg);
 317         if (ret) {
 318                 dev_err(printdev(devrec), "SPI RX Buffer Read Failed.\n");
 319                 goto out;
 320         }
 321
 322         *lqi = lqi_rssi[0];
 323         *len = rx_len;
 324
 325 #ifdef DEBUG
 326         print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ",
 327                 DUMP_PREFIX_OFFSET, 16, 1, data, *len, 0);
 328         printk(KERN_DEBUG "mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
 329                 lqi_rssi[0], lqi_rssi[1]);
 330 #endif
 331
 332 out:
 333         return ret;
 334 }
 335
 336 static int mrf24j40_tx(struct ieee802154_dev *dev, struct sk_buff *skb)
 337 {
 338         struct mrf24j40 *devrec = dev->priv;
 339         u8 val;
 340         int ret = 0;
 341
 342         dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
 343
 344         ret = write_tx_buf(devrec, 0x000, skb->data, skb->len);
 345         if (ret)
 346                 goto err;
 347
 348         /* Set TXNTRIG bit of TXNCON to send packet */
 349         ret = read_short_reg(devrec, REG_TXNCON, &val);
 350         if (ret)
 351                 goto err;
 352         val |= 0x1;
 353         /* Set TXNACKREQ if the ACK bit is set in the packet. */
 354         if (skb->data[0] & IEEE802154_FC_ACK_REQ)
 355                 val |= 0x4;
 356         write_short_reg(devrec, REG_TXNCON, val);
 357
 358         INIT_COMPLETION(devrec->tx_complete);
 359
 360         /* Wait for the device to send the TX complete interrupt. */
 361         ret = wait_for_completion_interruptible_timeout(
 362                                                 &devrec->tx_complete,
 363                                                 5 * HZ);
 364         if (ret == -ERESTARTSYS)
 365                 goto err;
 366         if (ret == 0) {
 367                 dev_warn(printdev(devrec), "Timeout waiting for TX interrupt\n");
 368                 ret = -ETIMEDOUT;
 369                 goto err;
 370         }
 371
 372         /* Check for send error from the device. */
 373         ret = read_short_reg(devrec, REG_TXSTAT, &val);
 374         if (ret)
 375                 goto err;
 376         if (val & 0x1) {
 377                 dev_dbg(printdev(devrec), "Error Sending. Retry count exceeded\n");
 378                 ret = -ECOMM; /* TODO: Better error code ? */
 379         } else
 380                 dev_dbg(printdev(devrec), "Packet Sent\n");
 381
 382 err:
 383
 384         return ret;
 385 }
 386
 387 static int mrf24j40_ed(struct ieee802154_dev *dev, u8 *level)
 388 {
 389         /* TODO: */
 390         printk(KERN_WARNING "mrf24j40: ed not implemented\n");
 391         *level = 0;
 392         return 0;
 393 }
 394
 395 static int mrf24j40_start(struct ieee802154_dev *dev)
 396 {
 397         struct mrf24j40 *devrec = dev->priv;
 398         u8 val;
 399         int ret;
 400
 401         dev_dbg(printdev(devrec), "start\n");
 402
 403         ret = read_short_reg(devrec, REG_INTCON, &val);
 404         if (ret)
 405                 return ret;
 406         val &= ~(0x1|0x8); /* Clear TXNIE and RXIE. Enable interrupts */
 407         write_short_reg(devrec, REG_INTCON, val);
 408
 409         return 0;
 410 }
 411
 412 static void mrf24j40_stop(struct ieee802154_dev *dev)
 413 {
 414         struct mrf24j40 *devrec = dev->priv;
 415         u8 val;
 416         int ret;
 417         dev_dbg(printdev(devrec), "stop\n");
 418
 419         ret = read_short_reg(devrec, REG_INTCON, &val);
 420         if (ret)
 421                 return;
 422         val |= 0x1|0x8; /* Set TXNIE and RXIE. Disable Interrupts */
 423         write_short_reg(devrec, REG_INTCON, val);
 424
 425         return;
 426 }
 427
 428 static int mrf24j40_set_channel(struct ieee802154_dev *dev,
 429                                 int page, int channel)
 430 {
 431         struct mrf24j40 *devrec = dev->priv;
 432         u8 val;
 433         int ret;
 434
 435         dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
 436
 437         WARN_ON(page != 0);
 438         WARN_ON(channel < MRF24J40_CHAN_MIN);
 439         WARN_ON(channel > MRF24J40_CHAN_MAX);
 440
 441         /* Set Channel TODO */
 442         val = (channel-11) << 4 | 0x03;
 443         write_long_reg(devrec, REG_RFCON0, val);
 444
 445         /* RF Reset */
 446         ret = read_short_reg(devrec, REG_RFCTL, &val);
 447         if (ret)
 448                 return ret;
 449         val |= 0x04;
 450         write_short_reg(devrec, REG_RFCTL, val);
 451         val &= ~0x04;
 452         write_short_reg(devrec, REG_RFCTL, val);
 453
 454         udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
 455
 456         return 0;
 457 }
 458
 459 static int mrf24j40_filter(struct ieee802154_dev *dev,
 460                            struct ieee802154_hw_addr_filt *filt,
 461                            unsigned long changed)
 462 {
 463         struct mrf24j40 *devrec = dev->priv;
 464
 465         dev_dbg(printdev(devrec), "filter\n");
 466
 467         if (changed & IEEE802515_AFILT_SADDR_CHANGED) {
 468                 /* Short Addr */
 469                 u8 addrh, addrl;
 470                 addrh = filt->short_addr >> 8 & 0xff;
 471                 addrl = filt->short_addr & 0xff;
 472
 473                 write_short_reg(devrec, REG_SADRH, addrh);
 474                 write_short_reg(devrec, REG_SADRL, addrl);
 475                 dev_dbg(printdev(devrec),
 476                         "Set short addr to %04hx\n", filt->short_addr);
 477         }
 478
 479         if (changed & IEEE802515_AFILT_IEEEADDR_CHANGED) {
 480                 /* Device Address */
 481                 int i;
 482                 for (i = 0; i < 8; i++)
 483                         write_short_reg(devrec, REG_EADR0+i,
 484                                         filt->ieee_addr[7-i]);
 485
 486 #ifdef DEBUG
 487                 printk(KERN_DEBUG "Set long addr to: ");
 488                 for (i = 0; i < 8; i++)
 489                         printk("%02hhx ", filt->ieee_addr[i]);
 490                 printk(KERN_DEBUG "\n");
 491 #endif
 492         }
 493
 494         if (changed & IEEE802515_AFILT_PANID_CHANGED) {
 495                 /* PAN ID */
 496                 u8 panidl, panidh;
 497                 panidh = filt->pan_id >> 8 & 0xff;
 498                 panidl = filt->pan_id & 0xff;
 499                 write_short_reg(devrec, REG_PANIDH, panidh);
 500                 write_short_reg(devrec, REG_PANIDL, panidl);
 501
 502                 dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
 503         }
 504
 505         if (changed & IEEE802515_AFILT_PANC_CHANGED) {
 506                 /* Pan Coordinator */
 507                 u8 val;
 508                 int ret;
 509
 510                 ret = read_short_reg(devrec, REG_RXMCR, &val);
 511                 if (ret)
 512                         return ret;
 513                 if (filt->pan_coord)
 514                         val |= 0x8;
 515                 else
 516                         val &= ~0x8;
 517                 write_short_reg(devrec, REG_RXMCR, val);
 518
 519                 /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
 520                  * REG_ORDER is maintained as default (no beacon/superframe).
 521                  */
 522
 523                 dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
 524                                         filt->pan_coord ? "on" : "off");
 525         }
 526
 527         return 0;
 528 }
 529
 530 static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
 531 {
 532         u8 len = RX_FIFO_SIZE;
 533         u8 lqi = 0;
 534         u8 val;
 535         int ret = 0;
 536         struct sk_buff *skb;
 537
 538         /* Turn off reception of packets off the air. This prevents the
 539          * device from overwriting the buffer while we're reading it. */
 540         ret = read_short_reg(devrec, REG_BBREG1, &val);
 541         if (ret)
 542                 goto out;
 543         val |= 4; /* SET RXDECINV */
 544         write_short_reg(devrec, REG_BBREG1, val);
 545
 546         skb = alloc_skb(len, GFP_KERNEL);
 547         if (!skb) {
 548                 ret = -ENOMEM;
 549                 goto out;
 550         }
 551
 552         ret = mrf24j40_read_rx_buf(devrec, skb_put(skb, len), &len, &lqi);
 553         if (ret < 0) {
 554                 dev_err(printdev(devrec), "Failure reading RX FIFO\n");
 555                 kfree_skb(skb);
 556                 ret = -EINVAL;
 557                 goto out;
 558         }
 559
 560         /* Cut off the checksum */
 561         skb_trim(skb, len-2);
 562
 563         /* TODO: Other drivers call ieee20154_rx_irqsafe() here (eg: cc2040,
 564          * also from a workqueue).  I think irqsafe is not necessary here.
 565          * Can someone confirm? */
 566         ieee802154_rx_irqsafe(devrec->dev, skb, lqi);
 567
 568         dev_dbg(printdev(devrec), "RX Handled\n");
 569
 570 out:
 571         /* Turn back on reception of packets off the air. */
 572         ret = read_short_reg(devrec, REG_BBREG1, &val);
 573         if (ret)
 574                 return ret;
 575         val &= ~0x4; /* Clear RXDECINV */
 576         write_short_reg(devrec, REG_BBREG1, val);
 577
 578         return ret;
 579 }
 580
 581 static struct ieee802154_ops mrf24j40_ops = {
 582         .owner = THIS_MODULE,
 583         .xmit = mrf24j40_tx,
 584         .ed = mrf24j40_ed,
 585         .start = mrf24j40_start,
 586         .stop = mrf24j40_stop,
 587         .set_channel = mrf24j40_set_channel,
 588         .set_hw_addr_filt = mrf24j40_filter,
 589 };
 590
 591 static irqreturn_t mrf24j40_isr(int irq, void *data)
 592 {
 593         struct mrf24j40 *devrec = data;
 594
 595         disable_irq_nosync(irq);
 596
 597         schedule_work(&devrec->irqwork);
 598
 599         return IRQ_HANDLED;
 600 }
 601
 602 static void mrf24j40_isrwork(struct work_struct *work)
 603 {
 604         struct mrf24j40 *devrec = container_of(work, struct mrf24j40, irqwork);
 605         u8 intstat;
 606         int ret;
 607
 608         /* Read the interrupt status */
 609         ret = read_short_reg(devrec, REG_INTSTAT, &intstat);
 610         if (ret)
 611                 goto out;
 612
 613         /* Check for TX complete */
 614         if (intstat & 0x1)
 615                 complete(&devrec->tx_complete);
 616
 617         /* Check for Rx */
 618         if (intstat & 0x8)
 619                 mrf24j40_handle_rx(devrec);
 620
 621 out:
 622         enable_irq(devrec->spi->irq);
 623 }
 624
 625 static int mrf24j40_probe(struct spi_device *spi)
 626 {
 627         int ret = -ENOMEM;
 628         u8 val;
 629         struct mrf24j40 *devrec;
 630         struct pinctrl *pinctrl;
 631
 632         printk(KERN_INFO "mrf24j40: probe(). IRQ: %d\n", spi->irq);
 633
 634         devrec = kzalloc(sizeof(struct mrf24j40), GFP_KERNEL);
 635         if (!devrec)
 636                 goto err_devrec;
 637         devrec->buf = kzalloc(3, GFP_KERNEL);
 638         if (!devrec->buf)
 639                 goto err_buf;
 640
 641         pinctrl = devm_pinctrl_get_select_default(&spi->dev);
 642         if (IS_ERR(pinctrl))
 643                 dev_warn(&spi->dev,
 644                         "pinctrl pins are not configured from the driver");
 645
 646         spi->mode = SPI_MODE_0; /* TODO: Is this appropriate for right here? */
 647         if (spi->max_speed_hz > MAX_SPI_SPEED_HZ)
 648                 spi->max_speed_hz = MAX_SPI_SPEED_HZ;
 649
 650         mutex_init(&devrec->buffer_mutex);
 651         init_completion(&devrec->tx_complete);
 652         INIT_WORK(&devrec->irqwork, mrf24j40_isrwork);
 653         devrec->spi = spi;
 654         spi_set_drvdata(spi, devrec);
 655
 656         /* Register with the 802154 subsystem */
 657
 658         devrec->dev = ieee802154_alloc_device(0, &mrf24j40_ops);
 659         if (!devrec->dev)
 660                 goto err_alloc_dev;
 661
 662         devrec->dev->priv = devrec;
 663         devrec->dev->parent = &devrec->spi->dev;
 664         devrec->dev->phy->channels_supported[0] = CHANNEL_MASK;
 665         devrec->dev->flags = IEEE802154_HW_OMIT_CKSUM|IEEE802154_HW_AACK;
 666
 667         dev_dbg(printdev(devrec), "registered mrf24j40\n");
 668         ret = ieee802154_register_device(devrec->dev);
 669         if (ret)
 670                 goto err_register_device;
 671
 672         /* Initialize the device.
 673                 From datasheet section 3.2: Initialization. */
 674         write_short_reg(devrec, REG_SOFTRST, 0x07);
 675         write_short_reg(devrec, REG_PACON2, 0x98);
 676         write_short_reg(devrec, REG_TXSTBL, 0x95);
 677         write_long_reg(devrec, REG_RFCON0, 0x03);
 678         write_long_reg(devrec, REG_RFCON1, 0x01);
 679         write_long_reg(devrec, REG_RFCON2, 0x80);
 680         write_long_reg(devrec, REG_RFCON6, 0x90);
 681         write_long_reg(devrec, REG_RFCON7, 0x80);
 682         write_long_reg(devrec, REG_RFCON8, 0x10);
 683         write_long_reg(devrec, REG_SLPCON1, 0x21);
 684         write_short_reg(devrec, REG_BBREG2, 0x80);
 685         write_short_reg(devrec, REG_CCAEDTH, 0x60);
 686         write_short_reg(devrec, REG_BBREG6, 0x40);
 687         write_short_reg(devrec, REG_RFCTL, 0x04);
 688         write_short_reg(devrec, REG_RFCTL, 0x0);
 689         udelay(192);
 690
 691         /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
 692         ret = read_short_reg(devrec, REG_RXMCR, &val);
 693         if (ret)
 694                 goto err_read_reg;
 695         val &= ~0x3; /* Clear RX mode (normal) */
 696         write_short_reg(devrec, REG_RXMCR, val);
 697
 698         ret = request_irq(spi->irq,
 699                           mrf24j40_isr,
 700                           IRQF_TRIGGER_FALLING,
 701                           dev_name(&spi->dev),
 702                           devrec);
 703
 704         if (ret) {
 705                 dev_err(printdev(devrec), "Unable to get IRQ");
 706                 goto err_irq;
 707         }
 708
 709         return 0;
 710
 711 err_irq:
 712 err_read_reg:
 713         ieee802154_unregister_device(devrec->dev);
 714 err_register_device:
 715         ieee802154_free_device(devrec->dev);
 716 err_alloc_dev:
 717         kfree(devrec->buf);
 718 err_buf:
 719         kfree(devrec);
 720 err_devrec:
 721         return ret;
 722 }
 723
 724 static int mrf24j40_remove(struct spi_device *spi)
 725 {
 726         struct mrf24j40 *devrec = spi_get_drvdata(spi);
 727
 728         dev_dbg(printdev(devrec), "remove\n");
 729
 730         free_irq(spi->irq, devrec);
 731         flush_work(&devrec->irqwork); /* TODO: Is this the right call? */
 732         ieee802154_unregister_device(devrec->dev);
 733         ieee802154_free_device(devrec->dev);
 734         /* TODO: Will ieee802154_free_device() wait until ->xmit() is
 735          * complete? */
 736
 737         /* Clean up the SPI stuff. */
 738         spi_set_drvdata(spi, NULL);
 739         kfree(devrec->buf);
 740         kfree(devrec);
 741         return 0;
 742 }
 743
 744 static const struct spi_device_id mrf24j40_ids[] = {
 745         { "mrf24j40", 0 },
 746         { "mrf24j40ma", 0 },
 747         { },
 748 };
 749 MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
 750
 751 static struct spi_driver mrf24j40_driver = {
 752         .driver = {
 753                 .name = "mrf24j40",
 754                 .bus = &spi_bus_type,
 755                 .owner = THIS_MODULE,
 756         },
 757         .id_table = mrf24j40_ids,
 758         .probe = mrf24j40_probe,
 759         .remove = mrf24j40_remove,
 760 };
 761
 762 module_spi_driver(mrf24j40_driver);
 763
 764 MODULE_LICENSE("GPL");
 765 MODULE_AUTHOR("Alan Ott");
 766 MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");