projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
[PATCH] smsc-ircc2: add to sysfs as platform device, new PM
[deliverable/linux.git] / drivers / net / irda / smsc-ircc2.c
1 /*********************************************************************
2 * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
3 *
4 * Description: Driver for the SMC Infrared Communications Controller
5 * Status: Experimental.
6 * Author: Daniele Peri (peri@csai.unipa.it)
7 * Created at:
8 * Modified at:
9 * Modified by:
10 *
11 * Copyright (c) 2002 Daniele Peri
12 * All Rights Reserved.
13 * Copyright (c) 2002 Jean Tourrilhes
14 *
15 *
16 * Based on smc-ircc.c:
17 *
18 * Copyright (c) 2001 Stefani Seibold
19 * Copyright (c) 1999-2001 Dag Brattli
20 * Copyright (c) 1998-1999 Thomas Davis,
21 *
22 * and irport.c:
23 *
24 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
25 *
26 *
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License as
29 * published by the Free Software Foundation; either version 2 of
30 * the License, or (at your option) any later version.
31 *
32 * This program is distributed in the hope that it will be useful,
33 * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 * GNU General Public License for more details.
36 *
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, write to the Free Software
39 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40 * MA 02111-1307 USA
41 *
42 ********************************************************************/
43
44 #include <linux/module.h>
45 #include <linux/kernel.h>
46 #include <linux/types.h>
47 #include <linux/skbuff.h>
48 #include <linux/netdevice.h>
49 #include <linux/ioport.h>
50 #include <linux/delay.h>
51 #include <linux/slab.h>
52 #include <linux/init.h>
53 #include <linux/rtnetlink.h>
54 #include <linux/serial_reg.h>
55 #include <linux/dma-mapping.h>
56
57 #include <asm/io.h>
58 #include <asm/dma.h>
59 #include <asm/byteorder.h>
60
61 #include <linux/spinlock.h>
62 #include <linux/pm.h>
63
64 #include <net/irda/wrapper.h>
65 #include <net/irda/irda.h>
66 #include <net/irda/irda_device.h>
67
68 #include "smsc-ircc2.h"
69 #include "smsc-sio.h"
70
71
72 MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
73 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
74 MODULE_LICENSE("GPL");
75
76 static int ircc_dma = 255;
77 module_param(ircc_dma, int, 0);
78 MODULE_PARM_DESC(ircc_dma, "DMA channel");
79
80 static int ircc_irq = 255;
81 module_param(ircc_irq, int, 0);
82 MODULE_PARM_DESC(ircc_irq, "IRQ line");
83
84 static int ircc_fir;
85 module_param(ircc_fir, int, 0);
86 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
87
88 static int ircc_sir;
89 module_param(ircc_sir, int, 0);
90 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
91
92 static int ircc_cfg;
93 module_param(ircc_cfg, int, 0);
94 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
95
96 static int ircc_transceiver;
97 module_param(ircc_transceiver, int, 0);
98 MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
99
100 /* Types */
101
102 struct smsc_transceiver {
103 char *name;
104 void (*set_for_speed)(int fir_base, u32 speed);
105 int (*probe)(int fir_base);
106 };
107
108 struct smsc_chip {
109 char *name;
110 #if 0
111 u8 type;
112 #endif
113 u16 flags;
114 u8 devid;
115 u8 rev;
116 };
117
118 struct smsc_chip_address {
119 unsigned int cfg_base;
120 unsigned int type;
121 };
122
123 /* Private data for each instance */
124 struct smsc_ircc_cb {
125 struct net_device *netdev; /* Yes! we are some kind of netdevice */
126 struct net_device_stats stats;
127 struct irlap_cb *irlap; /* The link layer we are binded to */
128
129 chipio_t io; /* IrDA controller information */
130 iobuff_t tx_buff; /* Transmit buffer */
131 iobuff_t rx_buff; /* Receive buffer */
132 dma_addr_t tx_buff_dma;
133 dma_addr_t rx_buff_dma;
134
135 struct qos_info qos; /* QoS capabilities for this device */
136
137 spinlock_t lock; /* For serializing operations */
138
139 __u32 new_speed;
140 __u32 flags; /* Interface flags */
141
142 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
143 int tx_len; /* Number of frames in tx_buff */
144
145 int transceiver;
146 struct platform_device *pldev;
147 };
148
149 /* Constants */
150
151 #define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
152
153 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
154 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
155 #define SMSC_IRCC2_C_NET_TIMEOUT 0
156 #define SMSC_IRCC2_C_SIR_STOP 0
157
158 static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
159
160 /* Prototypes */
161
162 static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
163 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
164 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
165 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
166 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
167 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
168 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
169 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
170 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
171 static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
172 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
173 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
174 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
175 static void smsc_ircc_change_speed(void *priv, u32 speed);
176 static void smsc_ircc_set_sir_speed(void *priv, u32 speed);
177 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
178 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
179 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
180 #if SMSC_IRCC2_C_SIR_STOP
181 static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
182 #endif
183 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
184 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
185 static int smsc_ircc_net_open(struct net_device *dev);
186 static int smsc_ircc_net_close(struct net_device *dev);
187 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
188 #if SMSC_IRCC2_C_NET_TIMEOUT
189 static void smsc_ircc_timeout(struct net_device *dev);
190 #endif
191 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
192 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
193 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
194 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
195 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
196
197 /* Probing */
198 static int __init smsc_ircc_look_for_chips(void);
199 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
200 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
201 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
202 static int __init smsc_superio_fdc(unsigned short cfg_base);
203 static int __init smsc_superio_lpc(unsigned short cfg_base);
204
205 /* Transceivers specific functions */
206
207 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
208 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
209 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
210 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
211 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
212 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
213
214 /* Power Management */
215
216 static int smsc_ircc_suspend(struct device *dev, pm_message_t state, u32 level);
217 static int smsc_ircc_resume(struct device *dev, u32 level);
218
219 static struct device_driver smsc_ircc_driver = {
220 .name = SMSC_IRCC2_DRIVER_NAME,
221 .bus = &platform_bus_type,
222 .suspend = smsc_ircc_suspend,
223 .resume = smsc_ircc_resume,
224 };
225
226 /* Transceivers for SMSC-ircc */
227
228 static struct smsc_transceiver smsc_transceivers[] =
229 {
230 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
231 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
232 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
233 { NULL, NULL }
234 };
235 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
236
237 /* SMC SuperIO chipsets definitions */
238
239 #define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
240 #define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
241 #define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
242 #define SIR 0 /* SuperIO Chip has only slow IRDA */
243 #define FIR 4 /* SuperIO Chip has fast IRDA */
244 #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
245
246 static struct smsc_chip __initdata fdc_chips_flat[] =
247 {
248 /* Base address 0x3f0 or 0x370 */
249 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
250 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
251 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
252 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
253 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
254 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
255 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
256 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
257 { NULL }
258 };
259
260 static struct smsc_chip __initdata fdc_chips_paged[] =
261 {
262 /* Base address 0x3f0 or 0x370 */
263 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
264 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
265 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
266 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
267 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
268 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
269 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
270 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
271 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
272 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
273 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
274 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
275 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
276 { NULL }
277 };
278
279 static struct smsc_chip __initdata lpc_chips_flat[] =
280 {
281 /* Base address 0x2E or 0x4E */
282 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
283 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
284 { NULL }
285 };
286
287 static struct smsc_chip __initdata lpc_chips_paged[] =
288 {
289 /* Base address 0x2E or 0x4E */
290 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
291 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
292 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
293 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
294 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
295 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
296 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
297 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
298 { NULL }
299 };
300
301 #define SMSCSIO_TYPE_FDC 1
302 #define SMSCSIO_TYPE_LPC 2
303 #define SMSCSIO_TYPE_FLAT 4
304 #define SMSCSIO_TYPE_PAGED 8
305
306 static struct smsc_chip_address __initdata possible_addresses[] =
307 {
308 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
309 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
310 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
311 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
312 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
313 { 0, 0 }
314 };
315
316 /* Globals */
317
318 static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
319 static unsigned short dev_count;
320
321 static inline void register_bank(int iobase, int bank)
322 {
323 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
324 iobase + IRCC_MASTER);
325 }
326
327
328 /*******************************************************************************
329 *
330 *
331 * SMSC-ircc stuff
332 *
333 *
334 *******************************************************************************/
335
336 /*
337 * Function smsc_ircc_init ()
338 *
339 * Initialize chip. Just try to find out how many chips we are dealing with
340 * and where they are
341 */
342 static int __init smsc_ircc_init(void)
343 {
344 int ret;
345
346 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
347
348 ret = driver_register(&smsc_ircc_driver);
349 if (ret) {
350 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
351 return ret;
352 }
353
354 dev_count = 0;
355
356 if (ircc_fir > 0 && ircc_sir > 0) {
357 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
358 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
359
360 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
361 ret = -ENODEV;
362 } else {
363
364 /* try user provided configuration register base address */
365 if (ircc_cfg > 0) {
366 IRDA_MESSAGE(" Overriding configuration address "
367 "0x%04x\n", ircc_cfg);
368 if (!smsc_superio_fdc(ircc_cfg))
369 ret = 0;
370 if (!smsc_superio_lpc(ircc_cfg))
371 ret = 0;
372 }
373
374 if (smsc_ircc_look_for_chips() > 0)
375 ret = 0;
376 }
377
378 if (ret)
379 driver_unregister(&smsc_ircc_driver);
380
381 return ret;
382 }
383
384 /*
385 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
386 *
387 * Try to open driver instance
388 *
389 */
390 static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
391 {
392 struct smsc_ircc_cb *self;
393 struct net_device *dev;
394 int err;
395
396 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
397
398 err = smsc_ircc_present(fir_base, sir_base);
399 if (err)
400 goto err_out;
401
402 err = -ENOMEM;
403 if (dev_count >= ARRAY_SIZE(dev_self)) {
404 IRDA_WARNING("%s(), too many devices!\n", __FUNCTION__);
405 goto err_out1;
406 }
407
408 /*
409 * Allocate new instance of the driver
410 */
411 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
412 if (!dev) {
413 IRDA_WARNING("%s() can't allocate net device\n", __FUNCTION__);
414 goto err_out1;
415 }
416
417 SET_MODULE_OWNER(dev);
418
419 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
420 #if SMSC_IRCC2_C_NET_TIMEOUT
421 dev->tx_timeout = smsc_ircc_timeout;
422 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
423 #endif
424 dev->open = smsc_ircc_net_open;
425 dev->stop = smsc_ircc_net_close;
426 dev->do_ioctl = smsc_ircc_net_ioctl;
427 dev->get_stats = smsc_ircc_net_get_stats;
428
429 self = dev->priv;
430 self->netdev = dev;
431
432 /* Make ifconfig display some details */
433 dev->base_addr = self->io.fir_base = fir_base;
434 dev->irq = self->io.irq = irq;
435
436 /* Need to store self somewhere */
437 dev_self[dev_count] = self;
438 spin_lock_init(&self->lock);
439
440 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
441 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
442
443 self->rx_buff.head =
444 dma_alloc_coherent(NULL, self->rx_buff.truesize,
445 &self->rx_buff_dma, GFP_KERNEL);
446 if (self->rx_buff.head == NULL) {
447 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
448 driver_name);
449 goto err_out2;
450 }
451
452 self->tx_buff.head =
453 dma_alloc_coherent(NULL, self->tx_buff.truesize,
454 &self->tx_buff_dma, GFP_KERNEL);
455 if (self->tx_buff.head == NULL) {
456 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
457 driver_name);
458 goto err_out3;
459 }
460
461 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
462 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
463
464 self->rx_buff.in_frame = FALSE;
465 self->rx_buff.state = OUTSIDE_FRAME;
466 self->tx_buff.data = self->tx_buff.head;
467 self->rx_buff.data = self->rx_buff.head;
468
469 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
470 smsc_ircc_setup_qos(self);
471 smsc_ircc_init_chip(self);
472
473 if (ircc_transceiver > 0 &&
474 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
475 self->transceiver = ircc_transceiver;
476 else
477 smsc_ircc_probe_transceiver(self);
478
479 err = register_netdev(self->netdev);
480 if (err) {
481 IRDA_ERROR("%s, Network device registration failed!\n",
482 driver_name);
483 goto err_out4;
484 }
485
486 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
487 dev_count, NULL, 0);
488 if (IS_ERR(self->pldev)) {
489 err = PTR_ERR(self->pldev);
490 goto err_out5;
491 }
492 dev_set_drvdata(&self->pldev->dev, self);
493
494 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
495 dev_count++;
496
497 return 0;
498
499 err_out5:
500 unregister_netdev(self->netdev);
501
502 err_out4:
503 dma_free_coherent(NULL, self->tx_buff.truesize,
504 self->tx_buff.head, self->tx_buff_dma);
505 err_out3:
506 dma_free_coherent(NULL, self->rx_buff.truesize,
507 self->rx_buff.head, self->rx_buff_dma);
508 err_out2:
509 free_netdev(self->netdev);
510 dev_self[dev_count] = NULL;
511 err_out1:
512 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
513 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
514 err_out:
515 return err;
516 }
517
518 /*
519 * Function smsc_ircc_present(fir_base, sir_base)
520 *
521 * Check the smsc-ircc chip presence
522 *
523 */
524 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
525 {
526 unsigned char low, high, chip, config, dma, irq, version;
527
528 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
529 driver_name)) {
530 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
531 __FUNCTION__, fir_base);
532 goto out1;
533 }
534
535 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
536 driver_name)) {
537 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
538 __FUNCTION__, sir_base);
539 goto out2;
540 }
541
542 register_bank(fir_base, 3);
543
544 high = inb(fir_base + IRCC_ID_HIGH);
545 low = inb(fir_base + IRCC_ID_LOW);
546 chip = inb(fir_base + IRCC_CHIP_ID);
547 version = inb(fir_base + IRCC_VERSION);
548 config = inb(fir_base + IRCC_INTERFACE);
549 dma = config & IRCC_INTERFACE_DMA_MASK;
550 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
551
552 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
553 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
554 __FUNCTION__, fir_base);
555 goto out3;
556 }
557 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
558 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
559 chip & 0x0f, version, fir_base, sir_base, dma, irq);
560
561 return 0;
562
563 out3:
564 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
565 out2:
566 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
567 out1:
568 return -ENODEV;
569 }
570
571 /*
572 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
573 *
574 * Setup I/O
575 *
576 */
577 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
578 unsigned int fir_base, unsigned int sir_base,
579 u8 dma, u8 irq)
580 {
581 unsigned char config, chip_dma, chip_irq;
582
583 register_bank(fir_base, 3);
584 config = inb(fir_base + IRCC_INTERFACE);
585 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
586 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
587
588 self->io.fir_base = fir_base;
589 self->io.sir_base = sir_base;
590 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
591 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
592 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
593 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
594
595 if (irq < 255) {
596 if (irq != chip_irq)
597 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
598 driver_name, chip_irq, irq);
599 self->io.irq = irq;
600 } else
601 self->io.irq = chip_irq;
602
603 if (dma < 255) {
604 if (dma != chip_dma)
605 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
606 driver_name, chip_dma, dma);
607 self->io.dma = dma;
608 } else
609 self->io.dma = chip_dma;
610
611 }
612
613 /*
614 * Function smsc_ircc_setup_qos(self)
615 *
616 * Setup qos
617 *
618 */
619 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
620 {
621 /* Initialize QoS for this device */
622 irda_init_max_qos_capabilies(&self->qos);
623
624 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
625 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
626
627 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
628 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
629 irda_qos_bits_to_value(&self->qos);
630 }
631
632 /*
633 * Function smsc_ircc_init_chip(self)
634 *
635 * Init chip
636 *
637 */
638 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
639 {
640 int iobase, ir_mode, ctrl, fast;
641
642 IRDA_ASSERT(self != NULL, return;);
643
644 iobase = self->io.fir_base;
645 ir_mode = IRCC_CFGA_IRDA_SIR_A;
646 ctrl = 0;
647 fast = 0;
648
649 register_bank(iobase, 0);
650 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
651 outb(0x00, iobase + IRCC_MASTER);
652
653 register_bank(iobase, 1);
654 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | ir_mode),
655 iobase + IRCC_SCE_CFGA);
656
657 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
658 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
659 iobase + IRCC_SCE_CFGB);
660 #else
661 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
662 iobase + IRCC_SCE_CFGB);
663 #endif
664 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
665 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
666
667 register_bank(iobase, 4);
668 outb((inb(iobase + IRCC_CONTROL) & 0x30) | ctrl, iobase + IRCC_CONTROL);
669
670 register_bank(iobase, 0);
671 outb(fast, iobase + IRCC_LCR_A);
672
673 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
674
675 /* Power on device */
676 outb(0x00, iobase + IRCC_MASTER);
677 }
678
679 /*
680 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
681 *
682 * Process IOCTL commands for this device
683 *
684 */
685 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
686 {
687 struct if_irda_req *irq = (struct if_irda_req *) rq;
688 struct smsc_ircc_cb *self;
689 unsigned long flags;
690 int ret = 0;
691
692 IRDA_ASSERT(dev != NULL, return -1;);
693
694 self = dev->priv;
695
696 IRDA_ASSERT(self != NULL, return -1;);
697
698 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
699
700 switch (cmd) {
701 case SIOCSBANDWIDTH: /* Set bandwidth */
702 if (!capable(CAP_NET_ADMIN))
703 ret = -EPERM;
704 else {
705 /* Make sure we are the only one touching
706 * self->io.speed and the hardware - Jean II */
707 spin_lock_irqsave(&self->lock, flags);
708 smsc_ircc_change_speed(self, irq->ifr_baudrate);
709 spin_unlock_irqrestore(&self->lock, flags);
710 }
711 break;
712 case SIOCSMEDIABUSY: /* Set media busy */
713 if (!capable(CAP_NET_ADMIN)) {
714 ret = -EPERM;
715 break;
716 }
717
718 irda_device_set_media_busy(self->netdev, TRUE);
719 break;
720 case SIOCGRECEIVING: /* Check if we are receiving right now */
721 irq->ifr_receiving = smsc_ircc_is_receiving(self);
722 break;
723 #if 0
724 case SIOCSDTRRTS:
725 if (!capable(CAP_NET_ADMIN)) {
726 ret = -EPERM;
727 break;
728 }
729 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
730 break;
731 #endif
732 default:
733 ret = -EOPNOTSUPP;
734 }
735
736 return ret;
737 }
738
739 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
740 {
741 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) dev->priv;
742
743 return &self->stats;
744 }
745
746 #if SMSC_IRCC2_C_NET_TIMEOUT
747 /*
748 * Function smsc_ircc_timeout (struct net_device *dev)
749 *
750 * The networking timeout management.
751 *
752 */
753
754 static void smsc_ircc_timeout(struct net_device *dev)
755 {
756 struct smsc_ircc_cb *self;
757 unsigned long flags;
758
759 self = (struct smsc_ircc_cb *) dev->priv;
760
761 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
762 dev->name, self->io.speed);
763 spin_lock_irqsave(&self->lock, flags);
764 smsc_ircc_sir_start(self);
765 smsc_ircc_change_speed(self, self->io.speed);
766 dev->trans_start = jiffies;
767 netif_wake_queue(dev);
768 spin_unlock_irqrestore(&self->lock, flags);
769 }
770 #endif
771
772 /*
773 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
774 *
775 * Transmits the current frame until FIFO is full, then
776 * waits until the next transmit interrupt, and continues until the
777 * frame is transmitted.
778 */
779 int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
780 {
781 struct smsc_ircc_cb *self;
782 unsigned long flags;
783 s32 speed;
784
785 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
786
787 IRDA_ASSERT(dev != NULL, return 0;);
788
789 self = (struct smsc_ircc_cb *) dev->priv;
790 IRDA_ASSERT(self != NULL, return 0;);
791
792 netif_stop_queue(dev);
793
794 /* Make sure test of self->io.speed & speed change are atomic */
795 spin_lock_irqsave(&self->lock, flags);
796
797 /* Check if we need to change the speed */
798 speed = irda_get_next_speed(skb);
799 if (speed != self->io.speed && speed != -1) {
800 /* Check for empty frame */
801 if (!skb->len) {
802 /*
803 * We send frames one by one in SIR mode (no
804 * pipelining), so at this point, if we were sending
805 * a previous frame, we just received the interrupt
806 * telling us it is finished (UART_IIR_THRI).
807 * Therefore, waiting for the transmitter to really
808 * finish draining the fifo won't take too long.
809 * And the interrupt handler is not expected to run.
810 * - Jean II */
811 smsc_ircc_sir_wait_hw_transmitter_finish(self);
812 smsc_ircc_change_speed(self, speed);
813 spin_unlock_irqrestore(&self->lock, flags);
814 dev_kfree_skb(skb);
815 return 0;
816 }
817 self->new_speed = speed;
818 }
819
820 /* Init tx buffer */
821 self->tx_buff.data = self->tx_buff.head;
822
823 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
824 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
825 self->tx_buff.truesize);
826
827 self->stats.tx_bytes += self->tx_buff.len;
828
829 /* Turn on transmit finished interrupt. Will fire immediately! */
830 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
831
832 spin_unlock_irqrestore(&self->lock, flags);
833
834 dev_kfree_skb(skb);
835
836 return 0;
837 }
838
839 /*
840 * Function smsc_ircc_set_fir_speed (self, baud)
841 *
842 * Change the speed of the device
843 *
844 */
845 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
846 {
847 int fir_base, ir_mode, ctrl, fast;
848
849 IRDA_ASSERT(self != NULL, return;);
850 fir_base = self->io.fir_base;
851
852 self->io.speed = speed;
853
854 switch (speed) {
855 default:
856 case 576000:
857 ir_mode = IRCC_CFGA_IRDA_HDLC;
858 ctrl = IRCC_CRC;
859 fast = 0;
860 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
861 break;
862 case 1152000:
863 ir_mode = IRCC_CFGA_IRDA_HDLC;
864 ctrl = IRCC_1152 | IRCC_CRC;
865 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
866 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
867 __FUNCTION__);
868 break;
869 case 4000000:
870 ir_mode = IRCC_CFGA_IRDA_4PPM;
871 ctrl = IRCC_CRC;
872 fast = IRCC_LCR_A_FAST;
873 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
874 __FUNCTION__);
875 break;
876 }
877 #if 0
878 Now in tranceiver!
879 /* This causes an interrupt */
880 register_bank(fir_base, 0);
881 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
882 #endif
883
884 register_bank(fir_base, 1);
885 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
886
887 register_bank(fir_base, 4);
888 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
889 }
890
891 /*
892 * Function smsc_ircc_fir_start(self)
893 *
894 * Change the speed of the device
895 *
896 */
897 static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
898 {
899 struct net_device *dev;
900 int fir_base;
901
902 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
903
904 IRDA_ASSERT(self != NULL, return;);
905 dev = self->netdev;
906 IRDA_ASSERT(dev != NULL, return;);
907
908 fir_base = self->io.fir_base;
909
910 /* Reset everything */
911
912 /* Install FIR transmit handler */
913 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
914
915 /* Clear FIFO */
916 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
917
918 /* Enable interrupt */
919 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
920
921 register_bank(fir_base, 1);
922
923 /* Select the TX/RX interface */
924 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
925 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
926 fir_base + IRCC_SCE_CFGB);
927 #else
928 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
929 fir_base + IRCC_SCE_CFGB);
930 #endif
931 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
932
933 /* Enable SCE interrupts */
934 outb(0, fir_base + IRCC_MASTER);
935 register_bank(fir_base, 0);
936 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
937 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
938 }
939
940 /*
941 * Function smsc_ircc_fir_stop(self, baud)
942 *
943 * Change the speed of the device
944 *
945 */
946 static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
947 {
948 int fir_base;
949
950 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
951
952 IRDA_ASSERT(self != NULL, return;);
953
954 fir_base = self->io.fir_base;
955 register_bank(fir_base, 0);
956 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
957 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
958 }
959
960
961 /*
962 * Function smsc_ircc_change_speed(self, baud)
963 *
964 * Change the speed of the device
965 *
966 * This function *must* be called with spinlock held, because it may
967 * be called from the irq handler. - Jean II
968 */
969 static void smsc_ircc_change_speed(void *priv, u32 speed)
970 {
971 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) priv;
972 struct net_device *dev;
973 int last_speed_was_sir;
974
975 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
976
977 IRDA_ASSERT(self != NULL, return;);
978 dev = self->netdev;
979
980 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
981
982 #if 0
983 /* Temp Hack */
984 speed= 1152000;
985 self->io.speed = speed;
986 last_speed_was_sir = 0;
987 smsc_ircc_fir_start(self);
988 #endif
989
990 if (self->io.speed == 0)
991 smsc_ircc_sir_start(self);
992
993 #if 0
994 if (!last_speed_was_sir) speed = self->io.speed;
995 #endif
996
997 if (self->io.speed != speed)
998 smsc_ircc_set_transceiver_for_speed(self, speed);
999
1000 self->io.speed = speed;
1001
1002 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1003 if (!last_speed_was_sir) {
1004 smsc_ircc_fir_stop(self);
1005 smsc_ircc_sir_start(self);
1006 }
1007 smsc_ircc_set_sir_speed(self, speed);
1008 } else {
1009 if (last_speed_was_sir) {
1010 #if SMSC_IRCC2_C_SIR_STOP
1011 smsc_ircc_sir_stop(self);
1012 #endif
1013 smsc_ircc_fir_start(self);
1014 }
1015 smsc_ircc_set_fir_speed(self, speed);
1016
1017 #if 0
1018 self->tx_buff.len = 10;
1019 self->tx_buff.data = self->tx_buff.head;
1020
1021 smsc_ircc_dma_xmit(self, 4000);
1022 #endif
1023 /* Be ready for incoming frames */
1024 smsc_ircc_dma_receive(self);
1025 }
1026
1027 netif_wake_queue(dev);
1028 }
1029
1030 /*
1031 * Function smsc_ircc_set_sir_speed (self, speed)
1032 *
1033 * Set speed of IrDA port to specified baudrate
1034 *
1035 */
1036 void smsc_ircc_set_sir_speed(void *priv, __u32 speed)
1037 {
1038 struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) priv;
1039 int iobase;
1040 int fcr; /* FIFO control reg */
1041 int lcr; /* Line control reg */
1042 int divisor;
1043
1044 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1045
1046 IRDA_ASSERT(self != NULL, return;);
1047 iobase = self->io.sir_base;
1048
1049 /* Update accounting for new speed */
1050 self->io.speed = speed;
1051
1052 /* Turn off interrupts */
1053 outb(0, iobase + UART_IER);
1054
1055 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1056
1057 fcr = UART_FCR_ENABLE_FIFO;
1058
1059 /*
1060 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1061 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1062 * about this timeout since it will always be fast enough.
1063 */
1064 fcr |= self->io.speed < 38400 ?
1065 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1066
1067 /* IrDA ports use 8N1 */
1068 lcr = UART_LCR_WLEN8;
1069
1070 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1071 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1072 outb(divisor >> 8, iobase + UART_DLM);
1073 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1074 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1075
1076 /* Turn on interrups */
1077 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1078
1079 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1080 }
1081
1082
1083 /*
1084 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1085 *
1086 * Transmit the frame!
1087 *
1088 */
1089 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1090 {
1091 struct smsc_ircc_cb *self;
1092 unsigned long flags;
1093 s32 speed;
1094 int mtt;
1095
1096 IRDA_ASSERT(dev != NULL, return 0;);
1097 self = (struct smsc_ircc_cb *) dev->priv;
1098 IRDA_ASSERT(self != NULL, return 0;);
1099
1100 netif_stop_queue(dev);
1101
1102 /* Make sure test of self->io.speed & speed change are atomic */
1103 spin_lock_irqsave(&self->lock, flags);
1104
1105 /* Check if we need to change the speed after this frame */
1106 speed = irda_get_next_speed(skb);
1107 if (speed != self->io.speed && speed != -1) {
1108 /* Check for empty frame */
1109 if (!skb->len) {
1110 /* Note : you should make sure that speed changes
1111 * are not going to corrupt any outgoing frame.
1112 * Look at nsc-ircc for the gory details - Jean II */
1113 smsc_ircc_change_speed(self, speed);
1114 spin_unlock_irqrestore(&self->lock, flags);
1115 dev_kfree_skb(skb);
1116 return 0;
1117 }
1118
1119 self->new_speed = speed;
1120 }
1121
1122 memcpy(self->tx_buff.head, skb->data, skb->len);
1123
1124 self->tx_buff.len = skb->len;
1125 self->tx_buff.data = self->tx_buff.head;
1126
1127 mtt = irda_get_mtt(skb);
1128 if (mtt) {
1129 int bofs;
1130
1131 /*
1132 * Compute how many BOFs (STA or PA's) we need to waste the
1133 * min turn time given the speed of the link.
1134 */
1135 bofs = mtt * (self->io.speed / 1000) / 8000;
1136 if (bofs > 4095)
1137 bofs = 4095;
1138
1139 smsc_ircc_dma_xmit(self, bofs);
1140 } else {
1141 /* Transmit frame */
1142 smsc_ircc_dma_xmit(self, 0);
1143 }
1144
1145 spin_unlock_irqrestore(&self->lock, flags);
1146 dev_kfree_skb(skb);
1147
1148 return 0;
1149 }
1150
1151 /*
1152 * Function smsc_ircc_dma_xmit (self, bofs)
1153 *
1154 * Transmit data using DMA
1155 *
1156 */
1157 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1158 {
1159 int iobase = self->io.fir_base;
1160 u8 ctrl;
1161
1162 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1163 #if 1
1164 /* Disable Rx */
1165 register_bank(iobase, 0);
1166 outb(0x00, iobase + IRCC_LCR_B);
1167 #endif
1168 register_bank(iobase, 1);
1169 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1170 iobase + IRCC_SCE_CFGB);
1171
1172 self->io.direction = IO_XMIT;
1173
1174 /* Set BOF additional count for generating the min turn time */
1175 register_bank(iobase, 4);
1176 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1177 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1178 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1179
1180 /* Set max Tx frame size */
1181 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1182 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1183
1184 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1185
1186 /* Enable burst mode chip Tx DMA */
1187 register_bank(iobase, 1);
1188 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1189 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1190
1191 /* Setup DMA controller (must be done after enabling chip DMA) */
1192 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1193 DMA_TX_MODE);
1194
1195 /* Enable interrupt */
1196
1197 register_bank(iobase, 0);
1198 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1199 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1200
1201 /* Enable transmit */
1202 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1203 }
1204
1205 /*
1206 * Function smsc_ircc_dma_xmit_complete (self)
1207 *
1208 * The transfer of a frame in finished. This function will only be called
1209 * by the interrupt handler
1210 *
1211 */
1212 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1213 {
1214 int iobase = self->io.fir_base;
1215
1216 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1217 #if 0
1218 /* Disable Tx */
1219 register_bank(iobase, 0);
1220 outb(0x00, iobase + IRCC_LCR_B);
1221 #endif
1222 register_bank(iobase, 1);
1223 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1224 iobase + IRCC_SCE_CFGB);
1225
1226 /* Check for underrun! */
1227 register_bank(iobase, 0);
1228 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1229 self->stats.tx_errors++;
1230 self->stats.tx_fifo_errors++;
1231
1232 /* Reset error condition */
1233 register_bank(iobase, 0);
1234 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1235 outb(0x00, iobase + IRCC_MASTER);
1236 } else {
1237 self->stats.tx_packets++;
1238 self->stats.tx_bytes += self->tx_buff.len;
1239 }
1240
1241 /* Check if it's time to change the speed */
1242 if (self->new_speed) {
1243 smsc_ircc_change_speed(self, self->new_speed);
1244 self->new_speed = 0;
1245 }
1246
1247 netif_wake_queue(self->netdev);
1248 }
1249
1250 /*
1251 * Function smsc_ircc_dma_receive(self)
1252 *
1253 * Get ready for receiving a frame. The device will initiate a DMA
1254 * if it starts to receive a frame.
1255 *
1256 */
1257 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1258 {
1259 int iobase = self->io.fir_base;
1260 #if 0
1261 /* Turn off chip DMA */
1262 register_bank(iobase, 1);
1263 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1264 iobase + IRCC_SCE_CFGB);
1265 #endif
1266
1267 /* Disable Tx */
1268 register_bank(iobase, 0);
1269 outb(0x00, iobase + IRCC_LCR_B);
1270
1271 /* Turn off chip DMA */
1272 register_bank(iobase, 1);
1273 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1274 iobase + IRCC_SCE_CFGB);
1275
1276 self->io.direction = IO_RECV;
1277 self->rx_buff.data = self->rx_buff.head;
1278
1279 /* Set max Rx frame size */
1280 register_bank(iobase, 4);
1281 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1282 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1283
1284 /* Setup DMA controller */
1285 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1286 DMA_RX_MODE);
1287
1288 /* Enable burst mode chip Rx DMA */
1289 register_bank(iobase, 1);
1290 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1291 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1292
1293 /* Enable interrupt */
1294 register_bank(iobase, 0);
1295 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1296 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1297
1298 /* Enable receiver */
1299 register_bank(iobase, 0);
1300 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1301 iobase + IRCC_LCR_B);
1302
1303 return 0;
1304 }
1305
1306 /*
1307 * Function smsc_ircc_dma_receive_complete(self)
1308 *
1309 * Finished with receiving frames
1310 *
1311 */
1312 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1313 {
1314 struct sk_buff *skb;
1315 int len, msgcnt, lsr;
1316 int iobase = self->io.fir_base;
1317
1318 register_bank(iobase, 0);
1319
1320 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1321 #if 0
1322 /* Disable Rx */
1323 register_bank(iobase, 0);
1324 outb(0x00, iobase + IRCC_LCR_B);
1325 #endif
1326 register_bank(iobase, 0);
1327 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1328 lsr= inb(iobase + IRCC_LSR);
1329 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1330
1331 IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1332 get_dma_residue(self->io.dma));
1333
1334 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1335
1336 /* Look for errors */
1337 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1338 self->stats.rx_errors++;
1339 if (lsr & IRCC_LSR_FRAME_ERROR)
1340 self->stats.rx_frame_errors++;
1341 if (lsr & IRCC_LSR_CRC_ERROR)
1342 self->stats.rx_crc_errors++;
1343 if (lsr & IRCC_LSR_SIZE_ERROR)
1344 self->stats.rx_length_errors++;
1345 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1346 self->stats.rx_length_errors++;
1347 return;
1348 }
1349
1350 /* Remove CRC */
1351 len -= self->io.speed < 4000000 ? 2 : 4;
1352
1353 if (len < 2 || len > 2050) {
1354 IRDA_WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1355 return;
1356 }
1357 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1358
1359 skb = dev_alloc_skb(len + 1);
1360 if (!skb) {
1361 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1362 __FUNCTION__);
1363 return;
1364 }
1365 /* Make sure IP header gets aligned */
1366 skb_reserve(skb, 1);
1367
1368 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1369 self->stats.rx_packets++;
1370 self->stats.rx_bytes += len;
1371
1372 skb->dev = self->netdev;
1373 skb->mac.raw = skb->data;
1374 skb->protocol = htons(ETH_P_IRDA);
1375 netif_rx(skb);
1376 }
1377
1378 /*
1379 * Function smsc_ircc_sir_receive (self)
1380 *
1381 * Receive one frame from the infrared port
1382 *
1383 */
1384 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1385 {
1386 int boguscount = 0;
1387 int iobase;
1388
1389 IRDA_ASSERT(self != NULL, return;);
1390
1391 iobase = self->io.sir_base;
1392
1393 /*
1394 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1395 * async_unwrap_char will deliver all found frames
1396 */
1397 do {
1398 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
1399 inb(iobase + UART_RX));
1400
1401 /* Make sure we don't stay here to long */
1402 if (boguscount++ > 32) {
1403 IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1404 break;
1405 }
1406 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1407 }
1408
1409
1410 /*
1411 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1412 *
1413 * An interrupt from the chip has arrived. Time to do some work
1414 *
1415 */
1416 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1417 {
1418 struct net_device *dev = (struct net_device *) dev_id;
1419 struct smsc_ircc_cb *self;
1420 int iobase, iir, lcra, lsr;
1421 irqreturn_t ret = IRQ_NONE;
1422
1423 if (dev == NULL) {
1424 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1425 driver_name, irq);
1426 goto irq_ret;
1427 }
1428 self = (struct smsc_ircc_cb *) dev->priv;
1429 IRDA_ASSERT(self != NULL, return IRQ_NONE;);
1430
1431 /* Serialise the interrupt handler in various CPUs, stop Tx path */
1432 spin_lock(&self->lock);
1433
1434 /* Check if we should use the SIR interrupt handler */
1435 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1436 ret = smsc_ircc_interrupt_sir(dev);
1437 goto irq_ret_unlock;
1438 }
1439
1440 iobase = self->io.fir_base;
1441
1442 register_bank(iobase, 0);
1443 iir = inb(iobase + IRCC_IIR);
1444 if (iir == 0)
1445 goto irq_ret_unlock;
1446 ret = IRQ_HANDLED;
1447
1448 /* Disable interrupts */
1449 outb(0, iobase + IRCC_IER);
1450 lcra = inb(iobase + IRCC_LCR_A);
1451 lsr = inb(iobase + IRCC_LSR);
1452
1453 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1454
1455 if (iir & IRCC_IIR_EOM) {
1456 if (self->io.direction == IO_RECV)
1457 smsc_ircc_dma_receive_complete(self);
1458 else
1459 smsc_ircc_dma_xmit_complete(self);
1460
1461 smsc_ircc_dma_receive(self);
1462 }
1463
1464 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1465 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1466 }
1467
1468 /* Enable interrupts again */
1469
1470 register_bank(iobase, 0);
1471 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1472
1473 irq_ret_unlock:
1474 spin_unlock(&self->lock);
1475 irq_ret:
1476 return ret;
1477 }
1478
1479 /*
1480 * Function irport_interrupt_sir (irq, dev_id, regs)
1481 *
1482 * Interrupt handler for SIR modes
1483 */
1484 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1485 {
1486 struct smsc_ircc_cb *self = dev->priv;
1487 int boguscount = 0;
1488 int iobase;
1489 int iir, lsr;
1490
1491 /* Already locked comming here in smsc_ircc_interrupt() */
1492 /*spin_lock(&self->lock);*/
1493
1494 iobase = self->io.sir_base;
1495
1496 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1497 if (iir == 0)
1498 return IRQ_NONE;
1499 while (iir) {
1500 /* Clear interrupt */
1501 lsr = inb(iobase + UART_LSR);
1502
1503 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1504 __FUNCTION__, iir, lsr, iobase);
1505
1506 switch (iir) {
1507 case UART_IIR_RLSI:
1508 IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1509 break;
1510 case UART_IIR_RDI:
1511 /* Receive interrupt */
1512 smsc_ircc_sir_receive(self);
1513 break;
1514 case UART_IIR_THRI:
1515 if (lsr & UART_LSR_THRE)
1516 /* Transmitter ready for data */
1517 smsc_ircc_sir_write_wakeup(self);
1518 break;
1519 default:
1520 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1521 __FUNCTION__, iir);
1522 break;
1523 }
1524
1525 /* Make sure we don't stay here to long */
1526 if (boguscount++ > 100)
1527 break;
1528
1529 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1530 }
1531 /*spin_unlock(&self->lock);*/
1532 return IRQ_HANDLED;
1533 }
1534
1535
1536 #if 0 /* unused */
1537 /*
1538 * Function ircc_is_receiving (self)
1539 *
1540 * Return TRUE is we are currently receiving a frame
1541 *
1542 */
1543 static int ircc_is_receiving(struct smsc_ircc_cb *self)
1544 {
1545 int status = FALSE;
1546 /* int iobase; */
1547
1548 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1549
1550 IRDA_ASSERT(self != NULL, return FALSE;);
1551
1552 IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1553 get_dma_residue(self->io.dma));
1554
1555 status = (self->rx_buff.state != OUTSIDE_FRAME);
1556
1557 return status;
1558 }
1559 #endif /* unused */
1560
1561
1562 /*
1563 * Function smsc_ircc_net_open (dev)
1564 *
1565 * Start the device
1566 *
1567 */
1568 static int smsc_ircc_net_open(struct net_device *dev)
1569 {
1570 struct smsc_ircc_cb *self;
1571 char hwname[16];
1572 unsigned long flags;
1573
1574 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1575
1576 IRDA_ASSERT(dev != NULL, return -1;);
1577 self = (struct smsc_ircc_cb *) dev->priv;
1578 IRDA_ASSERT(self != NULL, return 0;);
1579
1580 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1581 (void *) dev)) {
1582 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1583 __FUNCTION__, self->io.irq);
1584 return -EAGAIN;
1585 }
1586
1587 spin_lock_irqsave(&self->lock, flags);
1588 /*smsc_ircc_sir_start(self);*/
1589 self->io.speed = 0;
1590 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1591 spin_unlock_irqrestore(&self->lock, flags);
1592
1593 /* Give self a hardware name */
1594 /* It would be cool to offer the chip revision here - Jean II */
1595 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1596
1597 /*
1598 * Open new IrLAP layer instance, now that everything should be
1599 * initialized properly
1600 */
1601 self->irlap = irlap_open(dev, &self->qos, hwname);
1602
1603 /*
1604 * Always allocate the DMA channel after the IRQ,
1605 * and clean up on failure.
1606 */
1607 if (request_dma(self->io.dma, dev->name)) {
1608 smsc_ircc_net_close(dev);
1609
1610 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1611 __FUNCTION__, self->io.dma);
1612 return -EAGAIN;
1613 }
1614
1615 netif_start_queue(dev);
1616
1617 return 0;
1618 }
1619
1620 /*
1621 * Function smsc_ircc_net_close (dev)
1622 *
1623 * Stop the device
1624 *
1625 */
1626 static int smsc_ircc_net_close(struct net_device *dev)
1627 {
1628 struct smsc_ircc_cb *self;
1629
1630 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1631
1632 IRDA_ASSERT(dev != NULL, return -1;);
1633 self = (struct smsc_ircc_cb *) dev->priv;
1634 IRDA_ASSERT(self != NULL, return 0;);
1635
1636 /* Stop device */
1637 netif_stop_queue(dev);
1638
1639 /* Stop and remove instance of IrLAP */
1640 if (self->irlap)
1641 irlap_close(self->irlap);
1642 self->irlap = NULL;
1643
1644 free_irq(self->io.irq, dev);
1645 disable_dma(self->io.dma);
1646 free_dma(self->io.dma);
1647
1648 return 0;
1649 }
1650
1651 static int smsc_ircc_suspend(struct device *dev, pm_message_t state, u32 level)
1652 {
1653 struct smsc_ircc_cb *self = dev_get_drvdata(dev);
1654
1655 IRDA_MESSAGE("%s, Suspending\n", driver_name);
1656
1657 if (level == SUSPEND_DISABLE && !self->io.suspended) {
1658 smsc_ircc_net_close(self->netdev);
1659 self->io.suspended = 1;
1660 }
1661
1662 return 0;
1663 }
1664
1665 static int smsc_ircc_resume(struct device *dev, u32 level)
1666 {
1667 struct smsc_ircc_cb *self = dev_get_drvdata(dev);
1668
1669 if (level == RESUME_ENABLE && self->io.suspended) {
1670
1671 smsc_ircc_net_open(self->netdev);
1672 self->io.suspended = 0;
1673
1674 IRDA_MESSAGE("%s, Waking up\n", driver_name);
1675 }
1676 return 0;
1677 }
1678
1679 /*
1680 * Function smsc_ircc_close (self)
1681 *
1682 * Close driver instance
1683 *
1684 */
1685 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1686 {
1687 int iobase;
1688 unsigned long flags;
1689
1690 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1691
1692 IRDA_ASSERT(self != NULL, return -1;);
1693
1694 platform_device_unregister(self->pldev);
1695
1696 /* Remove netdevice */
1697 unregister_netdev(self->netdev);
1698
1699 /* Make sure the irq handler is not exectuting */
1700 spin_lock_irqsave(&self->lock, flags);
1701
1702 /* Stop interrupts */
1703 iobase = self->io.fir_base;
1704 register_bank(iobase, 0);
1705 outb(0, iobase + IRCC_IER);
1706 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1707 outb(0x00, iobase + IRCC_MASTER);
1708 #if 0
1709 /* Reset to SIR mode */
1710 register_bank(iobase, 1);
1711 outb(IRCC_CFGA_IRDA_SIR_A|IRCC_CFGA_TX_POLARITY, iobase + IRCC_SCE_CFGA);
1712 outb(IRCC_CFGB_IR, iobase + IRCC_SCE_CFGB);
1713 #endif
1714 spin_unlock_irqrestore(&self->lock, flags);
1715
1716 /* Release the PORTS that this driver is using */
1717 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1718 self->io.fir_base);
1719
1720 release_region(self->io.fir_base, self->io.fir_ext);
1721
1722 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1723 self->io.sir_base);
1724
1725 release_region(self->io.sir_base, self->io.sir_ext);
1726
1727 if (self->tx_buff.head)
1728 dma_free_coherent(NULL, self->tx_buff.truesize,
1729 self->tx_buff.head, self->tx_buff_dma);
1730
1731 if (self->rx_buff.head)
1732 dma_free_coherent(NULL, self->rx_buff.truesize,
1733 self->rx_buff.head, self->rx_buff_dma);
1734
1735 free_netdev(self->netdev);
1736
1737 return 0;
1738 }
1739
1740 static void __exit smsc_ircc_cleanup(void)
1741 {
1742 int i;
1743
1744 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1745
1746 for (i = 0; i < 2; i++) {
1747 if (dev_self[i])
1748 smsc_ircc_close(dev_self[i]);
1749 }
1750
1751 driver_unregister(&smsc_ircc_driver);
1752 }
1753
1754 /*
1755 * Start SIR operations
1756 *
1757 * This function *must* be called with spinlock held, because it may
1758 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1759 */
1760 void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1761 {
1762 struct net_device *dev;
1763 int fir_base, sir_base;
1764
1765 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1766
1767 IRDA_ASSERT(self != NULL, return;);
1768 dev = self->netdev;
1769 IRDA_ASSERT(dev != NULL, return;);
1770 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1771
1772 fir_base = self->io.fir_base;
1773 sir_base = self->io.sir_base;
1774
1775 /* Reset everything */
1776 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1777
1778 #if SMSC_IRCC2_C_SIR_STOP
1779 /*smsc_ircc_sir_stop(self);*/
1780 #endif
1781
1782 register_bank(fir_base, 1);
1783 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1784
1785 /* Initialize UART */
1786 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1787 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1788
1789 /* Turn on interrups */
1790 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1791
1792 IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1793
1794 outb(0x00, fir_base + IRCC_MASTER);
1795 }
1796
1797 #if SMSC_IRCC2_C_SIR_STOP
1798 void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1799 {
1800 int iobase;
1801
1802 IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1803 iobase = self->io.sir_base;
1804
1805 /* Reset UART */
1806 outb(0, iobase + UART_MCR);
1807
1808 /* Turn off interrupts */
1809 outb(0, iobase + UART_IER);
1810 }
1811 #endif
1812
1813 /*
1814 * Function smsc_sir_write_wakeup (self)
1815 *
1816 * Called by the SIR interrupt handler when there's room for more data.
1817 * If we have more packets to send, we send them here.
1818 *
1819 */
1820 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1821 {
1822 int actual = 0;
1823 int iobase;
1824 int fcr;
1825
1826 IRDA_ASSERT(self != NULL, return;);
1827
1828 IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1829
1830 iobase = self->io.sir_base;
1831
1832 /* Finished with frame? */
1833 if (self->tx_buff.len > 0) {
1834 /* Write data left in transmit buffer */
1835 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1836 self->tx_buff.data, self->tx_buff.len);
1837 self->tx_buff.data += actual;
1838 self->tx_buff.len -= actual;
1839 } else {
1840
1841 /*if (self->tx_buff.len ==0) {*/
1842
1843 /*
1844 * Now serial buffer is almost free & we can start
1845 * transmission of another packet. But first we must check
1846 * if we need to change the speed of the hardware
1847 */
1848 if (self->new_speed) {
1849 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1850 __FUNCTION__, self->new_speed);
1851 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1852 smsc_ircc_change_speed(self, self->new_speed);
1853 self->new_speed = 0;
1854 } else {
1855 /* Tell network layer that we want more frames */
1856 netif_wake_queue(self->netdev);
1857 }
1858 self->stats.tx_packets++;
1859
1860 if (self->io.speed <= 115200) {
1861 /*
1862 * Reset Rx FIFO to make sure that all reflected transmit data
1863 * is discarded. This is needed for half duplex operation
1864 */
1865 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
1866 fcr |= self->io.speed < 38400 ?
1867 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1868
1869 outb(fcr, iobase + UART_FCR);
1870
1871 /* Turn on receive interrupts */
1872 outb(UART_IER_RDI, iobase + UART_IER);
1873 }
1874 }
1875 }
1876
1877 /*
1878 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
1879 *
1880 * Fill Tx FIFO with transmit data
1881 *
1882 */
1883 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1884 {
1885 int actual = 0;
1886
1887 /* Tx FIFO should be empty! */
1888 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
1889 IRDA_WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
1890 return 0;
1891 }
1892
1893 /* Fill FIFO with current frame */
1894 while (fifo_size-- > 0 && actual < len) {
1895 /* Transmit next byte */
1896 outb(buf[actual], iobase + UART_TX);
1897 actual++;
1898 }
1899 return actual;
1900 }
1901
1902 /*
1903 * Function smsc_ircc_is_receiving (self)
1904 *
1905 * Returns true is we are currently receiving data
1906 *
1907 */
1908 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
1909 {
1910 return (self->rx_buff.state != OUTSIDE_FRAME);
1911 }
1912
1913
1914 /*
1915 * Function smsc_ircc_probe_transceiver(self)
1916 *
1917 * Tries to find the used Transceiver
1918 *
1919 */
1920 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
1921 {
1922 unsigned int i;
1923
1924 IRDA_ASSERT(self != NULL, return;);
1925
1926 for (i = 0; smsc_transceivers[i].name != NULL; i++)
1927 if (smsc_transceivers[i].probe(self->io.fir_base)) {
1928 IRDA_MESSAGE(" %s transceiver found\n",
1929 smsc_transceivers[i].name);
1930 self->transceiver= i + 1;
1931 return;
1932 }
1933
1934 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
1935 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
1936
1937 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1938 }
1939
1940
1941 /*
1942 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
1943 *
1944 * Set the transceiver according to the speed
1945 *
1946 */
1947 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
1948 {
1949 unsigned int trx;
1950
1951 trx = self->transceiver;
1952 if (trx > 0)
1953 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
1954 }
1955
1956 /*
1957 * Function smsc_ircc_wait_hw_transmitter_finish ()
1958 *
1959 * Wait for the real end of HW transmission
1960 *
1961 * The UART is a strict FIFO, and we get called only when we have finished
1962 * pushing data to the FIFO, so the maximum amount of time we must wait
1963 * is only for the FIFO to drain out.
1964 *
1965 * We use a simple calibrated loop. We may need to adjust the loop
1966 * delay (udelay) to balance I/O traffic and latency. And we also need to
1967 * adjust the maximum timeout.
1968 * It would probably be better to wait for the proper interrupt,
1969 * but it doesn't seem to be available.
1970 *
1971 * We can't use jiffies or kernel timers because :
1972 * 1) We are called from the interrupt handler, which disable softirqs,
1973 * so jiffies won't be increased
1974 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
1975 * want to wait that long to detect stuck hardware.
1976 * Jean II
1977 */
1978
1979 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
1980 {
1981 int iobase = self->io.sir_base;
1982 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
1983
1984 /* Calibrated busy loop */
1985 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
1986 udelay(1);
1987
1988 if (count == 0)
1989 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
1990 }
1991
1992
1993 /* PROBING
1994 *
1995 *
1996 */
1997
1998 static int __init smsc_ircc_look_for_chips(void)
1999 {
2000 struct smsc_chip_address *address;
2001 char *type;
2002 unsigned int cfg_base, found;
2003
2004 found = 0;
2005 address = possible_addresses;
2006
2007 while (address->cfg_base) {
2008 cfg_base = address->cfg_base;
2009
2010 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
2011
2012 if (address->type & SMSCSIO_TYPE_FDC) {
2013 type = "FDC";
2014 if (address->type & SMSCSIO_TYPE_FLAT)
2015 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2016 found++;
2017
2018 if (address->type & SMSCSIO_TYPE_PAGED)
2019 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2020 found++;
2021 }
2022 if (address->type & SMSCSIO_TYPE_LPC) {
2023 type = "LPC";
2024 if (address->type & SMSCSIO_TYPE_FLAT)
2025 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2026 found++;
2027
2028 if (address->type & SMSCSIO_TYPE_PAGED)
2029 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2030 found++;
2031 }
2032 address++;
2033 }
2034 return found;
2035 }
2036
2037 /*
2038 * Function smsc_superio_flat (chip, base, type)
2039 *
2040 * Try to get configuration of a smc SuperIO chip with flat register model
2041 *
2042 */
2043 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
2044 {
2045 unsigned short firbase, sirbase;
2046 u8 mode, dma, irq;
2047 int ret = -ENODEV;
2048
2049 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2050
2051 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
2052 return ret;
2053
2054 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2055 mode = inb(cfgbase + 1);
2056
2057 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
2058
2059 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2060 IRDA_WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2061
2062 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2063 sirbase = inb(cfgbase + 1) << 2;
2064
2065 /* FIR iobase */
2066 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2067 firbase = inb(cfgbase + 1) << 3;
2068
2069 /* DMA */
2070 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2071 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2072
2073 /* IRQ */
2074 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2075 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2076
2077 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2078
2079 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2080 ret = 0;
2081
2082 /* Exit configuration */
2083 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2084
2085 return ret;
2086 }
2087
2088 /*
2089 * Function smsc_superio_paged (chip, base, type)
2090 *
2091 * Try to get configuration of a smc SuperIO chip with paged register model
2092 *
2093 */
2094 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
2095 {
2096 unsigned short fir_io, sir_io;
2097 int ret = -ENODEV;
2098
2099 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2100
2101 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
2102 return ret;
2103
2104 /* Select logical device (UART2) */
2105 outb(0x07, cfg_base);
2106 outb(0x05, cfg_base + 1);
2107
2108 /* SIR iobase */
2109 outb(0x60, cfg_base);
2110 sir_io = inb(cfg_base + 1) << 8;
2111 outb(0x61, cfg_base);
2112 sir_io |= inb(cfg_base + 1);
2113
2114 /* Read FIR base */
2115 outb(0x62, cfg_base);
2116 fir_io = inb(cfg_base + 1) << 8;
2117 outb(0x63, cfg_base);
2118 fir_io |= inb(cfg_base + 1);
2119 outb(0x2b, cfg_base); /* ??? */
2120
2121 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2122 ret = 0;
2123
2124 /* Exit configuration */
2125 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2126
2127 return ret;
2128 }
2129
2130
2131 static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
2132 {
2133 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2134
2135 outb(reg, cfg_base);
2136 return inb(cfg_base) != reg ? -1 : 0;
2137 }
2138
2139 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
2140 {
2141 u8 devid, xdevid, rev;
2142
2143 IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2144
2145 /* Leave configuration */
2146
2147 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2148
2149 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2150 return NULL;
2151
2152 outb(reg, cfg_base);
2153
2154 xdevid = inb(cfg_base + 1);
2155
2156 /* Enter configuration */
2157
2158 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2159
2160 #if 0
2161 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2162 return NULL;
2163 #endif
2164
2165 /* probe device ID */
2166
2167 if (smsc_access(cfg_base, reg))
2168 return NULL;
2169
2170 devid = inb(cfg_base + 1);
2171
2172 if (devid == 0 || devid == 0xff) /* typical values for unused port */
2173 return NULL;
2174
2175 /* probe revision ID */
2176
2177 if (smsc_access(cfg_base, reg + 1))
2178 return NULL;
2179
2180 rev = inb(cfg_base + 1);
2181
2182 if (rev >= 128) /* i think this will make no sense */
2183 return NULL;
2184
2185 if (devid == xdevid) /* protection against false positives */
2186 return NULL;
2187
2188 /* Check for expected device ID; are there others? */
2189
2190 while (chip->devid != devid) {
2191
2192 chip++;
2193
2194 if (chip->name == NULL)
2195 return NULL;
2196 }
2197
2198 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2199 devid, rev, cfg_base, type, chip->name);
2200
2201 if (chip->rev > rev) {
2202 IRDA_MESSAGE("Revision higher than expected\n");
2203 return NULL;
2204 }
2205
2206 if (chip->flags & NoIRDA)
2207 IRDA_MESSAGE("chipset does not support IRDA\n");
2208
2209 return chip;
2210 }
2211
2212 static int __init smsc_superio_fdc(unsigned short cfg_base)
2213 {
2214 int ret = -1;
2215
2216 if (!request_region(cfg_base, 2, driver_name)) {
2217 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2218 __FUNCTION__, cfg_base);
2219 } else {
2220 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2221 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
2222 ret = 0;
2223
2224 release_region(cfg_base, 2);
2225 }
2226
2227 return ret;
2228 }
2229
2230 static int __init smsc_superio_lpc(unsigned short cfg_base)
2231 {
2232 int ret = -1;
2233
2234 if (!request_region(cfg_base, 2, driver_name)) {
2235 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2236 __FUNCTION__, cfg_base);
2237 } else {
2238 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2239 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
2240 ret = 0;
2241
2242 release_region(cfg_base, 2);
2243 }
2244 return ret;
2245 }
2246
2247 /************************************************
2248 *
2249 * Transceivers specific functions
2250 *
2251 ************************************************/
2252
2253
2254 /*
2255 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2256 *
2257 * Program transceiver through smsc-ircc ATC circuitry
2258 *
2259 */
2260
2261 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2262 {
2263 unsigned long jiffies_now, jiffies_timeout;
2264 u8 val;
2265
2266 jiffies_now = jiffies;
2267 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2268
2269 /* ATC */
2270 register_bank(fir_base, 4);
2271 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2272 fir_base + IRCC_ATC);
2273
2274 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2275 !time_after(jiffies, jiffies_timeout))
2276 /* empty */;
2277
2278 if (val)
2279 IRDA_WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
2280 inb(fir_base + IRCC_ATC));
2281 }
2282
2283 /*
2284 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2285 *
2286 * Probe transceiver smsc-ircc ATC circuitry
2287 *
2288 */
2289
2290 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2291 {
2292 return 0;
2293 }
2294
2295 /*
2296 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2297 *
2298 * Set transceiver
2299 *
2300 */
2301
2302 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2303 {
2304 u8 fast_mode;
2305
2306 switch (speed) {
2307 default:
2308 case 576000 :
2309 fast_mode = 0;
2310 break;
2311 case 1152000 :
2312 case 4000000 :
2313 fast_mode = IRCC_LCR_A_FAST;
2314 break;
2315 }
2316 register_bank(fir_base, 0);
2317 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2318 }
2319
2320 /*
2321 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2322 *
2323 * Probe transceiver
2324 *
2325 */
2326
2327 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2328 {
2329 return 0;
2330 }
2331
2332 /*
2333 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2334 *
2335 * Set transceiver
2336 *
2337 */
2338
2339 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2340 {
2341 u8 fast_mode;
2342
2343 switch (speed) {
2344 default:
2345 case 576000 :
2346 fast_mode = 0;
2347 break;
2348 case 1152000 :
2349 case 4000000 :
2350 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
2351 break;
2352
2353 }
2354 /* This causes an interrupt */
2355 register_bank(fir_base, 0);
2356 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2357 }
2358
2359 /*
2360 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
2361 *
2362 * Probe transceiver
2363 *
2364 */
2365
2366 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
2367 {
2368 return 0;
2369 }
2370
2371
2372 module_init(smsc_ircc_init);
2373 module_exit(smsc_ircc_cleanup);
Linux kernel - Deliverables
This page took 0.096928 seconds and 6 git commands to generate.