1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/inet_lro.h>
37 #include "ixgbe_type.h"
38 #include "ixgbe_common.h"
40 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
41 #include <linux/dca.h>
44 #define IXGBE_ERR(args...) printk(KERN_ERR "ixgbe: " args)
47 #define DPRINTK(nlevel, klevel, fmt, args...) \
48 ((void)((NETIF_MSG_##nlevel & adapter->msg_enable) && \
49 printk(KERN_##klevel PFX "%s: %s: " fmt, adapter->netdev->name, \
50 __FUNCTION__ , ## args)))
52 /* TX/RX descriptor defines */
53 #define IXGBE_DEFAULT_TXD 1024
54 #define IXGBE_MAX_TXD 4096
55 #define IXGBE_MIN_TXD 64
57 #define IXGBE_DEFAULT_RXD 1024
58 #define IXGBE_MAX_RXD 4096
59 #define IXGBE_MIN_RXD 64
61 #define IXGBE_DEFAULT_RXQ 1
62 #define IXGBE_MAX_RXQ 1
63 #define IXGBE_MIN_RXQ 1
66 #define IXGBE_DEFAULT_FCRTL 0x10000
67 #define IXGBE_MIN_FCRTL 0x40
68 #define IXGBE_MAX_FCRTL 0x7FF80
69 #define IXGBE_DEFAULT_FCRTH 0x20000
70 #define IXGBE_MIN_FCRTH 0x600
71 #define IXGBE_MAX_FCRTH 0x7FFF0
72 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
73 #define IXGBE_MIN_FCPAUSE 0
74 #define IXGBE_MAX_FCPAUSE 0xFFFF
76 /* Supported Rx Buffer Sizes */
77 #define IXGBE_RXBUFFER_64 64 /* Used for packet split */
78 #define IXGBE_RXBUFFER_128 128 /* Used for packet split */
79 #define IXGBE_RXBUFFER_256 256 /* Used for packet split */
80 #define IXGBE_RXBUFFER_2048 2048
82 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_256
84 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
86 /* How many Tx Descriptors do we need to call netif_wake_queue? */
87 #define IXGBE_TX_QUEUE_WAKE 16
89 /* How many Rx Buffers do we bundle into one write to the hardware ? */
90 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
92 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
93 #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
94 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
95 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
96 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
97 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
99 #define IXGBE_MAX_LRO_DESCRIPTORS 8
100 #define IXGBE_MAX_LRO_AGGREGATE 32
102 /* wrapper around a pointer to a socket buffer,
103 * so a DMA handle can be stored along with the buffer */
104 struct ixgbe_tx_buffer
{
107 unsigned long time_stamp
;
112 struct ixgbe_rx_buffer
{
117 unsigned int page_offset
;
120 struct ixgbe_queue_stats
{
126 void *desc
; /* descriptor ring memory */
127 dma_addr_t dma
; /* phys. address of descriptor ring */
128 unsigned int size
; /* length in bytes */
129 unsigned int count
; /* amount of descriptors */
130 unsigned int next_to_use
;
131 unsigned int next_to_clean
;
133 int queue_index
; /* needed for multiqueue queue management */
135 struct ixgbe_tx_buffer
*tx_buffer_info
;
136 struct ixgbe_rx_buffer
*rx_buffer_info
;
142 unsigned int total_bytes
;
143 unsigned int total_packets
;
145 u16 reg_idx
; /* holds the special value that gets the hardware register
146 * offset associated with this ring, which is different
147 * for DCE and RSS modes */
149 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
150 /* cpu for tx queue */
153 struct net_lro_mgr lro_mgr
;
155 struct ixgbe_queue_stats stats
;
156 u16 v_idx
; /* maps directly to the index for this ring in the hardware
157 * vector array, can also be used for finding the bit in EICR
158 * and friends that represents the vector for this ring */
161 u16 work_limit
; /* max work per interrupt */
165 #define RING_F_VMDQ 1
167 #define IXGBE_MAX_RSS_INDICES 16
168 #define IXGBE_MAX_VMDQ_INDICES 16
169 struct ixgbe_ring_feature
{
174 #define MAX_RX_QUEUES 64
175 #define MAX_TX_QUEUES 32
177 /* MAX_MSIX_Q_VECTORS of these are allocated,
178 * but we only use one per queue-specific vector.
180 struct ixgbe_q_vector
{
181 struct ixgbe_adapter
*adapter
;
182 struct napi_struct napi
;
183 DECLARE_BITMAP(rxr_idx
, MAX_RX_QUEUES
); /* Rx ring indices */
184 DECLARE_BITMAP(txr_idx
, MAX_TX_QUEUES
); /* Tx ring indices */
185 u8 rxr_count
; /* Rx ring count assigned to this vector */
186 u8 txr_count
; /* Tx ring count assigned to this vector */
192 /* Helper macros to switch between ints/sec and what the register uses.
193 * And yes, it's the same math going both ways.
195 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
196 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 0)
197 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
199 #define IXGBE_DESC_UNUSED(R) \
200 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
201 (R)->next_to_clean - (R)->next_to_use - 1)
203 #define IXGBE_RX_DESC_ADV(R, i) \
204 (&(((union ixgbe_adv_rx_desc *)((R).desc))[i]))
205 #define IXGBE_TX_DESC_ADV(R, i) \
206 (&(((union ixgbe_adv_tx_desc *)((R).desc))[i]))
207 #define IXGBE_TX_CTXTDESC_ADV(R, i) \
208 (&(((struct ixgbe_adv_tx_context_desc *)((R).desc))[i]))
210 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
212 #define OTHER_VECTOR 1
213 #define NON_Q_VECTORS (OTHER_VECTOR)
215 #define MAX_MSIX_Q_VECTORS 16
216 #define MIN_MSIX_Q_VECTORS 2
217 #define MAX_MSIX_COUNT (MAX_MSIX_Q_VECTORS + NON_Q_VECTORS)
218 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
220 /* board specific private data structure */
221 struct ixgbe_adapter
{
222 struct timer_list watchdog_timer
;
223 struct vlan_group
*vlgrp
;
225 struct work_struct reset_task
;
226 struct ixgbe_q_vector q_vector
[MAX_MSIX_Q_VECTORS
];
227 char name
[MAX_MSIX_COUNT
][IFNAMSIZ
+ 5];
229 /* Interrupt Throttle Rate */
235 struct ixgbe_ring
*tx_ring
; /* One per active queue */
242 u32 tx_timeout_count
;
246 struct ixgbe_ring
*rx_ring
; /* One per active queue */
248 u64 hw_csum_rx_error
;
251 int num_msix_vectors
;
252 struct ixgbe_ring_feature ring_feature
[3];
253 struct msix_entry
*msix_entries
;
256 u32 alloc_rx_page_failed
;
257 u32 alloc_rx_buff_failed
;
259 /* Some features need tri-state capability,
260 * thus the additional *_CAPABLE flags.
263 #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
264 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
265 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
266 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
267 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
268 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
269 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
270 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
271 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
272 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
273 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
274 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
275 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
276 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
277 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
278 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
279 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
280 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
281 #define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1 << 23)
283 /* default to trying for four seconds */
284 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
286 /* OS defined structs */
287 struct net_device
*netdev
;
288 struct pci_dev
*pdev
;
289 struct net_device_stats net_stats
;
291 /* structs defined in ixgbe_hw.h */
294 struct ixgbe_hw_stats stats
;
296 /* Interrupt Throttle Rate */
304 unsigned int tx_ring_count
;
305 unsigned int rx_ring_count
;
309 unsigned long link_check_timeout
;
311 struct work_struct watchdog_task
;
324 extern struct ixgbe_info ixgbe_82598_info
;
326 extern char ixgbe_driver_name
[];
327 extern const char ixgbe_driver_version
[];
329 extern int ixgbe_up(struct ixgbe_adapter
*adapter
);
330 extern void ixgbe_down(struct ixgbe_adapter
*adapter
);
331 extern void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
);
332 extern void ixgbe_reset(struct ixgbe_adapter
*adapter
);
333 extern void ixgbe_update_stats(struct ixgbe_adapter
*adapter
);
334 extern void ixgbe_set_ethtool_ops(struct net_device
*netdev
);
335 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter
*adapter
,
336 struct ixgbe_ring
*rxdr
);
337 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter
*adapter
,
338 struct ixgbe_ring
*txdr
);
339 extern void ixgbe_free_rx_resources(struct ixgbe_adapter
*adapter
,
340 struct ixgbe_ring
*rxdr
);
341 extern void ixgbe_free_tx_resources(struct ixgbe_adapter
*adapter
,
342 struct ixgbe_ring
*txdr
);
344 #endif /* _IXGBE_H_ */