1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
42 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
43 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
44 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
);
45 static s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
46 ixgbe_link_speed speed
,
48 bool autoneg_wait_to_complete
);
49 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
50 ixgbe_link_speed speed
,
52 bool autoneg_wait_to_complete
);
53 static s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
54 bool autoneg_wait_to_complete
);
55 static s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
56 ixgbe_link_speed speed
,
58 bool autoneg_wait_to_complete
);
59 static s32
ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw
*hw
,
60 ixgbe_link_speed
*speed
,
62 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
63 ixgbe_link_speed speed
,
65 bool autoneg_wait_to_complete
);
66 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
);
68 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw
*hw
)
70 struct ixgbe_mac_info
*mac
= &hw
->mac
;
71 if (hw
->phy
.multispeed_fiber
) {
72 /* Set up dual speed SFP+ support */
73 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_multispeed_fiber
;
74 mac
->ops
.disable_tx_laser
=
75 &ixgbe_disable_tx_laser_multispeed_fiber
;
76 mac
->ops
.enable_tx_laser
=
77 &ixgbe_enable_tx_laser_multispeed_fiber
;
78 mac
->ops
.flap_tx_laser
= &ixgbe_flap_tx_laser_multispeed_fiber
;
80 mac
->ops
.disable_tx_laser
= NULL
;
81 mac
->ops
.enable_tx_laser
= NULL
;
82 mac
->ops
.flap_tx_laser
= NULL
;
83 if ((mac
->ops
.get_media_type(hw
) ==
84 ixgbe_media_type_backplane
) &&
85 (hw
->phy
.smart_speed
== ixgbe_smart_speed_auto
||
86 hw
->phy
.smart_speed
== ixgbe_smart_speed_on
))
87 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_smartspeed
;
89 mac
->ops
.setup_link
= &ixgbe_setup_mac_link_82599
;
93 static s32
ixgbe_setup_sfp_modules_82599(struct ixgbe_hw
*hw
)
96 u16 list_offset
, data_offset
, data_value
;
98 if (hw
->phy
.sfp_type
!= ixgbe_sfp_type_unknown
) {
99 ixgbe_init_mac_link_ops_82599(hw
);
101 hw
->phy
.ops
.reset
= NULL
;
103 ret_val
= ixgbe_get_sfp_init_sequence_offsets(hw
, &list_offset
,
109 /* PHY config will finish before releasing the semaphore */
110 ret_val
= ixgbe_acquire_swfw_sync(hw
, IXGBE_GSSR_MAC_CSR_SM
);
112 ret_val
= IXGBE_ERR_SWFW_SYNC
;
116 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
117 while (data_value
!= 0xffff) {
118 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, data_value
);
119 IXGBE_WRITE_FLUSH(hw
);
120 hw
->eeprom
.ops
.read(hw
, ++data_offset
, &data_value
);
122 /* Now restart DSP by setting Restart_AN */
123 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
,
124 (IXGBE_READ_REG(hw
, IXGBE_AUTOC
) | IXGBE_AUTOC_AN_RESTART
));
126 /* Release the semaphore */
127 ixgbe_release_swfw_sync(hw
, IXGBE_GSSR_MAC_CSR_SM
);
128 /* Delay obtaining semaphore again to allow FW access */
129 msleep(hw
->eeprom
.semaphore_delay
);
136 static s32
ixgbe_get_invariants_82599(struct ixgbe_hw
*hw
)
138 struct ixgbe_mac_info
*mac
= &hw
->mac
;
140 ixgbe_init_mac_link_ops_82599(hw
);
142 mac
->mcft_size
= IXGBE_82599_MC_TBL_SIZE
;
143 mac
->vft_size
= IXGBE_82599_VFT_TBL_SIZE
;
144 mac
->num_rar_entries
= IXGBE_82599_RAR_ENTRIES
;
145 mac
->max_rx_queues
= IXGBE_82599_MAX_RX_QUEUES
;
146 mac
->max_tx_queues
= IXGBE_82599_MAX_TX_QUEUES
;
147 mac
->max_msix_vectors
= ixgbe_get_pcie_msix_count_generic(hw
);
153 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
154 * @hw: pointer to hardware structure
156 * Initialize any function pointers that were not able to be
157 * set during get_invariants because the PHY/SFP type was
158 * not known. Perform the SFP init if necessary.
161 static s32
ixgbe_init_phy_ops_82599(struct ixgbe_hw
*hw
)
163 struct ixgbe_mac_info
*mac
= &hw
->mac
;
164 struct ixgbe_phy_info
*phy
= &hw
->phy
;
167 /* Identify the PHY or SFP module */
168 ret_val
= phy
->ops
.identify(hw
);
170 /* Setup function pointers based on detected SFP module and speeds */
171 ixgbe_init_mac_link_ops_82599(hw
);
173 /* If copper media, overwrite with copper function pointers */
174 if (mac
->ops
.get_media_type(hw
) == ixgbe_media_type_copper
) {
175 mac
->ops
.setup_link
= &ixgbe_setup_copper_link_82599
;
176 mac
->ops
.get_link_capabilities
=
177 &ixgbe_get_copper_link_capabilities_82599
;
180 /* Set necessary function pointers based on phy type */
181 switch (hw
->phy
.type
) {
183 phy
->ops
.check_link
= &ixgbe_check_phy_link_tnx
;
184 phy
->ops
.get_firmware_version
=
185 &ixgbe_get_phy_firmware_version_tnx
;
195 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
196 * @hw: pointer to hardware structure
197 * @speed: pointer to link speed
198 * @negotiation: true when autoneg or autotry is enabled
200 * Determines the link capabilities by reading the AUTOC register.
202 static s32
ixgbe_get_link_capabilities_82599(struct ixgbe_hw
*hw
,
203 ixgbe_link_speed
*speed
,
209 /* Determine 1G link capabilities off of SFP+ type */
210 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_cu_core0
||
211 hw
->phy
.sfp_type
== ixgbe_sfp_type_1g_cu_core1
) {
212 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
218 * Determine link capabilities based on the stored value of AUTOC,
219 * which represents EEPROM defaults. If AUTOC value has not been
220 * stored, use the current register value.
222 if (hw
->mac
.orig_link_settings_stored
)
223 autoc
= hw
->mac
.orig_autoc
;
225 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
227 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
228 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
229 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
230 *negotiation
= false;
233 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
234 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
235 *negotiation
= false;
238 case IXGBE_AUTOC_LMS_1G_AN
:
239 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
243 case IXGBE_AUTOC_LMS_10G_SERIAL
:
244 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
245 *negotiation
= false;
248 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
249 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
250 *speed
= IXGBE_LINK_SPEED_UNKNOWN
;
251 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
252 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
253 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
254 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
255 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
256 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
260 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
:
261 *speed
= IXGBE_LINK_SPEED_100_FULL
;
262 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
263 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
264 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
265 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
266 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
267 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
271 case IXGBE_AUTOC_LMS_SGMII_1G_100M
:
272 *speed
= IXGBE_LINK_SPEED_1GB_FULL
| IXGBE_LINK_SPEED_100_FULL
;
273 *negotiation
= false;
277 status
= IXGBE_ERR_LINK_SETUP
;
282 if (hw
->phy
.multispeed_fiber
) {
283 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
|
284 IXGBE_LINK_SPEED_1GB_FULL
;
293 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
294 * @hw: pointer to hardware structure
295 * @speed: pointer to link speed
296 * @autoneg: boolean auto-negotiation value
298 * Determines the link capabilities by reading the AUTOC register.
300 static s32
ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw
*hw
,
301 ixgbe_link_speed
*speed
,
304 s32 status
= IXGBE_ERR_LINK_SETUP
;
310 status
= hw
->phy
.ops
.read_reg(hw
, MDIO_SPEED
, MDIO_MMD_PMAPMD
,
314 if (speed_ability
& MDIO_SPEED_10G
)
315 *speed
|= IXGBE_LINK_SPEED_10GB_FULL
;
316 if (speed_ability
& MDIO_PMA_SPEED_1000
)
317 *speed
|= IXGBE_LINK_SPEED_1GB_FULL
;
324 * ixgbe_get_media_type_82599 - Get media type
325 * @hw: pointer to hardware structure
327 * Returns the media type (fiber, copper, backplane)
329 static enum ixgbe_media_type
ixgbe_get_media_type_82599(struct ixgbe_hw
*hw
)
331 enum ixgbe_media_type media_type
;
333 /* Detect if there is a copper PHY attached. */
334 if (hw
->phy
.type
== ixgbe_phy_cu_unknown
||
335 hw
->phy
.type
== ixgbe_phy_tn
) {
336 media_type
= ixgbe_media_type_copper
;
340 switch (hw
->device_id
) {
341 case IXGBE_DEV_ID_82599_KX4
:
342 case IXGBE_DEV_ID_82599_KX4_MEZZ
:
343 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
344 case IXGBE_DEV_ID_82599_KR
:
345 case IXGBE_DEV_ID_82599_XAUI_LOM
:
346 /* Default device ID is mezzanine card KX/KX4 */
347 media_type
= ixgbe_media_type_backplane
;
349 case IXGBE_DEV_ID_82599_SFP
:
350 case IXGBE_DEV_ID_82599_SFP_EM
:
351 media_type
= ixgbe_media_type_fiber
;
353 case IXGBE_DEV_ID_82599_CX4
:
354 media_type
= ixgbe_media_type_cx4
;
357 media_type
= ixgbe_media_type_unknown
;
365 * ixgbe_start_mac_link_82599 - Setup MAC link settings
366 * @hw: pointer to hardware structure
367 * @autoneg_wait_to_complete: true when waiting for completion is needed
369 * Configures link settings based on values in the ixgbe_hw struct.
370 * Restarts the link. Performs autonegotiation if needed.
372 static s32
ixgbe_start_mac_link_82599(struct ixgbe_hw
*hw
,
373 bool autoneg_wait_to_complete
)
381 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
382 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
383 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
385 /* Only poll for autoneg to complete if specified to do so */
386 if (autoneg_wait_to_complete
) {
387 if ((autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
388 IXGBE_AUTOC_LMS_KX4_KX_KR
||
389 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
390 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
391 (autoc_reg
& IXGBE_AUTOC_LMS_MASK
) ==
392 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
393 links_reg
= 0; /* Just in case Autoneg time = 0 */
394 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
395 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
396 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
400 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
401 status
= IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
402 hw_dbg(hw
, "Autoneg did not complete.\n");
407 /* Add delay to filter out noises during initial link setup */
414 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
415 * @hw: pointer to hardware structure
417 * The base drivers may require better control over SFP+ module
418 * PHY states. This includes selectively shutting down the Tx
419 * laser on the PHY, effectively halting physical link.
421 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
423 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
425 /* Disable tx laser; allow 100us to go dark per spec */
426 esdp_reg
|= IXGBE_ESDP_SDP3
;
427 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
428 IXGBE_WRITE_FLUSH(hw
);
433 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
434 * @hw: pointer to hardware structure
436 * The base drivers may require better control over SFP+ module
437 * PHY states. This includes selectively turning on the Tx
438 * laser on the PHY, effectively starting physical link.
440 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
442 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
444 /* Enable tx laser; allow 100ms to light up */
445 esdp_reg
&= ~IXGBE_ESDP_SDP3
;
446 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
447 IXGBE_WRITE_FLUSH(hw
);
452 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
453 * @hw: pointer to hardware structure
455 * When the driver changes the link speeds that it can support,
456 * it sets autotry_restart to true to indicate that we need to
457 * initiate a new autotry session with the link partner. To do
458 * so, we set the speed then disable and re-enable the tx laser, to
459 * alert the link partner that it also needs to restart autotry on its
460 * end. This is consistent with true clause 37 autoneg, which also
461 * involves a loss of signal.
463 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw
*hw
)
465 hw_dbg(hw
, "ixgbe_flap_tx_laser_multispeed_fiber\n");
467 if (hw
->mac
.autotry_restart
) {
468 ixgbe_disable_tx_laser_multispeed_fiber(hw
);
469 ixgbe_enable_tx_laser_multispeed_fiber(hw
);
470 hw
->mac
.autotry_restart
= false;
475 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
476 * @hw: pointer to hardware structure
477 * @speed: new link speed
478 * @autoneg: true if autonegotiation enabled
479 * @autoneg_wait_to_complete: true when waiting for completion is needed
481 * Set the link speed in the AUTOC register and restarts link.
483 s32
ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw
*hw
,
484 ixgbe_link_speed speed
,
486 bool autoneg_wait_to_complete
)
489 ixgbe_link_speed phy_link_speed
;
490 ixgbe_link_speed highest_link_speed
= IXGBE_LINK_SPEED_UNKNOWN
;
492 u32 esdp_reg
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
493 bool link_up
= false;
497 /* Mask off requested but non-supported speeds */
498 hw
->mac
.ops
.get_link_capabilities(hw
, &phy_link_speed
, &negotiation
);
499 speed
&= phy_link_speed
;
502 * Try each speed one by one, highest priority first. We do this in
503 * software because 10gb fiber doesn't support speed autonegotiation.
505 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
) {
507 highest_link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
509 /* If we already have link at this speed, just jump out */
510 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
, &link_up
, false);
512 if ((phy_link_speed
== IXGBE_LINK_SPEED_10GB_FULL
) && link_up
)
515 /* Set the module link speed */
516 esdp_reg
|= (IXGBE_ESDP_SDP5_DIR
| IXGBE_ESDP_SDP5
);
517 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
518 IXGBE_WRITE_FLUSH(hw
);
520 /* Allow module to change analog characteristics (1G->10G) */
523 status
= ixgbe_setup_mac_link_82599(hw
,
524 IXGBE_LINK_SPEED_10GB_FULL
,
526 autoneg_wait_to_complete
);
530 /* Flap the tx laser if it has not already been done */
531 hw
->mac
.ops
.flap_tx_laser(hw
);
534 * Wait for the controller to acquire link. Per IEEE 802.3ap,
535 * Section 73.10.2, we may have to wait up to 500ms if KR is
536 * attempted. 82599 uses the same timing for 10g SFI.
539 for (i
= 0; i
< 5; i
++) {
540 /* Wait for the link partner to also set speed */
543 /* If we have link, just jump out */
544 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
,
551 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
) {
553 if (highest_link_speed
== IXGBE_LINK_SPEED_UNKNOWN
)
554 highest_link_speed
= IXGBE_LINK_SPEED_1GB_FULL
;
556 /* If we already have link at this speed, just jump out */
557 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
, &link_up
, false);
559 if ((phy_link_speed
== IXGBE_LINK_SPEED_1GB_FULL
) && link_up
)
562 /* Set the module link speed */
563 esdp_reg
&= ~IXGBE_ESDP_SDP5
;
564 esdp_reg
|= IXGBE_ESDP_SDP5_DIR
;
565 IXGBE_WRITE_REG(hw
, IXGBE_ESDP
, esdp_reg
);
566 IXGBE_WRITE_FLUSH(hw
);
568 /* Allow module to change analog characteristics (10G->1G) */
571 status
= ixgbe_setup_mac_link_82599(hw
,
572 IXGBE_LINK_SPEED_1GB_FULL
,
574 autoneg_wait_to_complete
);
578 /* Flap the tx laser if it has not already been done */
579 hw
->mac
.ops
.flap_tx_laser(hw
);
581 /* Wait for the link partner to also set speed */
584 /* If we have link, just jump out */
585 hw
->mac
.ops
.check_link(hw
, &phy_link_speed
, &link_up
, false);
591 * We didn't get link. Configure back to the highest speed we tried,
592 * (if there was more than one). We call ourselves back with just the
593 * single highest speed that the user requested.
596 status
= ixgbe_setup_mac_link_multispeed_fiber(hw
,
599 autoneg_wait_to_complete
);
602 /* Set autoneg_advertised value based on input link speed */
603 hw
->phy
.autoneg_advertised
= 0;
605 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
606 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
608 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
609 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
615 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
616 * @hw: pointer to hardware structure
617 * @speed: new link speed
618 * @autoneg: true if autonegotiation enabled
619 * @autoneg_wait_to_complete: true when waiting for completion is needed
621 * Implements the Intel SmartSpeed algorithm.
623 static s32
ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw
*hw
,
624 ixgbe_link_speed speed
, bool autoneg
,
625 bool autoneg_wait_to_complete
)
628 ixgbe_link_speed link_speed
;
630 bool link_up
= false;
631 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
632 struct ixgbe_adapter
*adapter
= hw
->back
;
634 hw_dbg(hw
, "ixgbe_setup_mac_link_smartspeed.\n");
636 /* Set autoneg_advertised value based on input link speed */
637 hw
->phy
.autoneg_advertised
= 0;
639 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
640 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
642 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
643 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
645 if (speed
& IXGBE_LINK_SPEED_100_FULL
)
646 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_100_FULL
;
649 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
650 * autoneg advertisement if link is unable to be established at the
651 * highest negotiated rate. This can sometimes happen due to integrity
652 * issues with the physical media connection.
655 /* First, try to get link with full advertisement */
656 hw
->phy
.smart_speed_active
= false;
657 for (j
= 0; j
< IXGBE_SMARTSPEED_MAX_RETRIES
; j
++) {
658 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
659 autoneg_wait_to_complete
);
664 * Wait for the controller to acquire link. Per IEEE 802.3ap,
665 * Section 73.10.2, we may have to wait up to 500ms if KR is
666 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
667 * Table 9 in the AN MAS.
669 for (i
= 0; i
< 5; i
++) {
672 /* If we have link, just jump out */
673 hw
->mac
.ops
.check_link(hw
, &link_speed
,
681 * We didn't get link. If we advertised KR plus one of KX4/KX
682 * (or BX4/BX), then disable KR and try again.
684 if (((autoc_reg
& IXGBE_AUTOC_KR_SUPP
) == 0) ||
685 ((autoc_reg
& IXGBE_AUTOC_KX4_KX_SUPP_MASK
) == 0))
688 /* Turn SmartSpeed on to disable KR support */
689 hw
->phy
.smart_speed_active
= true;
690 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
691 autoneg_wait_to_complete
);
696 * Wait for the controller to acquire link. 600ms will allow for
697 * the AN link_fail_inhibit_timer as well for multiple cycles of
698 * parallel detect, both 10g and 1g. This allows for the maximum
699 * connect attempts as defined in the AN MAS table 73-7.
701 for (i
= 0; i
< 6; i
++) {
704 /* If we have link, just jump out */
705 hw
->mac
.ops
.check_link(hw
, &link_speed
,
711 /* We didn't get link. Turn SmartSpeed back off. */
712 hw
->phy
.smart_speed_active
= false;
713 status
= ixgbe_setup_mac_link_82599(hw
, speed
, autoneg
,
714 autoneg_wait_to_complete
);
717 if (link_up
&& (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
))
718 e_info(hw
, "Smartspeed has downgraded the link speed from "
719 "the maximum advertised\n");
724 * ixgbe_setup_mac_link_82599 - Set MAC link speed
725 * @hw: pointer to hardware structure
726 * @speed: new link speed
727 * @autoneg: true if autonegotiation enabled
728 * @autoneg_wait_to_complete: true when waiting for completion is needed
730 * Set the link speed in the AUTOC register and restarts link.
732 static s32
ixgbe_setup_mac_link_82599(struct ixgbe_hw
*hw
,
733 ixgbe_link_speed speed
, bool autoneg
,
734 bool autoneg_wait_to_complete
)
737 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
738 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
739 u32 start_autoc
= autoc
;
741 u32 link_mode
= autoc
& IXGBE_AUTOC_LMS_MASK
;
742 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
743 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
746 ixgbe_link_speed link_capabilities
= IXGBE_LINK_SPEED_UNKNOWN
;
748 /* Check to see if speed passed in is supported. */
749 hw
->mac
.ops
.get_link_capabilities(hw
, &link_capabilities
, &autoneg
);
750 speed
&= link_capabilities
;
752 if (speed
== IXGBE_LINK_SPEED_UNKNOWN
) {
753 status
= IXGBE_ERR_LINK_SETUP
;
757 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
758 if (hw
->mac
.orig_link_settings_stored
)
759 orig_autoc
= hw
->mac
.orig_autoc
;
764 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
765 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
766 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
767 /* Set KX4/KX/KR support according to speed requested */
768 autoc
&= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK
| IXGBE_AUTOC_KR_SUPP
);
769 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
770 if (orig_autoc
& IXGBE_AUTOC_KX4_SUPP
)
771 autoc
|= IXGBE_AUTOC_KX4_SUPP
;
772 if ((orig_autoc
& IXGBE_AUTOC_KR_SUPP
) &&
773 (hw
->phy
.smart_speed_active
== false))
774 autoc
|= IXGBE_AUTOC_KR_SUPP
;
775 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
776 autoc
|= IXGBE_AUTOC_KX_SUPP
;
777 } else if ((pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
) &&
778 (link_mode
== IXGBE_AUTOC_LMS_1G_LINK_NO_AN
||
779 link_mode
== IXGBE_AUTOC_LMS_1G_AN
)) {
780 /* Switch from 1G SFI to 10G SFI if requested */
781 if ((speed
== IXGBE_LINK_SPEED_10GB_FULL
) &&
782 (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)) {
783 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
784 autoc
|= IXGBE_AUTOC_LMS_10G_SERIAL
;
786 } else if ((pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
) &&
787 (link_mode
== IXGBE_AUTOC_LMS_10G_SERIAL
)) {
788 /* Switch from 10G SFI to 1G SFI if requested */
789 if ((speed
== IXGBE_LINK_SPEED_1GB_FULL
) &&
790 (pma_pmd_1g
== IXGBE_AUTOC_1G_SFI
)) {
791 autoc
&= ~IXGBE_AUTOC_LMS_MASK
;
793 autoc
|= IXGBE_AUTOC_LMS_1G_AN
;
795 autoc
|= IXGBE_AUTOC_LMS_1G_LINK_NO_AN
;
799 if (autoc
!= start_autoc
) {
801 autoc
|= IXGBE_AUTOC_AN_RESTART
;
802 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc
);
804 /* Only poll for autoneg to complete if specified to do so */
805 if (autoneg_wait_to_complete
) {
806 if (link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR
||
807 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
||
808 link_mode
== IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII
) {
809 links_reg
= 0; /*Just in case Autoneg time=0*/
810 for (i
= 0; i
< IXGBE_AUTO_NEG_TIME
; i
++) {
812 IXGBE_READ_REG(hw
, IXGBE_LINKS
);
813 if (links_reg
& IXGBE_LINKS_KX_AN_COMP
)
817 if (!(links_reg
& IXGBE_LINKS_KX_AN_COMP
)) {
819 IXGBE_ERR_AUTONEG_NOT_COMPLETE
;
820 hw_dbg(hw
, "Autoneg did not "
826 /* Add delay to filter out noises during initial link setup */
835 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
836 * @hw: pointer to hardware structure
837 * @speed: new link speed
838 * @autoneg: true if autonegotiation enabled
839 * @autoneg_wait_to_complete: true if waiting is needed to complete
841 * Restarts link on PHY and MAC based on settings passed in.
843 static s32
ixgbe_setup_copper_link_82599(struct ixgbe_hw
*hw
,
844 ixgbe_link_speed speed
,
846 bool autoneg_wait_to_complete
)
850 /* Setup the PHY according to input speed */
851 status
= hw
->phy
.ops
.setup_link_speed(hw
, speed
, autoneg
,
852 autoneg_wait_to_complete
);
854 ixgbe_start_mac_link_82599(hw
, autoneg_wait_to_complete
);
860 * ixgbe_reset_hw_82599 - Perform hardware reset
861 * @hw: pointer to hardware structure
863 * Resets the hardware by resetting the transmit and receive units, masks
864 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
867 static s32
ixgbe_reset_hw_82599(struct ixgbe_hw
*hw
)
875 /* Call adapter stop to disable tx/rx and clear interrupts */
876 hw
->mac
.ops
.stop_adapter(hw
);
878 /* PHY ops must be identified and initialized prior to reset */
880 /* Init PHY and function pointers, perform SFP setup */
881 status
= hw
->phy
.ops
.init(hw
);
883 if (status
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
886 /* Setup SFP module if there is one present. */
887 if (hw
->phy
.sfp_setup_needed
) {
888 status
= hw
->mac
.ops
.setup_sfp(hw
);
889 hw
->phy
.sfp_setup_needed
= false;
893 if (hw
->phy
.reset_disable
== false && hw
->phy
.ops
.reset
!= NULL
)
894 hw
->phy
.ops
.reset(hw
);
897 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
898 * access and verify no pending requests before reset
900 status
= ixgbe_disable_pcie_master(hw
);
902 status
= IXGBE_ERR_MASTER_REQUESTS_PENDING
;
903 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
907 * Issue global reset to the MAC. This needs to be a SW reset.
908 * If link reset is used, it might reset the MAC when mng is using it
910 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
911 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, (ctrl
| IXGBE_CTRL_RST
));
912 IXGBE_WRITE_FLUSH(hw
);
914 /* Poll for reset bit to self-clear indicating reset is complete */
915 for (i
= 0; i
< 10; i
++) {
917 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
918 if (!(ctrl
& IXGBE_CTRL_RST
))
921 if (ctrl
& IXGBE_CTRL_RST
) {
922 status
= IXGBE_ERR_RESET_FAILED
;
923 hw_dbg(hw
, "Reset polling failed to complete.\n");
929 * Store the original AUTOC/AUTOC2 values if they have not been
930 * stored off yet. Otherwise restore the stored original
931 * values since the reset operation sets back to defaults.
933 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
934 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
935 if (hw
->mac
.orig_link_settings_stored
== false) {
936 hw
->mac
.orig_autoc
= autoc
;
937 hw
->mac
.orig_autoc2
= autoc2
;
938 hw
->mac
.orig_link_settings_stored
= true;
940 if (autoc
!= hw
->mac
.orig_autoc
)
941 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, (hw
->mac
.orig_autoc
|
942 IXGBE_AUTOC_AN_RESTART
));
944 if ((autoc2
& IXGBE_AUTOC2_UPPER_MASK
) !=
945 (hw
->mac
.orig_autoc2
& IXGBE_AUTOC2_UPPER_MASK
)) {
946 autoc2
&= ~IXGBE_AUTOC2_UPPER_MASK
;
947 autoc2
|= (hw
->mac
.orig_autoc2
&
948 IXGBE_AUTOC2_UPPER_MASK
);
949 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC2
, autoc2
);
954 * Store MAC address from RAR0, clear receive address registers, and
955 * clear the multicast table. Also reset num_rar_entries to 128,
956 * since we modify this value when programming the SAN MAC address.
958 hw
->mac
.num_rar_entries
= 128;
959 hw
->mac
.ops
.init_rx_addrs(hw
);
961 /* Store the permanent mac address */
962 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.perm_addr
);
964 /* Store the permanent SAN mac address */
965 hw
->mac
.ops
.get_san_mac_addr(hw
, hw
->mac
.san_addr
);
967 /* Add the SAN MAC address to the RAR only if it's a valid address */
968 if (ixgbe_validate_mac_addr(hw
->mac
.san_addr
) == 0) {
969 hw
->mac
.ops
.set_rar(hw
, hw
->mac
.num_rar_entries
- 1,
970 hw
->mac
.san_addr
, 0, IXGBE_RAH_AV
);
972 /* Reserve the last RAR for the SAN MAC address */
973 hw
->mac
.num_rar_entries
--;
976 /* Store the alternative WWNN/WWPN prefix */
977 hw
->mac
.ops
.get_wwn_prefix(hw
, &hw
->mac
.wwnn_prefix
,
978 &hw
->mac
.wwpn_prefix
);
985 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
986 * @hw: pointer to hardware structure
988 s32
ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw
*hw
)
991 u32 fdirctrl
= IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
);
992 fdirctrl
&= ~IXGBE_FDIRCTRL_INIT_DONE
;
995 * Before starting reinitialization process,
996 * FDIRCMD.CMD must be zero.
998 for (i
= 0; i
< IXGBE_FDIRCMD_CMD_POLL
; i
++) {
999 if (!(IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1000 IXGBE_FDIRCMD_CMD_MASK
))
1004 if (i
>= IXGBE_FDIRCMD_CMD_POLL
) {
1005 hw_dbg(hw
,"Flow Director previous command isn't complete, "
1006 "aborting table re-initialization.\n");
1007 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1010 IXGBE_WRITE_REG(hw
, IXGBE_FDIRFREE
, 0);
1011 IXGBE_WRITE_FLUSH(hw
);
1013 * 82599 adapters flow director init flow cannot be restarted,
1014 * Workaround 82599 silicon errata by performing the following steps
1015 * before re-writing the FDIRCTRL control register with the same value.
1016 * - write 1 to bit 8 of FDIRCMD register &
1017 * - write 0 to bit 8 of FDIRCMD register
1019 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1020 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) |
1021 IXGBE_FDIRCMD_CLEARHT
));
1022 IXGBE_WRITE_FLUSH(hw
);
1023 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
,
1024 (IXGBE_READ_REG(hw
, IXGBE_FDIRCMD
) &
1025 ~IXGBE_FDIRCMD_CLEARHT
));
1026 IXGBE_WRITE_FLUSH(hw
);
1028 * Clear FDIR Hash register to clear any leftover hashes
1029 * waiting to be programmed.
1031 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, 0x00);
1032 IXGBE_WRITE_FLUSH(hw
);
1034 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1035 IXGBE_WRITE_FLUSH(hw
);
1037 /* Poll init-done after we write FDIRCTRL register */
1038 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1039 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1040 IXGBE_FDIRCTRL_INIT_DONE
)
1044 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
) {
1045 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1046 return IXGBE_ERR_FDIR_REINIT_FAILED
;
1049 /* Clear FDIR statistics registers (read to clear) */
1050 IXGBE_READ_REG(hw
, IXGBE_FDIRUSTAT
);
1051 IXGBE_READ_REG(hw
, IXGBE_FDIRFSTAT
);
1052 IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
1053 IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
1054 IXGBE_READ_REG(hw
, IXGBE_FDIRLEN
);
1060 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1061 * @hw: pointer to hardware structure
1062 * @pballoc: which mode to allocate filters with
1064 s32
ixgbe_init_fdir_signature_82599(struct ixgbe_hw
*hw
, u32 pballoc
)
1071 * Before enabling Flow Director, the Rx Packet Buffer size
1072 * must be reduced. The new value is the current size minus
1073 * flow director memory usage size.
1075 pbsize
= (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT
+ pballoc
));
1076 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(0),
1077 (IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(0)) - pbsize
));
1080 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1081 * initialized to zero for non DCB mode otherwise actual total RX PB
1082 * would be bigger than programmed and filter space would run into
1085 for (i
= 1; i
< 8; i
++)
1086 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
1088 /* Send interrupt when 64 filters are left */
1089 fdirctrl
|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
;
1091 /* Set the maximum length per hash bucket to 0xA filters */
1092 fdirctrl
|= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
;
1095 case IXGBE_FDIR_PBALLOC_64K
:
1096 /* 8k - 1 signature filters */
1097 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_64K
;
1099 case IXGBE_FDIR_PBALLOC_128K
:
1100 /* 16k - 1 signature filters */
1101 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_128K
;
1103 case IXGBE_FDIR_PBALLOC_256K
:
1104 /* 32k - 1 signature filters */
1105 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_256K
;
1109 return IXGBE_ERR_CONFIG
;
1112 /* Move the flexible bytes to use the ethertype - shift 6 words */
1113 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
);
1115 fdirctrl
|= IXGBE_FDIRCTRL_REPORT_STATUS
;
1117 /* Prime the keys for hashing */
1118 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
,
1119 htonl(IXGBE_ATR_BUCKET_HASH_KEY
));
1120 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
,
1121 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY
));
1124 * Poll init-done after we write the register. Estimated times:
1125 * 10G: PBALLOC = 11b, timing is 60us
1126 * 1G: PBALLOC = 11b, timing is 600us
1127 * 100M: PBALLOC = 11b, timing is 6ms
1129 * Multiple these timings by 4 if under full Rx load
1131 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1132 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1133 * this might not finish in our poll time, but we can live with that
1136 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1137 IXGBE_WRITE_FLUSH(hw
);
1138 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1139 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1140 IXGBE_FDIRCTRL_INIT_DONE
)
1144 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1145 hw_dbg(hw
, "Flow Director Signature poll time exceeded!\n");
1151 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1152 * @hw: pointer to hardware structure
1153 * @pballoc: which mode to allocate filters with
1155 s32
ixgbe_init_fdir_perfect_82599(struct ixgbe_hw
*hw
, u32 pballoc
)
1162 * Before enabling Flow Director, the Rx Packet Buffer size
1163 * must be reduced. The new value is the current size minus
1164 * flow director memory usage size.
1166 pbsize
= (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT
+ pballoc
));
1167 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(0),
1168 (IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(0)) - pbsize
));
1171 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1172 * initialized to zero for non DCB mode otherwise actual total RX PB
1173 * would be bigger than programmed and filter space would run into
1176 for (i
= 1; i
< 8; i
++)
1177 IXGBE_WRITE_REG(hw
, IXGBE_RXPBSIZE(i
), 0);
1179 /* Send interrupt when 64 filters are left */
1180 fdirctrl
|= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT
;
1182 /* Initialize the drop queue to Rx queue 127 */
1183 fdirctrl
|= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT
);
1186 case IXGBE_FDIR_PBALLOC_64K
:
1187 /* 2k - 1 perfect filters */
1188 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_64K
;
1190 case IXGBE_FDIR_PBALLOC_128K
:
1191 /* 4k - 1 perfect filters */
1192 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_128K
;
1194 case IXGBE_FDIR_PBALLOC_256K
:
1195 /* 8k - 1 perfect filters */
1196 fdirctrl
|= IXGBE_FDIRCTRL_PBALLOC_256K
;
1200 return IXGBE_ERR_CONFIG
;
1203 /* Turn perfect match filtering on */
1204 fdirctrl
|= IXGBE_FDIRCTRL_PERFECT_MATCH
;
1205 fdirctrl
|= IXGBE_FDIRCTRL_REPORT_STATUS
;
1207 /* Move the flexible bytes to use the ethertype - shift 6 words */
1208 fdirctrl
|= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT
);
1210 /* Prime the keys for hashing */
1211 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHKEY
,
1212 htonl(IXGBE_ATR_BUCKET_HASH_KEY
));
1213 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSKEY
,
1214 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY
));
1217 * Poll init-done after we write the register. Estimated times:
1218 * 10G: PBALLOC = 11b, timing is 60us
1219 * 1G: PBALLOC = 11b, timing is 600us
1220 * 100M: PBALLOC = 11b, timing is 6ms
1222 * Multiple these timings by 4 if under full Rx load
1224 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1225 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1226 * this might not finish in our poll time, but we can live with that
1230 /* Set the maximum length per hash bucket to 0xA filters */
1231 fdirctrl
|= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT
);
1233 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCTRL
, fdirctrl
);
1234 IXGBE_WRITE_FLUSH(hw
);
1235 for (i
= 0; i
< IXGBE_FDIR_INIT_DONE_POLL
; i
++) {
1236 if (IXGBE_READ_REG(hw
, IXGBE_FDIRCTRL
) &
1237 IXGBE_FDIRCTRL_INIT_DONE
)
1241 if (i
>= IXGBE_FDIR_INIT_DONE_POLL
)
1242 hw_dbg(hw
, "Flow Director Perfect poll time exceeded!\n");
1249 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1250 * @stream: input bitstream to compute the hash on
1251 * @key: 32-bit hash key
1253 static u16
ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input
*atr_input
,
1257 * The algorithm is as follows:
1258 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1259 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1260 * and A[n] x B[n] is bitwise AND between same length strings
1262 * K[n] is 16 bits, defined as:
1263 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1264 * for n modulo 32 < 15, K[n] =
1265 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1267 * S[n] is 16 bits, defined as:
1268 * for n >= 15, S[n] = S[n:n - 15]
1269 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1271 * To simplify for programming, the algorithm is implemented
1272 * in software this way:
1274 * Key[31:0], Stream[335:0]
1276 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1277 * int_key[350:0] = tmp_key[351:1]
1278 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1281 * for (i = 0; i < 351; i++) {
1283 * hash ^= int_stream[(i + 15):i];
1293 u8
*stream
= (u8
*)atr_input
;
1294 u8 int_key
[44]; /* upper-most bit unused */
1295 u8 hash_str
[46]; /* upper-most 2 bits unused */
1296 u16 hash_result
= 0;
1300 * Initialize the fill member to prevent warnings
1303 tmp_key
.fill
[0] = 0;
1305 /* First load the temporary key stream */
1306 for (i
= 0; i
< 6; i
++) {
1307 u64 fillkey
= ((u64
)key
<< 32) | key
;
1308 tmp_key
.fill
[i
] = fillkey
;
1312 * Set the interim key for the hashing. Bit 352 is unused, so we must
1313 * shift and compensate when building the key.
1316 int_key
[0] = tmp_key
.key_stream
[0] >> 1;
1317 for (i
= 1, j
= 0; i
< 44; i
++) {
1318 unsigned int this_key
= tmp_key
.key_stream
[j
] << 7;
1320 int_key
[i
] = (u8
)(this_key
| (tmp_key
.key_stream
[j
] >> 1));
1324 * Set the interim bit string for the hashing. Bits 368 and 367 are
1325 * unused, so shift and compensate when building the string.
1327 hash_str
[0] = (stream
[40] & 0x7f) >> 1;
1328 for (i
= 1, j
= 40; i
< 46; i
++) {
1329 unsigned int this_str
= stream
[j
] << 7;
1333 hash_str
[i
] = (u8
)(this_str
| (stream
[j
] >> 1));
1337 * Now compute the hash. i is the index into hash_str, j is into our
1338 * key stream, k is counting the number of bits, and h interates within
1341 for (i
= 45, j
= 43, k
= 0; k
< 351 && i
>= 2 && j
>= 0; i
--, j
--) {
1342 for (h
= 0; h
< 8 && k
< 351; h
++, k
++) {
1343 if (int_key
[j
] & (1 << h
)) {
1345 * Key bit is set, XOR in the current 16-bit
1346 * string. Example of processing:
1348 * tmp = (hash_str[i - 2] & 0 << 16) |
1349 * (hash_str[i - 1] & 0xff << 8) |
1350 * (hash_str[i] & 0xff >> 0)
1351 * So tmp = hash_str[15 + k:k], since the
1352 * i + 2 clause rolls off the 16-bit value
1354 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1355 * (hash_str[i - 1] & 0xff << 1) |
1356 * (hash_str[i] & 0x80 >> 7)
1358 int tmp
= (hash_str
[i
] >> h
);
1359 tmp
|= (hash_str
[i
- 1] << (8 - h
));
1360 tmp
|= (int)(hash_str
[i
- 2] & ((1 << h
) - 1))
1362 hash_result
^= (u16
)tmp
;
1371 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1372 * @input: input stream to modify
1373 * @vlan: the VLAN id to load
1375 s32
ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input
*input
, u16 vlan
)
1377 input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
+ 1] = vlan
>> 8;
1378 input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
] = vlan
& 0xff;
1384 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1385 * @input: input stream to modify
1386 * @src_addr: the IP address to load
1388 s32
ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input
*input
, u32 src_addr
)
1390 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 3] = src_addr
>> 24;
1391 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 2] =
1392 (src_addr
>> 16) & 0xff;
1393 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 1] =
1394 (src_addr
>> 8) & 0xff;
1395 input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
] = src_addr
& 0xff;
1401 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1402 * @input: input stream to modify
1403 * @dst_addr: the IP address to load
1405 s32
ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input
*input
, u32 dst_addr
)
1407 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 3] = dst_addr
>> 24;
1408 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 2] =
1409 (dst_addr
>> 16) & 0xff;
1410 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 1] =
1411 (dst_addr
>> 8) & 0xff;
1412 input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
] = dst_addr
& 0xff;
1418 * ixgbe_atr_set_src_port_82599 - Sets the source port
1419 * @input: input stream to modify
1420 * @src_port: the source port to load
1422 s32
ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input
*input
, u16 src_port
)
1424 input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
+ 1] = src_port
>> 8;
1425 input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
] = src_port
& 0xff;
1431 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1432 * @input: input stream to modify
1433 * @dst_port: the destination port to load
1435 s32
ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input
*input
, u16 dst_port
)
1437 input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
+ 1] = dst_port
>> 8;
1438 input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
] = dst_port
& 0xff;
1444 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1445 * @input: input stream to modify
1446 * @flex_bytes: the flexible bytes to load
1448 s32
ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input
*input
, u16 flex_byte
)
1450 input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
+ 1] = flex_byte
>> 8;
1451 input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
] = flex_byte
& 0xff;
1457 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1458 * @input: input stream to modify
1459 * @l4type: the layer 4 type value to load
1461 s32
ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input
*input
, u8 l4type
)
1463 input
->byte_stream
[IXGBE_ATR_L4TYPE_OFFSET
] = l4type
;
1469 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1470 * @input: input stream to search
1471 * @vlan: the VLAN id to load
1473 static s32
ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input
*input
, u16
*vlan
)
1475 *vlan
= input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
];
1476 *vlan
|= input
->byte_stream
[IXGBE_ATR_VLAN_OFFSET
+ 1] << 8;
1482 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1483 * @input: input stream to search
1484 * @src_addr: the IP address to load
1486 static s32
ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input
*input
,
1489 *src_addr
= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
];
1490 *src_addr
|= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 1] << 8;
1491 *src_addr
|= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 2] << 16;
1492 *src_addr
|= input
->byte_stream
[IXGBE_ATR_SRC_IPV4_OFFSET
+ 3] << 24;
1498 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1499 * @input: input stream to search
1500 * @dst_addr: the IP address to load
1502 static s32
ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input
*input
,
1505 *dst_addr
= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
];
1506 *dst_addr
|= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 1] << 8;
1507 *dst_addr
|= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 2] << 16;
1508 *dst_addr
|= input
->byte_stream
[IXGBE_ATR_DST_IPV4_OFFSET
+ 3] << 24;
1514 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1515 * @input: input stream to search
1516 * @src_addr_1: the first 4 bytes of the IP address to load
1517 * @src_addr_2: the second 4 bytes of the IP address to load
1518 * @src_addr_3: the third 4 bytes of the IP address to load
1519 * @src_addr_4: the fourth 4 bytes of the IP address to load
1521 static s32
ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input
*input
,
1522 u32
*src_addr_1
, u32
*src_addr_2
,
1523 u32
*src_addr_3
, u32
*src_addr_4
)
1525 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 12];
1526 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 13] << 8;
1527 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 14] << 16;
1528 *src_addr_1
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 15] << 24;
1530 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 8];
1531 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 9] << 8;
1532 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 10] << 16;
1533 *src_addr_2
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 11] << 24;
1535 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 4];
1536 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 5] << 8;
1537 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 6] << 16;
1538 *src_addr_3
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 7] << 24;
1540 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
];
1541 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 1] << 8;
1542 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 2] << 16;
1543 *src_addr_4
= input
->byte_stream
[IXGBE_ATR_SRC_IPV6_OFFSET
+ 3] << 24;
1549 * ixgbe_atr_get_src_port_82599 - Gets the source port
1550 * @input: input stream to modify
1551 * @src_port: the source port to load
1553 * Even though the input is given in big-endian, the FDIRPORT registers
1554 * expect the ports to be programmed in little-endian. Hence the need to swap
1555 * endianness when retrieving the data. This can be confusing since the
1556 * internal hash engine expects it to be big-endian.
1558 static s32
ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input
*input
,
1561 *src_port
= input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
] << 8;
1562 *src_port
|= input
->byte_stream
[IXGBE_ATR_SRC_PORT_OFFSET
+ 1];
1568 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1569 * @input: input stream to modify
1570 * @dst_port: the destination port to load
1572 * Even though the input is given in big-endian, the FDIRPORT registers
1573 * expect the ports to be programmed in little-endian. Hence the need to swap
1574 * endianness when retrieving the data. This can be confusing since the
1575 * internal hash engine expects it to be big-endian.
1577 static s32
ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input
*input
,
1580 *dst_port
= input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
] << 8;
1581 *dst_port
|= input
->byte_stream
[IXGBE_ATR_DST_PORT_OFFSET
+ 1];
1587 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1588 * @input: input stream to modify
1589 * @flex_bytes: the flexible bytes to load
1591 static s32
ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input
*input
,
1594 *flex_byte
= input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
];
1595 *flex_byte
|= input
->byte_stream
[IXGBE_ATR_FLEX_BYTE_OFFSET
+ 1] << 8;
1601 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1602 * @input: input stream to modify
1603 * @l4type: the layer 4 type value to load
1605 static s32
ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input
*input
,
1608 *l4type
= input
->byte_stream
[IXGBE_ATR_L4TYPE_OFFSET
];
1614 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1615 * @hw: pointer to hardware structure
1616 * @stream: input bitstream
1617 * @queue: queue index to direct traffic to
1619 s32
ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw
*hw
,
1620 struct ixgbe_atr_input
*input
,
1626 u16 bucket_hash
, sig_hash
;
1629 bucket_hash
= ixgbe_atr_compute_hash_82599(input
,
1630 IXGBE_ATR_BUCKET_HASH_KEY
);
1632 /* bucket_hash is only 15 bits */
1633 bucket_hash
&= IXGBE_ATR_HASH_MASK
;
1635 sig_hash
= ixgbe_atr_compute_hash_82599(input
,
1636 IXGBE_ATR_SIGNATURE_HASH_KEY
);
1638 /* Get the l4type in order to program FDIRCMD properly */
1639 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1640 ixgbe_atr_get_l4type_82599(input
, &l4type
);
1643 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1644 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1646 fdirhash
= sig_hash
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
| bucket_hash
;
1648 fdircmd
= (IXGBE_FDIRCMD_CMD_ADD_FLOW
| IXGBE_FDIRCMD_FILTER_UPDATE
|
1649 IXGBE_FDIRCMD_LAST
| IXGBE_FDIRCMD_QUEUE_EN
);
1651 switch (l4type
& IXGBE_ATR_L4TYPE_MASK
) {
1652 case IXGBE_ATR_L4TYPE_TCP
:
1653 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_TCP
;
1655 case IXGBE_ATR_L4TYPE_UDP
:
1656 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_UDP
;
1658 case IXGBE_ATR_L4TYPE_SCTP
:
1659 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_SCTP
;
1662 hw_dbg(hw
, "Error on l4type input\n");
1663 return IXGBE_ERR_CONFIG
;
1666 if (l4type
& IXGBE_ATR_L4TYPE_IPV6_MASK
)
1667 fdircmd
|= IXGBE_FDIRCMD_IPV6
;
1669 fdircmd
|= ((u64
)queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
);
1670 fdirhashcmd
= ((fdircmd
<< 32) | fdirhash
);
1672 IXGBE_WRITE_REG64(hw
, IXGBE_FDIRHASH
, fdirhashcmd
);
1678 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1679 * @hw: pointer to hardware structure
1680 * @input: input bitstream
1681 * @input_masks: bitwise masks for relevant fields
1682 * @soft_id: software index into the silicon hash tables for filter storage
1683 * @queue: queue index to direct traffic to
1685 * Note that the caller to this function must lock before calling, since the
1686 * hardware writes must be protected from one another.
1688 s32
ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw
*hw
,
1689 struct ixgbe_atr_input
*input
,
1690 struct ixgbe_atr_input_masks
*input_masks
,
1691 u16 soft_id
, u8 queue
)
1695 u32 src_ipv4
= 0, dst_ipv4
= 0;
1696 u32 src_ipv6_1
, src_ipv6_2
, src_ipv6_3
, src_ipv6_4
;
1697 u16 src_port
, dst_port
, vlan_id
, flex_bytes
;
1702 /* Get our input values */
1703 ixgbe_atr_get_l4type_82599(input
, &l4type
);
1706 * Check l4type formatting, and bail out before we touch the hardware
1707 * if there's a configuration issue
1709 switch (l4type
& IXGBE_ATR_L4TYPE_MASK
) {
1710 case IXGBE_ATR_L4TYPE_TCP
:
1711 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_TCP
;
1713 case IXGBE_ATR_L4TYPE_UDP
:
1714 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_UDP
;
1716 case IXGBE_ATR_L4TYPE_SCTP
:
1717 fdircmd
|= IXGBE_FDIRCMD_L4TYPE_SCTP
;
1720 hw_dbg(hw
, "Error on l4type input\n");
1721 return IXGBE_ERR_CONFIG
;
1724 bucket_hash
= ixgbe_atr_compute_hash_82599(input
,
1725 IXGBE_ATR_BUCKET_HASH_KEY
);
1727 /* bucket_hash is only 15 bits */
1728 bucket_hash
&= IXGBE_ATR_HASH_MASK
;
1730 ixgbe_atr_get_vlan_id_82599(input
, &vlan_id
);
1731 ixgbe_atr_get_src_port_82599(input
, &src_port
);
1732 ixgbe_atr_get_dst_port_82599(input
, &dst_port
);
1733 ixgbe_atr_get_flex_byte_82599(input
, &flex_bytes
);
1735 fdirhash
= soft_id
<< IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT
| bucket_hash
;
1737 /* Now figure out if we're IPv4 or IPv6 */
1738 if (l4type
& IXGBE_ATR_L4TYPE_IPV6_MASK
) {
1740 ixgbe_atr_get_src_ipv6_82599(input
, &src_ipv6_1
, &src_ipv6_2
,
1741 &src_ipv6_3
, &src_ipv6_4
);
1743 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSIPv6(0), src_ipv6_1
);
1744 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSIPv6(1), src_ipv6_2
);
1745 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSIPv6(2), src_ipv6_3
);
1746 /* The last 4 bytes is the same register as IPv4 */
1747 IXGBE_WRITE_REG(hw
, IXGBE_FDIRIPSA
, src_ipv6_4
);
1749 fdircmd
|= IXGBE_FDIRCMD_IPV6
;
1750 fdircmd
|= IXGBE_FDIRCMD_IPv6DMATCH
;
1753 ixgbe_atr_get_src_ipv4_82599(input
, &src_ipv4
);
1754 IXGBE_WRITE_REG(hw
, IXGBE_FDIRIPSA
, src_ipv4
);
1757 ixgbe_atr_get_dst_ipv4_82599(input
, &dst_ipv4
);
1758 IXGBE_WRITE_REG(hw
, IXGBE_FDIRIPDA
, dst_ipv4
);
1760 IXGBE_WRITE_REG(hw
, IXGBE_FDIRVLAN
, (vlan_id
|
1761 (flex_bytes
<< IXGBE_FDIRVLAN_FLEX_SHIFT
)));
1762 IXGBE_WRITE_REG(hw
, IXGBE_FDIRPORT
, (src_port
|
1763 (dst_port
<< IXGBE_FDIRPORT_DESTINATION_SHIFT
)));
1766 * Program the relevant mask registers. L4type cannot be
1767 * masked out in this implementation.
1769 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1772 IXGBE_WRITE_REG(hw
, IXGBE_FDIRSIP4M
, input_masks
->src_ip_mask
);
1773 IXGBE_WRITE_REG(hw
, IXGBE_FDIRDIP4M
, input_masks
->dst_ip_mask
);
1775 switch (l4type
& IXGBE_ATR_L4TYPE_MASK
) {
1776 case IXGBE_ATR_L4TYPE_TCP
:
1777 IXGBE_WRITE_REG(hw
, IXGBE_FDIRTCPM
, input_masks
->src_port_mask
);
1778 IXGBE_WRITE_REG(hw
, IXGBE_FDIRTCPM
,
1779 (IXGBE_READ_REG(hw
, IXGBE_FDIRTCPM
) |
1780 (input_masks
->dst_port_mask
<< 16)));
1782 case IXGBE_ATR_L4TYPE_UDP
:
1783 IXGBE_WRITE_REG(hw
, IXGBE_FDIRUDPM
, input_masks
->src_port_mask
);
1784 IXGBE_WRITE_REG(hw
, IXGBE_FDIRUDPM
,
1785 (IXGBE_READ_REG(hw
, IXGBE_FDIRUDPM
) |
1786 (input_masks
->src_port_mask
<< 16)));
1789 /* this already would have failed above */
1793 /* Program the last mask register, FDIRM */
1794 if (input_masks
->vlan_id_mask
)
1795 /* Mask both VLAN and VLANP - bits 0 and 1 */
1798 if (input_masks
->data_mask
)
1799 /* Flex bytes need masking, so mask the whole thing - bit 4 */
1802 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1805 IXGBE_WRITE_REG(hw
, IXGBE_FDIRM
, fdirm
);
1807 fdircmd
|= IXGBE_FDIRCMD_CMD_ADD_FLOW
;
1808 fdircmd
|= IXGBE_FDIRCMD_FILTER_UPDATE
;
1809 fdircmd
|= IXGBE_FDIRCMD_LAST
;
1810 fdircmd
|= IXGBE_FDIRCMD_QUEUE_EN
;
1811 fdircmd
|= queue
<< IXGBE_FDIRCMD_RX_QUEUE_SHIFT
;
1813 IXGBE_WRITE_REG(hw
, IXGBE_FDIRHASH
, fdirhash
);
1814 IXGBE_WRITE_REG(hw
, IXGBE_FDIRCMD
, fdircmd
);
1819 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1820 * @hw: pointer to hardware structure
1821 * @reg: analog register to read
1824 * Performs read operation to Omer analog register specified.
1826 static s32
ixgbe_read_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8
*val
)
1830 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, IXGBE_CORECTL_WRITE_CMD
|
1832 IXGBE_WRITE_FLUSH(hw
);
1834 core_ctl
= IXGBE_READ_REG(hw
, IXGBE_CORECTL
);
1835 *val
= (u8
)core_ctl
;
1841 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1842 * @hw: pointer to hardware structure
1843 * @reg: atlas register to write
1844 * @val: value to write
1846 * Performs write operation to Omer analog register specified.
1848 static s32
ixgbe_write_analog_reg8_82599(struct ixgbe_hw
*hw
, u32 reg
, u8 val
)
1852 core_ctl
= (reg
<< 8) | val
;
1853 IXGBE_WRITE_REG(hw
, IXGBE_CORECTL
, core_ctl
);
1854 IXGBE_WRITE_FLUSH(hw
);
1861 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1862 * @hw: pointer to hardware structure
1864 * Starts the hardware using the generic start_hw function.
1865 * Then performs device-specific:
1866 * Clears the rate limiter registers.
1868 static s32
ixgbe_start_hw_82599(struct ixgbe_hw
*hw
)
1873 ret_val
= ixgbe_start_hw_generic(hw
);
1875 /* Clear the rate limiters */
1876 for (q_num
= 0; q_num
< hw
->mac
.max_tx_queues
; q_num
++) {
1877 IXGBE_WRITE_REG(hw
, IXGBE_RTTDQSEL
, q_num
);
1878 IXGBE_WRITE_REG(hw
, IXGBE_RTTBCNRC
, 0);
1880 IXGBE_WRITE_FLUSH(hw
);
1882 /* We need to run link autotry after the driver loads */
1883 hw
->mac
.autotry_restart
= true;
1886 ret_val
= ixgbe_verify_fw_version_82599(hw
);
1892 * ixgbe_identify_phy_82599 - Get physical layer module
1893 * @hw: pointer to hardware structure
1895 * Determines the physical layer module found on the current adapter.
1897 static s32
ixgbe_identify_phy_82599(struct ixgbe_hw
*hw
)
1899 s32 status
= IXGBE_ERR_PHY_ADDR_INVALID
;
1900 status
= ixgbe_identify_phy_generic(hw
);
1902 status
= ixgbe_identify_sfp_module_generic(hw
);
1907 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1908 * @hw: pointer to hardware structure
1910 * Determines physical layer capabilities of the current configuration.
1912 static u32
ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw
*hw
)
1914 u32 physical_layer
= IXGBE_PHYSICAL_LAYER_UNKNOWN
;
1915 u32 autoc
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
1916 u32 autoc2
= IXGBE_READ_REG(hw
, IXGBE_AUTOC2
);
1917 u32 pma_pmd_10g_serial
= autoc2
& IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK
;
1918 u32 pma_pmd_10g_parallel
= autoc
& IXGBE_AUTOC_10G_PMA_PMD_MASK
;
1919 u32 pma_pmd_1g
= autoc
& IXGBE_AUTOC_1G_PMA_PMD_MASK
;
1920 u16 ext_ability
= 0;
1921 u8 comp_codes_10g
= 0;
1922 u8 comp_codes_1g
= 0;
1924 hw
->phy
.ops
.identify(hw
);
1926 if (hw
->phy
.type
== ixgbe_phy_tn
||
1927 hw
->phy
.type
== ixgbe_phy_cu_unknown
) {
1928 hw
->phy
.ops
.read_reg(hw
, MDIO_PMA_EXTABLE
, MDIO_MMD_PMAPMD
,
1930 if (ext_ability
& MDIO_PMA_EXTABLE_10GBT
)
1931 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_T
;
1932 if (ext_ability
& MDIO_PMA_EXTABLE_1000BT
)
1933 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
1934 if (ext_ability
& MDIO_PMA_EXTABLE_100BTX
)
1935 physical_layer
|= IXGBE_PHYSICAL_LAYER_100BASE_TX
;
1939 switch (autoc
& IXGBE_AUTOC_LMS_MASK
) {
1940 case IXGBE_AUTOC_LMS_1G_AN
:
1941 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN
:
1942 if (pma_pmd_1g
== IXGBE_AUTOC_1G_KX_BX
) {
1943 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_KX
|
1944 IXGBE_PHYSICAL_LAYER_1000BASE_BX
;
1947 /* SFI mode so read SFP module */
1950 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN
:
1951 if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_CX4
)
1952 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_CX4
;
1953 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_KX4
)
1954 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1955 else if (pma_pmd_10g_parallel
== IXGBE_AUTOC_10G_XAUI
)
1956 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_XAUI
;
1959 case IXGBE_AUTOC_LMS_10G_SERIAL
:
1960 if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_KR
) {
1961 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
1963 } else if (pma_pmd_10g_serial
== IXGBE_AUTOC2_10G_SFI
)
1966 case IXGBE_AUTOC_LMS_KX4_KX_KR
:
1967 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN
:
1968 if (autoc
& IXGBE_AUTOC_KX_SUPP
)
1969 physical_layer
|= IXGBE_PHYSICAL_LAYER_1000BASE_KX
;
1970 if (autoc
& IXGBE_AUTOC_KX4_SUPP
)
1971 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KX4
;
1972 if (autoc
& IXGBE_AUTOC_KR_SUPP
)
1973 physical_layer
|= IXGBE_PHYSICAL_LAYER_10GBASE_KR
;
1982 /* SFP check must be done last since DA modules are sometimes used to
1983 * test KR mode - we need to id KR mode correctly before SFP module.
1984 * Call identify_sfp because the pluggable module may have changed */
1985 hw
->phy
.ops
.identify_sfp(hw
);
1986 if (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)
1989 switch (hw
->phy
.type
) {
1990 case ixgbe_phy_sfp_passive_tyco
:
1991 case ixgbe_phy_sfp_passive_unknown
:
1992 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU
;
1994 case ixgbe_phy_sfp_ftl_active
:
1995 case ixgbe_phy_sfp_active_unknown
:
1996 physical_layer
= IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA
;
1998 case ixgbe_phy_sfp_avago
:
1999 case ixgbe_phy_sfp_ftl
:
2000 case ixgbe_phy_sfp_intel
:
2001 case ixgbe_phy_sfp_unknown
:
2002 hw
->phy
.ops
.read_i2c_eeprom(hw
,
2003 IXGBE_SFF_1GBE_COMP_CODES
, &comp_codes_1g
);
2004 hw
->phy
.ops
.read_i2c_eeprom(hw
,
2005 IXGBE_SFF_10GBE_COMP_CODES
, &comp_codes_10g
);
2006 if (comp_codes_10g
& IXGBE_SFF_10GBASESR_CAPABLE
)
2007 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_SR
;
2008 else if (comp_codes_10g
& IXGBE_SFF_10GBASELR_CAPABLE
)
2009 physical_layer
= IXGBE_PHYSICAL_LAYER_10GBASE_LR
;
2010 else if (comp_codes_1g
& IXGBE_SFF_1GBASET_CAPABLE
)
2011 physical_layer
= IXGBE_PHYSICAL_LAYER_1000BASE_T
;
2018 return physical_layer
;
2022 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2023 * @hw: pointer to hardware structure
2024 * @regval: register value to write to RXCTRL
2026 * Enables the Rx DMA unit for 82599
2028 static s32
ixgbe_enable_rx_dma_82599(struct ixgbe_hw
*hw
, u32 regval
)
2030 #define IXGBE_MAX_SECRX_POLL 30
2035 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2036 * If traffic is incoming before we enable the Rx unit, it could hang
2037 * the Rx DMA unit. Therefore, make sure the security engine is
2038 * completely disabled prior to enabling the Rx unit.
2040 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
2041 secrxreg
|= IXGBE_SECRXCTRL_RX_DIS
;
2042 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
2043 for (i
= 0; i
< IXGBE_MAX_SECRX_POLL
; i
++) {
2044 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXSTAT
);
2045 if (secrxreg
& IXGBE_SECRXSTAT_SECRX_RDY
)
2051 /* For informational purposes only */
2052 if (i
>= IXGBE_MAX_SECRX_POLL
)
2053 hw_dbg(hw
, "Rx unit being enabled before security "
2054 "path fully disabled. Continuing with init.\n");
2056 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, regval
);
2057 secrxreg
= IXGBE_READ_REG(hw
, IXGBE_SECRXCTRL
);
2058 secrxreg
&= ~IXGBE_SECRXCTRL_RX_DIS
;
2059 IXGBE_WRITE_REG(hw
, IXGBE_SECRXCTRL
, secrxreg
);
2060 IXGBE_WRITE_FLUSH(hw
);
2066 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2067 * @hw: pointer to hardware structure
2068 * @device_caps: the EEPROM word with the extra device capabilities
2070 * This function will read the EEPROM location for the device capabilities,
2071 * and return the word through device_caps.
2073 static s32
ixgbe_get_device_caps_82599(struct ixgbe_hw
*hw
, u16
*device_caps
)
2075 hw
->eeprom
.ops
.read(hw
, IXGBE_DEVICE_CAPS
, device_caps
);
2081 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2082 * @hw: pointer to hardware structure
2084 * Verifies that installed the firmware version is 0.6 or higher
2085 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2087 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2088 * if the FW version is not supported.
2090 static s32
ixgbe_verify_fw_version_82599(struct ixgbe_hw
*hw
)
2092 s32 status
= IXGBE_ERR_EEPROM_VERSION
;
2093 u16 fw_offset
, fw_ptp_cfg_offset
;
2096 /* firmware check is only necessary for SFI devices */
2097 if (hw
->phy
.media_type
!= ixgbe_media_type_fiber
) {
2099 goto fw_version_out
;
2102 /* get the offset to the Firmware Module block */
2103 hw
->eeprom
.ops
.read(hw
, IXGBE_FW_PTR
, &fw_offset
);
2105 if ((fw_offset
== 0) || (fw_offset
== 0xFFFF))
2106 goto fw_version_out
;
2108 /* get the offset to the Pass Through Patch Configuration block */
2109 hw
->eeprom
.ops
.read(hw
, (fw_offset
+
2110 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR
),
2111 &fw_ptp_cfg_offset
);
2113 if ((fw_ptp_cfg_offset
== 0) || (fw_ptp_cfg_offset
== 0xFFFF))
2114 goto fw_version_out
;
2116 /* get the firmware version */
2117 hw
->eeprom
.ops
.read(hw
, (fw_ptp_cfg_offset
+
2118 IXGBE_FW_PATCH_VERSION_4
),
2121 if (fw_version
> 0x5)
2129 * ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from
2131 * @hw: pointer to hardware structure
2132 * @wwnn_prefix: the alternative WWNN prefix
2133 * @wwpn_prefix: the alternative WWPN prefix
2135 * This function will read the EEPROM from the alternative SAN MAC address
2136 * block to check the support for the alternative WWNN/WWPN prefix support.
2138 static s32
ixgbe_get_wwn_prefix_82599(struct ixgbe_hw
*hw
, u16
*wwnn_prefix
,
2142 u16 alt_san_mac_blk_offset
;
2144 /* clear output first */
2145 *wwnn_prefix
= 0xFFFF;
2146 *wwpn_prefix
= 0xFFFF;
2148 /* check if alternative SAN MAC is supported */
2149 hw
->eeprom
.ops
.read(hw
, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR
,
2150 &alt_san_mac_blk_offset
);
2152 if ((alt_san_mac_blk_offset
== 0) ||
2153 (alt_san_mac_blk_offset
== 0xFFFF))
2154 goto wwn_prefix_out
;
2156 /* check capability in alternative san mac address block */
2157 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET
;
2158 hw
->eeprom
.ops
.read(hw
, offset
, &caps
);
2159 if (!(caps
& IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN
))
2160 goto wwn_prefix_out
;
2162 /* get the corresponding prefix for WWNN/WWPN */
2163 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET
;
2164 hw
->eeprom
.ops
.read(hw
, offset
, wwnn_prefix
);
2166 offset
= alt_san_mac_blk_offset
+ IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET
;
2167 hw
->eeprom
.ops
.read(hw
, offset
, wwpn_prefix
);
2173 static struct ixgbe_mac_operations mac_ops_82599
= {
2174 .init_hw
= &ixgbe_init_hw_generic
,
2175 .reset_hw
= &ixgbe_reset_hw_82599
,
2176 .start_hw
= &ixgbe_start_hw_82599
,
2177 .clear_hw_cntrs
= &ixgbe_clear_hw_cntrs_generic
,
2178 .get_media_type
= &ixgbe_get_media_type_82599
,
2179 .get_supported_physical_layer
= &ixgbe_get_supported_physical_layer_82599
,
2180 .enable_rx_dma
= &ixgbe_enable_rx_dma_82599
,
2181 .get_mac_addr
= &ixgbe_get_mac_addr_generic
,
2182 .get_san_mac_addr
= &ixgbe_get_san_mac_addr_generic
,
2183 .get_device_caps
= &ixgbe_get_device_caps_82599
,
2184 .get_wwn_prefix
= &ixgbe_get_wwn_prefix_82599
,
2185 .stop_adapter
= &ixgbe_stop_adapter_generic
,
2186 .get_bus_info
= &ixgbe_get_bus_info_generic
,
2187 .set_lan_id
= &ixgbe_set_lan_id_multi_port_pcie
,
2188 .read_analog_reg8
= &ixgbe_read_analog_reg8_82599
,
2189 .write_analog_reg8
= &ixgbe_write_analog_reg8_82599
,
2190 .setup_link
= &ixgbe_setup_mac_link_82599
,
2191 .check_link
= &ixgbe_check_mac_link_generic
,
2192 .get_link_capabilities
= &ixgbe_get_link_capabilities_82599
,
2193 .led_on
= &ixgbe_led_on_generic
,
2194 .led_off
= &ixgbe_led_off_generic
,
2195 .blink_led_start
= &ixgbe_blink_led_start_generic
,
2196 .blink_led_stop
= &ixgbe_blink_led_stop_generic
,
2197 .set_rar
= &ixgbe_set_rar_generic
,
2198 .clear_rar
= &ixgbe_clear_rar_generic
,
2199 .set_vmdq
= &ixgbe_set_vmdq_generic
,
2200 .clear_vmdq
= &ixgbe_clear_vmdq_generic
,
2201 .init_rx_addrs
= &ixgbe_init_rx_addrs_generic
,
2202 .update_uc_addr_list
= &ixgbe_update_uc_addr_list_generic
,
2203 .update_mc_addr_list
= &ixgbe_update_mc_addr_list_generic
,
2204 .enable_mc
= &ixgbe_enable_mc_generic
,
2205 .disable_mc
= &ixgbe_disable_mc_generic
,
2206 .clear_vfta
= &ixgbe_clear_vfta_generic
,
2207 .set_vfta
= &ixgbe_set_vfta_generic
,
2208 .fc_enable
= &ixgbe_fc_enable_generic
,
2209 .init_uta_tables
= &ixgbe_init_uta_tables_generic
,
2210 .setup_sfp
= &ixgbe_setup_sfp_modules_82599
,
2213 static struct ixgbe_eeprom_operations eeprom_ops_82599
= {
2214 .init_params
= &ixgbe_init_eeprom_params_generic
,
2215 .read
= &ixgbe_read_eerd_generic
,
2216 .write
= &ixgbe_write_eeprom_generic
,
2217 .validate_checksum
= &ixgbe_validate_eeprom_checksum_generic
,
2218 .update_checksum
= &ixgbe_update_eeprom_checksum_generic
,
2221 static struct ixgbe_phy_operations phy_ops_82599
= {
2222 .identify
= &ixgbe_identify_phy_82599
,
2223 .identify_sfp
= &ixgbe_identify_sfp_module_generic
,
2224 .init
= &ixgbe_init_phy_ops_82599
,
2225 .reset
= &ixgbe_reset_phy_generic
,
2226 .read_reg
= &ixgbe_read_phy_reg_generic
,
2227 .write_reg
= &ixgbe_write_phy_reg_generic
,
2228 .setup_link
= &ixgbe_setup_phy_link_generic
,
2229 .setup_link_speed
= &ixgbe_setup_phy_link_speed_generic
,
2230 .read_i2c_byte
= &ixgbe_read_i2c_byte_generic
,
2231 .write_i2c_byte
= &ixgbe_write_i2c_byte_generic
,
2232 .read_i2c_eeprom
= &ixgbe_read_i2c_eeprom_generic
,
2233 .write_i2c_eeprom
= &ixgbe_write_i2c_eeprom_generic
,
2234 .check_overtemp
= &ixgbe_tn_check_overtemp
,
2237 struct ixgbe_info ixgbe_82599_info
= {
2238 .mac
= ixgbe_mac_82599EB
,
2239 .get_invariants
= &ixgbe_get_invariants_82599
,
2240 .mac_ops
= &mac_ops_82599
,
2241 .eeprom_ops
= &eeprom_ops_82599
,
2242 .phy_ops
= &phy_ops_82599
,
2243 .mbx_ops
= &mbx_ops_82599
,