1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31 #include <linux/netdevice.h>
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
37 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
);
38 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
);
39 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
);
40 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
);
41 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
);
42 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
44 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
);
45 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
46 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
);
47 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
);
48 static u16
ixgbe_calc_eeprom_checksum(struct ixgbe_hw
*hw
);
50 static void ixgbe_enable_rar(struct ixgbe_hw
*hw
, u32 index
);
51 static void ixgbe_disable_rar(struct ixgbe_hw
*hw
, u32 index
);
52 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
);
53 static void ixgbe_add_uc_addr(struct ixgbe_hw
*hw
, u8
*addr
, u32 vmdq
);
54 static s32
ixgbe_setup_fc(struct ixgbe_hw
*hw
, s32 packetbuf_num
);
55 static s32
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw
*hw
, u32 ee_reg
);
58 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
59 * @hw: pointer to hardware structure
61 * Starts the hardware by filling the bus info structure and media type, clears
62 * all on chip counters, initializes receive address registers, multicast
63 * table, VLAN filter table, calls routine to set up link and flow control
64 * settings, and leaves transmit and receive units disabled and uninitialized
66 s32
ixgbe_start_hw_generic(struct ixgbe_hw
*hw
)
70 /* Set the media type */
71 hw
->phy
.media_type
= hw
->mac
.ops
.get_media_type(hw
);
73 /* Identify the PHY */
74 hw
->phy
.ops
.identify(hw
);
76 /* Clear the VLAN filter table */
77 hw
->mac
.ops
.clear_vfta(hw
);
79 /* Clear statistics registers */
80 hw
->mac
.ops
.clear_hw_cntrs(hw
);
82 /* Set No Snoop Disable */
83 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
84 ctrl_ext
|= IXGBE_CTRL_EXT_NS_DIS
;
85 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
86 IXGBE_WRITE_FLUSH(hw
);
88 /* Setup flow control */
89 ixgbe_setup_fc(hw
, 0);
91 /* Clear adapter stopped flag */
92 hw
->adapter_stopped
= false;
98 * ixgbe_init_hw_generic - Generic hardware initialization
99 * @hw: pointer to hardware structure
101 * Initialize the hardware by resetting the hardware, filling the bus info
102 * structure and media type, clears all on chip counters, initializes receive
103 * address registers, multicast table, VLAN filter table, calls routine to set
104 * up link and flow control settings, and leaves transmit and receive units
105 * disabled and uninitialized
107 s32
ixgbe_init_hw_generic(struct ixgbe_hw
*hw
)
111 /* Reset the hardware */
112 status
= hw
->mac
.ops
.reset_hw(hw
);
116 status
= hw
->mac
.ops
.start_hw(hw
);
123 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
124 * @hw: pointer to hardware structure
126 * Clears all hardware statistics counters by reading them from the hardware
127 * Statistics counters are clear on read.
129 s32
ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw
*hw
)
133 IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
134 IXGBE_READ_REG(hw
, IXGBE_ILLERRC
);
135 IXGBE_READ_REG(hw
, IXGBE_ERRBC
);
136 IXGBE_READ_REG(hw
, IXGBE_MSPDC
);
137 for (i
= 0; i
< 8; i
++)
138 IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
140 IXGBE_READ_REG(hw
, IXGBE_MLFC
);
141 IXGBE_READ_REG(hw
, IXGBE_MRFC
);
142 IXGBE_READ_REG(hw
, IXGBE_RLEC
);
143 IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
144 IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
145 IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
146 IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
148 for (i
= 0; i
< 8; i
++) {
149 IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
150 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
151 IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
152 IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
155 IXGBE_READ_REG(hw
, IXGBE_PRC64
);
156 IXGBE_READ_REG(hw
, IXGBE_PRC127
);
157 IXGBE_READ_REG(hw
, IXGBE_PRC255
);
158 IXGBE_READ_REG(hw
, IXGBE_PRC511
);
159 IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
160 IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
161 IXGBE_READ_REG(hw
, IXGBE_GPRC
);
162 IXGBE_READ_REG(hw
, IXGBE_BPRC
);
163 IXGBE_READ_REG(hw
, IXGBE_MPRC
);
164 IXGBE_READ_REG(hw
, IXGBE_GPTC
);
165 IXGBE_READ_REG(hw
, IXGBE_GORCL
);
166 IXGBE_READ_REG(hw
, IXGBE_GORCH
);
167 IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
168 IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
169 for (i
= 0; i
< 8; i
++)
170 IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
171 IXGBE_READ_REG(hw
, IXGBE_RUC
);
172 IXGBE_READ_REG(hw
, IXGBE_RFC
);
173 IXGBE_READ_REG(hw
, IXGBE_ROC
);
174 IXGBE_READ_REG(hw
, IXGBE_RJC
);
175 IXGBE_READ_REG(hw
, IXGBE_MNGPRC
);
176 IXGBE_READ_REG(hw
, IXGBE_MNGPDC
);
177 IXGBE_READ_REG(hw
, IXGBE_MNGPTC
);
178 IXGBE_READ_REG(hw
, IXGBE_TORL
);
179 IXGBE_READ_REG(hw
, IXGBE_TORH
);
180 IXGBE_READ_REG(hw
, IXGBE_TPR
);
181 IXGBE_READ_REG(hw
, IXGBE_TPT
);
182 IXGBE_READ_REG(hw
, IXGBE_PTC64
);
183 IXGBE_READ_REG(hw
, IXGBE_PTC127
);
184 IXGBE_READ_REG(hw
, IXGBE_PTC255
);
185 IXGBE_READ_REG(hw
, IXGBE_PTC511
);
186 IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
187 IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
188 IXGBE_READ_REG(hw
, IXGBE_MPTC
);
189 IXGBE_READ_REG(hw
, IXGBE_BPTC
);
190 for (i
= 0; i
< 16; i
++) {
191 IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
192 IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
193 IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
194 IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
201 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
202 * @hw: pointer to hardware structure
203 * @pba_num: stores the part number from the EEPROM
205 * Reads the part number from the EEPROM.
207 s32
ixgbe_read_pba_num_generic(struct ixgbe_hw
*hw
, u32
*pba_num
)
212 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM0_PTR
, &data
);
214 hw_dbg(hw
, "NVM Read Error\n");
217 *pba_num
= (u32
)(data
<< 16);
219 ret_val
= hw
->eeprom
.ops
.read(hw
, IXGBE_PBANUM1_PTR
, &data
);
221 hw_dbg(hw
, "NVM Read Error\n");
230 * ixgbe_get_mac_addr_generic - Generic get MAC address
231 * @hw: pointer to hardware structure
232 * @mac_addr: Adapter MAC address
234 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
235 * A reset of the adapter must be performed prior to calling this function
236 * in order for the MAC address to have been loaded from the EEPROM into RAR0
238 s32
ixgbe_get_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*mac_addr
)
244 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(0));
245 rar_low
= IXGBE_READ_REG(hw
, IXGBE_RAL(0));
247 for (i
= 0; i
< 4; i
++)
248 mac_addr
[i
] = (u8
)(rar_low
>> (i
*8));
250 for (i
= 0; i
< 2; i
++)
251 mac_addr
[i
+4] = (u8
)(rar_high
>> (i
*8));
257 * ixgbe_get_bus_info_generic - Generic set PCI bus info
258 * @hw: pointer to hardware structure
260 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
262 s32
ixgbe_get_bus_info_generic(struct ixgbe_hw
*hw
)
264 struct ixgbe_adapter
*adapter
= hw
->back
;
265 struct ixgbe_mac_info
*mac
= &hw
->mac
;
268 hw
->bus
.type
= ixgbe_bus_type_pci_express
;
270 /* Get the negotiated link width and speed from PCI config space */
271 pci_read_config_word(adapter
->pdev
, IXGBE_PCI_LINK_STATUS
,
274 switch (link_status
& IXGBE_PCI_LINK_WIDTH
) {
275 case IXGBE_PCI_LINK_WIDTH_1
:
276 hw
->bus
.width
= ixgbe_bus_width_pcie_x1
;
278 case IXGBE_PCI_LINK_WIDTH_2
:
279 hw
->bus
.width
= ixgbe_bus_width_pcie_x2
;
281 case IXGBE_PCI_LINK_WIDTH_4
:
282 hw
->bus
.width
= ixgbe_bus_width_pcie_x4
;
284 case IXGBE_PCI_LINK_WIDTH_8
:
285 hw
->bus
.width
= ixgbe_bus_width_pcie_x8
;
288 hw
->bus
.width
= ixgbe_bus_width_unknown
;
292 switch (link_status
& IXGBE_PCI_LINK_SPEED
) {
293 case IXGBE_PCI_LINK_SPEED_2500
:
294 hw
->bus
.speed
= ixgbe_bus_speed_2500
;
296 case IXGBE_PCI_LINK_SPEED_5000
:
297 hw
->bus
.speed
= ixgbe_bus_speed_5000
;
300 hw
->bus
.speed
= ixgbe_bus_speed_unknown
;
304 mac
->ops
.set_lan_id(hw
);
310 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
311 * @hw: pointer to the HW structure
313 * Determines the LAN function id by reading memory-mapped registers
314 * and swaps the port value if requested.
316 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw
*hw
)
318 struct ixgbe_bus_info
*bus
= &hw
->bus
;
321 reg
= IXGBE_READ_REG(hw
, IXGBE_STATUS
);
322 bus
->func
= (reg
& IXGBE_STATUS_LAN_ID
) >> IXGBE_STATUS_LAN_ID_SHIFT
;
323 bus
->lan_id
= bus
->func
;
325 /* check for a port swap */
326 reg
= IXGBE_READ_REG(hw
, IXGBE_FACTPS
);
327 if (reg
& IXGBE_FACTPS_LFS
)
332 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
333 * @hw: pointer to hardware structure
335 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
336 * disables transmit and receive units. The adapter_stopped flag is used by
337 * the shared code and drivers to determine if the adapter is in a stopped
338 * state and should not touch the hardware.
340 s32
ixgbe_stop_adapter_generic(struct ixgbe_hw
*hw
)
342 u32 number_of_queues
;
347 * Set the adapter_stopped flag so other driver functions stop touching
350 hw
->adapter_stopped
= true;
352 /* Disable the receive unit */
353 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
354 reg_val
&= ~(IXGBE_RXCTRL_RXEN
);
355 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, reg_val
);
356 IXGBE_WRITE_FLUSH(hw
);
359 /* Clear interrupt mask to stop from interrupts being generated */
360 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
362 /* Clear any pending interrupts */
363 IXGBE_READ_REG(hw
, IXGBE_EICR
);
365 /* Disable the transmit unit. Each queue must be disabled. */
366 number_of_queues
= hw
->mac
.max_tx_queues
;
367 for (i
= 0; i
< number_of_queues
; i
++) {
368 reg_val
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
369 if (reg_val
& IXGBE_TXDCTL_ENABLE
) {
370 reg_val
&= ~IXGBE_TXDCTL_ENABLE
;
371 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(i
), reg_val
);
376 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
377 * access and verify no pending requests
379 if (ixgbe_disable_pcie_master(hw
) != 0)
380 hw_dbg(hw
, "PCI-E Master disable polling has failed.\n");
386 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
387 * @hw: pointer to hardware structure
388 * @index: led number to turn on
390 s32
ixgbe_led_on_generic(struct ixgbe_hw
*hw
, u32 index
)
392 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
394 /* To turn on the LED, set mode to ON. */
395 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
396 led_reg
|= IXGBE_LED_ON
<< IXGBE_LED_MODE_SHIFT(index
);
397 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
398 IXGBE_WRITE_FLUSH(hw
);
404 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
405 * @hw: pointer to hardware structure
406 * @index: led number to turn off
408 s32
ixgbe_led_off_generic(struct ixgbe_hw
*hw
, u32 index
)
410 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
412 /* To turn off the LED, set mode to OFF. */
413 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
414 led_reg
|= IXGBE_LED_OFF
<< IXGBE_LED_MODE_SHIFT(index
);
415 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
416 IXGBE_WRITE_FLUSH(hw
);
422 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
423 * @hw: pointer to hardware structure
425 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
426 * ixgbe_hw struct in order to set up EEPROM access.
428 s32
ixgbe_init_eeprom_params_generic(struct ixgbe_hw
*hw
)
430 struct ixgbe_eeprom_info
*eeprom
= &hw
->eeprom
;
434 if (eeprom
->type
== ixgbe_eeprom_uninitialized
) {
435 eeprom
->type
= ixgbe_eeprom_none
;
436 /* Set default semaphore delay to 10ms which is a well
438 eeprom
->semaphore_delay
= 10;
441 * Check for EEPROM present first.
442 * If not present leave as none
444 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
445 if (eec
& IXGBE_EEC_PRES
) {
446 eeprom
->type
= ixgbe_eeprom_spi
;
449 * SPI EEPROM is assumed here. This code would need to
450 * change if a future EEPROM is not SPI.
452 eeprom_size
= (u16
)((eec
& IXGBE_EEC_SIZE
) >>
453 IXGBE_EEC_SIZE_SHIFT
);
454 eeprom
->word_size
= 1 << (eeprom_size
+
455 IXGBE_EEPROM_WORD_SIZE_SHIFT
);
458 if (eec
& IXGBE_EEC_ADDR_SIZE
)
459 eeprom
->address_bits
= 16;
461 eeprom
->address_bits
= 8;
462 hw_dbg(hw
, "Eeprom params: type = %d, size = %d, address bits: "
463 "%d\n", eeprom
->type
, eeprom
->word_size
,
464 eeprom
->address_bits
);
471 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
472 * @hw: pointer to hardware structure
473 * @offset: offset within the EEPROM to be written to
474 * @data: 16 bit word to be written to the EEPROM
476 * If ixgbe_eeprom_update_checksum is not called after this function, the
477 * EEPROM will most likely contain an invalid checksum.
479 s32
ixgbe_write_eeprom_generic(struct ixgbe_hw
*hw
, u16 offset
, u16 data
)
482 u8 write_opcode
= IXGBE_EEPROM_WRITE_OPCODE_SPI
;
484 hw
->eeprom
.ops
.init_params(hw
);
486 if (offset
>= hw
->eeprom
.word_size
) {
487 status
= IXGBE_ERR_EEPROM
;
491 /* Prepare the EEPROM for writing */
492 status
= ixgbe_acquire_eeprom(hw
);
495 if (ixgbe_ready_eeprom(hw
) != 0) {
496 ixgbe_release_eeprom(hw
);
497 status
= IXGBE_ERR_EEPROM
;
502 ixgbe_standby_eeprom(hw
);
504 /* Send the WRITE ENABLE command (8 bit opcode ) */
505 ixgbe_shift_out_eeprom_bits(hw
, IXGBE_EEPROM_WREN_OPCODE_SPI
,
506 IXGBE_EEPROM_OPCODE_BITS
);
508 ixgbe_standby_eeprom(hw
);
511 * Some SPI eeproms use the 8th address bit embedded in the
514 if ((hw
->eeprom
.address_bits
== 8) && (offset
>= 128))
515 write_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
517 /* Send the Write command (8-bit opcode + addr) */
518 ixgbe_shift_out_eeprom_bits(hw
, write_opcode
,
519 IXGBE_EEPROM_OPCODE_BITS
);
520 ixgbe_shift_out_eeprom_bits(hw
, (u16
)(offset
*2),
521 hw
->eeprom
.address_bits
);
524 data
= (data
>> 8) | (data
<< 8);
525 ixgbe_shift_out_eeprom_bits(hw
, data
, 16);
526 ixgbe_standby_eeprom(hw
);
528 msleep(hw
->eeprom
.semaphore_delay
);
529 /* Done with writing - release the EEPROM */
530 ixgbe_release_eeprom(hw
);
538 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
539 * @hw: pointer to hardware structure
540 * @offset: offset within the EEPROM to be read
541 * @data: read 16 bit value from EEPROM
543 * Reads 16 bit value from EEPROM through bit-bang method
545 s32
ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw
*hw
, u16 offset
,
550 u8 read_opcode
= IXGBE_EEPROM_READ_OPCODE_SPI
;
552 hw
->eeprom
.ops
.init_params(hw
);
554 if (offset
>= hw
->eeprom
.word_size
) {
555 status
= IXGBE_ERR_EEPROM
;
559 /* Prepare the EEPROM for reading */
560 status
= ixgbe_acquire_eeprom(hw
);
563 if (ixgbe_ready_eeprom(hw
) != 0) {
564 ixgbe_release_eeprom(hw
);
565 status
= IXGBE_ERR_EEPROM
;
570 ixgbe_standby_eeprom(hw
);
573 * Some SPI eeproms use the 8th address bit embedded in the
576 if ((hw
->eeprom
.address_bits
== 8) && (offset
>= 128))
577 read_opcode
|= IXGBE_EEPROM_A8_OPCODE_SPI
;
579 /* Send the READ command (opcode + addr) */
580 ixgbe_shift_out_eeprom_bits(hw
, read_opcode
,
581 IXGBE_EEPROM_OPCODE_BITS
);
582 ixgbe_shift_out_eeprom_bits(hw
, (u16
)(offset
*2),
583 hw
->eeprom
.address_bits
);
586 word_in
= ixgbe_shift_in_eeprom_bits(hw
, 16);
587 *data
= (word_in
>> 8) | (word_in
<< 8);
589 /* End this read operation */
590 ixgbe_release_eeprom(hw
);
598 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
599 * @hw: pointer to hardware structure
600 * @offset: offset of word in the EEPROM to read
601 * @data: word read from the EEPROM
603 * Reads a 16 bit word from the EEPROM using the EERD register.
605 s32
ixgbe_read_eerd_generic(struct ixgbe_hw
*hw
, u16 offset
, u16
*data
)
610 hw
->eeprom
.ops
.init_params(hw
);
612 if (offset
>= hw
->eeprom
.word_size
) {
613 status
= IXGBE_ERR_EEPROM
;
617 eerd
= (offset
<< IXGBE_EEPROM_RW_ADDR_SHIFT
) +
618 IXGBE_EEPROM_RW_REG_START
;
620 IXGBE_WRITE_REG(hw
, IXGBE_EERD
, eerd
);
621 status
= ixgbe_poll_eerd_eewr_done(hw
, IXGBE_NVM_POLL_READ
);
624 *data
= (IXGBE_READ_REG(hw
, IXGBE_EERD
) >>
625 IXGBE_EEPROM_RW_REG_DATA
);
627 hw_dbg(hw
, "Eeprom read timed out\n");
634 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
635 * @hw: pointer to hardware structure
636 * @ee_reg: EEPROM flag for polling
638 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
639 * read or write is done respectively.
641 static s32
ixgbe_poll_eerd_eewr_done(struct ixgbe_hw
*hw
, u32 ee_reg
)
645 s32 status
= IXGBE_ERR_EEPROM
;
647 for (i
= 0; i
< IXGBE_EERD_EEWR_ATTEMPTS
; i
++) {
648 if (ee_reg
== IXGBE_NVM_POLL_READ
)
649 reg
= IXGBE_READ_REG(hw
, IXGBE_EERD
);
651 reg
= IXGBE_READ_REG(hw
, IXGBE_EEWR
);
653 if (reg
& IXGBE_EEPROM_RW_REG_DONE
) {
663 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
664 * @hw: pointer to hardware structure
666 * Prepares EEPROM for access using bit-bang method. This function should
667 * be called before issuing a command to the EEPROM.
669 static s32
ixgbe_acquire_eeprom(struct ixgbe_hw
*hw
)
675 if (ixgbe_acquire_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
) != 0)
676 status
= IXGBE_ERR_SWFW_SYNC
;
679 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
681 /* Request EEPROM Access */
682 eec
|= IXGBE_EEC_REQ
;
683 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
685 for (i
= 0; i
< IXGBE_EEPROM_GRANT_ATTEMPTS
; i
++) {
686 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
687 if (eec
& IXGBE_EEC_GNT
)
692 /* Release if grant not acquired */
693 if (!(eec
& IXGBE_EEC_GNT
)) {
694 eec
&= ~IXGBE_EEC_REQ
;
695 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
696 hw_dbg(hw
, "Could not acquire EEPROM grant\n");
698 ixgbe_release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
699 status
= IXGBE_ERR_EEPROM
;
703 /* Setup EEPROM for Read/Write */
705 /* Clear CS and SK */
706 eec
&= ~(IXGBE_EEC_CS
| IXGBE_EEC_SK
);
707 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
708 IXGBE_WRITE_FLUSH(hw
);
715 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
716 * @hw: pointer to hardware structure
718 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
720 static s32
ixgbe_get_eeprom_semaphore(struct ixgbe_hw
*hw
)
722 s32 status
= IXGBE_ERR_EEPROM
;
727 /* Set timeout value based on size of EEPROM */
728 timeout
= hw
->eeprom
.word_size
+ 1;
730 /* Get SMBI software semaphore between device drivers first */
731 for (i
= 0; i
< timeout
; i
++) {
733 * If the SMBI bit is 0 when we read it, then the bit will be
734 * set and we have the semaphore
736 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
737 if (!(swsm
& IXGBE_SWSM_SMBI
)) {
744 /* Now get the semaphore between SW/FW through the SWESMBI bit */
746 for (i
= 0; i
< timeout
; i
++) {
747 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
749 /* Set the SW EEPROM semaphore bit to request access */
750 swsm
|= IXGBE_SWSM_SWESMBI
;
751 IXGBE_WRITE_REG(hw
, IXGBE_SWSM
, swsm
);
754 * If we set the bit successfully then we got the
757 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
758 if (swsm
& IXGBE_SWSM_SWESMBI
)
765 * Release semaphores and return error if SW EEPROM semaphore
766 * was not granted because we don't have access to the EEPROM
769 hw_dbg(hw
, "Driver can't access the Eeprom - Semaphore "
771 ixgbe_release_eeprom_semaphore(hw
);
772 status
= IXGBE_ERR_EEPROM
;
780 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
781 * @hw: pointer to hardware structure
783 * This function clears hardware semaphore bits.
785 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw
*hw
)
789 swsm
= IXGBE_READ_REG(hw
, IXGBE_SWSM
);
791 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
792 swsm
&= ~(IXGBE_SWSM_SWESMBI
| IXGBE_SWSM_SMBI
);
793 IXGBE_WRITE_REG(hw
, IXGBE_SWSM
, swsm
);
794 IXGBE_WRITE_FLUSH(hw
);
798 * ixgbe_ready_eeprom - Polls for EEPROM ready
799 * @hw: pointer to hardware structure
801 static s32
ixgbe_ready_eeprom(struct ixgbe_hw
*hw
)
808 * Read "Status Register" repeatedly until the LSB is cleared. The
809 * EEPROM will signal that the command has been completed by clearing
810 * bit 0 of the internal status register. If it's not cleared within
811 * 5 milliseconds, then error out.
813 for (i
= 0; i
< IXGBE_EEPROM_MAX_RETRY_SPI
; i
+= 5) {
814 ixgbe_shift_out_eeprom_bits(hw
, IXGBE_EEPROM_RDSR_OPCODE_SPI
,
815 IXGBE_EEPROM_OPCODE_BITS
);
816 spi_stat_reg
= (u8
)ixgbe_shift_in_eeprom_bits(hw
, 8);
817 if (!(spi_stat_reg
& IXGBE_EEPROM_STATUS_RDY_SPI
))
821 ixgbe_standby_eeprom(hw
);
825 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
826 * devices (and only 0-5mSec on 5V devices)
828 if (i
>= IXGBE_EEPROM_MAX_RETRY_SPI
) {
829 hw_dbg(hw
, "SPI EEPROM Status error\n");
830 status
= IXGBE_ERR_EEPROM
;
837 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
838 * @hw: pointer to hardware structure
840 static void ixgbe_standby_eeprom(struct ixgbe_hw
*hw
)
844 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
846 /* Toggle CS to flush commands */
848 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
849 IXGBE_WRITE_FLUSH(hw
);
851 eec
&= ~IXGBE_EEC_CS
;
852 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
853 IXGBE_WRITE_FLUSH(hw
);
858 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
859 * @hw: pointer to hardware structure
860 * @data: data to send to the EEPROM
861 * @count: number of bits to shift out
863 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw
*hw
, u16 data
,
870 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
873 * Mask is used to shift "count" bits of "data" out to the EEPROM
874 * one bit at a time. Determine the starting bit based on count
876 mask
= 0x01 << (count
- 1);
878 for (i
= 0; i
< count
; i
++) {
880 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
881 * "1", and then raising and then lowering the clock (the SK
882 * bit controls the clock input to the EEPROM). A "0" is
883 * shifted out to the EEPROM by setting "DI" to "0" and then
884 * raising and then lowering the clock.
889 eec
&= ~IXGBE_EEC_DI
;
891 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
892 IXGBE_WRITE_FLUSH(hw
);
896 ixgbe_raise_eeprom_clk(hw
, &eec
);
897 ixgbe_lower_eeprom_clk(hw
, &eec
);
900 * Shift mask to signify next bit of data to shift in to the
906 /* We leave the "DI" bit set to "0" when we leave this routine. */
907 eec
&= ~IXGBE_EEC_DI
;
908 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
909 IXGBE_WRITE_FLUSH(hw
);
913 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
914 * @hw: pointer to hardware structure
916 static u16
ixgbe_shift_in_eeprom_bits(struct ixgbe_hw
*hw
, u16 count
)
923 * In order to read a register from the EEPROM, we need to shift
924 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
925 * the clock input to the EEPROM (setting the SK bit), and then reading
926 * the value of the "DO" bit. During this "shifting in" process the
927 * "DI" bit should always be clear.
929 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
931 eec
&= ~(IXGBE_EEC_DO
| IXGBE_EEC_DI
);
933 for (i
= 0; i
< count
; i
++) {
935 ixgbe_raise_eeprom_clk(hw
, &eec
);
937 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
939 eec
&= ~(IXGBE_EEC_DI
);
940 if (eec
& IXGBE_EEC_DO
)
943 ixgbe_lower_eeprom_clk(hw
, &eec
);
950 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
951 * @hw: pointer to hardware structure
952 * @eec: EEC register's current value
954 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
957 * Raise the clock input to the EEPROM
958 * (setting the SK bit), then delay
960 *eec
= *eec
| IXGBE_EEC_SK
;
961 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, *eec
);
962 IXGBE_WRITE_FLUSH(hw
);
967 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
968 * @hw: pointer to hardware structure
969 * @eecd: EECD's current value
971 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw
*hw
, u32
*eec
)
974 * Lower the clock input to the EEPROM (clearing the SK bit), then
977 *eec
= *eec
& ~IXGBE_EEC_SK
;
978 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, *eec
);
979 IXGBE_WRITE_FLUSH(hw
);
984 * ixgbe_release_eeprom - Release EEPROM, release semaphores
985 * @hw: pointer to hardware structure
987 static void ixgbe_release_eeprom(struct ixgbe_hw
*hw
)
991 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
993 eec
|= IXGBE_EEC_CS
; /* Pull CS high */
994 eec
&= ~IXGBE_EEC_SK
; /* Lower SCK */
996 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
997 IXGBE_WRITE_FLUSH(hw
);
1001 /* Stop requesting EEPROM access */
1002 eec
&= ~IXGBE_EEC_REQ
;
1003 IXGBE_WRITE_REG(hw
, IXGBE_EEC
, eec
);
1005 ixgbe_release_swfw_sync(hw
, IXGBE_GSSR_EEP_SM
);
1009 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1010 * @hw: pointer to hardware structure
1012 static u16
ixgbe_calc_eeprom_checksum(struct ixgbe_hw
*hw
)
1021 /* Include 0x0-0x3F in the checksum */
1022 for (i
= 0; i
< IXGBE_EEPROM_CHECKSUM
; i
++) {
1023 if (hw
->eeprom
.ops
.read(hw
, i
, &word
) != 0) {
1024 hw_dbg(hw
, "EEPROM read failed\n");
1030 /* Include all data from pointers except for the fw pointer */
1031 for (i
= IXGBE_PCIE_ANALOG_PTR
; i
< IXGBE_FW_PTR
; i
++) {
1032 hw
->eeprom
.ops
.read(hw
, i
, &pointer
);
1034 /* Make sure the pointer seems valid */
1035 if (pointer
!= 0xFFFF && pointer
!= 0) {
1036 hw
->eeprom
.ops
.read(hw
, pointer
, &length
);
1038 if (length
!= 0xFFFF && length
!= 0) {
1039 for (j
= pointer
+1; j
<= pointer
+length
; j
++) {
1040 hw
->eeprom
.ops
.read(hw
, j
, &word
);
1047 checksum
= (u16
)IXGBE_EEPROM_SUM
- checksum
;
1053 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1054 * @hw: pointer to hardware structure
1055 * @checksum_val: calculated checksum
1057 * Performs checksum calculation and validates the EEPROM checksum. If the
1058 * caller does not need checksum_val, the value can be NULL.
1060 s32
ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw
*hw
,
1065 u16 read_checksum
= 0;
1068 * Read the first word from the EEPROM. If this times out or fails, do
1069 * not continue or we could be in for a very long wait while every
1072 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
1075 checksum
= ixgbe_calc_eeprom_checksum(hw
);
1077 hw
->eeprom
.ops
.read(hw
, IXGBE_EEPROM_CHECKSUM
, &read_checksum
);
1080 * Verify read checksum from EEPROM is the same as
1081 * calculated checksum
1083 if (read_checksum
!= checksum
)
1084 status
= IXGBE_ERR_EEPROM_CHECKSUM
;
1086 /* If the user cares, return the calculated checksum */
1088 *checksum_val
= checksum
;
1090 hw_dbg(hw
, "EEPROM read failed\n");
1097 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1098 * @hw: pointer to hardware structure
1100 s32
ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw
*hw
)
1106 * Read the first word from the EEPROM. If this times out or fails, do
1107 * not continue or we could be in for a very long wait while every
1110 status
= hw
->eeprom
.ops
.read(hw
, 0, &checksum
);
1113 checksum
= ixgbe_calc_eeprom_checksum(hw
);
1114 status
= hw
->eeprom
.ops
.write(hw
, IXGBE_EEPROM_CHECKSUM
,
1117 hw_dbg(hw
, "EEPROM read failed\n");
1124 * ixgbe_validate_mac_addr - Validate MAC address
1125 * @mac_addr: pointer to MAC address.
1127 * Tests a MAC address to ensure it is a valid Individual Address
1129 s32
ixgbe_validate_mac_addr(u8
*mac_addr
)
1133 /* Make sure it is not a multicast address */
1134 if (IXGBE_IS_MULTICAST(mac_addr
))
1135 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1136 /* Not a broadcast address */
1137 else if (IXGBE_IS_BROADCAST(mac_addr
))
1138 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1139 /* Reject the zero address */
1140 else if (mac_addr
[0] == 0 && mac_addr
[1] == 0 && mac_addr
[2] == 0 &&
1141 mac_addr
[3] == 0 && mac_addr
[4] == 0 && mac_addr
[5] == 0)
1142 status
= IXGBE_ERR_INVALID_MAC_ADDR
;
1148 * ixgbe_set_rar_generic - Set Rx address register
1149 * @hw: pointer to hardware structure
1150 * @index: Receive address register to write
1151 * @addr: Address to put into receive address register
1152 * @vmdq: VMDq "set" or "pool" index
1153 * @enable_addr: set flag that address is active
1155 * Puts an ethernet address into a receive address register.
1157 s32
ixgbe_set_rar_generic(struct ixgbe_hw
*hw
, u32 index
, u8
*addr
, u32 vmdq
,
1160 u32 rar_low
, rar_high
;
1161 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1163 /* setup VMDq pool selection before this RAR gets enabled */
1164 hw
->mac
.ops
.set_vmdq(hw
, index
, vmdq
);
1166 /* Make sure we are using a valid rar index range */
1167 if (index
< rar_entries
) {
1169 * HW expects these in little endian so we reverse the byte
1170 * order from network order (big endian) to little endian
1172 rar_low
= ((u32
)addr
[0] |
1173 ((u32
)addr
[1] << 8) |
1174 ((u32
)addr
[2] << 16) |
1175 ((u32
)addr
[3] << 24));
1177 * Some parts put the VMDq setting in the extra RAH bits,
1178 * so save everything except the lower 16 bits that hold part
1179 * of the address and the address valid bit.
1181 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1182 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1183 rar_high
|= ((u32
)addr
[4] | ((u32
)addr
[5] << 8));
1185 if (enable_addr
!= 0)
1186 rar_high
|= IXGBE_RAH_AV
;
1188 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), rar_low
);
1189 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1191 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1192 return IXGBE_ERR_RAR_INDEX
;
1199 * ixgbe_clear_rar_generic - Remove Rx address register
1200 * @hw: pointer to hardware structure
1201 * @index: Receive address register to write
1203 * Clears an ethernet address from a receive address register.
1205 s32
ixgbe_clear_rar_generic(struct ixgbe_hw
*hw
, u32 index
)
1208 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1210 /* Make sure we are using a valid rar index range */
1211 if (index
< rar_entries
) {
1213 * Some parts put the VMDq setting in the extra RAH bits,
1214 * so save everything except the lower 16 bits that hold part
1215 * of the address and the address valid bit.
1217 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1218 rar_high
&= ~(0x0000FFFF | IXGBE_RAH_AV
);
1220 IXGBE_WRITE_REG(hw
, IXGBE_RAL(index
), 0);
1221 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1223 hw_dbg(hw
, "RAR index %d is out of range.\n", index
);
1224 return IXGBE_ERR_RAR_INDEX
;
1227 /* clear VMDq pool/queue selection for this RAR */
1228 hw
->mac
.ops
.clear_vmdq(hw
, index
, IXGBE_CLEAR_VMDQ_ALL
);
1234 * ixgbe_enable_rar - Enable Rx address register
1235 * @hw: pointer to hardware structure
1236 * @index: index into the RAR table
1238 * Enables the select receive address register.
1240 static void ixgbe_enable_rar(struct ixgbe_hw
*hw
, u32 index
)
1244 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1245 rar_high
|= IXGBE_RAH_AV
;
1246 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1250 * ixgbe_disable_rar - Disable Rx address register
1251 * @hw: pointer to hardware structure
1252 * @index: index into the RAR table
1254 * Disables the select receive address register.
1256 static void ixgbe_disable_rar(struct ixgbe_hw
*hw
, u32 index
)
1260 rar_high
= IXGBE_READ_REG(hw
, IXGBE_RAH(index
));
1261 rar_high
&= (~IXGBE_RAH_AV
);
1262 IXGBE_WRITE_REG(hw
, IXGBE_RAH(index
), rar_high
);
1266 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1267 * @hw: pointer to hardware structure
1269 * Places the MAC address in receive address register 0 and clears the rest
1270 * of the receive address registers. Clears the multicast table. Assumes
1271 * the receiver is in reset when the routine is called.
1273 s32
ixgbe_init_rx_addrs_generic(struct ixgbe_hw
*hw
)
1276 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1279 * If the current mac address is valid, assume it is a software override
1280 * to the permanent address.
1281 * Otherwise, use the permanent address from the eeprom.
1283 if (ixgbe_validate_mac_addr(hw
->mac
.addr
) ==
1284 IXGBE_ERR_INVALID_MAC_ADDR
) {
1285 /* Get the MAC address from the RAR0 for later reference */
1286 hw
->mac
.ops
.get_mac_addr(hw
, hw
->mac
.addr
);
1288 hw_dbg(hw
, " Keeping Current RAR0 Addr =%pM\n", hw
->mac
.addr
);
1290 /* Setup the receive address. */
1291 hw_dbg(hw
, "Overriding MAC Address in RAR[0]\n");
1292 hw_dbg(hw
, " New MAC Addr =%pM\n", hw
->mac
.addr
);
1294 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, 0, IXGBE_RAH_AV
);
1296 hw
->addr_ctrl
.overflow_promisc
= 0;
1298 hw
->addr_ctrl
.rar_used_count
= 1;
1300 /* Zero out the other receive addresses. */
1301 hw_dbg(hw
, "Clearing RAR[1-%d]\n", rar_entries
- 1);
1302 for (i
= 1; i
< rar_entries
; i
++) {
1303 IXGBE_WRITE_REG(hw
, IXGBE_RAL(i
), 0);
1304 IXGBE_WRITE_REG(hw
, IXGBE_RAH(i
), 0);
1308 hw
->addr_ctrl
.mc_addr_in_rar_count
= 0;
1309 hw
->addr_ctrl
.mta_in_use
= 0;
1310 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
1312 hw_dbg(hw
, " Clearing MTA\n");
1313 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
1314 IXGBE_WRITE_REG(hw
, IXGBE_MTA(i
), 0);
1316 if (hw
->mac
.ops
.init_uta_tables
)
1317 hw
->mac
.ops
.init_uta_tables(hw
);
1323 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1324 * @hw: pointer to hardware structure
1325 * @addr: new address
1327 * Adds it to unused receive address register or goes into promiscuous mode.
1329 static void ixgbe_add_uc_addr(struct ixgbe_hw
*hw
, u8
*addr
, u32 vmdq
)
1331 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1334 hw_dbg(hw
, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1335 addr
[0], addr
[1], addr
[2], addr
[3], addr
[4], addr
[5]);
1338 * Place this address in the RAR if there is room,
1339 * else put the controller into promiscuous mode
1341 if (hw
->addr_ctrl
.rar_used_count
< rar_entries
) {
1342 rar
= hw
->addr_ctrl
.rar_used_count
-
1343 hw
->addr_ctrl
.mc_addr_in_rar_count
;
1344 hw
->mac
.ops
.set_rar(hw
, rar
, addr
, vmdq
, IXGBE_RAH_AV
);
1345 hw_dbg(hw
, "Added a secondary address to RAR[%d]\n", rar
);
1346 hw
->addr_ctrl
.rar_used_count
++;
1348 hw
->addr_ctrl
.overflow_promisc
++;
1351 hw_dbg(hw
, "ixgbe_add_uc_addr Complete\n");
1355 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
1356 * @hw: pointer to hardware structure
1357 * @netdev: pointer to net device structure
1359 * The given list replaces any existing list. Clears the secondary addrs from
1360 * receive address registers. Uses unused receive address registers for the
1361 * first secondary addresses, and falls back to promiscuous mode as needed.
1363 * Drivers using secondary unicast addresses must set user_set_promisc when
1364 * manually putting the device into promiscuous mode.
1366 s32
ixgbe_update_uc_addr_list_generic(struct ixgbe_hw
*hw
,
1367 struct net_device
*netdev
)
1370 u32 old_promisc_setting
= hw
->addr_ctrl
.overflow_promisc
;
1373 struct netdev_hw_addr
*ha
;
1376 * Clear accounting of old secondary address list,
1377 * don't count RAR[0]
1379 uc_addr_in_use
= hw
->addr_ctrl
.rar_used_count
- 1;
1380 hw
->addr_ctrl
.rar_used_count
-= uc_addr_in_use
;
1381 hw
->addr_ctrl
.overflow_promisc
= 0;
1383 /* Zero out the other receive addresses */
1384 hw_dbg(hw
, "Clearing RAR[1-%d]\n", uc_addr_in_use
+ 1);
1385 for (i
= 0; i
< uc_addr_in_use
; i
++) {
1386 IXGBE_WRITE_REG(hw
, IXGBE_RAL(1+i
), 0);
1387 IXGBE_WRITE_REG(hw
, IXGBE_RAH(1+i
), 0);
1390 /* Add the new addresses */
1391 netdev_for_each_uc_addr(ha
, netdev
) {
1392 hw_dbg(hw
, " Adding the secondary addresses:\n");
1393 ixgbe_add_uc_addr(hw
, ha
->addr
, 0);
1396 if (hw
->addr_ctrl
.overflow_promisc
) {
1397 /* enable promisc if not already in overflow or set by user */
1398 if (!old_promisc_setting
&& !hw
->addr_ctrl
.user_set_promisc
) {
1399 hw_dbg(hw
, " Entering address overflow promisc mode\n");
1400 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
1401 fctrl
|= IXGBE_FCTRL_UPE
;
1402 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
1403 hw
->addr_ctrl
.uc_set_promisc
= true;
1406 /* only disable if set by overflow, not by user */
1407 if ((old_promisc_setting
&& hw
->addr_ctrl
.uc_set_promisc
) &&
1408 !(hw
->addr_ctrl
.user_set_promisc
)) {
1409 hw_dbg(hw
, " Leaving address overflow promisc mode\n");
1410 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
1411 fctrl
&= ~IXGBE_FCTRL_UPE
;
1412 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
1413 hw
->addr_ctrl
.uc_set_promisc
= false;
1417 hw_dbg(hw
, "ixgbe_update_uc_addr_list_generic Complete\n");
1422 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1423 * @hw: pointer to hardware structure
1424 * @mc_addr: the multicast address
1426 * Extracts the 12 bits, from a multicast address, to determine which
1427 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1428 * incoming rx multicast addresses, to determine the bit-vector to check in
1429 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1430 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1431 * to mc_filter_type.
1433 static s32
ixgbe_mta_vector(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1437 switch (hw
->mac
.mc_filter_type
) {
1438 case 0: /* use bits [47:36] of the address */
1439 vector
= ((mc_addr
[4] >> 4) | (((u16
)mc_addr
[5]) << 4));
1441 case 1: /* use bits [46:35] of the address */
1442 vector
= ((mc_addr
[4] >> 3) | (((u16
)mc_addr
[5]) << 5));
1444 case 2: /* use bits [45:34] of the address */
1445 vector
= ((mc_addr
[4] >> 2) | (((u16
)mc_addr
[5]) << 6));
1447 case 3: /* use bits [43:32] of the address */
1448 vector
= ((mc_addr
[4]) | (((u16
)mc_addr
[5]) << 8));
1450 default: /* Invalid mc_filter_type */
1451 hw_dbg(hw
, "MC filter type param set incorrectly\n");
1455 /* vector can only be 12-bits or boundary will be exceeded */
1461 * ixgbe_set_mta - Set bit-vector in multicast table
1462 * @hw: pointer to hardware structure
1463 * @hash_value: Multicast address hash value
1465 * Sets the bit-vector in the multicast table.
1467 static void ixgbe_set_mta(struct ixgbe_hw
*hw
, u8
*mc_addr
)
1474 hw
->addr_ctrl
.mta_in_use
++;
1476 vector
= ixgbe_mta_vector(hw
, mc_addr
);
1477 hw_dbg(hw
, " bit-vector = 0x%03X\n", vector
);
1480 * The MTA is a register array of 128 32-bit registers. It is treated
1481 * like an array of 4096 bits. We want to set bit
1482 * BitArray[vector_value]. So we figure out what register the bit is
1483 * in, read it, OR in the new bit, then write back the new value. The
1484 * register is determined by the upper 7 bits of the vector value and
1485 * the bit within that register are determined by the lower 5 bits of
1488 vector_reg
= (vector
>> 5) & 0x7F;
1489 vector_bit
= vector
& 0x1F;
1490 mta_reg
= IXGBE_READ_REG(hw
, IXGBE_MTA(vector_reg
));
1491 mta_reg
|= (1 << vector_bit
);
1492 IXGBE_WRITE_REG(hw
, IXGBE_MTA(vector_reg
), mta_reg
);
1496 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1497 * @hw: pointer to hardware structure
1498 * @netdev: pointer to net device structure
1500 * The given list replaces any existing list. Clears the MC addrs from receive
1501 * address registers and the multicast table. Uses unused receive address
1502 * registers for the first multicast addresses, and hashes the rest into the
1505 s32
ixgbe_update_mc_addr_list_generic(struct ixgbe_hw
*hw
,
1506 struct net_device
*netdev
)
1508 struct netdev_hw_addr
*ha
;
1512 * Set the new number of MC addresses that we are being requested to
1515 hw
->addr_ctrl
.num_mc_addrs
= netdev_mc_count(netdev
);
1516 hw
->addr_ctrl
.mta_in_use
= 0;
1519 hw_dbg(hw
, " Clearing MTA\n");
1520 for (i
= 0; i
< hw
->mac
.mcft_size
; i
++)
1521 IXGBE_WRITE_REG(hw
, IXGBE_MTA(i
), 0);
1523 /* Add the new addresses */
1524 netdev_for_each_mc_addr(ha
, netdev
) {
1525 hw_dbg(hw
, " Adding the multicast addresses:\n");
1526 ixgbe_set_mta(hw
, ha
->addr
);
1530 if (hw
->addr_ctrl
.mta_in_use
> 0)
1531 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
,
1532 IXGBE_MCSTCTRL_MFE
| hw
->mac
.mc_filter_type
);
1534 hw_dbg(hw
, "ixgbe_update_mc_addr_list_generic Complete\n");
1539 * ixgbe_enable_mc_generic - Enable multicast address in RAR
1540 * @hw: pointer to hardware structure
1542 * Enables multicast address in RAR and the use of the multicast hash table.
1544 s32
ixgbe_enable_mc_generic(struct ixgbe_hw
*hw
)
1547 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1548 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
1550 if (a
->mc_addr_in_rar_count
> 0)
1551 for (i
= (rar_entries
- a
->mc_addr_in_rar_count
);
1552 i
< rar_entries
; i
++)
1553 ixgbe_enable_rar(hw
, i
);
1555 if (a
->mta_in_use
> 0)
1556 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, IXGBE_MCSTCTRL_MFE
|
1557 hw
->mac
.mc_filter_type
);
1563 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1564 * @hw: pointer to hardware structure
1566 * Disables multicast address in RAR and the use of the multicast hash table.
1568 s32
ixgbe_disable_mc_generic(struct ixgbe_hw
*hw
)
1571 u32 rar_entries
= hw
->mac
.num_rar_entries
;
1572 struct ixgbe_addr_filter_info
*a
= &hw
->addr_ctrl
;
1574 if (a
->mc_addr_in_rar_count
> 0)
1575 for (i
= (rar_entries
- a
->mc_addr_in_rar_count
);
1576 i
< rar_entries
; i
++)
1577 ixgbe_disable_rar(hw
, i
);
1579 if (a
->mta_in_use
> 0)
1580 IXGBE_WRITE_REG(hw
, IXGBE_MCSTCTRL
, hw
->mac
.mc_filter_type
);
1586 * ixgbe_fc_enable_generic - Enable flow control
1587 * @hw: pointer to hardware structure
1588 * @packetbuf_num: packet buffer number (0-7)
1590 * Enable flow control according to the current settings.
1592 s32
ixgbe_fc_enable_generic(struct ixgbe_hw
*hw
, s32 packetbuf_num
)
1595 u32 mflcn_reg
, fccfg_reg
;
1600 if (hw
->fc
.requested_mode
== ixgbe_fc_pfc
)
1603 #endif /* CONFIG_DCB */
1604 /* Negotiate the fc mode to use */
1605 ret_val
= ixgbe_fc_autoneg(hw
);
1609 /* Disable any previous flow control settings */
1610 mflcn_reg
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
1611 mflcn_reg
&= ~(IXGBE_MFLCN_RFCE
| IXGBE_MFLCN_RPFCE
);
1613 fccfg_reg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
1614 fccfg_reg
&= ~(IXGBE_FCCFG_TFCE_802_3X
| IXGBE_FCCFG_TFCE_PRIORITY
);
1617 * The possible values of fc.current_mode are:
1618 * 0: Flow control is completely disabled
1619 * 1: Rx flow control is enabled (we can receive pause frames,
1620 * but not send pause frames).
1621 * 2: Tx flow control is enabled (we can send pause frames but
1622 * we do not support receiving pause frames).
1623 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1624 * 4: Priority Flow Control is enabled.
1627 switch (hw
->fc
.current_mode
) {
1630 * Flow control is disabled by software override or autoneg.
1631 * The code below will actually disable it in the HW.
1634 case ixgbe_fc_rx_pause
:
1636 * Rx Flow control is enabled and Tx Flow control is
1637 * disabled by software override. Since there really
1638 * isn't a way to advertise that we are capable of RX
1639 * Pause ONLY, we will advertise that we support both
1640 * symmetric and asymmetric Rx PAUSE. Later, we will
1641 * disable the adapter's ability to send PAUSE frames.
1643 mflcn_reg
|= IXGBE_MFLCN_RFCE
;
1645 case ixgbe_fc_tx_pause
:
1647 * Tx Flow control is enabled, and Rx Flow control is
1648 * disabled by software override.
1650 fccfg_reg
|= IXGBE_FCCFG_TFCE_802_3X
;
1653 /* Flow control (both Rx and Tx) is enabled by SW override. */
1654 mflcn_reg
|= IXGBE_MFLCN_RFCE
;
1655 fccfg_reg
|= IXGBE_FCCFG_TFCE_802_3X
;
1661 #endif /* CONFIG_DCB */
1663 hw_dbg(hw
, "Flow control param set incorrectly\n");
1664 ret_val
= IXGBE_ERR_CONFIG
;
1669 /* Set 802.3x based flow control settings. */
1670 mflcn_reg
|= IXGBE_MFLCN_DPF
;
1671 IXGBE_WRITE_REG(hw
, IXGBE_MFLCN
, mflcn_reg
);
1672 IXGBE_WRITE_REG(hw
, IXGBE_FCCFG
, fccfg_reg
);
1674 reg
= IXGBE_READ_REG(hw
, IXGBE_MTQC
);
1675 /* Thresholds are different for link flow control when in DCB mode */
1676 if (reg
& IXGBE_MTQC_RT_ENA
) {
1677 rx_pba_size
= IXGBE_READ_REG(hw
, IXGBE_RXPBSIZE(packetbuf_num
));
1679 /* Always disable XON for LFC when in DCB mode */
1680 reg
= (rx_pba_size
>> 5) & 0xFFE0;
1681 IXGBE_WRITE_REG(hw
, IXGBE_FCRTL_82599(packetbuf_num
), reg
);
1683 reg
= (rx_pba_size
>> 2) & 0xFFE0;
1684 if (hw
->fc
.current_mode
& ixgbe_fc_tx_pause
)
1685 reg
|= IXGBE_FCRTH_FCEN
;
1686 IXGBE_WRITE_REG(hw
, IXGBE_FCRTH_82599(packetbuf_num
), reg
);
1689 * Set up and enable Rx high/low water mark thresholds,
1692 if (hw
->fc
.current_mode
& ixgbe_fc_tx_pause
) {
1693 if (hw
->fc
.send_xon
) {
1695 IXGBE_FCRTL_82599(packetbuf_num
),
1700 IXGBE_FCRTL_82599(packetbuf_num
),
1704 IXGBE_WRITE_REG(hw
, IXGBE_FCRTH_82599(packetbuf_num
),
1705 (hw
->fc
.high_water
| IXGBE_FCRTH_FCEN
));
1709 /* Configure pause time (2 TCs per register) */
1710 reg
= IXGBE_READ_REG(hw
, IXGBE_FCTTV(packetbuf_num
/ 2));
1711 if ((packetbuf_num
& 1) == 0)
1712 reg
= (reg
& 0xFFFF0000) | hw
->fc
.pause_time
;
1714 reg
= (reg
& 0x0000FFFF) | (hw
->fc
.pause_time
<< 16);
1715 IXGBE_WRITE_REG(hw
, IXGBE_FCTTV(packetbuf_num
/ 2), reg
);
1717 IXGBE_WRITE_REG(hw
, IXGBE_FCRTV
, (hw
->fc
.pause_time
>> 1));
1724 * ixgbe_fc_autoneg - Configure flow control
1725 * @hw: pointer to hardware structure
1727 * Compares our advertised flow control capabilities to those advertised by
1728 * our link partner, and determines the proper flow control mode to use.
1730 s32
ixgbe_fc_autoneg(struct ixgbe_hw
*hw
)
1733 ixgbe_link_speed speed
;
1734 u32 pcs_anadv_reg
, pcs_lpab_reg
, linkstat
;
1735 u32 links2
, anlp1_reg
, autoc_reg
, links
;
1739 * AN should have completed when the cable was plugged in.
1740 * Look for reasons to bail out. Bail out if:
1741 * - FC autoneg is disabled, or if
1744 * Since we're being called from an LSC, link is already known to be up.
1745 * So use link_up_wait_to_complete=false.
1747 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
1749 if (hw
->fc
.disable_fc_autoneg
|| (!link_up
)) {
1750 hw
->fc
.fc_was_autonegged
= false;
1751 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1756 * On backplane, bail out if
1757 * - backplane autoneg was not completed, or if
1758 * - we are 82599 and link partner is not AN enabled
1760 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
) {
1761 links
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
1762 if ((links
& IXGBE_LINKS_KX_AN_COMP
) == 0) {
1763 hw
->fc
.fc_was_autonegged
= false;
1764 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1768 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1769 links2
= IXGBE_READ_REG(hw
, IXGBE_LINKS2
);
1770 if ((links2
& IXGBE_LINKS2_AN_SUPPORTED
) == 0) {
1771 hw
->fc
.fc_was_autonegged
= false;
1772 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1779 * On multispeed fiber at 1g, bail out if
1780 * - link is up but AN did not complete, or if
1781 * - link is up and AN completed but timed out
1783 if (hw
->phy
.multispeed_fiber
&& (speed
== IXGBE_LINK_SPEED_1GB_FULL
)) {
1784 linkstat
= IXGBE_READ_REG(hw
, IXGBE_PCS1GLSTA
);
1785 if (((linkstat
& IXGBE_PCS1GLSTA_AN_COMPLETE
) == 0) ||
1786 ((linkstat
& IXGBE_PCS1GLSTA_AN_TIMED_OUT
) == 1)) {
1787 hw
->fc
.fc_was_autonegged
= false;
1788 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1795 * - copper or CX4 adapters
1796 * - fiber adapters running at 10gig
1798 if ((hw
->phy
.media_type
== ixgbe_media_type_copper
) ||
1799 (hw
->phy
.media_type
== ixgbe_media_type_cx4
) ||
1800 ((hw
->phy
.media_type
== ixgbe_media_type_fiber
) &&
1801 (speed
== IXGBE_LINK_SPEED_10GB_FULL
))) {
1802 hw
->fc
.fc_was_autonegged
= false;
1803 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1808 * Read the AN advertisement and LP ability registers and resolve
1809 * local flow control settings accordingly
1811 if ((speed
== IXGBE_LINK_SPEED_1GB_FULL
) &&
1812 (hw
->phy
.media_type
!= ixgbe_media_type_backplane
)) {
1813 pcs_anadv_reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANA
);
1814 pcs_lpab_reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANLP
);
1815 if ((pcs_anadv_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1816 (pcs_lpab_reg
& IXGBE_PCS1GANA_SYM_PAUSE
)) {
1818 * Now we need to check if the user selected Rx ONLY
1819 * of pause frames. In this case, we had to advertise
1820 * FULL flow control because we could not advertise RX
1821 * ONLY. Hence, we must now check to see if we need to
1822 * turn OFF the TRANSMISSION of PAUSE frames.
1824 if (hw
->fc
.requested_mode
== ixgbe_fc_full
) {
1825 hw
->fc
.current_mode
= ixgbe_fc_full
;
1826 hw_dbg(hw
, "Flow Control = FULL.\n");
1828 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
1829 hw_dbg(hw
, "Flow Control=RX PAUSE only\n");
1831 } else if (!(pcs_anadv_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1832 (pcs_anadv_reg
& IXGBE_PCS1GANA_ASM_PAUSE
) &&
1833 (pcs_lpab_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1834 (pcs_lpab_reg
& IXGBE_PCS1GANA_ASM_PAUSE
)) {
1835 hw
->fc
.current_mode
= ixgbe_fc_tx_pause
;
1836 hw_dbg(hw
, "Flow Control = TX PAUSE frames only.\n");
1837 } else if ((pcs_anadv_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1838 (pcs_anadv_reg
& IXGBE_PCS1GANA_ASM_PAUSE
) &&
1839 !(pcs_lpab_reg
& IXGBE_PCS1GANA_SYM_PAUSE
) &&
1840 (pcs_lpab_reg
& IXGBE_PCS1GANA_ASM_PAUSE
)) {
1841 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
1842 hw_dbg(hw
, "Flow Control = RX PAUSE frames only.\n");
1844 hw
->fc
.current_mode
= ixgbe_fc_none
;
1845 hw_dbg(hw
, "Flow Control = NONE.\n");
1849 if (hw
->phy
.media_type
== ixgbe_media_type_backplane
) {
1851 * Read the 10g AN autoc and LP ability registers and resolve
1852 * local flow control settings accordingly
1854 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
1855 anlp1_reg
= IXGBE_READ_REG(hw
, IXGBE_ANLP1
);
1857 if ((autoc_reg
& IXGBE_AUTOC_SYM_PAUSE
) &&
1858 (anlp1_reg
& IXGBE_ANLP1_SYM_PAUSE
)) {
1860 * Now we need to check if the user selected Rx ONLY
1861 * of pause frames. In this case, we had to advertise
1862 * FULL flow control because we could not advertise RX
1863 * ONLY. Hence, we must now check to see if we need to
1864 * turn OFF the TRANSMISSION of PAUSE frames.
1866 if (hw
->fc
.requested_mode
== ixgbe_fc_full
) {
1867 hw
->fc
.current_mode
= ixgbe_fc_full
;
1868 hw_dbg(hw
, "Flow Control = FULL.\n");
1870 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
1871 hw_dbg(hw
, "Flow Control=RX PAUSE only\n");
1873 } else if (!(autoc_reg
& IXGBE_AUTOC_SYM_PAUSE
) &&
1874 (autoc_reg
& IXGBE_AUTOC_ASM_PAUSE
) &&
1875 (anlp1_reg
& IXGBE_ANLP1_SYM_PAUSE
) &&
1876 (anlp1_reg
& IXGBE_ANLP1_ASM_PAUSE
)) {
1877 hw
->fc
.current_mode
= ixgbe_fc_tx_pause
;
1878 hw_dbg(hw
, "Flow Control = TX PAUSE frames only.\n");
1879 } else if ((autoc_reg
& IXGBE_AUTOC_SYM_PAUSE
) &&
1880 (autoc_reg
& IXGBE_AUTOC_ASM_PAUSE
) &&
1881 !(anlp1_reg
& IXGBE_ANLP1_SYM_PAUSE
) &&
1882 (anlp1_reg
& IXGBE_ANLP1_ASM_PAUSE
)) {
1883 hw
->fc
.current_mode
= ixgbe_fc_rx_pause
;
1884 hw_dbg(hw
, "Flow Control = RX PAUSE frames only.\n");
1886 hw
->fc
.current_mode
= ixgbe_fc_none
;
1887 hw_dbg(hw
, "Flow Control = NONE.\n");
1890 /* Record that current_mode is the result of a successful autoneg */
1891 hw
->fc
.fc_was_autonegged
= true;
1898 * ixgbe_setup_fc - Set up flow control
1899 * @hw: pointer to hardware structure
1901 * Called at init time to set up flow control.
1903 static s32
ixgbe_setup_fc(struct ixgbe_hw
*hw
, s32 packetbuf_num
)
1909 if (hw
->fc
.requested_mode
== ixgbe_fc_pfc
) {
1910 hw
->fc
.current_mode
= hw
->fc
.requested_mode
;
1915 /* Validate the packetbuf configuration */
1916 if (packetbuf_num
< 0 || packetbuf_num
> 7) {
1917 hw_dbg(hw
, "Invalid packet buffer number [%d], expected range "
1918 "is 0-7\n", packetbuf_num
);
1919 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
1924 * Validate the water mark configuration. Zero water marks are invalid
1925 * because it causes the controller to just blast out fc packets.
1927 if (!hw
->fc
.low_water
|| !hw
->fc
.high_water
|| !hw
->fc
.pause_time
) {
1928 hw_dbg(hw
, "Invalid water mark configuration\n");
1929 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
1934 * Validate the requested mode. Strict IEEE mode does not allow
1935 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
1937 if (hw
->fc
.strict_ieee
&& hw
->fc
.requested_mode
== ixgbe_fc_rx_pause
) {
1938 hw_dbg(hw
, "ixgbe_fc_rx_pause not valid in strict "
1940 ret_val
= IXGBE_ERR_INVALID_LINK_SETTINGS
;
1945 * 10gig parts do not have a word in the EEPROM to determine the
1946 * default flow control setting, so we explicitly set it to full.
1948 if (hw
->fc
.requested_mode
== ixgbe_fc_default
)
1949 hw
->fc
.requested_mode
= ixgbe_fc_full
;
1952 * Set up the 1G flow control advertisement registers so the HW will be
1953 * able to do fc autoneg once the cable is plugged in. If we end up
1954 * using 10g instead, this is harmless.
1956 reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GANA
);
1959 * The possible values of fc.requested_mode are:
1960 * 0: Flow control is completely disabled
1961 * 1: Rx flow control is enabled (we can receive pause frames,
1962 * but not send pause frames).
1963 * 2: Tx flow control is enabled (we can send pause frames but
1964 * we do not support receiving pause frames).
1965 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1967 * 4: Priority Flow Control is enabled.
1971 switch (hw
->fc
.requested_mode
) {
1973 /* Flow control completely disabled by software override. */
1974 reg
&= ~(IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
1976 case ixgbe_fc_rx_pause
:
1978 * Rx Flow control is enabled and Tx Flow control is
1979 * disabled by software override. Since there really
1980 * isn't a way to advertise that we are capable of RX
1981 * Pause ONLY, we will advertise that we support both
1982 * symmetric and asymmetric Rx PAUSE. Later, we will
1983 * disable the adapter's ability to send PAUSE frames.
1985 reg
|= (IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
1987 case ixgbe_fc_tx_pause
:
1989 * Tx Flow control is enabled, and Rx Flow control is
1990 * disabled by software override.
1992 reg
|= (IXGBE_PCS1GANA_ASM_PAUSE
);
1993 reg
&= ~(IXGBE_PCS1GANA_SYM_PAUSE
);
1996 /* Flow control (both Rx and Tx) is enabled by SW override. */
1997 reg
|= (IXGBE_PCS1GANA_SYM_PAUSE
| IXGBE_PCS1GANA_ASM_PAUSE
);
2003 #endif /* CONFIG_DCB */
2005 hw_dbg(hw
, "Flow control param set incorrectly\n");
2006 ret_val
= IXGBE_ERR_CONFIG
;
2011 IXGBE_WRITE_REG(hw
, IXGBE_PCS1GANA
, reg
);
2012 reg
= IXGBE_READ_REG(hw
, IXGBE_PCS1GLCTL
);
2014 /* Disable AN timeout */
2015 if (hw
->fc
.strict_ieee
)
2016 reg
&= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN
;
2018 IXGBE_WRITE_REG(hw
, IXGBE_PCS1GLCTL
, reg
);
2019 hw_dbg(hw
, "Set up FC; PCS1GLCTL = 0x%08X\n", reg
);
2022 * Set up the 10G flow control advertisement registers so the HW
2023 * can do fc autoneg once the cable is plugged in. If we end up
2024 * using 1g instead, this is harmless.
2026 reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2029 * The possible values of fc.requested_mode are:
2030 * 0: Flow control is completely disabled
2031 * 1: Rx flow control is enabled (we can receive pause frames,
2032 * but not send pause frames).
2033 * 2: Tx flow control is enabled (we can send pause frames but
2034 * we do not support receiving pause frames).
2035 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2038 switch (hw
->fc
.requested_mode
) {
2040 /* Flow control completely disabled by software override. */
2041 reg
&= ~(IXGBE_AUTOC_SYM_PAUSE
| IXGBE_AUTOC_ASM_PAUSE
);
2043 case ixgbe_fc_rx_pause
:
2045 * Rx Flow control is enabled and Tx Flow control is
2046 * disabled by software override. Since there really
2047 * isn't a way to advertise that we are capable of RX
2048 * Pause ONLY, we will advertise that we support both
2049 * symmetric and asymmetric Rx PAUSE. Later, we will
2050 * disable the adapter's ability to send PAUSE frames.
2052 reg
|= (IXGBE_AUTOC_SYM_PAUSE
| IXGBE_AUTOC_ASM_PAUSE
);
2054 case ixgbe_fc_tx_pause
:
2056 * Tx Flow control is enabled, and Rx Flow control is
2057 * disabled by software override.
2059 reg
|= (IXGBE_AUTOC_ASM_PAUSE
);
2060 reg
&= ~(IXGBE_AUTOC_SYM_PAUSE
);
2063 /* Flow control (both Rx and Tx) is enabled by SW override. */
2064 reg
|= (IXGBE_AUTOC_SYM_PAUSE
| IXGBE_AUTOC_ASM_PAUSE
);
2070 #endif /* CONFIG_DCB */
2072 hw_dbg(hw
, "Flow control param set incorrectly\n");
2073 ret_val
= IXGBE_ERR_CONFIG
;
2078 * AUTOC restart handles negotiation of 1G and 10G. There is
2079 * no need to set the PCS1GCTL register.
2081 reg
|= IXGBE_AUTOC_AN_RESTART
;
2082 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, reg
);
2083 hw_dbg(hw
, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg
);
2090 * ixgbe_disable_pcie_master - Disable PCI-express master access
2091 * @hw: pointer to hardware structure
2093 * Disables PCI-Express master access and verifies there are no pending
2094 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
2095 * bit hasn't caused the master requests to be disabled, else 0
2096 * is returned signifying master requests disabled.
2098 s32
ixgbe_disable_pcie_master(struct ixgbe_hw
*hw
)
2102 u32 number_of_queues
;
2103 s32 status
= IXGBE_ERR_MASTER_REQUESTS_PENDING
;
2105 /* Disable the receive unit by stopping each queue */
2106 number_of_queues
= hw
->mac
.max_rx_queues
;
2107 for (i
= 0; i
< number_of_queues
; i
++) {
2108 reg_val
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
2109 if (reg_val
& IXGBE_RXDCTL_ENABLE
) {
2110 reg_val
&= ~IXGBE_RXDCTL_ENABLE
;
2111 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(i
), reg_val
);
2115 reg_val
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
2116 reg_val
|= IXGBE_CTRL_GIO_DIS
;
2117 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, reg_val
);
2119 for (i
= 0; i
< IXGBE_PCI_MASTER_DISABLE_TIMEOUT
; i
++) {
2120 if (!(IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_GIO
)) {
2132 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
2133 * @hw: pointer to hardware structure
2134 * @mask: Mask to specify which semaphore to acquire
2136 * Acquires the SWFW semaphore thought the GSSR register for the specified
2137 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2139 s32
ixgbe_acquire_swfw_sync(struct ixgbe_hw
*hw
, u16 mask
)
2143 u32 fwmask
= mask
<< 5;
2147 if (ixgbe_get_eeprom_semaphore(hw
))
2148 return IXGBE_ERR_SWFW_SYNC
;
2150 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
2151 if (!(gssr
& (fwmask
| swmask
)))
2155 * Firmware currently using resource (fwmask) or other software
2156 * thread currently using resource (swmask)
2158 ixgbe_release_eeprom_semaphore(hw
);
2164 hw_dbg(hw
, "Driver can't access resource, GSSR timeout.\n");
2165 return IXGBE_ERR_SWFW_SYNC
;
2169 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
2171 ixgbe_release_eeprom_semaphore(hw
);
2176 * ixgbe_release_swfw_sync - Release SWFW semaphore
2177 * @hw: pointer to hardware structure
2178 * @mask: Mask to specify which semaphore to release
2180 * Releases the SWFW semaphore thought the GSSR register for the specified
2181 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2183 void ixgbe_release_swfw_sync(struct ixgbe_hw
*hw
, u16 mask
)
2188 ixgbe_get_eeprom_semaphore(hw
);
2190 gssr
= IXGBE_READ_REG(hw
, IXGBE_GSSR
);
2192 IXGBE_WRITE_REG(hw
, IXGBE_GSSR
, gssr
);
2194 ixgbe_release_eeprom_semaphore(hw
);
2198 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2199 * @hw: pointer to hardware structure
2200 * @regval: register value to write to RXCTRL
2202 * Enables the Rx DMA unit
2204 s32
ixgbe_enable_rx_dma_generic(struct ixgbe_hw
*hw
, u32 regval
)
2206 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, regval
);
2212 * ixgbe_blink_led_start_generic - Blink LED based on index.
2213 * @hw: pointer to hardware structure
2214 * @index: led number to blink
2216 s32
ixgbe_blink_led_start_generic(struct ixgbe_hw
*hw
, u32 index
)
2218 ixgbe_link_speed speed
= 0;
2220 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2221 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
2224 * Link must be up to auto-blink the LEDs;
2225 * Force it if link is down.
2227 hw
->mac
.ops
.check_link(hw
, &speed
, &link_up
, false);
2230 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
2231 autoc_reg
|= IXGBE_AUTOC_FLU
;
2232 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
2236 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
2237 led_reg
|= IXGBE_LED_BLINK(index
);
2238 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
2239 IXGBE_WRITE_FLUSH(hw
);
2245 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2246 * @hw: pointer to hardware structure
2247 * @index: led number to stop blinking
2249 s32
ixgbe_blink_led_stop_generic(struct ixgbe_hw
*hw
, u32 index
)
2251 u32 autoc_reg
= IXGBE_READ_REG(hw
, IXGBE_AUTOC
);
2252 u32 led_reg
= IXGBE_READ_REG(hw
, IXGBE_LEDCTL
);
2254 autoc_reg
&= ~IXGBE_AUTOC_FLU
;
2255 autoc_reg
|= IXGBE_AUTOC_AN_RESTART
;
2256 IXGBE_WRITE_REG(hw
, IXGBE_AUTOC
, autoc_reg
);
2258 led_reg
&= ~IXGBE_LED_MODE_MASK(index
);
2259 led_reg
&= ~IXGBE_LED_BLINK(index
);
2260 led_reg
|= IXGBE_LED_LINK_ACTIVE
<< IXGBE_LED_MODE_SHIFT(index
);
2261 IXGBE_WRITE_REG(hw
, IXGBE_LEDCTL
, led_reg
);
2262 IXGBE_WRITE_FLUSH(hw
);
2268 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
2269 * @hw: pointer to hardware structure
2270 * @san_mac_offset: SAN MAC address offset
2272 * This function will read the EEPROM location for the SAN MAC address
2273 * pointer, and returns the value at that location. This is used in both
2274 * get and set mac_addr routines.
2276 static s32
ixgbe_get_san_mac_addr_offset(struct ixgbe_hw
*hw
,
2277 u16
*san_mac_offset
)
2280 * First read the EEPROM pointer to see if the MAC addresses are
2283 hw
->eeprom
.ops
.read(hw
, IXGBE_SAN_MAC_ADDR_PTR
, san_mac_offset
);
2289 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
2290 * @hw: pointer to hardware structure
2291 * @san_mac_addr: SAN MAC address
2293 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2294 * per-port, so set_lan_id() must be called before reading the addresses.
2295 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2296 * upon for non-SFP connections, so we must call it here.
2298 s32
ixgbe_get_san_mac_addr_generic(struct ixgbe_hw
*hw
, u8
*san_mac_addr
)
2300 u16 san_mac_data
, san_mac_offset
;
2304 * First read the EEPROM pointer to see if the MAC addresses are
2305 * available. If they're not, no point in calling set_lan_id() here.
2307 ixgbe_get_san_mac_addr_offset(hw
, &san_mac_offset
);
2309 if ((san_mac_offset
== 0) || (san_mac_offset
== 0xFFFF)) {
2311 * No addresses available in this EEPROM. It's not an
2312 * error though, so just wipe the local address and return.
2314 for (i
= 0; i
< 6; i
++)
2315 san_mac_addr
[i
] = 0xFF;
2317 goto san_mac_addr_out
;
2320 /* make sure we know which port we need to program */
2321 hw
->mac
.ops
.set_lan_id(hw
);
2322 /* apply the port offset to the address offset */
2323 (hw
->bus
.func
) ? (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT1_OFFSET
) :
2324 (san_mac_offset
+= IXGBE_SAN_MAC_ADDR_PORT0_OFFSET
);
2325 for (i
= 0; i
< 3; i
++) {
2326 hw
->eeprom
.ops
.read(hw
, san_mac_offset
, &san_mac_data
);
2327 san_mac_addr
[i
* 2] = (u8
)(san_mac_data
);
2328 san_mac_addr
[i
* 2 + 1] = (u8
)(san_mac_data
>> 8);
2337 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
2338 * @hw: pointer to hardware structure
2340 * Read PCIe configuration space, and get the MSI-X vector count from
2341 * the capabilities table.
2343 u32
ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw
*hw
)
2345 struct ixgbe_adapter
*adapter
= hw
->back
;
2347 pci_read_config_word(adapter
->pdev
, IXGBE_PCIE_MSIX_82599_CAPS
,
2349 msix_count
&= IXGBE_PCIE_MSIX_TBL_SZ_MASK
;
2351 /* MSI-X count is zero-based in HW, so increment to give proper value */
2358 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
2359 * @hw: pointer to hardware struct
2360 * @rar: receive address register index to disassociate
2361 * @vmdq: VMDq pool index to remove from the rar
2363 s32
ixgbe_clear_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
2365 u32 mpsar_lo
, mpsar_hi
;
2366 u32 rar_entries
= hw
->mac
.num_rar_entries
;
2368 if (rar
< rar_entries
) {
2369 mpsar_lo
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
2370 mpsar_hi
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
2372 if (!mpsar_lo
&& !mpsar_hi
)
2375 if (vmdq
== IXGBE_CLEAR_VMDQ_ALL
) {
2377 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), 0);
2381 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), 0);
2384 } else if (vmdq
< 32) {
2385 mpsar_lo
&= ~(1 << vmdq
);
2386 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar_lo
);
2388 mpsar_hi
&= ~(1 << (vmdq
- 32));
2389 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar_hi
);
2392 /* was that the last pool using this rar? */
2393 if (mpsar_lo
== 0 && mpsar_hi
== 0 && rar
!= 0)
2394 hw
->mac
.ops
.clear_rar(hw
, rar
);
2396 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
2404 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
2405 * @hw: pointer to hardware struct
2406 * @rar: receive address register index to associate with a VMDq index
2407 * @vmdq: VMDq pool index
2409 s32
ixgbe_set_vmdq_generic(struct ixgbe_hw
*hw
, u32 rar
, u32 vmdq
)
2412 u32 rar_entries
= hw
->mac
.num_rar_entries
;
2414 if (rar
< rar_entries
) {
2416 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_LO(rar
));
2418 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_LO(rar
), mpsar
);
2420 mpsar
= IXGBE_READ_REG(hw
, IXGBE_MPSAR_HI(rar
));
2421 mpsar
|= 1 << (vmdq
- 32);
2422 IXGBE_WRITE_REG(hw
, IXGBE_MPSAR_HI(rar
), mpsar
);
2425 hw_dbg(hw
, "RAR index %d is out of range.\n", rar
);
2431 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
2432 * @hw: pointer to hardware structure
2434 s32
ixgbe_init_uta_tables_generic(struct ixgbe_hw
*hw
)
2439 for (i
= 0; i
< 128; i
++)
2440 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), 0);
2446 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
2447 * @hw: pointer to hardware structure
2448 * @vlan: VLAN id to write to VLAN filter
2450 * return the VLVF index where this VLAN id should be placed
2453 static s32
ixgbe_find_vlvf_slot(struct ixgbe_hw
*hw
, u32 vlan
)
2456 u32 first_empty_slot
= 0;
2459 /* short cut the special case */
2464 * Search for the vlan id in the VLVF entries. Save off the first empty
2465 * slot found along the way
2467 for (regindex
= 1; regindex
< IXGBE_VLVF_ENTRIES
; regindex
++) {
2468 bits
= IXGBE_READ_REG(hw
, IXGBE_VLVF(regindex
));
2469 if (!bits
&& !(first_empty_slot
))
2470 first_empty_slot
= regindex
;
2471 else if ((bits
& 0x0FFF) == vlan
)
2476 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
2477 * in the VLVF. Else use the first empty VLVF register for this
2480 if (regindex
>= IXGBE_VLVF_ENTRIES
) {
2481 if (first_empty_slot
)
2482 regindex
= first_empty_slot
;
2484 hw_dbg(hw
, "No space in VLVF.\n");
2485 regindex
= IXGBE_ERR_NO_SPACE
;
2493 * ixgbe_set_vfta_generic - Set VLAN filter table
2494 * @hw: pointer to hardware structure
2495 * @vlan: VLAN id to write to VLAN filter
2496 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
2497 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
2499 * Turn on/off specified VLAN in the VLAN filter table.
2501 s32
ixgbe_set_vfta_generic(struct ixgbe_hw
*hw
, u32 vlan
, u32 vind
,
2510 bool vfta_changed
= false;
2513 return IXGBE_ERR_PARAM
;
2516 * this is a 2 part operation - first the VFTA, then the
2517 * VLVF and VLVFB if VT Mode is set
2518 * We don't write the VFTA until we know the VLVF part succeeded.
2522 * The VFTA is a bitstring made up of 128 32-bit registers
2523 * that enable the particular VLAN id, much like the MTA:
2524 * bits[11-5]: which register
2525 * bits[4-0]: which bit in the register
2527 regindex
= (vlan
>> 5) & 0x7F;
2528 bitindex
= vlan
& 0x1F;
2529 targetbit
= (1 << bitindex
);
2530 vfta
= IXGBE_READ_REG(hw
, IXGBE_VFTA(regindex
));
2533 if (!(vfta
& targetbit
)) {
2535 vfta_changed
= true;
2538 if ((vfta
& targetbit
)) {
2540 vfta_changed
= true;
2547 * make sure the vlan is in VLVF
2548 * set the vind bit in the matching VLVFB
2550 * clear the pool bit and possibly the vind
2552 vt
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2553 if (vt
& IXGBE_VT_CTL_VT_ENABLE
) {
2556 vlvf_index
= ixgbe_find_vlvf_slot(hw
, vlan
);
2561 /* set the pool bit */
2563 bits
= IXGBE_READ_REG(hw
,
2564 IXGBE_VLVFB(vlvf_index
*2));
2565 bits
|= (1 << vind
);
2567 IXGBE_VLVFB(vlvf_index
*2),
2570 bits
= IXGBE_READ_REG(hw
,
2571 IXGBE_VLVFB((vlvf_index
*2)+1));
2572 bits
|= (1 << (vind
-32));
2574 IXGBE_VLVFB((vlvf_index
*2)+1),
2578 /* clear the pool bit */
2580 bits
= IXGBE_READ_REG(hw
,
2581 IXGBE_VLVFB(vlvf_index
*2));
2582 bits
&= ~(1 << vind
);
2584 IXGBE_VLVFB(vlvf_index
*2),
2586 bits
|= IXGBE_READ_REG(hw
,
2587 IXGBE_VLVFB((vlvf_index
*2)+1));
2589 bits
= IXGBE_READ_REG(hw
,
2590 IXGBE_VLVFB((vlvf_index
*2)+1));
2591 bits
&= ~(1 << (vind
-32));
2593 IXGBE_VLVFB((vlvf_index
*2)+1),
2595 bits
|= IXGBE_READ_REG(hw
,
2596 IXGBE_VLVFB(vlvf_index
*2));
2601 * If there are still bits set in the VLVFB registers
2602 * for the VLAN ID indicated we need to see if the
2603 * caller is requesting that we clear the VFTA entry bit.
2604 * If the caller has requested that we clear the VFTA
2605 * entry bit but there are still pools/VFs using this VLAN
2606 * ID entry then ignore the request. We're not worried
2607 * about the case where we're turning the VFTA VLAN ID
2608 * entry bit on, only when requested to turn it off as
2609 * there may be multiple pools and/or VFs using the
2610 * VLAN ID entry. In that case we cannot clear the
2611 * VFTA bit until all pools/VFs using that VLAN ID have also
2612 * been cleared. This will be indicated by "bits" being
2616 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(vlvf_index
),
2617 (IXGBE_VLVF_VIEN
| vlan
));
2619 /* someone wants to clear the vfta entry
2620 * but some pools/VFs are still using it.
2622 vfta_changed
= false;
2626 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(vlvf_index
), 0);
2630 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(regindex
), vfta
);
2636 * ixgbe_clear_vfta_generic - Clear VLAN filter table
2637 * @hw: pointer to hardware structure
2639 * Clears the VLAN filer table, and the VMDq index associated with the filter
2641 s32
ixgbe_clear_vfta_generic(struct ixgbe_hw
*hw
)
2645 for (offset
= 0; offset
< hw
->mac
.vft_size
; offset
++)
2646 IXGBE_WRITE_REG(hw
, IXGBE_VFTA(offset
), 0);
2648 for (offset
= 0; offset
< IXGBE_VLVF_ENTRIES
; offset
++) {
2649 IXGBE_WRITE_REG(hw
, IXGBE_VLVF(offset
), 0);
2650 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB(offset
*2), 0);
2651 IXGBE_WRITE_REG(hw
, IXGBE_VLVFB((offset
*2)+1), 0);
2658 * ixgbe_check_mac_link_generic - Determine link and speed status
2659 * @hw: pointer to hardware structure
2660 * @speed: pointer to link speed
2661 * @link_up: true when link is up
2662 * @link_up_wait_to_complete: bool used to wait for link up or not
2664 * Reads the links register to determine if link is up and the current speed
2666 s32
ixgbe_check_mac_link_generic(struct ixgbe_hw
*hw
, ixgbe_link_speed
*speed
,
2667 bool *link_up
, bool link_up_wait_to_complete
)
2672 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
2673 if (link_up_wait_to_complete
) {
2674 for (i
= 0; i
< IXGBE_LINK_UP_TIME
; i
++) {
2675 if (links_reg
& IXGBE_LINKS_UP
) {
2682 links_reg
= IXGBE_READ_REG(hw
, IXGBE_LINKS
);
2685 if (links_reg
& IXGBE_LINKS_UP
)
2691 if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
2692 IXGBE_LINKS_SPEED_10G_82599
)
2693 *speed
= IXGBE_LINK_SPEED_10GB_FULL
;
2694 else if ((links_reg
& IXGBE_LINKS_SPEED_82599
) ==
2695 IXGBE_LINKS_SPEED_1G_82599
)
2696 *speed
= IXGBE_LINK_SPEED_1GB_FULL
;
2698 *speed
= IXGBE_LINK_SPEED_100_FULL
;
2700 /* if link is down, zero out the current_mode */
2701 if (*link_up
== false) {
2702 hw
->fc
.current_mode
= ixgbe_fc_none
;
2703 hw
->fc
.fc_was_autonegged
= false;