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ixgbe: move all GPIE register config into a single function
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
45
46 #include "ixgbe.h"
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
50
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
54
55 #define DRV_VERSION "2.0.84-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
58
59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
60 [board_82598] = &ixgbe_82598_info,
61 [board_82599] = &ixgbe_82599_info,
62 };
63
64 /* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
76 board_82598 },
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
78 board_82598 },
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
84 board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
115
116 /* required last entry */
117 {0, }
118 };
119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
123 void *p);
124 static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128 };
129 #endif
130
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs;
133 module_param(max_vfs, uint, 0);
134 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
135 "per physical function");
136 #endif /* CONFIG_PCI_IOV */
137
138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_VERSION);
142
143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146 {
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152 #ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155 #endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
172 if (adapter->vfinfo)
173 kfree(adapter->vfinfo);
174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178 }
179
180 struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183 };
184
185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215 };
216
217
218 /*
219 * ixgbe_regdump - register printout routine
220 */
221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222 {
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
285 printk(KERN_INFO "%-15s %08x\n", reginfo->name,
286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
292 printk(KERN_ERR "%-15s ", rname);
293 for (j = 0; j < 8; j++)
294 printk(KERN_CONT "%08x ", regs[i*8+j]);
295 printk(KERN_CONT "\n");
296 }
297
298 }
299
300 /*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
304 {
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
325 printk(KERN_INFO "Device Name state "
326 "trans_start last_rx\n");
327 printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
336 printk(KERN_INFO " Register Name Value\n");
337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
347 printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma ] "
348 "leng ntw timestamp\n");
349 for (n = 0; n < adapter->num_tx_queues; n++) {
350 tx_ring = adapter->tx_ring[n];
351 tx_buffer_info =
352 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
353 printk(KERN_INFO " %5d %5X %5X %016llX %04X %3X %016llX\n",
354 n, tx_ring->next_to_use, tx_ring->next_to_clean,
355 (u64)tx_buffer_info->dma,
356 tx_buffer_info->length,
357 tx_buffer_info->next_to_watch,
358 (u64)tx_buffer_info->time_stamp);
359 }
360
361 /* Print TX Rings */
362 if (!netif_msg_tx_done(adapter))
363 goto rx_ring_summary;
364
365 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
366
367 /* Transmit Descriptor Formats
368 *
369 * Advanced Transmit Descriptor
370 * +--------------------------------------------------------------+
371 * 0 | Buffer Address [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
374 * +--------------------------------------------------------------+
375 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
376 */
377
378 for (n = 0; n < adapter->num_tx_queues; n++) {
379 tx_ring = adapter->tx_ring[n];
380 printk(KERN_INFO "------------------------------------\n");
381 printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
382 printk(KERN_INFO "------------------------------------\n");
383 printk(KERN_INFO "T [desc] [address 63:0 ] "
384 "[PlPOIdStDDt Ln] [bi->dma ] "
385 "leng ntw timestamp bi->skb\n");
386
387 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
388 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
389 tx_buffer_info = &tx_ring->tx_buffer_info[i];
390 u0 = (struct my_u0 *)tx_desc;
391 printk(KERN_INFO "T [0x%03X] %016llX %016llX %016llX"
392 " %04X %3X %016llX %p", i,
393 le64_to_cpu(u0->a),
394 le64_to_cpu(u0->b),
395 (u64)tx_buffer_info->dma,
396 tx_buffer_info->length,
397 tx_buffer_info->next_to_watch,
398 (u64)tx_buffer_info->time_stamp,
399 tx_buffer_info->skb);
400 if (i == tx_ring->next_to_use &&
401 i == tx_ring->next_to_clean)
402 printk(KERN_CONT " NTC/U\n");
403 else if (i == tx_ring->next_to_use)
404 printk(KERN_CONT " NTU\n");
405 else if (i == tx_ring->next_to_clean)
406 printk(KERN_CONT " NTC\n");
407 else
408 printk(KERN_CONT "\n");
409
410 if (netif_msg_pktdata(adapter) &&
411 tx_buffer_info->dma != 0)
412 print_hex_dump(KERN_INFO, "",
413 DUMP_PREFIX_ADDRESS, 16, 1,
414 phys_to_virt(tx_buffer_info->dma),
415 tx_buffer_info->length, true);
416 }
417 }
418
419 /* Print RX Rings Summary */
420 rx_ring_summary:
421 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
422 printk(KERN_INFO "Queue [NTU] [NTC]\n");
423 for (n = 0; n < adapter->num_rx_queues; n++) {
424 rx_ring = adapter->rx_ring[n];
425 printk(KERN_INFO "%5d %5X %5X\n", n,
426 rx_ring->next_to_use, rx_ring->next_to_clean);
427 }
428
429 /* Print RX Rings */
430 if (!netif_msg_rx_status(adapter))
431 goto exit;
432
433 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
434
435 /* Advanced Receive Descriptor (Read) Format
436 * 63 1 0
437 * +-----------------------------------------------------+
438 * 0 | Packet Buffer Address [63:1] |A0/NSE|
439 * +----------------------------------------------+------+
440 * 8 | Header Buffer Address [63:1] | DD |
441 * +-----------------------------------------------------+
442 *
443 *
444 * Advanced Receive Descriptor (Write-Back) Format
445 *
446 * 63 48 47 32 31 30 21 20 16 15 4 3 0
447 * +------------------------------------------------------+
448 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
449 * | Checksum Ident | | | | Type | Type |
450 * +------------------------------------------------------+
451 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
452 * +------------------------------------------------------+
453 * 63 48 47 32 31 20 19 0
454 */
455 for (n = 0; n < adapter->num_rx_queues; n++) {
456 rx_ring = adapter->rx_ring[n];
457 printk(KERN_INFO "------------------------------------\n");
458 printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
459 printk(KERN_INFO "------------------------------------\n");
460 printk(KERN_INFO "R [desc] [ PktBuf A0] "
461 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
462 "<-- Adv Rx Read format\n");
463 printk(KERN_INFO "RWB[desc] [PcsmIpSHl PtRs] "
464 "[vl er S cks ln] ---------------- [bi->skb] "
465 "<-- Adv Rx Write-Back format\n");
466
467 for (i = 0; i < rx_ring->count; i++) {
468 rx_buffer_info = &rx_ring->rx_buffer_info[i];
469 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
470 u0 = (struct my_u0 *)rx_desc;
471 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
472 if (staterr & IXGBE_RXD_STAT_DD) {
473 /* Descriptor Done */
474 printk(KERN_INFO "RWB[0x%03X] %016llX "
475 "%016llX ---------------- %p", i,
476 le64_to_cpu(u0->a),
477 le64_to_cpu(u0->b),
478 rx_buffer_info->skb);
479 } else {
480 printk(KERN_INFO "R [0x%03X] %016llX "
481 "%016llX %016llX %p", i,
482 le64_to_cpu(u0->a),
483 le64_to_cpu(u0->b),
484 (u64)rx_buffer_info->dma,
485 rx_buffer_info->skb);
486
487 if (netif_msg_pktdata(adapter)) {
488 print_hex_dump(KERN_INFO, "",
489 DUMP_PREFIX_ADDRESS, 16, 1,
490 phys_to_virt(rx_buffer_info->dma),
491 rx_ring->rx_buf_len, true);
492
493 if (rx_ring->rx_buf_len
494 < IXGBE_RXBUFFER_2048)
495 print_hex_dump(KERN_INFO, "",
496 DUMP_PREFIX_ADDRESS, 16, 1,
497 phys_to_virt(
498 rx_buffer_info->page_dma +
499 rx_buffer_info->page_offset
500 ),
501 PAGE_SIZE/2, true);
502 }
503 }
504
505 if (i == rx_ring->next_to_use)
506 printk(KERN_CONT " NTU\n");
507 else if (i == rx_ring->next_to_clean)
508 printk(KERN_CONT " NTC\n");
509 else
510 printk(KERN_CONT "\n");
511
512 }
513 }
514
515 exit:
516 return;
517 }
518
519 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
520 {
521 u32 ctrl_ext;
522
523 /* Let firmware take over control of h/w */
524 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
525 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
526 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
527 }
528
529 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
530 {
531 u32 ctrl_ext;
532
533 /* Let firmware know the driver has taken over */
534 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
535 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
536 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
537 }
538
539 /*
540 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
541 * @adapter: pointer to adapter struct
542 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
543 * @queue: queue to map the corresponding interrupt to
544 * @msix_vector: the vector to map to the corresponding queue
545 *
546 */
547 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
548 u8 queue, u8 msix_vector)
549 {
550 u32 ivar, index;
551 struct ixgbe_hw *hw = &adapter->hw;
552 switch (hw->mac.type) {
553 case ixgbe_mac_82598EB:
554 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
555 if (direction == -1)
556 direction = 0;
557 index = (((direction * 64) + queue) >> 2) & 0x1F;
558 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
559 ivar &= ~(0xFF << (8 * (queue & 0x3)));
560 ivar |= (msix_vector << (8 * (queue & 0x3)));
561 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
562 break;
563 case ixgbe_mac_82599EB:
564 if (direction == -1) {
565 /* other causes */
566 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
567 index = ((queue & 1) * 8);
568 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
569 ivar &= ~(0xFF << index);
570 ivar |= (msix_vector << index);
571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
572 break;
573 } else {
574 /* tx or rx causes */
575 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
576 index = ((16 * (queue & 1)) + (8 * direction));
577 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
578 ivar &= ~(0xFF << index);
579 ivar |= (msix_vector << index);
580 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
581 break;
582 }
583 default:
584 break;
585 }
586 }
587
588 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
589 u64 qmask)
590 {
591 u32 mask;
592
593 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
594 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
595 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
596 } else {
597 mask = (qmask & 0xFFFFFFFF);
598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
599 mask = (qmask >> 32);
600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
601 }
602 }
603
604 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
605 struct ixgbe_tx_buffer
606 *tx_buffer_info)
607 {
608 if (tx_buffer_info->dma) {
609 if (tx_buffer_info->mapped_as_page)
610 dma_unmap_page(&adapter->pdev->dev,
611 tx_buffer_info->dma,
612 tx_buffer_info->length,
613 DMA_TO_DEVICE);
614 else
615 dma_unmap_single(&adapter->pdev->dev,
616 tx_buffer_info->dma,
617 tx_buffer_info->length,
618 DMA_TO_DEVICE);
619 tx_buffer_info->dma = 0;
620 }
621 if (tx_buffer_info->skb) {
622 dev_kfree_skb_any(tx_buffer_info->skb);
623 tx_buffer_info->skb = NULL;
624 }
625 tx_buffer_info->time_stamp = 0;
626 /* tx_buffer_info must be completely set up in the transmit path */
627 }
628
629 /**
630 * ixgbe_tx_xon_state - check the tx ring xon state
631 * @adapter: the ixgbe adapter
632 * @tx_ring: the corresponding tx_ring
633 *
634 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
635 * corresponding TC of this tx_ring when checking TFCS.
636 *
637 * Returns : true if in xon state (currently not paused)
638 */
639 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
640 struct ixgbe_ring *tx_ring)
641 {
642 u32 txoff = IXGBE_TFCS_TXOFF;
643
644 #ifdef CONFIG_IXGBE_DCB
645 if (adapter->dcb_cfg.pfc_mode_enable) {
646 int tc;
647 int reg_idx = tx_ring->reg_idx;
648 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
649
650 switch (adapter->hw.mac.type) {
651 case ixgbe_mac_82598EB:
652 tc = reg_idx >> 2;
653 txoff = IXGBE_TFCS_TXOFF0;
654 break;
655 case ixgbe_mac_82599EB:
656 tc = 0;
657 txoff = IXGBE_TFCS_TXOFF;
658 if (dcb_i == 8) {
659 /* TC0, TC1 */
660 tc = reg_idx >> 5;
661 if (tc == 2) /* TC2, TC3 */
662 tc += (reg_idx - 64) >> 4;
663 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
664 tc += 1 + ((reg_idx - 96) >> 3);
665 } else if (dcb_i == 4) {
666 /* TC0, TC1 */
667 tc = reg_idx >> 6;
668 if (tc == 1) {
669 tc += (reg_idx - 64) >> 5;
670 if (tc == 2) /* TC2, TC3 */
671 tc += (reg_idx - 96) >> 4;
672 }
673 }
674 break;
675 default:
676 tc = 0;
677 }
678 txoff <<= tc;
679 }
680 #endif
681 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
682 }
683
684 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
685 struct ixgbe_ring *tx_ring,
686 unsigned int eop)
687 {
688 struct ixgbe_hw *hw = &adapter->hw;
689
690 /* Detect a transmit hang in hardware, this serializes the
691 * check with the clearing of time_stamp and movement of eop */
692 adapter->detect_tx_hung = false;
693 if (tx_ring->tx_buffer_info[eop].time_stamp &&
694 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
695 ixgbe_tx_xon_state(adapter, tx_ring)) {
696 /* detected Tx unit hang */
697 union ixgbe_adv_tx_desc *tx_desc;
698 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
699 e_err(drv, "Detected Tx Unit Hang\n"
700 " Tx Queue <%d>\n"
701 " TDH, TDT <%x>, <%x>\n"
702 " next_to_use <%x>\n"
703 " next_to_clean <%x>\n"
704 "tx_buffer_info[next_to_clean]\n"
705 " time_stamp <%lx>\n"
706 " jiffies <%lx>\n",
707 tx_ring->queue_index,
708 IXGBE_READ_REG(hw, tx_ring->head),
709 IXGBE_READ_REG(hw, tx_ring->tail),
710 tx_ring->next_to_use, eop,
711 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
712 return true;
713 }
714
715 return false;
716 }
717
718 #define IXGBE_MAX_TXD_PWR 14
719 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
720
721 /* Tx Descriptors needed, worst case */
722 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
723 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
724 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
725 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
726
727 static void ixgbe_tx_timeout(struct net_device *netdev);
728
729 /**
730 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
731 * @q_vector: structure containing interrupt and ring information
732 * @tx_ring: tx ring to clean
733 **/
734 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
735 struct ixgbe_ring *tx_ring)
736 {
737 struct ixgbe_adapter *adapter = q_vector->adapter;
738 struct net_device *netdev = adapter->netdev;
739 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
740 struct ixgbe_tx_buffer *tx_buffer_info;
741 unsigned int i, eop, count = 0;
742 unsigned int total_bytes = 0, total_packets = 0;
743
744 i = tx_ring->next_to_clean;
745 eop = tx_ring->tx_buffer_info[i].next_to_watch;
746 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
747
748 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
749 (count < tx_ring->work_limit)) {
750 bool cleaned = false;
751 rmb(); /* read buffer_info after eop_desc */
752 for ( ; !cleaned; count++) {
753 struct sk_buff *skb;
754 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
755 tx_buffer_info = &tx_ring->tx_buffer_info[i];
756 cleaned = (i == eop);
757 skb = tx_buffer_info->skb;
758
759 if (cleaned && skb) {
760 unsigned int segs, bytecount;
761 unsigned int hlen = skb_headlen(skb);
762
763 /* gso_segs is currently only valid for tcp */
764 segs = skb_shinfo(skb)->gso_segs ?: 1;
765 #ifdef IXGBE_FCOE
766 /* adjust for FCoE Sequence Offload */
767 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
768 && (skb->protocol == htons(ETH_P_FCOE)) &&
769 skb_is_gso(skb)) {
770 hlen = skb_transport_offset(skb) +
771 sizeof(struct fc_frame_header) +
772 sizeof(struct fcoe_crc_eof);
773 segs = DIV_ROUND_UP(skb->len - hlen,
774 skb_shinfo(skb)->gso_size);
775 }
776 #endif /* IXGBE_FCOE */
777 /* multiply data chunks by size of headers */
778 bytecount = ((segs - 1) * hlen) + skb->len;
779 total_packets += segs;
780 total_bytes += bytecount;
781 }
782
783 ixgbe_unmap_and_free_tx_resource(adapter,
784 tx_buffer_info);
785
786 tx_desc->wb.status = 0;
787
788 i++;
789 if (i == tx_ring->count)
790 i = 0;
791 }
792
793 eop = tx_ring->tx_buffer_info[i].next_to_watch;
794 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
795 }
796
797 tx_ring->next_to_clean = i;
798
799 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
800 if (unlikely(count && netif_carrier_ok(netdev) &&
801 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
802 /* Make sure that anybody stopping the queue after this
803 * sees the new next_to_clean.
804 */
805 smp_mb();
806 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
807 !test_bit(__IXGBE_DOWN, &adapter->state)) {
808 netif_wake_subqueue(netdev, tx_ring->queue_index);
809 ++tx_ring->restart_queue;
810 }
811 }
812
813 if (adapter->detect_tx_hung) {
814 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
815 /* schedule immediate reset if we believe we hung */
816 e_info(probe, "tx hang %d detected, resetting "
817 "adapter\n", adapter->tx_timeout_count + 1);
818 ixgbe_tx_timeout(adapter->netdev);
819 }
820 }
821
822 /* re-arm the interrupt */
823 if (count >= tx_ring->work_limit)
824 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
825
826 tx_ring->total_bytes += total_bytes;
827 tx_ring->total_packets += total_packets;
828 tx_ring->stats.packets += total_packets;
829 tx_ring->stats.bytes += total_bytes;
830 return (count < tx_ring->work_limit);
831 }
832
833 #ifdef CONFIG_IXGBE_DCA
834 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
835 struct ixgbe_ring *rx_ring)
836 {
837 u32 rxctrl;
838 int cpu = get_cpu();
839 int q = rx_ring->reg_idx;
840
841 if (rx_ring->cpu != cpu) {
842 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
843 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
844 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
845 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
846 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
847 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
848 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
849 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
850 }
851 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
852 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
853 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
854 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
855 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
856 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
857 rx_ring->cpu = cpu;
858 }
859 put_cpu();
860 }
861
862 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
863 struct ixgbe_ring *tx_ring)
864 {
865 u32 txctrl;
866 int cpu = get_cpu();
867 int q = tx_ring->reg_idx;
868 struct ixgbe_hw *hw = &adapter->hw;
869
870 if (tx_ring->cpu != cpu) {
871 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
872 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
873 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
874 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
875 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
876 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
877 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
878 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
879 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
880 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
881 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
882 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
883 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
884 }
885 tx_ring->cpu = cpu;
886 }
887 put_cpu();
888 }
889
890 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
891 {
892 int i;
893
894 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
895 return;
896
897 /* always use CB2 mode, difference is masked in the CB driver */
898 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
899
900 for (i = 0; i < adapter->num_tx_queues; i++) {
901 adapter->tx_ring[i]->cpu = -1;
902 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
903 }
904 for (i = 0; i < adapter->num_rx_queues; i++) {
905 adapter->rx_ring[i]->cpu = -1;
906 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
907 }
908 }
909
910 static int __ixgbe_notify_dca(struct device *dev, void *data)
911 {
912 struct net_device *netdev = dev_get_drvdata(dev);
913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
914 unsigned long event = *(unsigned long *)data;
915
916 switch (event) {
917 case DCA_PROVIDER_ADD:
918 /* if we're already enabled, don't do it again */
919 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
920 break;
921 if (dca_add_requester(dev) == 0) {
922 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
923 ixgbe_setup_dca(adapter);
924 break;
925 }
926 /* Fall Through since DCA is disabled. */
927 case DCA_PROVIDER_REMOVE:
928 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
929 dca_remove_requester(dev);
930 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
931 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
932 }
933 break;
934 }
935
936 return 0;
937 }
938
939 #endif /* CONFIG_IXGBE_DCA */
940 /**
941 * ixgbe_receive_skb - Send a completed packet up the stack
942 * @adapter: board private structure
943 * @skb: packet to send up
944 * @status: hardware indication of status of receive
945 * @rx_ring: rx descriptor ring (for a specific queue) to setup
946 * @rx_desc: rx descriptor
947 **/
948 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
949 struct sk_buff *skb, u8 status,
950 struct ixgbe_ring *ring,
951 union ixgbe_adv_rx_desc *rx_desc)
952 {
953 struct ixgbe_adapter *adapter = q_vector->adapter;
954 struct napi_struct *napi = &q_vector->napi;
955 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
956 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
957
958 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
959 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
960 vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
961 else
962 napi_gro_receive(napi, skb);
963 } else {
964 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
965 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
966 else
967 netif_rx(skb);
968 }
969 }
970
971 /**
972 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
973 * @adapter: address of board private structure
974 * @status_err: hardware indication of status of receive
975 * @skb: skb currently being received and modified
976 **/
977 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
978 union ixgbe_adv_rx_desc *rx_desc,
979 struct sk_buff *skb)
980 {
981 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
982
983 skb->ip_summed = CHECKSUM_NONE;
984
985 /* Rx csum disabled */
986 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
987 return;
988
989 /* if IP and error */
990 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
991 (status_err & IXGBE_RXDADV_ERR_IPE)) {
992 adapter->hw_csum_rx_error++;
993 return;
994 }
995
996 if (!(status_err & IXGBE_RXD_STAT_L4CS))
997 return;
998
999 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1000 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1001
1002 /*
1003 * 82599 errata, UDP frames with a 0 checksum can be marked as
1004 * checksum errors.
1005 */
1006 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1007 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1008 return;
1009
1010 adapter->hw_csum_rx_error++;
1011 return;
1012 }
1013
1014 /* It must be a TCP or UDP packet with a valid checksum */
1015 skb->ip_summed = CHECKSUM_UNNECESSARY;
1016 }
1017
1018 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1019 struct ixgbe_ring *rx_ring, u32 val)
1020 {
1021 /*
1022 * Force memory writes to complete before letting h/w
1023 * know there are new descriptors to fetch. (Only
1024 * applicable for weak-ordered memory model archs,
1025 * such as IA-64).
1026 */
1027 wmb();
1028 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1029 }
1030
1031 /**
1032 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033 * @adapter: address of board private structure
1034 **/
1035 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1036 struct ixgbe_ring *rx_ring,
1037 int cleaned_count)
1038 {
1039 struct net_device *netdev = adapter->netdev;
1040 struct pci_dev *pdev = adapter->pdev;
1041 union ixgbe_adv_rx_desc *rx_desc;
1042 struct ixgbe_rx_buffer *bi;
1043 unsigned int i;
1044 unsigned int bufsz = rx_ring->rx_buf_len;
1045
1046 i = rx_ring->next_to_use;
1047 bi = &rx_ring->rx_buffer_info[i];
1048
1049 while (cleaned_count--) {
1050 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1051
1052 if (!bi->page_dma &&
1053 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1054 if (!bi->page) {
1055 bi->page = netdev_alloc_page(netdev);
1056 if (!bi->page) {
1057 adapter->alloc_rx_page_failed++;
1058 goto no_buffers;
1059 }
1060 bi->page_offset = 0;
1061 } else {
1062 /* use a half page if we're re-using */
1063 bi->page_offset ^= (PAGE_SIZE / 2);
1064 }
1065
1066 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1067 bi->page_offset,
1068 (PAGE_SIZE / 2),
1069 DMA_FROM_DEVICE);
1070 }
1071
1072 if (!bi->skb) {
1073 struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1074 bufsz);
1075 bi->skb = skb;
1076
1077 if (!skb) {
1078 adapter->alloc_rx_buff_failed++;
1079 goto no_buffers;
1080 }
1081 /* initialize queue mapping */
1082 skb_record_rx_queue(skb, rx_ring->queue_index);
1083 }
1084
1085 if (!bi->dma) {
1086 bi->dma = dma_map_single(&pdev->dev,
1087 bi->skb->data,
1088 rx_ring->rx_buf_len,
1089 DMA_FROM_DEVICE);
1090 }
1091 /* Refresh the desc even if buffer_addrs didn't change because
1092 * each write-back erases this info. */
1093 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1094 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1095 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1096 } else {
1097 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1098 }
1099
1100 i++;
1101 if (i == rx_ring->count)
1102 i = 0;
1103 bi = &rx_ring->rx_buffer_info[i];
1104 }
1105
1106 no_buffers:
1107 if (rx_ring->next_to_use != i) {
1108 rx_ring->next_to_use = i;
1109 if (i-- == 0)
1110 i = (rx_ring->count - 1);
1111
1112 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1113 }
1114 }
1115
1116 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1117 {
1118 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1119 }
1120
1121 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1122 {
1123 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1124 }
1125
1126 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1127 {
1128 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1129 IXGBE_RXDADV_RSCCNT_MASK) >>
1130 IXGBE_RXDADV_RSCCNT_SHIFT;
1131 }
1132
1133 /**
1134 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1135 * @skb: pointer to the last skb in the rsc queue
1136 * @count: pointer to number of packets coalesced in this context
1137 *
1138 * This function changes a queue full of hw rsc buffers into a completed
1139 * packet. It uses the ->prev pointers to find the first packet and then
1140 * turns it into the frag list owner.
1141 **/
1142 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1143 u64 *count)
1144 {
1145 unsigned int frag_list_size = 0;
1146
1147 while (skb->prev) {
1148 struct sk_buff *prev = skb->prev;
1149 frag_list_size += skb->len;
1150 skb->prev = NULL;
1151 skb = prev;
1152 *count += 1;
1153 }
1154
1155 skb_shinfo(skb)->frag_list = skb->next;
1156 skb->next = NULL;
1157 skb->len += frag_list_size;
1158 skb->data_len += frag_list_size;
1159 skb->truesize += frag_list_size;
1160 return skb;
1161 }
1162
1163 struct ixgbe_rsc_cb {
1164 dma_addr_t dma;
1165 bool delay_unmap;
1166 };
1167
1168 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169
1170 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1171 struct ixgbe_ring *rx_ring,
1172 int *work_done, int work_to_do)
1173 {
1174 struct ixgbe_adapter *adapter = q_vector->adapter;
1175 struct net_device *netdev = adapter->netdev;
1176 struct pci_dev *pdev = adapter->pdev;
1177 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1178 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1179 struct sk_buff *skb;
1180 unsigned int i, rsc_count = 0;
1181 u32 len, staterr;
1182 u16 hdr_info;
1183 bool cleaned = false;
1184 int cleaned_count = 0;
1185 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1186 #ifdef IXGBE_FCOE
1187 int ddp_bytes = 0;
1188 #endif /* IXGBE_FCOE */
1189
1190 i = rx_ring->next_to_clean;
1191 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
1192 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1193 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1194
1195 while (staterr & IXGBE_RXD_STAT_DD) {
1196 u32 upper_len = 0;
1197 if (*work_done >= work_to_do)
1198 break;
1199 (*work_done)++;
1200
1201 rmb(); /* read descriptor and rx_buffer_info after status DD */
1202 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1203 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1204 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1205 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1206 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1207 if ((len > IXGBE_RX_HDR_SIZE) ||
1208 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1209 len = IXGBE_RX_HDR_SIZE;
1210 } else {
1211 len = le16_to_cpu(rx_desc->wb.upper.length);
1212 }
1213
1214 cleaned = true;
1215 skb = rx_buffer_info->skb;
1216 prefetch(skb->data);
1217 rx_buffer_info->skb = NULL;
1218
1219 if (rx_buffer_info->dma) {
1220 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1221 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1222 (!(skb->prev))) {
1223 /*
1224 * When HWRSC is enabled, delay unmapping
1225 * of the first packet. It carries the
1226 * header information, HW may still
1227 * access the header after the writeback.
1228 * Only unmap it when EOP is reached
1229 */
1230 IXGBE_RSC_CB(skb)->delay_unmap = true;
1231 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1232 } else {
1233 dma_unmap_single(&pdev->dev,
1234 rx_buffer_info->dma,
1235 rx_ring->rx_buf_len,
1236 DMA_FROM_DEVICE);
1237 }
1238 rx_buffer_info->dma = 0;
1239 skb_put(skb, len);
1240 }
1241
1242 if (upper_len) {
1243 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1244 PAGE_SIZE / 2, DMA_FROM_DEVICE);
1245 rx_buffer_info->page_dma = 0;
1246 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1247 rx_buffer_info->page,
1248 rx_buffer_info->page_offset,
1249 upper_len);
1250
1251 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1252 (page_count(rx_buffer_info->page) != 1))
1253 rx_buffer_info->page = NULL;
1254 else
1255 get_page(rx_buffer_info->page);
1256
1257 skb->len += upper_len;
1258 skb->data_len += upper_len;
1259 skb->truesize += upper_len;
1260 }
1261
1262 i++;
1263 if (i == rx_ring->count)
1264 i = 0;
1265
1266 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
1267 prefetch(next_rxd);
1268 cleaned_count++;
1269
1270 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1271 rsc_count = ixgbe_get_rsc_count(rx_desc);
1272
1273 if (rsc_count) {
1274 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1275 IXGBE_RXDADV_NEXTP_SHIFT;
1276 next_buffer = &rx_ring->rx_buffer_info[nextp];
1277 } else {
1278 next_buffer = &rx_ring->rx_buffer_info[i];
1279 }
1280
1281 if (staterr & IXGBE_RXD_STAT_EOP) {
1282 if (skb->prev)
1283 skb = ixgbe_transform_rsc_queue(skb, &(rx_ring->rsc_count));
1284 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1285 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1286 dma_unmap_single(&pdev->dev,
1287 IXGBE_RSC_CB(skb)->dma,
1288 rx_ring->rx_buf_len,
1289 DMA_FROM_DEVICE);
1290 IXGBE_RSC_CB(skb)->dma = 0;
1291 IXGBE_RSC_CB(skb)->delay_unmap = false;
1292 }
1293 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1294 rx_ring->rsc_count += skb_shinfo(skb)->nr_frags;
1295 else
1296 rx_ring->rsc_count++;
1297 rx_ring->rsc_flush++;
1298 }
1299 rx_ring->stats.packets++;
1300 rx_ring->stats.bytes += skb->len;
1301 } else {
1302 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1303 rx_buffer_info->skb = next_buffer->skb;
1304 rx_buffer_info->dma = next_buffer->dma;
1305 next_buffer->skb = skb;
1306 next_buffer->dma = 0;
1307 } else {
1308 skb->next = next_buffer->skb;
1309 skb->next->prev = skb;
1310 }
1311 rx_ring->non_eop_descs++;
1312 goto next_desc;
1313 }
1314
1315 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1316 dev_kfree_skb_irq(skb);
1317 goto next_desc;
1318 }
1319
1320 ixgbe_rx_checksum(adapter, rx_desc, skb);
1321
1322 /* probably a little skewed due to removing CRC */
1323 total_rx_bytes += skb->len;
1324 total_rx_packets++;
1325
1326 skb->protocol = eth_type_trans(skb, adapter->netdev);
1327 #ifdef IXGBE_FCOE
1328 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1329 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1330 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1331 if (!ddp_bytes)
1332 goto next_desc;
1333 }
1334 #endif /* IXGBE_FCOE */
1335 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1336
1337 next_desc:
1338 rx_desc->wb.upper.status_error = 0;
1339
1340 /* return some buffers to hardware, one at a time is too slow */
1341 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1342 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1343 cleaned_count = 0;
1344 }
1345
1346 /* use prefetched values */
1347 rx_desc = next_rxd;
1348 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1349
1350 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1351 }
1352
1353 rx_ring->next_to_clean = i;
1354 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1355
1356 if (cleaned_count)
1357 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1358
1359 #ifdef IXGBE_FCOE
1360 /* include DDPed FCoE data */
1361 if (ddp_bytes > 0) {
1362 unsigned int mss;
1363
1364 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1365 sizeof(struct fc_frame_header) -
1366 sizeof(struct fcoe_crc_eof);
1367 if (mss > 512)
1368 mss &= ~511;
1369 total_rx_bytes += ddp_bytes;
1370 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1371 }
1372 #endif /* IXGBE_FCOE */
1373
1374 rx_ring->total_packets += total_rx_packets;
1375 rx_ring->total_bytes += total_rx_bytes;
1376 netdev->stats.rx_bytes += total_rx_bytes;
1377 netdev->stats.rx_packets += total_rx_packets;
1378
1379 return cleaned;
1380 }
1381
1382 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1383 /**
1384 * ixgbe_configure_msix - Configure MSI-X hardware
1385 * @adapter: board private structure
1386 *
1387 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388 * interrupts.
1389 **/
1390 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391 {
1392 struct ixgbe_q_vector *q_vector;
1393 int i, j, q_vectors, v_idx, r_idx;
1394 u32 mask;
1395
1396 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1397
1398 /*
1399 * Populate the IVAR table and set the ITR values to the
1400 * corresponding register.
1401 */
1402 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1403 q_vector = adapter->q_vector[v_idx];
1404 /* XXX for_each_set_bit(...) */
1405 r_idx = find_first_bit(q_vector->rxr_idx,
1406 adapter->num_rx_queues);
1407
1408 for (i = 0; i < q_vector->rxr_count; i++) {
1409 j = adapter->rx_ring[r_idx]->reg_idx;
1410 ixgbe_set_ivar(adapter, 0, j, v_idx);
1411 r_idx = find_next_bit(q_vector->rxr_idx,
1412 adapter->num_rx_queues,
1413 r_idx + 1);
1414 }
1415 r_idx = find_first_bit(q_vector->txr_idx,
1416 adapter->num_tx_queues);
1417
1418 for (i = 0; i < q_vector->txr_count; i++) {
1419 j = adapter->tx_ring[r_idx]->reg_idx;
1420 ixgbe_set_ivar(adapter, 1, j, v_idx);
1421 r_idx = find_next_bit(q_vector->txr_idx,
1422 adapter->num_tx_queues,
1423 r_idx + 1);
1424 }
1425
1426 if (q_vector->txr_count && !q_vector->rxr_count)
1427 /* tx only */
1428 q_vector->eitr = adapter->tx_eitr_param;
1429 else if (q_vector->rxr_count)
1430 /* rx or mixed */
1431 q_vector->eitr = adapter->rx_eitr_param;
1432
1433 ixgbe_write_eitr(q_vector);
1434 }
1435
1436 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1437 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1438 v_idx);
1439 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1440 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1441 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1442
1443 /* set up to autoclear timer, and the vectors */
1444 mask = IXGBE_EIMS_ENABLE_MASK;
1445 if (adapter->num_vfs)
1446 mask &= ~(IXGBE_EIMS_OTHER |
1447 IXGBE_EIMS_MAILBOX |
1448 IXGBE_EIMS_LSC);
1449 else
1450 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1451 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1452 }
1453
1454 enum latency_range {
1455 lowest_latency = 0,
1456 low_latency = 1,
1457 bulk_latency = 2,
1458 latency_invalid = 255
1459 };
1460
1461 /**
1462 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1463 * @adapter: pointer to adapter
1464 * @eitr: eitr setting (ints per sec) to give last timeslice
1465 * @itr_setting: current throttle rate in ints/second
1466 * @packets: the number of packets during this measurement interval
1467 * @bytes: the number of bytes during this measurement interval
1468 *
1469 * Stores a new ITR value based on packets and byte
1470 * counts during the last interrupt. The advantage of per interrupt
1471 * computation is faster updates and more accurate ITR for the current
1472 * traffic pattern. Constants in this function were computed
1473 * based on theoretical maximum wire speed and thresholds were set based
1474 * on testing data as well as attempting to minimize response time
1475 * while increasing bulk throughput.
1476 * this functionality is controlled by the InterruptThrottleRate module
1477 * parameter (see ixgbe_param.c)
1478 **/
1479 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1480 u32 eitr, u8 itr_setting,
1481 int packets, int bytes)
1482 {
1483 unsigned int retval = itr_setting;
1484 u32 timepassed_us;
1485 u64 bytes_perint;
1486
1487 if (packets == 0)
1488 goto update_itr_done;
1489
1490
1491 /* simple throttlerate management
1492 * 0-20MB/s lowest (100000 ints/s)
1493 * 20-100MB/s low (20000 ints/s)
1494 * 100-1249MB/s bulk (8000 ints/s)
1495 */
1496 /* what was last interrupt timeslice? */
1497 timepassed_us = 1000000/eitr;
1498 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1499
1500 switch (itr_setting) {
1501 case lowest_latency:
1502 if (bytes_perint > adapter->eitr_low)
1503 retval = low_latency;
1504 break;
1505 case low_latency:
1506 if (bytes_perint > adapter->eitr_high)
1507 retval = bulk_latency;
1508 else if (bytes_perint <= adapter->eitr_low)
1509 retval = lowest_latency;
1510 break;
1511 case bulk_latency:
1512 if (bytes_perint <= adapter->eitr_high)
1513 retval = low_latency;
1514 break;
1515 }
1516
1517 update_itr_done:
1518 return retval;
1519 }
1520
1521 /**
1522 * ixgbe_write_eitr - write EITR register in hardware specific way
1523 * @q_vector: structure containing interrupt and ring information
1524 *
1525 * This function is made to be called by ethtool and by the driver
1526 * when it needs to update EITR registers at runtime. Hardware
1527 * specific quirks/differences are taken care of here.
1528 */
1529 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1530 {
1531 struct ixgbe_adapter *adapter = q_vector->adapter;
1532 struct ixgbe_hw *hw = &adapter->hw;
1533 int v_idx = q_vector->v_idx;
1534 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1535
1536 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1537 /* must write high and low 16 bits to reset counter */
1538 itr_reg |= (itr_reg << 16);
1539 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1540 /*
1541 * 82599 can support a value of zero, so allow it for
1542 * max interrupt rate, but there is an errata where it can
1543 * not be zero with RSC
1544 */
1545 if (itr_reg == 8 &&
1546 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1547 itr_reg = 0;
1548
1549 /*
1550 * set the WDIS bit to not clear the timer bits and cause an
1551 * immediate assertion of the interrupt
1552 */
1553 itr_reg |= IXGBE_EITR_CNT_WDIS;
1554 }
1555 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1556 }
1557
1558 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1559 {
1560 struct ixgbe_adapter *adapter = q_vector->adapter;
1561 u32 new_itr;
1562 u8 current_itr, ret_itr;
1563 int i, r_idx;
1564 struct ixgbe_ring *rx_ring, *tx_ring;
1565
1566 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1567 for (i = 0; i < q_vector->txr_count; i++) {
1568 tx_ring = adapter->tx_ring[r_idx];
1569 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1570 q_vector->tx_itr,
1571 tx_ring->total_packets,
1572 tx_ring->total_bytes);
1573 /* if the result for this queue would decrease interrupt
1574 * rate for this vector then use that result */
1575 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1576 q_vector->tx_itr - 1 : ret_itr);
1577 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1578 r_idx + 1);
1579 }
1580
1581 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1582 for (i = 0; i < q_vector->rxr_count; i++) {
1583 rx_ring = adapter->rx_ring[r_idx];
1584 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1585 q_vector->rx_itr,
1586 rx_ring->total_packets,
1587 rx_ring->total_bytes);
1588 /* if the result for this queue would decrease interrupt
1589 * rate for this vector then use that result */
1590 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1591 q_vector->rx_itr - 1 : ret_itr);
1592 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1593 r_idx + 1);
1594 }
1595
1596 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1597
1598 switch (current_itr) {
1599 /* counts and packets in update_itr are dependent on these numbers */
1600 case lowest_latency:
1601 new_itr = 100000;
1602 break;
1603 case low_latency:
1604 new_itr = 20000; /* aka hwitr = ~200 */
1605 break;
1606 case bulk_latency:
1607 default:
1608 new_itr = 8000;
1609 break;
1610 }
1611
1612 if (new_itr != q_vector->eitr) {
1613 /* do an exponential smoothing */
1614 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1615
1616 /* save the algorithm value here, not the smoothed one */
1617 q_vector->eitr = new_itr;
1618
1619 ixgbe_write_eitr(q_vector);
1620 }
1621 }
1622
1623 /**
1624 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1625 * @work: pointer to work_struct containing our data
1626 **/
1627 static void ixgbe_check_overtemp_task(struct work_struct *work)
1628 {
1629 struct ixgbe_adapter *adapter = container_of(work,
1630 struct ixgbe_adapter,
1631 check_overtemp_task);
1632 struct ixgbe_hw *hw = &adapter->hw;
1633 u32 eicr = adapter->interrupt_event;
1634
1635 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
1636 switch (hw->device_id) {
1637 case IXGBE_DEV_ID_82599_T3_LOM: {
1638 u32 autoneg;
1639 bool link_up = false;
1640
1641 if (hw->mac.ops.check_link)
1642 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1643
1644 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1645 (eicr & IXGBE_EICR_LSC))
1646 /* Check if this is due to overtemp */
1647 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1648 break;
1649 }
1650 return;
1651 default:
1652 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1653 return;
1654 break;
1655 }
1656 e_crit(drv, "Network adapter has been stopped because it has "
1657 "over heated. Restart the computer. If the problem "
1658 "persists, power off the system and replace the "
1659 "adapter\n");
1660 /* write to clear the interrupt */
1661 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1662 }
1663 }
1664
1665 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1666 {
1667 struct ixgbe_hw *hw = &adapter->hw;
1668
1669 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1670 (eicr & IXGBE_EICR_GPI_SDP1)) {
1671 e_crit(probe, "Fan has stopped, replace the adapter\n");
1672 /* write to clear the interrupt */
1673 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1674 }
1675 }
1676
1677 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1678 {
1679 struct ixgbe_hw *hw = &adapter->hw;
1680
1681 if (eicr & IXGBE_EICR_GPI_SDP1) {
1682 /* Clear the interrupt */
1683 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1684 schedule_work(&adapter->multispeed_fiber_task);
1685 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1686 /* Clear the interrupt */
1687 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1688 schedule_work(&adapter->sfp_config_module_task);
1689 } else {
1690 /* Interrupt isn't for us... */
1691 return;
1692 }
1693 }
1694
1695 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1696 {
1697 struct ixgbe_hw *hw = &adapter->hw;
1698
1699 adapter->lsc_int++;
1700 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1701 adapter->link_check_timeout = jiffies;
1702 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1703 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1704 IXGBE_WRITE_FLUSH(hw);
1705 schedule_work(&adapter->watchdog_task);
1706 }
1707 }
1708
1709 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1710 {
1711 struct net_device *netdev = data;
1712 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713 struct ixgbe_hw *hw = &adapter->hw;
1714 u32 eicr;
1715
1716 /*
1717 * Workaround for Silicon errata. Use clear-by-write instead
1718 * of clear-by-read. Reading with EICS will return the
1719 * interrupt causes without clearing, which later be done
1720 * with the write to EICR.
1721 */
1722 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1723 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1724
1725 if (eicr & IXGBE_EICR_LSC)
1726 ixgbe_check_lsc(adapter);
1727
1728 if (eicr & IXGBE_EICR_MAILBOX)
1729 ixgbe_msg_task(adapter);
1730
1731 if (hw->mac.type == ixgbe_mac_82598EB)
1732 ixgbe_check_fan_failure(adapter, eicr);
1733
1734 if (hw->mac.type == ixgbe_mac_82599EB) {
1735 ixgbe_check_sfp_event(adapter, eicr);
1736 adapter->interrupt_event = eicr;
1737 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1738 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1739 schedule_work(&adapter->check_overtemp_task);
1740
1741 /* Handle Flow Director Full threshold interrupt */
1742 if (eicr & IXGBE_EICR_FLOW_DIR) {
1743 int i;
1744 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1745 /* Disable transmits before FDIR Re-initialization */
1746 netif_tx_stop_all_queues(netdev);
1747 for (i = 0; i < adapter->num_tx_queues; i++) {
1748 struct ixgbe_ring *tx_ring =
1749 adapter->tx_ring[i];
1750 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1751 &tx_ring->reinit_state))
1752 schedule_work(&adapter->fdir_reinit_task);
1753 }
1754 }
1755 }
1756 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1757 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1758
1759 return IRQ_HANDLED;
1760 }
1761
1762 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1763 u64 qmask)
1764 {
1765 u32 mask;
1766
1767 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1768 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1769 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1770 } else {
1771 mask = (qmask & 0xFFFFFFFF);
1772 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1773 mask = (qmask >> 32);
1774 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1775 }
1776 /* skip the flush */
1777 }
1778
1779 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1780 u64 qmask)
1781 {
1782 u32 mask;
1783
1784 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1785 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1786 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1787 } else {
1788 mask = (qmask & 0xFFFFFFFF);
1789 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1790 mask = (qmask >> 32);
1791 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1792 }
1793 /* skip the flush */
1794 }
1795
1796 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1797 {
1798 struct ixgbe_q_vector *q_vector = data;
1799 struct ixgbe_adapter *adapter = q_vector->adapter;
1800 struct ixgbe_ring *tx_ring;
1801 int i, r_idx;
1802
1803 if (!q_vector->txr_count)
1804 return IRQ_HANDLED;
1805
1806 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1807 for (i = 0; i < q_vector->txr_count; i++) {
1808 tx_ring = adapter->tx_ring[r_idx];
1809 tx_ring->total_bytes = 0;
1810 tx_ring->total_packets = 0;
1811 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1812 r_idx + 1);
1813 }
1814
1815 /* EIAM disabled interrupts (on this vector) for us */
1816 napi_schedule(&q_vector->napi);
1817
1818 return IRQ_HANDLED;
1819 }
1820
1821 /**
1822 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1823 * @irq: unused
1824 * @data: pointer to our q_vector struct for this interrupt vector
1825 **/
1826 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1827 {
1828 struct ixgbe_q_vector *q_vector = data;
1829 struct ixgbe_adapter *adapter = q_vector->adapter;
1830 struct ixgbe_ring *rx_ring;
1831 int r_idx;
1832 int i;
1833
1834 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1835 for (i = 0; i < q_vector->rxr_count; i++) {
1836 rx_ring = adapter->rx_ring[r_idx];
1837 rx_ring->total_bytes = 0;
1838 rx_ring->total_packets = 0;
1839 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1840 r_idx + 1);
1841 }
1842
1843 if (!q_vector->rxr_count)
1844 return IRQ_HANDLED;
1845
1846 /* disable interrupts on this vector only */
1847 /* EIAM disabled interrupts (on this vector) for us */
1848 napi_schedule(&q_vector->napi);
1849
1850 return IRQ_HANDLED;
1851 }
1852
1853 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1854 {
1855 struct ixgbe_q_vector *q_vector = data;
1856 struct ixgbe_adapter *adapter = q_vector->adapter;
1857 struct ixgbe_ring *ring;
1858 int r_idx;
1859 int i;
1860
1861 if (!q_vector->txr_count && !q_vector->rxr_count)
1862 return IRQ_HANDLED;
1863
1864 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1865 for (i = 0; i < q_vector->txr_count; i++) {
1866 ring = adapter->tx_ring[r_idx];
1867 ring->total_bytes = 0;
1868 ring->total_packets = 0;
1869 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1870 r_idx + 1);
1871 }
1872
1873 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1874 for (i = 0; i < q_vector->rxr_count; i++) {
1875 ring = adapter->rx_ring[r_idx];
1876 ring->total_bytes = 0;
1877 ring->total_packets = 0;
1878 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1879 r_idx + 1);
1880 }
1881
1882 /* EIAM disabled interrupts (on this vector) for us */
1883 napi_schedule(&q_vector->napi);
1884
1885 return IRQ_HANDLED;
1886 }
1887
1888 /**
1889 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1890 * @napi: napi struct with our devices info in it
1891 * @budget: amount of work driver is allowed to do this pass, in packets
1892 *
1893 * This function is optimized for cleaning one queue only on a single
1894 * q_vector!!!
1895 **/
1896 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1897 {
1898 struct ixgbe_q_vector *q_vector =
1899 container_of(napi, struct ixgbe_q_vector, napi);
1900 struct ixgbe_adapter *adapter = q_vector->adapter;
1901 struct ixgbe_ring *rx_ring = NULL;
1902 int work_done = 0;
1903 long r_idx;
1904
1905 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1906 rx_ring = adapter->rx_ring[r_idx];
1907 #ifdef CONFIG_IXGBE_DCA
1908 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1909 ixgbe_update_rx_dca(adapter, rx_ring);
1910 #endif
1911
1912 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1913
1914 /* If all Rx work done, exit the polling mode */
1915 if (work_done < budget) {
1916 napi_complete(napi);
1917 if (adapter->rx_itr_setting & 1)
1918 ixgbe_set_itr_msix(q_vector);
1919 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1920 ixgbe_irq_enable_queues(adapter,
1921 ((u64)1 << q_vector->v_idx));
1922 }
1923
1924 return work_done;
1925 }
1926
1927 /**
1928 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1929 * @napi: napi struct with our devices info in it
1930 * @budget: amount of work driver is allowed to do this pass, in packets
1931 *
1932 * This function will clean more than one rx queue associated with a
1933 * q_vector.
1934 **/
1935 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1936 {
1937 struct ixgbe_q_vector *q_vector =
1938 container_of(napi, struct ixgbe_q_vector, napi);
1939 struct ixgbe_adapter *adapter = q_vector->adapter;
1940 struct ixgbe_ring *ring = NULL;
1941 int work_done = 0, i;
1942 long r_idx;
1943 bool tx_clean_complete = true;
1944
1945 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1946 for (i = 0; i < q_vector->txr_count; i++) {
1947 ring = adapter->tx_ring[r_idx];
1948 #ifdef CONFIG_IXGBE_DCA
1949 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1950 ixgbe_update_tx_dca(adapter, ring);
1951 #endif
1952 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1953 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1954 r_idx + 1);
1955 }
1956
1957 /* attempt to distribute budget to each queue fairly, but don't allow
1958 * the budget to go below 1 because we'll exit polling */
1959 budget /= (q_vector->rxr_count ?: 1);
1960 budget = max(budget, 1);
1961 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1962 for (i = 0; i < q_vector->rxr_count; i++) {
1963 ring = adapter->rx_ring[r_idx];
1964 #ifdef CONFIG_IXGBE_DCA
1965 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1966 ixgbe_update_rx_dca(adapter, ring);
1967 #endif
1968 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1969 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1970 r_idx + 1);
1971 }
1972
1973 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1974 ring = adapter->rx_ring[r_idx];
1975 /* If all Rx work done, exit the polling mode */
1976 if (work_done < budget) {
1977 napi_complete(napi);
1978 if (adapter->rx_itr_setting & 1)
1979 ixgbe_set_itr_msix(q_vector);
1980 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1981 ixgbe_irq_enable_queues(adapter,
1982 ((u64)1 << q_vector->v_idx));
1983 return 0;
1984 }
1985
1986 return work_done;
1987 }
1988
1989 /**
1990 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1991 * @napi: napi struct with our devices info in it
1992 * @budget: amount of work driver is allowed to do this pass, in packets
1993 *
1994 * This function is optimized for cleaning one queue only on a single
1995 * q_vector!!!
1996 **/
1997 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1998 {
1999 struct ixgbe_q_vector *q_vector =
2000 container_of(napi, struct ixgbe_q_vector, napi);
2001 struct ixgbe_adapter *adapter = q_vector->adapter;
2002 struct ixgbe_ring *tx_ring = NULL;
2003 int work_done = 0;
2004 long r_idx;
2005
2006 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2007 tx_ring = adapter->tx_ring[r_idx];
2008 #ifdef CONFIG_IXGBE_DCA
2009 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2010 ixgbe_update_tx_dca(adapter, tx_ring);
2011 #endif
2012
2013 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2014 work_done = budget;
2015
2016 /* If all Tx work done, exit the polling mode */
2017 if (work_done < budget) {
2018 napi_complete(napi);
2019 if (adapter->tx_itr_setting & 1)
2020 ixgbe_set_itr_msix(q_vector);
2021 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2022 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2023 }
2024
2025 return work_done;
2026 }
2027
2028 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2029 int r_idx)
2030 {
2031 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2032
2033 set_bit(r_idx, q_vector->rxr_idx);
2034 q_vector->rxr_count++;
2035 }
2036
2037 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2038 int t_idx)
2039 {
2040 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2041
2042 set_bit(t_idx, q_vector->txr_idx);
2043 q_vector->txr_count++;
2044 }
2045
2046 /**
2047 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2048 * @adapter: board private structure to initialize
2049 * @vectors: allotted vector count for descriptor rings
2050 *
2051 * This function maps descriptor rings to the queue-specific vectors
2052 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2053 * one vector per ring/queue, but on a constrained vector budget, we
2054 * group the rings as "efficiently" as possible. You would add new
2055 * mapping configurations in here.
2056 **/
2057 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2058 int vectors)
2059 {
2060 int v_start = 0;
2061 int rxr_idx = 0, txr_idx = 0;
2062 int rxr_remaining = adapter->num_rx_queues;
2063 int txr_remaining = adapter->num_tx_queues;
2064 int i, j;
2065 int rqpv, tqpv;
2066 int err = 0;
2067
2068 /* No mapping required if MSI-X is disabled. */
2069 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2070 goto out;
2071
2072 /*
2073 * The ideal configuration...
2074 * We have enough vectors to map one per queue.
2075 */
2076 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2077 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2078 map_vector_to_rxq(adapter, v_start, rxr_idx);
2079
2080 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2081 map_vector_to_txq(adapter, v_start, txr_idx);
2082
2083 goto out;
2084 }
2085
2086 /*
2087 * If we don't have enough vectors for a 1-to-1
2088 * mapping, we'll have to group them so there are
2089 * multiple queues per vector.
2090 */
2091 /* Re-adjusting *qpv takes care of the remainder. */
2092 for (i = v_start; i < vectors; i++) {
2093 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2094 for (j = 0; j < rqpv; j++) {
2095 map_vector_to_rxq(adapter, i, rxr_idx);
2096 rxr_idx++;
2097 rxr_remaining--;
2098 }
2099 }
2100 for (i = v_start; i < vectors; i++) {
2101 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2102 for (j = 0; j < tqpv; j++) {
2103 map_vector_to_txq(adapter, i, txr_idx);
2104 txr_idx++;
2105 txr_remaining--;
2106 }
2107 }
2108
2109 out:
2110 return err;
2111 }
2112
2113 /**
2114 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2115 * @adapter: board private structure
2116 *
2117 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2118 * interrupts from the kernel.
2119 **/
2120 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2121 {
2122 struct net_device *netdev = adapter->netdev;
2123 irqreturn_t (*handler)(int, void *);
2124 int i, vector, q_vectors, err;
2125 int ri=0, ti=0;
2126
2127 /* Decrement for Other and TCP Timer vectors */
2128 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2129
2130 /* Map the Tx/Rx rings to the vectors we were allotted. */
2131 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2132 if (err)
2133 goto out;
2134
2135 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2136 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2137 &ixgbe_msix_clean_many)
2138 for (vector = 0; vector < q_vectors; vector++) {
2139 handler = SET_HANDLER(adapter->q_vector[vector]);
2140
2141 if(handler == &ixgbe_msix_clean_rx) {
2142 sprintf(adapter->name[vector], "%s-%s-%d",
2143 netdev->name, "rx", ri++);
2144 }
2145 else if(handler == &ixgbe_msix_clean_tx) {
2146 sprintf(adapter->name[vector], "%s-%s-%d",
2147 netdev->name, "tx", ti++);
2148 }
2149 else
2150 sprintf(adapter->name[vector], "%s-%s-%d",
2151 netdev->name, "TxRx", vector);
2152
2153 err = request_irq(adapter->msix_entries[vector].vector,
2154 handler, 0, adapter->name[vector],
2155 adapter->q_vector[vector]);
2156 if (err) {
2157 e_err(probe, "request_irq failed for MSIX interrupt "
2158 "Error: %d\n", err);
2159 goto free_queue_irqs;
2160 }
2161 }
2162
2163 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2164 err = request_irq(adapter->msix_entries[vector].vector,
2165 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2166 if (err) {
2167 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2168 goto free_queue_irqs;
2169 }
2170
2171 return 0;
2172
2173 free_queue_irqs:
2174 for (i = vector - 1; i >= 0; i--)
2175 free_irq(adapter->msix_entries[--vector].vector,
2176 adapter->q_vector[i]);
2177 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2178 pci_disable_msix(adapter->pdev);
2179 kfree(adapter->msix_entries);
2180 adapter->msix_entries = NULL;
2181 out:
2182 return err;
2183 }
2184
2185 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2186 {
2187 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2188 u8 current_itr;
2189 u32 new_itr = q_vector->eitr;
2190 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2191 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2192
2193 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2194 q_vector->tx_itr,
2195 tx_ring->total_packets,
2196 tx_ring->total_bytes);
2197 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2198 q_vector->rx_itr,
2199 rx_ring->total_packets,
2200 rx_ring->total_bytes);
2201
2202 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2203
2204 switch (current_itr) {
2205 /* counts and packets in update_itr are dependent on these numbers */
2206 case lowest_latency:
2207 new_itr = 100000;
2208 break;
2209 case low_latency:
2210 new_itr = 20000; /* aka hwitr = ~200 */
2211 break;
2212 case bulk_latency:
2213 new_itr = 8000;
2214 break;
2215 default:
2216 break;
2217 }
2218
2219 if (new_itr != q_vector->eitr) {
2220 /* do an exponential smoothing */
2221 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2222
2223 /* save the algorithm value here, not the smoothed one */
2224 q_vector->eitr = new_itr;
2225
2226 ixgbe_write_eitr(q_vector);
2227 }
2228 }
2229
2230 /**
2231 * ixgbe_irq_enable - Enable default interrupt generation settings
2232 * @adapter: board private structure
2233 **/
2234 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
2235 {
2236 u32 mask;
2237
2238 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2239 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2240 mask |= IXGBE_EIMS_GPI_SDP0;
2241 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2242 mask |= IXGBE_EIMS_GPI_SDP1;
2243 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2244 mask |= IXGBE_EIMS_ECC;
2245 mask |= IXGBE_EIMS_GPI_SDP1;
2246 mask |= IXGBE_EIMS_GPI_SDP2;
2247 if (adapter->num_vfs)
2248 mask |= IXGBE_EIMS_MAILBOX;
2249 }
2250 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2251 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2252 mask |= IXGBE_EIMS_FLOW_DIR;
2253
2254 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2255 ixgbe_irq_enable_queues(adapter, ~0);
2256 IXGBE_WRITE_FLUSH(&adapter->hw);
2257
2258 if (adapter->num_vfs > 32) {
2259 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2260 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2261 }
2262 }
2263
2264 /**
2265 * ixgbe_intr - legacy mode Interrupt Handler
2266 * @irq: interrupt number
2267 * @data: pointer to a network interface device structure
2268 **/
2269 static irqreturn_t ixgbe_intr(int irq, void *data)
2270 {
2271 struct net_device *netdev = data;
2272 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2273 struct ixgbe_hw *hw = &adapter->hw;
2274 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2275 u32 eicr;
2276
2277 /*
2278 * Workaround for silicon errata. Mask the interrupts
2279 * before the read of EICR.
2280 */
2281 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2282
2283 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2284 * therefore no explict interrupt disable is necessary */
2285 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2286 if (!eicr) {
2287 /* shared interrupt alert!
2288 * make sure interrupts are enabled because the read will
2289 * have disabled interrupts due to EIAM */
2290 ixgbe_irq_enable(adapter);
2291 return IRQ_NONE; /* Not our interrupt */
2292 }
2293
2294 if (eicr & IXGBE_EICR_LSC)
2295 ixgbe_check_lsc(adapter);
2296
2297 if (hw->mac.type == ixgbe_mac_82599EB)
2298 ixgbe_check_sfp_event(adapter, eicr);
2299
2300 ixgbe_check_fan_failure(adapter, eicr);
2301 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2302 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2303 schedule_work(&adapter->check_overtemp_task);
2304
2305 if (napi_schedule_prep(&(q_vector->napi))) {
2306 adapter->tx_ring[0]->total_packets = 0;
2307 adapter->tx_ring[0]->total_bytes = 0;
2308 adapter->rx_ring[0]->total_packets = 0;
2309 adapter->rx_ring[0]->total_bytes = 0;
2310 /* would disable interrupts here but EIAM disabled it */
2311 __napi_schedule(&(q_vector->napi));
2312 }
2313
2314 return IRQ_HANDLED;
2315 }
2316
2317 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2318 {
2319 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2320
2321 for (i = 0; i < q_vectors; i++) {
2322 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2323 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2324 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2325 q_vector->rxr_count = 0;
2326 q_vector->txr_count = 0;
2327 }
2328 }
2329
2330 /**
2331 * ixgbe_request_irq - initialize interrupts
2332 * @adapter: board private structure
2333 *
2334 * Attempts to configure interrupts using the best available
2335 * capabilities of the hardware and kernel.
2336 **/
2337 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2338 {
2339 struct net_device *netdev = adapter->netdev;
2340 int err;
2341
2342 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2343 err = ixgbe_request_msix_irqs(adapter);
2344 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2345 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2346 netdev->name, netdev);
2347 } else {
2348 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2349 netdev->name, netdev);
2350 }
2351
2352 if (err)
2353 e_err(probe, "request_irq failed, Error %d\n", err);
2354
2355 return err;
2356 }
2357
2358 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2359 {
2360 struct net_device *netdev = adapter->netdev;
2361
2362 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2363 int i, q_vectors;
2364
2365 q_vectors = adapter->num_msix_vectors;
2366
2367 i = q_vectors - 1;
2368 free_irq(adapter->msix_entries[i].vector, netdev);
2369
2370 i--;
2371 for (; i >= 0; i--) {
2372 free_irq(adapter->msix_entries[i].vector,
2373 adapter->q_vector[i]);
2374 }
2375
2376 ixgbe_reset_q_vectors(adapter);
2377 } else {
2378 free_irq(adapter->pdev->irq, netdev);
2379 }
2380 }
2381
2382 /**
2383 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2384 * @adapter: board private structure
2385 **/
2386 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2387 {
2388 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2389 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2390 } else {
2391 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2392 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2394 if (adapter->num_vfs > 32)
2395 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2396 }
2397 IXGBE_WRITE_FLUSH(&adapter->hw);
2398 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2399 int i;
2400 for (i = 0; i < adapter->num_msix_vectors; i++)
2401 synchronize_irq(adapter->msix_entries[i].vector);
2402 } else {
2403 synchronize_irq(adapter->pdev->irq);
2404 }
2405 }
2406
2407 /**
2408 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2409 *
2410 **/
2411 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2412 {
2413 struct ixgbe_hw *hw = &adapter->hw;
2414
2415 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2416 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2417
2418 ixgbe_set_ivar(adapter, 0, 0, 0);
2419 ixgbe_set_ivar(adapter, 1, 0, 0);
2420
2421 map_vector_to_rxq(adapter, 0, 0);
2422 map_vector_to_txq(adapter, 0, 0);
2423
2424 e_info(hw, "Legacy interrupt IVAR setup done\n");
2425 }
2426
2427 /**
2428 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2429 * @adapter: board private structure
2430 * @ring: structure containing ring specific data
2431 *
2432 * Configure the Tx descriptor ring after a reset.
2433 **/
2434 static void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2435 struct ixgbe_ring *ring)
2436 {
2437 struct ixgbe_hw *hw = &adapter->hw;
2438 u64 tdba = ring->dma;
2439 u16 reg_idx = ring->reg_idx;
2440
2441 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2442 (tdba & DMA_BIT_MASK(32)));
2443 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2444 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2445 ring->count * sizeof(union ixgbe_adv_tx_desc));
2446 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2447 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2448 ring->head = IXGBE_TDH(reg_idx);
2449 ring->tail = IXGBE_TDT(reg_idx);
2450
2451 }
2452
2453 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2454 {
2455 struct ixgbe_hw *hw = &adapter->hw;
2456 u32 rttdcs;
2457 u32 mask;
2458
2459 if (hw->mac.type == ixgbe_mac_82598EB)
2460 return;
2461
2462 /* disable the arbiter while setting MTQC */
2463 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2464 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2465 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2466
2467 /* set transmit pool layout */
2468 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2469 switch (adapter->flags & mask) {
2470
2471 case (IXGBE_FLAG_SRIOV_ENABLED):
2472 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2473 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2474 break;
2475
2476 case (IXGBE_FLAG_DCB_ENABLED):
2477 /* We enable 8 traffic classes, DCB only */
2478 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2479 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2480 break;
2481
2482 default:
2483 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2484 break;
2485 }
2486
2487 /* re-enable the arbiter */
2488 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2489 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2490 }
2491
2492 /**
2493 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2494 * @adapter: board private structure
2495 *
2496 * Configure the Tx unit of the MAC after a reset.
2497 **/
2498 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2499 {
2500 u32 i;
2501
2502 /* Setup the HW Tx Head and Tail descriptor pointers */
2503 for (i = 0; i < adapter->num_tx_queues; i++)
2504 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2505
2506 ixgbe_setup_mtqc(adapter);
2507 }
2508
2509 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2510
2511 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2512 struct ixgbe_ring *rx_ring)
2513 {
2514 u32 srrctl;
2515 int index;
2516 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2517
2518 index = rx_ring->reg_idx;
2519 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2520 unsigned long mask;
2521 mask = (unsigned long) feature[RING_F_RSS].mask;
2522 index = index & mask;
2523 }
2524 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2525
2526 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2527 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2528
2529 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2530 IXGBE_SRRCTL_BSIZEHDR_MASK;
2531
2532 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2533 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2534 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2535 #else
2536 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2537 #endif
2538 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2539 } else {
2540 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2541 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2542 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2543 }
2544
2545 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2546 }
2547
2548 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2549 {
2550 struct ixgbe_hw *hw = &adapter->hw;
2551 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2552 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2553 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2554 u32 mrqc = 0, reta = 0;
2555 u32 rxcsum;
2556 int i, j;
2557 int mask;
2558
2559 /* Fill out hash function seeds */
2560 for (i = 0; i < 10; i++)
2561 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2562
2563 /* Fill out redirection table */
2564 for (i = 0, j = 0; i < 128; i++, j++) {
2565 if (j == adapter->ring_feature[RING_F_RSS].indices)
2566 j = 0;
2567 /* reta = 4-byte sliding window of
2568 * 0x00..(indices-1)(indices-1)00..etc. */
2569 reta = (reta << 8) | (j * 0x11);
2570 if ((i & 3) == 3)
2571 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2572 }
2573
2574 /* Disable indicating checksum in descriptor, enables RSS hash */
2575 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2576 rxcsum |= IXGBE_RXCSUM_PCSD;
2577 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2578
2579 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2580 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2581 else
2582 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2583 #ifdef CONFIG_IXGBE_DCB
2584 | IXGBE_FLAG_DCB_ENABLED
2585 #endif
2586 | IXGBE_FLAG_SRIOV_ENABLED
2587 );
2588
2589 switch (mask) {
2590 case (IXGBE_FLAG_RSS_ENABLED):
2591 mrqc = IXGBE_MRQC_RSSEN;
2592 break;
2593 case (IXGBE_FLAG_SRIOV_ENABLED):
2594 mrqc = IXGBE_MRQC_VMDQEN;
2595 break;
2596 #ifdef CONFIG_IXGBE_DCB
2597 case (IXGBE_FLAG_DCB_ENABLED):
2598 mrqc = IXGBE_MRQC_RT8TCEN;
2599 break;
2600 #endif /* CONFIG_IXGBE_DCB */
2601 default:
2602 break;
2603 }
2604
2605 /* Perform hash on these packet types */
2606 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2607 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2608 | IXGBE_MRQC_RSS_FIELD_IPV6
2609 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2610
2611 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2612 }
2613
2614 /**
2615 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2616 * @adapter: address of board private structure
2617 * @index: index of ring to set
2618 **/
2619 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2620 struct ixgbe_ring *ring)
2621 {
2622 struct ixgbe_hw *hw = &adapter->hw;
2623 u32 rscctrl;
2624 int rx_buf_len;
2625 u16 reg_idx = ring->reg_idx;
2626
2627 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2628 return;
2629
2630 rx_buf_len = ring->rx_buf_len;
2631 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2632 rscctrl |= IXGBE_RSCCTL_RSCEN;
2633 /*
2634 * we must limit the number of descriptors so that the
2635 * total size of max desc * buf_len is not greater
2636 * than 65535
2637 */
2638 if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2639 #if (MAX_SKB_FRAGS > 16)
2640 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2641 #elif (MAX_SKB_FRAGS > 8)
2642 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2643 #elif (MAX_SKB_FRAGS > 4)
2644 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2645 #else
2646 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2647 #endif
2648 } else {
2649 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2650 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2651 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2652 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2653 else
2654 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2655 }
2656 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2657 }
2658
2659 static void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2660 struct ixgbe_ring *ring)
2661 {
2662 struct ixgbe_hw *hw = &adapter->hw;
2663 u64 rdba = ring->dma;
2664 u16 reg_idx = ring->reg_idx;
2665
2666 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2667 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2668 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2669 ring->count * sizeof(union ixgbe_adv_rx_desc));
2670 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2671 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2672 ring->head = IXGBE_RDH(reg_idx);
2673 ring->tail = IXGBE_RDT(reg_idx);
2674 }
2675
2676 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2677 {
2678 struct ixgbe_hw *hw = &adapter->hw;
2679 int p;
2680
2681 /* PSRTYPE must be initialized in non 82598 adapters */
2682 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2683 IXGBE_PSRTYPE_UDPHDR |
2684 IXGBE_PSRTYPE_IPV4HDR |
2685 IXGBE_PSRTYPE_L2HDR |
2686 IXGBE_PSRTYPE_IPV6HDR;
2687
2688 if (hw->mac.type == ixgbe_mac_82598EB)
2689 return;
2690
2691 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2692 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2693
2694 for (p = 0; p < adapter->num_rx_pools; p++)
2695 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2696 psrtype);
2697 }
2698
2699 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2700 {
2701 struct ixgbe_hw *hw = &adapter->hw;
2702 u32 gcr_ext;
2703 u32 vt_reg_bits;
2704 u32 reg_offset, vf_shift;
2705 u32 vmdctl;
2706
2707 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2708 return;
2709
2710 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2711 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2712 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2713 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2714
2715 vf_shift = adapter->num_vfs % 32;
2716 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2717
2718 /* Enable only the PF's pool for Tx/Rx */
2719 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2720 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2721 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2722 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2723 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2724
2725 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2726 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2727
2728 /*
2729 * Set up VF register offsets for selected VT Mode,
2730 * i.e. 32 or 64 VFs for SR-IOV
2731 */
2732 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2733 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2734 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2735 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2736
2737 /* enable Tx loopback for VF/PF communication */
2738 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2739 }
2740
2741 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2742 {
2743 struct ixgbe_hw *hw = &adapter->hw;
2744 struct net_device *netdev = adapter->netdev;
2745 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2746 int rx_buf_len;
2747 struct ixgbe_ring *rx_ring;
2748 int i;
2749 u32 mhadd, hlreg0;
2750
2751 /* Decide whether to use packet split mode or not */
2752 /* Do not use packet split if we're in SR-IOV Mode */
2753 if (!adapter->num_vfs)
2754 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2755
2756 /* Set the RX buffer length according to the mode */
2757 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2758 rx_buf_len = IXGBE_RX_HDR_SIZE;
2759 } else {
2760 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2761 (netdev->mtu <= ETH_DATA_LEN))
2762 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2763 else
2764 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2765 }
2766
2767 #ifdef IXGBE_FCOE
2768 /* adjust max frame to be able to do baby jumbo for FCoE */
2769 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2770 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2771 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2772
2773 #endif /* IXGBE_FCOE */
2774 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2775 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2776 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2777 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2778
2779 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2780 }
2781
2782 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2783 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2784 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2785 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2786
2787 /*
2788 * Setup the HW Rx Head and Tail Descriptor Pointers and
2789 * the Base and Length of the Rx Descriptor Ring
2790 */
2791 for (i = 0; i < adapter->num_rx_queues; i++) {
2792 rx_ring = adapter->rx_ring[i];
2793 rx_ring->rx_buf_len = rx_buf_len;
2794
2795 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2796 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2797 else
2798 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2799
2800 #ifdef IXGBE_FCOE
2801 if (netdev->features & NETIF_F_FCOE_MTU)
2802 {
2803 struct ixgbe_ring_feature *f;
2804 f = &adapter->ring_feature[RING_F_FCOE];
2805 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2806 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2807 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2808 rx_ring->rx_buf_len =
2809 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2810 }
2811 }
2812 #endif /* IXGBE_FCOE */
2813 }
2814
2815 }
2816
2817 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2818 {
2819 struct ixgbe_hw *hw = &adapter->hw;
2820 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2821
2822 switch (hw->mac.type) {
2823 case ixgbe_mac_82598EB:
2824 /*
2825 * For VMDq support of different descriptor types or
2826 * buffer sizes through the use of multiple SRRCTL
2827 * registers, RDRXCTL.MVMEN must be set to 1
2828 *
2829 * also, the manual doesn't mention it clearly but DCA hints
2830 * will only use queue 0's tags unless this bit is set. Side
2831 * effects of setting this bit are only that SRRCTL must be
2832 * fully programmed [0..15]
2833 */
2834 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2835 break;
2836 case ixgbe_mac_82599EB:
2837 /* Disable RSC for ACK packets */
2838 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2839 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2840 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2841 /* hardware requires some bits to be set by default */
2842 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2843 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2844 break;
2845 default:
2846 /* We should do nothing since we don't know this hardware */
2847 return;
2848 }
2849
2850 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2851 }
2852
2853 /**
2854 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2855 * @adapter: board private structure
2856 *
2857 * Configure the Rx unit of the MAC after a reset.
2858 **/
2859 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
2860 {
2861 struct ixgbe_hw *hw = &adapter->hw;
2862 struct ixgbe_ring *rx_ring;
2863 int i;
2864 u32 rxctrl;
2865
2866 /* disable receives while setting up the descriptors */
2867 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2868 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2869
2870 ixgbe_setup_psrtype(adapter);
2871 ixgbe_setup_rdrxctl(adapter);
2872
2873 /* Program MRQC for the distribution of queues */
2874 ixgbe_setup_mrqc(adapter);
2875 ixgbe_configure_virtualization(adapter);
2876
2877 /* set_rx_buffer_len must be called before ring initialization */
2878 ixgbe_set_rx_buffer_len(adapter);
2879
2880 /*
2881 * Setup the HW Rx Head and Tail Descriptor Pointers and
2882 * the Base and Length of the Rx Descriptor Ring
2883 */
2884 for (i = 0; i < adapter->num_rx_queues; i++) {
2885 rx_ring = adapter->rx_ring[i];
2886 ixgbe_configure_rx_ring(adapter, rx_ring);
2887 ixgbe_configure_srrctl(adapter, rx_ring);
2888 ixgbe_configure_rscctl(adapter, rx_ring);
2889 }
2890
2891 }
2892
2893 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2894 {
2895 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2896 struct ixgbe_hw *hw = &adapter->hw;
2897 int pool_ndx = adapter->num_vfs;
2898
2899 /* add VID to filter table */
2900 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
2901 }
2902
2903 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2904 {
2905 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2906 struct ixgbe_hw *hw = &adapter->hw;
2907 int pool_ndx = adapter->num_vfs;
2908
2909 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2910 ixgbe_irq_disable(adapter);
2911
2912 vlan_group_set_device(adapter->vlgrp, vid, NULL);
2913
2914 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2915 ixgbe_irq_enable(adapter);
2916
2917 /* remove VID from filter table */
2918 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
2919 }
2920
2921 /**
2922 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2923 * @adapter: driver data
2924 */
2925 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
2926 {
2927 struct ixgbe_hw *hw = &adapter->hw;
2928 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2929 int i, j;
2930
2931 switch (hw->mac.type) {
2932 case ixgbe_mac_82598EB:
2933 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2934 #ifdef CONFIG_IXGBE_DCB
2935 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
2936 vlnctrl &= ~IXGBE_VLNCTRL_VME;
2937 #endif
2938 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2939 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2940 break;
2941 case ixgbe_mac_82599EB:
2942 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2943 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2944 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2945 #ifdef CONFIG_IXGBE_DCB
2946 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
2947 break;
2948 #endif
2949 for (i = 0; i < adapter->num_rx_queues; i++) {
2950 j = adapter->rx_ring[i]->reg_idx;
2951 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2952 vlnctrl &= ~IXGBE_RXDCTL_VME;
2953 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2954 }
2955 break;
2956 default:
2957 break;
2958 }
2959 }
2960
2961 /**
2962 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2963 * @adapter: driver data
2964 */
2965 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
2966 {
2967 struct ixgbe_hw *hw = &adapter->hw;
2968 u32 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2969 int i, j;
2970
2971 switch (hw->mac.type) {
2972 case ixgbe_mac_82598EB:
2973 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2974 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2975 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2976 break;
2977 case ixgbe_mac_82599EB:
2978 vlnctrl |= IXGBE_VLNCTRL_VFE;
2979 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2980 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2981 for (i = 0; i < adapter->num_rx_queues; i++) {
2982 j = adapter->rx_ring[i]->reg_idx;
2983 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2984 vlnctrl |= IXGBE_RXDCTL_VME;
2985 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2986 }
2987 break;
2988 default:
2989 break;
2990 }
2991 }
2992
2993 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2994 struct vlan_group *grp)
2995 {
2996 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2997
2998 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2999 ixgbe_irq_disable(adapter);
3000 adapter->vlgrp = grp;
3001
3002 /*
3003 * For a DCB driver, always enable VLAN tag stripping so we can
3004 * still receive traffic from a DCB-enabled host even if we're
3005 * not in DCB mode.
3006 */
3007 ixgbe_vlan_filter_enable(adapter);
3008
3009 ixgbe_vlan_rx_add_vid(netdev, 0);
3010
3011 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3012 ixgbe_irq_enable(adapter);
3013 }
3014
3015 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3016 {
3017 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3018
3019 if (adapter->vlgrp) {
3020 u16 vid;
3021 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3022 if (!vlan_group_get_device(adapter->vlgrp, vid))
3023 continue;
3024 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3025 }
3026 }
3027 }
3028
3029 /**
3030 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3031 * @netdev: network interface device structure
3032 *
3033 * Writes unicast address list to the RAR table.
3034 * Returns: -ENOMEM on failure/insufficient address space
3035 * 0 on no addresses written
3036 * X on writing X addresses to the RAR table
3037 **/
3038 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3039 {
3040 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3041 struct ixgbe_hw *hw = &adapter->hw;
3042 unsigned int vfn = adapter->num_vfs;
3043 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3044 int count = 0;
3045
3046 /* return ENOMEM indicating insufficient memory for addresses */
3047 if (netdev_uc_count(netdev) > rar_entries)
3048 return -ENOMEM;
3049
3050 if (!netdev_uc_empty(netdev) && rar_entries) {
3051 struct netdev_hw_addr *ha;
3052 /* return error if we do not support writing to RAR table */
3053 if (!hw->mac.ops.set_rar)
3054 return -ENOMEM;
3055
3056 netdev_for_each_uc_addr(ha, netdev) {
3057 if (!rar_entries)
3058 break;
3059 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3060 vfn, IXGBE_RAH_AV);
3061 count++;
3062 }
3063 }
3064 /* write the addresses in reverse order to avoid write combining */
3065 for (; rar_entries > 0 ; rar_entries--)
3066 hw->mac.ops.clear_rar(hw, rar_entries);
3067
3068 return count;
3069 }
3070
3071 /**
3072 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3073 * @netdev: network interface device structure
3074 *
3075 * The set_rx_method entry point is called whenever the unicast/multicast
3076 * address list or the network interface flags are updated. This routine is
3077 * responsible for configuring the hardware for proper unicast, multicast and
3078 * promiscuous mode.
3079 **/
3080 void ixgbe_set_rx_mode(struct net_device *netdev)
3081 {
3082 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3083 struct ixgbe_hw *hw = &adapter->hw;
3084 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3085 int count;
3086
3087 /* Check for Promiscuous and All Multicast modes */
3088
3089 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3090
3091 /* set all bits that we expect to always be set */
3092 fctrl |= IXGBE_FCTRL_BAM;
3093 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3094 fctrl |= IXGBE_FCTRL_PMCF;
3095
3096 /* clear the bits we are changing the status of */
3097 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3098
3099 if (netdev->flags & IFF_PROMISC) {
3100 hw->addr_ctrl.user_set_promisc = true;
3101 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3102 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3103 /* don't hardware filter vlans in promisc mode */
3104 ixgbe_vlan_filter_disable(adapter);
3105 } else {
3106 if (netdev->flags & IFF_ALLMULTI) {
3107 fctrl |= IXGBE_FCTRL_MPE;
3108 vmolr |= IXGBE_VMOLR_MPE;
3109 } else {
3110 /*
3111 * Write addresses to the MTA, if the attempt fails
3112 * then we should just turn on promiscous mode so
3113 * that we can at least receive multicast traffic
3114 */
3115 hw->mac.ops.update_mc_addr_list(hw, netdev);
3116 vmolr |= IXGBE_VMOLR_ROMPE;
3117 }
3118 ixgbe_vlan_filter_enable(adapter);
3119 hw->addr_ctrl.user_set_promisc = false;
3120 /*
3121 * Write addresses to available RAR registers, if there is not
3122 * sufficient space to store all the addresses then enable
3123 * unicast promiscous mode
3124 */
3125 count = ixgbe_write_uc_addr_list(netdev);
3126 if (count < 0) {
3127 fctrl |= IXGBE_FCTRL_UPE;
3128 vmolr |= IXGBE_VMOLR_ROPE;
3129 }
3130 }
3131
3132 if (adapter->num_vfs) {
3133 ixgbe_restore_vf_multicasts(adapter);
3134 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3135 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3136 IXGBE_VMOLR_ROPE);
3137 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3138 }
3139
3140 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3141 }
3142
3143 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3144 {
3145 int q_idx;
3146 struct ixgbe_q_vector *q_vector;
3147 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3148
3149 /* legacy and MSI only use one vector */
3150 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3151 q_vectors = 1;
3152
3153 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3154 struct napi_struct *napi;
3155 q_vector = adapter->q_vector[q_idx];
3156 napi = &q_vector->napi;
3157 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3158 if (!q_vector->rxr_count || !q_vector->txr_count) {
3159 if (q_vector->txr_count == 1)
3160 napi->poll = &ixgbe_clean_txonly;
3161 else if (q_vector->rxr_count == 1)
3162 napi->poll = &ixgbe_clean_rxonly;
3163 }
3164 }
3165
3166 napi_enable(napi);
3167 }
3168 }
3169
3170 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3171 {
3172 int q_idx;
3173 struct ixgbe_q_vector *q_vector;
3174 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3175
3176 /* legacy and MSI only use one vector */
3177 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3178 q_vectors = 1;
3179
3180 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3181 q_vector = adapter->q_vector[q_idx];
3182 napi_disable(&q_vector->napi);
3183 }
3184 }
3185
3186 #ifdef CONFIG_IXGBE_DCB
3187 /*
3188 * ixgbe_configure_dcb - Configure DCB hardware
3189 * @adapter: ixgbe adapter struct
3190 *
3191 * This is called by the driver on open to configure the DCB hardware.
3192 * This is also called by the gennetlink interface when reconfiguring
3193 * the DCB state.
3194 */
3195 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3196 {
3197 struct ixgbe_hw *hw = &adapter->hw;
3198 u32 txdctl;
3199 int i, j;
3200
3201 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3202 if (hw->mac.type == ixgbe_mac_82598EB)
3203 netif_set_gso_max_size(adapter->netdev, 65536);
3204 return;
3205 }
3206
3207 if (hw->mac.type == ixgbe_mac_82598EB)
3208 netif_set_gso_max_size(adapter->netdev, 32768);
3209
3210 ixgbe_dcb_check_config(&adapter->dcb_cfg);
3211 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3212 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3213
3214 /* reconfigure the hardware */
3215 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3216
3217 for (i = 0; i < adapter->num_tx_queues; i++) {
3218 j = adapter->tx_ring[i]->reg_idx;
3219 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3220 /* PThresh workaround for Tx hang with DFP enabled. */
3221 txdctl |= 32;
3222 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3223 }
3224 /* Enable VLAN tag insert/strip */
3225 ixgbe_vlan_filter_enable(adapter);
3226
3227 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3228 }
3229
3230 #endif
3231 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3232 {
3233 struct net_device *netdev = adapter->netdev;
3234 struct ixgbe_hw *hw = &adapter->hw;
3235 int i;
3236
3237 ixgbe_set_rx_mode(netdev);
3238
3239 ixgbe_restore_vlan(adapter);
3240 #ifdef CONFIG_IXGBE_DCB
3241 ixgbe_configure_dcb(adapter);
3242 #endif
3243
3244 #ifdef IXGBE_FCOE
3245 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3246 ixgbe_configure_fcoe(adapter);
3247
3248 #endif /* IXGBE_FCOE */
3249 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3250 for (i = 0; i < adapter->num_tx_queues; i++)
3251 adapter->tx_ring[i]->atr_sample_rate =
3252 adapter->atr_sample_rate;
3253 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3254 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3255 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3256 }
3257
3258 ixgbe_configure_tx(adapter);
3259 ixgbe_configure_rx(adapter);
3260 for (i = 0; i < adapter->num_rx_queues; i++)
3261 ixgbe_alloc_rx_buffers(adapter, adapter->rx_ring[i],
3262 (adapter->rx_ring[i]->count - 1));
3263 }
3264
3265 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3266 {
3267 switch (hw->phy.type) {
3268 case ixgbe_phy_sfp_avago:
3269 case ixgbe_phy_sfp_ftl:
3270 case ixgbe_phy_sfp_intel:
3271 case ixgbe_phy_sfp_unknown:
3272 case ixgbe_phy_sfp_passive_tyco:
3273 case ixgbe_phy_sfp_passive_unknown:
3274 case ixgbe_phy_sfp_active_unknown:
3275 case ixgbe_phy_sfp_ftl_active:
3276 return true;
3277 default:
3278 return false;
3279 }
3280 }
3281
3282 /**
3283 * ixgbe_sfp_link_config - set up SFP+ link
3284 * @adapter: pointer to private adapter struct
3285 **/
3286 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3287 {
3288 struct ixgbe_hw *hw = &adapter->hw;
3289
3290 if (hw->phy.multispeed_fiber) {
3291 /*
3292 * In multispeed fiber setups, the device may not have
3293 * had a physical connection when the driver loaded.
3294 * If that's the case, the initial link configuration
3295 * couldn't get the MAC into 10G or 1G mode, so we'll
3296 * never have a link status change interrupt fire.
3297 * We need to try and force an autonegotiation
3298 * session, then bring up link.
3299 */
3300 hw->mac.ops.setup_sfp(hw);
3301 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3302 schedule_work(&adapter->multispeed_fiber_task);
3303 } else {
3304 /*
3305 * Direct Attach Cu and non-multispeed fiber modules
3306 * still need to be configured properly prior to
3307 * attempting link.
3308 */
3309 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3310 schedule_work(&adapter->sfp_config_module_task);
3311 }
3312 }
3313
3314 /**
3315 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3316 * @hw: pointer to private hardware struct
3317 *
3318 * Returns 0 on success, negative on failure
3319 **/
3320 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3321 {
3322 u32 autoneg;
3323 bool negotiation, link_up = false;
3324 u32 ret = IXGBE_ERR_LINK_SETUP;
3325
3326 if (hw->mac.ops.check_link)
3327 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3328
3329 if (ret)
3330 goto link_cfg_out;
3331
3332 if (hw->mac.ops.get_link_capabilities)
3333 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
3334 if (ret)
3335 goto link_cfg_out;
3336
3337 if (hw->mac.ops.setup_link)
3338 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3339 link_cfg_out:
3340 return ret;
3341 }
3342
3343 #define IXGBE_MAX_RX_DESC_POLL 10
3344 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3345 int rxr)
3346 {
3347 int j = adapter->rx_ring[rxr]->reg_idx;
3348 int k;
3349
3350 for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
3351 if (IXGBE_READ_REG(&adapter->hw,
3352 IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
3353 break;
3354 else
3355 msleep(1);
3356 }
3357 if (k >= IXGBE_MAX_RX_DESC_POLL) {
3358 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3359 "the polling period\n", rxr);
3360 }
3361 ixgbe_release_rx_desc(&adapter->hw, adapter->rx_ring[rxr],
3362 (adapter->rx_ring[rxr]->count - 1));
3363 }
3364
3365 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3366 {
3367 struct ixgbe_hw *hw = &adapter->hw;
3368 u32 gpie = 0;
3369
3370 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3371 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3372 IXGBE_GPIE_OCD;
3373 gpie |= IXGBE_GPIE_EIAME;
3374 /*
3375 * use EIAM to auto-mask when MSI-X interrupt is asserted
3376 * this saves a register write for every interrupt
3377 */
3378 switch (hw->mac.type) {
3379 case ixgbe_mac_82598EB:
3380 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3381 break;
3382 default:
3383 case ixgbe_mac_82599EB:
3384 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3385 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3386 break;
3387 }
3388 } else {
3389 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3390 * specifically only auto mask tx and rx interrupts */
3391 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3392 }
3393
3394 /* XXX: to interrupt immediately for EICS writes, enable this */
3395 /* gpie |= IXGBE_GPIE_EIMEN; */
3396
3397 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3398 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3399 gpie |= IXGBE_GPIE_VTMODE_64;
3400 }
3401
3402 /* Enable fan failure interrupt */
3403 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3404 gpie |= IXGBE_SDP1_GPIEN;
3405
3406 if (hw->mac.type == ixgbe_mac_82599EB)
3407 gpie |= IXGBE_SDP1_GPIEN;
3408 gpie |= IXGBE_SDP2_GPIEN;
3409
3410 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3411 }
3412
3413 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3414 {
3415 struct ixgbe_hw *hw = &adapter->hw;
3416 int i, j = 0;
3417 int num_rx_rings = adapter->num_rx_queues;
3418 int err;
3419 u32 txdctl, rxdctl;
3420 u32 dmatxctl;
3421 u32 ctrl_ext;
3422
3423 ixgbe_get_hw_control(adapter);
3424 ixgbe_setup_gpie(adapter);
3425
3426 if (hw->mac.type == ixgbe_mac_82599EB) {
3427 /* DMATXCTL.EN must be set after all Tx queue config is done */
3428 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3429 dmatxctl |= IXGBE_DMATXCTL_TE;
3430 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3431 }
3432 for (i = 0; i < adapter->num_tx_queues; i++) {
3433 j = adapter->tx_ring[i]->reg_idx;
3434 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3435 if (adapter->rx_itr_setting == 0) {
3436 /* cannot set wthresh when itr==0 */
3437 txdctl &= ~0x007F0000;
3438 } else {
3439 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3440 txdctl |= (8 << 16);
3441 }
3442 txdctl |= IXGBE_TXDCTL_ENABLE;
3443 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3444 if (hw->mac.type == ixgbe_mac_82599EB) {
3445 int wait_loop = 10;
3446 /* poll for Tx Enable ready */
3447 do {
3448 msleep(1);
3449 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3450 } while (--wait_loop &&
3451 !(txdctl & IXGBE_TXDCTL_ENABLE));
3452 if (!wait_loop)
3453 e_err(drv, "Could not enable Tx Queue %d\n", j);
3454 }
3455 }
3456
3457 for (i = 0; i < num_rx_rings; i++) {
3458 j = adapter->rx_ring[i]->reg_idx;
3459 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3460 /* enable PTHRESH=32 descriptors (half the internal cache)
3461 * and HTHRESH=0 descriptors (to minimize latency on fetch),
3462 * this also removes a pesky rx_no_buffer_count increment */
3463 rxdctl |= 0x0020;
3464 rxdctl |= IXGBE_RXDCTL_ENABLE;
3465 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
3466 if (hw->mac.type == ixgbe_mac_82599EB)
3467 ixgbe_rx_desc_queue_enable(adapter, i);
3468 }
3469 /* enable all receives */
3470 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3471 if (hw->mac.type == ixgbe_mac_82598EB)
3472 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
3473 else
3474 rxdctl |= IXGBE_RXCTRL_RXEN;
3475 hw->mac.ops.enable_rx_dma(hw, rxdctl);
3476
3477 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3478 ixgbe_configure_msix(adapter);
3479 else
3480 ixgbe_configure_msi_and_legacy(adapter);
3481
3482 /* enable the optics */
3483 if (hw->phy.multispeed_fiber)
3484 hw->mac.ops.enable_tx_laser(hw);
3485
3486 clear_bit(__IXGBE_DOWN, &adapter->state);
3487 ixgbe_napi_enable_all(adapter);
3488
3489 /* clear any pending interrupts, may auto mask */
3490 IXGBE_READ_REG(hw, IXGBE_EICR);
3491
3492 ixgbe_irq_enable(adapter);
3493
3494 /*
3495 * If this adapter has a fan, check to see if we had a failure
3496 * before we enabled the interrupt.
3497 */
3498 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3499 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3500 if (esdp & IXGBE_ESDP_SDP1)
3501 e_crit(drv, "Fan has stopped, replace the adapter\n");
3502 }
3503
3504 /*
3505 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3506 * arrived before interrupts were enabled but after probe. Such
3507 * devices wouldn't have their type identified yet. We need to
3508 * kick off the SFP+ module setup first, then try to bring up link.
3509 * If we're not hot-pluggable SFP+, we just need to configure link
3510 * and bring it up.
3511 */
3512 if (hw->phy.type == ixgbe_phy_unknown) {
3513 err = hw->phy.ops.identify(hw);
3514 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3515 /*
3516 * Take the device down and schedule the sfp tasklet
3517 * which will unregister_netdev and log it.
3518 */
3519 ixgbe_down(adapter);
3520 schedule_work(&adapter->sfp_config_module_task);
3521 return err;
3522 }
3523 }
3524
3525 if (ixgbe_is_sfp(hw)) {
3526 ixgbe_sfp_link_config(adapter);
3527 } else {
3528 err = ixgbe_non_sfp_link_config(hw);
3529 if (err)
3530 e_err(probe, "link_config FAILED %d\n", err);
3531 }
3532
3533 for (i = 0; i < adapter->num_tx_queues; i++)
3534 set_bit(__IXGBE_FDIR_INIT_DONE,
3535 &(adapter->tx_ring[i]->reinit_state));
3536
3537 /* enable transmits */
3538 netif_tx_start_all_queues(adapter->netdev);
3539
3540 /* bring the link up in the watchdog, this could race with our first
3541 * link up interrupt but shouldn't be a problem */
3542 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3543 adapter->link_check_timeout = jiffies;
3544 mod_timer(&adapter->watchdog_timer, jiffies);
3545
3546 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3547 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3548 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3549 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3550
3551 return 0;
3552 }
3553
3554 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3555 {
3556 WARN_ON(in_interrupt());
3557 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3558 msleep(1);
3559 ixgbe_down(adapter);
3560 /*
3561 * If SR-IOV enabled then wait a bit before bringing the adapter
3562 * back up to give the VFs time to respond to the reset. The
3563 * two second wait is based upon the watchdog timer cycle in
3564 * the VF driver.
3565 */
3566 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3567 msleep(2000);
3568 ixgbe_up(adapter);
3569 clear_bit(__IXGBE_RESETTING, &adapter->state);
3570 }
3571
3572 int ixgbe_up(struct ixgbe_adapter *adapter)
3573 {
3574 /* hardware has been reset, we need to reload some things */
3575 ixgbe_configure(adapter);
3576
3577 return ixgbe_up_complete(adapter);
3578 }
3579
3580 void ixgbe_reset(struct ixgbe_adapter *adapter)
3581 {
3582 struct ixgbe_hw *hw = &adapter->hw;
3583 int err;
3584
3585 err = hw->mac.ops.init_hw(hw);
3586 switch (err) {
3587 case 0:
3588 case IXGBE_ERR_SFP_NOT_PRESENT:
3589 break;
3590 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3591 e_dev_err("master disable timed out\n");
3592 break;
3593 case IXGBE_ERR_EEPROM_VERSION:
3594 /* We are running on a pre-production device, log a warning */
3595 e_dev_warn("This device is a pre-production adapter/LOM. "
3596 "Please be aware there may be issuesassociated with "
3597 "your hardware. If you are experiencing problems "
3598 "please contact your Intel or hardware "
3599 "representative who provided you with this "
3600 "hardware.\n");
3601 break;
3602 default:
3603 e_dev_err("Hardware Error: %d\n", err);
3604 }
3605
3606 /* reprogram the RAR[0] in case user changed it. */
3607 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3608 IXGBE_RAH_AV);
3609 }
3610
3611 /**
3612 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3613 * @adapter: board private structure
3614 * @rx_ring: ring to free buffers from
3615 **/
3616 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3617 struct ixgbe_ring *rx_ring)
3618 {
3619 struct pci_dev *pdev = adapter->pdev;
3620 unsigned long size;
3621 unsigned int i;
3622
3623 /* Free all the Rx ring sk_buffs */
3624
3625 for (i = 0; i < rx_ring->count; i++) {
3626 struct ixgbe_rx_buffer *rx_buffer_info;
3627
3628 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3629 if (rx_buffer_info->dma) {
3630 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3631 rx_ring->rx_buf_len,
3632 DMA_FROM_DEVICE);
3633 rx_buffer_info->dma = 0;
3634 }
3635 if (rx_buffer_info->skb) {
3636 struct sk_buff *skb = rx_buffer_info->skb;
3637 rx_buffer_info->skb = NULL;
3638 do {
3639 struct sk_buff *this = skb;
3640 if (IXGBE_RSC_CB(this)->delay_unmap) {
3641 dma_unmap_single(&pdev->dev,
3642 IXGBE_RSC_CB(this)->dma,
3643 rx_ring->rx_buf_len,
3644 DMA_FROM_DEVICE);
3645 IXGBE_RSC_CB(this)->dma = 0;
3646 IXGBE_RSC_CB(skb)->delay_unmap = false;
3647 }
3648 skb = skb->prev;
3649 dev_kfree_skb(this);
3650 } while (skb);
3651 }
3652 if (!rx_buffer_info->page)
3653 continue;
3654 if (rx_buffer_info->page_dma) {
3655 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3656 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3657 rx_buffer_info->page_dma = 0;
3658 }
3659 put_page(rx_buffer_info->page);
3660 rx_buffer_info->page = NULL;
3661 rx_buffer_info->page_offset = 0;
3662 }
3663
3664 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3665 memset(rx_ring->rx_buffer_info, 0, size);
3666
3667 /* Zero out the descriptor ring */
3668 memset(rx_ring->desc, 0, rx_ring->size);
3669
3670 rx_ring->next_to_clean = 0;
3671 rx_ring->next_to_use = 0;
3672
3673 if (rx_ring->head)
3674 writel(0, adapter->hw.hw_addr + rx_ring->head);
3675 if (rx_ring->tail)
3676 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3677 }
3678
3679 /**
3680 * ixgbe_clean_tx_ring - Free Tx Buffers
3681 * @adapter: board private structure
3682 * @tx_ring: ring to be cleaned
3683 **/
3684 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3685 struct ixgbe_ring *tx_ring)
3686 {
3687 struct ixgbe_tx_buffer *tx_buffer_info;
3688 unsigned long size;
3689 unsigned int i;
3690
3691 /* Free all the Tx ring sk_buffs */
3692
3693 for (i = 0; i < tx_ring->count; i++) {
3694 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3695 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3696 }
3697
3698 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3699 memset(tx_ring->tx_buffer_info, 0, size);
3700
3701 /* Zero out the descriptor ring */
3702 memset(tx_ring->desc, 0, tx_ring->size);
3703
3704 tx_ring->next_to_use = 0;
3705 tx_ring->next_to_clean = 0;
3706
3707 if (tx_ring->head)
3708 writel(0, adapter->hw.hw_addr + tx_ring->head);
3709 if (tx_ring->tail)
3710 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3711 }
3712
3713 /**
3714 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3715 * @adapter: board private structure
3716 **/
3717 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3718 {
3719 int i;
3720
3721 for (i = 0; i < adapter->num_rx_queues; i++)
3722 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3723 }
3724
3725 /**
3726 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3727 * @adapter: board private structure
3728 **/
3729 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3730 {
3731 int i;
3732
3733 for (i = 0; i < adapter->num_tx_queues; i++)
3734 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3735 }
3736
3737 void ixgbe_down(struct ixgbe_adapter *adapter)
3738 {
3739 struct net_device *netdev = adapter->netdev;
3740 struct ixgbe_hw *hw = &adapter->hw;
3741 u32 rxctrl;
3742 u32 txdctl;
3743 int i, j;
3744
3745 /* signal that we are down to the interrupt handler */
3746 set_bit(__IXGBE_DOWN, &adapter->state);
3747
3748 /* disable receive for all VFs and wait one second */
3749 if (adapter->num_vfs) {
3750 /* ping all the active vfs to let them know we are going down */
3751 ixgbe_ping_all_vfs(adapter);
3752
3753 /* Disable all VFTE/VFRE TX/RX */
3754 ixgbe_disable_tx_rx(adapter);
3755
3756 /* Mark all the VFs as inactive */
3757 for (i = 0 ; i < adapter->num_vfs; i++)
3758 adapter->vfinfo[i].clear_to_send = 0;
3759 }
3760
3761 /* disable receives */
3762 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3763 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3764
3765 IXGBE_WRITE_FLUSH(hw);
3766 msleep(10);
3767
3768 netif_tx_stop_all_queues(netdev);
3769
3770 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3771 del_timer_sync(&adapter->sfp_timer);
3772 del_timer_sync(&adapter->watchdog_timer);
3773 cancel_work_sync(&adapter->watchdog_task);
3774
3775 netif_carrier_off(netdev);
3776 netif_tx_disable(netdev);
3777
3778 ixgbe_irq_disable(adapter);
3779
3780 ixgbe_napi_disable_all(adapter);
3781
3782 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3783 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3784 cancel_work_sync(&adapter->fdir_reinit_task);
3785
3786 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3787 cancel_work_sync(&adapter->check_overtemp_task);
3788
3789 /* disable transmits in the hardware now that interrupts are off */
3790 for (i = 0; i < adapter->num_tx_queues; i++) {
3791 j = adapter->tx_ring[i]->reg_idx;
3792 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3793 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3794 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3795 }
3796 /* Disable the Tx DMA engine on 82599 */
3797 if (hw->mac.type == ixgbe_mac_82599EB)
3798 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3799 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3800 ~IXGBE_DMATXCTL_TE));
3801
3802 /* power down the optics */
3803 if (hw->phy.multispeed_fiber)
3804 hw->mac.ops.disable_tx_laser(hw);
3805
3806 /* clear n-tuple filters that are cached */
3807 ethtool_ntuple_flush(netdev);
3808
3809 if (!pci_channel_offline(adapter->pdev))
3810 ixgbe_reset(adapter);
3811 ixgbe_clean_all_tx_rings(adapter);
3812 ixgbe_clean_all_rx_rings(adapter);
3813
3814 #ifdef CONFIG_IXGBE_DCA
3815 /* since we reset the hardware DCA settings were cleared */
3816 ixgbe_setup_dca(adapter);
3817 #endif
3818 }
3819
3820 /**
3821 * ixgbe_poll - NAPI Rx polling callback
3822 * @napi: structure for representing this polling device
3823 * @budget: how many packets driver is allowed to clean
3824 *
3825 * This function is used for legacy and MSI, NAPI mode
3826 **/
3827 static int ixgbe_poll(struct napi_struct *napi, int budget)
3828 {
3829 struct ixgbe_q_vector *q_vector =
3830 container_of(napi, struct ixgbe_q_vector, napi);
3831 struct ixgbe_adapter *adapter = q_vector->adapter;
3832 int tx_clean_complete, work_done = 0;
3833
3834 #ifdef CONFIG_IXGBE_DCA
3835 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3836 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3837 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3838 }
3839 #endif
3840
3841 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3842 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3843
3844 if (!tx_clean_complete)
3845 work_done = budget;
3846
3847 /* If budget not fully consumed, exit the polling mode */
3848 if (work_done < budget) {
3849 napi_complete(napi);
3850 if (adapter->rx_itr_setting & 1)
3851 ixgbe_set_itr(adapter);
3852 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3853 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3854 }
3855 return work_done;
3856 }
3857
3858 /**
3859 * ixgbe_tx_timeout - Respond to a Tx Hang
3860 * @netdev: network interface device structure
3861 **/
3862 static void ixgbe_tx_timeout(struct net_device *netdev)
3863 {
3864 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3865
3866 /* Do the reset outside of interrupt context */
3867 schedule_work(&adapter->reset_task);
3868 }
3869
3870 static void ixgbe_reset_task(struct work_struct *work)
3871 {
3872 struct ixgbe_adapter *adapter;
3873 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3874
3875 /* If we're already down or resetting, just bail */
3876 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3877 test_bit(__IXGBE_RESETTING, &adapter->state))
3878 return;
3879
3880 adapter->tx_timeout_count++;
3881
3882 ixgbe_dump(adapter);
3883 netdev_err(adapter->netdev, "Reset adapter\n");
3884 ixgbe_reinit_locked(adapter);
3885 }
3886
3887 #ifdef CONFIG_IXGBE_DCB
3888 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3889 {
3890 bool ret = false;
3891 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3892
3893 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3894 return ret;
3895
3896 f->mask = 0x7 << 3;
3897 adapter->num_rx_queues = f->indices;
3898 adapter->num_tx_queues = f->indices;
3899 ret = true;
3900
3901 return ret;
3902 }
3903 #endif
3904
3905 /**
3906 * ixgbe_set_rss_queues: Allocate queues for RSS
3907 * @adapter: board private structure to initialize
3908 *
3909 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3910 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3911 *
3912 **/
3913 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3914 {
3915 bool ret = false;
3916 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3917
3918 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3919 f->mask = 0xF;
3920 adapter->num_rx_queues = f->indices;
3921 adapter->num_tx_queues = f->indices;
3922 ret = true;
3923 } else {
3924 ret = false;
3925 }
3926
3927 return ret;
3928 }
3929
3930 /**
3931 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3932 * @adapter: board private structure to initialize
3933 *
3934 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3935 * to the original CPU that initiated the Tx session. This runs in addition
3936 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3937 * Rx load across CPUs using RSS.
3938 *
3939 **/
3940 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3941 {
3942 bool ret = false;
3943 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3944
3945 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3946 f_fdir->mask = 0;
3947
3948 /* Flow Director must have RSS enabled */
3949 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3950 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3951 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3952 adapter->num_tx_queues = f_fdir->indices;
3953 adapter->num_rx_queues = f_fdir->indices;
3954 ret = true;
3955 } else {
3956 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3957 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3958 }
3959 return ret;
3960 }
3961
3962 #ifdef IXGBE_FCOE
3963 /**
3964 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3965 * @adapter: board private structure to initialize
3966 *
3967 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3968 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3969 * rx queues out of the max number of rx queues, instead, it is used as the
3970 * index of the first rx queue used by FCoE.
3971 *
3972 **/
3973 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3974 {
3975 bool ret = false;
3976 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3977
3978 f->indices = min((int)num_online_cpus(), f->indices);
3979 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3980 adapter->num_rx_queues = 1;
3981 adapter->num_tx_queues = 1;
3982 #ifdef CONFIG_IXGBE_DCB
3983 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3984 e_info(probe, "FCoE enabled with DCB\n");
3985 ixgbe_set_dcb_queues(adapter);
3986 }
3987 #endif
3988 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3989 e_info(probe, "FCoE enabled with RSS\n");
3990 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3991 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3992 ixgbe_set_fdir_queues(adapter);
3993 else
3994 ixgbe_set_rss_queues(adapter);
3995 }
3996 /* adding FCoE rx rings to the end */
3997 f->mask = adapter->num_rx_queues;
3998 adapter->num_rx_queues += f->indices;
3999 adapter->num_tx_queues += f->indices;
4000
4001 ret = true;
4002 }
4003
4004 return ret;
4005 }
4006
4007 #endif /* IXGBE_FCOE */
4008 /**
4009 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4010 * @adapter: board private structure to initialize
4011 *
4012 * IOV doesn't actually use anything, so just NAK the
4013 * request for now and let the other queue routines
4014 * figure out what to do.
4015 */
4016 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4017 {
4018 return false;
4019 }
4020
4021 /*
4022 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4023 * @adapter: board private structure to initialize
4024 *
4025 * This is the top level queue allocation routine. The order here is very
4026 * important, starting with the "most" number of features turned on at once,
4027 * and ending with the smallest set of features. This way large combinations
4028 * can be allocated if they're turned on, and smaller combinations are the
4029 * fallthrough conditions.
4030 *
4031 **/
4032 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4033 {
4034 /* Start with base case */
4035 adapter->num_rx_queues = 1;
4036 adapter->num_tx_queues = 1;
4037 adapter->num_rx_pools = adapter->num_rx_queues;
4038 adapter->num_rx_queues_per_pool = 1;
4039
4040 if (ixgbe_set_sriov_queues(adapter))
4041 return;
4042
4043 #ifdef IXGBE_FCOE
4044 if (ixgbe_set_fcoe_queues(adapter))
4045 goto done;
4046
4047 #endif /* IXGBE_FCOE */
4048 #ifdef CONFIG_IXGBE_DCB
4049 if (ixgbe_set_dcb_queues(adapter))
4050 goto done;
4051
4052 #endif
4053 if (ixgbe_set_fdir_queues(adapter))
4054 goto done;
4055
4056 if (ixgbe_set_rss_queues(adapter))
4057 goto done;
4058
4059 /* fallback to base case */
4060 adapter->num_rx_queues = 1;
4061 adapter->num_tx_queues = 1;
4062
4063 done:
4064 /* Notify the stack of the (possibly) reduced Tx Queue count. */
4065 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4066 }
4067
4068 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4069 int vectors)
4070 {
4071 int err, vector_threshold;
4072
4073 /* We'll want at least 3 (vector_threshold):
4074 * 1) TxQ[0] Cleanup
4075 * 2) RxQ[0] Cleanup
4076 * 3) Other (Link Status Change, etc.)
4077 * 4) TCP Timer (optional)
4078 */
4079 vector_threshold = MIN_MSIX_COUNT;
4080
4081 /* The more we get, the more we will assign to Tx/Rx Cleanup
4082 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4083 * Right now, we simply care about how many we'll get; we'll
4084 * set them up later while requesting irq's.
4085 */
4086 while (vectors >= vector_threshold) {
4087 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4088 vectors);
4089 if (!err) /* Success in acquiring all requested vectors. */
4090 break;
4091 else if (err < 0)
4092 vectors = 0; /* Nasty failure, quit now */
4093 else /* err == number of vectors we should try again with */
4094 vectors = err;
4095 }
4096
4097 if (vectors < vector_threshold) {
4098 /* Can't allocate enough MSI-X interrupts? Oh well.
4099 * This just means we'll go with either a single MSI
4100 * vector or fall back to legacy interrupts.
4101 */
4102 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4103 "Unable to allocate MSI-X interrupts\n");
4104 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4105 kfree(adapter->msix_entries);
4106 adapter->msix_entries = NULL;
4107 } else {
4108 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4109 /*
4110 * Adjust for only the vectors we'll use, which is minimum
4111 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4112 * vectors we were allocated.
4113 */
4114 adapter->num_msix_vectors = min(vectors,
4115 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4116 }
4117 }
4118
4119 /**
4120 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4121 * @adapter: board private structure to initialize
4122 *
4123 * Cache the descriptor ring offsets for RSS to the assigned rings.
4124 *
4125 **/
4126 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4127 {
4128 int i;
4129 bool ret = false;
4130
4131 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4132 for (i = 0; i < adapter->num_rx_queues; i++)
4133 adapter->rx_ring[i]->reg_idx = i;
4134 for (i = 0; i < adapter->num_tx_queues; i++)
4135 adapter->tx_ring[i]->reg_idx = i;
4136 ret = true;
4137 } else {
4138 ret = false;
4139 }
4140
4141 return ret;
4142 }
4143
4144 #ifdef CONFIG_IXGBE_DCB
4145 /**
4146 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4147 * @adapter: board private structure to initialize
4148 *
4149 * Cache the descriptor ring offsets for DCB to the assigned rings.
4150 *
4151 **/
4152 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4153 {
4154 int i;
4155 bool ret = false;
4156 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4157
4158 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4159 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4160 /* the number of queues is assumed to be symmetric */
4161 for (i = 0; i < dcb_i; i++) {
4162 adapter->rx_ring[i]->reg_idx = i << 3;
4163 adapter->tx_ring[i]->reg_idx = i << 2;
4164 }
4165 ret = true;
4166 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4167 if (dcb_i == 8) {
4168 /*
4169 * Tx TC0 starts at: descriptor queue 0
4170 * Tx TC1 starts at: descriptor queue 32
4171 * Tx TC2 starts at: descriptor queue 64
4172 * Tx TC3 starts at: descriptor queue 80
4173 * Tx TC4 starts at: descriptor queue 96
4174 * Tx TC5 starts at: descriptor queue 104
4175 * Tx TC6 starts at: descriptor queue 112
4176 * Tx TC7 starts at: descriptor queue 120
4177 *
4178 * Rx TC0-TC7 are offset by 16 queues each
4179 */
4180 for (i = 0; i < 3; i++) {
4181 adapter->tx_ring[i]->reg_idx = i << 5;
4182 adapter->rx_ring[i]->reg_idx = i << 4;
4183 }
4184 for ( ; i < 5; i++) {
4185 adapter->tx_ring[i]->reg_idx =
4186 ((i + 2) << 4);
4187 adapter->rx_ring[i]->reg_idx = i << 4;
4188 }
4189 for ( ; i < dcb_i; i++) {
4190 adapter->tx_ring[i]->reg_idx =
4191 ((i + 8) << 3);
4192 adapter->rx_ring[i]->reg_idx = i << 4;
4193 }
4194
4195 ret = true;
4196 } else if (dcb_i == 4) {
4197 /*
4198 * Tx TC0 starts at: descriptor queue 0
4199 * Tx TC1 starts at: descriptor queue 64
4200 * Tx TC2 starts at: descriptor queue 96
4201 * Tx TC3 starts at: descriptor queue 112
4202 *
4203 * Rx TC0-TC3 are offset by 32 queues each
4204 */
4205 adapter->tx_ring[0]->reg_idx = 0;
4206 adapter->tx_ring[1]->reg_idx = 64;
4207 adapter->tx_ring[2]->reg_idx = 96;
4208 adapter->tx_ring[3]->reg_idx = 112;
4209 for (i = 0 ; i < dcb_i; i++)
4210 adapter->rx_ring[i]->reg_idx = i << 5;
4211
4212 ret = true;
4213 } else {
4214 ret = false;
4215 }
4216 } else {
4217 ret = false;
4218 }
4219 } else {
4220 ret = false;
4221 }
4222
4223 return ret;
4224 }
4225 #endif
4226
4227 /**
4228 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4229 * @adapter: board private structure to initialize
4230 *
4231 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4232 *
4233 **/
4234 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4235 {
4236 int i;
4237 bool ret = false;
4238
4239 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4240 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4241 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4242 for (i = 0; i < adapter->num_rx_queues; i++)
4243 adapter->rx_ring[i]->reg_idx = i;
4244 for (i = 0; i < adapter->num_tx_queues; i++)
4245 adapter->tx_ring[i]->reg_idx = i;
4246 ret = true;
4247 }
4248
4249 return ret;
4250 }
4251
4252 #ifdef IXGBE_FCOE
4253 /**
4254 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4255 * @adapter: board private structure to initialize
4256 *
4257 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4258 *
4259 */
4260 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4261 {
4262 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4263 bool ret = false;
4264 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4265
4266 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4267 #ifdef CONFIG_IXGBE_DCB
4268 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4269 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4270
4271 ixgbe_cache_ring_dcb(adapter);
4272 /* find out queues in TC for FCoE */
4273 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4274 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4275 /*
4276 * In 82599, the number of Tx queues for each traffic
4277 * class for both 8-TC and 4-TC modes are:
4278 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4279 * 8 TCs: 32 32 16 16 8 8 8 8
4280 * 4 TCs: 64 64 32 32
4281 * We have max 8 queues for FCoE, where 8 the is
4282 * FCoE redirection table size. If TC for FCoE is
4283 * less than or equal to TC3, we have enough queues
4284 * to add max of 8 queues for FCoE, so we start FCoE
4285 * tx descriptor from the next one, i.e., reg_idx + 1.
4286 * If TC for FCoE is above TC3, implying 8 TC mode,
4287 * and we need 8 for FCoE, we have to take all queues
4288 * in that traffic class for FCoE.
4289 */
4290 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4291 fcoe_tx_i--;
4292 }
4293 #endif /* CONFIG_IXGBE_DCB */
4294 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4295 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4296 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4297 ixgbe_cache_ring_fdir(adapter);
4298 else
4299 ixgbe_cache_ring_rss(adapter);
4300
4301 fcoe_rx_i = f->mask;
4302 fcoe_tx_i = f->mask;
4303 }
4304 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4305 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4306 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4307 }
4308 ret = true;
4309 }
4310 return ret;
4311 }
4312
4313 #endif /* IXGBE_FCOE */
4314 /**
4315 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4316 * @adapter: board private structure to initialize
4317 *
4318 * SR-IOV doesn't use any descriptor rings but changes the default if
4319 * no other mapping is used.
4320 *
4321 */
4322 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4323 {
4324 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4325 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4326 if (adapter->num_vfs)
4327 return true;
4328 else
4329 return false;
4330 }
4331
4332 /**
4333 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4334 * @adapter: board private structure to initialize
4335 *
4336 * Once we know the feature-set enabled for the device, we'll cache
4337 * the register offset the descriptor ring is assigned to.
4338 *
4339 * Note, the order the various feature calls is important. It must start with
4340 * the "most" features enabled at the same time, then trickle down to the
4341 * least amount of features turned on at once.
4342 **/
4343 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4344 {
4345 /* start with default case */
4346 adapter->rx_ring[0]->reg_idx = 0;
4347 adapter->tx_ring[0]->reg_idx = 0;
4348
4349 if (ixgbe_cache_ring_sriov(adapter))
4350 return;
4351
4352 #ifdef IXGBE_FCOE
4353 if (ixgbe_cache_ring_fcoe(adapter))
4354 return;
4355
4356 #endif /* IXGBE_FCOE */
4357 #ifdef CONFIG_IXGBE_DCB
4358 if (ixgbe_cache_ring_dcb(adapter))
4359 return;
4360
4361 #endif
4362 if (ixgbe_cache_ring_fdir(adapter))
4363 return;
4364
4365 if (ixgbe_cache_ring_rss(adapter))
4366 return;
4367 }
4368
4369 /**
4370 * ixgbe_alloc_queues - Allocate memory for all rings
4371 * @adapter: board private structure to initialize
4372 *
4373 * We allocate one ring per queue at run-time since we don't know the
4374 * number of queues at compile-time. The polling_netdev array is
4375 * intended for Multiqueue, but should work fine with a single queue.
4376 **/
4377 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4378 {
4379 int i;
4380 int orig_node = adapter->node;
4381
4382 for (i = 0; i < adapter->num_tx_queues; i++) {
4383 struct ixgbe_ring *ring = adapter->tx_ring[i];
4384 if (orig_node == -1) {
4385 int cur_node = next_online_node(adapter->node);
4386 if (cur_node == MAX_NUMNODES)
4387 cur_node = first_online_node;
4388 adapter->node = cur_node;
4389 }
4390 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4391 adapter->node);
4392 if (!ring)
4393 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4394 if (!ring)
4395 goto err_tx_ring_allocation;
4396 ring->count = adapter->tx_ring_count;
4397 ring->queue_index = i;
4398 ring->numa_node = adapter->node;
4399
4400 adapter->tx_ring[i] = ring;
4401 }
4402
4403 /* Restore the adapter's original node */
4404 adapter->node = orig_node;
4405
4406 for (i = 0; i < adapter->num_rx_queues; i++) {
4407 struct ixgbe_ring *ring = adapter->rx_ring[i];
4408 if (orig_node == -1) {
4409 int cur_node = next_online_node(adapter->node);
4410 if (cur_node == MAX_NUMNODES)
4411 cur_node = first_online_node;
4412 adapter->node = cur_node;
4413 }
4414 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4415 adapter->node);
4416 if (!ring)
4417 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4418 if (!ring)
4419 goto err_rx_ring_allocation;
4420 ring->count = adapter->rx_ring_count;
4421 ring->queue_index = i;
4422 ring->numa_node = adapter->node;
4423
4424 adapter->rx_ring[i] = ring;
4425 }
4426
4427 /* Restore the adapter's original node */
4428 adapter->node = orig_node;
4429
4430 ixgbe_cache_ring_register(adapter);
4431
4432 return 0;
4433
4434 err_rx_ring_allocation:
4435 for (i = 0; i < adapter->num_tx_queues; i++)
4436 kfree(adapter->tx_ring[i]);
4437 err_tx_ring_allocation:
4438 return -ENOMEM;
4439 }
4440
4441 /**
4442 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4443 * @adapter: board private structure to initialize
4444 *
4445 * Attempt to configure the interrupts using the best available
4446 * capabilities of the hardware and the kernel.
4447 **/
4448 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4449 {
4450 struct ixgbe_hw *hw = &adapter->hw;
4451 int err = 0;
4452 int vector, v_budget;
4453
4454 /*
4455 * It's easy to be greedy for MSI-X vectors, but it really
4456 * doesn't do us much good if we have a lot more vectors
4457 * than CPU's. So let's be conservative and only ask for
4458 * (roughly) the same number of vectors as there are CPU's.
4459 */
4460 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4461 (int)num_online_cpus()) + NON_Q_VECTORS;
4462
4463 /*
4464 * At the same time, hardware can only support a maximum of
4465 * hw.mac->max_msix_vectors vectors. With features
4466 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4467 * descriptor queues supported by our device. Thus, we cap it off in
4468 * those rare cases where the cpu count also exceeds our vector limit.
4469 */
4470 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4471
4472 /* A failure in MSI-X entry allocation isn't fatal, but it does
4473 * mean we disable MSI-X capabilities of the adapter. */
4474 adapter->msix_entries = kcalloc(v_budget,
4475 sizeof(struct msix_entry), GFP_KERNEL);
4476 if (adapter->msix_entries) {
4477 for (vector = 0; vector < v_budget; vector++)
4478 adapter->msix_entries[vector].entry = vector;
4479
4480 ixgbe_acquire_msix_vectors(adapter, v_budget);
4481
4482 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4483 goto out;
4484 }
4485
4486 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4487 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4488 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4489 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4490 adapter->atr_sample_rate = 0;
4491 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4492 ixgbe_disable_sriov(adapter);
4493
4494 ixgbe_set_num_queues(adapter);
4495
4496 err = pci_enable_msi(adapter->pdev);
4497 if (!err) {
4498 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4499 } else {
4500 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4501 "Unable to allocate MSI interrupt, "
4502 "falling back to legacy. Error: %d\n", err);
4503 /* reset err */
4504 err = 0;
4505 }
4506
4507 out:
4508 return err;
4509 }
4510
4511 /**
4512 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4513 * @adapter: board private structure to initialize
4514 *
4515 * We allocate one q_vector per queue interrupt. If allocation fails we
4516 * return -ENOMEM.
4517 **/
4518 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4519 {
4520 int q_idx, num_q_vectors;
4521 struct ixgbe_q_vector *q_vector;
4522 int napi_vectors;
4523 int (*poll)(struct napi_struct *, int);
4524
4525 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4526 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4527 napi_vectors = adapter->num_rx_queues;
4528 poll = &ixgbe_clean_rxtx_many;
4529 } else {
4530 num_q_vectors = 1;
4531 napi_vectors = 1;
4532 poll = &ixgbe_poll;
4533 }
4534
4535 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4536 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4537 GFP_KERNEL, adapter->node);
4538 if (!q_vector)
4539 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4540 GFP_KERNEL);
4541 if (!q_vector)
4542 goto err_out;
4543 q_vector->adapter = adapter;
4544 if (q_vector->txr_count && !q_vector->rxr_count)
4545 q_vector->eitr = adapter->tx_eitr_param;
4546 else
4547 q_vector->eitr = adapter->rx_eitr_param;
4548 q_vector->v_idx = q_idx;
4549 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4550 adapter->q_vector[q_idx] = q_vector;
4551 }
4552
4553 return 0;
4554
4555 err_out:
4556 while (q_idx) {
4557 q_idx--;
4558 q_vector = adapter->q_vector[q_idx];
4559 netif_napi_del(&q_vector->napi);
4560 kfree(q_vector);
4561 adapter->q_vector[q_idx] = NULL;
4562 }
4563 return -ENOMEM;
4564 }
4565
4566 /**
4567 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4568 * @adapter: board private structure to initialize
4569 *
4570 * This function frees the memory allocated to the q_vectors. In addition if
4571 * NAPI is enabled it will delete any references to the NAPI struct prior
4572 * to freeing the q_vector.
4573 **/
4574 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4575 {
4576 int q_idx, num_q_vectors;
4577
4578 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4579 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4580 else
4581 num_q_vectors = 1;
4582
4583 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4584 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4585 adapter->q_vector[q_idx] = NULL;
4586 netif_napi_del(&q_vector->napi);
4587 kfree(q_vector);
4588 }
4589 }
4590
4591 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4592 {
4593 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4594 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4595 pci_disable_msix(adapter->pdev);
4596 kfree(adapter->msix_entries);
4597 adapter->msix_entries = NULL;
4598 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4599 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4600 pci_disable_msi(adapter->pdev);
4601 }
4602 }
4603
4604 /**
4605 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4606 * @adapter: board private structure to initialize
4607 *
4608 * We determine which interrupt scheme to use based on...
4609 * - Kernel support (MSI, MSI-X)
4610 * - which can be user-defined (via MODULE_PARAM)
4611 * - Hardware queue count (num_*_queues)
4612 * - defined by miscellaneous hardware support/features (RSS, etc.)
4613 **/
4614 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4615 {
4616 int err;
4617
4618 /* Number of supported queues */
4619 ixgbe_set_num_queues(adapter);
4620
4621 err = ixgbe_set_interrupt_capability(adapter);
4622 if (err) {
4623 e_dev_err("Unable to setup interrupt capabilities\n");
4624 goto err_set_interrupt;
4625 }
4626
4627 err = ixgbe_alloc_q_vectors(adapter);
4628 if (err) {
4629 e_dev_err("Unable to allocate memory for queue vectors\n");
4630 goto err_alloc_q_vectors;
4631 }
4632
4633 err = ixgbe_alloc_queues(adapter);
4634 if (err) {
4635 e_dev_err("Unable to allocate memory for queues\n");
4636 goto err_alloc_queues;
4637 }
4638
4639 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4640 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4641 adapter->num_rx_queues, adapter->num_tx_queues);
4642
4643 set_bit(__IXGBE_DOWN, &adapter->state);
4644
4645 return 0;
4646
4647 err_alloc_queues:
4648 ixgbe_free_q_vectors(adapter);
4649 err_alloc_q_vectors:
4650 ixgbe_reset_interrupt_capability(adapter);
4651 err_set_interrupt:
4652 return err;
4653 }
4654
4655 /**
4656 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4657 * @adapter: board private structure to clear interrupt scheme on
4658 *
4659 * We go through and clear interrupt specific resources and reset the structure
4660 * to pre-load conditions
4661 **/
4662 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4663 {
4664 int i;
4665
4666 for (i = 0; i < adapter->num_tx_queues; i++) {
4667 kfree(adapter->tx_ring[i]);
4668 adapter->tx_ring[i] = NULL;
4669 }
4670 for (i = 0; i < adapter->num_rx_queues; i++) {
4671 kfree(adapter->rx_ring[i]);
4672 adapter->rx_ring[i] = NULL;
4673 }
4674
4675 ixgbe_free_q_vectors(adapter);
4676 ixgbe_reset_interrupt_capability(adapter);
4677 }
4678
4679 /**
4680 * ixgbe_sfp_timer - worker thread to find a missing module
4681 * @data: pointer to our adapter struct
4682 **/
4683 static void ixgbe_sfp_timer(unsigned long data)
4684 {
4685 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4686
4687 /*
4688 * Do the sfp_timer outside of interrupt context due to the
4689 * delays that sfp+ detection requires
4690 */
4691 schedule_work(&adapter->sfp_task);
4692 }
4693
4694 /**
4695 * ixgbe_sfp_task - worker thread to find a missing module
4696 * @work: pointer to work_struct containing our data
4697 **/
4698 static void ixgbe_sfp_task(struct work_struct *work)
4699 {
4700 struct ixgbe_adapter *adapter = container_of(work,
4701 struct ixgbe_adapter,
4702 sfp_task);
4703 struct ixgbe_hw *hw = &adapter->hw;
4704
4705 if ((hw->phy.type == ixgbe_phy_nl) &&
4706 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4707 s32 ret = hw->phy.ops.identify_sfp(hw);
4708 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4709 goto reschedule;
4710 ret = hw->phy.ops.reset(hw);
4711 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4712 e_dev_err("failed to initialize because an unsupported "
4713 "SFP+ module type was detected.\n");
4714 e_dev_err("Reload the driver after installing a "
4715 "supported module.\n");
4716 unregister_netdev(adapter->netdev);
4717 } else {
4718 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4719 }
4720 /* don't need this routine any more */
4721 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4722 }
4723 return;
4724 reschedule:
4725 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4726 mod_timer(&adapter->sfp_timer,
4727 round_jiffies(jiffies + (2 * HZ)));
4728 }
4729
4730 /**
4731 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4732 * @adapter: board private structure to initialize
4733 *
4734 * ixgbe_sw_init initializes the Adapter private data structure.
4735 * Fields are initialized based on PCI device information and
4736 * OS network device settings (MTU size).
4737 **/
4738 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4739 {
4740 struct ixgbe_hw *hw = &adapter->hw;
4741 struct pci_dev *pdev = adapter->pdev;
4742 struct net_device *dev = adapter->netdev;
4743 unsigned int rss;
4744 #ifdef CONFIG_IXGBE_DCB
4745 int j;
4746 struct tc_configuration *tc;
4747 #endif
4748
4749 /* PCI config space info */
4750
4751 hw->vendor_id = pdev->vendor;
4752 hw->device_id = pdev->device;
4753 hw->revision_id = pdev->revision;
4754 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4755 hw->subsystem_device_id = pdev->subsystem_device;
4756
4757 /* Set capability flags */
4758 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4759 adapter->ring_feature[RING_F_RSS].indices = rss;
4760 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4761 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4762 if (hw->mac.type == ixgbe_mac_82598EB) {
4763 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4764 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4765 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4766 } else if (hw->mac.type == ixgbe_mac_82599EB) {
4767 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4768 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4769 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4770 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4771 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4772 if (dev->features & NETIF_F_NTUPLE) {
4773 /* Flow Director perfect filter enabled */
4774 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4775 adapter->atr_sample_rate = 0;
4776 spin_lock_init(&adapter->fdir_perfect_lock);
4777 } else {
4778 /* Flow Director hash filters enabled */
4779 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4780 adapter->atr_sample_rate = 20;
4781 }
4782 adapter->ring_feature[RING_F_FDIR].indices =
4783 IXGBE_MAX_FDIR_INDICES;
4784 adapter->fdir_pballoc = 0;
4785 #ifdef IXGBE_FCOE
4786 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4787 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4788 adapter->ring_feature[RING_F_FCOE].indices = 0;
4789 #ifdef CONFIG_IXGBE_DCB
4790 /* Default traffic class to use for FCoE */
4791 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4792 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4793 #endif
4794 #endif /* IXGBE_FCOE */
4795 }
4796
4797 #ifdef CONFIG_IXGBE_DCB
4798 /* Configure DCB traffic classes */
4799 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4800 tc = &adapter->dcb_cfg.tc_config[j];
4801 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4802 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4803 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4804 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4805 tc->dcb_pfc = pfc_disabled;
4806 }
4807 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4808 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4809 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4810 adapter->dcb_cfg.pfc_mode_enable = false;
4811 adapter->dcb_cfg.round_robin_enable = false;
4812 adapter->dcb_set_bitmap = 0x00;
4813 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4814 adapter->ring_feature[RING_F_DCB].indices);
4815
4816 #endif
4817
4818 /* default flow control settings */
4819 hw->fc.requested_mode = ixgbe_fc_full;
4820 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4821 #ifdef CONFIG_DCB
4822 adapter->last_lfc_mode = hw->fc.current_mode;
4823 #endif
4824 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4825 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4826 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4827 hw->fc.send_xon = true;
4828 hw->fc.disable_fc_autoneg = false;
4829
4830 /* enable itr by default in dynamic mode */
4831 adapter->rx_itr_setting = 1;
4832 adapter->rx_eitr_param = 20000;
4833 adapter->tx_itr_setting = 1;
4834 adapter->tx_eitr_param = 10000;
4835
4836 /* set defaults for eitr in MegaBytes */
4837 adapter->eitr_low = 10;
4838 adapter->eitr_high = 20;
4839
4840 /* set default ring sizes */
4841 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4842 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4843
4844 /* initialize eeprom parameters */
4845 if (ixgbe_init_eeprom_params_generic(hw)) {
4846 e_dev_err("EEPROM initialization failed\n");
4847 return -EIO;
4848 }
4849
4850 /* enable rx csum by default */
4851 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4852
4853 /* get assigned NUMA node */
4854 adapter->node = dev_to_node(&pdev->dev);
4855
4856 set_bit(__IXGBE_DOWN, &adapter->state);
4857
4858 return 0;
4859 }
4860
4861 /**
4862 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4863 * @adapter: board private structure
4864 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4865 *
4866 * Return 0 on success, negative on failure
4867 **/
4868 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4869 struct ixgbe_ring *tx_ring)
4870 {
4871 struct pci_dev *pdev = adapter->pdev;
4872 int size;
4873
4874 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4875 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4876 if (!tx_ring->tx_buffer_info)
4877 tx_ring->tx_buffer_info = vmalloc(size);
4878 if (!tx_ring->tx_buffer_info)
4879 goto err;
4880 memset(tx_ring->tx_buffer_info, 0, size);
4881
4882 /* round up to nearest 4K */
4883 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4884 tx_ring->size = ALIGN(tx_ring->size, 4096);
4885
4886 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4887 &tx_ring->dma, GFP_KERNEL);
4888 if (!tx_ring->desc)
4889 goto err;
4890
4891 tx_ring->next_to_use = 0;
4892 tx_ring->next_to_clean = 0;
4893 tx_ring->work_limit = tx_ring->count;
4894 return 0;
4895
4896 err:
4897 vfree(tx_ring->tx_buffer_info);
4898 tx_ring->tx_buffer_info = NULL;
4899 e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
4900 return -ENOMEM;
4901 }
4902
4903 /**
4904 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4905 * @adapter: board private structure
4906 *
4907 * If this function returns with an error, then it's possible one or
4908 * more of the rings is populated (while the rest are not). It is the
4909 * callers duty to clean those orphaned rings.
4910 *
4911 * Return 0 on success, negative on failure
4912 **/
4913 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4914 {
4915 int i, err = 0;
4916
4917 for (i = 0; i < adapter->num_tx_queues; i++) {
4918 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
4919 if (!err)
4920 continue;
4921 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4922 break;
4923 }
4924
4925 return err;
4926 }
4927
4928 /**
4929 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4930 * @adapter: board private structure
4931 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4932 *
4933 * Returns 0 on success, negative on failure
4934 **/
4935 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
4936 struct ixgbe_ring *rx_ring)
4937 {
4938 struct pci_dev *pdev = adapter->pdev;
4939 int size;
4940
4941 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4942 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
4943 if (!rx_ring->rx_buffer_info)
4944 rx_ring->rx_buffer_info = vmalloc(size);
4945 if (!rx_ring->rx_buffer_info) {
4946 e_err(probe, "vmalloc allocation failed for the Rx "
4947 "descriptor ring\n");
4948 goto alloc_failed;
4949 }
4950 memset(rx_ring->rx_buffer_info, 0, size);
4951
4952 /* Round up to nearest 4K */
4953 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4954 rx_ring->size = ALIGN(rx_ring->size, 4096);
4955
4956 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
4957 &rx_ring->dma, GFP_KERNEL);
4958
4959 if (!rx_ring->desc) {
4960 e_err(probe, "Memory allocation failed for the Rx "
4961 "descriptor ring\n");
4962 vfree(rx_ring->rx_buffer_info);
4963 goto alloc_failed;
4964 }
4965
4966 rx_ring->next_to_clean = 0;
4967 rx_ring->next_to_use = 0;
4968
4969 return 0;
4970
4971 alloc_failed:
4972 return -ENOMEM;
4973 }
4974
4975 /**
4976 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4977 * @adapter: board private structure
4978 *
4979 * If this function returns with an error, then it's possible one or
4980 * more of the rings is populated (while the rest are not). It is the
4981 * callers duty to clean those orphaned rings.
4982 *
4983 * Return 0 on success, negative on failure
4984 **/
4985
4986 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4987 {
4988 int i, err = 0;
4989
4990 for (i = 0; i < adapter->num_rx_queues; i++) {
4991 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
4992 if (!err)
4993 continue;
4994 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
4995 break;
4996 }
4997
4998 return err;
4999 }
5000
5001 /**
5002 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5003 * @adapter: board private structure
5004 * @tx_ring: Tx descriptor ring for a specific queue
5005 *
5006 * Free all transmit software resources
5007 **/
5008 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
5009 struct ixgbe_ring *tx_ring)
5010 {
5011 struct pci_dev *pdev = adapter->pdev;
5012
5013 ixgbe_clean_tx_ring(adapter, tx_ring);
5014
5015 vfree(tx_ring->tx_buffer_info);
5016 tx_ring->tx_buffer_info = NULL;
5017
5018 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5019 tx_ring->dma);
5020
5021 tx_ring->desc = NULL;
5022 }
5023
5024 /**
5025 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5026 * @adapter: board private structure
5027 *
5028 * Free all transmit software resources
5029 **/
5030 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5031 {
5032 int i;
5033
5034 for (i = 0; i < adapter->num_tx_queues; i++)
5035 if (adapter->tx_ring[i]->desc)
5036 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
5037 }
5038
5039 /**
5040 * ixgbe_free_rx_resources - Free Rx Resources
5041 * @adapter: board private structure
5042 * @rx_ring: ring to clean the resources from
5043 *
5044 * Free all receive software resources
5045 **/
5046 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5047 struct ixgbe_ring *rx_ring)
5048 {
5049 struct pci_dev *pdev = adapter->pdev;
5050
5051 ixgbe_clean_rx_ring(adapter, rx_ring);
5052
5053 vfree(rx_ring->rx_buffer_info);
5054 rx_ring->rx_buffer_info = NULL;
5055
5056 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5057 rx_ring->dma);
5058
5059 rx_ring->desc = NULL;
5060 }
5061
5062 /**
5063 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5064 * @adapter: board private structure
5065 *
5066 * Free all receive software resources
5067 **/
5068 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5069 {
5070 int i;
5071
5072 for (i = 0; i < adapter->num_rx_queues; i++)
5073 if (adapter->rx_ring[i]->desc)
5074 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
5075 }
5076
5077 /**
5078 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5079 * @netdev: network interface device structure
5080 * @new_mtu: new value for maximum frame size
5081 *
5082 * Returns 0 on success, negative on failure
5083 **/
5084 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5085 {
5086 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5087 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5088
5089 /* MTU < 68 is an error and causes problems on some kernels */
5090 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5091 return -EINVAL;
5092
5093 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5094 /* must set new MTU before calling down or up */
5095 netdev->mtu = new_mtu;
5096
5097 if (netif_running(netdev))
5098 ixgbe_reinit_locked(adapter);
5099
5100 return 0;
5101 }
5102
5103 /**
5104 * ixgbe_open - Called when a network interface is made active
5105 * @netdev: network interface device structure
5106 *
5107 * Returns 0 on success, negative value on failure
5108 *
5109 * The open entry point is called when a network interface is made
5110 * active by the system (IFF_UP). At this point all resources needed
5111 * for transmit and receive operations are allocated, the interrupt
5112 * handler is registered with the OS, the watchdog timer is started,
5113 * and the stack is notified that the interface is ready.
5114 **/
5115 static int ixgbe_open(struct net_device *netdev)
5116 {
5117 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5118 int err;
5119
5120 /* disallow open during test */
5121 if (test_bit(__IXGBE_TESTING, &adapter->state))
5122 return -EBUSY;
5123
5124 netif_carrier_off(netdev);
5125
5126 /* allocate transmit descriptors */
5127 err = ixgbe_setup_all_tx_resources(adapter);
5128 if (err)
5129 goto err_setup_tx;
5130
5131 /* allocate receive descriptors */
5132 err = ixgbe_setup_all_rx_resources(adapter);
5133 if (err)
5134 goto err_setup_rx;
5135
5136 ixgbe_configure(adapter);
5137
5138 err = ixgbe_request_irq(adapter);
5139 if (err)
5140 goto err_req_irq;
5141
5142 err = ixgbe_up_complete(adapter);
5143 if (err)
5144 goto err_up;
5145
5146 netif_tx_start_all_queues(netdev);
5147
5148 return 0;
5149
5150 err_up:
5151 ixgbe_release_hw_control(adapter);
5152 ixgbe_free_irq(adapter);
5153 err_req_irq:
5154 err_setup_rx:
5155 ixgbe_free_all_rx_resources(adapter);
5156 err_setup_tx:
5157 ixgbe_free_all_tx_resources(adapter);
5158 ixgbe_reset(adapter);
5159
5160 return err;
5161 }
5162
5163 /**
5164 * ixgbe_close - Disables a network interface
5165 * @netdev: network interface device structure
5166 *
5167 * Returns 0, this is not allowed to fail
5168 *
5169 * The close entry point is called when an interface is de-activated
5170 * by the OS. The hardware is still under the drivers control, but
5171 * needs to be disabled. A global MAC reset is issued to stop the
5172 * hardware, and all transmit and receive resources are freed.
5173 **/
5174 static int ixgbe_close(struct net_device *netdev)
5175 {
5176 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5177
5178 ixgbe_down(adapter);
5179 ixgbe_free_irq(adapter);
5180
5181 ixgbe_free_all_tx_resources(adapter);
5182 ixgbe_free_all_rx_resources(adapter);
5183
5184 ixgbe_release_hw_control(adapter);
5185
5186 return 0;
5187 }
5188
5189 #ifdef CONFIG_PM
5190 static int ixgbe_resume(struct pci_dev *pdev)
5191 {
5192 struct net_device *netdev = pci_get_drvdata(pdev);
5193 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5194 u32 err;
5195
5196 pci_set_power_state(pdev, PCI_D0);
5197 pci_restore_state(pdev);
5198 /*
5199 * pci_restore_state clears dev->state_saved so call
5200 * pci_save_state to restore it.
5201 */
5202 pci_save_state(pdev);
5203
5204 err = pci_enable_device_mem(pdev);
5205 if (err) {
5206 e_dev_err("Cannot enable PCI device from suspend\n");
5207 return err;
5208 }
5209 pci_set_master(pdev);
5210
5211 pci_wake_from_d3(pdev, false);
5212
5213 err = ixgbe_init_interrupt_scheme(adapter);
5214 if (err) {
5215 e_dev_err("Cannot initialize interrupts for device\n");
5216 return err;
5217 }
5218
5219 ixgbe_reset(adapter);
5220
5221 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5222
5223 if (netif_running(netdev)) {
5224 err = ixgbe_open(adapter->netdev);
5225 if (err)
5226 return err;
5227 }
5228
5229 netif_device_attach(netdev);
5230
5231 return 0;
5232 }
5233 #endif /* CONFIG_PM */
5234
5235 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5236 {
5237 struct net_device *netdev = pci_get_drvdata(pdev);
5238 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5239 struct ixgbe_hw *hw = &adapter->hw;
5240 u32 ctrl, fctrl;
5241 u32 wufc = adapter->wol;
5242 #ifdef CONFIG_PM
5243 int retval = 0;
5244 #endif
5245
5246 netif_device_detach(netdev);
5247
5248 if (netif_running(netdev)) {
5249 ixgbe_down(adapter);
5250 ixgbe_free_irq(adapter);
5251 ixgbe_free_all_tx_resources(adapter);
5252 ixgbe_free_all_rx_resources(adapter);
5253 }
5254
5255 #ifdef CONFIG_PM
5256 retval = pci_save_state(pdev);
5257 if (retval)
5258 return retval;
5259
5260 #endif
5261 if (wufc) {
5262 ixgbe_set_rx_mode(netdev);
5263
5264 /* turn on all-multi mode if wake on multicast is enabled */
5265 if (wufc & IXGBE_WUFC_MC) {
5266 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5267 fctrl |= IXGBE_FCTRL_MPE;
5268 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5269 }
5270
5271 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5272 ctrl |= IXGBE_CTRL_GIO_DIS;
5273 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5274
5275 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5276 } else {
5277 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5278 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5279 }
5280
5281 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5282 pci_wake_from_d3(pdev, true);
5283 else
5284 pci_wake_from_d3(pdev, false);
5285
5286 *enable_wake = !!wufc;
5287
5288 ixgbe_clear_interrupt_scheme(adapter);
5289
5290 ixgbe_release_hw_control(adapter);
5291
5292 pci_disable_device(pdev);
5293
5294 return 0;
5295 }
5296
5297 #ifdef CONFIG_PM
5298 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5299 {
5300 int retval;
5301 bool wake;
5302
5303 retval = __ixgbe_shutdown(pdev, &wake);
5304 if (retval)
5305 return retval;
5306
5307 if (wake) {
5308 pci_prepare_to_sleep(pdev);
5309 } else {
5310 pci_wake_from_d3(pdev, false);
5311 pci_set_power_state(pdev, PCI_D3hot);
5312 }
5313
5314 return 0;
5315 }
5316 #endif /* CONFIG_PM */
5317
5318 static void ixgbe_shutdown(struct pci_dev *pdev)
5319 {
5320 bool wake;
5321
5322 __ixgbe_shutdown(pdev, &wake);
5323
5324 if (system_state == SYSTEM_POWER_OFF) {
5325 pci_wake_from_d3(pdev, wake);
5326 pci_set_power_state(pdev, PCI_D3hot);
5327 }
5328 }
5329
5330 /**
5331 * ixgbe_update_stats - Update the board statistics counters.
5332 * @adapter: board private structure
5333 **/
5334 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5335 {
5336 struct net_device *netdev = adapter->netdev;
5337 struct ixgbe_hw *hw = &adapter->hw;
5338 u64 total_mpc = 0;
5339 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5340 u64 non_eop_descs = 0, restart_queue = 0;
5341
5342 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5343 test_bit(__IXGBE_RESETTING, &adapter->state))
5344 return;
5345
5346 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5347 u64 rsc_count = 0;
5348 u64 rsc_flush = 0;
5349 for (i = 0; i < 16; i++)
5350 adapter->hw_rx_no_dma_resources +=
5351 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5352 for (i = 0; i < adapter->num_rx_queues; i++) {
5353 rsc_count += adapter->rx_ring[i]->rsc_count;
5354 rsc_flush += adapter->rx_ring[i]->rsc_flush;
5355 }
5356 adapter->rsc_total_count = rsc_count;
5357 adapter->rsc_total_flush = rsc_flush;
5358 }
5359
5360 /* gather some stats to the adapter struct that are per queue */
5361 for (i = 0; i < adapter->num_tx_queues; i++)
5362 restart_queue += adapter->tx_ring[i]->restart_queue;
5363 adapter->restart_queue = restart_queue;
5364
5365 for (i = 0; i < adapter->num_rx_queues; i++)
5366 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5367 adapter->non_eop_descs = non_eop_descs;
5368
5369 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5370 for (i = 0; i < 8; i++) {
5371 /* for packet buffers not used, the register should read 0 */
5372 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5373 missed_rx += mpc;
5374 adapter->stats.mpc[i] += mpc;
5375 total_mpc += adapter->stats.mpc[i];
5376 if (hw->mac.type == ixgbe_mac_82598EB)
5377 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5378 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5379 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5380 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5381 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5382 if (hw->mac.type == ixgbe_mac_82599EB) {
5383 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5384 IXGBE_PXONRXCNT(i));
5385 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5386 IXGBE_PXOFFRXCNT(i));
5387 adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5388 } else {
5389 adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
5390 IXGBE_PXONRXC(i));
5391 adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
5392 IXGBE_PXOFFRXC(i));
5393 }
5394 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
5395 IXGBE_PXONTXC(i));
5396 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
5397 IXGBE_PXOFFTXC(i));
5398 }
5399 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5400 /* work around hardware counting issue */
5401 adapter->stats.gprc -= missed_rx;
5402
5403 /* 82598 hardware only has a 32 bit counter in the high register */
5404 if (hw->mac.type == ixgbe_mac_82599EB) {
5405 u64 tmp;
5406 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5407 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF; /* 4 high bits of GORC */
5408 adapter->stats.gorc += (tmp << 32);
5409 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5410 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF; /* 4 high bits of GOTC */
5411 adapter->stats.gotc += (tmp << 32);
5412 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5413 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5414 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5415 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5416 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5417 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5418 #ifdef IXGBE_FCOE
5419 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5420 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5421 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5422 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5423 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5424 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5425 #endif /* IXGBE_FCOE */
5426 } else {
5427 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5428 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5429 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5430 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5431 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5432 }
5433 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5434 adapter->stats.bprc += bprc;
5435 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5436 if (hw->mac.type == ixgbe_mac_82598EB)
5437 adapter->stats.mprc -= bprc;
5438 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5439 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5440 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5441 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5442 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5443 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5444 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5445 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5446 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5447 adapter->stats.lxontxc += lxon;
5448 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5449 adapter->stats.lxofftxc += lxoff;
5450 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5451 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5452 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5453 /*
5454 * 82598 errata - tx of flow control packets is included in tx counters
5455 */
5456 xon_off_tot = lxon + lxoff;
5457 adapter->stats.gptc -= xon_off_tot;
5458 adapter->stats.mptc -= xon_off_tot;
5459 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5460 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5461 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5462 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5463 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5464 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5465 adapter->stats.ptc64 -= xon_off_tot;
5466 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5467 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5468 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5469 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5470 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5471 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5472
5473 /* Fill out the OS statistics structure */
5474 netdev->stats.multicast = adapter->stats.mprc;
5475
5476 /* Rx Errors */
5477 netdev->stats.rx_errors = adapter->stats.crcerrs +
5478 adapter->stats.rlec;
5479 netdev->stats.rx_dropped = 0;
5480 netdev->stats.rx_length_errors = adapter->stats.rlec;
5481 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5482 netdev->stats.rx_missed_errors = total_mpc;
5483 }
5484
5485 /**
5486 * ixgbe_watchdog - Timer Call-back
5487 * @data: pointer to adapter cast into an unsigned long
5488 **/
5489 static void ixgbe_watchdog(unsigned long data)
5490 {
5491 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5492 struct ixgbe_hw *hw = &adapter->hw;
5493 u64 eics = 0;
5494 int i;
5495
5496 /*
5497 * Do the watchdog outside of interrupt context due to the lovely
5498 * delays that some of the newer hardware requires
5499 */
5500
5501 if (test_bit(__IXGBE_DOWN, &adapter->state))
5502 goto watchdog_short_circuit;
5503
5504 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5505 /*
5506 * for legacy and MSI interrupts don't set any bits
5507 * that are enabled for EIAM, because this operation
5508 * would set *both* EIMS and EICS for any bit in EIAM
5509 */
5510 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5511 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5512 goto watchdog_reschedule;
5513 }
5514
5515 /* get one bit for every active tx/rx interrupt vector */
5516 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5517 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5518 if (qv->rxr_count || qv->txr_count)
5519 eics |= ((u64)1 << i);
5520 }
5521
5522 /* Cause software interrupt to ensure rx rings are cleaned */
5523 ixgbe_irq_rearm_queues(adapter, eics);
5524
5525 watchdog_reschedule:
5526 /* Reset the timer */
5527 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5528
5529 watchdog_short_circuit:
5530 schedule_work(&adapter->watchdog_task);
5531 }
5532
5533 /**
5534 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5535 * @work: pointer to work_struct containing our data
5536 **/
5537 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5538 {
5539 struct ixgbe_adapter *adapter = container_of(work,
5540 struct ixgbe_adapter,
5541 multispeed_fiber_task);
5542 struct ixgbe_hw *hw = &adapter->hw;
5543 u32 autoneg;
5544 bool negotiation;
5545
5546 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5547 autoneg = hw->phy.autoneg_advertised;
5548 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5549 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5550 hw->mac.autotry_restart = false;
5551 if (hw->mac.ops.setup_link)
5552 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5553 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5554 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5555 }
5556
5557 /**
5558 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5559 * @work: pointer to work_struct containing our data
5560 **/
5561 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5562 {
5563 struct ixgbe_adapter *adapter = container_of(work,
5564 struct ixgbe_adapter,
5565 sfp_config_module_task);
5566 struct ixgbe_hw *hw = &adapter->hw;
5567 u32 err;
5568
5569 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5570
5571 /* Time for electrical oscillations to settle down */
5572 msleep(100);
5573 err = hw->phy.ops.identify_sfp(hw);
5574
5575 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5576 e_dev_err("failed to initialize because an unsupported SFP+ "
5577 "module type was detected.\n");
5578 e_dev_err("Reload the driver after installing a supported "
5579 "module.\n");
5580 unregister_netdev(adapter->netdev);
5581 return;
5582 }
5583 hw->mac.ops.setup_sfp(hw);
5584
5585 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5586 /* This will also work for DA Twinax connections */
5587 schedule_work(&adapter->multispeed_fiber_task);
5588 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5589 }
5590
5591 /**
5592 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5593 * @work: pointer to work_struct containing our data
5594 **/
5595 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5596 {
5597 struct ixgbe_adapter *adapter = container_of(work,
5598 struct ixgbe_adapter,
5599 fdir_reinit_task);
5600 struct ixgbe_hw *hw = &adapter->hw;
5601 int i;
5602
5603 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5604 for (i = 0; i < adapter->num_tx_queues; i++)
5605 set_bit(__IXGBE_FDIR_INIT_DONE,
5606 &(adapter->tx_ring[i]->reinit_state));
5607 } else {
5608 e_err(probe, "failed to finish FDIR re-initialization, "
5609 "ignored adding FDIR ATR filters\n");
5610 }
5611 /* Done FDIR Re-initialization, enable transmits */
5612 netif_tx_start_all_queues(adapter->netdev);
5613 }
5614
5615 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5616
5617 /**
5618 * ixgbe_watchdog_task - worker thread to bring link up
5619 * @work: pointer to work_struct containing our data
5620 **/
5621 static void ixgbe_watchdog_task(struct work_struct *work)
5622 {
5623 struct ixgbe_adapter *adapter = container_of(work,
5624 struct ixgbe_adapter,
5625 watchdog_task);
5626 struct net_device *netdev = adapter->netdev;
5627 struct ixgbe_hw *hw = &adapter->hw;
5628 u32 link_speed;
5629 bool link_up;
5630 int i;
5631 struct ixgbe_ring *tx_ring;
5632 int some_tx_pending = 0;
5633
5634 mutex_lock(&ixgbe_watchdog_lock);
5635
5636 link_up = adapter->link_up;
5637 link_speed = adapter->link_speed;
5638
5639 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5640 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5641 if (link_up) {
5642 #ifdef CONFIG_DCB
5643 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5644 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5645 hw->mac.ops.fc_enable(hw, i);
5646 } else {
5647 hw->mac.ops.fc_enable(hw, 0);
5648 }
5649 #else
5650 hw->mac.ops.fc_enable(hw, 0);
5651 #endif
5652 }
5653
5654 if (link_up ||
5655 time_after(jiffies, (adapter->link_check_timeout +
5656 IXGBE_TRY_LINK_TIMEOUT))) {
5657 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5658 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5659 }
5660 adapter->link_up = link_up;
5661 adapter->link_speed = link_speed;
5662 }
5663
5664 if (link_up) {
5665 if (!netif_carrier_ok(netdev)) {
5666 bool flow_rx, flow_tx;
5667
5668 if (hw->mac.type == ixgbe_mac_82599EB) {
5669 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5670 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5671 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5672 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5673 } else {
5674 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5675 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5676 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5677 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5678 }
5679
5680 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5681 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5682 "10 Gbps" :
5683 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5684 "1 Gbps" : "unknown speed")),
5685 ((flow_rx && flow_tx) ? "RX/TX" :
5686 (flow_rx ? "RX" :
5687 (flow_tx ? "TX" : "None"))));
5688
5689 netif_carrier_on(netdev);
5690 } else {
5691 /* Force detection of hung controller */
5692 adapter->detect_tx_hung = true;
5693 }
5694 } else {
5695 adapter->link_up = false;
5696 adapter->link_speed = 0;
5697 if (netif_carrier_ok(netdev)) {
5698 e_info(drv, "NIC Link is Down\n");
5699 netif_carrier_off(netdev);
5700 }
5701 }
5702
5703 if (!netif_carrier_ok(netdev)) {
5704 for (i = 0; i < adapter->num_tx_queues; i++) {
5705 tx_ring = adapter->tx_ring[i];
5706 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5707 some_tx_pending = 1;
5708 break;
5709 }
5710 }
5711
5712 if (some_tx_pending) {
5713 /* We've lost link, so the controller stops DMA,
5714 * but we've got queued Tx work that's never going
5715 * to get done, so reset controller to flush Tx.
5716 * (Do the reset outside of interrupt context).
5717 */
5718 schedule_work(&adapter->reset_task);
5719 }
5720 }
5721
5722 ixgbe_update_stats(adapter);
5723 mutex_unlock(&ixgbe_watchdog_lock);
5724 }
5725
5726 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5727 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5728 u32 tx_flags, u8 *hdr_len)
5729 {
5730 struct ixgbe_adv_tx_context_desc *context_desc;
5731 unsigned int i;
5732 int err;
5733 struct ixgbe_tx_buffer *tx_buffer_info;
5734 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5735 u32 mss_l4len_idx, l4len;
5736
5737 if (skb_is_gso(skb)) {
5738 if (skb_header_cloned(skb)) {
5739 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5740 if (err)
5741 return err;
5742 }
5743 l4len = tcp_hdrlen(skb);
5744 *hdr_len += l4len;
5745
5746 if (skb->protocol == htons(ETH_P_IP)) {
5747 struct iphdr *iph = ip_hdr(skb);
5748 iph->tot_len = 0;
5749 iph->check = 0;
5750 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5751 iph->daddr, 0,
5752 IPPROTO_TCP,
5753 0);
5754 } else if (skb_is_gso_v6(skb)) {
5755 ipv6_hdr(skb)->payload_len = 0;
5756 tcp_hdr(skb)->check =
5757 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5758 &ipv6_hdr(skb)->daddr,
5759 0, IPPROTO_TCP, 0);
5760 }
5761
5762 i = tx_ring->next_to_use;
5763
5764 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5765 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5766
5767 /* VLAN MACLEN IPLEN */
5768 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5769 vlan_macip_lens |=
5770 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5771 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5772 IXGBE_ADVTXD_MACLEN_SHIFT);
5773 *hdr_len += skb_network_offset(skb);
5774 vlan_macip_lens |=
5775 (skb_transport_header(skb) - skb_network_header(skb));
5776 *hdr_len +=
5777 (skb_transport_header(skb) - skb_network_header(skb));
5778 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5779 context_desc->seqnum_seed = 0;
5780
5781 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5782 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5783 IXGBE_ADVTXD_DTYP_CTXT);
5784
5785 if (skb->protocol == htons(ETH_P_IP))
5786 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5787 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5788 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5789
5790 /* MSS L4LEN IDX */
5791 mss_l4len_idx =
5792 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5793 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5794 /* use index 1 for TSO */
5795 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5796 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5797
5798 tx_buffer_info->time_stamp = jiffies;
5799 tx_buffer_info->next_to_watch = i;
5800
5801 i++;
5802 if (i == tx_ring->count)
5803 i = 0;
5804 tx_ring->next_to_use = i;
5805
5806 return true;
5807 }
5808 return false;
5809 }
5810
5811 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5812 struct ixgbe_ring *tx_ring,
5813 struct sk_buff *skb, u32 tx_flags)
5814 {
5815 struct ixgbe_adv_tx_context_desc *context_desc;
5816 unsigned int i;
5817 struct ixgbe_tx_buffer *tx_buffer_info;
5818 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5819
5820 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5821 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5822 i = tx_ring->next_to_use;
5823 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5824 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
5825
5826 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5827 vlan_macip_lens |=
5828 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5829 vlan_macip_lens |= (skb_network_offset(skb) <<
5830 IXGBE_ADVTXD_MACLEN_SHIFT);
5831 if (skb->ip_summed == CHECKSUM_PARTIAL)
5832 vlan_macip_lens |= (skb_transport_header(skb) -
5833 skb_network_header(skb));
5834
5835 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5836 context_desc->seqnum_seed = 0;
5837
5838 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5839 IXGBE_ADVTXD_DTYP_CTXT);
5840
5841 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5842 __be16 protocol;
5843
5844 if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
5845 const struct vlan_ethhdr *vhdr =
5846 (const struct vlan_ethhdr *)skb->data;
5847
5848 protocol = vhdr->h_vlan_encapsulated_proto;
5849 } else {
5850 protocol = skb->protocol;
5851 }
5852
5853 switch (protocol) {
5854 case cpu_to_be16(ETH_P_IP):
5855 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5856 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5857 type_tucmd_mlhl |=
5858 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5859 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
5860 type_tucmd_mlhl |=
5861 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5862 break;
5863 case cpu_to_be16(ETH_P_IPV6):
5864 /* XXX what about other V6 headers?? */
5865 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5866 type_tucmd_mlhl |=
5867 IXGBE_ADVTXD_TUCMD_L4T_TCP;
5868 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
5869 type_tucmd_mlhl |=
5870 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5871 break;
5872 default:
5873 if (unlikely(net_ratelimit())) {
5874 e_warn(probe, "partial checksum "
5875 "but proto=%x!\n",
5876 skb->protocol);
5877 }
5878 break;
5879 }
5880 }
5881
5882 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5883 /* use index zero for tx checksum offload */
5884 context_desc->mss_l4len_idx = 0;
5885
5886 tx_buffer_info->time_stamp = jiffies;
5887 tx_buffer_info->next_to_watch = i;
5888
5889 i++;
5890 if (i == tx_ring->count)
5891 i = 0;
5892 tx_ring->next_to_use = i;
5893
5894 return true;
5895 }
5896
5897 return false;
5898 }
5899
5900 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5901 struct ixgbe_ring *tx_ring,
5902 struct sk_buff *skb, u32 tx_flags,
5903 unsigned int first)
5904 {
5905 struct pci_dev *pdev = adapter->pdev;
5906 struct ixgbe_tx_buffer *tx_buffer_info;
5907 unsigned int len;
5908 unsigned int total = skb->len;
5909 unsigned int offset = 0, size, count = 0, i;
5910 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5911 unsigned int f;
5912
5913 i = tx_ring->next_to_use;
5914
5915 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
5916 /* excluding fcoe_crc_eof for FCoE */
5917 total -= sizeof(struct fcoe_crc_eof);
5918
5919 len = min(skb_headlen(skb), total);
5920 while (len) {
5921 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5922 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5923
5924 tx_buffer_info->length = size;
5925 tx_buffer_info->mapped_as_page = false;
5926 tx_buffer_info->dma = dma_map_single(&pdev->dev,
5927 skb->data + offset,
5928 size, DMA_TO_DEVICE);
5929 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5930 goto dma_error;
5931 tx_buffer_info->time_stamp = jiffies;
5932 tx_buffer_info->next_to_watch = i;
5933
5934 len -= size;
5935 total -= size;
5936 offset += size;
5937 count++;
5938
5939 if (len) {
5940 i++;
5941 if (i == tx_ring->count)
5942 i = 0;
5943 }
5944 }
5945
5946 for (f = 0; f < nr_frags; f++) {
5947 struct skb_frag_struct *frag;
5948
5949 frag = &skb_shinfo(skb)->frags[f];
5950 len = min((unsigned int)frag->size, total);
5951 offset = frag->page_offset;
5952
5953 while (len) {
5954 i++;
5955 if (i == tx_ring->count)
5956 i = 0;
5957
5958 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5959 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
5960
5961 tx_buffer_info->length = size;
5962 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
5963 frag->page,
5964 offset, size,
5965 DMA_TO_DEVICE);
5966 tx_buffer_info->mapped_as_page = true;
5967 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
5968 goto dma_error;
5969 tx_buffer_info->time_stamp = jiffies;
5970 tx_buffer_info->next_to_watch = i;
5971
5972 len -= size;
5973 total -= size;
5974 offset += size;
5975 count++;
5976 }
5977 if (total == 0)
5978 break;
5979 }
5980
5981 tx_ring->tx_buffer_info[i].skb = skb;
5982 tx_ring->tx_buffer_info[first].next_to_watch = i;
5983
5984 return count;
5985
5986 dma_error:
5987 e_dev_err("TX DMA map failed\n");
5988
5989 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5990 tx_buffer_info->dma = 0;
5991 tx_buffer_info->time_stamp = 0;
5992 tx_buffer_info->next_to_watch = 0;
5993 if (count)
5994 count--;
5995
5996 /* clear timestamp and dma mappings for remaining portion of packet */
5997 while (count--) {
5998 if (i==0)
5999 i += tx_ring->count;
6000 i--;
6001 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6002 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6003 }
6004
6005 return 0;
6006 }
6007
6008 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
6009 struct ixgbe_ring *tx_ring,
6010 int tx_flags, int count, u32 paylen, u8 hdr_len)
6011 {
6012 union ixgbe_adv_tx_desc *tx_desc = NULL;
6013 struct ixgbe_tx_buffer *tx_buffer_info;
6014 u32 olinfo_status = 0, cmd_type_len = 0;
6015 unsigned int i;
6016 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6017
6018 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6019
6020 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6021
6022 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6023 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6024
6025 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6026 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6027
6028 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6029 IXGBE_ADVTXD_POPTS_SHIFT;
6030
6031 /* use index 1 context for tso */
6032 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6033 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6034 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6035 IXGBE_ADVTXD_POPTS_SHIFT;
6036
6037 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6038 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6039 IXGBE_ADVTXD_POPTS_SHIFT;
6040
6041 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6042 olinfo_status |= IXGBE_ADVTXD_CC;
6043 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6044 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6045 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6046 }
6047
6048 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6049
6050 i = tx_ring->next_to_use;
6051 while (count--) {
6052 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6053 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
6054 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6055 tx_desc->read.cmd_type_len =
6056 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6057 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6058 i++;
6059 if (i == tx_ring->count)
6060 i = 0;
6061 }
6062
6063 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6064
6065 /*
6066 * Force memory writes to complete before letting h/w
6067 * know there are new descriptors to fetch. (Only
6068 * applicable for weak-ordered memory model archs,
6069 * such as IA-64).
6070 */
6071 wmb();
6072
6073 tx_ring->next_to_use = i;
6074 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6075 }
6076
6077 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6078 int queue, u32 tx_flags)
6079 {
6080 struct ixgbe_atr_input atr_input;
6081 struct tcphdr *th;
6082 struct iphdr *iph = ip_hdr(skb);
6083 struct ethhdr *eth = (struct ethhdr *)skb->data;
6084 u16 vlan_id, src_port, dst_port, flex_bytes;
6085 u32 src_ipv4_addr, dst_ipv4_addr;
6086 u8 l4type = 0;
6087
6088 /* Right now, we support IPv4 only */
6089 if (skb->protocol != htons(ETH_P_IP))
6090 return;
6091 /* check if we're UDP or TCP */
6092 if (iph->protocol == IPPROTO_TCP) {
6093 th = tcp_hdr(skb);
6094 src_port = th->source;
6095 dst_port = th->dest;
6096 l4type |= IXGBE_ATR_L4TYPE_TCP;
6097 /* l4type IPv4 type is 0, no need to assign */
6098 } else {
6099 /* Unsupported L4 header, just bail here */
6100 return;
6101 }
6102
6103 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6104
6105 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6106 IXGBE_TX_FLAGS_VLAN_SHIFT;
6107 src_ipv4_addr = iph->saddr;
6108 dst_ipv4_addr = iph->daddr;
6109 flex_bytes = eth->h_proto;
6110
6111 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6112 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6113 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6114 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6115 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6116 /* src and dst are inverted, think how the receiver sees them */
6117 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6118 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6119
6120 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6121 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6122 }
6123
6124 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6125 struct ixgbe_ring *tx_ring, int size)
6126 {
6127 netif_stop_subqueue(netdev, tx_ring->queue_index);
6128 /* Herbert's original patch had:
6129 * smp_mb__after_netif_stop_queue();
6130 * but since that doesn't exist yet, just open code it. */
6131 smp_mb();
6132
6133 /* We need to check again in a case another CPU has just
6134 * made room available. */
6135 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6136 return -EBUSY;
6137
6138 /* A reprieve! - use start_queue because it doesn't call schedule */
6139 netif_start_subqueue(netdev, tx_ring->queue_index);
6140 ++tx_ring->restart_queue;
6141 return 0;
6142 }
6143
6144 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6145 struct ixgbe_ring *tx_ring, int size)
6146 {
6147 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6148 return 0;
6149 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6150 }
6151
6152 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6153 {
6154 struct ixgbe_adapter *adapter = netdev_priv(dev);
6155 int txq = smp_processor_id();
6156
6157 #ifdef IXGBE_FCOE
6158 if ((skb->protocol == htons(ETH_P_FCOE)) ||
6159 (skb->protocol == htons(ETH_P_FIP))) {
6160 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6161 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6162 txq += adapter->ring_feature[RING_F_FCOE].mask;
6163 return txq;
6164 #ifdef CONFIG_IXGBE_DCB
6165 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6166 txq = adapter->fcoe.up;
6167 return txq;
6168 #endif
6169 }
6170 }
6171 #endif
6172
6173 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6174 while (unlikely(txq >= dev->real_num_tx_queues))
6175 txq -= dev->real_num_tx_queues;
6176 return txq;
6177 }
6178
6179 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6180 if (skb->priority == TC_PRIO_CONTROL)
6181 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6182 else
6183 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6184 >> 13;
6185 return txq;
6186 }
6187
6188 return skb_tx_hash(dev, skb);
6189 }
6190
6191 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6192 struct net_device *netdev)
6193 {
6194 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6195 struct ixgbe_ring *tx_ring;
6196 struct netdev_queue *txq;
6197 unsigned int first;
6198 unsigned int tx_flags = 0;
6199 u8 hdr_len = 0;
6200 int tso;
6201 int count = 0;
6202 unsigned int f;
6203
6204 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
6205 tx_flags |= vlan_tx_tag_get(skb);
6206 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6207 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6208 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6209 }
6210 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6211 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6212 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6213 skb->priority != TC_PRIO_CONTROL) {
6214 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6215 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6216 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6217 }
6218
6219 tx_ring = adapter->tx_ring[skb->queue_mapping];
6220
6221 #ifdef IXGBE_FCOE
6222 /* for FCoE with DCB, we force the priority to what
6223 * was specified by the switch */
6224 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6225 (skb->protocol == htons(ETH_P_FCOE) ||
6226 skb->protocol == htons(ETH_P_FIP))) {
6227 #ifdef CONFIG_IXGBE_DCB
6228 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6229 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6230 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6231 tx_flags |= ((adapter->fcoe.up << 13)
6232 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6233 }
6234 #endif
6235 /* flag for FCoE offloads */
6236 if (skb->protocol == htons(ETH_P_FCOE))
6237 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6238 }
6239 #endif
6240
6241 /* four things can cause us to need a context descriptor */
6242 if (skb_is_gso(skb) ||
6243 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6244 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6245 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6246 count++;
6247
6248 count += TXD_USE_COUNT(skb_headlen(skb));
6249 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6250 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6251
6252 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6253 adapter->tx_busy++;
6254 return NETDEV_TX_BUSY;
6255 }
6256
6257 first = tx_ring->next_to_use;
6258 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6259 #ifdef IXGBE_FCOE
6260 /* setup tx offload for FCoE */
6261 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6262 if (tso < 0) {
6263 dev_kfree_skb_any(skb);
6264 return NETDEV_TX_OK;
6265 }
6266 if (tso)
6267 tx_flags |= IXGBE_TX_FLAGS_FSO;
6268 #endif /* IXGBE_FCOE */
6269 } else {
6270 if (skb->protocol == htons(ETH_P_IP))
6271 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6272 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6273 if (tso < 0) {
6274 dev_kfree_skb_any(skb);
6275 return NETDEV_TX_OK;
6276 }
6277
6278 if (tso)
6279 tx_flags |= IXGBE_TX_FLAGS_TSO;
6280 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6281 (skb->ip_summed == CHECKSUM_PARTIAL))
6282 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6283 }
6284
6285 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6286 if (count) {
6287 /* add the ATR filter if ATR is on */
6288 if (tx_ring->atr_sample_rate) {
6289 ++tx_ring->atr_count;
6290 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6291 test_bit(__IXGBE_FDIR_INIT_DONE,
6292 &tx_ring->reinit_state)) {
6293 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6294 tx_flags);
6295 tx_ring->atr_count = 0;
6296 }
6297 }
6298 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6299 txq->tx_bytes += skb->len;
6300 txq->tx_packets++;
6301 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6302 hdr_len);
6303 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6304
6305 } else {
6306 dev_kfree_skb_any(skb);
6307 tx_ring->tx_buffer_info[first].time_stamp = 0;
6308 tx_ring->next_to_use = first;
6309 }
6310
6311 return NETDEV_TX_OK;
6312 }
6313
6314 /**
6315 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6316 * @netdev: network interface device structure
6317 * @p: pointer to an address structure
6318 *
6319 * Returns 0 on success, negative on failure
6320 **/
6321 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6322 {
6323 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6324 struct ixgbe_hw *hw = &adapter->hw;
6325 struct sockaddr *addr = p;
6326
6327 if (!is_valid_ether_addr(addr->sa_data))
6328 return -EADDRNOTAVAIL;
6329
6330 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6331 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6332
6333 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6334 IXGBE_RAH_AV);
6335
6336 return 0;
6337 }
6338
6339 static int
6340 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6341 {
6342 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6343 struct ixgbe_hw *hw = &adapter->hw;
6344 u16 value;
6345 int rc;
6346
6347 if (prtad != hw->phy.mdio.prtad)
6348 return -EINVAL;
6349 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6350 if (!rc)
6351 rc = value;
6352 return rc;
6353 }
6354
6355 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6356 u16 addr, u16 value)
6357 {
6358 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6359 struct ixgbe_hw *hw = &adapter->hw;
6360
6361 if (prtad != hw->phy.mdio.prtad)
6362 return -EINVAL;
6363 return hw->phy.ops.write_reg(hw, addr, devad, value);
6364 }
6365
6366 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6367 {
6368 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6369
6370 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6371 }
6372
6373 /**
6374 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6375 * netdev->dev_addrs
6376 * @netdev: network interface device structure
6377 *
6378 * Returns non-zero on failure
6379 **/
6380 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6381 {
6382 int err = 0;
6383 struct ixgbe_adapter *adapter = netdev_priv(dev);
6384 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6385
6386 if (is_valid_ether_addr(mac->san_addr)) {
6387 rtnl_lock();
6388 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6389 rtnl_unlock();
6390 }
6391 return err;
6392 }
6393
6394 /**
6395 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6396 * netdev->dev_addrs
6397 * @netdev: network interface device structure
6398 *
6399 * Returns non-zero on failure
6400 **/
6401 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6402 {
6403 int err = 0;
6404 struct ixgbe_adapter *adapter = netdev_priv(dev);
6405 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6406
6407 if (is_valid_ether_addr(mac->san_addr)) {
6408 rtnl_lock();
6409 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6410 rtnl_unlock();
6411 }
6412 return err;
6413 }
6414
6415 #ifdef CONFIG_NET_POLL_CONTROLLER
6416 /*
6417 * Polling 'interrupt' - used by things like netconsole to send skbs
6418 * without having to re-enable interrupts. It's not called while
6419 * the interrupt routine is executing.
6420 */
6421 static void ixgbe_netpoll(struct net_device *netdev)
6422 {
6423 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6424 int i;
6425
6426 /* if interface is down do nothing */
6427 if (test_bit(__IXGBE_DOWN, &adapter->state))
6428 return;
6429
6430 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6431 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6432 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6433 for (i = 0; i < num_q_vectors; i++) {
6434 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6435 ixgbe_msix_clean_many(0, q_vector);
6436 }
6437 } else {
6438 ixgbe_intr(adapter->pdev->irq, netdev);
6439 }
6440 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6441 }
6442 #endif
6443
6444 static const struct net_device_ops ixgbe_netdev_ops = {
6445 .ndo_open = ixgbe_open,
6446 .ndo_stop = ixgbe_close,
6447 .ndo_start_xmit = ixgbe_xmit_frame,
6448 .ndo_select_queue = ixgbe_select_queue,
6449 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6450 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6451 .ndo_validate_addr = eth_validate_addr,
6452 .ndo_set_mac_address = ixgbe_set_mac,
6453 .ndo_change_mtu = ixgbe_change_mtu,
6454 .ndo_tx_timeout = ixgbe_tx_timeout,
6455 .ndo_vlan_rx_register = ixgbe_vlan_rx_register,
6456 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6457 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6458 .ndo_do_ioctl = ixgbe_ioctl,
6459 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6460 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6461 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6462 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6463 #ifdef CONFIG_NET_POLL_CONTROLLER
6464 .ndo_poll_controller = ixgbe_netpoll,
6465 #endif
6466 #ifdef IXGBE_FCOE
6467 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6468 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6469 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6470 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6471 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6472 #endif /* IXGBE_FCOE */
6473 };
6474
6475 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6476 const struct ixgbe_info *ii)
6477 {
6478 #ifdef CONFIG_PCI_IOV
6479 struct ixgbe_hw *hw = &adapter->hw;
6480 int err;
6481
6482 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6483 return;
6484
6485 /* The 82599 supports up to 64 VFs per physical function
6486 * but this implementation limits allocation to 63 so that
6487 * basic networking resources are still available to the
6488 * physical function
6489 */
6490 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6491 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6492 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6493 if (err) {
6494 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6495 goto err_novfs;
6496 }
6497 /* If call to enable VFs succeeded then allocate memory
6498 * for per VF control structures.
6499 */
6500 adapter->vfinfo =
6501 kcalloc(adapter->num_vfs,
6502 sizeof(struct vf_data_storage), GFP_KERNEL);
6503 if (adapter->vfinfo) {
6504 /* Now that we're sure SR-IOV is enabled
6505 * and memory allocated set up the mailbox parameters
6506 */
6507 ixgbe_init_mbx_params_pf(hw);
6508 memcpy(&hw->mbx.ops, ii->mbx_ops,
6509 sizeof(hw->mbx.ops));
6510
6511 /* Disable RSC when in SR-IOV mode */
6512 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6513 IXGBE_FLAG2_RSC_ENABLED);
6514 return;
6515 }
6516
6517 /* Oh oh */
6518 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6519 "SRIOV disabled\n");
6520 pci_disable_sriov(adapter->pdev);
6521
6522 err_novfs:
6523 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6524 adapter->num_vfs = 0;
6525 #endif /* CONFIG_PCI_IOV */
6526 }
6527
6528 /**
6529 * ixgbe_probe - Device Initialization Routine
6530 * @pdev: PCI device information struct
6531 * @ent: entry in ixgbe_pci_tbl
6532 *
6533 * Returns 0 on success, negative on failure
6534 *
6535 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6536 * The OS initialization, configuring of the adapter private structure,
6537 * and a hardware reset occur.
6538 **/
6539 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6540 const struct pci_device_id *ent)
6541 {
6542 struct net_device *netdev;
6543 struct ixgbe_adapter *adapter = NULL;
6544 struct ixgbe_hw *hw;
6545 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6546 static int cards_found;
6547 int i, err, pci_using_dac;
6548 unsigned int indices = num_possible_cpus();
6549 #ifdef IXGBE_FCOE
6550 u16 device_caps;
6551 #endif
6552 u32 part_num, eec;
6553
6554 /* Catch broken hardware that put the wrong VF device ID in
6555 * the PCIe SR-IOV capability.
6556 */
6557 if (pdev->is_virtfn) {
6558 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6559 pci_name(pdev), pdev->vendor, pdev->device);
6560 return -EINVAL;
6561 }
6562
6563 err = pci_enable_device_mem(pdev);
6564 if (err)
6565 return err;
6566
6567 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6568 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6569 pci_using_dac = 1;
6570 } else {
6571 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6572 if (err) {
6573 err = dma_set_coherent_mask(&pdev->dev,
6574 DMA_BIT_MASK(32));
6575 if (err) {
6576 dev_err(&pdev->dev,
6577 "No usable DMA configuration, aborting\n");
6578 goto err_dma;
6579 }
6580 }
6581 pci_using_dac = 0;
6582 }
6583
6584 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6585 IORESOURCE_MEM), ixgbe_driver_name);
6586 if (err) {
6587 dev_err(&pdev->dev,
6588 "pci_request_selected_regions failed 0x%x\n", err);
6589 goto err_pci_reg;
6590 }
6591
6592 pci_enable_pcie_error_reporting(pdev);
6593
6594 pci_set_master(pdev);
6595 pci_save_state(pdev);
6596
6597 if (ii->mac == ixgbe_mac_82598EB)
6598 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6599 else
6600 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6601
6602 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6603 #ifdef IXGBE_FCOE
6604 indices += min_t(unsigned int, num_possible_cpus(),
6605 IXGBE_MAX_FCOE_INDICES);
6606 #endif
6607 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6608 if (!netdev) {
6609 err = -ENOMEM;
6610 goto err_alloc_etherdev;
6611 }
6612
6613 SET_NETDEV_DEV(netdev, &pdev->dev);
6614
6615 pci_set_drvdata(pdev, netdev);
6616 adapter = netdev_priv(netdev);
6617
6618 adapter->netdev = netdev;
6619 adapter->pdev = pdev;
6620 hw = &adapter->hw;
6621 hw->back = adapter;
6622 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6623
6624 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6625 pci_resource_len(pdev, 0));
6626 if (!hw->hw_addr) {
6627 err = -EIO;
6628 goto err_ioremap;
6629 }
6630
6631 for (i = 1; i <= 5; i++) {
6632 if (pci_resource_len(pdev, i) == 0)
6633 continue;
6634 }
6635
6636 netdev->netdev_ops = &ixgbe_netdev_ops;
6637 ixgbe_set_ethtool_ops(netdev);
6638 netdev->watchdog_timeo = 5 * HZ;
6639 strcpy(netdev->name, pci_name(pdev));
6640
6641 adapter->bd_number = cards_found;
6642
6643 /* Setup hw api */
6644 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6645 hw->mac.type = ii->mac;
6646
6647 /* EEPROM */
6648 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6649 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6650 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6651 if (!(eec & (1 << 8)))
6652 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6653
6654 /* PHY */
6655 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6656 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6657 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6658 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6659 hw->phy.mdio.mmds = 0;
6660 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6661 hw->phy.mdio.dev = netdev;
6662 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6663 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6664
6665 /* set up this timer and work struct before calling get_invariants
6666 * which might start the timer
6667 */
6668 init_timer(&adapter->sfp_timer);
6669 adapter->sfp_timer.function = &ixgbe_sfp_timer;
6670 adapter->sfp_timer.data = (unsigned long) adapter;
6671
6672 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6673
6674 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6675 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6676
6677 /* a new SFP+ module arrival, called from GPI SDP2 context */
6678 INIT_WORK(&adapter->sfp_config_module_task,
6679 ixgbe_sfp_config_module_task);
6680
6681 ii->get_invariants(hw);
6682
6683 /* setup the private structure */
6684 err = ixgbe_sw_init(adapter);
6685 if (err)
6686 goto err_sw_init;
6687
6688 /* Make it possible the adapter to be woken up via WOL */
6689 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6690 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6691
6692 /*
6693 * If there is a fan on this device and it has failed log the
6694 * failure.
6695 */
6696 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6697 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6698 if (esdp & IXGBE_ESDP_SDP1)
6699 e_crit(probe, "Fan has stopped, replace the adapter\n");
6700 }
6701
6702 /* reset_hw fills in the perm_addr as well */
6703 hw->phy.reset_if_overtemp = true;
6704 err = hw->mac.ops.reset_hw(hw);
6705 hw->phy.reset_if_overtemp = false;
6706 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6707 hw->mac.type == ixgbe_mac_82598EB) {
6708 /*
6709 * Start a kernel thread to watch for a module to arrive.
6710 * Only do this for 82598, since 82599 will generate
6711 * interrupts on module arrival.
6712 */
6713 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6714 mod_timer(&adapter->sfp_timer,
6715 round_jiffies(jiffies + (2 * HZ)));
6716 err = 0;
6717 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6718 e_dev_err("failed to initialize because an unsupported SFP+ "
6719 "module type was detected.\n");
6720 e_dev_err("Reload the driver after installing a supported "
6721 "module.\n");
6722 goto err_sw_init;
6723 } else if (err) {
6724 e_dev_err("HW Init failed: %d\n", err);
6725 goto err_sw_init;
6726 }
6727
6728 ixgbe_probe_vf(adapter, ii);
6729
6730 netdev->features = NETIF_F_SG |
6731 NETIF_F_IP_CSUM |
6732 NETIF_F_HW_VLAN_TX |
6733 NETIF_F_HW_VLAN_RX |
6734 NETIF_F_HW_VLAN_FILTER;
6735
6736 netdev->features |= NETIF_F_IPV6_CSUM;
6737 netdev->features |= NETIF_F_TSO;
6738 netdev->features |= NETIF_F_TSO6;
6739 netdev->features |= NETIF_F_GRO;
6740
6741 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6742 netdev->features |= NETIF_F_SCTP_CSUM;
6743
6744 netdev->vlan_features |= NETIF_F_TSO;
6745 netdev->vlan_features |= NETIF_F_TSO6;
6746 netdev->vlan_features |= NETIF_F_IP_CSUM;
6747 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6748 netdev->vlan_features |= NETIF_F_SG;
6749
6750 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6751 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6752 IXGBE_FLAG_DCB_ENABLED);
6753 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6754 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6755
6756 #ifdef CONFIG_IXGBE_DCB
6757 netdev->dcbnl_ops = &dcbnl_ops;
6758 #endif
6759
6760 #ifdef IXGBE_FCOE
6761 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6762 if (hw->mac.ops.get_device_caps) {
6763 hw->mac.ops.get_device_caps(hw, &device_caps);
6764 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6765 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6766 }
6767 }
6768 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6769 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6770 netdev->vlan_features |= NETIF_F_FSO;
6771 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6772 }
6773 #endif /* IXGBE_FCOE */
6774 if (pci_using_dac)
6775 netdev->features |= NETIF_F_HIGHDMA;
6776
6777 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6778 netdev->features |= NETIF_F_LRO;
6779
6780 /* make sure the EEPROM is good */
6781 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6782 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6783 err = -EIO;
6784 goto err_eeprom;
6785 }
6786
6787 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6788 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6789
6790 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6791 e_dev_err("invalid MAC address\n");
6792 err = -EIO;
6793 goto err_eeprom;
6794 }
6795
6796 /* power down the optics */
6797 if (hw->phy.multispeed_fiber)
6798 hw->mac.ops.disable_tx_laser(hw);
6799
6800 init_timer(&adapter->watchdog_timer);
6801 adapter->watchdog_timer.function = &ixgbe_watchdog;
6802 adapter->watchdog_timer.data = (unsigned long)adapter;
6803
6804 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6805 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6806
6807 err = ixgbe_init_interrupt_scheme(adapter);
6808 if (err)
6809 goto err_sw_init;
6810
6811 switch (pdev->device) {
6812 case IXGBE_DEV_ID_82599_KX4:
6813 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6814 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6815 break;
6816 default:
6817 adapter->wol = 0;
6818 break;
6819 }
6820 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6821
6822 /* pick up the PCI bus settings for reporting later */
6823 hw->mac.ops.get_bus_info(hw);
6824
6825 /* print bus type/speed/width info */
6826 e_dev_info("(PCI Express:%s:%s) %pM\n",
6827 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
6828 (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
6829 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
6830 (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
6831 (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
6832 "Unknown"),
6833 netdev->dev_addr);
6834 ixgbe_read_pba_num_generic(hw, &part_num);
6835 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6836 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6837 "PBA No: %06x-%03x\n",
6838 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6839 (part_num >> 8), (part_num & 0xff));
6840 else
6841 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6842 hw->mac.type, hw->phy.type,
6843 (part_num >> 8), (part_num & 0xff));
6844
6845 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6846 e_dev_warn("PCI-Express bandwidth available for this card is "
6847 "not sufficient for optimal performance.\n");
6848 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6849 "is required.\n");
6850 }
6851
6852 /* save off EEPROM version number */
6853 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6854
6855 /* reset the hardware with the new settings */
6856 err = hw->mac.ops.start_hw(hw);
6857
6858 if (err == IXGBE_ERR_EEPROM_VERSION) {
6859 /* We are running on a pre-production device, log a warning */
6860 e_dev_warn("This device is a pre-production adapter/LOM. "
6861 "Please be aware there may be issues associated "
6862 "with your hardware. If you are experiencing "
6863 "problems please contact your Intel or hardware "
6864 "representative who provided you with this "
6865 "hardware.\n");
6866 }
6867 strcpy(netdev->name, "eth%d");
6868 err = register_netdev(netdev);
6869 if (err)
6870 goto err_register;
6871
6872 /* carrier off reporting is important to ethtool even BEFORE open */
6873 netif_carrier_off(netdev);
6874
6875 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6876 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6877 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6878
6879 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6880 INIT_WORK(&adapter->check_overtemp_task, ixgbe_check_overtemp_task);
6881 #ifdef CONFIG_IXGBE_DCA
6882 if (dca_add_requester(&pdev->dev) == 0) {
6883 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6884 ixgbe_setup_dca(adapter);
6885 }
6886 #endif
6887 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6888 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
6889 for (i = 0; i < adapter->num_vfs; i++)
6890 ixgbe_vf_configuration(pdev, (i | 0x10000000));
6891 }
6892
6893 /* add san mac addr to netdev */
6894 ixgbe_add_sanmac_netdev(netdev);
6895
6896 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
6897 cards_found++;
6898 return 0;
6899
6900 err_register:
6901 ixgbe_release_hw_control(adapter);
6902 ixgbe_clear_interrupt_scheme(adapter);
6903 err_sw_init:
6904 err_eeprom:
6905 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6906 ixgbe_disable_sriov(adapter);
6907 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6908 del_timer_sync(&adapter->sfp_timer);
6909 cancel_work_sync(&adapter->sfp_task);
6910 cancel_work_sync(&adapter->multispeed_fiber_task);
6911 cancel_work_sync(&adapter->sfp_config_module_task);
6912 iounmap(hw->hw_addr);
6913 err_ioremap:
6914 free_netdev(netdev);
6915 err_alloc_etherdev:
6916 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6917 IORESOURCE_MEM));
6918 err_pci_reg:
6919 err_dma:
6920 pci_disable_device(pdev);
6921 return err;
6922 }
6923
6924 /**
6925 * ixgbe_remove - Device Removal Routine
6926 * @pdev: PCI device information struct
6927 *
6928 * ixgbe_remove is called by the PCI subsystem to alert the driver
6929 * that it should release a PCI device. The could be caused by a
6930 * Hot-Plug event, or because the driver is going to be removed from
6931 * memory.
6932 **/
6933 static void __devexit ixgbe_remove(struct pci_dev *pdev)
6934 {
6935 struct net_device *netdev = pci_get_drvdata(pdev);
6936 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6937
6938 set_bit(__IXGBE_DOWN, &adapter->state);
6939 /* clear the module not found bit to make sure the worker won't
6940 * reschedule
6941 */
6942 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6943 del_timer_sync(&adapter->watchdog_timer);
6944
6945 del_timer_sync(&adapter->sfp_timer);
6946 cancel_work_sync(&adapter->watchdog_task);
6947 cancel_work_sync(&adapter->sfp_task);
6948 cancel_work_sync(&adapter->multispeed_fiber_task);
6949 cancel_work_sync(&adapter->sfp_config_module_task);
6950 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6951 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6952 cancel_work_sync(&adapter->fdir_reinit_task);
6953 flush_scheduled_work();
6954
6955 #ifdef CONFIG_IXGBE_DCA
6956 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
6957 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
6958 dca_remove_requester(&pdev->dev);
6959 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
6960 }
6961
6962 #endif
6963 #ifdef IXGBE_FCOE
6964 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6965 ixgbe_cleanup_fcoe(adapter);
6966
6967 #endif /* IXGBE_FCOE */
6968
6969 /* remove the added san mac */
6970 ixgbe_del_sanmac_netdev(netdev);
6971
6972 if (netdev->reg_state == NETREG_REGISTERED)
6973 unregister_netdev(netdev);
6974
6975 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6976 ixgbe_disable_sriov(adapter);
6977
6978 ixgbe_clear_interrupt_scheme(adapter);
6979
6980 ixgbe_release_hw_control(adapter);
6981
6982 iounmap(adapter->hw.hw_addr);
6983 pci_release_selected_regions(pdev, pci_select_bars(pdev,
6984 IORESOURCE_MEM));
6985
6986 e_dev_info("complete\n");
6987
6988 free_netdev(netdev);
6989
6990 pci_disable_pcie_error_reporting(pdev);
6991
6992 pci_disable_device(pdev);
6993 }
6994
6995 /**
6996 * ixgbe_io_error_detected - called when PCI error is detected
6997 * @pdev: Pointer to PCI device
6998 * @state: The current pci connection state
6999 *
7000 * This function is called after a PCI bus error affecting
7001 * this device has been detected.
7002 */
7003 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7004 pci_channel_state_t state)
7005 {
7006 struct net_device *netdev = pci_get_drvdata(pdev);
7007 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7008
7009 netif_device_detach(netdev);
7010
7011 if (state == pci_channel_io_perm_failure)
7012 return PCI_ERS_RESULT_DISCONNECT;
7013
7014 if (netif_running(netdev))
7015 ixgbe_down(adapter);
7016 pci_disable_device(pdev);
7017
7018 /* Request a slot reset. */
7019 return PCI_ERS_RESULT_NEED_RESET;
7020 }
7021
7022 /**
7023 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7024 * @pdev: Pointer to PCI device
7025 *
7026 * Restart the card from scratch, as if from a cold-boot.
7027 */
7028 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7029 {
7030 struct net_device *netdev = pci_get_drvdata(pdev);
7031 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7032 pci_ers_result_t result;
7033 int err;
7034
7035 if (pci_enable_device_mem(pdev)) {
7036 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7037 result = PCI_ERS_RESULT_DISCONNECT;
7038 } else {
7039 pci_set_master(pdev);
7040 pci_restore_state(pdev);
7041 pci_save_state(pdev);
7042
7043 pci_wake_from_d3(pdev, false);
7044
7045 ixgbe_reset(adapter);
7046 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7047 result = PCI_ERS_RESULT_RECOVERED;
7048 }
7049
7050 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7051 if (err) {
7052 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7053 "failed 0x%0x\n", err);
7054 /* non-fatal, continue */
7055 }
7056
7057 return result;
7058 }
7059
7060 /**
7061 * ixgbe_io_resume - called when traffic can start flowing again.
7062 * @pdev: Pointer to PCI device
7063 *
7064 * This callback is called when the error recovery driver tells us that
7065 * its OK to resume normal operation.
7066 */
7067 static void ixgbe_io_resume(struct pci_dev *pdev)
7068 {
7069 struct net_device *netdev = pci_get_drvdata(pdev);
7070 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7071
7072 if (netif_running(netdev)) {
7073 if (ixgbe_up(adapter)) {
7074 e_info(probe, "ixgbe_up failed after reset\n");
7075 return;
7076 }
7077 }
7078
7079 netif_device_attach(netdev);
7080 }
7081
7082 static struct pci_error_handlers ixgbe_err_handler = {
7083 .error_detected = ixgbe_io_error_detected,
7084 .slot_reset = ixgbe_io_slot_reset,
7085 .resume = ixgbe_io_resume,
7086 };
7087
7088 static struct pci_driver ixgbe_driver = {
7089 .name = ixgbe_driver_name,
7090 .id_table = ixgbe_pci_tbl,
7091 .probe = ixgbe_probe,
7092 .remove = __devexit_p(ixgbe_remove),
7093 #ifdef CONFIG_PM
7094 .suspend = ixgbe_suspend,
7095 .resume = ixgbe_resume,
7096 #endif
7097 .shutdown = ixgbe_shutdown,
7098 .err_handler = &ixgbe_err_handler
7099 };
7100
7101 /**
7102 * ixgbe_init_module - Driver Registration Routine
7103 *
7104 * ixgbe_init_module is the first routine called when the driver is
7105 * loaded. All it does is register with the PCI subsystem.
7106 **/
7107 static int __init ixgbe_init_module(void)
7108 {
7109 int ret;
7110 pr_info("%s - version %s\n", ixgbe_driver_string,
7111 ixgbe_driver_version);
7112 pr_info("%s\n", ixgbe_copyright);
7113
7114 #ifdef CONFIG_IXGBE_DCA
7115 dca_register_notify(&dca_notifier);
7116 #endif
7117
7118 ret = pci_register_driver(&ixgbe_driver);
7119 return ret;
7120 }
7121
7122 module_init(ixgbe_init_module);
7123
7124 /**
7125 * ixgbe_exit_module - Driver Exit Cleanup Routine
7126 *
7127 * ixgbe_exit_module is called just before the driver is removed
7128 * from memory.
7129 **/
7130 static void __exit ixgbe_exit_module(void)
7131 {
7132 #ifdef CONFIG_IXGBE_DCA
7133 dca_unregister_notify(&dca_notifier);
7134 #endif
7135 pci_unregister_driver(&ixgbe_driver);
7136 }
7137
7138 #ifdef CONFIG_IXGBE_DCA
7139 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7140 void *p)
7141 {
7142 int ret_val;
7143
7144 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7145 __ixgbe_notify_dca);
7146
7147 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7148 }
7149
7150 #endif /* CONFIG_IXGBE_DCA */
7151
7152 /**
7153 * ixgbe_get_hw_dev return device
7154 * used by hardware layer to print debugging information
7155 **/
7156 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7157 {
7158 struct ixgbe_adapter *adapter = hw->back;
7159 return adapter->netdev;
7160 }
7161
7162 module_exit(ixgbe_exit_module);
7163
7164 /* ixgbe_main.c */
Linux kernel - Deliverables
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