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ixgbe: reorder Tx cleanup so that if adapter will reset we don't rearm
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
45
46 #include "ixgbe.h"
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
50
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
54
55 #define DRV_VERSION "2.0.84-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
58
59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
60 [board_82598] = &ixgbe_82598_info,
61 [board_82599] = &ixgbe_82599_info,
62 };
63
64 /* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
76 board_82598 },
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
78 board_82598 },
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
84 board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
115
116 /* required last entry */
117 {0, }
118 };
119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
123 void *p);
124 static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128 };
129 #endif
130
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs;
133 module_param(max_vfs, uint, 0);
134 MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function");
136 #endif /* CONFIG_PCI_IOV */
137
138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_VERSION);
142
143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146 {
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152 #ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155 #endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
172
173 kfree(adapter->vfinfo);
174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178 }
179
180 struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183 };
184
185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215 };
216
217
218 /*
219 * ixgbe_regdump - register printout routine
220 */
221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222 {
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
285 pr_info("%-15s %08x\n", reginfo->name,
286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
292 pr_err("%-15s", rname);
293 for (j = 0; j < 8; j++)
294 pr_cont(" %08x", regs[i*8+j]);
295 pr_cont("\n");
296 }
297
298 }
299
300 /*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
304 {
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
325 pr_info("Device Name state "
326 "trans_start last_rx\n");
327 pr_info("%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
336 pr_info(" Register Name Value\n");
337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
347 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
348 for (n = 0; n < adapter->num_tx_queues; n++) {
349 tx_ring = adapter->tx_ring[n];
350 tx_buffer_info =
351 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
352 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
353 n, tx_ring->next_to_use, tx_ring->next_to_clean,
354 (u64)tx_buffer_info->dma,
355 tx_buffer_info->length,
356 tx_buffer_info->next_to_watch,
357 (u64)tx_buffer_info->time_stamp);
358 }
359
360 /* Print TX Rings */
361 if (!netif_msg_tx_done(adapter))
362 goto rx_ring_summary;
363
364 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
365
366 /* Transmit Descriptor Formats
367 *
368 * Advanced Transmit Descriptor
369 * +--------------------------------------------------------------+
370 * 0 | Buffer Address [63:0] |
371 * +--------------------------------------------------------------+
372 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
373 * +--------------------------------------------------------------+
374 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
375 */
376
377 for (n = 0; n < adapter->num_tx_queues; n++) {
378 tx_ring = adapter->tx_ring[n];
379 pr_info("------------------------------------\n");
380 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
381 pr_info("------------------------------------\n");
382 pr_info("T [desc] [address 63:0 ] "
383 "[PlPOIdStDDt Ln] [bi->dma ] "
384 "leng ntw timestamp bi->skb\n");
385
386 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
387 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
388 tx_buffer_info = &tx_ring->tx_buffer_info[i];
389 u0 = (struct my_u0 *)tx_desc;
390 pr_info("T [0x%03X] %016llX %016llX %016llX"
391 " %04X %3X %016llX %p", i,
392 le64_to_cpu(u0->a),
393 le64_to_cpu(u0->b),
394 (u64)tx_buffer_info->dma,
395 tx_buffer_info->length,
396 tx_buffer_info->next_to_watch,
397 (u64)tx_buffer_info->time_stamp,
398 tx_buffer_info->skb);
399 if (i == tx_ring->next_to_use &&
400 i == tx_ring->next_to_clean)
401 pr_cont(" NTC/U\n");
402 else if (i == tx_ring->next_to_use)
403 pr_cont(" NTU\n");
404 else if (i == tx_ring->next_to_clean)
405 pr_cont(" NTC\n");
406 else
407 pr_cont("\n");
408
409 if (netif_msg_pktdata(adapter) &&
410 tx_buffer_info->dma != 0)
411 print_hex_dump(KERN_INFO, "",
412 DUMP_PREFIX_ADDRESS, 16, 1,
413 phys_to_virt(tx_buffer_info->dma),
414 tx_buffer_info->length, true);
415 }
416 }
417
418 /* Print RX Rings Summary */
419 rx_ring_summary:
420 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
421 pr_info("Queue [NTU] [NTC]\n");
422 for (n = 0; n < adapter->num_rx_queues; n++) {
423 rx_ring = adapter->rx_ring[n];
424 pr_info("%5d %5X %5X\n",
425 n, rx_ring->next_to_use, rx_ring->next_to_clean);
426 }
427
428 /* Print RX Rings */
429 if (!netif_msg_rx_status(adapter))
430 goto exit;
431
432 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
433
434 /* Advanced Receive Descriptor (Read) Format
435 * 63 1 0
436 * +-----------------------------------------------------+
437 * 0 | Packet Buffer Address [63:1] |A0/NSE|
438 * +----------------------------------------------+------+
439 * 8 | Header Buffer Address [63:1] | DD |
440 * +-----------------------------------------------------+
441 *
442 *
443 * Advanced Receive Descriptor (Write-Back) Format
444 *
445 * 63 48 47 32 31 30 21 20 16 15 4 3 0
446 * +------------------------------------------------------+
447 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
448 * | Checksum Ident | | | | Type | Type |
449 * +------------------------------------------------------+
450 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
451 * +------------------------------------------------------+
452 * 63 48 47 32 31 20 19 0
453 */
454 for (n = 0; n < adapter->num_rx_queues; n++) {
455 rx_ring = adapter->rx_ring[n];
456 pr_info("------------------------------------\n");
457 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
458 pr_info("------------------------------------\n");
459 pr_info("R [desc] [ PktBuf A0] "
460 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
461 "<-- Adv Rx Read format\n");
462 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
463 "[vl er S cks ln] ---------------- [bi->skb] "
464 "<-- Adv Rx Write-Back format\n");
465
466 for (i = 0; i < rx_ring->count; i++) {
467 rx_buffer_info = &rx_ring->rx_buffer_info[i];
468 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
469 u0 = (struct my_u0 *)rx_desc;
470 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
471 if (staterr & IXGBE_RXD_STAT_DD) {
472 /* Descriptor Done */
473 pr_info("RWB[0x%03X] %016llX "
474 "%016llX ---------------- %p", i,
475 le64_to_cpu(u0->a),
476 le64_to_cpu(u0->b),
477 rx_buffer_info->skb);
478 } else {
479 pr_info("R [0x%03X] %016llX "
480 "%016llX %016llX %p", i,
481 le64_to_cpu(u0->a),
482 le64_to_cpu(u0->b),
483 (u64)rx_buffer_info->dma,
484 rx_buffer_info->skb);
485
486 if (netif_msg_pktdata(adapter)) {
487 print_hex_dump(KERN_INFO, "",
488 DUMP_PREFIX_ADDRESS, 16, 1,
489 phys_to_virt(rx_buffer_info->dma),
490 rx_ring->rx_buf_len, true);
491
492 if (rx_ring->rx_buf_len
493 < IXGBE_RXBUFFER_2048)
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
496 phys_to_virt(
497 rx_buffer_info->page_dma +
498 rx_buffer_info->page_offset
499 ),
500 PAGE_SIZE/2, true);
501 }
502 }
503
504 if (i == rx_ring->next_to_use)
505 pr_cont(" NTU\n");
506 else if (i == rx_ring->next_to_clean)
507 pr_cont(" NTC\n");
508 else
509 pr_cont("\n");
510
511 }
512 }
513
514 exit:
515 return;
516 }
517
518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
519 {
520 u32 ctrl_ext;
521
522 /* Let firmware take over control of h/w */
523 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
525 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
526 }
527
528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
529 {
530 u32 ctrl_ext;
531
532 /* Let firmware know the driver has taken over */
533 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
534 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
535 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
536 }
537
538 /*
539 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
540 * @adapter: pointer to adapter struct
541 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
542 * @queue: queue to map the corresponding interrupt to
543 * @msix_vector: the vector to map to the corresponding queue
544 *
545 */
546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
547 u8 queue, u8 msix_vector)
548 {
549 u32 ivar, index;
550 struct ixgbe_hw *hw = &adapter->hw;
551 switch (hw->mac.type) {
552 case ixgbe_mac_82598EB:
553 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
554 if (direction == -1)
555 direction = 0;
556 index = (((direction * 64) + queue) >> 2) & 0x1F;
557 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
558 ivar &= ~(0xFF << (8 * (queue & 0x3)));
559 ivar |= (msix_vector << (8 * (queue & 0x3)));
560 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
561 break;
562 case ixgbe_mac_82599EB:
563 if (direction == -1) {
564 /* other causes */
565 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
566 index = ((queue & 1) * 8);
567 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
568 ivar &= ~(0xFF << index);
569 ivar |= (msix_vector << index);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
571 break;
572 } else {
573 /* tx or rx causes */
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((16 * (queue & 1)) + (8 * direction));
576 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
580 break;
581 }
582 default:
583 break;
584 }
585 }
586
587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
588 u64 qmask)
589 {
590 u32 mask;
591
592 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
593 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
594 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
595 } else {
596 mask = (qmask & 0xFFFFFFFF);
597 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
598 mask = (qmask >> 32);
599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
600 }
601 }
602
603 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
604 struct ixgbe_tx_buffer *tx_buffer_info)
605 {
606 if (tx_buffer_info->dma) {
607 if (tx_buffer_info->mapped_as_page)
608 dma_unmap_page(tx_ring->dev,
609 tx_buffer_info->dma,
610 tx_buffer_info->length,
611 DMA_TO_DEVICE);
612 else
613 dma_unmap_single(tx_ring->dev,
614 tx_buffer_info->dma,
615 tx_buffer_info->length,
616 DMA_TO_DEVICE);
617 tx_buffer_info->dma = 0;
618 }
619 if (tx_buffer_info->skb) {
620 dev_kfree_skb_any(tx_buffer_info->skb);
621 tx_buffer_info->skb = NULL;
622 }
623 tx_buffer_info->time_stamp = 0;
624 /* tx_buffer_info must be completely set up in the transmit path */
625 }
626
627 /**
628 * ixgbe_tx_xon_state - check the tx ring xon state
629 * @adapter: the ixgbe adapter
630 * @tx_ring: the corresponding tx_ring
631 *
632 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
633 * corresponding TC of this tx_ring when checking TFCS.
634 *
635 * Returns : true if in xon state (currently not paused)
636 */
637 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
638 struct ixgbe_ring *tx_ring)
639 {
640 u32 txoff = IXGBE_TFCS_TXOFF;
641
642 #ifdef CONFIG_IXGBE_DCB
643 if (adapter->dcb_cfg.pfc_mode_enable) {
644 int tc;
645 int reg_idx = tx_ring->reg_idx;
646 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
647
648 switch (adapter->hw.mac.type) {
649 case ixgbe_mac_82598EB:
650 tc = reg_idx >> 2;
651 txoff = IXGBE_TFCS_TXOFF0;
652 break;
653 case ixgbe_mac_82599EB:
654 tc = 0;
655 txoff = IXGBE_TFCS_TXOFF;
656 if (dcb_i == 8) {
657 /* TC0, TC1 */
658 tc = reg_idx >> 5;
659 if (tc == 2) /* TC2, TC3 */
660 tc += (reg_idx - 64) >> 4;
661 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
662 tc += 1 + ((reg_idx - 96) >> 3);
663 } else if (dcb_i == 4) {
664 /* TC0, TC1 */
665 tc = reg_idx >> 6;
666 if (tc == 1) {
667 tc += (reg_idx - 64) >> 5;
668 if (tc == 2) /* TC2, TC3 */
669 tc += (reg_idx - 96) >> 4;
670 }
671 }
672 break;
673 default:
674 tc = 0;
675 }
676 txoff <<= tc;
677 }
678 #endif
679 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
680 }
681
682 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
683 struct ixgbe_ring *tx_ring,
684 unsigned int eop)
685 {
686 struct ixgbe_hw *hw = &adapter->hw;
687
688 /* Detect a transmit hang in hardware, this serializes the
689 * check with the clearing of time_stamp and movement of eop */
690 clear_check_for_tx_hang(tx_ring);
691 if (tx_ring->tx_buffer_info[eop].time_stamp &&
692 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
693 ixgbe_tx_xon_state(adapter, tx_ring)) {
694 /* detected Tx unit hang */
695 union ixgbe_adv_tx_desc *tx_desc;
696 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
697 e_err(drv, "Detected Tx Unit Hang\n"
698 " Tx Queue <%d>\n"
699 " TDH, TDT <%x>, <%x>\n"
700 " next_to_use <%x>\n"
701 " next_to_clean <%x>\n"
702 "tx_buffer_info[next_to_clean]\n"
703 " time_stamp <%lx>\n"
704 " jiffies <%lx>\n",
705 tx_ring->queue_index,
706 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
707 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
708 tx_ring->next_to_use, eop,
709 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
710 return true;
711 }
712
713 return false;
714 }
715
716 #define IXGBE_MAX_TXD_PWR 14
717 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
718
719 /* Tx Descriptors needed, worst case */
720 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
721 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
722 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
723 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
724
725 static void ixgbe_tx_timeout(struct net_device *netdev);
726
727 /**
728 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
729 * @q_vector: structure containing interrupt and ring information
730 * @tx_ring: tx ring to clean
731 **/
732 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
733 struct ixgbe_ring *tx_ring)
734 {
735 struct ixgbe_adapter *adapter = q_vector->adapter;
736 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
737 struct ixgbe_tx_buffer *tx_buffer_info;
738 unsigned int total_bytes = 0, total_packets = 0;
739 u16 i, eop, count = 0;
740
741 i = tx_ring->next_to_clean;
742 eop = tx_ring->tx_buffer_info[i].next_to_watch;
743 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
744
745 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
746 (count < tx_ring->work_limit)) {
747 bool cleaned = false;
748 rmb(); /* read buffer_info after eop_desc */
749 for ( ; !cleaned; count++) {
750 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
751 tx_buffer_info = &tx_ring->tx_buffer_info[i];
752
753 tx_desc->wb.status = 0;
754 cleaned = (i == eop);
755
756 i++;
757 if (i == tx_ring->count)
758 i = 0;
759
760 if (cleaned && tx_buffer_info->skb) {
761 total_bytes += tx_buffer_info->bytecount;
762 total_packets += tx_buffer_info->gso_segs;
763 }
764
765 ixgbe_unmap_and_free_tx_resource(tx_ring,
766 tx_buffer_info);
767 }
768
769 eop = tx_ring->tx_buffer_info[i].next_to_watch;
770 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
771 }
772
773 tx_ring->next_to_clean = i;
774 tx_ring->total_bytes += total_bytes;
775 tx_ring->total_packets += total_packets;
776 u64_stats_update_begin(&tx_ring->syncp);
777 tx_ring->stats.packets += total_packets;
778 tx_ring->stats.bytes += total_bytes;
779 u64_stats_update_end(&tx_ring->syncp);
780
781 if (check_for_tx_hang(tx_ring) &&
782 ixgbe_check_tx_hang(adapter, tx_ring, i)) {
783 /* schedule immediate reset if we believe we hung */
784 e_info(probe, "tx hang %d detected, resetting "
785 "adapter\n", adapter->tx_timeout_count + 1);
786 ixgbe_tx_timeout(adapter->netdev);
787
788 /* the adapter is about to reset, no point in enabling stuff */
789 return true;
790 }
791
792 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
793 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
794 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
795 /* Make sure that anybody stopping the queue after this
796 * sees the new next_to_clean.
797 */
798 smp_mb();
799 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
800 !test_bit(__IXGBE_DOWN, &adapter->state)) {
801 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
802 ++tx_ring->tx_stats.restart_queue;
803 }
804 }
805
806 return count < tx_ring->work_limit;
807 }
808
809 #ifdef CONFIG_IXGBE_DCA
810 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
811 struct ixgbe_ring *rx_ring,
812 int cpu)
813 {
814 struct ixgbe_hw *hw = &adapter->hw;
815 u32 rxctrl;
816 u8 reg_idx = rx_ring->reg_idx;
817
818 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
819 switch (hw->mac.type) {
820 case ixgbe_mac_82598EB:
821 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
822 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
823 break;
824 case ixgbe_mac_82599EB:
825 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
826 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
827 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
828 break;
829 default:
830 break;
831 }
832 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
833 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
834 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
835 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
836 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
837 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
838 }
839
840 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
841 struct ixgbe_ring *tx_ring,
842 int cpu)
843 {
844 struct ixgbe_hw *hw = &adapter->hw;
845 u32 txctrl;
846 u8 reg_idx = tx_ring->reg_idx;
847
848 switch (hw->mac.type) {
849 case ixgbe_mac_82598EB:
850 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
851 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
852 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
853 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
854 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
855 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
856 break;
857 case ixgbe_mac_82599EB:
858 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
859 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
860 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
861 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
862 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
863 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
864 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
865 break;
866 default:
867 break;
868 }
869 }
870
871 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
872 {
873 struct ixgbe_adapter *adapter = q_vector->adapter;
874 int cpu = get_cpu();
875 long r_idx;
876 int i;
877
878 if (q_vector->cpu == cpu)
879 goto out_no_update;
880
881 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
882 for (i = 0; i < q_vector->txr_count; i++) {
883 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
884 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
885 r_idx + 1);
886 }
887
888 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
889 for (i = 0; i < q_vector->rxr_count; i++) {
890 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
891 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
892 r_idx + 1);
893 }
894
895 q_vector->cpu = cpu;
896 out_no_update:
897 put_cpu();
898 }
899
900 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
901 {
902 int num_q_vectors;
903 int i;
904
905 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
906 return;
907
908 /* always use CB2 mode, difference is masked in the CB driver */
909 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
910
911 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
912 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
913 else
914 num_q_vectors = 1;
915
916 for (i = 0; i < num_q_vectors; i++) {
917 adapter->q_vector[i]->cpu = -1;
918 ixgbe_update_dca(adapter->q_vector[i]);
919 }
920 }
921
922 static int __ixgbe_notify_dca(struct device *dev, void *data)
923 {
924 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
925 unsigned long event = *(unsigned long *)data;
926
927 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
928 return 0;
929
930 switch (event) {
931 case DCA_PROVIDER_ADD:
932 /* if we're already enabled, don't do it again */
933 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
934 break;
935 if (dca_add_requester(dev) == 0) {
936 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
937 ixgbe_setup_dca(adapter);
938 break;
939 }
940 /* Fall Through since DCA is disabled. */
941 case DCA_PROVIDER_REMOVE:
942 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
943 dca_remove_requester(dev);
944 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
945 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
946 }
947 break;
948 }
949
950 return 0;
951 }
952
953 #endif /* CONFIG_IXGBE_DCA */
954 /**
955 * ixgbe_receive_skb - Send a completed packet up the stack
956 * @adapter: board private structure
957 * @skb: packet to send up
958 * @status: hardware indication of status of receive
959 * @rx_ring: rx descriptor ring (for a specific queue) to setup
960 * @rx_desc: rx descriptor
961 **/
962 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
963 struct sk_buff *skb, u8 status,
964 struct ixgbe_ring *ring,
965 union ixgbe_adv_rx_desc *rx_desc)
966 {
967 struct ixgbe_adapter *adapter = q_vector->adapter;
968 struct napi_struct *napi = &q_vector->napi;
969 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
970 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
971
972 if (is_vlan && (tag & VLAN_VID_MASK))
973 __vlan_hwaccel_put_tag(skb, tag);
974
975 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
976 napi_gro_receive(napi, skb);
977 else
978 netif_rx(skb);
979 }
980
981 /**
982 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
983 * @adapter: address of board private structure
984 * @status_err: hardware indication of status of receive
985 * @skb: skb currently being received and modified
986 **/
987 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
988 union ixgbe_adv_rx_desc *rx_desc,
989 struct sk_buff *skb)
990 {
991 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
992
993 skb_checksum_none_assert(skb);
994
995 /* Rx csum disabled */
996 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
997 return;
998
999 /* if IP and error */
1000 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1001 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1002 adapter->hw_csum_rx_error++;
1003 return;
1004 }
1005
1006 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1007 return;
1008
1009 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1010 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1011
1012 /*
1013 * 82599 errata, UDP frames with a 0 checksum can be marked as
1014 * checksum errors.
1015 */
1016 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1017 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1018 return;
1019
1020 adapter->hw_csum_rx_error++;
1021 return;
1022 }
1023
1024 /* It must be a TCP or UDP packet with a valid checksum */
1025 skb->ip_summed = CHECKSUM_UNNECESSARY;
1026 }
1027
1028 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1029 {
1030 /*
1031 * Force memory writes to complete before letting h/w
1032 * know there are new descriptors to fetch. (Only
1033 * applicable for weak-ordered memory model archs,
1034 * such as IA-64).
1035 */
1036 wmb();
1037 writel(val, rx_ring->tail);
1038 }
1039
1040 /**
1041 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1042 * @rx_ring: ring to place buffers on
1043 * @cleaned_count: number of buffers to replace
1044 **/
1045 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1046 {
1047 union ixgbe_adv_rx_desc *rx_desc;
1048 struct ixgbe_rx_buffer *bi;
1049 struct sk_buff *skb;
1050 u16 i = rx_ring->next_to_use;
1051
1052 /* do nothing if no valid netdev defined */
1053 if (!rx_ring->netdev)
1054 return;
1055
1056 while (cleaned_count--) {
1057 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1058 bi = &rx_ring->rx_buffer_info[i];
1059 skb = bi->skb;
1060
1061 if (!skb) {
1062 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1063 rx_ring->rx_buf_len);
1064 if (!skb) {
1065 rx_ring->rx_stats.alloc_rx_buff_failed++;
1066 goto no_buffers;
1067 }
1068 /* initialize queue mapping */
1069 skb_record_rx_queue(skb, rx_ring->queue_index);
1070 bi->skb = skb;
1071 }
1072
1073 if (!bi->dma) {
1074 bi->dma = dma_map_single(rx_ring->dev,
1075 skb->data,
1076 rx_ring->rx_buf_len,
1077 DMA_FROM_DEVICE);
1078 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1079 rx_ring->rx_stats.alloc_rx_buff_failed++;
1080 bi->dma = 0;
1081 goto no_buffers;
1082 }
1083 }
1084
1085 if (ring_is_ps_enabled(rx_ring)) {
1086 if (!bi->page) {
1087 bi->page = netdev_alloc_page(rx_ring->netdev);
1088 if (!bi->page) {
1089 rx_ring->rx_stats.alloc_rx_page_failed++;
1090 goto no_buffers;
1091 }
1092 }
1093
1094 if (!bi->page_dma) {
1095 /* use a half page if we're re-using */
1096 bi->page_offset ^= PAGE_SIZE / 2;
1097 bi->page_dma = dma_map_page(rx_ring->dev,
1098 bi->page,
1099 bi->page_offset,
1100 PAGE_SIZE / 2,
1101 DMA_FROM_DEVICE);
1102 if (dma_mapping_error(rx_ring->dev,
1103 bi->page_dma)) {
1104 rx_ring->rx_stats.alloc_rx_page_failed++;
1105 bi->page_dma = 0;
1106 goto no_buffers;
1107 }
1108 }
1109
1110 /* Refresh the desc even if buffer_addrs didn't change
1111 * because each write-back erases this info. */
1112 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1113 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1114 } else {
1115 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1116 rx_desc->read.hdr_addr = 0;
1117 }
1118
1119 i++;
1120 if (i == rx_ring->count)
1121 i = 0;
1122 }
1123
1124 no_buffers:
1125 if (rx_ring->next_to_use != i) {
1126 rx_ring->next_to_use = i;
1127 ixgbe_release_rx_desc(rx_ring, i);
1128 }
1129 }
1130
1131 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1132 {
1133 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1134 }
1135
1136 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1137 {
1138 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1139 }
1140
1141 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1142 {
1143 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1144 IXGBE_RXDADV_RSCCNT_MASK) >>
1145 IXGBE_RXDADV_RSCCNT_SHIFT;
1146 }
1147
1148 /**
1149 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1150 * @skb: pointer to the last skb in the rsc queue
1151 * @count: pointer to number of packets coalesced in this context
1152 *
1153 * This function changes a queue full of hw rsc buffers into a completed
1154 * packet. It uses the ->prev pointers to find the first packet and then
1155 * turns it into the frag list owner.
1156 **/
1157 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1158 u64 *count)
1159 {
1160 unsigned int frag_list_size = 0;
1161
1162 while (skb->prev) {
1163 struct sk_buff *prev = skb->prev;
1164 frag_list_size += skb->len;
1165 skb->prev = NULL;
1166 skb = prev;
1167 *count += 1;
1168 }
1169
1170 skb_shinfo(skb)->frag_list = skb->next;
1171 skb->next = NULL;
1172 skb->len += frag_list_size;
1173 skb->data_len += frag_list_size;
1174 skb->truesize += frag_list_size;
1175 return skb;
1176 }
1177
1178 struct ixgbe_rsc_cb {
1179 dma_addr_t dma;
1180 bool delay_unmap;
1181 };
1182
1183 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1184
1185 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1186 struct ixgbe_ring *rx_ring,
1187 int *work_done, int work_to_do)
1188 {
1189 struct ixgbe_adapter *adapter = q_vector->adapter;
1190 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1191 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1192 struct sk_buff *skb;
1193 unsigned int i, rsc_count = 0;
1194 u32 len, staterr;
1195 u16 hdr_info;
1196 bool cleaned = false;
1197 int cleaned_count = 0;
1198 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1199 #ifdef IXGBE_FCOE
1200 int ddp_bytes = 0;
1201 #endif /* IXGBE_FCOE */
1202
1203 i = rx_ring->next_to_clean;
1204 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1205 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1206 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1207
1208 while (staterr & IXGBE_RXD_STAT_DD) {
1209 u32 upper_len = 0;
1210 if (*work_done >= work_to_do)
1211 break;
1212 (*work_done)++;
1213
1214 rmb(); /* read descriptor and rx_buffer_info after status DD */
1215 if (ring_is_ps_enabled(rx_ring)) {
1216 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1217 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1218 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1219 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1220 if ((len > IXGBE_RX_HDR_SIZE) ||
1221 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1222 len = IXGBE_RX_HDR_SIZE;
1223 } else {
1224 len = le16_to_cpu(rx_desc->wb.upper.length);
1225 }
1226
1227 cleaned = true;
1228 skb = rx_buffer_info->skb;
1229 prefetch(skb->data);
1230 rx_buffer_info->skb = NULL;
1231
1232 if (rx_buffer_info->dma) {
1233 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1234 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1235 (!(skb->prev))) {
1236 /*
1237 * When HWRSC is enabled, delay unmapping
1238 * of the first packet. It carries the
1239 * header information, HW may still
1240 * access the header after the writeback.
1241 * Only unmap it when EOP is reached
1242 */
1243 IXGBE_RSC_CB(skb)->delay_unmap = true;
1244 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1245 } else {
1246 dma_unmap_single(rx_ring->dev,
1247 rx_buffer_info->dma,
1248 rx_ring->rx_buf_len,
1249 DMA_FROM_DEVICE);
1250 }
1251 rx_buffer_info->dma = 0;
1252 skb_put(skb, len);
1253 }
1254
1255 if (upper_len) {
1256 dma_unmap_page(rx_ring->dev,
1257 rx_buffer_info->page_dma,
1258 PAGE_SIZE / 2,
1259 DMA_FROM_DEVICE);
1260 rx_buffer_info->page_dma = 0;
1261 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1262 rx_buffer_info->page,
1263 rx_buffer_info->page_offset,
1264 upper_len);
1265
1266 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1267 (page_count(rx_buffer_info->page) != 1))
1268 rx_buffer_info->page = NULL;
1269 else
1270 get_page(rx_buffer_info->page);
1271
1272 skb->len += upper_len;
1273 skb->data_len += upper_len;
1274 skb->truesize += upper_len;
1275 }
1276
1277 i++;
1278 if (i == rx_ring->count)
1279 i = 0;
1280
1281 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1282 prefetch(next_rxd);
1283 cleaned_count++;
1284
1285 if (ring_is_rsc_enabled(rx_ring))
1286 rsc_count = ixgbe_get_rsc_count(rx_desc);
1287
1288 if (rsc_count) {
1289 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1290 IXGBE_RXDADV_NEXTP_SHIFT;
1291 next_buffer = &rx_ring->rx_buffer_info[nextp];
1292 } else {
1293 next_buffer = &rx_ring->rx_buffer_info[i];
1294 }
1295
1296 if (staterr & IXGBE_RXD_STAT_EOP) {
1297 if (skb->prev)
1298 skb = ixgbe_transform_rsc_queue(skb,
1299 &(rx_ring->rx_stats.rsc_count));
1300 if (ring_is_rsc_enabled(rx_ring)) {
1301 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1302 dma_unmap_single(rx_ring->dev,
1303 IXGBE_RSC_CB(skb)->dma,
1304 rx_ring->rx_buf_len,
1305 DMA_FROM_DEVICE);
1306 IXGBE_RSC_CB(skb)->dma = 0;
1307 IXGBE_RSC_CB(skb)->delay_unmap = false;
1308 }
1309 if (ring_is_ps_enabled(rx_ring))
1310 rx_ring->rx_stats.rsc_count +=
1311 skb_shinfo(skb)->nr_frags;
1312 else
1313 rx_ring->rx_stats.rsc_count++;
1314 rx_ring->rx_stats.rsc_flush++;
1315 }
1316 u64_stats_update_begin(&rx_ring->syncp);
1317 rx_ring->stats.packets++;
1318 rx_ring->stats.bytes += skb->len;
1319 u64_stats_update_end(&rx_ring->syncp);
1320 } else {
1321 if (ring_is_ps_enabled(rx_ring)) {
1322 rx_buffer_info->skb = next_buffer->skb;
1323 rx_buffer_info->dma = next_buffer->dma;
1324 next_buffer->skb = skb;
1325 next_buffer->dma = 0;
1326 } else {
1327 skb->next = next_buffer->skb;
1328 skb->next->prev = skb;
1329 }
1330 rx_ring->rx_stats.non_eop_descs++;
1331 goto next_desc;
1332 }
1333
1334 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1335 dev_kfree_skb_irq(skb);
1336 goto next_desc;
1337 }
1338
1339 ixgbe_rx_checksum(adapter, rx_desc, skb);
1340
1341 /* probably a little skewed due to removing CRC */
1342 total_rx_bytes += skb->len;
1343 total_rx_packets++;
1344
1345 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1346 #ifdef IXGBE_FCOE
1347 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1348 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1349 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1350 if (!ddp_bytes)
1351 goto next_desc;
1352 }
1353 #endif /* IXGBE_FCOE */
1354 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1355
1356 next_desc:
1357 rx_desc->wb.upper.status_error = 0;
1358
1359 /* return some buffers to hardware, one at a time is too slow */
1360 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1361 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1362 cleaned_count = 0;
1363 }
1364
1365 /* use prefetched values */
1366 rx_desc = next_rxd;
1367 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1368
1369 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1370 }
1371
1372 rx_ring->next_to_clean = i;
1373 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1374
1375 if (cleaned_count)
1376 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1377
1378 #ifdef IXGBE_FCOE
1379 /* include DDPed FCoE data */
1380 if (ddp_bytes > 0) {
1381 unsigned int mss;
1382
1383 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1384 sizeof(struct fc_frame_header) -
1385 sizeof(struct fcoe_crc_eof);
1386 if (mss > 512)
1387 mss &= ~511;
1388 total_rx_bytes += ddp_bytes;
1389 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1390 }
1391 #endif /* IXGBE_FCOE */
1392
1393 rx_ring->total_packets += total_rx_packets;
1394 rx_ring->total_bytes += total_rx_bytes;
1395
1396 return cleaned;
1397 }
1398
1399 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1400 /**
1401 * ixgbe_configure_msix - Configure MSI-X hardware
1402 * @adapter: board private structure
1403 *
1404 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1405 * interrupts.
1406 **/
1407 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1408 {
1409 struct ixgbe_q_vector *q_vector;
1410 int i, j, q_vectors, v_idx, r_idx;
1411 u32 mask;
1412
1413 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1414
1415 /*
1416 * Populate the IVAR table and set the ITR values to the
1417 * corresponding register.
1418 */
1419 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1420 q_vector = adapter->q_vector[v_idx];
1421 /* XXX for_each_set_bit(...) */
1422 r_idx = find_first_bit(q_vector->rxr_idx,
1423 adapter->num_rx_queues);
1424
1425 for (i = 0; i < q_vector->rxr_count; i++) {
1426 j = adapter->rx_ring[r_idx]->reg_idx;
1427 ixgbe_set_ivar(adapter, 0, j, v_idx);
1428 r_idx = find_next_bit(q_vector->rxr_idx,
1429 adapter->num_rx_queues,
1430 r_idx + 1);
1431 }
1432 r_idx = find_first_bit(q_vector->txr_idx,
1433 adapter->num_tx_queues);
1434
1435 for (i = 0; i < q_vector->txr_count; i++) {
1436 j = adapter->tx_ring[r_idx]->reg_idx;
1437 ixgbe_set_ivar(adapter, 1, j, v_idx);
1438 r_idx = find_next_bit(q_vector->txr_idx,
1439 adapter->num_tx_queues,
1440 r_idx + 1);
1441 }
1442
1443 if (q_vector->txr_count && !q_vector->rxr_count)
1444 /* tx only */
1445 q_vector->eitr = adapter->tx_eitr_param;
1446 else if (q_vector->rxr_count)
1447 /* rx or mixed */
1448 q_vector->eitr = adapter->rx_eitr_param;
1449
1450 ixgbe_write_eitr(q_vector);
1451 /* If Flow Director is enabled, set interrupt affinity */
1452 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1453 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1454 /*
1455 * Allocate the affinity_hint cpumask, assign the mask
1456 * for this vector, and set our affinity_hint for
1457 * this irq.
1458 */
1459 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1460 GFP_KERNEL))
1461 return;
1462 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1463 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1464 q_vector->affinity_mask);
1465 }
1466 }
1467
1468 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1469 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1470 v_idx);
1471 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1472 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1473 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1474
1475 /* set up to autoclear timer, and the vectors */
1476 mask = IXGBE_EIMS_ENABLE_MASK;
1477 if (adapter->num_vfs)
1478 mask &= ~(IXGBE_EIMS_OTHER |
1479 IXGBE_EIMS_MAILBOX |
1480 IXGBE_EIMS_LSC);
1481 else
1482 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1483 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1484 }
1485
1486 enum latency_range {
1487 lowest_latency = 0,
1488 low_latency = 1,
1489 bulk_latency = 2,
1490 latency_invalid = 255
1491 };
1492
1493 /**
1494 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1495 * @adapter: pointer to adapter
1496 * @eitr: eitr setting (ints per sec) to give last timeslice
1497 * @itr_setting: current throttle rate in ints/second
1498 * @packets: the number of packets during this measurement interval
1499 * @bytes: the number of bytes during this measurement interval
1500 *
1501 * Stores a new ITR value based on packets and byte
1502 * counts during the last interrupt. The advantage of per interrupt
1503 * computation is faster updates and more accurate ITR for the current
1504 * traffic pattern. Constants in this function were computed
1505 * based on theoretical maximum wire speed and thresholds were set based
1506 * on testing data as well as attempting to minimize response time
1507 * while increasing bulk throughput.
1508 * this functionality is controlled by the InterruptThrottleRate module
1509 * parameter (see ixgbe_param.c)
1510 **/
1511 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1512 u32 eitr, u8 itr_setting,
1513 int packets, int bytes)
1514 {
1515 unsigned int retval = itr_setting;
1516 u32 timepassed_us;
1517 u64 bytes_perint;
1518
1519 if (packets == 0)
1520 goto update_itr_done;
1521
1522
1523 /* simple throttlerate management
1524 * 0-20MB/s lowest (100000 ints/s)
1525 * 20-100MB/s low (20000 ints/s)
1526 * 100-1249MB/s bulk (8000 ints/s)
1527 */
1528 /* what was last interrupt timeslice? */
1529 timepassed_us = 1000000/eitr;
1530 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1531
1532 switch (itr_setting) {
1533 case lowest_latency:
1534 if (bytes_perint > adapter->eitr_low)
1535 retval = low_latency;
1536 break;
1537 case low_latency:
1538 if (bytes_perint > adapter->eitr_high)
1539 retval = bulk_latency;
1540 else if (bytes_perint <= adapter->eitr_low)
1541 retval = lowest_latency;
1542 break;
1543 case bulk_latency:
1544 if (bytes_perint <= adapter->eitr_high)
1545 retval = low_latency;
1546 break;
1547 }
1548
1549 update_itr_done:
1550 return retval;
1551 }
1552
1553 /**
1554 * ixgbe_write_eitr - write EITR register in hardware specific way
1555 * @q_vector: structure containing interrupt and ring information
1556 *
1557 * This function is made to be called by ethtool and by the driver
1558 * when it needs to update EITR registers at runtime. Hardware
1559 * specific quirks/differences are taken care of here.
1560 */
1561 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1562 {
1563 struct ixgbe_adapter *adapter = q_vector->adapter;
1564 struct ixgbe_hw *hw = &adapter->hw;
1565 int v_idx = q_vector->v_idx;
1566 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1567
1568 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1569 /* must write high and low 16 bits to reset counter */
1570 itr_reg |= (itr_reg << 16);
1571 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1572 /*
1573 * 82599 can support a value of zero, so allow it for
1574 * max interrupt rate, but there is an errata where it can
1575 * not be zero with RSC
1576 */
1577 if (itr_reg == 8 &&
1578 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1579 itr_reg = 0;
1580
1581 /*
1582 * set the WDIS bit to not clear the timer bits and cause an
1583 * immediate assertion of the interrupt
1584 */
1585 itr_reg |= IXGBE_EITR_CNT_WDIS;
1586 }
1587 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1588 }
1589
1590 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1591 {
1592 struct ixgbe_adapter *adapter = q_vector->adapter;
1593 u32 new_itr;
1594 u8 current_itr, ret_itr;
1595 int i, r_idx;
1596 struct ixgbe_ring *rx_ring, *tx_ring;
1597
1598 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1599 for (i = 0; i < q_vector->txr_count; i++) {
1600 tx_ring = adapter->tx_ring[r_idx];
1601 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1602 q_vector->tx_itr,
1603 tx_ring->total_packets,
1604 tx_ring->total_bytes);
1605 /* if the result for this queue would decrease interrupt
1606 * rate for this vector then use that result */
1607 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1608 q_vector->tx_itr - 1 : ret_itr);
1609 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1610 r_idx + 1);
1611 }
1612
1613 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1614 for (i = 0; i < q_vector->rxr_count; i++) {
1615 rx_ring = adapter->rx_ring[r_idx];
1616 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1617 q_vector->rx_itr,
1618 rx_ring->total_packets,
1619 rx_ring->total_bytes);
1620 /* if the result for this queue would decrease interrupt
1621 * rate for this vector then use that result */
1622 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1623 q_vector->rx_itr - 1 : ret_itr);
1624 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1625 r_idx + 1);
1626 }
1627
1628 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1629
1630 switch (current_itr) {
1631 /* counts and packets in update_itr are dependent on these numbers */
1632 case lowest_latency:
1633 new_itr = 100000;
1634 break;
1635 case low_latency:
1636 new_itr = 20000; /* aka hwitr = ~200 */
1637 break;
1638 case bulk_latency:
1639 default:
1640 new_itr = 8000;
1641 break;
1642 }
1643
1644 if (new_itr != q_vector->eitr) {
1645 /* do an exponential smoothing */
1646 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1647
1648 /* save the algorithm value here, not the smoothed one */
1649 q_vector->eitr = new_itr;
1650
1651 ixgbe_write_eitr(q_vector);
1652 }
1653 }
1654
1655 /**
1656 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1657 * @work: pointer to work_struct containing our data
1658 **/
1659 static void ixgbe_check_overtemp_task(struct work_struct *work)
1660 {
1661 struct ixgbe_adapter *adapter = container_of(work,
1662 struct ixgbe_adapter,
1663 check_overtemp_task);
1664 struct ixgbe_hw *hw = &adapter->hw;
1665 u32 eicr = adapter->interrupt_event;
1666
1667 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1668 return;
1669
1670 switch (hw->device_id) {
1671 case IXGBE_DEV_ID_82599_T3_LOM: {
1672 u32 autoneg;
1673 bool link_up = false;
1674
1675 if (hw->mac.ops.check_link)
1676 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1677
1678 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1679 (eicr & IXGBE_EICR_LSC))
1680 /* Check if this is due to overtemp */
1681 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1682 break;
1683 return;
1684 }
1685 default:
1686 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1687 return;
1688 break;
1689 }
1690 e_crit(drv,
1691 "Network adapter has been stopped because it has over heated. "
1692 "Restart the computer. If the problem persists, "
1693 "power off the system and replace the adapter\n");
1694 /* write to clear the interrupt */
1695 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1696 }
1697
1698 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1699 {
1700 struct ixgbe_hw *hw = &adapter->hw;
1701
1702 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1703 (eicr & IXGBE_EICR_GPI_SDP1)) {
1704 e_crit(probe, "Fan has stopped, replace the adapter\n");
1705 /* write to clear the interrupt */
1706 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1707 }
1708 }
1709
1710 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1711 {
1712 struct ixgbe_hw *hw = &adapter->hw;
1713
1714 if (eicr & IXGBE_EICR_GPI_SDP2) {
1715 /* Clear the interrupt */
1716 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1717 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1718 schedule_work(&adapter->sfp_config_module_task);
1719 }
1720
1721 if (eicr & IXGBE_EICR_GPI_SDP1) {
1722 /* Clear the interrupt */
1723 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1724 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1725 schedule_work(&adapter->multispeed_fiber_task);
1726 }
1727 }
1728
1729 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1730 {
1731 struct ixgbe_hw *hw = &adapter->hw;
1732
1733 adapter->lsc_int++;
1734 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1735 adapter->link_check_timeout = jiffies;
1736 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1737 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1738 IXGBE_WRITE_FLUSH(hw);
1739 schedule_work(&adapter->watchdog_task);
1740 }
1741 }
1742
1743 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1744 {
1745 struct net_device *netdev = data;
1746 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1747 struct ixgbe_hw *hw = &adapter->hw;
1748 u32 eicr;
1749
1750 /*
1751 * Workaround for Silicon errata. Use clear-by-write instead
1752 * of clear-by-read. Reading with EICS will return the
1753 * interrupt causes without clearing, which later be done
1754 * with the write to EICR.
1755 */
1756 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1757 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1758
1759 if (eicr & IXGBE_EICR_LSC)
1760 ixgbe_check_lsc(adapter);
1761
1762 if (eicr & IXGBE_EICR_MAILBOX)
1763 ixgbe_msg_task(adapter);
1764
1765 if (hw->mac.type == ixgbe_mac_82598EB)
1766 ixgbe_check_fan_failure(adapter, eicr);
1767
1768 if (hw->mac.type == ixgbe_mac_82599EB) {
1769 ixgbe_check_sfp_event(adapter, eicr);
1770 adapter->interrupt_event = eicr;
1771 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1772 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1773 schedule_work(&adapter->check_overtemp_task);
1774
1775 /* Handle Flow Director Full threshold interrupt */
1776 if (eicr & IXGBE_EICR_FLOW_DIR) {
1777 int i;
1778 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1779 /* Disable transmits before FDIR Re-initialization */
1780 netif_tx_stop_all_queues(netdev);
1781 for (i = 0; i < adapter->num_tx_queues; i++) {
1782 struct ixgbe_ring *tx_ring =
1783 adapter->tx_ring[i];
1784 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1785 &tx_ring->state))
1786 schedule_work(&adapter->fdir_reinit_task);
1787 }
1788 }
1789 }
1790 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1791 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1792
1793 return IRQ_HANDLED;
1794 }
1795
1796 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1797 u64 qmask)
1798 {
1799 u32 mask;
1800
1801 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1802 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1803 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1804 } else {
1805 mask = (qmask & 0xFFFFFFFF);
1806 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1807 mask = (qmask >> 32);
1808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1809 }
1810 /* skip the flush */
1811 }
1812
1813 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1814 u64 qmask)
1815 {
1816 u32 mask;
1817
1818 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1819 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1820 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1821 } else {
1822 mask = (qmask & 0xFFFFFFFF);
1823 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1824 mask = (qmask >> 32);
1825 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1826 }
1827 /* skip the flush */
1828 }
1829
1830 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1831 {
1832 struct ixgbe_q_vector *q_vector = data;
1833 struct ixgbe_adapter *adapter = q_vector->adapter;
1834 struct ixgbe_ring *tx_ring;
1835 int i, r_idx;
1836
1837 if (!q_vector->txr_count)
1838 return IRQ_HANDLED;
1839
1840 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1841 for (i = 0; i < q_vector->txr_count; i++) {
1842 tx_ring = adapter->tx_ring[r_idx];
1843 tx_ring->total_bytes = 0;
1844 tx_ring->total_packets = 0;
1845 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1846 r_idx + 1);
1847 }
1848
1849 /* EIAM disabled interrupts (on this vector) for us */
1850 napi_schedule(&q_vector->napi);
1851
1852 return IRQ_HANDLED;
1853 }
1854
1855 /**
1856 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1857 * @irq: unused
1858 * @data: pointer to our q_vector struct for this interrupt vector
1859 **/
1860 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1861 {
1862 struct ixgbe_q_vector *q_vector = data;
1863 struct ixgbe_adapter *adapter = q_vector->adapter;
1864 struct ixgbe_ring *rx_ring;
1865 int r_idx;
1866 int i;
1867
1868 #ifdef CONFIG_IXGBE_DCA
1869 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1870 ixgbe_update_dca(q_vector);
1871 #endif
1872
1873 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1874 for (i = 0; i < q_vector->rxr_count; i++) {
1875 rx_ring = adapter->rx_ring[r_idx];
1876 rx_ring->total_bytes = 0;
1877 rx_ring->total_packets = 0;
1878 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1879 r_idx + 1);
1880 }
1881
1882 if (!q_vector->rxr_count)
1883 return IRQ_HANDLED;
1884
1885 /* EIAM disabled interrupts (on this vector) for us */
1886 napi_schedule(&q_vector->napi);
1887
1888 return IRQ_HANDLED;
1889 }
1890
1891 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1892 {
1893 struct ixgbe_q_vector *q_vector = data;
1894 struct ixgbe_adapter *adapter = q_vector->adapter;
1895 struct ixgbe_ring *ring;
1896 int r_idx;
1897 int i;
1898
1899 if (!q_vector->txr_count && !q_vector->rxr_count)
1900 return IRQ_HANDLED;
1901
1902 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1903 for (i = 0; i < q_vector->txr_count; i++) {
1904 ring = adapter->tx_ring[r_idx];
1905 ring->total_bytes = 0;
1906 ring->total_packets = 0;
1907 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1908 r_idx + 1);
1909 }
1910
1911 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1912 for (i = 0; i < q_vector->rxr_count; i++) {
1913 ring = adapter->rx_ring[r_idx];
1914 ring->total_bytes = 0;
1915 ring->total_packets = 0;
1916 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1917 r_idx + 1);
1918 }
1919
1920 /* EIAM disabled interrupts (on this vector) for us */
1921 napi_schedule(&q_vector->napi);
1922
1923 return IRQ_HANDLED;
1924 }
1925
1926 /**
1927 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1928 * @napi: napi struct with our devices info in it
1929 * @budget: amount of work driver is allowed to do this pass, in packets
1930 *
1931 * This function is optimized for cleaning one queue only on a single
1932 * q_vector!!!
1933 **/
1934 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1935 {
1936 struct ixgbe_q_vector *q_vector =
1937 container_of(napi, struct ixgbe_q_vector, napi);
1938 struct ixgbe_adapter *adapter = q_vector->adapter;
1939 struct ixgbe_ring *rx_ring = NULL;
1940 int work_done = 0;
1941 long r_idx;
1942
1943 #ifdef CONFIG_IXGBE_DCA
1944 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1945 ixgbe_update_dca(q_vector);
1946 #endif
1947
1948 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1949 rx_ring = adapter->rx_ring[r_idx];
1950
1951 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1952
1953 /* If all Rx work done, exit the polling mode */
1954 if (work_done < budget) {
1955 napi_complete(napi);
1956 if (adapter->rx_itr_setting & 1)
1957 ixgbe_set_itr_msix(q_vector);
1958 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1959 ixgbe_irq_enable_queues(adapter,
1960 ((u64)1 << q_vector->v_idx));
1961 }
1962
1963 return work_done;
1964 }
1965
1966 /**
1967 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1968 * @napi: napi struct with our devices info in it
1969 * @budget: amount of work driver is allowed to do this pass, in packets
1970 *
1971 * This function will clean more than one rx queue associated with a
1972 * q_vector.
1973 **/
1974 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1975 {
1976 struct ixgbe_q_vector *q_vector =
1977 container_of(napi, struct ixgbe_q_vector, napi);
1978 struct ixgbe_adapter *adapter = q_vector->adapter;
1979 struct ixgbe_ring *ring = NULL;
1980 int work_done = 0, i;
1981 long r_idx;
1982 bool tx_clean_complete = true;
1983
1984 #ifdef CONFIG_IXGBE_DCA
1985 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1986 ixgbe_update_dca(q_vector);
1987 #endif
1988
1989 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1990 for (i = 0; i < q_vector->txr_count; i++) {
1991 ring = adapter->tx_ring[r_idx];
1992 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1993 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1994 r_idx + 1);
1995 }
1996
1997 /* attempt to distribute budget to each queue fairly, but don't allow
1998 * the budget to go below 1 because we'll exit polling */
1999 budget /= (q_vector->rxr_count ?: 1);
2000 budget = max(budget, 1);
2001 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2002 for (i = 0; i < q_vector->rxr_count; i++) {
2003 ring = adapter->rx_ring[r_idx];
2004 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2005 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2006 r_idx + 1);
2007 }
2008
2009 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2010 ring = adapter->rx_ring[r_idx];
2011 /* If all Rx work done, exit the polling mode */
2012 if (work_done < budget) {
2013 napi_complete(napi);
2014 if (adapter->rx_itr_setting & 1)
2015 ixgbe_set_itr_msix(q_vector);
2016 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2017 ixgbe_irq_enable_queues(adapter,
2018 ((u64)1 << q_vector->v_idx));
2019 return 0;
2020 }
2021
2022 return work_done;
2023 }
2024
2025 /**
2026 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2027 * @napi: napi struct with our devices info in it
2028 * @budget: amount of work driver is allowed to do this pass, in packets
2029 *
2030 * This function is optimized for cleaning one queue only on a single
2031 * q_vector!!!
2032 **/
2033 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2034 {
2035 struct ixgbe_q_vector *q_vector =
2036 container_of(napi, struct ixgbe_q_vector, napi);
2037 struct ixgbe_adapter *adapter = q_vector->adapter;
2038 struct ixgbe_ring *tx_ring = NULL;
2039 int work_done = 0;
2040 long r_idx;
2041
2042 #ifdef CONFIG_IXGBE_DCA
2043 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2044 ixgbe_update_dca(q_vector);
2045 #endif
2046
2047 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2048 tx_ring = adapter->tx_ring[r_idx];
2049
2050 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2051 work_done = budget;
2052
2053 /* If all Tx work done, exit the polling mode */
2054 if (work_done < budget) {
2055 napi_complete(napi);
2056 if (adapter->tx_itr_setting & 1)
2057 ixgbe_set_itr_msix(q_vector);
2058 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2059 ixgbe_irq_enable_queues(adapter,
2060 ((u64)1 << q_vector->v_idx));
2061 }
2062
2063 return work_done;
2064 }
2065
2066 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2067 int r_idx)
2068 {
2069 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2070
2071 set_bit(r_idx, q_vector->rxr_idx);
2072 q_vector->rxr_count++;
2073 }
2074
2075 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2076 int t_idx)
2077 {
2078 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2079
2080 set_bit(t_idx, q_vector->txr_idx);
2081 q_vector->txr_count++;
2082 }
2083
2084 /**
2085 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2086 * @adapter: board private structure to initialize
2087 * @vectors: allotted vector count for descriptor rings
2088 *
2089 * This function maps descriptor rings to the queue-specific vectors
2090 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2091 * one vector per ring/queue, but on a constrained vector budget, we
2092 * group the rings as "efficiently" as possible. You would add new
2093 * mapping configurations in here.
2094 **/
2095 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2096 int vectors)
2097 {
2098 int v_start = 0;
2099 int rxr_idx = 0, txr_idx = 0;
2100 int rxr_remaining = adapter->num_rx_queues;
2101 int txr_remaining = adapter->num_tx_queues;
2102 int i, j;
2103 int rqpv, tqpv;
2104 int err = 0;
2105
2106 /* No mapping required if MSI-X is disabled. */
2107 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2108 goto out;
2109
2110 /*
2111 * The ideal configuration...
2112 * We have enough vectors to map one per queue.
2113 */
2114 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2115 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2116 map_vector_to_rxq(adapter, v_start, rxr_idx);
2117
2118 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2119 map_vector_to_txq(adapter, v_start, txr_idx);
2120
2121 goto out;
2122 }
2123
2124 /*
2125 * If we don't have enough vectors for a 1-to-1
2126 * mapping, we'll have to group them so there are
2127 * multiple queues per vector.
2128 */
2129 /* Re-adjusting *qpv takes care of the remainder. */
2130 for (i = v_start; i < vectors; i++) {
2131 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2132 for (j = 0; j < rqpv; j++) {
2133 map_vector_to_rxq(adapter, i, rxr_idx);
2134 rxr_idx++;
2135 rxr_remaining--;
2136 }
2137 }
2138 for (i = v_start; i < vectors; i++) {
2139 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2140 for (j = 0; j < tqpv; j++) {
2141 map_vector_to_txq(adapter, i, txr_idx);
2142 txr_idx++;
2143 txr_remaining--;
2144 }
2145 }
2146
2147 out:
2148 return err;
2149 }
2150
2151 /**
2152 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2153 * @adapter: board private structure
2154 *
2155 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2156 * interrupts from the kernel.
2157 **/
2158 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2159 {
2160 struct net_device *netdev = adapter->netdev;
2161 irqreturn_t (*handler)(int, void *);
2162 int i, vector, q_vectors, err;
2163 int ri = 0, ti = 0;
2164
2165 /* Decrement for Other and TCP Timer vectors */
2166 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2167
2168 /* Map the Tx/Rx rings to the vectors we were allotted. */
2169 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2170 if (err)
2171 goto out;
2172
2173 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2174 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2175 &ixgbe_msix_clean_many)
2176 for (vector = 0; vector < q_vectors; vector++) {
2177 handler = SET_HANDLER(adapter->q_vector[vector]);
2178
2179 if (handler == &ixgbe_msix_clean_rx) {
2180 sprintf(adapter->name[vector], "%s-%s-%d",
2181 netdev->name, "rx", ri++);
2182 } else if (handler == &ixgbe_msix_clean_tx) {
2183 sprintf(adapter->name[vector], "%s-%s-%d",
2184 netdev->name, "tx", ti++);
2185 } else
2186 sprintf(adapter->name[vector], "%s-%s-%d",
2187 netdev->name, "TxRx", vector);
2188
2189 err = request_irq(adapter->msix_entries[vector].vector,
2190 handler, 0, adapter->name[vector],
2191 adapter->q_vector[vector]);
2192 if (err) {
2193 e_err(probe, "request_irq failed for MSIX interrupt "
2194 "Error: %d\n", err);
2195 goto free_queue_irqs;
2196 }
2197 }
2198
2199 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2200 err = request_irq(adapter->msix_entries[vector].vector,
2201 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2202 if (err) {
2203 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2204 goto free_queue_irqs;
2205 }
2206
2207 return 0;
2208
2209 free_queue_irqs:
2210 for (i = vector - 1; i >= 0; i--)
2211 free_irq(adapter->msix_entries[--vector].vector,
2212 adapter->q_vector[i]);
2213 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2214 pci_disable_msix(adapter->pdev);
2215 kfree(adapter->msix_entries);
2216 adapter->msix_entries = NULL;
2217 out:
2218 return err;
2219 }
2220
2221 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2222 {
2223 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2224 u8 current_itr;
2225 u32 new_itr = q_vector->eitr;
2226 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2227 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2228
2229 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2230 q_vector->tx_itr,
2231 tx_ring->total_packets,
2232 tx_ring->total_bytes);
2233 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2234 q_vector->rx_itr,
2235 rx_ring->total_packets,
2236 rx_ring->total_bytes);
2237
2238 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2239
2240 switch (current_itr) {
2241 /* counts and packets in update_itr are dependent on these numbers */
2242 case lowest_latency:
2243 new_itr = 100000;
2244 break;
2245 case low_latency:
2246 new_itr = 20000; /* aka hwitr = ~200 */
2247 break;
2248 case bulk_latency:
2249 new_itr = 8000;
2250 break;
2251 default:
2252 break;
2253 }
2254
2255 if (new_itr != q_vector->eitr) {
2256 /* do an exponential smoothing */
2257 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2258
2259 /* save the algorithm value here, not the smoothed one */
2260 q_vector->eitr = new_itr;
2261
2262 ixgbe_write_eitr(q_vector);
2263 }
2264 }
2265
2266 /**
2267 * ixgbe_irq_enable - Enable default interrupt generation settings
2268 * @adapter: board private structure
2269 **/
2270 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2271 bool flush)
2272 {
2273 u32 mask;
2274
2275 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2276 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2277 mask |= IXGBE_EIMS_GPI_SDP0;
2278 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2279 mask |= IXGBE_EIMS_GPI_SDP1;
2280 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2281 mask |= IXGBE_EIMS_ECC;
2282 mask |= IXGBE_EIMS_GPI_SDP1;
2283 mask |= IXGBE_EIMS_GPI_SDP2;
2284 if (adapter->num_vfs)
2285 mask |= IXGBE_EIMS_MAILBOX;
2286 }
2287 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2288 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2289 mask |= IXGBE_EIMS_FLOW_DIR;
2290
2291 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2292 if (queues)
2293 ixgbe_irq_enable_queues(adapter, ~0);
2294 if (flush)
2295 IXGBE_WRITE_FLUSH(&adapter->hw);
2296
2297 if (adapter->num_vfs > 32) {
2298 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2299 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2300 }
2301 }
2302
2303 /**
2304 * ixgbe_intr - legacy mode Interrupt Handler
2305 * @irq: interrupt number
2306 * @data: pointer to a network interface device structure
2307 **/
2308 static irqreturn_t ixgbe_intr(int irq, void *data)
2309 {
2310 struct net_device *netdev = data;
2311 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2312 struct ixgbe_hw *hw = &adapter->hw;
2313 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2314 u32 eicr;
2315
2316 /*
2317 * Workaround for silicon errata on 82598. Mask the interrupts
2318 * before the read of EICR.
2319 */
2320 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2321
2322 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2323 * therefore no explict interrupt disable is necessary */
2324 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2325 if (!eicr) {
2326 /*
2327 * shared interrupt alert!
2328 * make sure interrupts are enabled because the read will
2329 * have disabled interrupts due to EIAM
2330 * finish the workaround of silicon errata on 82598. Unmask
2331 * the interrupt that we masked before the EICR read.
2332 */
2333 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2334 ixgbe_irq_enable(adapter, true, true);
2335 return IRQ_NONE; /* Not our interrupt */
2336 }
2337
2338 if (eicr & IXGBE_EICR_LSC)
2339 ixgbe_check_lsc(adapter);
2340
2341 if (hw->mac.type == ixgbe_mac_82599EB)
2342 ixgbe_check_sfp_event(adapter, eicr);
2343
2344 ixgbe_check_fan_failure(adapter, eicr);
2345 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2346 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2347 schedule_work(&adapter->check_overtemp_task);
2348
2349 if (napi_schedule_prep(&(q_vector->napi))) {
2350 adapter->tx_ring[0]->total_packets = 0;
2351 adapter->tx_ring[0]->total_bytes = 0;
2352 adapter->rx_ring[0]->total_packets = 0;
2353 adapter->rx_ring[0]->total_bytes = 0;
2354 /* would disable interrupts here but EIAM disabled it */
2355 __napi_schedule(&(q_vector->napi));
2356 }
2357
2358 /*
2359 * re-enable link(maybe) and non-queue interrupts, no flush.
2360 * ixgbe_poll will re-enable the queue interrupts
2361 */
2362
2363 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2364 ixgbe_irq_enable(adapter, false, false);
2365
2366 return IRQ_HANDLED;
2367 }
2368
2369 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2370 {
2371 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2372
2373 for (i = 0; i < q_vectors; i++) {
2374 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2375 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2376 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2377 q_vector->rxr_count = 0;
2378 q_vector->txr_count = 0;
2379 }
2380 }
2381
2382 /**
2383 * ixgbe_request_irq - initialize interrupts
2384 * @adapter: board private structure
2385 *
2386 * Attempts to configure interrupts using the best available
2387 * capabilities of the hardware and kernel.
2388 **/
2389 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2390 {
2391 struct net_device *netdev = adapter->netdev;
2392 int err;
2393
2394 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2395 err = ixgbe_request_msix_irqs(adapter);
2396 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2397 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2398 netdev->name, netdev);
2399 } else {
2400 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2401 netdev->name, netdev);
2402 }
2403
2404 if (err)
2405 e_err(probe, "request_irq failed, Error %d\n", err);
2406
2407 return err;
2408 }
2409
2410 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2411 {
2412 struct net_device *netdev = adapter->netdev;
2413
2414 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2415 int i, q_vectors;
2416
2417 q_vectors = adapter->num_msix_vectors;
2418
2419 i = q_vectors - 1;
2420 free_irq(adapter->msix_entries[i].vector, netdev);
2421
2422 i--;
2423 for (; i >= 0; i--) {
2424 free_irq(adapter->msix_entries[i].vector,
2425 adapter->q_vector[i]);
2426 }
2427
2428 ixgbe_reset_q_vectors(adapter);
2429 } else {
2430 free_irq(adapter->pdev->irq, netdev);
2431 }
2432 }
2433
2434 /**
2435 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2436 * @adapter: board private structure
2437 **/
2438 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2439 {
2440 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2441 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2442 } else {
2443 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2444 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2445 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2446 if (adapter->num_vfs > 32)
2447 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2448 }
2449 IXGBE_WRITE_FLUSH(&adapter->hw);
2450 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2451 int i;
2452 for (i = 0; i < adapter->num_msix_vectors; i++)
2453 synchronize_irq(adapter->msix_entries[i].vector);
2454 } else {
2455 synchronize_irq(adapter->pdev->irq);
2456 }
2457 }
2458
2459 /**
2460 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2461 *
2462 **/
2463 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2464 {
2465 struct ixgbe_hw *hw = &adapter->hw;
2466
2467 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2468 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2469
2470 ixgbe_set_ivar(adapter, 0, 0, 0);
2471 ixgbe_set_ivar(adapter, 1, 0, 0);
2472
2473 map_vector_to_rxq(adapter, 0, 0);
2474 map_vector_to_txq(adapter, 0, 0);
2475
2476 e_info(hw, "Legacy interrupt IVAR setup done\n");
2477 }
2478
2479 /**
2480 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2481 * @adapter: board private structure
2482 * @ring: structure containing ring specific data
2483 *
2484 * Configure the Tx descriptor ring after a reset.
2485 **/
2486 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2487 struct ixgbe_ring *ring)
2488 {
2489 struct ixgbe_hw *hw = &adapter->hw;
2490 u64 tdba = ring->dma;
2491 int wait_loop = 10;
2492 u32 txdctl;
2493 u16 reg_idx = ring->reg_idx;
2494
2495 /* disable queue to avoid issues while updating state */
2496 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2497 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2498 txdctl & ~IXGBE_TXDCTL_ENABLE);
2499 IXGBE_WRITE_FLUSH(hw);
2500
2501 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2502 (tdba & DMA_BIT_MASK(32)));
2503 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2504 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2505 ring->count * sizeof(union ixgbe_adv_tx_desc));
2506 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2507 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2508 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2509
2510 /* configure fetching thresholds */
2511 if (adapter->rx_itr_setting == 0) {
2512 /* cannot set wthresh when itr==0 */
2513 txdctl &= ~0x007F0000;
2514 } else {
2515 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2516 txdctl |= (8 << 16);
2517 }
2518 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2519 /* PThresh workaround for Tx hang with DFP enabled. */
2520 txdctl |= 32;
2521 }
2522
2523 /* reinitialize flowdirector state */
2524 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2525
2526 /* enable queue */
2527 txdctl |= IXGBE_TXDCTL_ENABLE;
2528 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2529
2530 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2531 if (hw->mac.type == ixgbe_mac_82598EB &&
2532 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2533 return;
2534
2535 /* poll to verify queue is enabled */
2536 do {
2537 msleep(1);
2538 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2539 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2540 if (!wait_loop)
2541 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2542 }
2543
2544 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2545 {
2546 struct ixgbe_hw *hw = &adapter->hw;
2547 u32 rttdcs;
2548 u32 mask;
2549
2550 if (hw->mac.type == ixgbe_mac_82598EB)
2551 return;
2552
2553 /* disable the arbiter while setting MTQC */
2554 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2555 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2556 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2557
2558 /* set transmit pool layout */
2559 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2560 switch (adapter->flags & mask) {
2561
2562 case (IXGBE_FLAG_SRIOV_ENABLED):
2563 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2564 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2565 break;
2566
2567 case (IXGBE_FLAG_DCB_ENABLED):
2568 /* We enable 8 traffic classes, DCB only */
2569 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2570 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2571 break;
2572
2573 default:
2574 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2575 break;
2576 }
2577
2578 /* re-enable the arbiter */
2579 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2580 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2581 }
2582
2583 /**
2584 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2585 * @adapter: board private structure
2586 *
2587 * Configure the Tx unit of the MAC after a reset.
2588 **/
2589 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2590 {
2591 struct ixgbe_hw *hw = &adapter->hw;
2592 u32 dmatxctl;
2593 u32 i;
2594
2595 ixgbe_setup_mtqc(adapter);
2596
2597 if (hw->mac.type != ixgbe_mac_82598EB) {
2598 /* DMATXCTL.EN must be before Tx queues are enabled */
2599 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2600 dmatxctl |= IXGBE_DMATXCTL_TE;
2601 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2602 }
2603
2604 /* Setup the HW Tx Head and Tail descriptor pointers */
2605 for (i = 0; i < adapter->num_tx_queues; i++)
2606 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2607 }
2608
2609 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2610
2611 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2612 struct ixgbe_ring *rx_ring)
2613 {
2614 u32 srrctl;
2615 int index;
2616 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2617
2618 index = rx_ring->reg_idx;
2619 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2620 unsigned long mask;
2621 mask = (unsigned long) feature[RING_F_RSS].mask;
2622 index = index & mask;
2623 }
2624 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2625
2626 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2627 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2628 if (adapter->num_vfs)
2629 srrctl |= IXGBE_SRRCTL_DROP_EN;
2630
2631 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2632 IXGBE_SRRCTL_BSIZEHDR_MASK;
2633
2634 if (ring_is_ps_enabled(rx_ring)) {
2635 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2636 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2637 #else
2638 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2639 #endif
2640 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2641 } else {
2642 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2643 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2644 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2645 }
2646
2647 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2648 }
2649
2650 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2651 {
2652 struct ixgbe_hw *hw = &adapter->hw;
2653 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2654 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2655 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2656 u32 mrqc = 0, reta = 0;
2657 u32 rxcsum;
2658 int i, j;
2659 int mask;
2660
2661 /* Fill out hash function seeds */
2662 for (i = 0; i < 10; i++)
2663 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2664
2665 /* Fill out redirection table */
2666 for (i = 0, j = 0; i < 128; i++, j++) {
2667 if (j == adapter->ring_feature[RING_F_RSS].indices)
2668 j = 0;
2669 /* reta = 4-byte sliding window of
2670 * 0x00..(indices-1)(indices-1)00..etc. */
2671 reta = (reta << 8) | (j * 0x11);
2672 if ((i & 3) == 3)
2673 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2674 }
2675
2676 /* Disable indicating checksum in descriptor, enables RSS hash */
2677 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2678 rxcsum |= IXGBE_RXCSUM_PCSD;
2679 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2680
2681 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2682 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2683 else
2684 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2685 #ifdef CONFIG_IXGBE_DCB
2686 | IXGBE_FLAG_DCB_ENABLED
2687 #endif
2688 | IXGBE_FLAG_SRIOV_ENABLED
2689 );
2690
2691 switch (mask) {
2692 case (IXGBE_FLAG_RSS_ENABLED):
2693 mrqc = IXGBE_MRQC_RSSEN;
2694 break;
2695 case (IXGBE_FLAG_SRIOV_ENABLED):
2696 mrqc = IXGBE_MRQC_VMDQEN;
2697 break;
2698 #ifdef CONFIG_IXGBE_DCB
2699 case (IXGBE_FLAG_DCB_ENABLED):
2700 mrqc = IXGBE_MRQC_RT8TCEN;
2701 break;
2702 #endif /* CONFIG_IXGBE_DCB */
2703 default:
2704 break;
2705 }
2706
2707 /* Perform hash on these packet types */
2708 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2709 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2710 | IXGBE_MRQC_RSS_FIELD_IPV6
2711 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2712
2713 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2714 }
2715
2716 /**
2717 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2718 * @adapter: address of board private structure
2719 * @index: index of ring to set
2720 **/
2721 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2722 struct ixgbe_ring *ring)
2723 {
2724 struct ixgbe_hw *hw = &adapter->hw;
2725 u32 rscctrl;
2726 int rx_buf_len;
2727 u16 reg_idx = ring->reg_idx;
2728
2729 if (!ring_is_rsc_enabled(ring))
2730 return;
2731
2732 rx_buf_len = ring->rx_buf_len;
2733 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2734 rscctrl |= IXGBE_RSCCTL_RSCEN;
2735 /*
2736 * we must limit the number of descriptors so that the
2737 * total size of max desc * buf_len is not greater
2738 * than 65535
2739 */
2740 if (ring_is_ps_enabled(ring)) {
2741 #if (MAX_SKB_FRAGS > 16)
2742 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2743 #elif (MAX_SKB_FRAGS > 8)
2744 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2745 #elif (MAX_SKB_FRAGS > 4)
2746 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2747 #else
2748 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2749 #endif
2750 } else {
2751 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2752 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2753 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2754 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2755 else
2756 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2757 }
2758 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2759 }
2760
2761 /**
2762 * ixgbe_set_uta - Set unicast filter table address
2763 * @adapter: board private structure
2764 *
2765 * The unicast table address is a register array of 32-bit registers.
2766 * The table is meant to be used in a way similar to how the MTA is used
2767 * however due to certain limitations in the hardware it is necessary to
2768 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2769 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2770 **/
2771 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2772 {
2773 struct ixgbe_hw *hw = &adapter->hw;
2774 int i;
2775
2776 /* The UTA table only exists on 82599 hardware and newer */
2777 if (hw->mac.type < ixgbe_mac_82599EB)
2778 return;
2779
2780 /* we only need to do this if VMDq is enabled */
2781 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2782 return;
2783
2784 for (i = 0; i < 128; i++)
2785 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2786 }
2787
2788 #define IXGBE_MAX_RX_DESC_POLL 10
2789 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2790 struct ixgbe_ring *ring)
2791 {
2792 struct ixgbe_hw *hw = &adapter->hw;
2793 int reg_idx = ring->reg_idx;
2794 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2795 u32 rxdctl;
2796
2797 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2798 if (hw->mac.type == ixgbe_mac_82598EB &&
2799 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2800 return;
2801
2802 do {
2803 msleep(1);
2804 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2805 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2806
2807 if (!wait_loop) {
2808 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2809 "the polling period\n", reg_idx);
2810 }
2811 }
2812
2813 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2814 struct ixgbe_ring *ring)
2815 {
2816 struct ixgbe_hw *hw = &adapter->hw;
2817 u64 rdba = ring->dma;
2818 u32 rxdctl;
2819 u16 reg_idx = ring->reg_idx;
2820
2821 /* disable queue to avoid issues while updating state */
2822 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2823 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2824 rxdctl & ~IXGBE_RXDCTL_ENABLE);
2825 IXGBE_WRITE_FLUSH(hw);
2826
2827 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2828 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2829 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2830 ring->count * sizeof(union ixgbe_adv_rx_desc));
2831 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2832 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2833 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2834
2835 ixgbe_configure_srrctl(adapter, ring);
2836 ixgbe_configure_rscctl(adapter, ring);
2837
2838 if (hw->mac.type == ixgbe_mac_82598EB) {
2839 /*
2840 * enable cache line friendly hardware writes:
2841 * PTHRESH=32 descriptors (half the internal cache),
2842 * this also removes ugly rx_no_buffer_count increment
2843 * HTHRESH=4 descriptors (to minimize latency on fetch)
2844 * WTHRESH=8 burst writeback up to two cache lines
2845 */
2846 rxdctl &= ~0x3FFFFF;
2847 rxdctl |= 0x080420;
2848 }
2849
2850 /* enable receive descriptor ring */
2851 rxdctl |= IXGBE_RXDCTL_ENABLE;
2852 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2853
2854 ixgbe_rx_desc_queue_enable(adapter, ring);
2855 ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
2856 }
2857
2858 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2859 {
2860 struct ixgbe_hw *hw = &adapter->hw;
2861 int p;
2862
2863 /* PSRTYPE must be initialized in non 82598 adapters */
2864 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2865 IXGBE_PSRTYPE_UDPHDR |
2866 IXGBE_PSRTYPE_IPV4HDR |
2867 IXGBE_PSRTYPE_L2HDR |
2868 IXGBE_PSRTYPE_IPV6HDR;
2869
2870 if (hw->mac.type == ixgbe_mac_82598EB)
2871 return;
2872
2873 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2874 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2875
2876 for (p = 0; p < adapter->num_rx_pools; p++)
2877 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2878 psrtype);
2879 }
2880
2881 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2882 {
2883 struct ixgbe_hw *hw = &adapter->hw;
2884 u32 gcr_ext;
2885 u32 vt_reg_bits;
2886 u32 reg_offset, vf_shift;
2887 u32 vmdctl;
2888
2889 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2890 return;
2891
2892 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2893 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2894 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2895 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2896
2897 vf_shift = adapter->num_vfs % 32;
2898 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2899
2900 /* Enable only the PF's pool for Tx/Rx */
2901 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2902 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2903 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2904 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2905 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2906
2907 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2908 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2909
2910 /*
2911 * Set up VF register offsets for selected VT Mode,
2912 * i.e. 32 or 64 VFs for SR-IOV
2913 */
2914 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2915 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2916 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2917 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2918
2919 /* enable Tx loopback for VF/PF communication */
2920 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2921 }
2922
2923 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2924 {
2925 struct ixgbe_hw *hw = &adapter->hw;
2926 struct net_device *netdev = adapter->netdev;
2927 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2928 int rx_buf_len;
2929 struct ixgbe_ring *rx_ring;
2930 int i;
2931 u32 mhadd, hlreg0;
2932
2933 /* Decide whether to use packet split mode or not */
2934 /* Do not use packet split if we're in SR-IOV Mode */
2935 if (!adapter->num_vfs)
2936 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2937
2938 /* Set the RX buffer length according to the mode */
2939 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2940 rx_buf_len = IXGBE_RX_HDR_SIZE;
2941 } else {
2942 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2943 (netdev->mtu <= ETH_DATA_LEN))
2944 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2945 else
2946 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2947 }
2948
2949 #ifdef IXGBE_FCOE
2950 /* adjust max frame to be able to do baby jumbo for FCoE */
2951 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2952 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2953 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2954
2955 #endif /* IXGBE_FCOE */
2956 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2957 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2958 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2959 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2960
2961 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2962 }
2963
2964 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2965 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2966 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2967 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2968
2969 /*
2970 * Setup the HW Rx Head and Tail Descriptor Pointers and
2971 * the Base and Length of the Rx Descriptor Ring
2972 */
2973 for (i = 0; i < adapter->num_rx_queues; i++) {
2974 rx_ring = adapter->rx_ring[i];
2975 rx_ring->rx_buf_len = rx_buf_len;
2976
2977 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2978 set_ring_ps_enabled(rx_ring);
2979 else
2980 clear_ring_ps_enabled(rx_ring);
2981
2982 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2983 set_ring_rsc_enabled(rx_ring);
2984 else
2985 clear_ring_rsc_enabled(rx_ring);
2986
2987 #ifdef IXGBE_FCOE
2988 if (netdev->features & NETIF_F_FCOE_MTU) {
2989 struct ixgbe_ring_feature *f;
2990 f = &adapter->ring_feature[RING_F_FCOE];
2991 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2992 clear_ring_ps_enabled(rx_ring);
2993 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2994 rx_ring->rx_buf_len =
2995 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2996 } else if (!ring_is_rsc_enabled(rx_ring) &&
2997 !ring_is_ps_enabled(rx_ring)) {
2998 rx_ring->rx_buf_len =
2999 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3000 }
3001 }
3002 #endif /* IXGBE_FCOE */
3003 }
3004
3005 }
3006
3007 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3008 {
3009 struct ixgbe_hw *hw = &adapter->hw;
3010 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3011
3012 switch (hw->mac.type) {
3013 case ixgbe_mac_82598EB:
3014 /*
3015 * For VMDq support of different descriptor types or
3016 * buffer sizes through the use of multiple SRRCTL
3017 * registers, RDRXCTL.MVMEN must be set to 1
3018 *
3019 * also, the manual doesn't mention it clearly but DCA hints
3020 * will only use queue 0's tags unless this bit is set. Side
3021 * effects of setting this bit are only that SRRCTL must be
3022 * fully programmed [0..15]
3023 */
3024 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3025 break;
3026 case ixgbe_mac_82599EB:
3027 /* Disable RSC for ACK packets */
3028 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3029 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3030 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3031 /* hardware requires some bits to be set by default */
3032 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3033 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3034 break;
3035 default:
3036 /* We should do nothing since we don't know this hardware */
3037 return;
3038 }
3039
3040 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3041 }
3042
3043 /**
3044 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3045 * @adapter: board private structure
3046 *
3047 * Configure the Rx unit of the MAC after a reset.
3048 **/
3049 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3050 {
3051 struct ixgbe_hw *hw = &adapter->hw;
3052 int i;
3053 u32 rxctrl;
3054
3055 /* disable receives while setting up the descriptors */
3056 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3057 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3058
3059 ixgbe_setup_psrtype(adapter);
3060 ixgbe_setup_rdrxctl(adapter);
3061
3062 /* Program registers for the distribution of queues */
3063 ixgbe_setup_mrqc(adapter);
3064
3065 ixgbe_set_uta(adapter);
3066
3067 /* set_rx_buffer_len must be called before ring initialization */
3068 ixgbe_set_rx_buffer_len(adapter);
3069
3070 /*
3071 * Setup the HW Rx Head and Tail Descriptor Pointers and
3072 * the Base and Length of the Rx Descriptor Ring
3073 */
3074 for (i = 0; i < adapter->num_rx_queues; i++)
3075 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3076
3077 /* disable drop enable for 82598 parts */
3078 if (hw->mac.type == ixgbe_mac_82598EB)
3079 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3080
3081 /* enable all receives */
3082 rxctrl |= IXGBE_RXCTRL_RXEN;
3083 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3084 }
3085
3086 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3087 {
3088 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3089 struct ixgbe_hw *hw = &adapter->hw;
3090 int pool_ndx = adapter->num_vfs;
3091
3092 /* add VID to filter table */
3093 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3094 set_bit(vid, adapter->active_vlans);
3095 }
3096
3097 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3098 {
3099 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3100 struct ixgbe_hw *hw = &adapter->hw;
3101 int pool_ndx = adapter->num_vfs;
3102
3103 /* remove VID from filter table */
3104 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3105 clear_bit(vid, adapter->active_vlans);
3106 }
3107
3108 /**
3109 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3110 * @adapter: driver data
3111 */
3112 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3113 {
3114 struct ixgbe_hw *hw = &adapter->hw;
3115 u32 vlnctrl;
3116
3117 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3118 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3119 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3120 }
3121
3122 /**
3123 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3124 * @adapter: driver data
3125 */
3126 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3127 {
3128 struct ixgbe_hw *hw = &adapter->hw;
3129 u32 vlnctrl;
3130
3131 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3132 vlnctrl |= IXGBE_VLNCTRL_VFE;
3133 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3134 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3135 }
3136
3137 /**
3138 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3139 * @adapter: driver data
3140 */
3141 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3142 {
3143 struct ixgbe_hw *hw = &adapter->hw;
3144 u32 vlnctrl;
3145 int i, j;
3146
3147 switch (hw->mac.type) {
3148 case ixgbe_mac_82598EB:
3149 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3150 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3151 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3152 break;
3153 case ixgbe_mac_82599EB:
3154 for (i = 0; i < adapter->num_rx_queues; i++) {
3155 j = adapter->rx_ring[i]->reg_idx;
3156 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3157 vlnctrl &= ~IXGBE_RXDCTL_VME;
3158 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3159 }
3160 break;
3161 default:
3162 break;
3163 }
3164 }
3165
3166 /**
3167 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3168 * @adapter: driver data
3169 */
3170 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3171 {
3172 struct ixgbe_hw *hw = &adapter->hw;
3173 u32 vlnctrl;
3174 int i, j;
3175
3176 switch (hw->mac.type) {
3177 case ixgbe_mac_82598EB:
3178 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3179 vlnctrl |= IXGBE_VLNCTRL_VME;
3180 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3181 break;
3182 case ixgbe_mac_82599EB:
3183 for (i = 0; i < adapter->num_rx_queues; i++) {
3184 j = adapter->rx_ring[i]->reg_idx;
3185 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3186 vlnctrl |= IXGBE_RXDCTL_VME;
3187 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3188 }
3189 break;
3190 default:
3191 break;
3192 }
3193 }
3194
3195 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3196 {
3197 u16 vid;
3198
3199 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3200
3201 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3202 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3203 }
3204
3205 /**
3206 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3207 * @netdev: network interface device structure
3208 *
3209 * Writes unicast address list to the RAR table.
3210 * Returns: -ENOMEM on failure/insufficient address space
3211 * 0 on no addresses written
3212 * X on writing X addresses to the RAR table
3213 **/
3214 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3215 {
3216 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3217 struct ixgbe_hw *hw = &adapter->hw;
3218 unsigned int vfn = adapter->num_vfs;
3219 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3220 int count = 0;
3221
3222 /* return ENOMEM indicating insufficient memory for addresses */
3223 if (netdev_uc_count(netdev) > rar_entries)
3224 return -ENOMEM;
3225
3226 if (!netdev_uc_empty(netdev) && rar_entries) {
3227 struct netdev_hw_addr *ha;
3228 /* return error if we do not support writing to RAR table */
3229 if (!hw->mac.ops.set_rar)
3230 return -ENOMEM;
3231
3232 netdev_for_each_uc_addr(ha, netdev) {
3233 if (!rar_entries)
3234 break;
3235 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3236 vfn, IXGBE_RAH_AV);
3237 count++;
3238 }
3239 }
3240 /* write the addresses in reverse order to avoid write combining */
3241 for (; rar_entries > 0 ; rar_entries--)
3242 hw->mac.ops.clear_rar(hw, rar_entries);
3243
3244 return count;
3245 }
3246
3247 /**
3248 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3249 * @netdev: network interface device structure
3250 *
3251 * The set_rx_method entry point is called whenever the unicast/multicast
3252 * address list or the network interface flags are updated. This routine is
3253 * responsible for configuring the hardware for proper unicast, multicast and
3254 * promiscuous mode.
3255 **/
3256 void ixgbe_set_rx_mode(struct net_device *netdev)
3257 {
3258 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3259 struct ixgbe_hw *hw = &adapter->hw;
3260 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3261 int count;
3262
3263 /* Check for Promiscuous and All Multicast modes */
3264
3265 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3266
3267 /* set all bits that we expect to always be set */
3268 fctrl |= IXGBE_FCTRL_BAM;
3269 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3270 fctrl |= IXGBE_FCTRL_PMCF;
3271
3272 /* clear the bits we are changing the status of */
3273 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3274
3275 if (netdev->flags & IFF_PROMISC) {
3276 hw->addr_ctrl.user_set_promisc = true;
3277 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3278 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3279 /* don't hardware filter vlans in promisc mode */
3280 ixgbe_vlan_filter_disable(adapter);
3281 } else {
3282 if (netdev->flags & IFF_ALLMULTI) {
3283 fctrl |= IXGBE_FCTRL_MPE;
3284 vmolr |= IXGBE_VMOLR_MPE;
3285 } else {
3286 /*
3287 * Write addresses to the MTA, if the attempt fails
3288 * then we should just turn on promiscous mode so
3289 * that we can at least receive multicast traffic
3290 */
3291 hw->mac.ops.update_mc_addr_list(hw, netdev);
3292 vmolr |= IXGBE_VMOLR_ROMPE;
3293 }
3294 ixgbe_vlan_filter_enable(adapter);
3295 hw->addr_ctrl.user_set_promisc = false;
3296 /*
3297 * Write addresses to available RAR registers, if there is not
3298 * sufficient space to store all the addresses then enable
3299 * unicast promiscous mode
3300 */
3301 count = ixgbe_write_uc_addr_list(netdev);
3302 if (count < 0) {
3303 fctrl |= IXGBE_FCTRL_UPE;
3304 vmolr |= IXGBE_VMOLR_ROPE;
3305 }
3306 }
3307
3308 if (adapter->num_vfs) {
3309 ixgbe_restore_vf_multicasts(adapter);
3310 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3311 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3312 IXGBE_VMOLR_ROPE);
3313 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3314 }
3315
3316 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3317
3318 if (netdev->features & NETIF_F_HW_VLAN_RX)
3319 ixgbe_vlan_strip_enable(adapter);
3320 else
3321 ixgbe_vlan_strip_disable(adapter);
3322 }
3323
3324 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3325 {
3326 int q_idx;
3327 struct ixgbe_q_vector *q_vector;
3328 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3329
3330 /* legacy and MSI only use one vector */
3331 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3332 q_vectors = 1;
3333
3334 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3335 struct napi_struct *napi;
3336 q_vector = adapter->q_vector[q_idx];
3337 napi = &q_vector->napi;
3338 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3339 if (!q_vector->rxr_count || !q_vector->txr_count) {
3340 if (q_vector->txr_count == 1)
3341 napi->poll = &ixgbe_clean_txonly;
3342 else if (q_vector->rxr_count == 1)
3343 napi->poll = &ixgbe_clean_rxonly;
3344 }
3345 }
3346
3347 napi_enable(napi);
3348 }
3349 }
3350
3351 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3352 {
3353 int q_idx;
3354 struct ixgbe_q_vector *q_vector;
3355 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3356
3357 /* legacy and MSI only use one vector */
3358 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3359 q_vectors = 1;
3360
3361 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3362 q_vector = adapter->q_vector[q_idx];
3363 napi_disable(&q_vector->napi);
3364 }
3365 }
3366
3367 #ifdef CONFIG_IXGBE_DCB
3368 /*
3369 * ixgbe_configure_dcb - Configure DCB hardware
3370 * @adapter: ixgbe adapter struct
3371 *
3372 * This is called by the driver on open to configure the DCB hardware.
3373 * This is also called by the gennetlink interface when reconfiguring
3374 * the DCB state.
3375 */
3376 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3377 {
3378 struct ixgbe_hw *hw = &adapter->hw;
3379 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3380
3381 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3382 if (hw->mac.type == ixgbe_mac_82598EB)
3383 netif_set_gso_max_size(adapter->netdev, 65536);
3384 return;
3385 }
3386
3387 if (hw->mac.type == ixgbe_mac_82598EB)
3388 netif_set_gso_max_size(adapter->netdev, 32768);
3389
3390 #ifdef CONFIG_FCOE
3391 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3392 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3393 #endif
3394
3395 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3396 DCB_TX_CONFIG);
3397 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3398 DCB_RX_CONFIG);
3399
3400 /* Enable VLAN tag insert/strip */
3401 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3402
3403 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3404
3405 /* reconfigure the hardware */
3406 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3407 }
3408
3409 #endif
3410 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3411 {
3412 struct net_device *netdev = adapter->netdev;
3413 struct ixgbe_hw *hw = &adapter->hw;
3414 int i;
3415
3416 #ifdef CONFIG_IXGBE_DCB
3417 ixgbe_configure_dcb(adapter);
3418 #endif
3419
3420 ixgbe_set_rx_mode(netdev);
3421 ixgbe_restore_vlan(adapter);
3422
3423 #ifdef IXGBE_FCOE
3424 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3425 ixgbe_configure_fcoe(adapter);
3426
3427 #endif /* IXGBE_FCOE */
3428 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3429 for (i = 0; i < adapter->num_tx_queues; i++)
3430 adapter->tx_ring[i]->atr_sample_rate =
3431 adapter->atr_sample_rate;
3432 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3433 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3434 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3435 }
3436 ixgbe_configure_virtualization(adapter);
3437
3438 ixgbe_configure_tx(adapter);
3439 ixgbe_configure_rx(adapter);
3440 }
3441
3442 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3443 {
3444 switch (hw->phy.type) {
3445 case ixgbe_phy_sfp_avago:
3446 case ixgbe_phy_sfp_ftl:
3447 case ixgbe_phy_sfp_intel:
3448 case ixgbe_phy_sfp_unknown:
3449 case ixgbe_phy_sfp_passive_tyco:
3450 case ixgbe_phy_sfp_passive_unknown:
3451 case ixgbe_phy_sfp_active_unknown:
3452 case ixgbe_phy_sfp_ftl_active:
3453 return true;
3454 default:
3455 return false;
3456 }
3457 }
3458
3459 /**
3460 * ixgbe_sfp_link_config - set up SFP+ link
3461 * @adapter: pointer to private adapter struct
3462 **/
3463 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3464 {
3465 struct ixgbe_hw *hw = &adapter->hw;
3466
3467 if (hw->phy.multispeed_fiber) {
3468 /*
3469 * In multispeed fiber setups, the device may not have
3470 * had a physical connection when the driver loaded.
3471 * If that's the case, the initial link configuration
3472 * couldn't get the MAC into 10G or 1G mode, so we'll
3473 * never have a link status change interrupt fire.
3474 * We need to try and force an autonegotiation
3475 * session, then bring up link.
3476 */
3477 hw->mac.ops.setup_sfp(hw);
3478 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3479 schedule_work(&adapter->multispeed_fiber_task);
3480 } else {
3481 /*
3482 * Direct Attach Cu and non-multispeed fiber modules
3483 * still need to be configured properly prior to
3484 * attempting link.
3485 */
3486 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3487 schedule_work(&adapter->sfp_config_module_task);
3488 }
3489 }
3490
3491 /**
3492 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3493 * @hw: pointer to private hardware struct
3494 *
3495 * Returns 0 on success, negative on failure
3496 **/
3497 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3498 {
3499 u32 autoneg;
3500 bool negotiation, link_up = false;
3501 u32 ret = IXGBE_ERR_LINK_SETUP;
3502
3503 if (hw->mac.ops.check_link)
3504 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3505
3506 if (ret)
3507 goto link_cfg_out;
3508
3509 if (hw->mac.ops.get_link_capabilities)
3510 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3511 &negotiation);
3512 if (ret)
3513 goto link_cfg_out;
3514
3515 if (hw->mac.ops.setup_link)
3516 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3517 link_cfg_out:
3518 return ret;
3519 }
3520
3521 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3522 {
3523 struct ixgbe_hw *hw = &adapter->hw;
3524 u32 gpie = 0;
3525
3526 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3527 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3528 IXGBE_GPIE_OCD;
3529 gpie |= IXGBE_GPIE_EIAME;
3530 /*
3531 * use EIAM to auto-mask when MSI-X interrupt is asserted
3532 * this saves a register write for every interrupt
3533 */
3534 switch (hw->mac.type) {
3535 case ixgbe_mac_82598EB:
3536 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3537 break;
3538 default:
3539 case ixgbe_mac_82599EB:
3540 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3541 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3542 break;
3543 }
3544 } else {
3545 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3546 * specifically only auto mask tx and rx interrupts */
3547 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3548 }
3549
3550 /* XXX: to interrupt immediately for EICS writes, enable this */
3551 /* gpie |= IXGBE_GPIE_EIMEN; */
3552
3553 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3554 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3555 gpie |= IXGBE_GPIE_VTMODE_64;
3556 }
3557
3558 /* Enable fan failure interrupt */
3559 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3560 gpie |= IXGBE_SDP1_GPIEN;
3561
3562 if (hw->mac.type == ixgbe_mac_82599EB)
3563 gpie |= IXGBE_SDP1_GPIEN;
3564 gpie |= IXGBE_SDP2_GPIEN;
3565
3566 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3567 }
3568
3569 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3570 {
3571 struct ixgbe_hw *hw = &adapter->hw;
3572 int err;
3573 u32 ctrl_ext;
3574
3575 ixgbe_get_hw_control(adapter);
3576 ixgbe_setup_gpie(adapter);
3577
3578 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3579 ixgbe_configure_msix(adapter);
3580 else
3581 ixgbe_configure_msi_and_legacy(adapter);
3582
3583 /* enable the optics */
3584 if (hw->phy.multispeed_fiber)
3585 hw->mac.ops.enable_tx_laser(hw);
3586
3587 clear_bit(__IXGBE_DOWN, &adapter->state);
3588 ixgbe_napi_enable_all(adapter);
3589
3590 if (ixgbe_is_sfp(hw)) {
3591 ixgbe_sfp_link_config(adapter);
3592 } else {
3593 err = ixgbe_non_sfp_link_config(hw);
3594 if (err)
3595 e_err(probe, "link_config FAILED %d\n", err);
3596 }
3597
3598 /* clear any pending interrupts, may auto mask */
3599 IXGBE_READ_REG(hw, IXGBE_EICR);
3600 ixgbe_irq_enable(adapter, true, true);
3601
3602 /*
3603 * If this adapter has a fan, check to see if we had a failure
3604 * before we enabled the interrupt.
3605 */
3606 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3607 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3608 if (esdp & IXGBE_ESDP_SDP1)
3609 e_crit(drv, "Fan has stopped, replace the adapter\n");
3610 }
3611
3612 /*
3613 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3614 * arrived before interrupts were enabled but after probe. Such
3615 * devices wouldn't have their type identified yet. We need to
3616 * kick off the SFP+ module setup first, then try to bring up link.
3617 * If we're not hot-pluggable SFP+, we just need to configure link
3618 * and bring it up.
3619 */
3620 if (hw->phy.type == ixgbe_phy_unknown)
3621 schedule_work(&adapter->sfp_config_module_task);
3622
3623 /* enable transmits */
3624 netif_tx_start_all_queues(adapter->netdev);
3625
3626 /* bring the link up in the watchdog, this could race with our first
3627 * link up interrupt but shouldn't be a problem */
3628 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3629 adapter->link_check_timeout = jiffies;
3630 mod_timer(&adapter->watchdog_timer, jiffies);
3631
3632 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3633 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3634 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3635 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3636
3637 return 0;
3638 }
3639
3640 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3641 {
3642 WARN_ON(in_interrupt());
3643 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3644 msleep(1);
3645 ixgbe_down(adapter);
3646 /*
3647 * If SR-IOV enabled then wait a bit before bringing the adapter
3648 * back up to give the VFs time to respond to the reset. The
3649 * two second wait is based upon the watchdog timer cycle in
3650 * the VF driver.
3651 */
3652 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3653 msleep(2000);
3654 ixgbe_up(adapter);
3655 clear_bit(__IXGBE_RESETTING, &adapter->state);
3656 }
3657
3658 int ixgbe_up(struct ixgbe_adapter *adapter)
3659 {
3660 /* hardware has been reset, we need to reload some things */
3661 ixgbe_configure(adapter);
3662
3663 return ixgbe_up_complete(adapter);
3664 }
3665
3666 void ixgbe_reset(struct ixgbe_adapter *adapter)
3667 {
3668 struct ixgbe_hw *hw = &adapter->hw;
3669 int err;
3670
3671 err = hw->mac.ops.init_hw(hw);
3672 switch (err) {
3673 case 0:
3674 case IXGBE_ERR_SFP_NOT_PRESENT:
3675 break;
3676 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3677 e_dev_err("master disable timed out\n");
3678 break;
3679 case IXGBE_ERR_EEPROM_VERSION:
3680 /* We are running on a pre-production device, log a warning */
3681 e_dev_warn("This device is a pre-production adapter/LOM. "
3682 "Please be aware there may be issuesassociated with "
3683 "your hardware. If you are experiencing problems "
3684 "please contact your Intel or hardware "
3685 "representative who provided you with this "
3686 "hardware.\n");
3687 break;
3688 default:
3689 e_dev_err("Hardware Error: %d\n", err);
3690 }
3691
3692 /* reprogram the RAR[0] in case user changed it. */
3693 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3694 IXGBE_RAH_AV);
3695 }
3696
3697 /**
3698 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3699 * @rx_ring: ring to free buffers from
3700 **/
3701 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3702 {
3703 struct device *dev = rx_ring->dev;
3704 unsigned long size;
3705 u16 i;
3706
3707 /* ring already cleared, nothing to do */
3708 if (!rx_ring->rx_buffer_info)
3709 return;
3710
3711 /* Free all the Rx ring sk_buffs */
3712 for (i = 0; i < rx_ring->count; i++) {
3713 struct ixgbe_rx_buffer *rx_buffer_info;
3714
3715 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3716 if (rx_buffer_info->dma) {
3717 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3718 rx_ring->rx_buf_len,
3719 DMA_FROM_DEVICE);
3720 rx_buffer_info->dma = 0;
3721 }
3722 if (rx_buffer_info->skb) {
3723 struct sk_buff *skb = rx_buffer_info->skb;
3724 rx_buffer_info->skb = NULL;
3725 do {
3726 struct sk_buff *this = skb;
3727 if (IXGBE_RSC_CB(this)->delay_unmap) {
3728 dma_unmap_single(dev,
3729 IXGBE_RSC_CB(this)->dma,
3730 rx_ring->rx_buf_len,
3731 DMA_FROM_DEVICE);
3732 IXGBE_RSC_CB(this)->dma = 0;
3733 IXGBE_RSC_CB(skb)->delay_unmap = false;
3734 }
3735 skb = skb->prev;
3736 dev_kfree_skb(this);
3737 } while (skb);
3738 }
3739 if (!rx_buffer_info->page)
3740 continue;
3741 if (rx_buffer_info->page_dma) {
3742 dma_unmap_page(dev, rx_buffer_info->page_dma,
3743 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3744 rx_buffer_info->page_dma = 0;
3745 }
3746 put_page(rx_buffer_info->page);
3747 rx_buffer_info->page = NULL;
3748 rx_buffer_info->page_offset = 0;
3749 }
3750
3751 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3752 memset(rx_ring->rx_buffer_info, 0, size);
3753
3754 /* Zero out the descriptor ring */
3755 memset(rx_ring->desc, 0, rx_ring->size);
3756
3757 rx_ring->next_to_clean = 0;
3758 rx_ring->next_to_use = 0;
3759 }
3760
3761 /**
3762 * ixgbe_clean_tx_ring - Free Tx Buffers
3763 * @tx_ring: ring to be cleaned
3764 **/
3765 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3766 {
3767 struct ixgbe_tx_buffer *tx_buffer_info;
3768 unsigned long size;
3769 u16 i;
3770
3771 /* ring already cleared, nothing to do */
3772 if (!tx_ring->tx_buffer_info)
3773 return;
3774
3775 /* Free all the Tx ring sk_buffs */
3776 for (i = 0; i < tx_ring->count; i++) {
3777 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3778 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3779 }
3780
3781 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3782 memset(tx_ring->tx_buffer_info, 0, size);
3783
3784 /* Zero out the descriptor ring */
3785 memset(tx_ring->desc, 0, tx_ring->size);
3786
3787 tx_ring->next_to_use = 0;
3788 tx_ring->next_to_clean = 0;
3789 }
3790
3791 /**
3792 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3793 * @adapter: board private structure
3794 **/
3795 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3796 {
3797 int i;
3798
3799 for (i = 0; i < adapter->num_rx_queues; i++)
3800 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3801 }
3802
3803 /**
3804 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3805 * @adapter: board private structure
3806 **/
3807 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3808 {
3809 int i;
3810
3811 for (i = 0; i < adapter->num_tx_queues; i++)
3812 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3813 }
3814
3815 void ixgbe_down(struct ixgbe_adapter *adapter)
3816 {
3817 struct net_device *netdev = adapter->netdev;
3818 struct ixgbe_hw *hw = &adapter->hw;
3819 u32 rxctrl;
3820 u32 txdctl;
3821 int i, j;
3822 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3823
3824 /* signal that we are down to the interrupt handler */
3825 set_bit(__IXGBE_DOWN, &adapter->state);
3826
3827 /* disable receive for all VFs and wait one second */
3828 if (adapter->num_vfs) {
3829 /* ping all the active vfs to let them know we are going down */
3830 ixgbe_ping_all_vfs(adapter);
3831
3832 /* Disable all VFTE/VFRE TX/RX */
3833 ixgbe_disable_tx_rx(adapter);
3834
3835 /* Mark all the VFs as inactive */
3836 for (i = 0 ; i < adapter->num_vfs; i++)
3837 adapter->vfinfo[i].clear_to_send = 0;
3838 }
3839
3840 /* disable receives */
3841 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3842 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3843
3844 IXGBE_WRITE_FLUSH(hw);
3845 msleep(10);
3846
3847 netif_tx_stop_all_queues(netdev);
3848
3849 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3850 del_timer_sync(&adapter->sfp_timer);
3851 del_timer_sync(&adapter->watchdog_timer);
3852 cancel_work_sync(&adapter->watchdog_task);
3853
3854 netif_carrier_off(netdev);
3855 netif_tx_disable(netdev);
3856
3857 ixgbe_irq_disable(adapter);
3858
3859 ixgbe_napi_disable_all(adapter);
3860
3861 /* Cleanup the affinity_hint CPU mask memory and callback */
3862 for (i = 0; i < num_q_vectors; i++) {
3863 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3864 /* clear the affinity_mask in the IRQ descriptor */
3865 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3866 /* release the CPU mask memory */
3867 free_cpumask_var(q_vector->affinity_mask);
3868 }
3869
3870 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3871 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3872 cancel_work_sync(&adapter->fdir_reinit_task);
3873
3874 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3875 cancel_work_sync(&adapter->check_overtemp_task);
3876
3877 /* disable transmits in the hardware now that interrupts are off */
3878 for (i = 0; i < adapter->num_tx_queues; i++) {
3879 j = adapter->tx_ring[i]->reg_idx;
3880 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3881 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3882 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3883 }
3884 /* Disable the Tx DMA engine on 82599 */
3885 if (hw->mac.type == ixgbe_mac_82599EB)
3886 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3887 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3888 ~IXGBE_DMATXCTL_TE));
3889
3890 /* power down the optics */
3891 if (hw->phy.multispeed_fiber)
3892 hw->mac.ops.disable_tx_laser(hw);
3893
3894 /* clear n-tuple filters that are cached */
3895 ethtool_ntuple_flush(netdev);
3896
3897 if (!pci_channel_offline(adapter->pdev))
3898 ixgbe_reset(adapter);
3899 ixgbe_clean_all_tx_rings(adapter);
3900 ixgbe_clean_all_rx_rings(adapter);
3901
3902 #ifdef CONFIG_IXGBE_DCA
3903 /* since we reset the hardware DCA settings were cleared */
3904 ixgbe_setup_dca(adapter);
3905 #endif
3906 }
3907
3908 /**
3909 * ixgbe_poll - NAPI Rx polling callback
3910 * @napi: structure for representing this polling device
3911 * @budget: how many packets driver is allowed to clean
3912 *
3913 * This function is used for legacy and MSI, NAPI mode
3914 **/
3915 static int ixgbe_poll(struct napi_struct *napi, int budget)
3916 {
3917 struct ixgbe_q_vector *q_vector =
3918 container_of(napi, struct ixgbe_q_vector, napi);
3919 struct ixgbe_adapter *adapter = q_vector->adapter;
3920 int tx_clean_complete, work_done = 0;
3921
3922 #ifdef CONFIG_IXGBE_DCA
3923 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3924 ixgbe_update_dca(q_vector);
3925 #endif
3926
3927 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3928 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3929
3930 if (!tx_clean_complete)
3931 work_done = budget;
3932
3933 /* If budget not fully consumed, exit the polling mode */
3934 if (work_done < budget) {
3935 napi_complete(napi);
3936 if (adapter->rx_itr_setting & 1)
3937 ixgbe_set_itr(adapter);
3938 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3939 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3940 }
3941 return work_done;
3942 }
3943
3944 /**
3945 * ixgbe_tx_timeout - Respond to a Tx Hang
3946 * @netdev: network interface device structure
3947 **/
3948 static void ixgbe_tx_timeout(struct net_device *netdev)
3949 {
3950 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3951
3952 /* Do the reset outside of interrupt context */
3953 schedule_work(&adapter->reset_task);
3954 }
3955
3956 static void ixgbe_reset_task(struct work_struct *work)
3957 {
3958 struct ixgbe_adapter *adapter;
3959 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3960
3961 /* If we're already down or resetting, just bail */
3962 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3963 test_bit(__IXGBE_RESETTING, &adapter->state))
3964 return;
3965
3966 adapter->tx_timeout_count++;
3967
3968 ixgbe_dump(adapter);
3969 netdev_err(adapter->netdev, "Reset adapter\n");
3970 ixgbe_reinit_locked(adapter);
3971 }
3972
3973 #ifdef CONFIG_IXGBE_DCB
3974 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3975 {
3976 bool ret = false;
3977 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3978
3979 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3980 return ret;
3981
3982 f->mask = 0x7 << 3;
3983 adapter->num_rx_queues = f->indices;
3984 adapter->num_tx_queues = f->indices;
3985 ret = true;
3986
3987 return ret;
3988 }
3989 #endif
3990
3991 /**
3992 * ixgbe_set_rss_queues: Allocate queues for RSS
3993 * @adapter: board private structure to initialize
3994 *
3995 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3996 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3997 *
3998 **/
3999 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4000 {
4001 bool ret = false;
4002 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4003
4004 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4005 f->mask = 0xF;
4006 adapter->num_rx_queues = f->indices;
4007 adapter->num_tx_queues = f->indices;
4008 ret = true;
4009 } else {
4010 ret = false;
4011 }
4012
4013 return ret;
4014 }
4015
4016 /**
4017 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4018 * @adapter: board private structure to initialize
4019 *
4020 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4021 * to the original CPU that initiated the Tx session. This runs in addition
4022 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4023 * Rx load across CPUs using RSS.
4024 *
4025 **/
4026 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4027 {
4028 bool ret = false;
4029 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4030
4031 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4032 f_fdir->mask = 0;
4033
4034 /* Flow Director must have RSS enabled */
4035 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4036 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4037 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4038 adapter->num_tx_queues = f_fdir->indices;
4039 adapter->num_rx_queues = f_fdir->indices;
4040 ret = true;
4041 } else {
4042 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4043 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4044 }
4045 return ret;
4046 }
4047
4048 #ifdef IXGBE_FCOE
4049 /**
4050 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4051 * @adapter: board private structure to initialize
4052 *
4053 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4054 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4055 * rx queues out of the max number of rx queues, instead, it is used as the
4056 * index of the first rx queue used by FCoE.
4057 *
4058 **/
4059 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4060 {
4061 bool ret = false;
4062 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4063
4064 f->indices = min((int)num_online_cpus(), f->indices);
4065 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4066 adapter->num_rx_queues = 1;
4067 adapter->num_tx_queues = 1;
4068 #ifdef CONFIG_IXGBE_DCB
4069 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4070 e_info(probe, "FCoE enabled with DCB\n");
4071 ixgbe_set_dcb_queues(adapter);
4072 }
4073 #endif
4074 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4075 e_info(probe, "FCoE enabled with RSS\n");
4076 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4077 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4078 ixgbe_set_fdir_queues(adapter);
4079 else
4080 ixgbe_set_rss_queues(adapter);
4081 }
4082 /* adding FCoE rx rings to the end */
4083 f->mask = adapter->num_rx_queues;
4084 adapter->num_rx_queues += f->indices;
4085 adapter->num_tx_queues += f->indices;
4086
4087 ret = true;
4088 }
4089
4090 return ret;
4091 }
4092
4093 #endif /* IXGBE_FCOE */
4094 /**
4095 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4096 * @adapter: board private structure to initialize
4097 *
4098 * IOV doesn't actually use anything, so just NAK the
4099 * request for now and let the other queue routines
4100 * figure out what to do.
4101 */
4102 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4103 {
4104 return false;
4105 }
4106
4107 /*
4108 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4109 * @adapter: board private structure to initialize
4110 *
4111 * This is the top level queue allocation routine. The order here is very
4112 * important, starting with the "most" number of features turned on at once,
4113 * and ending with the smallest set of features. This way large combinations
4114 * can be allocated if they're turned on, and smaller combinations are the
4115 * fallthrough conditions.
4116 *
4117 **/
4118 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4119 {
4120 /* Start with base case */
4121 adapter->num_rx_queues = 1;
4122 adapter->num_tx_queues = 1;
4123 adapter->num_rx_pools = adapter->num_rx_queues;
4124 adapter->num_rx_queues_per_pool = 1;
4125
4126 if (ixgbe_set_sriov_queues(adapter))
4127 goto done;
4128
4129 #ifdef IXGBE_FCOE
4130 if (ixgbe_set_fcoe_queues(adapter))
4131 goto done;
4132
4133 #endif /* IXGBE_FCOE */
4134 #ifdef CONFIG_IXGBE_DCB
4135 if (ixgbe_set_dcb_queues(adapter))
4136 goto done;
4137
4138 #endif
4139 if (ixgbe_set_fdir_queues(adapter))
4140 goto done;
4141
4142 if (ixgbe_set_rss_queues(adapter))
4143 goto done;
4144
4145 /* fallback to base case */
4146 adapter->num_rx_queues = 1;
4147 adapter->num_tx_queues = 1;
4148
4149 done:
4150 /* Notify the stack of the (possibly) reduced queue counts. */
4151 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4152 return netif_set_real_num_rx_queues(adapter->netdev,
4153 adapter->num_rx_queues);
4154 }
4155
4156 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4157 int vectors)
4158 {
4159 int err, vector_threshold;
4160
4161 /* We'll want at least 3 (vector_threshold):
4162 * 1) TxQ[0] Cleanup
4163 * 2) RxQ[0] Cleanup
4164 * 3) Other (Link Status Change, etc.)
4165 * 4) TCP Timer (optional)
4166 */
4167 vector_threshold = MIN_MSIX_COUNT;
4168
4169 /* The more we get, the more we will assign to Tx/Rx Cleanup
4170 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4171 * Right now, we simply care about how many we'll get; we'll
4172 * set them up later while requesting irq's.
4173 */
4174 while (vectors >= vector_threshold) {
4175 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4176 vectors);
4177 if (!err) /* Success in acquiring all requested vectors. */
4178 break;
4179 else if (err < 0)
4180 vectors = 0; /* Nasty failure, quit now */
4181 else /* err == number of vectors we should try again with */
4182 vectors = err;
4183 }
4184
4185 if (vectors < vector_threshold) {
4186 /* Can't allocate enough MSI-X interrupts? Oh well.
4187 * This just means we'll go with either a single MSI
4188 * vector or fall back to legacy interrupts.
4189 */
4190 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4191 "Unable to allocate MSI-X interrupts\n");
4192 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4193 kfree(adapter->msix_entries);
4194 adapter->msix_entries = NULL;
4195 } else {
4196 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4197 /*
4198 * Adjust for only the vectors we'll use, which is minimum
4199 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4200 * vectors we were allocated.
4201 */
4202 adapter->num_msix_vectors = min(vectors,
4203 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4204 }
4205 }
4206
4207 /**
4208 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4209 * @adapter: board private structure to initialize
4210 *
4211 * Cache the descriptor ring offsets for RSS to the assigned rings.
4212 *
4213 **/
4214 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4215 {
4216 int i;
4217 bool ret = false;
4218
4219 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4220 for (i = 0; i < adapter->num_rx_queues; i++)
4221 adapter->rx_ring[i]->reg_idx = i;
4222 for (i = 0; i < adapter->num_tx_queues; i++)
4223 adapter->tx_ring[i]->reg_idx = i;
4224 ret = true;
4225 } else {
4226 ret = false;
4227 }
4228
4229 return ret;
4230 }
4231
4232 #ifdef CONFIG_IXGBE_DCB
4233 /**
4234 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4235 * @adapter: board private structure to initialize
4236 *
4237 * Cache the descriptor ring offsets for DCB to the assigned rings.
4238 *
4239 **/
4240 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4241 {
4242 int i;
4243 bool ret = false;
4244 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4245
4246 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4247 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4248 /* the number of queues is assumed to be symmetric */
4249 for (i = 0; i < dcb_i; i++) {
4250 adapter->rx_ring[i]->reg_idx = i << 3;
4251 adapter->tx_ring[i]->reg_idx = i << 2;
4252 }
4253 ret = true;
4254 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4255 if (dcb_i == 8) {
4256 /*
4257 * Tx TC0 starts at: descriptor queue 0
4258 * Tx TC1 starts at: descriptor queue 32
4259 * Tx TC2 starts at: descriptor queue 64
4260 * Tx TC3 starts at: descriptor queue 80
4261 * Tx TC4 starts at: descriptor queue 96
4262 * Tx TC5 starts at: descriptor queue 104
4263 * Tx TC6 starts at: descriptor queue 112
4264 * Tx TC7 starts at: descriptor queue 120
4265 *
4266 * Rx TC0-TC7 are offset by 16 queues each
4267 */
4268 for (i = 0; i < 3; i++) {
4269 adapter->tx_ring[i]->reg_idx = i << 5;
4270 adapter->rx_ring[i]->reg_idx = i << 4;
4271 }
4272 for ( ; i < 5; i++) {
4273 adapter->tx_ring[i]->reg_idx =
4274 ((i + 2) << 4);
4275 adapter->rx_ring[i]->reg_idx = i << 4;
4276 }
4277 for ( ; i < dcb_i; i++) {
4278 adapter->tx_ring[i]->reg_idx =
4279 ((i + 8) << 3);
4280 adapter->rx_ring[i]->reg_idx = i << 4;
4281 }
4282
4283 ret = true;
4284 } else if (dcb_i == 4) {
4285 /*
4286 * Tx TC0 starts at: descriptor queue 0
4287 * Tx TC1 starts at: descriptor queue 64
4288 * Tx TC2 starts at: descriptor queue 96
4289 * Tx TC3 starts at: descriptor queue 112
4290 *
4291 * Rx TC0-TC3 are offset by 32 queues each
4292 */
4293 adapter->tx_ring[0]->reg_idx = 0;
4294 adapter->tx_ring[1]->reg_idx = 64;
4295 adapter->tx_ring[2]->reg_idx = 96;
4296 adapter->tx_ring[3]->reg_idx = 112;
4297 for (i = 0 ; i < dcb_i; i++)
4298 adapter->rx_ring[i]->reg_idx = i << 5;
4299
4300 ret = true;
4301 } else {
4302 ret = false;
4303 }
4304 } else {
4305 ret = false;
4306 }
4307 } else {
4308 ret = false;
4309 }
4310
4311 return ret;
4312 }
4313 #endif
4314
4315 /**
4316 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4317 * @adapter: board private structure to initialize
4318 *
4319 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4320 *
4321 **/
4322 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4323 {
4324 int i;
4325 bool ret = false;
4326
4327 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4328 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4329 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4330 for (i = 0; i < adapter->num_rx_queues; i++)
4331 adapter->rx_ring[i]->reg_idx = i;
4332 for (i = 0; i < adapter->num_tx_queues; i++)
4333 adapter->tx_ring[i]->reg_idx = i;
4334 ret = true;
4335 }
4336
4337 return ret;
4338 }
4339
4340 #ifdef IXGBE_FCOE
4341 /**
4342 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4343 * @adapter: board private structure to initialize
4344 *
4345 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4346 *
4347 */
4348 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4349 {
4350 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4351 bool ret = false;
4352 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4353
4354 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4355 #ifdef CONFIG_IXGBE_DCB
4356 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4357 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4358
4359 ixgbe_cache_ring_dcb(adapter);
4360 /* find out queues in TC for FCoE */
4361 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4362 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4363 /*
4364 * In 82599, the number of Tx queues for each traffic
4365 * class for both 8-TC and 4-TC modes are:
4366 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4367 * 8 TCs: 32 32 16 16 8 8 8 8
4368 * 4 TCs: 64 64 32 32
4369 * We have max 8 queues for FCoE, where 8 the is
4370 * FCoE redirection table size. If TC for FCoE is
4371 * less than or equal to TC3, we have enough queues
4372 * to add max of 8 queues for FCoE, so we start FCoE
4373 * tx descriptor from the next one, i.e., reg_idx + 1.
4374 * If TC for FCoE is above TC3, implying 8 TC mode,
4375 * and we need 8 for FCoE, we have to take all queues
4376 * in that traffic class for FCoE.
4377 */
4378 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4379 fcoe_tx_i--;
4380 }
4381 #endif /* CONFIG_IXGBE_DCB */
4382 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4383 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4384 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4385 ixgbe_cache_ring_fdir(adapter);
4386 else
4387 ixgbe_cache_ring_rss(adapter);
4388
4389 fcoe_rx_i = f->mask;
4390 fcoe_tx_i = f->mask;
4391 }
4392 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4393 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4394 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4395 }
4396 ret = true;
4397 }
4398 return ret;
4399 }
4400
4401 #endif /* IXGBE_FCOE */
4402 /**
4403 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4404 * @adapter: board private structure to initialize
4405 *
4406 * SR-IOV doesn't use any descriptor rings but changes the default if
4407 * no other mapping is used.
4408 *
4409 */
4410 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4411 {
4412 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4413 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4414 if (adapter->num_vfs)
4415 return true;
4416 else
4417 return false;
4418 }
4419
4420 /**
4421 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4422 * @adapter: board private structure to initialize
4423 *
4424 * Once we know the feature-set enabled for the device, we'll cache
4425 * the register offset the descriptor ring is assigned to.
4426 *
4427 * Note, the order the various feature calls is important. It must start with
4428 * the "most" features enabled at the same time, then trickle down to the
4429 * least amount of features turned on at once.
4430 **/
4431 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4432 {
4433 /* start with default case */
4434 adapter->rx_ring[0]->reg_idx = 0;
4435 adapter->tx_ring[0]->reg_idx = 0;
4436
4437 if (ixgbe_cache_ring_sriov(adapter))
4438 return;
4439
4440 #ifdef IXGBE_FCOE
4441 if (ixgbe_cache_ring_fcoe(adapter))
4442 return;
4443
4444 #endif /* IXGBE_FCOE */
4445 #ifdef CONFIG_IXGBE_DCB
4446 if (ixgbe_cache_ring_dcb(adapter))
4447 return;
4448
4449 #endif
4450 if (ixgbe_cache_ring_fdir(adapter))
4451 return;
4452
4453 if (ixgbe_cache_ring_rss(adapter))
4454 return;
4455 }
4456
4457 /**
4458 * ixgbe_alloc_queues - Allocate memory for all rings
4459 * @adapter: board private structure to initialize
4460 *
4461 * We allocate one ring per queue at run-time since we don't know the
4462 * number of queues at compile-time. The polling_netdev array is
4463 * intended for Multiqueue, but should work fine with a single queue.
4464 **/
4465 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4466 {
4467 int i;
4468 int rx_count;
4469 int orig_node = adapter->node;
4470
4471 for (i = 0; i < adapter->num_tx_queues; i++) {
4472 struct ixgbe_ring *ring = adapter->tx_ring[i];
4473 if (orig_node == -1) {
4474 int cur_node = next_online_node(adapter->node);
4475 if (cur_node == MAX_NUMNODES)
4476 cur_node = first_online_node;
4477 adapter->node = cur_node;
4478 }
4479 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4480 adapter->node);
4481 if (!ring)
4482 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4483 if (!ring)
4484 goto err_tx_ring_allocation;
4485 ring->count = adapter->tx_ring_count;
4486 ring->queue_index = i;
4487 ring->dev = &adapter->pdev->dev;
4488 ring->netdev = adapter->netdev;
4489 ring->numa_node = adapter->node;
4490
4491 adapter->tx_ring[i] = ring;
4492 }
4493
4494 /* Restore the adapter's original node */
4495 adapter->node = orig_node;
4496
4497 rx_count = adapter->rx_ring_count;
4498 for (i = 0; i < adapter->num_rx_queues; i++) {
4499 struct ixgbe_ring *ring = adapter->rx_ring[i];
4500 if (orig_node == -1) {
4501 int cur_node = next_online_node(adapter->node);
4502 if (cur_node == MAX_NUMNODES)
4503 cur_node = first_online_node;
4504 adapter->node = cur_node;
4505 }
4506 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4507 adapter->node);
4508 if (!ring)
4509 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4510 if (!ring)
4511 goto err_rx_ring_allocation;
4512 ring->count = rx_count;
4513 ring->queue_index = i;
4514 ring->dev = &adapter->pdev->dev;
4515 ring->netdev = adapter->netdev;
4516 ring->numa_node = adapter->node;
4517
4518 adapter->rx_ring[i] = ring;
4519 }
4520
4521 /* Restore the adapter's original node */
4522 adapter->node = orig_node;
4523
4524 ixgbe_cache_ring_register(adapter);
4525
4526 return 0;
4527
4528 err_rx_ring_allocation:
4529 for (i = 0; i < adapter->num_tx_queues; i++)
4530 kfree(adapter->tx_ring[i]);
4531 err_tx_ring_allocation:
4532 return -ENOMEM;
4533 }
4534
4535 /**
4536 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4537 * @adapter: board private structure to initialize
4538 *
4539 * Attempt to configure the interrupts using the best available
4540 * capabilities of the hardware and the kernel.
4541 **/
4542 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4543 {
4544 struct ixgbe_hw *hw = &adapter->hw;
4545 int err = 0;
4546 int vector, v_budget;
4547
4548 /*
4549 * It's easy to be greedy for MSI-X vectors, but it really
4550 * doesn't do us much good if we have a lot more vectors
4551 * than CPU's. So let's be conservative and only ask for
4552 * (roughly) the same number of vectors as there are CPU's.
4553 */
4554 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4555 (int)num_online_cpus()) + NON_Q_VECTORS;
4556
4557 /*
4558 * At the same time, hardware can only support a maximum of
4559 * hw.mac->max_msix_vectors vectors. With features
4560 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4561 * descriptor queues supported by our device. Thus, we cap it off in
4562 * those rare cases where the cpu count also exceeds our vector limit.
4563 */
4564 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4565
4566 /* A failure in MSI-X entry allocation isn't fatal, but it does
4567 * mean we disable MSI-X capabilities of the adapter. */
4568 adapter->msix_entries = kcalloc(v_budget,
4569 sizeof(struct msix_entry), GFP_KERNEL);
4570 if (adapter->msix_entries) {
4571 for (vector = 0; vector < v_budget; vector++)
4572 adapter->msix_entries[vector].entry = vector;
4573
4574 ixgbe_acquire_msix_vectors(adapter, v_budget);
4575
4576 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4577 goto out;
4578 }
4579
4580 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4581 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4582 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4583 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4584 adapter->atr_sample_rate = 0;
4585 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4586 ixgbe_disable_sriov(adapter);
4587
4588 err = ixgbe_set_num_queues(adapter);
4589 if (err)
4590 return err;
4591
4592 err = pci_enable_msi(adapter->pdev);
4593 if (!err) {
4594 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4595 } else {
4596 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4597 "Unable to allocate MSI interrupt, "
4598 "falling back to legacy. Error: %d\n", err);
4599 /* reset err */
4600 err = 0;
4601 }
4602
4603 out:
4604 return err;
4605 }
4606
4607 /**
4608 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4609 * @adapter: board private structure to initialize
4610 *
4611 * We allocate one q_vector per queue interrupt. If allocation fails we
4612 * return -ENOMEM.
4613 **/
4614 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4615 {
4616 int q_idx, num_q_vectors;
4617 struct ixgbe_q_vector *q_vector;
4618 int napi_vectors;
4619 int (*poll)(struct napi_struct *, int);
4620
4621 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4622 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4623 napi_vectors = adapter->num_rx_queues;
4624 poll = &ixgbe_clean_rxtx_many;
4625 } else {
4626 num_q_vectors = 1;
4627 napi_vectors = 1;
4628 poll = &ixgbe_poll;
4629 }
4630
4631 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4632 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4633 GFP_KERNEL, adapter->node);
4634 if (!q_vector)
4635 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4636 GFP_KERNEL);
4637 if (!q_vector)
4638 goto err_out;
4639 q_vector->adapter = adapter;
4640 if (q_vector->txr_count && !q_vector->rxr_count)
4641 q_vector->eitr = adapter->tx_eitr_param;
4642 else
4643 q_vector->eitr = adapter->rx_eitr_param;
4644 q_vector->v_idx = q_idx;
4645 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4646 adapter->q_vector[q_idx] = q_vector;
4647 }
4648
4649 return 0;
4650
4651 err_out:
4652 while (q_idx) {
4653 q_idx--;
4654 q_vector = adapter->q_vector[q_idx];
4655 netif_napi_del(&q_vector->napi);
4656 kfree(q_vector);
4657 adapter->q_vector[q_idx] = NULL;
4658 }
4659 return -ENOMEM;
4660 }
4661
4662 /**
4663 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4664 * @adapter: board private structure to initialize
4665 *
4666 * This function frees the memory allocated to the q_vectors. In addition if
4667 * NAPI is enabled it will delete any references to the NAPI struct prior
4668 * to freeing the q_vector.
4669 **/
4670 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4671 {
4672 int q_idx, num_q_vectors;
4673
4674 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4675 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4676 else
4677 num_q_vectors = 1;
4678
4679 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4680 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4681 adapter->q_vector[q_idx] = NULL;
4682 netif_napi_del(&q_vector->napi);
4683 kfree(q_vector);
4684 }
4685 }
4686
4687 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4688 {
4689 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4690 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4691 pci_disable_msix(adapter->pdev);
4692 kfree(adapter->msix_entries);
4693 adapter->msix_entries = NULL;
4694 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4695 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4696 pci_disable_msi(adapter->pdev);
4697 }
4698 }
4699
4700 /**
4701 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4702 * @adapter: board private structure to initialize
4703 *
4704 * We determine which interrupt scheme to use based on...
4705 * - Kernel support (MSI, MSI-X)
4706 * - which can be user-defined (via MODULE_PARAM)
4707 * - Hardware queue count (num_*_queues)
4708 * - defined by miscellaneous hardware support/features (RSS, etc.)
4709 **/
4710 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4711 {
4712 int err;
4713
4714 /* Number of supported queues */
4715 err = ixgbe_set_num_queues(adapter);
4716 if (err)
4717 return err;
4718
4719 err = ixgbe_set_interrupt_capability(adapter);
4720 if (err) {
4721 e_dev_err("Unable to setup interrupt capabilities\n");
4722 goto err_set_interrupt;
4723 }
4724
4725 err = ixgbe_alloc_q_vectors(adapter);
4726 if (err) {
4727 e_dev_err("Unable to allocate memory for queue vectors\n");
4728 goto err_alloc_q_vectors;
4729 }
4730
4731 err = ixgbe_alloc_queues(adapter);
4732 if (err) {
4733 e_dev_err("Unable to allocate memory for queues\n");
4734 goto err_alloc_queues;
4735 }
4736
4737 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4738 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4739 adapter->num_rx_queues, adapter->num_tx_queues);
4740
4741 set_bit(__IXGBE_DOWN, &adapter->state);
4742
4743 return 0;
4744
4745 err_alloc_queues:
4746 ixgbe_free_q_vectors(adapter);
4747 err_alloc_q_vectors:
4748 ixgbe_reset_interrupt_capability(adapter);
4749 err_set_interrupt:
4750 return err;
4751 }
4752
4753 static void ring_free_rcu(struct rcu_head *head)
4754 {
4755 kfree(container_of(head, struct ixgbe_ring, rcu));
4756 }
4757
4758 /**
4759 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4760 * @adapter: board private structure to clear interrupt scheme on
4761 *
4762 * We go through and clear interrupt specific resources and reset the structure
4763 * to pre-load conditions
4764 **/
4765 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4766 {
4767 int i;
4768
4769 for (i = 0; i < adapter->num_tx_queues; i++) {
4770 kfree(adapter->tx_ring[i]);
4771 adapter->tx_ring[i] = NULL;
4772 }
4773 for (i = 0; i < adapter->num_rx_queues; i++) {
4774 struct ixgbe_ring *ring = adapter->rx_ring[i];
4775
4776 /* ixgbe_get_stats64() might access this ring, we must wait
4777 * a grace period before freeing it.
4778 */
4779 call_rcu(&ring->rcu, ring_free_rcu);
4780 adapter->rx_ring[i] = NULL;
4781 }
4782
4783 ixgbe_free_q_vectors(adapter);
4784 ixgbe_reset_interrupt_capability(adapter);
4785 }
4786
4787 /**
4788 * ixgbe_sfp_timer - worker thread to find a missing module
4789 * @data: pointer to our adapter struct
4790 **/
4791 static void ixgbe_sfp_timer(unsigned long data)
4792 {
4793 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4794
4795 /*
4796 * Do the sfp_timer outside of interrupt context due to the
4797 * delays that sfp+ detection requires
4798 */
4799 schedule_work(&adapter->sfp_task);
4800 }
4801
4802 /**
4803 * ixgbe_sfp_task - worker thread to find a missing module
4804 * @work: pointer to work_struct containing our data
4805 **/
4806 static void ixgbe_sfp_task(struct work_struct *work)
4807 {
4808 struct ixgbe_adapter *adapter = container_of(work,
4809 struct ixgbe_adapter,
4810 sfp_task);
4811 struct ixgbe_hw *hw = &adapter->hw;
4812
4813 if ((hw->phy.type == ixgbe_phy_nl) &&
4814 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4815 s32 ret = hw->phy.ops.identify_sfp(hw);
4816 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4817 goto reschedule;
4818 ret = hw->phy.ops.reset(hw);
4819 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4820 e_dev_err("failed to initialize because an unsupported "
4821 "SFP+ module type was detected.\n");
4822 e_dev_err("Reload the driver after installing a "
4823 "supported module.\n");
4824 unregister_netdev(adapter->netdev);
4825 } else {
4826 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4827 }
4828 /* don't need this routine any more */
4829 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4830 }
4831 return;
4832 reschedule:
4833 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4834 mod_timer(&adapter->sfp_timer,
4835 round_jiffies(jiffies + (2 * HZ)));
4836 }
4837
4838 /**
4839 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4840 * @adapter: board private structure to initialize
4841 *
4842 * ixgbe_sw_init initializes the Adapter private data structure.
4843 * Fields are initialized based on PCI device information and
4844 * OS network device settings (MTU size).
4845 **/
4846 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4847 {
4848 struct ixgbe_hw *hw = &adapter->hw;
4849 struct pci_dev *pdev = adapter->pdev;
4850 struct net_device *dev = adapter->netdev;
4851 unsigned int rss;
4852 #ifdef CONFIG_IXGBE_DCB
4853 int j;
4854 struct tc_configuration *tc;
4855 #endif
4856 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4857
4858 /* PCI config space info */
4859
4860 hw->vendor_id = pdev->vendor;
4861 hw->device_id = pdev->device;
4862 hw->revision_id = pdev->revision;
4863 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4864 hw->subsystem_device_id = pdev->subsystem_device;
4865
4866 /* Set capability flags */
4867 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4868 adapter->ring_feature[RING_F_RSS].indices = rss;
4869 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4870 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4871 if (hw->mac.type == ixgbe_mac_82598EB) {
4872 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4873 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4874 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4875 } else if (hw->mac.type == ixgbe_mac_82599EB) {
4876 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4877 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4878 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4879 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4880 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4881 if (dev->features & NETIF_F_NTUPLE) {
4882 /* Flow Director perfect filter enabled */
4883 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4884 adapter->atr_sample_rate = 0;
4885 spin_lock_init(&adapter->fdir_perfect_lock);
4886 } else {
4887 /* Flow Director hash filters enabled */
4888 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4889 adapter->atr_sample_rate = 20;
4890 }
4891 adapter->ring_feature[RING_F_FDIR].indices =
4892 IXGBE_MAX_FDIR_INDICES;
4893 adapter->fdir_pballoc = 0;
4894 #ifdef IXGBE_FCOE
4895 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4896 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4897 adapter->ring_feature[RING_F_FCOE].indices = 0;
4898 #ifdef CONFIG_IXGBE_DCB
4899 /* Default traffic class to use for FCoE */
4900 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4901 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4902 #endif
4903 #endif /* IXGBE_FCOE */
4904 }
4905
4906 #ifdef CONFIG_IXGBE_DCB
4907 /* Configure DCB traffic classes */
4908 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4909 tc = &adapter->dcb_cfg.tc_config[j];
4910 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4911 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4912 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4913 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4914 tc->dcb_pfc = pfc_disabled;
4915 }
4916 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4917 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4918 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4919 adapter->dcb_cfg.pfc_mode_enable = false;
4920 adapter->dcb_cfg.round_robin_enable = false;
4921 adapter->dcb_set_bitmap = 0x00;
4922 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4923 adapter->ring_feature[RING_F_DCB].indices);
4924
4925 #endif
4926
4927 /* default flow control settings */
4928 hw->fc.requested_mode = ixgbe_fc_full;
4929 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4930 #ifdef CONFIG_DCB
4931 adapter->last_lfc_mode = hw->fc.current_mode;
4932 #endif
4933 hw->fc.high_water = FC_HIGH_WATER(max_frame);
4934 hw->fc.low_water = FC_LOW_WATER(max_frame);
4935 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4936 hw->fc.send_xon = true;
4937 hw->fc.disable_fc_autoneg = false;
4938
4939 /* enable itr by default in dynamic mode */
4940 adapter->rx_itr_setting = 1;
4941 adapter->rx_eitr_param = 20000;
4942 adapter->tx_itr_setting = 1;
4943 adapter->tx_eitr_param = 10000;
4944
4945 /* set defaults for eitr in MegaBytes */
4946 adapter->eitr_low = 10;
4947 adapter->eitr_high = 20;
4948
4949 /* set default ring sizes */
4950 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4951 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4952
4953 /* initialize eeprom parameters */
4954 if (ixgbe_init_eeprom_params_generic(hw)) {
4955 e_dev_err("EEPROM initialization failed\n");
4956 return -EIO;
4957 }
4958
4959 /* enable rx csum by default */
4960 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4961
4962 /* get assigned NUMA node */
4963 adapter->node = dev_to_node(&pdev->dev);
4964
4965 set_bit(__IXGBE_DOWN, &adapter->state);
4966
4967 return 0;
4968 }
4969
4970 /**
4971 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4972 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4973 *
4974 * Return 0 on success, negative on failure
4975 **/
4976 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4977 {
4978 struct device *dev = tx_ring->dev;
4979 int size;
4980
4981 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4982 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4983 if (!tx_ring->tx_buffer_info)
4984 tx_ring->tx_buffer_info = vmalloc(size);
4985 if (!tx_ring->tx_buffer_info)
4986 goto err;
4987 memset(tx_ring->tx_buffer_info, 0, size);
4988
4989 /* round up to nearest 4K */
4990 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4991 tx_ring->size = ALIGN(tx_ring->size, 4096);
4992
4993 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4994 &tx_ring->dma, GFP_KERNEL);
4995 if (!tx_ring->desc)
4996 goto err;
4997
4998 tx_ring->next_to_use = 0;
4999 tx_ring->next_to_clean = 0;
5000 tx_ring->work_limit = tx_ring->count;
5001 return 0;
5002
5003 err:
5004 vfree(tx_ring->tx_buffer_info);
5005 tx_ring->tx_buffer_info = NULL;
5006 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5007 return -ENOMEM;
5008 }
5009
5010 /**
5011 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5012 * @adapter: board private structure
5013 *
5014 * If this function returns with an error, then it's possible one or
5015 * more of the rings is populated (while the rest are not). It is the
5016 * callers duty to clean those orphaned rings.
5017 *
5018 * Return 0 on success, negative on failure
5019 **/
5020 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5021 {
5022 int i, err = 0;
5023
5024 for (i = 0; i < adapter->num_tx_queues; i++) {
5025 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5026 if (!err)
5027 continue;
5028 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5029 break;
5030 }
5031
5032 return err;
5033 }
5034
5035 /**
5036 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5037 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5038 *
5039 * Returns 0 on success, negative on failure
5040 **/
5041 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5042 {
5043 struct device *dev = rx_ring->dev;
5044 int size;
5045
5046 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5047 rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
5048 if (!rx_ring->rx_buffer_info)
5049 rx_ring->rx_buffer_info = vmalloc(size);
5050 if (!rx_ring->rx_buffer_info)
5051 goto err;
5052 memset(rx_ring->rx_buffer_info, 0, size);
5053
5054 /* Round up to nearest 4K */
5055 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5056 rx_ring->size = ALIGN(rx_ring->size, 4096);
5057
5058 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5059 &rx_ring->dma, GFP_KERNEL);
5060
5061 if (!rx_ring->desc)
5062 goto err;
5063
5064 rx_ring->next_to_clean = 0;
5065 rx_ring->next_to_use = 0;
5066
5067 return 0;
5068 err:
5069 vfree(rx_ring->rx_buffer_info);
5070 rx_ring->rx_buffer_info = NULL;
5071 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5072 return -ENOMEM;
5073 }
5074
5075 /**
5076 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5077 * @adapter: board private structure
5078 *
5079 * If this function returns with an error, then it's possible one or
5080 * more of the rings is populated (while the rest are not). It is the
5081 * callers duty to clean those orphaned rings.
5082 *
5083 * Return 0 on success, negative on failure
5084 **/
5085 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5086 {
5087 int i, err = 0;
5088
5089 for (i = 0; i < adapter->num_rx_queues; i++) {
5090 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5091 if (!err)
5092 continue;
5093 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5094 break;
5095 }
5096
5097 return err;
5098 }
5099
5100 /**
5101 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5102 * @tx_ring: Tx descriptor ring for a specific queue
5103 *
5104 * Free all transmit software resources
5105 **/
5106 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5107 {
5108 ixgbe_clean_tx_ring(tx_ring);
5109
5110 vfree(tx_ring->tx_buffer_info);
5111 tx_ring->tx_buffer_info = NULL;
5112
5113 /* if not set, then don't free */
5114 if (!tx_ring->desc)
5115 return;
5116
5117 dma_free_coherent(tx_ring->dev, tx_ring->size,
5118 tx_ring->desc, tx_ring->dma);
5119
5120 tx_ring->desc = NULL;
5121 }
5122
5123 /**
5124 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5125 * @adapter: board private structure
5126 *
5127 * Free all transmit software resources
5128 **/
5129 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5130 {
5131 int i;
5132
5133 for (i = 0; i < adapter->num_tx_queues; i++)
5134 if (adapter->tx_ring[i]->desc)
5135 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5136 }
5137
5138 /**
5139 * ixgbe_free_rx_resources - Free Rx Resources
5140 * @rx_ring: ring to clean the resources from
5141 *
5142 * Free all receive software resources
5143 **/
5144 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5145 {
5146 ixgbe_clean_rx_ring(rx_ring);
5147
5148 vfree(rx_ring->rx_buffer_info);
5149 rx_ring->rx_buffer_info = NULL;
5150
5151 /* if not set, then don't free */
5152 if (!rx_ring->desc)
5153 return;
5154
5155 dma_free_coherent(rx_ring->dev, rx_ring->size,
5156 rx_ring->desc, rx_ring->dma);
5157
5158 rx_ring->desc = NULL;
5159 }
5160
5161 /**
5162 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5163 * @adapter: board private structure
5164 *
5165 * Free all receive software resources
5166 **/
5167 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5168 {
5169 int i;
5170
5171 for (i = 0; i < adapter->num_rx_queues; i++)
5172 if (adapter->rx_ring[i]->desc)
5173 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5174 }
5175
5176 /**
5177 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5178 * @netdev: network interface device structure
5179 * @new_mtu: new value for maximum frame size
5180 *
5181 * Returns 0 on success, negative on failure
5182 **/
5183 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5184 {
5185 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5186 struct ixgbe_hw *hw = &adapter->hw;
5187 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5188
5189 /* MTU < 68 is an error and causes problems on some kernels */
5190 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5191 return -EINVAL;
5192
5193 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5194 /* must set new MTU before calling down or up */
5195 netdev->mtu = new_mtu;
5196
5197 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5198 hw->fc.low_water = FC_LOW_WATER(max_frame);
5199
5200 if (netif_running(netdev))
5201 ixgbe_reinit_locked(adapter);
5202
5203 return 0;
5204 }
5205
5206 /**
5207 * ixgbe_open - Called when a network interface is made active
5208 * @netdev: network interface device structure
5209 *
5210 * Returns 0 on success, negative value on failure
5211 *
5212 * The open entry point is called when a network interface is made
5213 * active by the system (IFF_UP). At this point all resources needed
5214 * for transmit and receive operations are allocated, the interrupt
5215 * handler is registered with the OS, the watchdog timer is started,
5216 * and the stack is notified that the interface is ready.
5217 **/
5218 static int ixgbe_open(struct net_device *netdev)
5219 {
5220 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5221 int err;
5222
5223 /* disallow open during test */
5224 if (test_bit(__IXGBE_TESTING, &adapter->state))
5225 return -EBUSY;
5226
5227 netif_carrier_off(netdev);
5228
5229 /* allocate transmit descriptors */
5230 err = ixgbe_setup_all_tx_resources(adapter);
5231 if (err)
5232 goto err_setup_tx;
5233
5234 /* allocate receive descriptors */
5235 err = ixgbe_setup_all_rx_resources(adapter);
5236 if (err)
5237 goto err_setup_rx;
5238
5239 ixgbe_configure(adapter);
5240
5241 err = ixgbe_request_irq(adapter);
5242 if (err)
5243 goto err_req_irq;
5244
5245 err = ixgbe_up_complete(adapter);
5246 if (err)
5247 goto err_up;
5248
5249 netif_tx_start_all_queues(netdev);
5250
5251 return 0;
5252
5253 err_up:
5254 ixgbe_release_hw_control(adapter);
5255 ixgbe_free_irq(adapter);
5256 err_req_irq:
5257 err_setup_rx:
5258 ixgbe_free_all_rx_resources(adapter);
5259 err_setup_tx:
5260 ixgbe_free_all_tx_resources(adapter);
5261 ixgbe_reset(adapter);
5262
5263 return err;
5264 }
5265
5266 /**
5267 * ixgbe_close - Disables a network interface
5268 * @netdev: network interface device structure
5269 *
5270 * Returns 0, this is not allowed to fail
5271 *
5272 * The close entry point is called when an interface is de-activated
5273 * by the OS. The hardware is still under the drivers control, but
5274 * needs to be disabled. A global MAC reset is issued to stop the
5275 * hardware, and all transmit and receive resources are freed.
5276 **/
5277 static int ixgbe_close(struct net_device *netdev)
5278 {
5279 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5280
5281 ixgbe_down(adapter);
5282 ixgbe_free_irq(adapter);
5283
5284 ixgbe_free_all_tx_resources(adapter);
5285 ixgbe_free_all_rx_resources(adapter);
5286
5287 ixgbe_release_hw_control(adapter);
5288
5289 return 0;
5290 }
5291
5292 #ifdef CONFIG_PM
5293 static int ixgbe_resume(struct pci_dev *pdev)
5294 {
5295 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5296 struct net_device *netdev = adapter->netdev;
5297 u32 err;
5298
5299 pci_set_power_state(pdev, PCI_D0);
5300 pci_restore_state(pdev);
5301 /*
5302 * pci_restore_state clears dev->state_saved so call
5303 * pci_save_state to restore it.
5304 */
5305 pci_save_state(pdev);
5306
5307 err = pci_enable_device_mem(pdev);
5308 if (err) {
5309 e_dev_err("Cannot enable PCI device from suspend\n");
5310 return err;
5311 }
5312 pci_set_master(pdev);
5313
5314 pci_wake_from_d3(pdev, false);
5315
5316 err = ixgbe_init_interrupt_scheme(adapter);
5317 if (err) {
5318 e_dev_err("Cannot initialize interrupts for device\n");
5319 return err;
5320 }
5321
5322 ixgbe_reset(adapter);
5323
5324 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5325
5326 if (netif_running(netdev)) {
5327 err = ixgbe_open(netdev);
5328 if (err)
5329 return err;
5330 }
5331
5332 netif_device_attach(netdev);
5333
5334 return 0;
5335 }
5336 #endif /* CONFIG_PM */
5337
5338 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5339 {
5340 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5341 struct net_device *netdev = adapter->netdev;
5342 struct ixgbe_hw *hw = &adapter->hw;
5343 u32 ctrl, fctrl;
5344 u32 wufc = adapter->wol;
5345 #ifdef CONFIG_PM
5346 int retval = 0;
5347 #endif
5348
5349 netif_device_detach(netdev);
5350
5351 if (netif_running(netdev)) {
5352 ixgbe_down(adapter);
5353 ixgbe_free_irq(adapter);
5354 ixgbe_free_all_tx_resources(adapter);
5355 ixgbe_free_all_rx_resources(adapter);
5356 }
5357
5358 ixgbe_clear_interrupt_scheme(adapter);
5359
5360 #ifdef CONFIG_PM
5361 retval = pci_save_state(pdev);
5362 if (retval)
5363 return retval;
5364
5365 #endif
5366 if (wufc) {
5367 ixgbe_set_rx_mode(netdev);
5368
5369 /* turn on all-multi mode if wake on multicast is enabled */
5370 if (wufc & IXGBE_WUFC_MC) {
5371 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5372 fctrl |= IXGBE_FCTRL_MPE;
5373 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5374 }
5375
5376 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5377 ctrl |= IXGBE_CTRL_GIO_DIS;
5378 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5379
5380 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5381 } else {
5382 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5383 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5384 }
5385
5386 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5387 pci_wake_from_d3(pdev, true);
5388 else
5389 pci_wake_from_d3(pdev, false);
5390
5391 *enable_wake = !!wufc;
5392
5393 ixgbe_release_hw_control(adapter);
5394
5395 pci_disable_device(pdev);
5396
5397 return 0;
5398 }
5399
5400 #ifdef CONFIG_PM
5401 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5402 {
5403 int retval;
5404 bool wake;
5405
5406 retval = __ixgbe_shutdown(pdev, &wake);
5407 if (retval)
5408 return retval;
5409
5410 if (wake) {
5411 pci_prepare_to_sleep(pdev);
5412 } else {
5413 pci_wake_from_d3(pdev, false);
5414 pci_set_power_state(pdev, PCI_D3hot);
5415 }
5416
5417 return 0;
5418 }
5419 #endif /* CONFIG_PM */
5420
5421 static void ixgbe_shutdown(struct pci_dev *pdev)
5422 {
5423 bool wake;
5424
5425 __ixgbe_shutdown(pdev, &wake);
5426
5427 if (system_state == SYSTEM_POWER_OFF) {
5428 pci_wake_from_d3(pdev, wake);
5429 pci_set_power_state(pdev, PCI_D3hot);
5430 }
5431 }
5432
5433 /**
5434 * ixgbe_update_stats - Update the board statistics counters.
5435 * @adapter: board private structure
5436 **/
5437 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5438 {
5439 struct net_device *netdev = adapter->netdev;
5440 struct ixgbe_hw *hw = &adapter->hw;
5441 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5442 u64 total_mpc = 0;
5443 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5444 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5445 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5446 u64 bytes = 0, packets = 0;
5447
5448 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5449 test_bit(__IXGBE_RESETTING, &adapter->state))
5450 return;
5451
5452 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5453 u64 rsc_count = 0;
5454 u64 rsc_flush = 0;
5455 for (i = 0; i < 16; i++)
5456 adapter->hw_rx_no_dma_resources +=
5457 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5458 for (i = 0; i < adapter->num_rx_queues; i++) {
5459 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5460 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5461 }
5462 adapter->rsc_total_count = rsc_count;
5463 adapter->rsc_total_flush = rsc_flush;
5464 }
5465
5466 for (i = 0; i < adapter->num_rx_queues; i++) {
5467 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5468 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5469 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5470 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5471 bytes += rx_ring->stats.bytes;
5472 packets += rx_ring->stats.packets;
5473 }
5474 adapter->non_eop_descs = non_eop_descs;
5475 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5476 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5477 netdev->stats.rx_bytes = bytes;
5478 netdev->stats.rx_packets = packets;
5479
5480 bytes = 0;
5481 packets = 0;
5482 /* gather some stats to the adapter struct that are per queue */
5483 for (i = 0; i < adapter->num_tx_queues; i++) {
5484 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5485 restart_queue += tx_ring->tx_stats.restart_queue;
5486 tx_busy += tx_ring->tx_stats.tx_busy;
5487 bytes += tx_ring->stats.bytes;
5488 packets += tx_ring->stats.packets;
5489 }
5490 adapter->restart_queue = restart_queue;
5491 adapter->tx_busy = tx_busy;
5492 netdev->stats.tx_bytes = bytes;
5493 netdev->stats.tx_packets = packets;
5494
5495 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5496 for (i = 0; i < 8; i++) {
5497 /* for packet buffers not used, the register should read 0 */
5498 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5499 missed_rx += mpc;
5500 hwstats->mpc[i] += mpc;
5501 total_mpc += hwstats->mpc[i];
5502 if (hw->mac.type == ixgbe_mac_82598EB)
5503 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5504 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5505 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5506 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5507 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5508 if (hw->mac.type == ixgbe_mac_82599EB) {
5509 hwstats->pxonrxc[i] +=
5510 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5511 hwstats->pxoffrxc[i] +=
5512 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5513 hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5514 } else {
5515 hwstats->pxonrxc[i] +=
5516 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5517 hwstats->pxoffrxc[i] +=
5518 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
5519 }
5520 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5521 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5522 }
5523 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5524 /* work around hardware counting issue */
5525 hwstats->gprc -= missed_rx;
5526
5527 /* 82598 hardware only has a 32 bit counter in the high register */
5528 if (hw->mac.type == ixgbe_mac_82599EB) {
5529 u64 tmp;
5530 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5531 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5532 /* 4 high bits of GORC */
5533 hwstats->gorc += (tmp << 32);
5534 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5535 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5536 /* 4 high bits of GOTC */
5537 hwstats->gotc += (tmp << 32);
5538 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5539 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5540 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5541 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5542 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5543 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5544 #ifdef IXGBE_FCOE
5545 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5546 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5547 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5548 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5549 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5550 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5551 #endif /* IXGBE_FCOE */
5552 } else {
5553 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5554 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5555 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5556 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5557 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5558 }
5559 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5560 hwstats->bprc += bprc;
5561 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5562 if (hw->mac.type == ixgbe_mac_82598EB)
5563 hwstats->mprc -= bprc;
5564 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5565 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5566 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5567 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5568 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5569 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5570 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5571 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5572 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5573 hwstats->lxontxc += lxon;
5574 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5575 hwstats->lxofftxc += lxoff;
5576 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5577 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5578 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5579 /*
5580 * 82598 errata - tx of flow control packets is included in tx counters
5581 */
5582 xon_off_tot = lxon + lxoff;
5583 hwstats->gptc -= xon_off_tot;
5584 hwstats->mptc -= xon_off_tot;
5585 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5586 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5587 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5588 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5589 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5590 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5591 hwstats->ptc64 -= xon_off_tot;
5592 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5593 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5594 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5595 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5596 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5597 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5598
5599 /* Fill out the OS statistics structure */
5600 netdev->stats.multicast = hwstats->mprc;
5601
5602 /* Rx Errors */
5603 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5604 netdev->stats.rx_dropped = 0;
5605 netdev->stats.rx_length_errors = hwstats->rlec;
5606 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5607 netdev->stats.rx_missed_errors = total_mpc;
5608 }
5609
5610 /**
5611 * ixgbe_watchdog - Timer Call-back
5612 * @data: pointer to adapter cast into an unsigned long
5613 **/
5614 static void ixgbe_watchdog(unsigned long data)
5615 {
5616 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5617 struct ixgbe_hw *hw = &adapter->hw;
5618 u64 eics = 0;
5619 int i;
5620
5621 /*
5622 * Do the watchdog outside of interrupt context due to the lovely
5623 * delays that some of the newer hardware requires
5624 */
5625
5626 if (test_bit(__IXGBE_DOWN, &adapter->state))
5627 goto watchdog_short_circuit;
5628
5629 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5630 /*
5631 * for legacy and MSI interrupts don't set any bits
5632 * that are enabled for EIAM, because this operation
5633 * would set *both* EIMS and EICS for any bit in EIAM
5634 */
5635 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5636 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5637 goto watchdog_reschedule;
5638 }
5639
5640 /* get one bit for every active tx/rx interrupt vector */
5641 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5642 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5643 if (qv->rxr_count || qv->txr_count)
5644 eics |= ((u64)1 << i);
5645 }
5646
5647 /* Cause software interrupt to ensure rx rings are cleaned */
5648 ixgbe_irq_rearm_queues(adapter, eics);
5649
5650 watchdog_reschedule:
5651 /* Reset the timer */
5652 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5653
5654 watchdog_short_circuit:
5655 schedule_work(&adapter->watchdog_task);
5656 }
5657
5658 /**
5659 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5660 * @work: pointer to work_struct containing our data
5661 **/
5662 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5663 {
5664 struct ixgbe_adapter *adapter = container_of(work,
5665 struct ixgbe_adapter,
5666 multispeed_fiber_task);
5667 struct ixgbe_hw *hw = &adapter->hw;
5668 u32 autoneg;
5669 bool negotiation;
5670
5671 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5672 autoneg = hw->phy.autoneg_advertised;
5673 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5674 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5675 hw->mac.autotry_restart = false;
5676 if (hw->mac.ops.setup_link)
5677 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5678 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5679 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5680 }
5681
5682 /**
5683 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5684 * @work: pointer to work_struct containing our data
5685 **/
5686 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5687 {
5688 struct ixgbe_adapter *adapter = container_of(work,
5689 struct ixgbe_adapter,
5690 sfp_config_module_task);
5691 struct ixgbe_hw *hw = &adapter->hw;
5692 u32 err;
5693
5694 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5695
5696 /* Time for electrical oscillations to settle down */
5697 msleep(100);
5698 err = hw->phy.ops.identify_sfp(hw);
5699
5700 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5701 e_dev_err("failed to initialize because an unsupported SFP+ "
5702 "module type was detected.\n");
5703 e_dev_err("Reload the driver after installing a supported "
5704 "module.\n");
5705 unregister_netdev(adapter->netdev);
5706 return;
5707 }
5708 hw->mac.ops.setup_sfp(hw);
5709
5710 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5711 /* This will also work for DA Twinax connections */
5712 schedule_work(&adapter->multispeed_fiber_task);
5713 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5714 }
5715
5716 /**
5717 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5718 * @work: pointer to work_struct containing our data
5719 **/
5720 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5721 {
5722 struct ixgbe_adapter *adapter = container_of(work,
5723 struct ixgbe_adapter,
5724 fdir_reinit_task);
5725 struct ixgbe_hw *hw = &adapter->hw;
5726 int i;
5727
5728 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5729 for (i = 0; i < adapter->num_tx_queues; i++)
5730 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5731 &(adapter->tx_ring[i]->state));
5732 } else {
5733 e_err(probe, "failed to finish FDIR re-initialization, "
5734 "ignored adding FDIR ATR filters\n");
5735 }
5736 /* Done FDIR Re-initialization, enable transmits */
5737 netif_tx_start_all_queues(adapter->netdev);
5738 }
5739
5740 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5741
5742 /**
5743 * ixgbe_watchdog_task - worker thread to bring link up
5744 * @work: pointer to work_struct containing our data
5745 **/
5746 static void ixgbe_watchdog_task(struct work_struct *work)
5747 {
5748 struct ixgbe_adapter *adapter = container_of(work,
5749 struct ixgbe_adapter,
5750 watchdog_task);
5751 struct net_device *netdev = adapter->netdev;
5752 struct ixgbe_hw *hw = &adapter->hw;
5753 u32 link_speed;
5754 bool link_up;
5755 int i;
5756 struct ixgbe_ring *tx_ring;
5757 int some_tx_pending = 0;
5758
5759 mutex_lock(&ixgbe_watchdog_lock);
5760
5761 link_up = adapter->link_up;
5762 link_speed = adapter->link_speed;
5763
5764 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5765 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5766 if (link_up) {
5767 #ifdef CONFIG_DCB
5768 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5769 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5770 hw->mac.ops.fc_enable(hw, i);
5771 } else {
5772 hw->mac.ops.fc_enable(hw, 0);
5773 }
5774 #else
5775 hw->mac.ops.fc_enable(hw, 0);
5776 #endif
5777 }
5778
5779 if (link_up ||
5780 time_after(jiffies, (adapter->link_check_timeout +
5781 IXGBE_TRY_LINK_TIMEOUT))) {
5782 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5783 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5784 }
5785 adapter->link_up = link_up;
5786 adapter->link_speed = link_speed;
5787 }
5788
5789 if (link_up) {
5790 if (!netif_carrier_ok(netdev)) {
5791 bool flow_rx, flow_tx;
5792
5793 if (hw->mac.type == ixgbe_mac_82599EB) {
5794 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5795 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5796 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5797 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5798 } else {
5799 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5800 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5801 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5802 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5803 }
5804
5805 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5806 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5807 "10 Gbps" :
5808 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5809 "1 Gbps" : "unknown speed")),
5810 ((flow_rx && flow_tx) ? "RX/TX" :
5811 (flow_rx ? "RX" :
5812 (flow_tx ? "TX" : "None"))));
5813
5814 netif_carrier_on(netdev);
5815 } else {
5816 /* Force detection of hung controller */
5817 for (i = 0; i < adapter->num_tx_queues; i++) {
5818 tx_ring = adapter->tx_ring[i];
5819 set_check_for_tx_hang(tx_ring);
5820 }
5821 }
5822 } else {
5823 adapter->link_up = false;
5824 adapter->link_speed = 0;
5825 if (netif_carrier_ok(netdev)) {
5826 e_info(drv, "NIC Link is Down\n");
5827 netif_carrier_off(netdev);
5828 }
5829 }
5830
5831 if (!netif_carrier_ok(netdev)) {
5832 for (i = 0; i < adapter->num_tx_queues; i++) {
5833 tx_ring = adapter->tx_ring[i];
5834 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5835 some_tx_pending = 1;
5836 break;
5837 }
5838 }
5839
5840 if (some_tx_pending) {
5841 /* We've lost link, so the controller stops DMA,
5842 * but we've got queued Tx work that's never going
5843 * to get done, so reset controller to flush Tx.
5844 * (Do the reset outside of interrupt context).
5845 */
5846 schedule_work(&adapter->reset_task);
5847 }
5848 }
5849
5850 ixgbe_update_stats(adapter);
5851 mutex_unlock(&ixgbe_watchdog_lock);
5852 }
5853
5854 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5855 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5856 u32 tx_flags, u8 *hdr_len, __be16 protocol)
5857 {
5858 struct ixgbe_adv_tx_context_desc *context_desc;
5859 unsigned int i;
5860 int err;
5861 struct ixgbe_tx_buffer *tx_buffer_info;
5862 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5863 u32 mss_l4len_idx, l4len;
5864
5865 if (skb_is_gso(skb)) {
5866 if (skb_header_cloned(skb)) {
5867 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5868 if (err)
5869 return err;
5870 }
5871 l4len = tcp_hdrlen(skb);
5872 *hdr_len += l4len;
5873
5874 if (protocol == htons(ETH_P_IP)) {
5875 struct iphdr *iph = ip_hdr(skb);
5876 iph->tot_len = 0;
5877 iph->check = 0;
5878 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5879 iph->daddr, 0,
5880 IPPROTO_TCP,
5881 0);
5882 } else if (skb_is_gso_v6(skb)) {
5883 ipv6_hdr(skb)->payload_len = 0;
5884 tcp_hdr(skb)->check =
5885 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5886 &ipv6_hdr(skb)->daddr,
5887 0, IPPROTO_TCP, 0);
5888 }
5889
5890 i = tx_ring->next_to_use;
5891
5892 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5893 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5894
5895 /* VLAN MACLEN IPLEN */
5896 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5897 vlan_macip_lens |=
5898 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5899 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5900 IXGBE_ADVTXD_MACLEN_SHIFT);
5901 *hdr_len += skb_network_offset(skb);
5902 vlan_macip_lens |=
5903 (skb_transport_header(skb) - skb_network_header(skb));
5904 *hdr_len +=
5905 (skb_transport_header(skb) - skb_network_header(skb));
5906 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5907 context_desc->seqnum_seed = 0;
5908
5909 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5910 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5911 IXGBE_ADVTXD_DTYP_CTXT);
5912
5913 if (protocol == htons(ETH_P_IP))
5914 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5915 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5916 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5917
5918 /* MSS L4LEN IDX */
5919 mss_l4len_idx =
5920 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5921 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5922 /* use index 1 for TSO */
5923 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5924 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5925
5926 tx_buffer_info->time_stamp = jiffies;
5927 tx_buffer_info->next_to_watch = i;
5928
5929 i++;
5930 if (i == tx_ring->count)
5931 i = 0;
5932 tx_ring->next_to_use = i;
5933
5934 return true;
5935 }
5936 return false;
5937 }
5938
5939 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5940 __be16 protocol)
5941 {
5942 u32 rtn = 0;
5943
5944 switch (protocol) {
5945 case cpu_to_be16(ETH_P_IP):
5946 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5947 switch (ip_hdr(skb)->protocol) {
5948 case IPPROTO_TCP:
5949 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5950 break;
5951 case IPPROTO_SCTP:
5952 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5953 break;
5954 }
5955 break;
5956 case cpu_to_be16(ETH_P_IPV6):
5957 /* XXX what about other V6 headers?? */
5958 switch (ipv6_hdr(skb)->nexthdr) {
5959 case IPPROTO_TCP:
5960 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5961 break;
5962 case IPPROTO_SCTP:
5963 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5964 break;
5965 }
5966 break;
5967 default:
5968 if (unlikely(net_ratelimit()))
5969 e_warn(probe, "partial checksum but proto=%x!\n",
5970 protocol);
5971 break;
5972 }
5973
5974 return rtn;
5975 }
5976
5977 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5978 struct ixgbe_ring *tx_ring,
5979 struct sk_buff *skb, u32 tx_flags,
5980 __be16 protocol)
5981 {
5982 struct ixgbe_adv_tx_context_desc *context_desc;
5983 unsigned int i;
5984 struct ixgbe_tx_buffer *tx_buffer_info;
5985 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5986
5987 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5988 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5989 i = tx_ring->next_to_use;
5990 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5991 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5992
5993 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5994 vlan_macip_lens |=
5995 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5996 vlan_macip_lens |= (skb_network_offset(skb) <<
5997 IXGBE_ADVTXD_MACLEN_SHIFT);
5998 if (skb->ip_summed == CHECKSUM_PARTIAL)
5999 vlan_macip_lens |= (skb_transport_header(skb) -
6000 skb_network_header(skb));
6001
6002 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6003 context_desc->seqnum_seed = 0;
6004
6005 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6006 IXGBE_ADVTXD_DTYP_CTXT);
6007
6008 if (skb->ip_summed == CHECKSUM_PARTIAL)
6009 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6010
6011 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6012 /* use index zero for tx checksum offload */
6013 context_desc->mss_l4len_idx = 0;
6014
6015 tx_buffer_info->time_stamp = jiffies;
6016 tx_buffer_info->next_to_watch = i;
6017
6018 i++;
6019 if (i == tx_ring->count)
6020 i = 0;
6021 tx_ring->next_to_use = i;
6022
6023 return true;
6024 }
6025
6026 return false;
6027 }
6028
6029 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6030 struct ixgbe_ring *tx_ring,
6031 struct sk_buff *skb, u32 tx_flags,
6032 unsigned int first, const u8 hdr_len)
6033 {
6034 struct device *dev = tx_ring->dev;
6035 struct ixgbe_tx_buffer *tx_buffer_info;
6036 unsigned int len;
6037 unsigned int total = skb->len;
6038 unsigned int offset = 0, size, count = 0, i;
6039 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6040 unsigned int f;
6041 unsigned int bytecount = skb->len;
6042 u16 gso_segs = 1;
6043
6044 i = tx_ring->next_to_use;
6045
6046 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6047 /* excluding fcoe_crc_eof for FCoE */
6048 total -= sizeof(struct fcoe_crc_eof);
6049
6050 len = min(skb_headlen(skb), total);
6051 while (len) {
6052 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6053 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6054
6055 tx_buffer_info->length = size;
6056 tx_buffer_info->mapped_as_page = false;
6057 tx_buffer_info->dma = dma_map_single(dev,
6058 skb->data + offset,
6059 size, DMA_TO_DEVICE);
6060 if (dma_mapping_error(dev, tx_buffer_info->dma))
6061 goto dma_error;
6062 tx_buffer_info->time_stamp = jiffies;
6063 tx_buffer_info->next_to_watch = i;
6064
6065 len -= size;
6066 total -= size;
6067 offset += size;
6068 count++;
6069
6070 if (len) {
6071 i++;
6072 if (i == tx_ring->count)
6073 i = 0;
6074 }
6075 }
6076
6077 for (f = 0; f < nr_frags; f++) {
6078 struct skb_frag_struct *frag;
6079
6080 frag = &skb_shinfo(skb)->frags[f];
6081 len = min((unsigned int)frag->size, total);
6082 offset = frag->page_offset;
6083
6084 while (len) {
6085 i++;
6086 if (i == tx_ring->count)
6087 i = 0;
6088
6089 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6090 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6091
6092 tx_buffer_info->length = size;
6093 tx_buffer_info->dma = dma_map_page(dev,
6094 frag->page,
6095 offset, size,
6096 DMA_TO_DEVICE);
6097 tx_buffer_info->mapped_as_page = true;
6098 if (dma_mapping_error(dev, tx_buffer_info->dma))
6099 goto dma_error;
6100 tx_buffer_info->time_stamp = jiffies;
6101 tx_buffer_info->next_to_watch = i;
6102
6103 len -= size;
6104 total -= size;
6105 offset += size;
6106 count++;
6107 }
6108 if (total == 0)
6109 break;
6110 }
6111
6112 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6113 gso_segs = skb_shinfo(skb)->gso_segs;
6114 #ifdef IXGBE_FCOE
6115 /* adjust for FCoE Sequence Offload */
6116 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6117 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6118 skb_shinfo(skb)->gso_size);
6119 #endif /* IXGBE_FCOE */
6120 bytecount += (gso_segs - 1) * hdr_len;
6121
6122 /* multiply data chunks by size of headers */
6123 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6124 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6125 tx_ring->tx_buffer_info[i].skb = skb;
6126 tx_ring->tx_buffer_info[first].next_to_watch = i;
6127
6128 return count;
6129
6130 dma_error:
6131 e_dev_err("TX DMA map failed\n");
6132
6133 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6134 tx_buffer_info->dma = 0;
6135 tx_buffer_info->time_stamp = 0;
6136 tx_buffer_info->next_to_watch = 0;
6137 if (count)
6138 count--;
6139
6140 /* clear timestamp and dma mappings for remaining portion of packet */
6141 while (count--) {
6142 if (i == 0)
6143 i += tx_ring->count;
6144 i--;
6145 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6146 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6147 }
6148
6149 return 0;
6150 }
6151
6152 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6153 int tx_flags, int count, u32 paylen, u8 hdr_len)
6154 {
6155 union ixgbe_adv_tx_desc *tx_desc = NULL;
6156 struct ixgbe_tx_buffer *tx_buffer_info;
6157 u32 olinfo_status = 0, cmd_type_len = 0;
6158 unsigned int i;
6159 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6160
6161 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6162
6163 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6164
6165 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6166 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6167
6168 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6169 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6170
6171 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6172 IXGBE_ADVTXD_POPTS_SHIFT;
6173
6174 /* use index 1 context for tso */
6175 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6176 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6177 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6178 IXGBE_ADVTXD_POPTS_SHIFT;
6179
6180 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6181 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6182 IXGBE_ADVTXD_POPTS_SHIFT;
6183
6184 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6185 olinfo_status |= IXGBE_ADVTXD_CC;
6186 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6187 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6188 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6189 }
6190
6191 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6192
6193 i = tx_ring->next_to_use;
6194 while (count--) {
6195 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6196 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6197 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6198 tx_desc->read.cmd_type_len =
6199 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6200 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6201 i++;
6202 if (i == tx_ring->count)
6203 i = 0;
6204 }
6205
6206 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6207
6208 /*
6209 * Force memory writes to complete before letting h/w
6210 * know there are new descriptors to fetch. (Only
6211 * applicable for weak-ordered memory model archs,
6212 * such as IA-64).
6213 */
6214 wmb();
6215
6216 tx_ring->next_to_use = i;
6217 writel(i, tx_ring->tail);
6218 }
6219
6220 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6221 int queue, u32 tx_flags, __be16 protocol)
6222 {
6223 struct ixgbe_atr_input atr_input;
6224 struct tcphdr *th;
6225 struct iphdr *iph = ip_hdr(skb);
6226 struct ethhdr *eth = (struct ethhdr *)skb->data;
6227 u16 vlan_id, src_port, dst_port, flex_bytes;
6228 u32 src_ipv4_addr, dst_ipv4_addr;
6229 u8 l4type = 0;
6230
6231 /* Right now, we support IPv4 only */
6232 if (protocol != htons(ETH_P_IP))
6233 return;
6234 /* check if we're UDP or TCP */
6235 if (iph->protocol == IPPROTO_TCP) {
6236 th = tcp_hdr(skb);
6237 src_port = th->source;
6238 dst_port = th->dest;
6239 l4type |= IXGBE_ATR_L4TYPE_TCP;
6240 /* l4type IPv4 type is 0, no need to assign */
6241 } else {
6242 /* Unsupported L4 header, just bail here */
6243 return;
6244 }
6245
6246 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6247
6248 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6249 IXGBE_TX_FLAGS_VLAN_SHIFT;
6250 src_ipv4_addr = iph->saddr;
6251 dst_ipv4_addr = iph->daddr;
6252 flex_bytes = eth->h_proto;
6253
6254 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6255 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6256 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6257 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6258 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6259 /* src and dst are inverted, think how the receiver sees them */
6260 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6261 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6262
6263 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6264 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6265 }
6266
6267 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6268 {
6269 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6270 /* Herbert's original patch had:
6271 * smp_mb__after_netif_stop_queue();
6272 * but since that doesn't exist yet, just open code it. */
6273 smp_mb();
6274
6275 /* We need to check again in a case another CPU has just
6276 * made room available. */
6277 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6278 return -EBUSY;
6279
6280 /* A reprieve! - use start_queue because it doesn't call schedule */
6281 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6282 ++tx_ring->tx_stats.restart_queue;
6283 return 0;
6284 }
6285
6286 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6287 {
6288 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6289 return 0;
6290 return __ixgbe_maybe_stop_tx(tx_ring, size);
6291 }
6292
6293 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6294 {
6295 struct ixgbe_adapter *adapter = netdev_priv(dev);
6296 int txq = smp_processor_id();
6297 #ifdef IXGBE_FCOE
6298 __be16 protocol;
6299
6300 protocol = vlan_get_protocol(skb);
6301
6302 if ((protocol == htons(ETH_P_FCOE)) ||
6303 (protocol == htons(ETH_P_FIP))) {
6304 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6305 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6306 txq += adapter->ring_feature[RING_F_FCOE].mask;
6307 return txq;
6308 #ifdef CONFIG_IXGBE_DCB
6309 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6310 txq = adapter->fcoe.up;
6311 return txq;
6312 #endif
6313 }
6314 }
6315 #endif
6316
6317 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6318 while (unlikely(txq >= dev->real_num_tx_queues))
6319 txq -= dev->real_num_tx_queues;
6320 return txq;
6321 }
6322
6323 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6324 if (skb->priority == TC_PRIO_CONTROL)
6325 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6326 else
6327 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6328 >> 13;
6329 return txq;
6330 }
6331
6332 return skb_tx_hash(dev, skb);
6333 }
6334
6335 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6336 struct ixgbe_adapter *adapter,
6337 struct ixgbe_ring *tx_ring)
6338 {
6339 struct net_device *netdev = tx_ring->netdev;
6340 struct netdev_queue *txq;
6341 unsigned int first;
6342 unsigned int tx_flags = 0;
6343 u8 hdr_len = 0;
6344 int tso;
6345 int count = 0;
6346 unsigned int f;
6347 __be16 protocol;
6348
6349 protocol = vlan_get_protocol(skb);
6350
6351 if (vlan_tx_tag_present(skb)) {
6352 tx_flags |= vlan_tx_tag_get(skb);
6353 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6354 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6355 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6356 }
6357 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6358 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6359 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6360 skb->priority != TC_PRIO_CONTROL) {
6361 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6362 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6363 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6364 }
6365
6366 #ifdef IXGBE_FCOE
6367 /* for FCoE with DCB, we force the priority to what
6368 * was specified by the switch */
6369 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6370 (protocol == htons(ETH_P_FCOE) ||
6371 protocol == htons(ETH_P_FIP))) {
6372 #ifdef CONFIG_IXGBE_DCB
6373 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6374 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6375 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6376 tx_flags |= ((adapter->fcoe.up << 13)
6377 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6378 }
6379 #endif
6380 /* flag for FCoE offloads */
6381 if (protocol == htons(ETH_P_FCOE))
6382 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6383 }
6384 #endif
6385
6386 /* four things can cause us to need a context descriptor */
6387 if (skb_is_gso(skb) ||
6388 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6389 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6390 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6391 count++;
6392
6393 count += TXD_USE_COUNT(skb_headlen(skb));
6394 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6395 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6396
6397 if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6398 tx_ring->tx_stats.tx_busy++;
6399 return NETDEV_TX_BUSY;
6400 }
6401
6402 first = tx_ring->next_to_use;
6403 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6404 #ifdef IXGBE_FCOE
6405 /* setup tx offload for FCoE */
6406 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6407 if (tso < 0) {
6408 dev_kfree_skb_any(skb);
6409 return NETDEV_TX_OK;
6410 }
6411 if (tso)
6412 tx_flags |= IXGBE_TX_FLAGS_FSO;
6413 #endif /* IXGBE_FCOE */
6414 } else {
6415 if (protocol == htons(ETH_P_IP))
6416 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6417 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6418 protocol);
6419 if (tso < 0) {
6420 dev_kfree_skb_any(skb);
6421 return NETDEV_TX_OK;
6422 }
6423
6424 if (tso)
6425 tx_flags |= IXGBE_TX_FLAGS_TSO;
6426 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6427 protocol) &&
6428 (skb->ip_summed == CHECKSUM_PARTIAL))
6429 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6430 }
6431
6432 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6433 if (count) {
6434 /* add the ATR filter if ATR is on */
6435 if (tx_ring->atr_sample_rate) {
6436 ++tx_ring->atr_count;
6437 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6438 test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6439 &tx_ring->state)) {
6440 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6441 tx_flags, protocol);
6442 tx_ring->atr_count = 0;
6443 }
6444 }
6445 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6446 txq->tx_bytes += skb->len;
6447 txq->tx_packets++;
6448 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6449 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6450
6451 } else {
6452 dev_kfree_skb_any(skb);
6453 tx_ring->tx_buffer_info[first].time_stamp = 0;
6454 tx_ring->next_to_use = first;
6455 }
6456
6457 return NETDEV_TX_OK;
6458 }
6459
6460 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6461 {
6462 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6463 struct ixgbe_ring *tx_ring;
6464
6465 tx_ring = adapter->tx_ring[skb->queue_mapping];
6466 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6467 }
6468
6469 /**
6470 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6471 * @netdev: network interface device structure
6472 * @p: pointer to an address structure
6473 *
6474 * Returns 0 on success, negative on failure
6475 **/
6476 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6477 {
6478 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6479 struct ixgbe_hw *hw = &adapter->hw;
6480 struct sockaddr *addr = p;
6481
6482 if (!is_valid_ether_addr(addr->sa_data))
6483 return -EADDRNOTAVAIL;
6484
6485 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6486 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6487
6488 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6489 IXGBE_RAH_AV);
6490
6491 return 0;
6492 }
6493
6494 static int
6495 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6496 {
6497 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6498 struct ixgbe_hw *hw = &adapter->hw;
6499 u16 value;
6500 int rc;
6501
6502 if (prtad != hw->phy.mdio.prtad)
6503 return -EINVAL;
6504 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6505 if (!rc)
6506 rc = value;
6507 return rc;
6508 }
6509
6510 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6511 u16 addr, u16 value)
6512 {
6513 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6514 struct ixgbe_hw *hw = &adapter->hw;
6515
6516 if (prtad != hw->phy.mdio.prtad)
6517 return -EINVAL;
6518 return hw->phy.ops.write_reg(hw, addr, devad, value);
6519 }
6520
6521 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6522 {
6523 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6524
6525 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6526 }
6527
6528 /**
6529 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6530 * netdev->dev_addrs
6531 * @netdev: network interface device structure
6532 *
6533 * Returns non-zero on failure
6534 **/
6535 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6536 {
6537 int err = 0;
6538 struct ixgbe_adapter *adapter = netdev_priv(dev);
6539 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6540
6541 if (is_valid_ether_addr(mac->san_addr)) {
6542 rtnl_lock();
6543 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6544 rtnl_unlock();
6545 }
6546 return err;
6547 }
6548
6549 /**
6550 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6551 * netdev->dev_addrs
6552 * @netdev: network interface device structure
6553 *
6554 * Returns non-zero on failure
6555 **/
6556 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6557 {
6558 int err = 0;
6559 struct ixgbe_adapter *adapter = netdev_priv(dev);
6560 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6561
6562 if (is_valid_ether_addr(mac->san_addr)) {
6563 rtnl_lock();
6564 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6565 rtnl_unlock();
6566 }
6567 return err;
6568 }
6569
6570 #ifdef CONFIG_NET_POLL_CONTROLLER
6571 /*
6572 * Polling 'interrupt' - used by things like netconsole to send skbs
6573 * without having to re-enable interrupts. It's not called while
6574 * the interrupt routine is executing.
6575 */
6576 static void ixgbe_netpoll(struct net_device *netdev)
6577 {
6578 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6579 int i;
6580
6581 /* if interface is down do nothing */
6582 if (test_bit(__IXGBE_DOWN, &adapter->state))
6583 return;
6584
6585 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6586 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6587 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6588 for (i = 0; i < num_q_vectors; i++) {
6589 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6590 ixgbe_msix_clean_many(0, q_vector);
6591 }
6592 } else {
6593 ixgbe_intr(adapter->pdev->irq, netdev);
6594 }
6595 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6596 }
6597 #endif
6598
6599 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6600 struct rtnl_link_stats64 *stats)
6601 {
6602 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6603 int i;
6604
6605 /* accurate rx/tx bytes/packets stats */
6606 dev_txq_stats_fold(netdev, stats);
6607 rcu_read_lock();
6608 for (i = 0; i < adapter->num_rx_queues; i++) {
6609 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6610 u64 bytes, packets;
6611 unsigned int start;
6612
6613 if (ring) {
6614 do {
6615 start = u64_stats_fetch_begin_bh(&ring->syncp);
6616 packets = ring->stats.packets;
6617 bytes = ring->stats.bytes;
6618 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6619 stats->rx_packets += packets;
6620 stats->rx_bytes += bytes;
6621 }
6622 }
6623 rcu_read_unlock();
6624 /* following stats updated by ixgbe_watchdog_task() */
6625 stats->multicast = netdev->stats.multicast;
6626 stats->rx_errors = netdev->stats.rx_errors;
6627 stats->rx_length_errors = netdev->stats.rx_length_errors;
6628 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6629 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6630 return stats;
6631 }
6632
6633
6634 static const struct net_device_ops ixgbe_netdev_ops = {
6635 .ndo_open = ixgbe_open,
6636 .ndo_stop = ixgbe_close,
6637 .ndo_start_xmit = ixgbe_xmit_frame,
6638 .ndo_select_queue = ixgbe_select_queue,
6639 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6640 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6641 .ndo_validate_addr = eth_validate_addr,
6642 .ndo_set_mac_address = ixgbe_set_mac,
6643 .ndo_change_mtu = ixgbe_change_mtu,
6644 .ndo_tx_timeout = ixgbe_tx_timeout,
6645 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6646 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6647 .ndo_do_ioctl = ixgbe_ioctl,
6648 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6649 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6650 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6651 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6652 .ndo_get_stats64 = ixgbe_get_stats64,
6653 #ifdef CONFIG_NET_POLL_CONTROLLER
6654 .ndo_poll_controller = ixgbe_netpoll,
6655 #endif
6656 #ifdef IXGBE_FCOE
6657 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6658 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6659 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6660 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6661 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6662 #endif /* IXGBE_FCOE */
6663 };
6664
6665 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6666 const struct ixgbe_info *ii)
6667 {
6668 #ifdef CONFIG_PCI_IOV
6669 struct ixgbe_hw *hw = &adapter->hw;
6670 int err;
6671
6672 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6673 return;
6674
6675 /* The 82599 supports up to 64 VFs per physical function
6676 * but this implementation limits allocation to 63 so that
6677 * basic networking resources are still available to the
6678 * physical function
6679 */
6680 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6681 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6682 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6683 if (err) {
6684 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6685 goto err_novfs;
6686 }
6687 /* If call to enable VFs succeeded then allocate memory
6688 * for per VF control structures.
6689 */
6690 adapter->vfinfo =
6691 kcalloc(adapter->num_vfs,
6692 sizeof(struct vf_data_storage), GFP_KERNEL);
6693 if (adapter->vfinfo) {
6694 /* Now that we're sure SR-IOV is enabled
6695 * and memory allocated set up the mailbox parameters
6696 */
6697 ixgbe_init_mbx_params_pf(hw);
6698 memcpy(&hw->mbx.ops, ii->mbx_ops,
6699 sizeof(hw->mbx.ops));
6700
6701 /* Disable RSC when in SR-IOV mode */
6702 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6703 IXGBE_FLAG2_RSC_ENABLED);
6704 return;
6705 }
6706
6707 /* Oh oh */
6708 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6709 "SRIOV disabled\n");
6710 pci_disable_sriov(adapter->pdev);
6711
6712 err_novfs:
6713 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6714 adapter->num_vfs = 0;
6715 #endif /* CONFIG_PCI_IOV */
6716 }
6717
6718 /**
6719 * ixgbe_probe - Device Initialization Routine
6720 * @pdev: PCI device information struct
6721 * @ent: entry in ixgbe_pci_tbl
6722 *
6723 * Returns 0 on success, negative on failure
6724 *
6725 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6726 * The OS initialization, configuring of the adapter private structure,
6727 * and a hardware reset occur.
6728 **/
6729 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6730 const struct pci_device_id *ent)
6731 {
6732 struct net_device *netdev;
6733 struct ixgbe_adapter *adapter = NULL;
6734 struct ixgbe_hw *hw;
6735 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6736 static int cards_found;
6737 int i, err, pci_using_dac;
6738 unsigned int indices = num_possible_cpus();
6739 #ifdef IXGBE_FCOE
6740 u16 device_caps;
6741 #endif
6742 u32 part_num, eec;
6743
6744 /* Catch broken hardware that put the wrong VF device ID in
6745 * the PCIe SR-IOV capability.
6746 */
6747 if (pdev->is_virtfn) {
6748 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6749 pci_name(pdev), pdev->vendor, pdev->device);
6750 return -EINVAL;
6751 }
6752
6753 err = pci_enable_device_mem(pdev);
6754 if (err)
6755 return err;
6756
6757 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6758 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6759 pci_using_dac = 1;
6760 } else {
6761 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6762 if (err) {
6763 err = dma_set_coherent_mask(&pdev->dev,
6764 DMA_BIT_MASK(32));
6765 if (err) {
6766 dev_err(&pdev->dev,
6767 "No usable DMA configuration, aborting\n");
6768 goto err_dma;
6769 }
6770 }
6771 pci_using_dac = 0;
6772 }
6773
6774 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6775 IORESOURCE_MEM), ixgbe_driver_name);
6776 if (err) {
6777 dev_err(&pdev->dev,
6778 "pci_request_selected_regions failed 0x%x\n", err);
6779 goto err_pci_reg;
6780 }
6781
6782 pci_enable_pcie_error_reporting(pdev);
6783
6784 pci_set_master(pdev);
6785 pci_save_state(pdev);
6786
6787 if (ii->mac == ixgbe_mac_82598EB)
6788 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6789 else
6790 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6791
6792 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6793 #ifdef IXGBE_FCOE
6794 indices += min_t(unsigned int, num_possible_cpus(),
6795 IXGBE_MAX_FCOE_INDICES);
6796 #endif
6797 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6798 if (!netdev) {
6799 err = -ENOMEM;
6800 goto err_alloc_etherdev;
6801 }
6802
6803 SET_NETDEV_DEV(netdev, &pdev->dev);
6804
6805 adapter = netdev_priv(netdev);
6806 pci_set_drvdata(pdev, adapter);
6807
6808 adapter->netdev = netdev;
6809 adapter->pdev = pdev;
6810 hw = &adapter->hw;
6811 hw->back = adapter;
6812 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6813
6814 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6815 pci_resource_len(pdev, 0));
6816 if (!hw->hw_addr) {
6817 err = -EIO;
6818 goto err_ioremap;
6819 }
6820
6821 for (i = 1; i <= 5; i++) {
6822 if (pci_resource_len(pdev, i) == 0)
6823 continue;
6824 }
6825
6826 netdev->netdev_ops = &ixgbe_netdev_ops;
6827 ixgbe_set_ethtool_ops(netdev);
6828 netdev->watchdog_timeo = 5 * HZ;
6829 strcpy(netdev->name, pci_name(pdev));
6830
6831 adapter->bd_number = cards_found;
6832
6833 /* Setup hw api */
6834 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6835 hw->mac.type = ii->mac;
6836
6837 /* EEPROM */
6838 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6839 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6840 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6841 if (!(eec & (1 << 8)))
6842 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6843
6844 /* PHY */
6845 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6846 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6847 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6848 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6849 hw->phy.mdio.mmds = 0;
6850 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6851 hw->phy.mdio.dev = netdev;
6852 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6853 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6854
6855 /* set up this timer and work struct before calling get_invariants
6856 * which might start the timer
6857 */
6858 init_timer(&adapter->sfp_timer);
6859 adapter->sfp_timer.function = ixgbe_sfp_timer;
6860 adapter->sfp_timer.data = (unsigned long) adapter;
6861
6862 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6863
6864 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6865 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6866
6867 /* a new SFP+ module arrival, called from GPI SDP2 context */
6868 INIT_WORK(&adapter->sfp_config_module_task,
6869 ixgbe_sfp_config_module_task);
6870
6871 ii->get_invariants(hw);
6872
6873 /* setup the private structure */
6874 err = ixgbe_sw_init(adapter);
6875 if (err)
6876 goto err_sw_init;
6877
6878 /* Make it possible the adapter to be woken up via WOL */
6879 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6880 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6881
6882 /*
6883 * If there is a fan on this device and it has failed log the
6884 * failure.
6885 */
6886 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6887 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6888 if (esdp & IXGBE_ESDP_SDP1)
6889 e_crit(probe, "Fan has stopped, replace the adapter\n");
6890 }
6891
6892 /* reset_hw fills in the perm_addr as well */
6893 hw->phy.reset_if_overtemp = true;
6894 err = hw->mac.ops.reset_hw(hw);
6895 hw->phy.reset_if_overtemp = false;
6896 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6897 hw->mac.type == ixgbe_mac_82598EB) {
6898 /*
6899 * Start a kernel thread to watch for a module to arrive.
6900 * Only do this for 82598, since 82599 will generate
6901 * interrupts on module arrival.
6902 */
6903 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6904 mod_timer(&adapter->sfp_timer,
6905 round_jiffies(jiffies + (2 * HZ)));
6906 err = 0;
6907 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6908 e_dev_err("failed to initialize because an unsupported SFP+ "
6909 "module type was detected.\n");
6910 e_dev_err("Reload the driver after installing a supported "
6911 "module.\n");
6912 goto err_sw_init;
6913 } else if (err) {
6914 e_dev_err("HW Init failed: %d\n", err);
6915 goto err_sw_init;
6916 }
6917
6918 ixgbe_probe_vf(adapter, ii);
6919
6920 netdev->features = NETIF_F_SG |
6921 NETIF_F_IP_CSUM |
6922 NETIF_F_HW_VLAN_TX |
6923 NETIF_F_HW_VLAN_RX |
6924 NETIF_F_HW_VLAN_FILTER;
6925
6926 netdev->features |= NETIF_F_IPV6_CSUM;
6927 netdev->features |= NETIF_F_TSO;
6928 netdev->features |= NETIF_F_TSO6;
6929 netdev->features |= NETIF_F_GRO;
6930
6931 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6932 netdev->features |= NETIF_F_SCTP_CSUM;
6933
6934 netdev->vlan_features |= NETIF_F_TSO;
6935 netdev->vlan_features |= NETIF_F_TSO6;
6936 netdev->vlan_features |= NETIF_F_IP_CSUM;
6937 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6938 netdev->vlan_features |= NETIF_F_SG;
6939
6940 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6941 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6942 IXGBE_FLAG_DCB_ENABLED);
6943 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6944 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6945
6946 #ifdef CONFIG_IXGBE_DCB
6947 netdev->dcbnl_ops = &dcbnl_ops;
6948 #endif
6949
6950 #ifdef IXGBE_FCOE
6951 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6952 if (hw->mac.ops.get_device_caps) {
6953 hw->mac.ops.get_device_caps(hw, &device_caps);
6954 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6955 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6956 }
6957 }
6958 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6959 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6960 netdev->vlan_features |= NETIF_F_FSO;
6961 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6962 }
6963 #endif /* IXGBE_FCOE */
6964 if (pci_using_dac) {
6965 netdev->features |= NETIF_F_HIGHDMA;
6966 netdev->vlan_features |= NETIF_F_HIGHDMA;
6967 }
6968
6969 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6970 netdev->features |= NETIF_F_LRO;
6971
6972 /* make sure the EEPROM is good */
6973 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6974 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6975 err = -EIO;
6976 goto err_eeprom;
6977 }
6978
6979 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6980 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6981
6982 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6983 e_dev_err("invalid MAC address\n");
6984 err = -EIO;
6985 goto err_eeprom;
6986 }
6987
6988 /* power down the optics */
6989 if (hw->phy.multispeed_fiber)
6990 hw->mac.ops.disable_tx_laser(hw);
6991
6992 init_timer(&adapter->watchdog_timer);
6993 adapter->watchdog_timer.function = ixgbe_watchdog;
6994 adapter->watchdog_timer.data = (unsigned long)adapter;
6995
6996 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6997 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6998
6999 err = ixgbe_init_interrupt_scheme(adapter);
7000 if (err)
7001 goto err_sw_init;
7002
7003 switch (pdev->device) {
7004 case IXGBE_DEV_ID_82599_KX4:
7005 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7006 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7007 break;
7008 default:
7009 adapter->wol = 0;
7010 break;
7011 }
7012 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7013
7014 /* pick up the PCI bus settings for reporting later */
7015 hw->mac.ops.get_bus_info(hw);
7016
7017 /* print bus type/speed/width info */
7018 e_dev_info("(PCI Express:%s:%s) %pM\n",
7019 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7020 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7021 "Unknown"),
7022 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7023 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7024 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7025 "Unknown"),
7026 netdev->dev_addr);
7027 ixgbe_read_pba_num_generic(hw, &part_num);
7028 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7029 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7030 "PBA No: %06x-%03x\n",
7031 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7032 (part_num >> 8), (part_num & 0xff));
7033 else
7034 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7035 hw->mac.type, hw->phy.type,
7036 (part_num >> 8), (part_num & 0xff));
7037
7038 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7039 e_dev_warn("PCI-Express bandwidth available for this card is "
7040 "not sufficient for optimal performance.\n");
7041 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7042 "is required.\n");
7043 }
7044
7045 /* save off EEPROM version number */
7046 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7047
7048 /* reset the hardware with the new settings */
7049 err = hw->mac.ops.start_hw(hw);
7050
7051 if (err == IXGBE_ERR_EEPROM_VERSION) {
7052 /* We are running on a pre-production device, log a warning */
7053 e_dev_warn("This device is a pre-production adapter/LOM. "
7054 "Please be aware there may be issues associated "
7055 "with your hardware. If you are experiencing "
7056 "problems please contact your Intel or hardware "
7057 "representative who provided you with this "
7058 "hardware.\n");
7059 }
7060 strcpy(netdev->name, "eth%d");
7061 err = register_netdev(netdev);
7062 if (err)
7063 goto err_register;
7064
7065 /* carrier off reporting is important to ethtool even BEFORE open */
7066 netif_carrier_off(netdev);
7067
7068 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7069 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7070 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7071
7072 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7073 INIT_WORK(&adapter->check_overtemp_task,
7074 ixgbe_check_overtemp_task);
7075 #ifdef CONFIG_IXGBE_DCA
7076 if (dca_add_requester(&pdev->dev) == 0) {
7077 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7078 ixgbe_setup_dca(adapter);
7079 }
7080 #endif
7081 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7082 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7083 for (i = 0; i < adapter->num_vfs; i++)
7084 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7085 }
7086
7087 /* add san mac addr to netdev */
7088 ixgbe_add_sanmac_netdev(netdev);
7089
7090 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7091 cards_found++;
7092 return 0;
7093
7094 err_register:
7095 ixgbe_release_hw_control(adapter);
7096 ixgbe_clear_interrupt_scheme(adapter);
7097 err_sw_init:
7098 err_eeprom:
7099 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7100 ixgbe_disable_sriov(adapter);
7101 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7102 del_timer_sync(&adapter->sfp_timer);
7103 cancel_work_sync(&adapter->sfp_task);
7104 cancel_work_sync(&adapter->multispeed_fiber_task);
7105 cancel_work_sync(&adapter->sfp_config_module_task);
7106 iounmap(hw->hw_addr);
7107 err_ioremap:
7108 free_netdev(netdev);
7109 err_alloc_etherdev:
7110 pci_release_selected_regions(pdev,
7111 pci_select_bars(pdev, IORESOURCE_MEM));
7112 err_pci_reg:
7113 err_dma:
7114 pci_disable_device(pdev);
7115 return err;
7116 }
7117
7118 /**
7119 * ixgbe_remove - Device Removal Routine
7120 * @pdev: PCI device information struct
7121 *
7122 * ixgbe_remove is called by the PCI subsystem to alert the driver
7123 * that it should release a PCI device. The could be caused by a
7124 * Hot-Plug event, or because the driver is going to be removed from
7125 * memory.
7126 **/
7127 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7128 {
7129 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7130 struct net_device *netdev = adapter->netdev;
7131
7132 set_bit(__IXGBE_DOWN, &adapter->state);
7133 /* clear the module not found bit to make sure the worker won't
7134 * reschedule
7135 */
7136 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7137 del_timer_sync(&adapter->watchdog_timer);
7138
7139 del_timer_sync(&adapter->sfp_timer);
7140 cancel_work_sync(&adapter->watchdog_task);
7141 cancel_work_sync(&adapter->sfp_task);
7142 cancel_work_sync(&adapter->multispeed_fiber_task);
7143 cancel_work_sync(&adapter->sfp_config_module_task);
7144 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7145 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7146 cancel_work_sync(&adapter->fdir_reinit_task);
7147 flush_scheduled_work();
7148
7149 #ifdef CONFIG_IXGBE_DCA
7150 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7151 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7152 dca_remove_requester(&pdev->dev);
7153 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7154 }
7155
7156 #endif
7157 #ifdef IXGBE_FCOE
7158 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7159 ixgbe_cleanup_fcoe(adapter);
7160
7161 #endif /* IXGBE_FCOE */
7162
7163 /* remove the added san mac */
7164 ixgbe_del_sanmac_netdev(netdev);
7165
7166 if (netdev->reg_state == NETREG_REGISTERED)
7167 unregister_netdev(netdev);
7168
7169 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7170 ixgbe_disable_sriov(adapter);
7171
7172 ixgbe_clear_interrupt_scheme(adapter);
7173
7174 ixgbe_release_hw_control(adapter);
7175
7176 iounmap(adapter->hw.hw_addr);
7177 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7178 IORESOURCE_MEM));
7179
7180 e_dev_info("complete\n");
7181
7182 free_netdev(netdev);
7183
7184 pci_disable_pcie_error_reporting(pdev);
7185
7186 pci_disable_device(pdev);
7187 }
7188
7189 /**
7190 * ixgbe_io_error_detected - called when PCI error is detected
7191 * @pdev: Pointer to PCI device
7192 * @state: The current pci connection state
7193 *
7194 * This function is called after a PCI bus error affecting
7195 * this device has been detected.
7196 */
7197 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7198 pci_channel_state_t state)
7199 {
7200 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7201 struct net_device *netdev = adapter->netdev;
7202
7203 netif_device_detach(netdev);
7204
7205 if (state == pci_channel_io_perm_failure)
7206 return PCI_ERS_RESULT_DISCONNECT;
7207
7208 if (netif_running(netdev))
7209 ixgbe_down(adapter);
7210 pci_disable_device(pdev);
7211
7212 /* Request a slot reset. */
7213 return PCI_ERS_RESULT_NEED_RESET;
7214 }
7215
7216 /**
7217 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7218 * @pdev: Pointer to PCI device
7219 *
7220 * Restart the card from scratch, as if from a cold-boot.
7221 */
7222 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7223 {
7224 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7225 pci_ers_result_t result;
7226 int err;
7227
7228 if (pci_enable_device_mem(pdev)) {
7229 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7230 result = PCI_ERS_RESULT_DISCONNECT;
7231 } else {
7232 pci_set_master(pdev);
7233 pci_restore_state(pdev);
7234 pci_save_state(pdev);
7235
7236 pci_wake_from_d3(pdev, false);
7237
7238 ixgbe_reset(adapter);
7239 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7240 result = PCI_ERS_RESULT_RECOVERED;
7241 }
7242
7243 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7244 if (err) {
7245 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7246 "failed 0x%0x\n", err);
7247 /* non-fatal, continue */
7248 }
7249
7250 return result;
7251 }
7252
7253 /**
7254 * ixgbe_io_resume - called when traffic can start flowing again.
7255 * @pdev: Pointer to PCI device
7256 *
7257 * This callback is called when the error recovery driver tells us that
7258 * its OK to resume normal operation.
7259 */
7260 static void ixgbe_io_resume(struct pci_dev *pdev)
7261 {
7262 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7263 struct net_device *netdev = adapter->netdev;
7264
7265 if (netif_running(netdev)) {
7266 if (ixgbe_up(adapter)) {
7267 e_info(probe, "ixgbe_up failed after reset\n");
7268 return;
7269 }
7270 }
7271
7272 netif_device_attach(netdev);
7273 }
7274
7275 static struct pci_error_handlers ixgbe_err_handler = {
7276 .error_detected = ixgbe_io_error_detected,
7277 .slot_reset = ixgbe_io_slot_reset,
7278 .resume = ixgbe_io_resume,
7279 };
7280
7281 static struct pci_driver ixgbe_driver = {
7282 .name = ixgbe_driver_name,
7283 .id_table = ixgbe_pci_tbl,
7284 .probe = ixgbe_probe,
7285 .remove = __devexit_p(ixgbe_remove),
7286 #ifdef CONFIG_PM
7287 .suspend = ixgbe_suspend,
7288 .resume = ixgbe_resume,
7289 #endif
7290 .shutdown = ixgbe_shutdown,
7291 .err_handler = &ixgbe_err_handler
7292 };
7293
7294 /**
7295 * ixgbe_init_module - Driver Registration Routine
7296 *
7297 * ixgbe_init_module is the first routine called when the driver is
7298 * loaded. All it does is register with the PCI subsystem.
7299 **/
7300 static int __init ixgbe_init_module(void)
7301 {
7302 int ret;
7303 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7304 pr_info("%s\n", ixgbe_copyright);
7305
7306 #ifdef CONFIG_IXGBE_DCA
7307 dca_register_notify(&dca_notifier);
7308 #endif
7309
7310 ret = pci_register_driver(&ixgbe_driver);
7311 return ret;
7312 }
7313
7314 module_init(ixgbe_init_module);
7315
7316 /**
7317 * ixgbe_exit_module - Driver Exit Cleanup Routine
7318 *
7319 * ixgbe_exit_module is called just before the driver is removed
7320 * from memory.
7321 **/
7322 static void __exit ixgbe_exit_module(void)
7323 {
7324 #ifdef CONFIG_IXGBE_DCA
7325 dca_unregister_notify(&dca_notifier);
7326 #endif
7327 pci_unregister_driver(&ixgbe_driver);
7328 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7329 }
7330
7331 #ifdef CONFIG_IXGBE_DCA
7332 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7333 void *p)
7334 {
7335 int ret_val;
7336
7337 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7338 __ixgbe_notify_dca);
7339
7340 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7341 }
7342
7343 #endif /* CONFIG_IXGBE_DCA */
7344
7345 /**
7346 * ixgbe_get_hw_dev return device
7347 * used by hardware layer to print debugging information
7348 **/
7349 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7350 {
7351 struct ixgbe_adapter *adapter = hw->back;
7352 return adapter->netdev;
7353 }
7354
7355 module_exit(ixgbe_exit_module);
7356
7357 /* ixgbe_main.c */
Linux kernel - Deliverables
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