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ixgbe: Patch to fix driver panic while freeing up tx & rx resources
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_type.h
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #ifndef _IXGBE_TYPE_H_
29 #define _IXGBE_TYPE_H_
30
31 #include <linux/types.h>
32
33 /* Vendor ID */
34 #define IXGBE_INTEL_VENDOR_ID 0x8086
35
36 /* Device IDs */
37 #define IXGBE_DEV_ID_82598 0x10B6
38 #define IXGBE_DEV_ID_82598_BX 0x1508
39 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
40 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
41 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
42 #define IXGBE_DEV_ID_82598AT 0x10C8
43 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD
44 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
45 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
46 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
47 #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
48 #define IXGBE_DEV_ID_82599 0x10D8
49 #define IXGBE_DEV_ID_82599_KX4 0x10F7
50 #define IXGBE_DEV_ID_82599_SFP 0x10FB
51
52 /* General Registers */
53 #define IXGBE_CTRL 0x00000
54 #define IXGBE_STATUS 0x00008
55 #define IXGBE_CTRL_EXT 0x00018
56 #define IXGBE_ESDP 0x00020
57 #define IXGBE_EODSDP 0x00028
58 #define IXGBE_I2CCTL 0x00028
59 #define IXGBE_LEDCTL 0x00200
60 #define IXGBE_FRTIMER 0x00048
61 #define IXGBE_TCPTIMER 0x0004C
62 #define IXGBE_CORESPARE 0x00600
63 #define IXGBE_EXVET 0x05078
64
65 /* NVM Registers */
66 #define IXGBE_EEC 0x10010
67 #define IXGBE_EERD 0x10014
68 #define IXGBE_FLA 0x1001C
69 #define IXGBE_EEMNGCTL 0x10110
70 #define IXGBE_EEMNGDATA 0x10114
71 #define IXGBE_FLMNGCTL 0x10118
72 #define IXGBE_FLMNGDATA 0x1011C
73 #define IXGBE_FLMNGCNT 0x10120
74 #define IXGBE_FLOP 0x1013C
75 #define IXGBE_GRC 0x10200
76
77 /* General Receive Control */
78 #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
79 #define IXGBE_GRC_APME 0x00000002 /* Advanced Power Management Enable */
80
81 #define IXGBE_VPDDIAG0 0x10204
82 #define IXGBE_VPDDIAG1 0x10208
83
84 /* I2CCTL Bit Masks */
85 #define IXGBE_I2C_CLK_IN 0x00000001
86 #define IXGBE_I2C_CLK_OUT 0x00000002
87 #define IXGBE_I2C_DATA_IN 0x00000004
88 #define IXGBE_I2C_DATA_OUT 0x00000008
89
90 /* Interrupt Registers */
91 #define IXGBE_EICR 0x00800
92 #define IXGBE_EICS 0x00808
93 #define IXGBE_EIMS 0x00880
94 #define IXGBE_EIMC 0x00888
95 #define IXGBE_EIAC 0x00810
96 #define IXGBE_EIAM 0x00890
97 #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
98 #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
99 #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
100 #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
101 /*
102 * 82598 EITR is 16 bits but set the limits based on the max
103 * supported by all ixgbe hardware. 82599 EITR is only 12 bits,
104 * with the lower 3 always zero.
105 */
106 #define IXGBE_MAX_INT_RATE 488281
107 #define IXGBE_MIN_INT_RATE 956
108 #define IXGBE_MAX_EITR 0x00000FF8
109 #define IXGBE_MIN_EITR 8
110 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
111 (0x012300 + (((_i) - 24) * 4)))
112 #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
113 #define IXGBE_EITR_LLI_MOD 0x00008000
114 #define IXGBE_EITR_CNT_WDIS 0x80000000
115 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
116 #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
117 #define IXGBE_EITRSEL 0x00894
118 #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
119 #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
120 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
121 #define IXGBE_GPIE 0x00898
122
123 /* Flow Control Registers */
124 #define IXGBE_FCADBUL 0x03210
125 #define IXGBE_FCADBUH 0x03214
126 #define IXGBE_FCAMACL 0x04328
127 #define IXGBE_FCAMACH 0x0432C
128 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
129 #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
130 #define IXGBE_PFCTOP 0x03008
131 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
132 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
133 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
134 #define IXGBE_FCRTV 0x032A0
135 #define IXGBE_FCCFG 0x03D00
136 #define IXGBE_TFCS 0x0CE00
137
138 /* Receive DMA Registers */
139 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
140 (0x0D000 + ((_i - 64) * 0x40)))
141 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
142 (0x0D004 + ((_i - 64) * 0x40)))
143 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
144 (0x0D008 + ((_i - 64) * 0x40)))
145 #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
146 (0x0D010 + ((_i - 64) * 0x40)))
147 #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
148 (0x0D018 + ((_i - 64) * 0x40)))
149 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
150 (0x0D028 + ((_i - 64) * 0x40)))
151 #define IXGBE_RDDCC 0x02F20
152 #define IXGBE_RXMEMWRAP 0x03190
153 #define IXGBE_STARCTRL 0x03024
154 /*
155 * Split and Replication Receive Control Registers
156 * 00-15 : 0x02100 + n*4
157 * 16-64 : 0x01014 + n*0x40
158 * 64-127: 0x0D014 + (n-64)*0x40
159 */
160 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
161 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
162 (0x0D014 + ((_i - 64) * 0x40))))
163 /*
164 * Rx DCA Control Register:
165 * 00-15 : 0x02200 + n*4
166 * 16-64 : 0x0100C + n*0x40
167 * 64-127: 0x0D00C + (n-64)*0x40
168 */
169 #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
170 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
171 (0x0D00C + ((_i - 64) * 0x40))))
172 #define IXGBE_RDRXCTL 0x02F00
173 #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
174 /* 8 of these 0x03C00 - 0x03C1C */
175 #define IXGBE_RXCTRL 0x03000
176 #define IXGBE_DROPEN 0x03D04
177 #define IXGBE_RXPBSIZE_SHIFT 10
178
179 /* Receive Registers */
180 #define IXGBE_RXCSUM 0x05000
181 #define IXGBE_RFCTL 0x05008
182 #define IXGBE_DRECCCTL 0x02F08
183 #define IXGBE_DRECCCTL_DISABLE 0
184 /* Multicast Table Array - 128 entries */
185 #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
186 #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
187 (0x0A200 + ((_i) * 8)))
188 #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
189 (0x0A204 + ((_i) * 8)))
190 #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
191 #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
192 /* Packet split receive type */
193 #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
194 (0x0EA00 + ((_i) * 4)))
195 /* array of 4096 1-bit vlan filters */
196 #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
197 /*array of 4096 4-bit vlan vmdq indices */
198 #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
199 #define IXGBE_FCTRL 0x05080
200 #define IXGBE_VLNCTRL 0x05088
201 #define IXGBE_MCSTCTRL 0x05090
202 #define IXGBE_MRQC 0x05818
203 #define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
204 #define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
205 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
206 #define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
207 #define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
208 #define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
209 #define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
210 #define IXGBE_RQTC 0x0EC70
211 #define IXGBE_MTQC 0x08120
212 #define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
213 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
214 #define IXGBE_VT_CTL 0x051B0
215 #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
216 #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
217 #define IXGBE_QDE 0x2F04
218 #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
219 #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
220 #define IXGBE_VMRCTL(_i) (0x0F600 + ((_i) * 4))
221 #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
222 #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
223 #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
224 #define IXGBE_LLITHRESH 0x0EC90
225 #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
226 #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
227 #define IXGBE_IMIRVP 0x05AC0
228 #define IXGBE_VMD_CTL 0x0581C
229 #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
230 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
231
232 /* Transmit DMA registers */
233 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
234 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
235 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
236 #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
237 #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
238 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
239 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
240 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
241 #define IXGBE_DTXCTL 0x07E00
242
243 #define IXGBE_DMATXCTL 0x04A80
244 #define IXGBE_DTXMXSZRQ 0x08100
245 #define IXGBE_DTXTCPFLGL 0x04A88
246 #define IXGBE_DTXTCPFLGH 0x04A8C
247 #define IXGBE_LBDRPEN 0x0CA00
248 #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
249
250 #define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
251 #define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
252 #define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
253 #define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
254 #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
255 /* Tx DCA Control register : 128 of these (0-127) */
256 #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
257 #define IXGBE_TIPG 0x0CB00
258 #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
259 #define IXGBE_MNGTXMAP 0x0CD10
260 #define IXGBE_TIPG_FIBER_DEFAULT 3
261 #define IXGBE_TXPBSIZE_SHIFT 10
262
263 /* Wake up registers */
264 #define IXGBE_WUC 0x05800
265 #define IXGBE_WUFC 0x05808
266 #define IXGBE_WUS 0x05810
267 #define IXGBE_IPAV 0x05838
268 #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
269 #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
270
271 #define IXGBE_WUPL 0x05900
272 #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
273 #define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
274 #define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host
275 * Filter Table */
276
277 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
278 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
279
280 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
281 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
282 #define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
283 #define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
284
285 /* Definitions for power management and wakeup registers */
286 /* Wake Up Control */
287 #define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
288 #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
289 #define IXGBE_WUC_ADVD3WUC 0x00000010 /* D3Cold wake up cap. enable*/
290
291 /* Wake Up Filter Control */
292 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
293 #define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
294 #define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
295 #define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
296 #define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
297 #define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
298 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
299 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
300 #define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
301
302 #define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
303 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
304 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
305 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
306 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
307 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
308 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
309 #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
310 #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
311 #define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all 6 wakeup filters*/
312 #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
313
314 /* Wake Up Status */
315 #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
316 #define IXGBE_WUS_MAG IXGBE_WUFC_MAG
317 #define IXGBE_WUS_EX IXGBE_WUFC_EX
318 #define IXGBE_WUS_MC IXGBE_WUFC_MC
319 #define IXGBE_WUS_BC IXGBE_WUFC_BC
320 #define IXGBE_WUS_ARP IXGBE_WUFC_ARP
321 #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
322 #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
323 #define IXGBE_WUS_MNG IXGBE_WUFC_MNG
324 #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
325 #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
326 #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
327 #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
328 #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
329 #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
330 #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
331
332 /* Wake Up Packet Length */
333 #define IXGBE_WUPL_LENGTH_MASK 0xFFFF
334
335 /* DCB registers */
336 #define IXGBE_RMCS 0x03D00
337 #define IXGBE_DPMCS 0x07F40
338 #define IXGBE_PDPMCS 0x0CD00
339 #define IXGBE_RUPPBMR 0x050A0
340 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
341 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
342 #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
343 #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
344 #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
345 #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
346
347
348 /* Security Control Registers */
349 #define IXGBE_SECTXCTRL 0x08800
350 #define IXGBE_SECTXSTAT 0x08804
351 #define IXGBE_SECTXBUFFAF 0x08808
352 #define IXGBE_SECTXMINIFG 0x08810
353 #define IXGBE_SECTXSTAT 0x08804
354 #define IXGBE_SECRXCTRL 0x08D00
355 #define IXGBE_SECRXSTAT 0x08D04
356
357 /* Security Bit Fields and Masks */
358 #define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
359 #define IXGBE_SECTXCTRL_TX_DIS 0x00000002
360 #define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
361
362 #define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
363 #define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
364
365 #define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
366 #define IXGBE_SECRXCTRL_RX_DIS 0x00000002
367
368 #define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
369 #define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
370
371 /* LinkSec (MacSec) Registers */
372 #define IXGBE_LSECTXCAP 0x08A00
373 #define IXGBE_LSECRXCAP 0x08F00
374 #define IXGBE_LSECTXCTRL 0x08A04
375 #define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
376 #define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
377 #define IXGBE_LSECTXSA 0x08A10
378 #define IXGBE_LSECTXPN0 0x08A14
379 #define IXGBE_LSECTXPN1 0x08A18
380 #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
381 #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
382 #define IXGBE_LSECRXCTRL 0x08F04
383 #define IXGBE_LSECRXSCL 0x08F08
384 #define IXGBE_LSECRXSCH 0x08F0C
385 #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
386 #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
387 #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
388 #define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */
389 #define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */
390 #define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */
391 #define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */
392 #define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */
393 #define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */
394 #define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */
395 #define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */
396 #define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */
397 #define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */
398 #define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */
399 #define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */
400 #define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */
401 #define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */
402 #define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */
403 #define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
404 #define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
405 #define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */
406 #define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */
407
408 /* LinkSec (MacSec) Bit Fields and Masks */
409 #define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
410 #define IXGBE_LSECTXCAP_SUM_SHIFT 16
411 #define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
412 #define IXGBE_LSECRXCAP_SUM_SHIFT 16
413
414 #define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
415 #define IXGBE_LSECTXCTRL_DISABLE 0x0
416 #define IXGBE_LSECTXCTRL_AUTH 0x1
417 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
418 #define IXGBE_LSECTXCTRL_AISCI 0x00000020
419 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
420 #define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
421
422 #define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
423 #define IXGBE_LSECRXCTRL_EN_SHIFT 2
424 #define IXGBE_LSECRXCTRL_DISABLE 0x0
425 #define IXGBE_LSECRXCTRL_CHECK 0x1
426 #define IXGBE_LSECRXCTRL_STRICT 0x2
427 #define IXGBE_LSECRXCTRL_DROP 0x3
428 #define IXGBE_LSECRXCTRL_PLSH 0x00000040
429 #define IXGBE_LSECRXCTRL_RP 0x00000080
430 #define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
431
432 /* IpSec Registers */
433 #define IXGBE_IPSTXIDX 0x08900
434 #define IXGBE_IPSTXSALT 0x08904
435 #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
436 #define IXGBE_IPSRXIDX 0x08E00
437 #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
438 #define IXGBE_IPSRXSPI 0x08E14
439 #define IXGBE_IPSRXIPIDX 0x08E18
440 #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
441 #define IXGBE_IPSRXSALT 0x08E2C
442 #define IXGBE_IPSRXMOD 0x08E30
443
444 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
445
446 /* DCB registers */
447 #define IXGBE_RTRPCS 0x02430
448 #define IXGBE_RTTDCS 0x04900
449 #define IXGBE_RTTPCS 0x0CD00
450 #define IXGBE_RTRUP2TC 0x03020
451 #define IXGBE_RTTUP2TC 0x0C800
452 #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
453 #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
454 #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
455 #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
456 #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
457 #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
458 #define IXGBE_RTTDQSEL 0x04904
459 #define IXGBE_RTTDT1C 0x04908
460 #define IXGBE_RTTDT1S 0x0490C
461 #define IXGBE_RTTDTECC 0x04990
462 #define IXGBE_RTTDTECC_NO_BCN 0x00000100
463 #define IXGBE_RTTBCNRC 0x04984
464
465 /* Stats registers */
466 #define IXGBE_CRCERRS 0x04000
467 #define IXGBE_ILLERRC 0x04004
468 #define IXGBE_ERRBC 0x04008
469 #define IXGBE_MSPDC 0x04010
470 #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
471 #define IXGBE_MLFC 0x04034
472 #define IXGBE_MRFC 0x04038
473 #define IXGBE_RLEC 0x04040
474 #define IXGBE_LXONTXC 0x03F60
475 #define IXGBE_LXONRXC 0x0CF60
476 #define IXGBE_LXOFFTXC 0x03F68
477 #define IXGBE_LXOFFRXC 0x0CF68
478 #define IXGBE_LXONRXCNT 0x041A4
479 #define IXGBE_LXOFFRXCNT 0x041A8
480 #define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */
481 #define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */
482 #define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */
483 #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
484 #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
485 #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
486 #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
487 #define IXGBE_PRC64 0x0405C
488 #define IXGBE_PRC127 0x04060
489 #define IXGBE_PRC255 0x04064
490 #define IXGBE_PRC511 0x04068
491 #define IXGBE_PRC1023 0x0406C
492 #define IXGBE_PRC1522 0x04070
493 #define IXGBE_GPRC 0x04074
494 #define IXGBE_BPRC 0x04078
495 #define IXGBE_MPRC 0x0407C
496 #define IXGBE_GPTC 0x04080
497 #define IXGBE_GORCL 0x04088
498 #define IXGBE_GORCH 0x0408C
499 #define IXGBE_GOTCL 0x04090
500 #define IXGBE_GOTCH 0x04094
501 #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
502 #define IXGBE_RUC 0x040A4
503 #define IXGBE_RFC 0x040A8
504 #define IXGBE_ROC 0x040AC
505 #define IXGBE_RJC 0x040B0
506 #define IXGBE_MNGPRC 0x040B4
507 #define IXGBE_MNGPDC 0x040B8
508 #define IXGBE_MNGPTC 0x0CF90
509 #define IXGBE_TORL 0x040C0
510 #define IXGBE_TORH 0x040C4
511 #define IXGBE_TPR 0x040D0
512 #define IXGBE_TPT 0x040D4
513 #define IXGBE_PTC64 0x040D8
514 #define IXGBE_PTC127 0x040DC
515 #define IXGBE_PTC255 0x040E0
516 #define IXGBE_PTC511 0x040E4
517 #define IXGBE_PTC1023 0x040E8
518 #define IXGBE_PTC1522 0x040EC
519 #define IXGBE_MPTC 0x040F0
520 #define IXGBE_BPTC 0x040F4
521 #define IXGBE_XEC 0x04120
522 #define IXGBE_SSVPC 0x08780
523
524 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
525 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
526 (0x08600 + ((_i) * 4)))
527 #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
528
529 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
530 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
531 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
532 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
533 #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
534 #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
535 #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
536
537 /* Management */
538 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
539 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
540 #define IXGBE_MANC 0x05820
541 #define IXGBE_MFVAL 0x05824
542 #define IXGBE_MANC2H 0x05860
543 #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
544 #define IXGBE_MIPAF 0x058B0
545 #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
546 #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
547 #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
548 #define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
549 #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
550 #define IXGBE_LSWFW 0x15014
551
552 /* ARC Subsystem registers */
553 #define IXGBE_HICR 0x15F00
554 #define IXGBE_FWSTS 0x15F0C
555 #define IXGBE_HSMC0R 0x15F04
556 #define IXGBE_HSMC1R 0x15F08
557 #define IXGBE_SWSR 0x15F10
558 #define IXGBE_HFDR 0x15FE8
559 #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
560
561 /* PCI-E registers */
562 #define IXGBE_GCR 0x11000
563 #define IXGBE_GTV 0x11004
564 #define IXGBE_FUNCTAG 0x11008
565 #define IXGBE_GLT 0x1100C
566 #define IXGBE_GSCL_1 0x11010
567 #define IXGBE_GSCL_2 0x11014
568 #define IXGBE_GSCL_3 0x11018
569 #define IXGBE_GSCL_4 0x1101C
570 #define IXGBE_GSCN_0 0x11020
571 #define IXGBE_GSCN_1 0x11024
572 #define IXGBE_GSCN_2 0x11028
573 #define IXGBE_GSCN_3 0x1102C
574 #define IXGBE_FACTPS 0x10150
575 #define IXGBE_PCIEANACTL 0x11040
576 #define IXGBE_SWSM 0x10140
577 #define IXGBE_FWSM 0x10148
578 #define IXGBE_GSSR 0x10160
579 #define IXGBE_MREVID 0x11064
580 #define IXGBE_DCA_ID 0x11070
581 #define IXGBE_DCA_CTRL 0x11074
582
583 /* PCIe registers 82599-specific */
584 #define IXGBE_GCR_EXT 0x11050
585 #define IXGBE_GSCL_5_82599 0x11030
586 #define IXGBE_GSCL_6_82599 0x11034
587 #define IXGBE_GSCL_7_82599 0x11038
588 #define IXGBE_GSCL_8_82599 0x1103C
589 #define IXGBE_PHYADR_82599 0x11040
590 #define IXGBE_PHYDAT_82599 0x11044
591 #define IXGBE_PHYCTL_82599 0x11048
592 #define IXGBE_PBACLR_82599 0x11068
593 #define IXGBE_CIAA_82599 0x11088
594 #define IXGBE_CIAD_82599 0x1108C
595 #define IXGBE_PCIE_DIAG_0_82599 0x11090
596 #define IXGBE_PCIE_DIAG_1_82599 0x11094
597 #define IXGBE_PCIE_DIAG_2_82599 0x11098
598 #define IXGBE_PCIE_DIAG_3_82599 0x1109C
599 #define IXGBE_PCIE_DIAG_4_82599 0x110A0
600 #define IXGBE_PCIE_DIAG_5_82599 0x110A4
601 #define IXGBE_PCIE_DIAG_6_82599 0x110A8
602 #define IXGBE_PCIE_DIAG_7_82599 0x110C0
603 #define IXGBE_INTRPT_CSR_82599 0x110B0
604 #define IXGBE_INTRPT_MASK_82599 0x110B8
605 #define IXGBE_CDQ_MBR_82599 0x110B4
606 #define IXGBE_MISC_REG_82599 0x110F0
607 #define IXGBE_ECC_CTRL_0_82599 0x11100
608 #define IXGBE_ECC_CTRL_1_82599 0x11104
609 #define IXGBE_ECC_STATUS_82599 0x110E0
610 #define IXGBE_BAR_CTRL_82599 0x110F4
611
612 /* Time Sync Registers */
613 #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
614 #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
615 #define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
616 #define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
617 #define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
618 #define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
619 #define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */
620 #define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */
621 #define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */
622 #define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
623 #define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
624 #define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
625 #define IXGBE_RXUDP 0x08C1C /* Time Sync Rx UDP Port - RW */
626
627 /* Diagnostic Registers */
628 #define IXGBE_RDSTATCTL 0x02C20
629 #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
630 #define IXGBE_RDHMPN 0x02F08
631 #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
632 #define IXGBE_RDPROBE 0x02F20
633 #define IXGBE_RDMAM 0x02F30
634 #define IXGBE_RDMAD 0x02F34
635 #define IXGBE_TDSTATCTL 0x07C20
636 #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
637 #define IXGBE_TDHMPN 0x07F08
638 #define IXGBE_TDHMPN2 0x082FC
639 #define IXGBE_TXDESCIC 0x082CC
640 #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
641 #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
642 #define IXGBE_TDPROBE 0x07F20
643 #define IXGBE_TXBUFCTRL 0x0C600
644 #define IXGBE_TXBUFDATA0 0x0C610
645 #define IXGBE_TXBUFDATA1 0x0C614
646 #define IXGBE_TXBUFDATA2 0x0C618
647 #define IXGBE_TXBUFDATA3 0x0C61C
648 #define IXGBE_RXBUFCTRL 0x03600
649 #define IXGBE_RXBUFDATA0 0x03610
650 #define IXGBE_RXBUFDATA1 0x03614
651 #define IXGBE_RXBUFDATA2 0x03618
652 #define IXGBE_RXBUFDATA3 0x0361C
653 #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
654 #define IXGBE_RFVAL 0x050A4
655 #define IXGBE_MDFTC1 0x042B8
656 #define IXGBE_MDFTC2 0x042C0
657 #define IXGBE_MDFTFIFO1 0x042C4
658 #define IXGBE_MDFTFIFO2 0x042C8
659 #define IXGBE_MDFTS 0x042CC
660 #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
661 #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
662 #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
663 #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
664 #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
665 #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
666 #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
667 #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
668 #define IXGBE_PCIEECCCTL 0x1106C
669 #define IXGBE_PCIEECCCTL0 0x11100
670 #define IXGBE_PCIEECCCTL1 0x11104
671 #define IXGBE_PBTXECC 0x0C300
672 #define IXGBE_PBRXECC 0x03300
673 #define IXGBE_GHECCR 0x110B0
674
675 /* MAC Registers */
676 #define IXGBE_PCS1GCFIG 0x04200
677 #define IXGBE_PCS1GLCTL 0x04208
678 #define IXGBE_PCS1GLSTA 0x0420C
679 #define IXGBE_PCS1GDBG0 0x04210
680 #define IXGBE_PCS1GDBG1 0x04214
681 #define IXGBE_PCS1GANA 0x04218
682 #define IXGBE_PCS1GANLP 0x0421C
683 #define IXGBE_PCS1GANNP 0x04220
684 #define IXGBE_PCS1GANLPNP 0x04224
685 #define IXGBE_HLREG0 0x04240
686 #define IXGBE_HLREG1 0x04244
687 #define IXGBE_PAP 0x04248
688 #define IXGBE_MACA 0x0424C
689 #define IXGBE_APAE 0x04250
690 #define IXGBE_ARD 0x04254
691 #define IXGBE_AIS 0x04258
692 #define IXGBE_MSCA 0x0425C
693 #define IXGBE_MSRWD 0x04260
694 #define IXGBE_MLADD 0x04264
695 #define IXGBE_MHADD 0x04268
696 #define IXGBE_MAXFRS 0x04268
697 #define IXGBE_TREG 0x0426C
698 #define IXGBE_PCSS1 0x04288
699 #define IXGBE_PCSS2 0x0428C
700 #define IXGBE_XPCSS 0x04290
701 #define IXGBE_MFLCN 0x04294
702 #define IXGBE_SERDESC 0x04298
703 #define IXGBE_MACS 0x0429C
704 #define IXGBE_AUTOC 0x042A0
705 #define IXGBE_LINKS 0x042A4
706 #define IXGBE_LINKS2 0x04324
707 #define IXGBE_AUTOC2 0x042A8
708 #define IXGBE_AUTOC3 0x042AC
709 #define IXGBE_ANLP1 0x042B0
710 #define IXGBE_ANLP2 0x042B4
711 #define IXGBE_ATLASCTL 0x04800
712 #define IXGBE_MMNGC 0x042D0
713 #define IXGBE_ANLPNP1 0x042D4
714 #define IXGBE_ANLPNP2 0x042D8
715 #define IXGBE_KRPCSFC 0x042E0
716 #define IXGBE_KRPCSS 0x042E4
717 #define IXGBE_FECS1 0x042E8
718 #define IXGBE_FECS2 0x042EC
719 #define IXGBE_SMADARCTL 0x14F10
720 #define IXGBE_MPVC 0x04318
721 #define IXGBE_SGMIIC 0x04314
722
723 /* Omer CORECTL */
724 #define IXGBE_CORECTL 0x014F00
725 /* BARCTRL */
726 #define IXGBE_BARCTRL 0x110F4
727 #define IXGBE_BARCTRL_FLSIZE 0x0700
728 #define IXGBE_BARCTRL_CSRSIZE 0x2000
729
730 /* RDRXCTL Bit Masks */
731 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
732 #define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
733 #define IXGBE_RDRXCTL_MVMEN 0x00000020
734 #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
735 #define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
736
737 /* RQTC Bit Masks and Shifts */
738 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
739 #define IXGBE_RQTC_TC0_MASK (0x7 << 0)
740 #define IXGBE_RQTC_TC1_MASK (0x7 << 4)
741 #define IXGBE_RQTC_TC2_MASK (0x7 << 8)
742 #define IXGBE_RQTC_TC3_MASK (0x7 << 12)
743 #define IXGBE_RQTC_TC4_MASK (0x7 << 16)
744 #define IXGBE_RQTC_TC5_MASK (0x7 << 20)
745 #define IXGBE_RQTC_TC6_MASK (0x7 << 24)
746 #define IXGBE_RQTC_TC7_MASK (0x7 << 28)
747
748 /* PSRTYPE.RQPL Bit masks and shift */
749 #define IXGBE_PSRTYPE_RQPL_MASK 0x7
750 #define IXGBE_PSRTYPE_RQPL_SHIFT 29
751
752 /* CTRL Bit Masks */
753 #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
754 #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
755 #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
756
757 /* FACTPS */
758 #define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
759
760 /* MHADD Bit Masks */
761 #define IXGBE_MHADD_MFS_MASK 0xFFFF0000
762 #define IXGBE_MHADD_MFS_SHIFT 16
763
764 /* Extended Device Control */
765 #define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
766 #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
767 #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
768 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
769
770 /* Direct Cache Access (DCA) definitions */
771 #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
772 #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
773
774 #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
775 #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
776
777 #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
778 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
779 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
780 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
781 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
782 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
783 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
784 #define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */
785 #define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */
786
787 #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
788 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
789 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
790 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
791 #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
792 #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
793
794 /* MSCA Bit Masks */
795 #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
796 #define IXGBE_MSCA_NP_ADDR_SHIFT 0
797 #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
798 #define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
799 #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
800 #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
801 #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
802 #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
803 #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
804 #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
805 #define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */
806 #define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/
807 #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
808 #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
809 #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */
810 #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */
811 #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
812 #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */
813
814 /* MSRWD bit masks */
815 #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
816 #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
817 #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
818 #define IXGBE_MSRWD_READ_DATA_SHIFT 16
819
820 /* Atlas registers */
821 #define IXGBE_ATLAS_PDN_LPBK 0x24
822 #define IXGBE_ATLAS_PDN_10G 0xB
823 #define IXGBE_ATLAS_PDN_1G 0xC
824 #define IXGBE_ATLAS_PDN_AN 0xD
825
826 /* Atlas bit masks */
827 #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
828 #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
829 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
830 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
831 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
832
833 /* Omer bit masks */
834 #define IXGBE_CORECTL_WRITE_CMD 0x00010000
835
836 /* Device Type definitions for new protocol MDIO commands */
837 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
838 #define IXGBE_MDIO_PCS_DEV_TYPE 0x3
839 #define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
840 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
841 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
842 #define IXGBE_TWINAX_DEV 1
843
844 #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
845
846 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
847 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
848 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
849 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
850 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
851 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
852
853 #define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
854 #define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
855 #define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
856 #define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
857 #define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
858 #define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
859 #define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
860 #define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
861 #define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
862 #define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */
863 #define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */
864 #define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */
865
866 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
867 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
868 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
869
870 /* MII clause 22/28 definitions */
871 #define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
872
873 #define IXGBE_MII_SPEED_SELECTION_REG 0x10
874 #define IXGBE_MII_RESTART 0x200
875 #define IXGBE_MII_AUTONEG_COMPLETE 0x20
876 #define IXGBE_MII_AUTONEG_REG 0x0
877
878 #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
879 #define IXGBE_MAX_PHY_ADDR 32
880
881 /* PHY IDs*/
882 #define TN1010_PHY_ID 0x00A19410
883 #define TNX_FW_REV 0xB
884 #define QT2022_PHY_ID 0x0043A400
885 #define ATH_PHY_ID 0x03429050
886
887 /* PHY Types */
888 #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
889
890 /* Special PHY Init Routine */
891 #define IXGBE_PHY_INIT_OFFSET_NL 0x002B
892 #define IXGBE_PHY_INIT_END_NL 0xFFFF
893 #define IXGBE_CONTROL_MASK_NL 0xF000
894 #define IXGBE_DATA_MASK_NL 0x0FFF
895 #define IXGBE_CONTROL_SHIFT_NL 12
896 #define IXGBE_DELAY_NL 0
897 #define IXGBE_DATA_NL 1
898 #define IXGBE_CONTROL_NL 0x000F
899 #define IXGBE_CONTROL_EOL_NL 0x0FFF
900 #define IXGBE_CONTROL_SOL_NL 0x0000
901 #define IXGBE_PHY_ENFORCE_INTEL_SFP_OFFSET 0x002C
902 #define IXGBE_PHY_ALLOW_ANY_SFP 0x1
903
904 /* General purpose Interrupt Enable */
905 #define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
906 #define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
907 #define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */
908 #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
909 #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
910 #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
911 #define IXGBE_GPIE_EIAME 0x40000000
912 #define IXGBE_GPIE_PBA_SUPPORT 0x80000000
913 #define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */
914 #define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */
915 #define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */
916 #define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */
917
918 /* Transmit Flow Control status */
919 #define IXGBE_TFCS_TXOFF 0x00000001
920 #define IXGBE_TFCS_TXOFF0 0x00000100
921 #define IXGBE_TFCS_TXOFF1 0x00000200
922 #define IXGBE_TFCS_TXOFF2 0x00000400
923 #define IXGBE_TFCS_TXOFF3 0x00000800
924 #define IXGBE_TFCS_TXOFF4 0x00001000
925 #define IXGBE_TFCS_TXOFF5 0x00002000
926 #define IXGBE_TFCS_TXOFF6 0x00004000
927 #define IXGBE_TFCS_TXOFF7 0x00008000
928
929 /* TCP Timer */
930 #define IXGBE_TCPTIMER_KS 0x00000100
931 #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
932 #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
933 #define IXGBE_TCPTIMER_LOOP 0x00000800
934 #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
935
936 /* HLREG0 Bit Masks */
937 #define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
938 #define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
939 #define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
940 #define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
941 #define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
942 #define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
943 #define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
944 #define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
945 #define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
946 #define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
947 #define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
948 #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
949 #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
950 #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
951 #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
952
953 /* VMD_CTL bitmasks */
954 #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
955 #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
956
957 /* VT_CTL bitmasks */
958 #define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
959 #define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
960 #define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
961
962 /* VMOLR bitmasks */
963 #define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
964 #define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
965 #define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
966 #define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
967 #define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
968
969 /* VFRE bitmask */
970 #define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
971
972 /* RDHMPN and TDHMPN bitmasks */
973 #define IXGBE_RDHMPN_RDICADDR 0x007FF800
974 #define IXGBE_RDHMPN_RDICRDREQ 0x00800000
975 #define IXGBE_RDHMPN_RDICADDR_SHIFT 11
976 #define IXGBE_TDHMPN_TDICADDR 0x003FF800
977 #define IXGBE_TDHMPN_TDICRDREQ 0x00800000
978 #define IXGBE_TDHMPN_TDICADDR_SHIFT 11
979
980 #define IXGBE_RDMAM_MEM_SEL_SHIFT 13
981 #define IXGBE_RDMAM_DWORD_SHIFT 9
982 #define IXGBE_RDMAM_DESC_COMP_FIFO 1
983 #define IXGBE_RDMAM_DFC_CMD_FIFO 2
984 #define IXGBE_RDMAM_TCN_STATUS_RAM 4
985 #define IXGBE_RDMAM_WB_COLL_FIFO 5
986 #define IXGBE_RDMAM_QSC_CNT_RAM 6
987 #define IXGBE_RDMAM_QSC_QUEUE_CNT 8
988 #define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
989 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
990 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
991 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
992 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
993 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
994 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
995 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
996 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
997 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
998 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
999 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
1000 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
1001 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
1002 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
1003
1004 #define IXGBE_TXDESCIC_READY 0x80000000
1005
1006 /* Receive Checksum Control */
1007 #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1008 #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1009
1010 /* FCRTL Bit Masks */
1011 #define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
1012 #define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
1013
1014 /* PAP bit masks*/
1015 #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
1016
1017 /* RMCS Bit Masks */
1018 #define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */
1019 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1020 #define IXGBE_RMCS_RAC 0x00000004
1021 #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
1022 #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
1023 #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
1024 #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
1025
1026 /* FCCFG Bit Masks */
1027 #define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */
1028 #define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */
1029
1030 /* Interrupt register bitmasks */
1031
1032 /* Extended Interrupt Cause Read */
1033 #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
1034 #define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */
1035 #define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */
1036 #define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */
1037 #define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
1038 #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
1039 #define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
1040 #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
1041 #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
1042 #define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
1043 #define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
1044 #define IXGBE_EICR_ECC 0x10000000 /* ECC Error */
1045 #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
1046 #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
1047 #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
1048 #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
1049
1050 /* Extended Interrupt Cause Set */
1051 #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1052 #define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1053 #define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */
1054 #define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
1055 #define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1056 #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
1057 #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1058 #define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1059 #define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1060 #define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1061 #define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */
1062 #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1063 #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
1064 #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1065 #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1066
1067 /* Extended Interrupt Mask Set */
1068 #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1069 #define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1070 #define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1071 #define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
1072 #define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1073 #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
1074 #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1075 #define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1076 #define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1077 #define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1078 #define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */
1079 #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1080 #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
1081 #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1082 #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1083
1084 /* Extended Interrupt Mask Clear */
1085 #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1086 #define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1087 #define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1088 #define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
1089 #define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1090 #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
1091 #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1092 #define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1093 #define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1094 #define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1095 #define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */
1096 #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1097 #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
1098 #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1099 #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1100
1101 #define IXGBE_EIMS_ENABLE_MASK ( \
1102 IXGBE_EIMS_RTX_QUEUE | \
1103 IXGBE_EIMS_LSC | \
1104 IXGBE_EIMS_TCP_TIMER | \
1105 IXGBE_EIMS_OTHER)
1106
1107 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1108 #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
1109 #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
1110 #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
1111 #define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
1112 #define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
1113 #define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
1114 #define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
1115 #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
1116 #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
1117 #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
1118 #define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */
1119 #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
1120 #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
1121 #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
1122 #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
1123 #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
1124 #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
1125 #define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */
1126 #define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */
1127 #define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */
1128 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1129 #define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */
1130 #define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */
1131
1132 #define IXGBE_MAX_FTQF_FILTERS 128
1133 #define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
1134 #define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
1135 #define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
1136 #define IXGBE_FTQF_PROTOCOL_SCTP 2
1137 #define IXGBE_FTQF_PRIORITY_MASK 0x00000007
1138 #define IXGBE_FTQF_PRIORITY_SHIFT 2
1139 #define IXGBE_FTQF_POOL_MASK 0x0000003F
1140 #define IXGBE_FTQF_POOL_SHIFT 8
1141 #define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
1142 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
1143 #define IXGBE_FTQF_POOL_MASK_EN 0x40000000
1144 #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
1145
1146 /* Interrupt clear mask */
1147 #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
1148
1149 /* Interrupt Vector Allocation Registers */
1150 #define IXGBE_IVAR_REG_NUM 25
1151 #define IXGBE_IVAR_TXRX_ENTRY 96
1152 #define IXGBE_IVAR_RX_ENTRY 64
1153 #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
1154 #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
1155 #define IXGBE_IVAR_TX_ENTRY 32
1156
1157 #define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
1158 #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
1159
1160 #define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
1161
1162 #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
1163
1164 /* ETYPE Queue Filter/Select Bit Masks */
1165 #define IXGBE_MAX_ETQF_FILTERS 8
1166 #define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */
1167 #define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
1168 #define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
1169 #define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
1170
1171 #define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
1172 #define IXGBE_ETQS_RX_QUEUE_SHIFT 16
1173 #define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */
1174 #define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */
1175
1176 /*
1177 * ETQF filter list: one static filter per filter consumer. This is
1178 * to avoid filter collisions later. Add new filters
1179 * here!!
1180 *
1181 * Current filters:
1182 * EAPOL 802.1x (0x888e): Filter 0
1183 * BCN (0x8904): Filter 1
1184 * 1588 (0x88f7): Filter 3
1185 */
1186 #define IXGBE_ETQF_FILTER_EAPOL 0
1187 #define IXGBE_ETQF_FILTER_BCN 1
1188 #define IXGBE_ETQF_FILTER_1588 3
1189 /* VLAN Control Bit Masks */
1190 #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
1191 #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
1192 #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
1193 #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
1194 #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
1195
1196 /* VLAN pool filtering masks */
1197 #define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
1198 #define IXGBE_VLVF_ENTRIES 64
1199
1200 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
1201
1202 /* STATUS Bit Masks */
1203 #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
1204 #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
1205 #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
1206
1207 #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
1208 #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
1209
1210 /* ESDP Bit Masks */
1211 #define IXGBE_ESDP_SDP0 0x00000001
1212 #define IXGBE_ESDP_SDP1 0x00000002
1213 #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1214 #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1215 #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
1216 #define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
1217 #define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
1218
1219 /* LEDCTL Bit Masks */
1220 #define IXGBE_LED_IVRT_BASE 0x00000040
1221 #define IXGBE_LED_BLINK_BASE 0x00000080
1222 #define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1223 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1224 #define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
1225 #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1226 #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1227 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1228
1229 /* LED modes */
1230 #define IXGBE_LED_LINK_UP 0x0
1231 #define IXGBE_LED_LINK_10G 0x1
1232 #define IXGBE_LED_MAC 0x2
1233 #define IXGBE_LED_FILTER 0x3
1234 #define IXGBE_LED_LINK_ACTIVE 0x4
1235 #define IXGBE_LED_LINK_1G 0x5
1236 #define IXGBE_LED_ON 0xE
1237 #define IXGBE_LED_OFF 0xF
1238
1239 /* AUTOC Bit Masks */
1240 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
1241 #define IXGBE_AUTOC_KX4_SUPP 0x80000000
1242 #define IXGBE_AUTOC_KX_SUPP 0x40000000
1243 #define IXGBE_AUTOC_PAUSE 0x30000000
1244 #define IXGBE_AUTOC_RF 0x08000000
1245 #define IXGBE_AUTOC_PD_TMR 0x06000000
1246 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1247 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1248 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
1249 #define IXGBE_AUTOC_FECA 0x00040000
1250 #define IXGBE_AUTOC_FECR 0x00020000
1251 #define IXGBE_AUTOC_KR_SUPP 0x00010000
1252 #define IXGBE_AUTOC_AN_RESTART 0x00001000
1253 #define IXGBE_AUTOC_FLU 0x00000001
1254 #define IXGBE_AUTOC_LMS_SHIFT 13
1255 #define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1256 #define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1257 #define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1258 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1259 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1260 #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1261 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1262 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1263 #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1264 #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1265 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1266 #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1267
1268 #define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
1269 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
1270 #define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
1271 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
1272 #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1273 #define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1274 #define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1275 #define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1276 #define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1277 #define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1278 #define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1279
1280 #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1281 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1282 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1283 #define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1284 #define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1285 #define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1286
1287 /* LINKS Bit Masks */
1288 #define IXGBE_LINKS_KX_AN_COMP 0x80000000
1289 #define IXGBE_LINKS_UP 0x40000000
1290 #define IXGBE_LINKS_SPEED 0x20000000
1291 #define IXGBE_LINKS_MODE 0x18000000
1292 #define IXGBE_LINKS_RX_MODE 0x06000000
1293 #define IXGBE_LINKS_TX_MODE 0x01800000
1294 #define IXGBE_LINKS_XGXS_EN 0x00400000
1295 #define IXGBE_LINKS_SGMII_EN 0x02000000
1296 #define IXGBE_LINKS_PCS_1G_EN 0x00200000
1297 #define IXGBE_LINKS_1G_AN_EN 0x00100000
1298 #define IXGBE_LINKS_KX_AN_IDLE 0x00080000
1299 #define IXGBE_LINKS_1G_SYNC 0x00040000
1300 #define IXGBE_LINKS_10G_ALIGN 0x00020000
1301 #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1302 #define IXGBE_LINKS_TL_FAULT 0x00001000
1303 #define IXGBE_LINKS_SIGNAL 0x00000F00
1304
1305 #define IXGBE_LINKS_SPEED_82599 0x30000000
1306 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1307 #define IXGBE_LINKS_SPEED_1G_82599 0x20000000
1308 #define IXGBE_LINKS_SPEED_100_82599 0x10000000
1309 #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
1310 #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
1311
1312 #define FIBER_LINK_UP_LIMIT 50
1313
1314 /* PCS1GLSTA Bit Masks */
1315 #define IXGBE_PCS1GLSTA_LINK_OK 1
1316 #define IXGBE_PCS1GLSTA_SYNK_OK 0x10
1317 #define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
1318 #define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
1319 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
1320 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1321 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
1322
1323 #define IXGBE_PCS1GANA_SYM_PAUSE 0x80
1324 #define IXGBE_PCS1GANA_ASM_PAUSE 0x100
1325
1326 /* PCS1GLCTL Bit Masks */
1327 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
1328 #define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
1329 #define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
1330 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
1331 #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
1332 #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
1333
1334 /* SW Semaphore Register bitmasks */
1335 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1336 #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1337 #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1338
1339 /* GSSR definitions */
1340 #define IXGBE_GSSR_EEP_SM 0x0001
1341 #define IXGBE_GSSR_PHY0_SM 0x0002
1342 #define IXGBE_GSSR_PHY1_SM 0x0004
1343 #define IXGBE_GSSR_MAC_CSR_SM 0x0008
1344 #define IXGBE_GSSR_FLASH_SM 0x0010
1345
1346 /* EEC Register */
1347 #define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
1348 #define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
1349 #define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
1350 #define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
1351 #define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
1352 #define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
1353 #define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
1354 #define IXGBE_EEC_FWE_SHIFT 4
1355 #define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
1356 #define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
1357 #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
1358 #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
1359 /* EEPROM Addressing bits based on type (0-small, 1-large) */
1360 #define IXGBE_EEC_ADDR_SIZE 0x00000400
1361 #define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
1362
1363 #define IXGBE_EEC_SIZE_SHIFT 11
1364 #define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
1365 #define IXGBE_EEPROM_OPCODE_BITS 8
1366
1367 /* Checksum and EEPROM pointers */
1368 #define IXGBE_EEPROM_CHECKSUM 0x3F
1369 #define IXGBE_EEPROM_SUM 0xBABA
1370 #define IXGBE_PCIE_ANALOG_PTR 0x03
1371 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
1372 #define IXGBE_ATLAS1_CONFIG_PTR 0x05
1373 #define IXGBE_PCIE_GENERAL_PTR 0x06
1374 #define IXGBE_PCIE_CONFIG0_PTR 0x07
1375 #define IXGBE_PCIE_CONFIG1_PTR 0x08
1376 #define IXGBE_CORE0_PTR 0x09
1377 #define IXGBE_CORE1_PTR 0x0A
1378 #define IXGBE_MAC0_PTR 0x0B
1379 #define IXGBE_MAC1_PTR 0x0C
1380 #define IXGBE_CSR0_CONFIG_PTR 0x0D
1381 #define IXGBE_CSR1_CONFIG_PTR 0x0E
1382 #define IXGBE_FW_PTR 0x0F
1383 #define IXGBE_PBANUM0_PTR 0x15
1384 #define IXGBE_PBANUM1_PTR 0x16
1385 #define IXGBE_PCIE_MSIX_82599_CAPS 0x72
1386 #define IXGBE_PCIE_MSIX_82598_CAPS 0x62
1387
1388 /* MSI-X capability fields masks */
1389 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
1390
1391 /* Legacy EEPROM word offsets */
1392 #define IXGBE_ISCSI_BOOT_CAPS 0x0033
1393 #define IXGBE_ISCSI_SETUP_PORT_0 0x0030
1394 #define IXGBE_ISCSI_SETUP_PORT_1 0x0034
1395
1396 /* EEPROM Commands - SPI */
1397 #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
1398 #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
1399 #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
1400 #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
1401 #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
1402 #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
1403 /* EEPROM reset Write Enable latch */
1404 #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
1405 #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
1406 #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
1407 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
1408 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
1409 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1410
1411 /* EEPROM Read Register */
1412 #define IXGBE_EEPROM_READ_REG_DATA 16 /* data offset in EEPROM read reg */
1413 #define IXGBE_EEPROM_READ_REG_DONE 2 /* Offset to READ done bit */
1414 #define IXGBE_EEPROM_READ_REG_START 1 /* First bit to start operation */
1415 #define IXGBE_EEPROM_READ_ADDR_SHIFT 2 /* Shift to the address bits */
1416
1417 #define IXGBE_ETH_LENGTH_OF_ADDRESS 6
1418
1419 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1420 #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1421 #endif
1422
1423 #ifndef IXGBE_EERD_ATTEMPTS
1424 /* Number of 5 microseconds we wait for EERD read to complete */
1425 #define IXGBE_EERD_ATTEMPTS 100000
1426 #endif
1427
1428 /* PCI Bus Info */
1429 #define IXGBE_PCI_LINK_STATUS 0xB2
1430 #define IXGBE_PCI_LINK_WIDTH 0x3F0
1431 #define IXGBE_PCI_LINK_WIDTH_1 0x10
1432 #define IXGBE_PCI_LINK_WIDTH_2 0x20
1433 #define IXGBE_PCI_LINK_WIDTH_4 0x40
1434 #define IXGBE_PCI_LINK_WIDTH_8 0x80
1435 #define IXGBE_PCI_LINK_SPEED 0xF
1436 #define IXGBE_PCI_LINK_SPEED_2500 0x1
1437 #define IXGBE_PCI_LINK_SPEED_5000 0x2
1438 #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
1439 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
1440
1441 /* Number of 100 microseconds we wait for PCI Express master disable */
1442 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
1443
1444 /* Check whether address is multicast. This is little-endian specific check.*/
1445 #define IXGBE_IS_MULTICAST(Address) \
1446 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
1447
1448 /* Check whether an address is broadcast. */
1449 #define IXGBE_IS_BROADCAST(Address) \
1450 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
1451 (((u8 *)(Address))[1] == ((u8)0xff)))
1452
1453 /* RAH */
1454 #define IXGBE_RAH_VIND_MASK 0x003C0000
1455 #define IXGBE_RAH_VIND_SHIFT 18
1456 #define IXGBE_RAH_AV 0x80000000
1457 #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
1458
1459 /* Header split receive */
1460 #define IXGBE_RFCTL_ISCSI_DIS 0x00000001
1461 #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
1462 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
1463 #define IXGBE_RFCTL_NFSW_DIS 0x00000040
1464 #define IXGBE_RFCTL_NFSR_DIS 0x00000080
1465 #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
1466 #define IXGBE_RFCTL_NFS_VER_SHIFT 8
1467 #define IXGBE_RFCTL_NFS_VER_2 0
1468 #define IXGBE_RFCTL_NFS_VER_3 1
1469 #define IXGBE_RFCTL_NFS_VER_4 2
1470 #define IXGBE_RFCTL_IPV6_DIS 0x00000400
1471 #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
1472 #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
1473 #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
1474 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1475
1476 /* Transmit Config masks */
1477 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
1478 #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
1479 /* Enable short packet padding to 64 bytes */
1480 #define IXGBE_TX_PAD_ENABLE 0x00000400
1481 #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
1482 /* This allows for 16K packets + 4k for vlan */
1483 #define IXGBE_MAX_FRAME_SZ 0x40040000
1484
1485 #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
1486 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */
1487
1488 /* Receive Config masks */
1489 #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
1490 #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
1491 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
1492 #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
1493
1494 #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
1495 #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
1496 #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
1497 #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
1498 #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
1499 #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
1500 /* Receive Priority Flow Control Enable */
1501 #define IXGBE_FCTRL_RPFCE 0x00004000
1502 #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
1503 #define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
1504 #define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
1505 #define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
1506 #define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
1507
1508 /* Multiple Receive Queue Control */
1509 #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
1510 #define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
1511 #define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */
1512 #define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
1513 #define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
1514 #define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
1515 #define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
1516 #define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
1517 #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
1518 #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
1519 #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
1520 #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
1521 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1522 #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
1523 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
1524 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1525 #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
1526 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
1527 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
1528 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
1529 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
1530 #define IXGBE_MRQC_L3L4TXSWEN 0x00008000
1531
1532 /* Queue Drop Enable */
1533 #define IXGBE_QDE_ENABLE 0x00000001
1534 #define IXGBE_QDE_IDX_MASK 0x00007F00
1535 #define IXGBE_QDE_IDX_SHIFT 8
1536
1537 #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
1538 #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
1539 #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
1540 #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
1541 #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
1542 #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
1543 #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
1544 #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
1545 #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
1546
1547 #define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
1548 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
1549 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
1550 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
1551 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
1552 /* Multiple Transmit Queue Command Register */
1553 #define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */
1554 #define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */
1555 #define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */
1556 #define IXGBE_MTQC_64VF 0x8 /* 2 TX Queues per pool w/64VF's */
1557 #define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
1558
1559 /* Receive Descriptor bit definitions */
1560 #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
1561 #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
1562 #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
1563 #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
1564 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
1565 #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
1566 #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
1567 #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
1568 #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
1569 #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
1570 #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
1571 #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
1572 #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
1573 #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
1574 #define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */
1575 #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
1576 #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
1577 #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
1578 #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
1579 #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
1580 #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
1581 #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
1582 #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
1583 #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
1584 #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
1585 #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
1586 #define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */
1587 #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
1588 #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
1589 #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
1590 #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
1591 #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
1592 #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
1593 #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
1594 #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
1595 #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
1596 #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
1597 #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
1598 #define IXGBE_RXD_PRI_SHIFT 13
1599 #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
1600 #define IXGBE_RXD_CFI_SHIFT 12
1601
1602 #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
1603 #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
1604 #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
1605 #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
1606 #define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */
1607
1608 /* PSRTYPE bit definitions */
1609 #define IXGBE_PSRTYPE_TCPHDR 0x00000010
1610 #define IXGBE_PSRTYPE_UDPHDR 0x00000020
1611 #define IXGBE_PSRTYPE_IPV4HDR 0x00000100
1612 #define IXGBE_PSRTYPE_IPV6HDR 0x00000200
1613
1614 /* SRRCTL bit definitions */
1615 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
1616 #define IXGBE_SRRCTL_RDMTS_SHIFT 22
1617 #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
1618 #define IXGBE_SRRCTL_DROP_EN 0x10000000
1619 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
1620 #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
1621 #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
1622 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
1623 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
1624 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
1625 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
1626 #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
1627
1628 #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
1629 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
1630
1631 #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
1632 #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
1633 #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
1634 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
1635 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
1636 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
1637 #define IXGBE_RXDADV_SPH 0x8000
1638
1639 /* RSS Hash results */
1640 #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
1641 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
1642 #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
1643 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
1644 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
1645 #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
1646 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
1647 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
1648 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
1649 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
1650
1651 /* RSS Packet Types as indicated in the receive descriptor. */
1652 #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
1653 #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
1654 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
1655 #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
1656 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
1657 #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
1658 #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
1659 #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
1660 #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
1661 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
1662 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
1663 #define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
1664 #define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
1665 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
1666 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
1667
1668 /* Security Processing bit Indication */
1669 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
1670 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
1671 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
1672 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
1673 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
1674
1675 /* Masks to determine if packets should be dropped due to frame errors */
1676 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
1677 IXGBE_RXD_ERR_CE | \
1678 IXGBE_RXD_ERR_LE | \
1679 IXGBE_RXD_ERR_PE | \
1680 IXGBE_RXD_ERR_OSE | \
1681 IXGBE_RXD_ERR_USE)
1682
1683 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
1684 IXGBE_RXDADV_ERR_CE | \
1685 IXGBE_RXDADV_ERR_LE | \
1686 IXGBE_RXDADV_ERR_PE | \
1687 IXGBE_RXDADV_ERR_OSE | \
1688 IXGBE_RXDADV_ERR_USE)
1689
1690 /* Multicast bit mask */
1691 #define IXGBE_MCSTCTRL_MFE 0x4
1692
1693 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
1694 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
1695 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
1696 #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
1697
1698 /* Vlan-specific macros */
1699 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
1700 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
1701 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
1702 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
1703
1704 /* Little Endian defines */
1705 #ifndef __le32
1706 #define __le32 u32
1707 #endif
1708 #ifndef __le64
1709 #define __le64 u64
1710
1711 #endif
1712
1713 /* Transmit Descriptor - Legacy */
1714 struct ixgbe_legacy_tx_desc {
1715 u64 buffer_addr; /* Address of the descriptor's data buffer */
1716 union {
1717 __le32 data;
1718 struct {
1719 __le16 length; /* Data buffer length */
1720 u8 cso; /* Checksum offset */
1721 u8 cmd; /* Descriptor control */
1722 } flags;
1723 } lower;
1724 union {
1725 __le32 data;
1726 struct {
1727 u8 status; /* Descriptor status */
1728 u8 css; /* Checksum start */
1729 __le16 vlan;
1730 } fields;
1731 } upper;
1732 };
1733
1734 /* Transmit Descriptor - Advanced */
1735 union ixgbe_adv_tx_desc {
1736 struct {
1737 __le64 buffer_addr; /* Address of descriptor's data buf */
1738 __le32 cmd_type_len;
1739 __le32 olinfo_status;
1740 } read;
1741 struct {
1742 __le64 rsvd; /* Reserved */
1743 __le32 nxtseq_seed;
1744 __le32 status;
1745 } wb;
1746 };
1747
1748 /* Receive Descriptor - Legacy */
1749 struct ixgbe_legacy_rx_desc {
1750 __le64 buffer_addr; /* Address of the descriptor's data buffer */
1751 __le16 length; /* Length of data DMAed into data buffer */
1752 __le16 csum; /* Packet checksum */
1753 u8 status; /* Descriptor status */
1754 u8 errors; /* Descriptor Errors */
1755 __le16 vlan;
1756 };
1757
1758 /* Receive Descriptor - Advanced */
1759 union ixgbe_adv_rx_desc {
1760 struct {
1761 __le64 pkt_addr; /* Packet buffer address */
1762 __le64 hdr_addr; /* Header buffer address */
1763 } read;
1764 struct {
1765 struct {
1766 union {
1767 __le32 data;
1768 struct {
1769 __le16 pkt_info; /* RSS, Pkt type */
1770 __le16 hdr_info; /* Splithdr, hdrlen */
1771 } hs_rss;
1772 } lo_dword;
1773 union {
1774 __le32 rss; /* RSS Hash */
1775 struct {
1776 __le16 ip_id; /* IP id */
1777 __le16 csum; /* Packet Checksum */
1778 } csum_ip;
1779 } hi_dword;
1780 } lower;
1781 struct {
1782 __le32 status_error; /* ext status/error */
1783 __le16 length; /* Packet length */
1784 __le16 vlan; /* VLAN tag */
1785 } upper;
1786 } wb; /* writeback */
1787 };
1788
1789 /* Context descriptors */
1790 struct ixgbe_adv_tx_context_desc {
1791 __le32 vlan_macip_lens;
1792 __le32 seqnum_seed;
1793 __le32 type_tucmd_mlhl;
1794 __le32 mss_l4len_idx;
1795 };
1796
1797 /* Adv Transmit Descriptor Config Masks */
1798 #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */
1799 #define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */
1800 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
1801 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */
1802 #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
1803 #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
1804 #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
1805 #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
1806 #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
1807 #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
1808 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
1809 #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
1810 #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
1811 #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
1812 #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
1813 #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */
1814 #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
1815 #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
1816 #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
1817 #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
1818 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
1819 IXGBE_ADVTXD_POPTS_SHIFT)
1820 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
1821 IXGBE_ADVTXD_POPTS_SHIFT)
1822 #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
1823 #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
1824 #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
1825 #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
1826 #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
1827 #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
1828 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
1829 #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
1830 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
1831 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
1832 #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
1833 #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
1834 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
1835 #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
1836 #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
1837 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
1838 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
1839 #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
1840 #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
1841
1842 /* Autonegotiation advertised speeds */
1843 typedef u32 ixgbe_autoneg_advertised;
1844 /* Link speed */
1845 typedef u32 ixgbe_link_speed;
1846 #define IXGBE_LINK_SPEED_UNKNOWN 0
1847 #define IXGBE_LINK_SPEED_100_FULL 0x0008
1848 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020
1849 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080
1850 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
1851 IXGBE_LINK_SPEED_10GB_FULL)
1852 #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
1853 IXGBE_LINK_SPEED_1GB_FULL | \
1854 IXGBE_LINK_SPEED_10GB_FULL)
1855
1856 #define IXGBE_PCIE_DEV_CTRL_2 0xC8
1857 #define PCIE_COMPL_TO_VALUE 0x05
1858
1859 /* Physical layer type */
1860 typedef u32 ixgbe_physical_layer;
1861 #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
1862 #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
1863 #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
1864 #define IXGBE_PHYSICAL_LAYER_100BASE_T 0x0004
1865 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
1866 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
1867 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
1868 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
1869 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
1870 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
1871 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
1872 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
1873
1874 enum ixgbe_eeprom_type {
1875 ixgbe_eeprom_uninitialized = 0,
1876 ixgbe_eeprom_spi,
1877 ixgbe_eeprom_none /* No NVM support */
1878 };
1879
1880 enum ixgbe_mac_type {
1881 ixgbe_mac_unknown = 0,
1882 ixgbe_mac_82598EB,
1883 ixgbe_mac_82599EB,
1884 ixgbe_num_macs
1885 };
1886
1887 enum ixgbe_phy_type {
1888 ixgbe_phy_unknown = 0,
1889 ixgbe_phy_tn,
1890 ixgbe_phy_cu_unknown,
1891 ixgbe_phy_qt,
1892 ixgbe_phy_xaui,
1893 ixgbe_phy_nl,
1894 ixgbe_phy_tw_tyco,
1895 ixgbe_phy_tw_unknown,
1896 ixgbe_phy_sfp_avago,
1897 ixgbe_phy_sfp_ftl,
1898 ixgbe_phy_sfp_unknown,
1899 ixgbe_phy_sfp_intel,
1900 ixgbe_phy_generic
1901 };
1902
1903 /*
1904 * SFP+ module type IDs:
1905 *
1906 * ID Module Type
1907 * =============
1908 * 0 SFP_DA_CU
1909 * 1 SFP_SR
1910 * 2 SFP_LR
1911 * 3 SFP_DA_CU_CORE0 - 82599-specific
1912 * 4 SFP_DA_CU_CORE1 - 82599-specific
1913 * 5 SFP_SR/LR_CORE0 - 82599-specific
1914 * 6 SFP_SR/LR_CORE1 - 82599-specific
1915 */
1916 enum ixgbe_sfp_type {
1917 ixgbe_sfp_type_da_cu = 0,
1918 ixgbe_sfp_type_sr = 1,
1919 ixgbe_sfp_type_lr = 2,
1920 ixgbe_sfp_type_da_cu_core0 = 3,
1921 ixgbe_sfp_type_da_cu_core1 = 4,
1922 ixgbe_sfp_type_srlr_core0 = 5,
1923 ixgbe_sfp_type_srlr_core1 = 6,
1924 ixgbe_sfp_type_not_present = 0xFFFE,
1925 ixgbe_sfp_type_unknown = 0xFFFF
1926 };
1927
1928 enum ixgbe_media_type {
1929 ixgbe_media_type_unknown = 0,
1930 ixgbe_media_type_fiber,
1931 ixgbe_media_type_copper,
1932 ixgbe_media_type_backplane,
1933 ixgbe_media_type_virtual
1934 };
1935
1936 /* Flow Control Settings */
1937 enum ixgbe_fc_mode {
1938 ixgbe_fc_none = 0,
1939 ixgbe_fc_rx_pause,
1940 ixgbe_fc_tx_pause,
1941 ixgbe_fc_full,
1942 #ifdef CONFIG_DCB
1943 ixgbe_fc_pfc,
1944 #endif
1945 ixgbe_fc_default
1946 };
1947
1948 /* PCI bus types */
1949 enum ixgbe_bus_type {
1950 ixgbe_bus_type_unknown = 0,
1951 ixgbe_bus_type_pci,
1952 ixgbe_bus_type_pcix,
1953 ixgbe_bus_type_pci_express,
1954 ixgbe_bus_type_reserved
1955 };
1956
1957 /* PCI bus speeds */
1958 enum ixgbe_bus_speed {
1959 ixgbe_bus_speed_unknown = 0,
1960 ixgbe_bus_speed_33,
1961 ixgbe_bus_speed_66,
1962 ixgbe_bus_speed_100,
1963 ixgbe_bus_speed_120,
1964 ixgbe_bus_speed_133,
1965 ixgbe_bus_speed_2500,
1966 ixgbe_bus_speed_5000,
1967 ixgbe_bus_speed_reserved
1968 };
1969
1970 /* PCI bus widths */
1971 enum ixgbe_bus_width {
1972 ixgbe_bus_width_unknown = 0,
1973 ixgbe_bus_width_pcie_x1,
1974 ixgbe_bus_width_pcie_x2,
1975 ixgbe_bus_width_pcie_x4 = 4,
1976 ixgbe_bus_width_pcie_x8 = 8,
1977 ixgbe_bus_width_32,
1978 ixgbe_bus_width_64,
1979 ixgbe_bus_width_reserved
1980 };
1981
1982 struct ixgbe_addr_filter_info {
1983 u32 num_mc_addrs;
1984 u32 rar_used_count;
1985 u32 mc_addr_in_rar_count;
1986 u32 mta_in_use;
1987 u32 overflow_promisc;
1988 bool user_set_promisc;
1989 };
1990
1991 /* Bus parameters */
1992 struct ixgbe_bus_info {
1993 enum ixgbe_bus_speed speed;
1994 enum ixgbe_bus_width width;
1995 enum ixgbe_bus_type type;
1996
1997 u16 func;
1998 u16 lan_id;
1999 };
2000
2001 /* Flow control parameters */
2002 struct ixgbe_fc_info {
2003 u32 high_water; /* Flow Control High-water */
2004 u32 low_water; /* Flow Control Low-water */
2005 u16 pause_time; /* Flow Control Pause timer */
2006 bool send_xon; /* Flow control send XON */
2007 bool strict_ieee; /* Strict IEEE mode */
2008 enum ixgbe_fc_mode current_mode; /* FC mode in effect */
2009 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
2010 };
2011
2012 /* Statistics counters collected by the MAC */
2013 struct ixgbe_hw_stats {
2014 u64 crcerrs;
2015 u64 illerrc;
2016 u64 errbc;
2017 u64 mspdc;
2018 u64 mpctotal;
2019 u64 mpc[8];
2020 u64 mlfc;
2021 u64 mrfc;
2022 u64 rlec;
2023 u64 lxontxc;
2024 u64 lxonrxc;
2025 u64 lxofftxc;
2026 u64 lxoffrxc;
2027 u64 pxontxc[8];
2028 u64 pxonrxc[8];
2029 u64 pxofftxc[8];
2030 u64 pxoffrxc[8];
2031 u64 prc64;
2032 u64 prc127;
2033 u64 prc255;
2034 u64 prc511;
2035 u64 prc1023;
2036 u64 prc1522;
2037 u64 gprc;
2038 u64 bprc;
2039 u64 mprc;
2040 u64 gptc;
2041 u64 gorc;
2042 u64 gotc;
2043 u64 rnbc[8];
2044 u64 ruc;
2045 u64 rfc;
2046 u64 roc;
2047 u64 rjc;
2048 u64 mngprc;
2049 u64 mngpdc;
2050 u64 mngptc;
2051 u64 tor;
2052 u64 tpr;
2053 u64 tpt;
2054 u64 ptc64;
2055 u64 ptc127;
2056 u64 ptc255;
2057 u64 ptc511;
2058 u64 ptc1023;
2059 u64 ptc1522;
2060 u64 mptc;
2061 u64 bptc;
2062 u64 xec;
2063 u64 rqsmr[16];
2064 u64 tqsmr[8];
2065 u64 qprc[16];
2066 u64 qptc[16];
2067 u64 qbrc[16];
2068 u64 qbtc[16];
2069 u64 qprdc[16];
2070 u64 pxon2offc[8];
2071 u64 fdirustat_add;
2072 u64 fdirustat_remove;
2073 u64 fdirfstat_fadd;
2074 u64 fdirfstat_fremove;
2075 u64 fdirmatch;
2076 u64 fdirmiss;
2077 };
2078
2079 /* forward declaration */
2080 struct ixgbe_hw;
2081
2082 /* iterator type for walking multicast address lists */
2083 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
2084 u32 *vmdq);
2085
2086 /* Function pointer table */
2087 struct ixgbe_eeprom_operations {
2088 s32 (*init_params)(struct ixgbe_hw *);
2089 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
2090 s32 (*write)(struct ixgbe_hw *, u16, u16);
2091 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
2092 s32 (*update_checksum)(struct ixgbe_hw *);
2093 };
2094
2095 struct ixgbe_mac_operations {
2096 s32 (*init_hw)(struct ixgbe_hw *);
2097 s32 (*reset_hw)(struct ixgbe_hw *);
2098 s32 (*start_hw)(struct ixgbe_hw *);
2099 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
2100 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
2101 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
2102 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
2103 s32 (*stop_adapter)(struct ixgbe_hw *);
2104 s32 (*get_bus_info)(struct ixgbe_hw *);
2105 void (*set_lan_id)(struct ixgbe_hw *);
2106 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
2107 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
2108 s32 (*setup_sfp)(struct ixgbe_hw *);
2109 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
2110
2111 /* Link */
2112 s32 (*setup_link)(struct ixgbe_hw *);
2113 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
2114 bool);
2115 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2116 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
2117 bool *);
2118
2119 /* LED */
2120 s32 (*led_on)(struct ixgbe_hw *, u32);
2121 s32 (*led_off)(struct ixgbe_hw *, u32);
2122 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
2123 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
2124
2125 /* RAR, Multicast, VLAN */
2126 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
2127 s32 (*clear_rar)(struct ixgbe_hw *, u32);
2128 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
2129 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
2130 s32 (*init_rx_addrs)(struct ixgbe_hw *);
2131 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
2132 ixgbe_mc_addr_itr);
2133 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
2134 ixgbe_mc_addr_itr);
2135 s32 (*enable_mc)(struct ixgbe_hw *);
2136 s32 (*disable_mc)(struct ixgbe_hw *);
2137 s32 (*clear_vfta)(struct ixgbe_hw *);
2138 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
2139 s32 (*init_uta_tables)(struct ixgbe_hw *);
2140
2141 /* Flow Control */
2142 s32 (*setup_fc)(struct ixgbe_hw *, s32);
2143 };
2144
2145 struct ixgbe_phy_operations {
2146 s32 (*identify)(struct ixgbe_hw *);
2147 s32 (*identify_sfp)(struct ixgbe_hw *);
2148 s32 (*reset)(struct ixgbe_hw *);
2149 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
2150 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
2151 s32 (*setup_link)(struct ixgbe_hw *);
2152 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
2153 bool);
2154 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
2155 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
2156 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
2157 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
2158 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
2159 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
2160 };
2161
2162 struct ixgbe_eeprom_info {
2163 struct ixgbe_eeprom_operations ops;
2164 enum ixgbe_eeprom_type type;
2165 u32 semaphore_delay;
2166 u16 word_size;
2167 u16 address_bits;
2168 };
2169
2170 struct ixgbe_mac_info {
2171 struct ixgbe_mac_operations ops;
2172 enum ixgbe_mac_type type;
2173 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2174 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2175 s32 mc_filter_type;
2176 u32 mcft_size;
2177 u32 vft_size;
2178 u32 num_rar_entries;
2179 u32 max_tx_queues;
2180 u32 max_rx_queues;
2181 u32 max_msix_vectors;
2182 u32 orig_autoc;
2183 u32 orig_autoc2;
2184 bool orig_link_settings_stored;
2185 bool autoneg;
2186 bool autoneg_succeeded;
2187 };
2188
2189 struct ixgbe_phy_info {
2190 struct ixgbe_phy_operations ops;
2191 enum ixgbe_phy_type type;
2192 u32 addr;
2193 u32 id;
2194 enum ixgbe_sfp_type sfp_type;
2195 u32 revision;
2196 enum ixgbe_media_type media_type;
2197 bool reset_disable;
2198 ixgbe_autoneg_advertised autoneg_advertised;
2199 bool autoneg_wait_to_complete;
2200 bool multispeed_fiber;
2201 };
2202
2203 struct ixgbe_hw {
2204 u8 __iomem *hw_addr;
2205 void *back;
2206 struct ixgbe_mac_info mac;
2207 struct ixgbe_addr_filter_info addr_ctrl;
2208 struct ixgbe_fc_info fc;
2209 struct ixgbe_phy_info phy;
2210 struct ixgbe_eeprom_info eeprom;
2211 struct ixgbe_bus_info bus;
2212 u16 device_id;
2213 u16 vendor_id;
2214 u16 subsystem_device_id;
2215 u16 subsystem_vendor_id;
2216 u8 revision_id;
2217 bool adapter_stopped;
2218 };
2219
2220 struct ixgbe_info {
2221 enum ixgbe_mac_type mac;
2222 s32 (*get_invariants)(struct ixgbe_hw *);
2223 struct ixgbe_mac_operations *mac_ops;
2224 struct ixgbe_eeprom_operations *eeprom_ops;
2225 struct ixgbe_phy_operations *phy_ops;
2226 };
2227
2228
2229 /* Error Codes */
2230 #define IXGBE_ERR_EEPROM -1
2231 #define IXGBE_ERR_EEPROM_CHECKSUM -2
2232 #define IXGBE_ERR_PHY -3
2233 #define IXGBE_ERR_CONFIG -4
2234 #define IXGBE_ERR_PARAM -5
2235 #define IXGBE_ERR_MAC_TYPE -6
2236 #define IXGBE_ERR_UNKNOWN_PHY -7
2237 #define IXGBE_ERR_LINK_SETUP -8
2238 #define IXGBE_ERR_ADAPTER_STOPPED -9
2239 #define IXGBE_ERR_INVALID_MAC_ADDR -10
2240 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
2241 #define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
2242 #define IXGBE_ERR_INVALID_LINK_SETTINGS -13
2243 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
2244 #define IXGBE_ERR_RESET_FAILED -15
2245 #define IXGBE_ERR_SWFW_SYNC -16
2246 #define IXGBE_ERR_PHY_ADDR_INVALID -17
2247 #define IXGBE_ERR_I2C -18
2248 #define IXGBE_ERR_SFP_NOT_SUPPORTED -19
2249 #define IXGBE_ERR_SFP_NOT_PRESENT -20
2250 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
2251 #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
2252
2253 #endif /* _IXGBE_TYPE_H_ */
Linux kernel - Deliverables
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